2 * wm8903.c -- WM8903 ALSA SoC Audio driver
4 * Copyright 2008-12 Wolfson Microelectronics
5 * Copyright 2011-2012 NVIDIA, Inc.
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * - TDM mode configuration.
15 * - Digital microphone support.
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/init.h>
21 #include <linux/completion.h>
22 #include <linux/delay.h>
23 #include <linux/gpio.h>
25 #include <linux/i2c.h>
26 #include <linux/regmap.h>
27 #include <linux/slab.h>
28 #include <linux/irq.h>
29 #include <linux/mutex.h>
30 #include <sound/core.h>
31 #include <sound/jack.h>
32 #include <sound/pcm.h>
33 #include <sound/pcm_params.h>
34 #include <sound/tlv.h>
35 #include <sound/soc.h>
36 #include <sound/initval.h>
37 #include <sound/wm8903.h>
38 #include <trace/events/asoc.h>
42 /* Register defaults at reset */
43 static const struct reg_default wm8903_reg_defaults
[] = {
44 { 4, 0x0018 }, /* R4 - Bias Control 0 */
45 { 5, 0x0000 }, /* R5 - VMID Control 0 */
46 { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */
47 { 8, 0x0001 }, /* R8 - Analogue DAC 0 */
48 { 10, 0x0001 }, /* R10 - Analogue ADC 0 */
49 { 12, 0x0000 }, /* R12 - Power Management 0 */
50 { 13, 0x0000 }, /* R13 - Power Management 1 */
51 { 14, 0x0000 }, /* R14 - Power Management 2 */
52 { 15, 0x0000 }, /* R15 - Power Management 3 */
53 { 16, 0x0000 }, /* R16 - Power Management 4 */
54 { 17, 0x0000 }, /* R17 - Power Management 5 */
55 { 18, 0x0000 }, /* R18 - Power Management 6 */
56 { 20, 0x0400 }, /* R20 - Clock Rates 0 */
57 { 21, 0x0D07 }, /* R21 - Clock Rates 1 */
58 { 22, 0x0000 }, /* R22 - Clock Rates 2 */
59 { 24, 0x0050 }, /* R24 - Audio Interface 0 */
60 { 25, 0x0242 }, /* R25 - Audio Interface 1 */
61 { 26, 0x0008 }, /* R26 - Audio Interface 2 */
62 { 27, 0x0022 }, /* R27 - Audio Interface 3 */
63 { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */
64 { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */
65 { 32, 0x0000 }, /* R32 - DAC Digital 0 */
66 { 33, 0x0000 }, /* R33 - DAC Digital 1 */
67 { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */
68 { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */
69 { 38, 0x0000 }, /* R38 - ADC Digital 0 */
70 { 39, 0x0073 }, /* R39 - Digital Microphone 0 */
71 { 40, 0x09BF }, /* R40 - DRC 0 */
72 { 41, 0x3241 }, /* R41 - DRC 1 */
73 { 42, 0x0020 }, /* R42 - DRC 2 */
74 { 43, 0x0000 }, /* R43 - DRC 3 */
75 { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */
76 { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */
77 { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */
78 { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */
79 { 50, 0x0008 }, /* R50 - Analogue Left Mix 0 */
80 { 51, 0x0004 }, /* R51 - Analogue Right Mix 0 */
81 { 52, 0x0000 }, /* R52 - Analogue Spk Mix Left 0 */
82 { 53, 0x0000 }, /* R53 - Analogue Spk Mix Left 1 */
83 { 54, 0x0000 }, /* R54 - Analogue Spk Mix Right 0 */
84 { 55, 0x0000 }, /* R55 - Analogue Spk Mix Right 1 */
85 { 57, 0x002D }, /* R57 - Analogue OUT1 Left */
86 { 58, 0x002D }, /* R58 - Analogue OUT1 Right */
87 { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */
88 { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */
89 { 62, 0x0139 }, /* R62 - Analogue OUT3 Left */
90 { 63, 0x0139 }, /* R63 - Analogue OUT3 Right */
91 { 64, 0x0000 }, /* R65 - Analogue SPK Output Control 0 */
92 { 67, 0x0010 }, /* R67 - DC Servo 0 */
93 { 69, 0x00A4 }, /* R69 - DC Servo 2 */
94 { 90, 0x0000 }, /* R90 - Analogue HP 0 */
95 { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */
96 { 98, 0x0000 }, /* R98 - Charge Pump 0 */
97 { 104, 0x0000 }, /* R104 - Class W 0 */
98 { 108, 0x0000 }, /* R108 - Write Sequencer 0 */
99 { 109, 0x0000 }, /* R109 - Write Sequencer 1 */
100 { 110, 0x0000 }, /* R110 - Write Sequencer 2 */
101 { 111, 0x0000 }, /* R111 - Write Sequencer 3 */
102 { 112, 0x0000 }, /* R112 - Write Sequencer 4 */
103 { 114, 0x0000 }, /* R114 - Control Interface */
104 { 116, 0x00A8 }, /* R116 - GPIO Control 1 */
105 { 117, 0x00A8 }, /* R117 - GPIO Control 2 */
106 { 118, 0x00A8 }, /* R118 - GPIO Control 3 */
107 { 119, 0x0220 }, /* R119 - GPIO Control 4 */
108 { 120, 0x01A0 }, /* R120 - GPIO Control 5 */
109 { 122, 0xFFFF }, /* R122 - Interrupt Status 1 Mask */
110 { 123, 0x0000 }, /* R123 - Interrupt Polarity 1 */
111 { 126, 0x0000 }, /* R126 - Interrupt Control */
112 { 129, 0x0000 }, /* R129 - Control Interface Test 1 */
113 { 149, 0x6810 }, /* R149 - Charge Pump Test 1 */
114 { 164, 0x0028 }, /* R164 - Clock Rate Test 4 */
115 { 172, 0x0000 }, /* R172 - Analogue Output Bias 0 */
119 struct wm8903_platform_data
*pdata
;
121 struct snd_soc_codec
*codec
;
122 struct regmap
*regmap
;
134 /* Reference count */
137 struct snd_soc_jack
*mic_jack
;
143 #ifdef CONFIG_GPIOLIB
144 struct gpio_chip gpio_chip
;
148 static bool wm8903_readable_register(struct device
*dev
, unsigned int reg
)
151 case WM8903_SW_RESET_AND_ID
:
152 case WM8903_REVISION_NUMBER
:
153 case WM8903_BIAS_CONTROL_0
:
154 case WM8903_VMID_CONTROL_0
:
155 case WM8903_MIC_BIAS_CONTROL_0
:
156 case WM8903_ANALOGUE_DAC_0
:
157 case WM8903_ANALOGUE_ADC_0
:
158 case WM8903_POWER_MANAGEMENT_0
:
159 case WM8903_POWER_MANAGEMENT_1
:
160 case WM8903_POWER_MANAGEMENT_2
:
161 case WM8903_POWER_MANAGEMENT_3
:
162 case WM8903_POWER_MANAGEMENT_4
:
163 case WM8903_POWER_MANAGEMENT_5
:
164 case WM8903_POWER_MANAGEMENT_6
:
165 case WM8903_CLOCK_RATES_0
:
166 case WM8903_CLOCK_RATES_1
:
167 case WM8903_CLOCK_RATES_2
:
168 case WM8903_AUDIO_INTERFACE_0
:
169 case WM8903_AUDIO_INTERFACE_1
:
170 case WM8903_AUDIO_INTERFACE_2
:
171 case WM8903_AUDIO_INTERFACE_3
:
172 case WM8903_DAC_DIGITAL_VOLUME_LEFT
:
173 case WM8903_DAC_DIGITAL_VOLUME_RIGHT
:
174 case WM8903_DAC_DIGITAL_0
:
175 case WM8903_DAC_DIGITAL_1
:
176 case WM8903_ADC_DIGITAL_VOLUME_LEFT
:
177 case WM8903_ADC_DIGITAL_VOLUME_RIGHT
:
178 case WM8903_ADC_DIGITAL_0
:
179 case WM8903_DIGITAL_MICROPHONE_0
:
184 case WM8903_ANALOGUE_LEFT_INPUT_0
:
185 case WM8903_ANALOGUE_RIGHT_INPUT_0
:
186 case WM8903_ANALOGUE_LEFT_INPUT_1
:
187 case WM8903_ANALOGUE_RIGHT_INPUT_1
:
188 case WM8903_ANALOGUE_LEFT_MIX_0
:
189 case WM8903_ANALOGUE_RIGHT_MIX_0
:
190 case WM8903_ANALOGUE_SPK_MIX_LEFT_0
:
191 case WM8903_ANALOGUE_SPK_MIX_LEFT_1
:
192 case WM8903_ANALOGUE_SPK_MIX_RIGHT_0
:
193 case WM8903_ANALOGUE_SPK_MIX_RIGHT_1
:
194 case WM8903_ANALOGUE_OUT1_LEFT
:
195 case WM8903_ANALOGUE_OUT1_RIGHT
:
196 case WM8903_ANALOGUE_OUT2_LEFT
:
197 case WM8903_ANALOGUE_OUT2_RIGHT
:
198 case WM8903_ANALOGUE_OUT3_LEFT
:
199 case WM8903_ANALOGUE_OUT3_RIGHT
:
200 case WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0
:
201 case WM8903_DC_SERVO_0
:
202 case WM8903_DC_SERVO_2
:
203 case WM8903_DC_SERVO_READBACK_1
:
204 case WM8903_DC_SERVO_READBACK_2
:
205 case WM8903_DC_SERVO_READBACK_3
:
206 case WM8903_DC_SERVO_READBACK_4
:
207 case WM8903_ANALOGUE_HP_0
:
208 case WM8903_ANALOGUE_LINEOUT_0
:
209 case WM8903_CHARGE_PUMP_0
:
210 case WM8903_CLASS_W_0
:
211 case WM8903_WRITE_SEQUENCER_0
:
212 case WM8903_WRITE_SEQUENCER_1
:
213 case WM8903_WRITE_SEQUENCER_2
:
214 case WM8903_WRITE_SEQUENCER_3
:
215 case WM8903_WRITE_SEQUENCER_4
:
216 case WM8903_CONTROL_INTERFACE
:
217 case WM8903_GPIO_CONTROL_1
:
218 case WM8903_GPIO_CONTROL_2
:
219 case WM8903_GPIO_CONTROL_3
:
220 case WM8903_GPIO_CONTROL_4
:
221 case WM8903_GPIO_CONTROL_5
:
222 case WM8903_INTERRUPT_STATUS_1
:
223 case WM8903_INTERRUPT_STATUS_1_MASK
:
224 case WM8903_INTERRUPT_POLARITY_1
:
225 case WM8903_INTERRUPT_CONTROL
:
226 case WM8903_CLOCK_RATE_TEST_4
:
227 case WM8903_ANALOGUE_OUTPUT_BIAS_0
:
234 static bool wm8903_volatile_register(struct device
*dev
, unsigned int reg
)
237 case WM8903_SW_RESET_AND_ID
:
238 case WM8903_REVISION_NUMBER
:
239 case WM8903_INTERRUPT_STATUS_1
:
240 case WM8903_WRITE_SEQUENCER_4
:
241 case WM8903_DC_SERVO_READBACK_1
:
242 case WM8903_DC_SERVO_READBACK_2
:
243 case WM8903_DC_SERVO_READBACK_3
:
244 case WM8903_DC_SERVO_READBACK_4
:
252 static int wm8903_cp_event(struct snd_soc_dapm_widget
*w
,
253 struct snd_kcontrol
*kcontrol
, int event
)
255 WARN_ON(event
!= SND_SOC_DAPM_POST_PMU
);
261 static int wm8903_dcs_event(struct snd_soc_dapm_widget
*w
,
262 struct snd_kcontrol
*kcontrol
, int event
)
264 struct snd_soc_codec
*codec
= w
->codec
;
265 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
268 case SND_SOC_DAPM_POST_PMU
:
269 wm8903
->dcs_pending
|= 1 << w
->shift
;
271 case SND_SOC_DAPM_PRE_PMD
:
272 snd_soc_update_bits(codec
, WM8903_DC_SERVO_0
,
280 #define WM8903_DCS_MODE_WRITE_STOP 0
281 #define WM8903_DCS_MODE_START_STOP 2
283 static void wm8903_seq_notifier(struct snd_soc_dapm_context
*dapm
,
284 enum snd_soc_dapm_type event
, int subseq
)
286 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(dapm
);
287 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
288 int dcs_mode
= WM8903_DCS_MODE_WRITE_STOP
;
291 /* Complete any pending DC servo starts */
292 if (wm8903
->dcs_pending
) {
293 dev_dbg(codec
->dev
, "Starting DC servo for %x\n",
294 wm8903
->dcs_pending
);
296 /* If we've no cached values then we need to do startup */
297 for (i
= 0; i
< ARRAY_SIZE(wm8903
->dcs_cache
); i
++) {
298 if (!(wm8903
->dcs_pending
& (1 << i
)))
301 if (wm8903
->dcs_cache
[i
]) {
303 "Restore DC servo %d value %x\n",
304 3 - i
, wm8903
->dcs_cache
[i
]);
306 snd_soc_write(codec
, WM8903_DC_SERVO_4
+ i
,
307 wm8903
->dcs_cache
[i
] & 0xff);
310 "Calibrate DC servo %d\n", 3 - i
);
311 dcs_mode
= WM8903_DCS_MODE_START_STOP
;
315 /* Don't trust the cache for analogue */
316 if (wm8903
->class_w_users
)
317 dcs_mode
= WM8903_DCS_MODE_START_STOP
;
319 snd_soc_update_bits(codec
, WM8903_DC_SERVO_2
,
320 WM8903_DCS_MODE_MASK
, dcs_mode
);
322 snd_soc_update_bits(codec
, WM8903_DC_SERVO_0
,
323 WM8903_DCS_ENA_MASK
, wm8903
->dcs_pending
);
326 case WM8903_DCS_MODE_WRITE_STOP
:
329 case WM8903_DCS_MODE_START_STOP
:
332 /* Cache the measured offsets for digital */
333 if (wm8903
->class_w_users
)
336 for (i
= 0; i
< ARRAY_SIZE(wm8903
->dcs_cache
); i
++) {
337 if (!(wm8903
->dcs_pending
& (1 << i
)))
340 val
= snd_soc_read(codec
,
341 WM8903_DC_SERVO_READBACK_1
+ i
);
342 dev_dbg(codec
->dev
, "DC servo %d: %x\n",
344 wm8903
->dcs_cache
[i
] = val
;
349 pr_warn("DCS mode %d delay not set\n", dcs_mode
);
353 wm8903
->dcs_pending
= 0;
358 * When used with DAC outputs only the WM8903 charge pump supports
359 * operation in class W mode, providing very low power consumption
360 * when used with digital sources. Enable and disable this mode
361 * automatically depending on the mixer configuration.
363 * All the relevant controls are simple switches.
365 static int wm8903_class_w_put(struct snd_kcontrol
*kcontrol
,
366 struct snd_ctl_elem_value
*ucontrol
)
368 struct snd_soc_codec
*codec
= snd_soc_dapm_kcontrol_codec(kcontrol
);
369 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
373 reg
= snd_soc_read(codec
, WM8903_CLASS_W_0
);
375 /* Turn it off if we're about to enable bypass */
376 if (ucontrol
->value
.integer
.value
[0]) {
377 if (wm8903
->class_w_users
== 0) {
378 dev_dbg(codec
->dev
, "Disabling Class W\n");
379 snd_soc_write(codec
, WM8903_CLASS_W_0
, reg
&
380 ~(WM8903_CP_DYN_FREQ
| WM8903_CP_DYN_V
));
382 wm8903
->class_w_users
++;
385 /* Implement the change */
386 ret
= snd_soc_dapm_put_volsw(kcontrol
, ucontrol
);
388 /* If we've just disabled the last bypass path turn Class W on */
389 if (!ucontrol
->value
.integer
.value
[0]) {
390 if (wm8903
->class_w_users
== 1) {
391 dev_dbg(codec
->dev
, "Enabling Class W\n");
392 snd_soc_write(codec
, WM8903_CLASS_W_0
, reg
|
393 WM8903_CP_DYN_FREQ
| WM8903_CP_DYN_V
);
395 wm8903
->class_w_users
--;
398 dev_dbg(codec
->dev
, "Bypass use count now %d\n",
399 wm8903
->class_w_users
);
404 #define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
405 SOC_SINGLE_EXT(xname, reg, shift, max, invert, \
406 snd_soc_dapm_get_volsw, wm8903_class_w_put)
409 static int wm8903_deemph
[] = { 0, 32000, 44100, 48000 };
411 static int wm8903_set_deemph(struct snd_soc_codec
*codec
)
413 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
416 /* If we're using deemphasis select the nearest available sample
419 if (wm8903
->deemph
) {
421 for (i
= 2; i
< ARRAY_SIZE(wm8903_deemph
); i
++) {
422 if (abs(wm8903_deemph
[i
] - wm8903
->fs
) <
423 abs(wm8903_deemph
[best
] - wm8903
->fs
))
427 val
= best
<< WM8903_DEEMPH_SHIFT
;
433 dev_dbg(codec
->dev
, "Set deemphasis %d (%dHz)\n",
434 best
, wm8903_deemph
[best
]);
436 return snd_soc_update_bits(codec
, WM8903_DAC_DIGITAL_1
,
437 WM8903_DEEMPH_MASK
, val
);
440 static int wm8903_get_deemph(struct snd_kcontrol
*kcontrol
,
441 struct snd_ctl_elem_value
*ucontrol
)
443 struct snd_soc_codec
*codec
= snd_soc_kcontrol_codec(kcontrol
);
444 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
446 ucontrol
->value
.enumerated
.item
[0] = wm8903
->deemph
;
451 static int wm8903_put_deemph(struct snd_kcontrol
*kcontrol
,
452 struct snd_ctl_elem_value
*ucontrol
)
454 struct snd_soc_codec
*codec
= snd_soc_kcontrol_codec(kcontrol
);
455 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
456 int deemph
= ucontrol
->value
.enumerated
.item
[0];
462 mutex_lock(&wm8903
->lock
);
463 if (wm8903
->deemph
!= deemph
) {
464 wm8903
->deemph
= deemph
;
466 wm8903_set_deemph(codec
);
470 mutex_unlock(&wm8903
->lock
);
475 /* ALSA can only do steps of .01dB */
476 static const DECLARE_TLV_DB_SCALE(digital_tlv
, -7200, 75, 1);
478 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv
, 0, 600, 0);
480 static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv
, -3600, 300, 0);
481 static const DECLARE_TLV_DB_SCALE(out_tlv
, -5700, 100, 0);
483 static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh
, 0, 75, 0);
484 static const DECLARE_TLV_DB_SCALE(drc_tlv_amp
, -2250, 75, 0);
485 static const DECLARE_TLV_DB_SCALE(drc_tlv_min
, 0, 600, 0);
486 static const DECLARE_TLV_DB_SCALE(drc_tlv_max
, 1200, 600, 0);
487 static const DECLARE_TLV_DB_SCALE(drc_tlv_startup
, -300, 50, 0);
489 static const char *hpf_mode_text
[] = {
490 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
493 static SOC_ENUM_SINGLE_DECL(hpf_mode
,
494 WM8903_ADC_DIGITAL_0
, 5, hpf_mode_text
);
496 static const char *osr_text
[] = {
497 "Low power", "High performance"
500 static SOC_ENUM_SINGLE_DECL(adc_osr
,
501 WM8903_ANALOGUE_ADC_0
, 0, osr_text
);
503 static SOC_ENUM_SINGLE_DECL(dac_osr
,
504 WM8903_DAC_DIGITAL_1
, 0, osr_text
);
506 static const char *drc_slope_text
[] = {
507 "1", "1/2", "1/4", "1/8", "1/16", "0"
510 static SOC_ENUM_SINGLE_DECL(drc_slope_r0
,
511 WM8903_DRC_2
, 3, drc_slope_text
);
513 static SOC_ENUM_SINGLE_DECL(drc_slope_r1
,
514 WM8903_DRC_2
, 0, drc_slope_text
);
516 static const char *drc_attack_text
[] = {
518 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
519 "46.4ms", "92.8ms", "185.6ms"
522 static SOC_ENUM_SINGLE_DECL(drc_attack
,
523 WM8903_DRC_1
, 12, drc_attack_text
);
525 static const char *drc_decay_text
[] = {
526 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
530 static SOC_ENUM_SINGLE_DECL(drc_decay
,
531 WM8903_DRC_1
, 8, drc_decay_text
);
533 static const char *drc_ff_delay_text
[] = {
534 "5 samples", "9 samples"
537 static SOC_ENUM_SINGLE_DECL(drc_ff_delay
,
538 WM8903_DRC_0
, 5, drc_ff_delay_text
);
540 static const char *drc_qr_decay_text
[] = {
541 "0.725ms", "1.45ms", "5.8ms"
544 static SOC_ENUM_SINGLE_DECL(drc_qr_decay
,
545 WM8903_DRC_1
, 4, drc_qr_decay_text
);
547 static const char *drc_smoothing_text
[] = {
548 "Low", "Medium", "High"
551 static SOC_ENUM_SINGLE_DECL(drc_smoothing
,
552 WM8903_DRC_0
, 11, drc_smoothing_text
);
554 static const char *soft_mute_text
[] = {
555 "Fast (fs/2)", "Slow (fs/32)"
558 static SOC_ENUM_SINGLE_DECL(soft_mute
,
559 WM8903_DAC_DIGITAL_1
, 10, soft_mute_text
);
561 static const char *mute_mode_text
[] = {
565 static SOC_ENUM_SINGLE_DECL(mute_mode
,
566 WM8903_DAC_DIGITAL_1
, 9, mute_mode_text
);
568 static const char *companding_text
[] = {
572 static SOC_ENUM_SINGLE_DECL(dac_companding
,
573 WM8903_AUDIO_INTERFACE_0
, 0, companding_text
);
575 static SOC_ENUM_SINGLE_DECL(adc_companding
,
576 WM8903_AUDIO_INTERFACE_0
, 2, companding_text
);
578 static const char *input_mode_text
[] = {
579 "Single-Ended", "Differential Line", "Differential Mic"
582 static SOC_ENUM_SINGLE_DECL(linput_mode_enum
,
583 WM8903_ANALOGUE_LEFT_INPUT_1
, 0, input_mode_text
);
585 static SOC_ENUM_SINGLE_DECL(rinput_mode_enum
,
586 WM8903_ANALOGUE_RIGHT_INPUT_1
, 0, input_mode_text
);
588 static const char *linput_mux_text
[] = {
589 "IN1L", "IN2L", "IN3L"
592 static SOC_ENUM_SINGLE_DECL(linput_enum
,
593 WM8903_ANALOGUE_LEFT_INPUT_1
, 2, linput_mux_text
);
595 static SOC_ENUM_SINGLE_DECL(linput_inv_enum
,
596 WM8903_ANALOGUE_LEFT_INPUT_1
, 4, linput_mux_text
);
598 static const char *rinput_mux_text
[] = {
599 "IN1R", "IN2R", "IN3R"
602 static SOC_ENUM_SINGLE_DECL(rinput_enum
,
603 WM8903_ANALOGUE_RIGHT_INPUT_1
, 2, rinput_mux_text
);
605 static SOC_ENUM_SINGLE_DECL(rinput_inv_enum
,
606 WM8903_ANALOGUE_RIGHT_INPUT_1
, 4, rinput_mux_text
);
609 static const char *sidetone_text
[] = {
610 "None", "Left", "Right"
613 static SOC_ENUM_SINGLE_DECL(lsidetone_enum
,
614 WM8903_DAC_DIGITAL_0
, 2, sidetone_text
);
616 static SOC_ENUM_SINGLE_DECL(rsidetone_enum
,
617 WM8903_DAC_DIGITAL_0
, 0, sidetone_text
);
619 static const char *adcinput_text
[] = {
623 static SOC_ENUM_SINGLE_DECL(adcinput_enum
,
624 WM8903_CLOCK_RATE_TEST_4
, 9, adcinput_text
);
626 static const char *aif_text
[] = {
630 static SOC_ENUM_SINGLE_DECL(lcapture_enum
,
631 WM8903_AUDIO_INTERFACE_0
, 7, aif_text
);
633 static SOC_ENUM_SINGLE_DECL(rcapture_enum
,
634 WM8903_AUDIO_INTERFACE_0
, 6, aif_text
);
636 static SOC_ENUM_SINGLE_DECL(lplay_enum
,
637 WM8903_AUDIO_INTERFACE_0
, 5, aif_text
);
639 static SOC_ENUM_SINGLE_DECL(rplay_enum
,
640 WM8903_AUDIO_INTERFACE_0
, 4, aif_text
);
642 static const struct snd_kcontrol_new wm8903_snd_controls
[] = {
644 /* Input PGAs - No TLV since the scale depends on PGA mode */
645 SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0
,
647 SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0
,
649 SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1
,
652 SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0
,
654 SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0
,
656 SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1
,
660 SOC_ENUM("ADC OSR", adc_osr
),
661 SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0
, 4, 1, 0),
662 SOC_ENUM("HPF Mode", hpf_mode
),
663 SOC_SINGLE("DRC Switch", WM8903_DRC_0
, 15, 1, 0),
664 SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0
),
665 SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1
),
666 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3
, 5, 124, 1,
668 SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3
, 0, 30, 1, drc_tlv_amp
),
669 SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1
, 2, 3, 1, drc_tlv_min
),
670 SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1
, 0, 3, 0, drc_tlv_max
),
671 SOC_ENUM("DRC Attack Rate", drc_attack
),
672 SOC_ENUM("DRC Decay Rate", drc_decay
),
673 SOC_ENUM("DRC FF Delay", drc_ff_delay
),
674 SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0
, 1, 1, 0),
675 SOC_SINGLE("DRC QR Switch", WM8903_DRC_0
, 2, 1, 0),
676 SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0
, 6, 3, 0, drc_tlv_max
),
677 SOC_ENUM("DRC QR Decay Rate", drc_qr_decay
),
678 SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0
, 3, 1, 0),
679 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0
, 0, 1, 0),
680 SOC_ENUM("DRC Smoothing Threshold", drc_smoothing
),
681 SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0
, 6, 18, 0, drc_tlv_startup
),
683 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT
,
684 WM8903_ADC_DIGITAL_VOLUME_RIGHT
, 1, 120, 0, digital_tlv
),
685 SOC_ENUM("ADC Companding Mode", adc_companding
),
686 SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0
, 3, 1, 0),
688 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0
, 4, 8,
689 12, 0, digital_sidetone_tlv
),
692 SOC_ENUM("DAC OSR", dac_osr
),
693 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT
,
694 WM8903_DAC_DIGITAL_VOLUME_RIGHT
, 1, 120, 0, digital_tlv
),
695 SOC_ENUM("DAC Soft Mute Rate", soft_mute
),
696 SOC_ENUM("DAC Mute Mode", mute_mode
),
697 SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1
, 12, 1, 0),
698 SOC_ENUM("DAC Companding Mode", dac_companding
),
699 SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0
, 1, 1, 0),
700 SOC_SINGLE_TLV("DAC Boost Volume", WM8903_AUDIO_INTERFACE_0
, 9, 3, 0,
702 SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
703 wm8903_get_deemph
, wm8903_put_deemph
),
706 SOC_DOUBLE_R("Headphone Switch",
707 WM8903_ANALOGUE_OUT1_LEFT
, WM8903_ANALOGUE_OUT1_RIGHT
,
709 SOC_DOUBLE_R("Headphone ZC Switch",
710 WM8903_ANALOGUE_OUT1_LEFT
, WM8903_ANALOGUE_OUT1_RIGHT
,
712 SOC_DOUBLE_R_TLV("Headphone Volume",
713 WM8903_ANALOGUE_OUT1_LEFT
, WM8903_ANALOGUE_OUT1_RIGHT
,
717 SOC_DOUBLE_R("Line Out Switch",
718 WM8903_ANALOGUE_OUT2_LEFT
, WM8903_ANALOGUE_OUT2_RIGHT
,
720 SOC_DOUBLE_R("Line Out ZC Switch",
721 WM8903_ANALOGUE_OUT2_LEFT
, WM8903_ANALOGUE_OUT2_RIGHT
,
723 SOC_DOUBLE_R_TLV("Line Out Volume",
724 WM8903_ANALOGUE_OUT2_LEFT
, WM8903_ANALOGUE_OUT2_RIGHT
,
728 SOC_DOUBLE_R("Speaker Switch",
729 WM8903_ANALOGUE_OUT3_LEFT
, WM8903_ANALOGUE_OUT3_RIGHT
, 8, 1, 1),
730 SOC_DOUBLE_R("Speaker ZC Switch",
731 WM8903_ANALOGUE_OUT3_LEFT
, WM8903_ANALOGUE_OUT3_RIGHT
, 6, 1, 0),
732 SOC_DOUBLE_R_TLV("Speaker Volume",
733 WM8903_ANALOGUE_OUT3_LEFT
, WM8903_ANALOGUE_OUT3_RIGHT
,
737 static const struct snd_kcontrol_new linput_mode_mux
=
738 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum
);
740 static const struct snd_kcontrol_new rinput_mode_mux
=
741 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum
);
743 static const struct snd_kcontrol_new linput_mux
=
744 SOC_DAPM_ENUM("Left Input Mux", linput_enum
);
746 static const struct snd_kcontrol_new linput_inv_mux
=
747 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum
);
749 static const struct snd_kcontrol_new rinput_mux
=
750 SOC_DAPM_ENUM("Right Input Mux", rinput_enum
);
752 static const struct snd_kcontrol_new rinput_inv_mux
=
753 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum
);
755 static const struct snd_kcontrol_new lsidetone_mux
=
756 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum
);
758 static const struct snd_kcontrol_new rsidetone_mux
=
759 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum
);
761 static const struct snd_kcontrol_new adcinput_mux
=
762 SOC_DAPM_ENUM("ADC Input", adcinput_enum
);
764 static const struct snd_kcontrol_new lcapture_mux
=
765 SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum
);
767 static const struct snd_kcontrol_new rcapture_mux
=
768 SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum
);
770 static const struct snd_kcontrol_new lplay_mux
=
771 SOC_DAPM_ENUM("Left Playback Mux", lplay_enum
);
773 static const struct snd_kcontrol_new rplay_mux
=
774 SOC_DAPM_ENUM("Right Playback Mux", rplay_enum
);
776 static const struct snd_kcontrol_new left_output_mixer
[] = {
777 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 3, 1, 0),
778 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 2, 1, 0),
779 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 1, 1, 0),
780 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 0, 1, 0),
783 static const struct snd_kcontrol_new right_output_mixer
[] = {
784 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 3, 1, 0),
785 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 2, 1, 0),
786 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 1, 1, 0),
787 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 0, 1, 0),
790 static const struct snd_kcontrol_new left_speaker_mixer
[] = {
791 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
, 3, 1, 0),
792 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
, 2, 1, 0),
793 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
, 1, 1, 0),
794 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
,
798 static const struct snd_kcontrol_new right_speaker_mixer
[] = {
799 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
, 3, 1, 0),
800 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
, 2, 1, 0),
801 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
,
803 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
,
807 static const struct snd_soc_dapm_widget wm8903_dapm_widgets
[] = {
808 SND_SOC_DAPM_INPUT("IN1L"),
809 SND_SOC_DAPM_INPUT("IN1R"),
810 SND_SOC_DAPM_INPUT("IN2L"),
811 SND_SOC_DAPM_INPUT("IN2R"),
812 SND_SOC_DAPM_INPUT("IN3L"),
813 SND_SOC_DAPM_INPUT("IN3R"),
814 SND_SOC_DAPM_INPUT("DMICDAT"),
816 SND_SOC_DAPM_OUTPUT("HPOUTL"),
817 SND_SOC_DAPM_OUTPUT("HPOUTR"),
818 SND_SOC_DAPM_OUTPUT("LINEOUTL"),
819 SND_SOC_DAPM_OUTPUT("LINEOUTR"),
820 SND_SOC_DAPM_OUTPUT("LOP"),
821 SND_SOC_DAPM_OUTPUT("LON"),
822 SND_SOC_DAPM_OUTPUT("ROP"),
823 SND_SOC_DAPM_OUTPUT("RON"),
825 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8903_MIC_BIAS_CONTROL_0
, 0, 0, NULL
, 0),
827 SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM
, 0, 0, &linput_mux
),
828 SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM
, 0, 0,
830 SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM
, 0, 0, &linput_mode_mux
),
832 SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM
, 0, 0, &rinput_mux
),
833 SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM
, 0, 0,
835 SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM
, 0, 0, &rinput_mode_mux
),
837 SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0
, 1, 0, NULL
, 0),
838 SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0
, 0, 0, NULL
, 0),
840 SND_SOC_DAPM_MUX("Left ADC Input", SND_SOC_NOPM
, 0, 0, &adcinput_mux
),
841 SND_SOC_DAPM_MUX("Right ADC Input", SND_SOC_NOPM
, 0, 0, &adcinput_mux
),
843 SND_SOC_DAPM_ADC("ADCL", NULL
, WM8903_POWER_MANAGEMENT_6
, 1, 0),
844 SND_SOC_DAPM_ADC("ADCR", NULL
, WM8903_POWER_MANAGEMENT_6
, 0, 0),
846 SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM
, 0, 0, &lcapture_mux
),
847 SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM
, 0, 0, &rcapture_mux
),
849 SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM
, 0, 0),
850 SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM
, 0, 0),
852 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM
, 0, 0, &lsidetone_mux
),
853 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM
, 0, 0, &rsidetone_mux
),
855 SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM
, 0, 0),
856 SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM
, 0, 0),
858 SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM
, 0, 0, &lplay_mux
),
859 SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM
, 0, 0, &rplay_mux
),
861 SND_SOC_DAPM_DAC("DACL", NULL
, WM8903_POWER_MANAGEMENT_6
, 3, 0),
862 SND_SOC_DAPM_DAC("DACR", NULL
, WM8903_POWER_MANAGEMENT_6
, 2, 0),
864 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1
, 1, 0,
865 left_output_mixer
, ARRAY_SIZE(left_output_mixer
)),
866 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1
, 0, 0,
867 right_output_mixer
, ARRAY_SIZE(right_output_mixer
)),
869 SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4
, 1, 0,
870 left_speaker_mixer
, ARRAY_SIZE(left_speaker_mixer
)),
871 SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4
, 0, 0,
872 right_speaker_mixer
, ARRAY_SIZE(right_speaker_mixer
)),
874 SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2
,
876 SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2
,
879 SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3
, 1, 0,
881 SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3
, 0, 0,
884 SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0
, 7, 0, NULL
, 0),
885 SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0
, 6, 0, NULL
, 0),
886 SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 2, WM8903_ANALOGUE_HP_0
, 5, 0, NULL
, 0),
887 SND_SOC_DAPM_PGA_S("HPL_ENA", 1, WM8903_ANALOGUE_HP_0
, 4, 0, NULL
, 0),
888 SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0
, 3, 0, NULL
, 0),
889 SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0
, 2, 0, NULL
, 0),
890 SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 2, WM8903_ANALOGUE_HP_0
, 1, 0, NULL
, 0),
891 SND_SOC_DAPM_PGA_S("HPR_ENA", 1, WM8903_ANALOGUE_HP_0
, 0, 0, NULL
, 0),
893 SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0
, 7, 0,
895 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0
, 6, 0,
897 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0
, 5, 0,
899 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA", 1, WM8903_ANALOGUE_LINEOUT_0
, 4, 0,
901 SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0
, 3, 0,
903 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0
, 2, 0,
905 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0
, 1, 0,
907 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA", 1, WM8903_ANALOGUE_LINEOUT_0
, 0, 0,
910 SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0
, 4, 0, NULL
, 0),
911 SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM
, 3, 0, wm8903_dcs_event
,
912 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
913 SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM
, 2, 0, wm8903_dcs_event
,
914 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
915 SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM
, 1, 0, wm8903_dcs_event
,
916 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
917 SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM
, 0, 0, wm8903_dcs_event
,
918 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
920 SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5
, 1, 0,
922 SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5
, 0, 0,
925 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0
, 0, 0,
926 wm8903_cp_event
, SND_SOC_DAPM_POST_PMU
),
927 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2
, 1, 0, NULL
, 0),
928 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2
, 2, 0, NULL
, 0),
931 static const struct snd_soc_dapm_route wm8903_intercon
[] = {
933 { "CLK_DSP", NULL
, "CLK_SYS" },
934 { "MICBIAS", NULL
, "CLK_SYS" },
935 { "HPL_DCS", NULL
, "CLK_SYS" },
936 { "HPR_DCS", NULL
, "CLK_SYS" },
937 { "LINEOUTL_DCS", NULL
, "CLK_SYS" },
938 { "LINEOUTR_DCS", NULL
, "CLK_SYS" },
940 { "Left Input Mux", "IN1L", "IN1L" },
941 { "Left Input Mux", "IN2L", "IN2L" },
942 { "Left Input Mux", "IN3L", "IN3L" },
944 { "Left Input Inverting Mux", "IN1L", "IN1L" },
945 { "Left Input Inverting Mux", "IN2L", "IN2L" },
946 { "Left Input Inverting Mux", "IN3L", "IN3L" },
948 { "Right Input Mux", "IN1R", "IN1R" },
949 { "Right Input Mux", "IN2R", "IN2R" },
950 { "Right Input Mux", "IN3R", "IN3R" },
952 { "Right Input Inverting Mux", "IN1R", "IN1R" },
953 { "Right Input Inverting Mux", "IN2R", "IN2R" },
954 { "Right Input Inverting Mux", "IN3R", "IN3R" },
956 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
957 { "Left Input Mode Mux", "Differential Line",
959 { "Left Input Mode Mux", "Differential Line",
960 "Left Input Inverting Mux" },
961 { "Left Input Mode Mux", "Differential Mic",
963 { "Left Input Mode Mux", "Differential Mic",
964 "Left Input Inverting Mux" },
966 { "Right Input Mode Mux", "Single-Ended",
967 "Right Input Inverting Mux" },
968 { "Right Input Mode Mux", "Differential Line",
970 { "Right Input Mode Mux", "Differential Line",
971 "Right Input Inverting Mux" },
972 { "Right Input Mode Mux", "Differential Mic",
974 { "Right Input Mode Mux", "Differential Mic",
975 "Right Input Inverting Mux" },
977 { "Left Input PGA", NULL
, "Left Input Mode Mux" },
978 { "Right Input PGA", NULL
, "Right Input Mode Mux" },
980 { "Left ADC Input", "ADC", "Left Input PGA" },
981 { "Left ADC Input", "DMIC", "DMICDAT" },
982 { "Right ADC Input", "ADC", "Right Input PGA" },
983 { "Right ADC Input", "DMIC", "DMICDAT" },
985 { "Left Capture Mux", "Left", "ADCL" },
986 { "Left Capture Mux", "Right", "ADCR" },
988 { "Right Capture Mux", "Left", "ADCL" },
989 { "Right Capture Mux", "Right", "ADCR" },
991 { "AIFTXL", NULL
, "Left Capture Mux" },
992 { "AIFTXR", NULL
, "Right Capture Mux" },
994 { "ADCL", NULL
, "Left ADC Input" },
995 { "ADCL", NULL
, "CLK_DSP" },
996 { "ADCR", NULL
, "Right ADC Input" },
997 { "ADCR", NULL
, "CLK_DSP" },
999 { "Left Playback Mux", "Left", "AIFRXL" },
1000 { "Left Playback Mux", "Right", "AIFRXR" },
1002 { "Right Playback Mux", "Left", "AIFRXL" },
1003 { "Right Playback Mux", "Right", "AIFRXR" },
1005 { "DACL Sidetone", "Left", "ADCL" },
1006 { "DACL Sidetone", "Right", "ADCR" },
1007 { "DACR Sidetone", "Left", "ADCL" },
1008 { "DACR Sidetone", "Right", "ADCR" },
1010 { "DACL", NULL
, "Left Playback Mux" },
1011 { "DACL", NULL
, "DACL Sidetone" },
1012 { "DACL", NULL
, "CLK_DSP" },
1014 { "DACR", NULL
, "Right Playback Mux" },
1015 { "DACR", NULL
, "DACR Sidetone" },
1016 { "DACR", NULL
, "CLK_DSP" },
1018 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1019 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1020 { "Left Output Mixer", "DACL Switch", "DACL" },
1021 { "Left Output Mixer", "DACR Switch", "DACR" },
1023 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1024 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1025 { "Right Output Mixer", "DACL Switch", "DACL" },
1026 { "Right Output Mixer", "DACR Switch", "DACR" },
1028 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1029 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1030 { "Left Speaker Mixer", "DACL Switch", "DACL" },
1031 { "Left Speaker Mixer", "DACR Switch", "DACR" },
1033 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1034 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1035 { "Right Speaker Mixer", "DACL Switch", "DACL" },
1036 { "Right Speaker Mixer", "DACR Switch", "DACR" },
1038 { "Left Line Output PGA", NULL
, "Left Output Mixer" },
1039 { "Right Line Output PGA", NULL
, "Right Output Mixer" },
1041 { "Left Headphone Output PGA", NULL
, "Left Output Mixer" },
1042 { "Right Headphone Output PGA", NULL
, "Right Output Mixer" },
1044 { "Left Speaker PGA", NULL
, "Left Speaker Mixer" },
1045 { "Right Speaker PGA", NULL
, "Right Speaker Mixer" },
1047 { "HPL_ENA", NULL
, "Left Headphone Output PGA" },
1048 { "HPR_ENA", NULL
, "Right Headphone Output PGA" },
1049 { "HPL_ENA_DLY", NULL
, "HPL_ENA" },
1050 { "HPR_ENA_DLY", NULL
, "HPR_ENA" },
1051 { "LINEOUTL_ENA", NULL
, "Left Line Output PGA" },
1052 { "LINEOUTR_ENA", NULL
, "Right Line Output PGA" },
1053 { "LINEOUTL_ENA_DLY", NULL
, "LINEOUTL_ENA" },
1054 { "LINEOUTR_ENA_DLY", NULL
, "LINEOUTR_ENA" },
1056 { "HPL_DCS", NULL
, "DCS Master" },
1057 { "HPR_DCS", NULL
, "DCS Master" },
1058 { "LINEOUTL_DCS", NULL
, "DCS Master" },
1059 { "LINEOUTR_DCS", NULL
, "DCS Master" },
1061 { "HPL_DCS", NULL
, "HPL_ENA_DLY" },
1062 { "HPR_DCS", NULL
, "HPR_ENA_DLY" },
1063 { "LINEOUTL_DCS", NULL
, "LINEOUTL_ENA_DLY" },
1064 { "LINEOUTR_DCS", NULL
, "LINEOUTR_ENA_DLY" },
1066 { "HPL_ENA_OUTP", NULL
, "HPL_DCS" },
1067 { "HPR_ENA_OUTP", NULL
, "HPR_DCS" },
1068 { "LINEOUTL_ENA_OUTP", NULL
, "LINEOUTL_DCS" },
1069 { "LINEOUTR_ENA_OUTP", NULL
, "LINEOUTR_DCS" },
1071 { "HPL_RMV_SHORT", NULL
, "HPL_ENA_OUTP" },
1072 { "HPR_RMV_SHORT", NULL
, "HPR_ENA_OUTP" },
1073 { "LINEOUTL_RMV_SHORT", NULL
, "LINEOUTL_ENA_OUTP" },
1074 { "LINEOUTR_RMV_SHORT", NULL
, "LINEOUTR_ENA_OUTP" },
1076 { "HPOUTL", NULL
, "HPL_RMV_SHORT" },
1077 { "HPOUTR", NULL
, "HPR_RMV_SHORT" },
1078 { "LINEOUTL", NULL
, "LINEOUTL_RMV_SHORT" },
1079 { "LINEOUTR", NULL
, "LINEOUTR_RMV_SHORT" },
1081 { "LOP", NULL
, "Left Speaker PGA" },
1082 { "LON", NULL
, "Left Speaker PGA" },
1084 { "ROP", NULL
, "Right Speaker PGA" },
1085 { "RON", NULL
, "Right Speaker PGA" },
1087 { "Charge Pump", NULL
, "CLK_DSP" },
1089 { "Left Headphone Output PGA", NULL
, "Charge Pump" },
1090 { "Right Headphone Output PGA", NULL
, "Charge Pump" },
1091 { "Left Line Output PGA", NULL
, "Charge Pump" },
1092 { "Right Line Output PGA", NULL
, "Charge Pump" },
1095 static int wm8903_set_bias_level(struct snd_soc_codec
*codec
,
1096 enum snd_soc_bias_level level
)
1099 case SND_SOC_BIAS_ON
:
1102 case SND_SOC_BIAS_PREPARE
:
1103 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1104 WM8903_VMID_RES_MASK
,
1105 WM8903_VMID_RES_50K
);
1108 case SND_SOC_BIAS_STANDBY
:
1109 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
1110 snd_soc_update_bits(codec
, WM8903_BIAS_CONTROL_0
,
1111 WM8903_POBCTRL
| WM8903_ISEL_MASK
|
1112 WM8903_STARTUP_BIAS_ENA
|
1115 (2 << WM8903_ISEL_SHIFT
) |
1116 WM8903_STARTUP_BIAS_ENA
);
1118 snd_soc_update_bits(codec
,
1119 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0
,
1120 WM8903_SPK_DISCHARGE
,
1121 WM8903_SPK_DISCHARGE
);
1125 snd_soc_update_bits(codec
, WM8903_POWER_MANAGEMENT_5
,
1126 WM8903_SPKL_ENA
| WM8903_SPKR_ENA
,
1127 WM8903_SPKL_ENA
| WM8903_SPKR_ENA
);
1129 snd_soc_update_bits(codec
,
1130 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0
,
1131 WM8903_SPK_DISCHARGE
, 0);
1133 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1134 WM8903_VMID_TIE_ENA
|
1136 WM8903_VMID_IO_ENA
|
1137 WM8903_VMID_SOFT_MASK
|
1138 WM8903_VMID_RES_MASK
|
1139 WM8903_VMID_BUF_ENA
,
1140 WM8903_VMID_TIE_ENA
|
1142 WM8903_VMID_IO_ENA
|
1143 (2 << WM8903_VMID_SOFT_SHIFT
) |
1144 WM8903_VMID_RES_250K
|
1145 WM8903_VMID_BUF_ENA
);
1149 snd_soc_update_bits(codec
, WM8903_POWER_MANAGEMENT_5
,
1150 WM8903_SPKL_ENA
| WM8903_SPKR_ENA
,
1153 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1154 WM8903_VMID_SOFT_MASK
, 0);
1156 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1157 WM8903_VMID_RES_MASK
,
1158 WM8903_VMID_RES_50K
);
1160 snd_soc_update_bits(codec
, WM8903_BIAS_CONTROL_0
,
1161 WM8903_BIAS_ENA
| WM8903_POBCTRL
,
1164 /* By default no bypass paths are enabled so
1165 * enable Class W support.
1167 dev_dbg(codec
->dev
, "Enabling Class W\n");
1168 snd_soc_update_bits(codec
, WM8903_CLASS_W_0
,
1169 WM8903_CP_DYN_FREQ
|
1171 WM8903_CP_DYN_FREQ
|
1175 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1176 WM8903_VMID_RES_MASK
,
1177 WM8903_VMID_RES_250K
);
1180 case SND_SOC_BIAS_OFF
:
1181 snd_soc_update_bits(codec
, WM8903_BIAS_CONTROL_0
,
1182 WM8903_BIAS_ENA
, 0);
1184 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1185 WM8903_VMID_SOFT_MASK
,
1186 2 << WM8903_VMID_SOFT_SHIFT
);
1188 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1189 WM8903_VMID_BUF_ENA
, 0);
1193 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1194 WM8903_VMID_TIE_ENA
| WM8903_BUFIO_ENA
|
1195 WM8903_VMID_IO_ENA
| WM8903_VMID_RES_MASK
|
1196 WM8903_VMID_SOFT_MASK
|
1197 WM8903_VMID_BUF_ENA
, 0);
1199 snd_soc_update_bits(codec
, WM8903_BIAS_CONTROL_0
,
1200 WM8903_STARTUP_BIAS_ENA
, 0);
1204 codec
->dapm
.bias_level
= level
;
1209 static int wm8903_set_dai_sysclk(struct snd_soc_dai
*codec_dai
,
1210 int clk_id
, unsigned int freq
, int dir
)
1212 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1213 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1215 wm8903
->sysclk
= freq
;
1220 static int wm8903_set_dai_fmt(struct snd_soc_dai
*codec_dai
,
1223 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1224 u16 aif1
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_1
);
1226 aif1
&= ~(WM8903_LRCLK_DIR
| WM8903_BCLK_DIR
| WM8903_AIF_FMT_MASK
|
1227 WM8903_AIF_LRCLK_INV
| WM8903_AIF_BCLK_INV
);
1229 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
1230 case SND_SOC_DAIFMT_CBS_CFS
:
1232 case SND_SOC_DAIFMT_CBS_CFM
:
1233 aif1
|= WM8903_LRCLK_DIR
;
1235 case SND_SOC_DAIFMT_CBM_CFM
:
1236 aif1
|= WM8903_LRCLK_DIR
| WM8903_BCLK_DIR
;
1238 case SND_SOC_DAIFMT_CBM_CFS
:
1239 aif1
|= WM8903_BCLK_DIR
;
1245 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1246 case SND_SOC_DAIFMT_DSP_A
:
1249 case SND_SOC_DAIFMT_DSP_B
:
1250 aif1
|= 0x3 | WM8903_AIF_LRCLK_INV
;
1252 case SND_SOC_DAIFMT_I2S
:
1255 case SND_SOC_DAIFMT_RIGHT_J
:
1258 case SND_SOC_DAIFMT_LEFT_J
:
1264 /* Clock inversion */
1265 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1266 case SND_SOC_DAIFMT_DSP_A
:
1267 case SND_SOC_DAIFMT_DSP_B
:
1268 /* frame inversion not valid for DSP modes */
1269 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1270 case SND_SOC_DAIFMT_NB_NF
:
1272 case SND_SOC_DAIFMT_IB_NF
:
1273 aif1
|= WM8903_AIF_BCLK_INV
;
1279 case SND_SOC_DAIFMT_I2S
:
1280 case SND_SOC_DAIFMT_RIGHT_J
:
1281 case SND_SOC_DAIFMT_LEFT_J
:
1282 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1283 case SND_SOC_DAIFMT_NB_NF
:
1285 case SND_SOC_DAIFMT_IB_IF
:
1286 aif1
|= WM8903_AIF_BCLK_INV
| WM8903_AIF_LRCLK_INV
;
1288 case SND_SOC_DAIFMT_IB_NF
:
1289 aif1
|= WM8903_AIF_BCLK_INV
;
1291 case SND_SOC_DAIFMT_NB_IF
:
1292 aif1
|= WM8903_AIF_LRCLK_INV
;
1302 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_1
, aif1
);
1307 static int wm8903_digital_mute(struct snd_soc_dai
*codec_dai
, int mute
)
1309 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1312 reg
= snd_soc_read(codec
, WM8903_DAC_DIGITAL_1
);
1315 reg
|= WM8903_DAC_MUTE
;
1317 reg
&= ~WM8903_DAC_MUTE
;
1319 snd_soc_write(codec
, WM8903_DAC_DIGITAL_1
, reg
);
1324 /* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1325 * for optimal performance so we list the lower rates first and match
1326 * on the last match we find. */
1332 } clk_sys_ratios
[] = {
1333 { 64, 0x0, 0x0, 1 },
1334 { 68, 0x0, 0x1, 1 },
1335 { 125, 0x0, 0x2, 1 },
1336 { 128, 0x1, 0x0, 1 },
1337 { 136, 0x1, 0x1, 1 },
1338 { 192, 0x2, 0x0, 1 },
1339 { 204, 0x2, 0x1, 1 },
1341 { 64, 0x0, 0x0, 2 },
1342 { 68, 0x0, 0x1, 2 },
1343 { 125, 0x0, 0x2, 2 },
1344 { 128, 0x1, 0x0, 2 },
1345 { 136, 0x1, 0x1, 2 },
1346 { 192, 0x2, 0x0, 2 },
1347 { 204, 0x2, 0x1, 2 },
1349 { 250, 0x2, 0x2, 1 },
1350 { 256, 0x3, 0x0, 1 },
1351 { 272, 0x3, 0x1, 1 },
1352 { 384, 0x4, 0x0, 1 },
1353 { 408, 0x4, 0x1, 1 },
1354 { 375, 0x4, 0x2, 1 },
1355 { 512, 0x5, 0x0, 1 },
1356 { 544, 0x5, 0x1, 1 },
1357 { 500, 0x5, 0x2, 1 },
1358 { 768, 0x6, 0x0, 1 },
1359 { 816, 0x6, 0x1, 1 },
1360 { 750, 0x6, 0x2, 1 },
1361 { 1024, 0x7, 0x0, 1 },
1362 { 1088, 0x7, 0x1, 1 },
1363 { 1000, 0x7, 0x2, 1 },
1364 { 1408, 0x8, 0x0, 1 },
1365 { 1496, 0x8, 0x1, 1 },
1366 { 1536, 0x9, 0x0, 1 },
1367 { 1632, 0x9, 0x1, 1 },
1368 { 1500, 0x9, 0x2, 1 },
1370 { 250, 0x2, 0x2, 2 },
1371 { 256, 0x3, 0x0, 2 },
1372 { 272, 0x3, 0x1, 2 },
1373 { 384, 0x4, 0x0, 2 },
1374 { 408, 0x4, 0x1, 2 },
1375 { 375, 0x4, 0x2, 2 },
1376 { 512, 0x5, 0x0, 2 },
1377 { 544, 0x5, 0x1, 2 },
1378 { 500, 0x5, 0x2, 2 },
1379 { 768, 0x6, 0x0, 2 },
1380 { 816, 0x6, 0x1, 2 },
1381 { 750, 0x6, 0x2, 2 },
1382 { 1024, 0x7, 0x0, 2 },
1383 { 1088, 0x7, 0x1, 2 },
1384 { 1000, 0x7, 0x2, 2 },
1385 { 1408, 0x8, 0x0, 2 },
1386 { 1496, 0x8, 0x1, 2 },
1387 { 1536, 0x9, 0x0, 2 },
1388 { 1632, 0x9, 0x1, 2 },
1389 { 1500, 0x9, 0x2, 2 },
1392 /* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1416 /* Sample rates for DSP */
1420 } sample_rates
[] = {
1435 static int wm8903_hw_params(struct snd_pcm_substream
*substream
,
1436 struct snd_pcm_hw_params
*params
,
1437 struct snd_soc_dai
*dai
)
1439 struct snd_soc_codec
*codec
= dai
->codec
;
1440 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1441 int fs
= params_rate(params
);
1451 u16 aif1
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_1
);
1452 u16 aif2
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_2
);
1453 u16 aif3
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_3
);
1454 u16 clock0
= snd_soc_read(codec
, WM8903_CLOCK_RATES_0
);
1455 u16 clock1
= snd_soc_read(codec
, WM8903_CLOCK_RATES_1
);
1456 u16 dac_digital1
= snd_soc_read(codec
, WM8903_DAC_DIGITAL_1
);
1458 /* Enable sloping stopband filter for low sample rates */
1460 dac_digital1
|= WM8903_DAC_SB_FILT
;
1462 dac_digital1
&= ~WM8903_DAC_SB_FILT
;
1464 /* Configure sample rate logic for DSP - choose nearest rate */
1466 best_val
= abs(sample_rates
[dsp_config
].rate
- fs
);
1467 for (i
= 1; i
< ARRAY_SIZE(sample_rates
); i
++) {
1468 cur_val
= abs(sample_rates
[i
].rate
- fs
);
1469 if (cur_val
<= best_val
) {
1475 dev_dbg(codec
->dev
, "DSP fs = %dHz\n", sample_rates
[dsp_config
].rate
);
1476 clock1
&= ~WM8903_SAMPLE_RATE_MASK
;
1477 clock1
|= sample_rates
[dsp_config
].value
;
1479 aif1
&= ~WM8903_AIF_WL_MASK
;
1481 switch (params_width(params
)) {
1501 dev_dbg(codec
->dev
, "MCLK = %dHz, target sample rate = %dHz\n",
1502 wm8903
->sysclk
, fs
);
1504 /* We may not have an MCLK which allows us to generate exactly
1505 * the clock we want, particularly with USB derived inputs, so
1509 best_val
= abs((wm8903
->sysclk
/
1510 (clk_sys_ratios
[0].mclk_div
*
1511 clk_sys_ratios
[0].div
)) - fs
);
1512 for (i
= 1; i
< ARRAY_SIZE(clk_sys_ratios
); i
++) {
1513 cur_val
= abs((wm8903
->sysclk
/
1514 (clk_sys_ratios
[i
].mclk_div
*
1515 clk_sys_ratios
[i
].div
)) - fs
);
1517 if (cur_val
<= best_val
) {
1523 if (clk_sys_ratios
[clk_config
].mclk_div
== 2) {
1524 clock0
|= WM8903_MCLKDIV2
;
1525 clk_sys
= wm8903
->sysclk
/ 2;
1527 clock0
&= ~WM8903_MCLKDIV2
;
1528 clk_sys
= wm8903
->sysclk
;
1531 clock1
&= ~(WM8903_CLK_SYS_RATE_MASK
|
1532 WM8903_CLK_SYS_MODE_MASK
);
1533 clock1
|= clk_sys_ratios
[clk_config
].rate
<< WM8903_CLK_SYS_RATE_SHIFT
;
1534 clock1
|= clk_sys_ratios
[clk_config
].mode
<< WM8903_CLK_SYS_MODE_SHIFT
;
1536 dev_dbg(codec
->dev
, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
1537 clk_sys_ratios
[clk_config
].rate
,
1538 clk_sys_ratios
[clk_config
].mode
,
1539 clk_sys_ratios
[clk_config
].div
);
1541 dev_dbg(codec
->dev
, "Actual CLK_SYS = %dHz\n", clk_sys
);
1543 /* We may not get quite the right frequency if using
1544 * approximate clocks so look for the closest match that is
1545 * higher than the target (we need to ensure that there enough
1546 * BCLKs to clock out the samples).
1549 best_val
= ((clk_sys
* 10) / bclk_divs
[0].ratio
) - bclk
;
1551 while (i
< ARRAY_SIZE(bclk_divs
)) {
1552 cur_val
= ((clk_sys
* 10) / bclk_divs
[i
].ratio
) - bclk
;
1553 if (cur_val
< 0) /* BCLK table is sorted */
1560 aif2
&= ~WM8903_BCLK_DIV_MASK
;
1561 aif3
&= ~WM8903_LRCLK_RATE_MASK
;
1563 dev_dbg(codec
->dev
, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
1564 bclk_divs
[bclk_div
].ratio
/ 10, bclk
,
1565 (clk_sys
* 10) / bclk_divs
[bclk_div
].ratio
);
1567 aif2
|= bclk_divs
[bclk_div
].div
;
1570 wm8903
->fs
= params_rate(params
);
1571 wm8903_set_deemph(codec
);
1573 snd_soc_write(codec
, WM8903_CLOCK_RATES_0
, clock0
);
1574 snd_soc_write(codec
, WM8903_CLOCK_RATES_1
, clock1
);
1575 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_1
, aif1
);
1576 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_2
, aif2
);
1577 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_3
, aif3
);
1578 snd_soc_write(codec
, WM8903_DAC_DIGITAL_1
, dac_digital1
);
1584 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1586 * @codec: WM8903 codec
1587 * @jack: jack to report detection events on
1588 * @det: value to report for presence detection
1589 * @shrt: value to report for short detection
1591 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1592 * being used to bring out signals to the processor then only platform
1593 * data configuration is needed for WM8903 and processor GPIOs should
1594 * be configured using snd_soc_jack_add_gpios() instead.
1596 * The current threasholds for detection should be configured using
1597 * micdet_cfg in the platform data. Using this function will force on
1598 * the microphone bias for the device.
1600 int wm8903_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
1603 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1604 int irq_mask
= WM8903_MICDET_EINT
| WM8903_MICSHRT_EINT
;
1606 dev_dbg(codec
->dev
, "Enabling microphone detection: %x %x\n",
1609 /* Store the configuration */
1610 wm8903
->mic_jack
= jack
;
1611 wm8903
->mic_det
= det
;
1612 wm8903
->mic_short
= shrt
;
1614 /* Enable interrupts we've got a report configured for */
1616 irq_mask
&= ~WM8903_MICDET_EINT
;
1618 irq_mask
&= ~WM8903_MICSHRT_EINT
;
1620 snd_soc_update_bits(codec
, WM8903_INTERRUPT_STATUS_1_MASK
,
1621 WM8903_MICDET_EINT
| WM8903_MICSHRT_EINT
,
1625 /* Enable mic detection, this may not have been set through
1626 * platform data (eg, if the defaults are OK). */
1627 snd_soc_update_bits(codec
, WM8903_WRITE_SEQUENCER_0
,
1628 WM8903_WSEQ_ENA
, WM8903_WSEQ_ENA
);
1629 snd_soc_update_bits(codec
, WM8903_MIC_BIAS_CONTROL_0
,
1630 WM8903_MICDET_ENA
, WM8903_MICDET_ENA
);
1632 snd_soc_update_bits(codec
, WM8903_MIC_BIAS_CONTROL_0
,
1633 WM8903_MICDET_ENA
, 0);
1638 EXPORT_SYMBOL_GPL(wm8903_mic_detect
);
1640 static irqreturn_t
wm8903_irq(int irq
, void *data
)
1642 struct wm8903_priv
*wm8903
= data
;
1643 int mic_report
, ret
;
1644 unsigned int int_val
, mask
, int_pol
;
1646 ret
= regmap_read(wm8903
->regmap
, WM8903_INTERRUPT_STATUS_1_MASK
,
1649 dev_err(wm8903
->dev
, "Failed to read IRQ mask: %d\n", ret
);
1653 ret
= regmap_read(wm8903
->regmap
, WM8903_INTERRUPT_STATUS_1
, &int_val
);
1655 dev_err(wm8903
->dev
, "Failed to read IRQ status: %d\n", ret
);
1661 if (int_val
& WM8903_WSEQ_BUSY_EINT
) {
1662 dev_warn(wm8903
->dev
, "Write sequencer done\n");
1666 * The rest is microphone jack detection. We need to manually
1667 * invert the polarity of the interrupt after each event - to
1668 * simplify the code keep track of the last state we reported
1669 * and just invert the relevant bits in both the report and
1670 * the polarity register.
1672 mic_report
= wm8903
->mic_last_report
;
1673 ret
= regmap_read(wm8903
->regmap
, WM8903_INTERRUPT_POLARITY_1
,
1676 dev_err(wm8903
->dev
, "Failed to read interrupt polarity: %d\n",
1681 #ifndef CONFIG_SND_SOC_WM8903_MODULE
1682 if (int_val
& (WM8903_MICSHRT_EINT
| WM8903_MICDET_EINT
))
1683 trace_snd_soc_jack_irq(dev_name(wm8903
->dev
));
1686 if (int_val
& WM8903_MICSHRT_EINT
) {
1687 dev_dbg(wm8903
->dev
, "Microphone short (pol=%x)\n", int_pol
);
1689 mic_report
^= wm8903
->mic_short
;
1690 int_pol
^= WM8903_MICSHRT_INV
;
1693 if (int_val
& WM8903_MICDET_EINT
) {
1694 dev_dbg(wm8903
->dev
, "Microphone detect (pol=%x)\n", int_pol
);
1696 mic_report
^= wm8903
->mic_det
;
1697 int_pol
^= WM8903_MICDET_INV
;
1699 msleep(wm8903
->mic_delay
);
1702 regmap_update_bits(wm8903
->regmap
, WM8903_INTERRUPT_POLARITY_1
,
1703 WM8903_MICSHRT_INV
| WM8903_MICDET_INV
, int_pol
);
1705 snd_soc_jack_report(wm8903
->mic_jack
, mic_report
,
1706 wm8903
->mic_short
| wm8903
->mic_det
);
1708 wm8903
->mic_last_report
= mic_report
;
1713 #define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1714 SNDRV_PCM_RATE_11025 | \
1715 SNDRV_PCM_RATE_16000 | \
1716 SNDRV_PCM_RATE_22050 | \
1717 SNDRV_PCM_RATE_32000 | \
1718 SNDRV_PCM_RATE_44100 | \
1719 SNDRV_PCM_RATE_48000 | \
1720 SNDRV_PCM_RATE_88200 | \
1721 SNDRV_PCM_RATE_96000)
1723 #define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1724 SNDRV_PCM_RATE_11025 | \
1725 SNDRV_PCM_RATE_16000 | \
1726 SNDRV_PCM_RATE_22050 | \
1727 SNDRV_PCM_RATE_32000 | \
1728 SNDRV_PCM_RATE_44100 | \
1729 SNDRV_PCM_RATE_48000)
1731 #define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1732 SNDRV_PCM_FMTBIT_S20_3LE |\
1733 SNDRV_PCM_FMTBIT_S24_LE)
1735 static const struct snd_soc_dai_ops wm8903_dai_ops
= {
1736 .hw_params
= wm8903_hw_params
,
1737 .digital_mute
= wm8903_digital_mute
,
1738 .set_fmt
= wm8903_set_dai_fmt
,
1739 .set_sysclk
= wm8903_set_dai_sysclk
,
1742 static struct snd_soc_dai_driver wm8903_dai
= {
1743 .name
= "wm8903-hifi",
1745 .stream_name
= "Playback",
1748 .rates
= WM8903_PLAYBACK_RATES
,
1749 .formats
= WM8903_FORMATS
,
1752 .stream_name
= "Capture",
1755 .rates
= WM8903_CAPTURE_RATES
,
1756 .formats
= WM8903_FORMATS
,
1758 .ops
= &wm8903_dai_ops
,
1759 .symmetric_rates
= 1,
1762 static int wm8903_suspend(struct snd_soc_codec
*codec
)
1764 wm8903_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1769 static int wm8903_resume(struct snd_soc_codec
*codec
)
1771 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1773 regcache_sync(wm8903
->regmap
);
1775 wm8903_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1780 #ifdef CONFIG_GPIOLIB
1781 static inline struct wm8903_priv
*gpio_to_wm8903(struct gpio_chip
*chip
)
1783 return container_of(chip
, struct wm8903_priv
, gpio_chip
);
1786 static int wm8903_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
1788 if (offset
>= WM8903_NUM_GPIO
)
1794 static int wm8903_gpio_direction_in(struct gpio_chip
*chip
, unsigned offset
)
1796 struct wm8903_priv
*wm8903
= gpio_to_wm8903(chip
);
1797 unsigned int mask
, val
;
1800 mask
= WM8903_GP1_FN_MASK
| WM8903_GP1_DIR_MASK
;
1801 val
= (WM8903_GPn_FN_GPIO_INPUT
<< WM8903_GP1_FN_SHIFT
) |
1804 ret
= regmap_update_bits(wm8903
->regmap
,
1805 WM8903_GPIO_CONTROL_1
+ offset
, mask
, val
);
1812 static int wm8903_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
1814 struct wm8903_priv
*wm8903
= gpio_to_wm8903(chip
);
1817 regmap_read(wm8903
->regmap
, WM8903_GPIO_CONTROL_1
+ offset
, ®
);
1819 return (reg
& WM8903_GP1_LVL_MASK
) >> WM8903_GP1_LVL_SHIFT
;
1822 static int wm8903_gpio_direction_out(struct gpio_chip
*chip
,
1823 unsigned offset
, int value
)
1825 struct wm8903_priv
*wm8903
= gpio_to_wm8903(chip
);
1826 unsigned int mask
, val
;
1829 mask
= WM8903_GP1_FN_MASK
| WM8903_GP1_DIR_MASK
| WM8903_GP1_LVL_MASK
;
1830 val
= (WM8903_GPn_FN_GPIO_OUTPUT
<< WM8903_GP1_FN_SHIFT
) |
1831 (value
<< WM8903_GP2_LVL_SHIFT
);
1833 ret
= regmap_update_bits(wm8903
->regmap
,
1834 WM8903_GPIO_CONTROL_1
+ offset
, mask
, val
);
1841 static void wm8903_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
1843 struct wm8903_priv
*wm8903
= gpio_to_wm8903(chip
);
1845 regmap_update_bits(wm8903
->regmap
, WM8903_GPIO_CONTROL_1
+ offset
,
1846 WM8903_GP1_LVL_MASK
,
1847 !!value
<< WM8903_GP1_LVL_SHIFT
);
1850 static struct gpio_chip wm8903_template_chip
= {
1852 .owner
= THIS_MODULE
,
1853 .request
= wm8903_gpio_request
,
1854 .direction_input
= wm8903_gpio_direction_in
,
1855 .get
= wm8903_gpio_get
,
1856 .direction_output
= wm8903_gpio_direction_out
,
1857 .set
= wm8903_gpio_set
,
1861 static void wm8903_init_gpio(struct wm8903_priv
*wm8903
)
1863 struct wm8903_platform_data
*pdata
= wm8903
->pdata
;
1866 wm8903
->gpio_chip
= wm8903_template_chip
;
1867 wm8903
->gpio_chip
.ngpio
= WM8903_NUM_GPIO
;
1868 wm8903
->gpio_chip
.dev
= wm8903
->dev
;
1870 if (pdata
->gpio_base
)
1871 wm8903
->gpio_chip
.base
= pdata
->gpio_base
;
1873 wm8903
->gpio_chip
.base
= -1;
1875 ret
= gpiochip_add(&wm8903
->gpio_chip
);
1877 dev_err(wm8903
->dev
, "Failed to add GPIOs: %d\n", ret
);
1880 static void wm8903_free_gpio(struct wm8903_priv
*wm8903
)
1882 gpiochip_remove(&wm8903
->gpio_chip
);
1885 static void wm8903_init_gpio(struct wm8903_priv
*wm8903
)
1889 static void wm8903_free_gpio(struct wm8903_priv
*wm8903
)
1894 static int wm8903_probe(struct snd_soc_codec
*codec
)
1896 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1898 wm8903
->codec
= codec
;
1900 /* power on device */
1901 wm8903_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1906 /* power down chip */
1907 static int wm8903_remove(struct snd_soc_codec
*codec
)
1909 wm8903_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1914 static struct snd_soc_codec_driver soc_codec_dev_wm8903
= {
1915 .probe
= wm8903_probe
,
1916 .remove
= wm8903_remove
,
1917 .suspend
= wm8903_suspend
,
1918 .resume
= wm8903_resume
,
1919 .set_bias_level
= wm8903_set_bias_level
,
1920 .seq_notifier
= wm8903_seq_notifier
,
1921 .controls
= wm8903_snd_controls
,
1922 .num_controls
= ARRAY_SIZE(wm8903_snd_controls
),
1923 .dapm_widgets
= wm8903_dapm_widgets
,
1924 .num_dapm_widgets
= ARRAY_SIZE(wm8903_dapm_widgets
),
1925 .dapm_routes
= wm8903_intercon
,
1926 .num_dapm_routes
= ARRAY_SIZE(wm8903_intercon
),
1929 static const struct regmap_config wm8903_regmap
= {
1933 .max_register
= WM8903_MAX_REGISTER
,
1934 .volatile_reg
= wm8903_volatile_register
,
1935 .readable_reg
= wm8903_readable_register
,
1937 .cache_type
= REGCACHE_RBTREE
,
1938 .reg_defaults
= wm8903_reg_defaults
,
1939 .num_reg_defaults
= ARRAY_SIZE(wm8903_reg_defaults
),
1942 static int wm8903_set_pdata_irq_trigger(struct i2c_client
*i2c
,
1943 struct wm8903_platform_data
*pdata
)
1945 struct irq_data
*irq_data
= irq_get_irq_data(i2c
->irq
);
1947 dev_err(&i2c
->dev
, "Invalid IRQ: %d\n",
1952 switch (irqd_get_trigger_type(irq_data
)) {
1956 * We assume the controller imposes no restrictions,
1957 * so we are able to select active-high
1960 case IRQ_TYPE_LEVEL_HIGH
:
1961 pdata
->irq_active_low
= false;
1963 case IRQ_TYPE_LEVEL_LOW
:
1964 pdata
->irq_active_low
= true;
1971 static int wm8903_set_pdata_from_of(struct i2c_client
*i2c
,
1972 struct wm8903_platform_data
*pdata
)
1974 const struct device_node
*np
= i2c
->dev
.of_node
;
1978 if (of_property_read_u32(np
, "micdet-cfg", &val32
) >= 0)
1979 pdata
->micdet_cfg
= val32
;
1981 if (of_property_read_u32(np
, "micdet-delay", &val32
) >= 0)
1982 pdata
->micdet_delay
= val32
;
1984 if (of_property_read_u32_array(np
, "gpio-cfg", pdata
->gpio_cfg
,
1985 ARRAY_SIZE(pdata
->gpio_cfg
)) >= 0) {
1987 * In device tree: 0 means "write 0",
1988 * 0xffffffff means "don't touch".
1990 * In platform data: 0 means "don't touch",
1991 * 0x8000 means "write 0".
1993 * Note: WM8903_GPIO_CONFIG_ZERO == 0x8000.
1995 * Convert from DT to pdata representation here,
1996 * so no other code needs to change.
1998 for (i
= 0; i
< ARRAY_SIZE(pdata
->gpio_cfg
); i
++) {
1999 if (pdata
->gpio_cfg
[i
] == 0) {
2000 pdata
->gpio_cfg
[i
] = WM8903_GPIO_CONFIG_ZERO
;
2001 } else if (pdata
->gpio_cfg
[i
] == 0xffffffff) {
2002 pdata
->gpio_cfg
[i
] = 0;
2003 } else if (pdata
->gpio_cfg
[i
] > 0x7fff) {
2004 dev_err(&i2c
->dev
, "Invalid gpio-cfg[%d] %x\n",
2005 i
, pdata
->gpio_cfg
[i
]);
2014 static int wm8903_i2c_probe(struct i2c_client
*i2c
,
2015 const struct i2c_device_id
*id
)
2017 struct wm8903_platform_data
*pdata
= dev_get_platdata(&i2c
->dev
);
2018 struct wm8903_priv
*wm8903
;
2020 bool mic_gpio
= false;
2021 unsigned int val
, irq_pol
;
2024 wm8903
= devm_kzalloc(&i2c
->dev
, sizeof(struct wm8903_priv
),
2029 mutex_init(&wm8903
->lock
);
2030 wm8903
->dev
= &i2c
->dev
;
2032 wm8903
->regmap
= devm_regmap_init_i2c(i2c
, &wm8903_regmap
);
2033 if (IS_ERR(wm8903
->regmap
)) {
2034 ret
= PTR_ERR(wm8903
->regmap
);
2035 dev_err(&i2c
->dev
, "Failed to allocate register map: %d\n",
2040 i2c_set_clientdata(i2c
, wm8903
);
2042 /* If no platform data was supplied, create storage for defaults */
2044 wm8903
->pdata
= pdata
;
2046 wm8903
->pdata
= devm_kzalloc(&i2c
->dev
,
2047 sizeof(struct wm8903_platform_data
),
2049 if (wm8903
->pdata
== NULL
) {
2050 dev_err(&i2c
->dev
, "Failed to allocate pdata\n");
2055 ret
= wm8903_set_pdata_irq_trigger(i2c
, wm8903
->pdata
);
2060 if (i2c
->dev
.of_node
) {
2061 ret
= wm8903_set_pdata_from_of(i2c
, wm8903
->pdata
);
2067 pdata
= wm8903
->pdata
;
2069 ret
= regmap_read(wm8903
->regmap
, WM8903_SW_RESET_AND_ID
, &val
);
2071 dev_err(&i2c
->dev
, "Failed to read chip ID: %d\n", ret
);
2074 if (val
!= 0x8903) {
2075 dev_err(&i2c
->dev
, "Device with ID %x is not a WM8903\n", val
);
2080 ret
= regmap_read(wm8903
->regmap
, WM8903_REVISION_NUMBER
, &val
);
2082 dev_err(&i2c
->dev
, "Failed to read chip revision: %d\n", ret
);
2085 dev_info(&i2c
->dev
, "WM8903 revision %c\n",
2086 (val
& WM8903_CHIP_REV_MASK
) + 'A');
2088 /* Reset the device */
2089 regmap_write(wm8903
->regmap
, WM8903_SW_RESET_AND_ID
, 0x8903);
2091 wm8903_init_gpio(wm8903
);
2093 /* Set up GPIO pin state, detect if any are MIC detect outputs */
2094 for (i
= 0; i
< ARRAY_SIZE(pdata
->gpio_cfg
); i
++) {
2095 if ((!pdata
->gpio_cfg
[i
]) ||
2096 (pdata
->gpio_cfg
[i
] > WM8903_GPIO_CONFIG_ZERO
))
2099 regmap_write(wm8903
->regmap
, WM8903_GPIO_CONTROL_1
+ i
,
2100 pdata
->gpio_cfg
[i
] & 0x7fff);
2102 val
= (pdata
->gpio_cfg
[i
] & WM8903_GP1_FN_MASK
)
2103 >> WM8903_GP1_FN_SHIFT
;
2106 case WM8903_GPn_FN_MICBIAS_CURRENT_DETECT
:
2107 case WM8903_GPn_FN_MICBIAS_SHORT_DETECT
:
2115 /* Set up microphone detection */
2116 regmap_write(wm8903
->regmap
, WM8903_MIC_BIAS_CONTROL_0
,
2119 /* Microphone detection needs the WSEQ clock */
2120 if (pdata
->micdet_cfg
)
2121 regmap_update_bits(wm8903
->regmap
, WM8903_WRITE_SEQUENCER_0
,
2122 WM8903_WSEQ_ENA
, WM8903_WSEQ_ENA
);
2124 /* If microphone detection is enabled by pdata but
2125 * detected via IRQ then interrupts can be lost before
2126 * the machine driver has set up microphone detection
2127 * IRQs as the IRQs are clear on read. The detection
2128 * will be enabled when the machine driver configures.
2130 WARN_ON(!mic_gpio
&& (pdata
->micdet_cfg
& WM8903_MICDET_ENA
));
2132 wm8903
->mic_delay
= pdata
->micdet_delay
;
2135 if (pdata
->irq_active_low
) {
2136 trigger
= IRQF_TRIGGER_LOW
;
2137 irq_pol
= WM8903_IRQ_POL
;
2139 trigger
= IRQF_TRIGGER_HIGH
;
2143 regmap_update_bits(wm8903
->regmap
, WM8903_INTERRUPT_CONTROL
,
2144 WM8903_IRQ_POL
, irq_pol
);
2146 ret
= request_threaded_irq(i2c
->irq
, NULL
, wm8903_irq
,
2147 trigger
| IRQF_ONESHOT
,
2150 dev_err(wm8903
->dev
, "Failed to request IRQ: %d\n",
2155 /* Enable write sequencer interrupts */
2156 regmap_update_bits(wm8903
->regmap
,
2157 WM8903_INTERRUPT_STATUS_1_MASK
,
2158 WM8903_IM_WSEQ_BUSY_EINT
, 0);
2161 /* Latch volume update bits */
2162 regmap_update_bits(wm8903
->regmap
, WM8903_ADC_DIGITAL_VOLUME_LEFT
,
2163 WM8903_ADCVU
, WM8903_ADCVU
);
2164 regmap_update_bits(wm8903
->regmap
, WM8903_ADC_DIGITAL_VOLUME_RIGHT
,
2165 WM8903_ADCVU
, WM8903_ADCVU
);
2167 regmap_update_bits(wm8903
->regmap
, WM8903_DAC_DIGITAL_VOLUME_LEFT
,
2168 WM8903_DACVU
, WM8903_DACVU
);
2169 regmap_update_bits(wm8903
->regmap
, WM8903_DAC_DIGITAL_VOLUME_RIGHT
,
2170 WM8903_DACVU
, WM8903_DACVU
);
2172 regmap_update_bits(wm8903
->regmap
, WM8903_ANALOGUE_OUT1_LEFT
,
2173 WM8903_HPOUTVU
, WM8903_HPOUTVU
);
2174 regmap_update_bits(wm8903
->regmap
, WM8903_ANALOGUE_OUT1_RIGHT
,
2175 WM8903_HPOUTVU
, WM8903_HPOUTVU
);
2177 regmap_update_bits(wm8903
->regmap
, WM8903_ANALOGUE_OUT2_LEFT
,
2178 WM8903_LINEOUTVU
, WM8903_LINEOUTVU
);
2179 regmap_update_bits(wm8903
->regmap
, WM8903_ANALOGUE_OUT2_RIGHT
,
2180 WM8903_LINEOUTVU
, WM8903_LINEOUTVU
);
2182 regmap_update_bits(wm8903
->regmap
, WM8903_ANALOGUE_OUT3_LEFT
,
2183 WM8903_SPKVU
, WM8903_SPKVU
);
2184 regmap_update_bits(wm8903
->regmap
, WM8903_ANALOGUE_OUT3_RIGHT
,
2185 WM8903_SPKVU
, WM8903_SPKVU
);
2187 /* Enable DAC soft mute by default */
2188 regmap_update_bits(wm8903
->regmap
, WM8903_DAC_DIGITAL_1
,
2189 WM8903_DAC_MUTEMODE
| WM8903_DAC_MUTE
,
2190 WM8903_DAC_MUTEMODE
| WM8903_DAC_MUTE
);
2192 ret
= snd_soc_register_codec(&i2c
->dev
,
2193 &soc_codec_dev_wm8903
, &wm8903_dai
, 1);
2202 static int wm8903_i2c_remove(struct i2c_client
*client
)
2204 struct wm8903_priv
*wm8903
= i2c_get_clientdata(client
);
2207 free_irq(client
->irq
, wm8903
);
2208 wm8903_free_gpio(wm8903
);
2209 snd_soc_unregister_codec(&client
->dev
);
2214 static const struct of_device_id wm8903_of_match
[] = {
2215 { .compatible
= "wlf,wm8903", },
2218 MODULE_DEVICE_TABLE(of
, wm8903_of_match
);
2220 static const struct i2c_device_id wm8903_i2c_id
[] = {
2224 MODULE_DEVICE_TABLE(i2c
, wm8903_i2c_id
);
2226 static struct i2c_driver wm8903_i2c_driver
= {
2229 .owner
= THIS_MODULE
,
2230 .of_match_table
= wm8903_of_match
,
2232 .probe
= wm8903_i2c_probe
,
2233 .remove
= wm8903_i2c_remove
,
2234 .id_table
= wm8903_i2c_id
,
2237 module_i2c_driver(wm8903_i2c_driver
);
2239 MODULE_DESCRIPTION("ASoC WM8903 driver");
2240 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
2241 MODULE_LICENSE("GPL");