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ASoC: Convert WM8903 to use PGA_S for output stage enables
[deliverable/linux.git] / sound / soc / codecs / wm8903.c
1 /*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics
5 * Copyright 2011 NVIDIA, Inc.
6 *
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * TODO:
14 * - TDM mode configuration.
15 * - Digital microphone support.
16 */
17
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/init.h>
21 #include <linux/completion.h>
22 #include <linux/delay.h>
23 #include <linux/gpio.h>
24 #include <linux/pm.h>
25 #include <linux/i2c.h>
26 #include <linux/platform_device.h>
27 #include <linux/slab.h>
28 #include <sound/core.h>
29 #include <sound/jack.h>
30 #include <sound/pcm.h>
31 #include <sound/pcm_params.h>
32 #include <sound/tlv.h>
33 #include <sound/soc.h>
34 #include <sound/initval.h>
35 #include <sound/wm8903.h>
36 #include <trace/events/asoc.h>
37
38 #include "wm8903.h"
39
40 /* Register defaults at reset */
41 static u16 wm8903_reg_defaults[] = {
42 0x8903, /* R0 - SW Reset and ID */
43 0x0000, /* R1 - Revision Number */
44 0x0000, /* R2 */
45 0x0000, /* R3 */
46 0x0018, /* R4 - Bias Control 0 */
47 0x0000, /* R5 - VMID Control 0 */
48 0x0000, /* R6 - Mic Bias Control 0 */
49 0x0000, /* R7 */
50 0x0001, /* R8 - Analogue DAC 0 */
51 0x0000, /* R9 */
52 0x0001, /* R10 - Analogue ADC 0 */
53 0x0000, /* R11 */
54 0x0000, /* R12 - Power Management 0 */
55 0x0000, /* R13 - Power Management 1 */
56 0x0000, /* R14 - Power Management 2 */
57 0x0000, /* R15 - Power Management 3 */
58 0x0000, /* R16 - Power Management 4 */
59 0x0000, /* R17 - Power Management 5 */
60 0x0000, /* R18 - Power Management 6 */
61 0x0000, /* R19 */
62 0x0400, /* R20 - Clock Rates 0 */
63 0x0D07, /* R21 - Clock Rates 1 */
64 0x0000, /* R22 - Clock Rates 2 */
65 0x0000, /* R23 */
66 0x0050, /* R24 - Audio Interface 0 */
67 0x0242, /* R25 - Audio Interface 1 */
68 0x0008, /* R26 - Audio Interface 2 */
69 0x0022, /* R27 - Audio Interface 3 */
70 0x0000, /* R28 */
71 0x0000, /* R29 */
72 0x00C0, /* R30 - DAC Digital Volume Left */
73 0x00C0, /* R31 - DAC Digital Volume Right */
74 0x0000, /* R32 - DAC Digital 0 */
75 0x0000, /* R33 - DAC Digital 1 */
76 0x0000, /* R34 */
77 0x0000, /* R35 */
78 0x00C0, /* R36 - ADC Digital Volume Left */
79 0x00C0, /* R37 - ADC Digital Volume Right */
80 0x0000, /* R38 - ADC Digital 0 */
81 0x0073, /* R39 - Digital Microphone 0 */
82 0x09BF, /* R40 - DRC 0 */
83 0x3241, /* R41 - DRC 1 */
84 0x0020, /* R42 - DRC 2 */
85 0x0000, /* R43 - DRC 3 */
86 0x0085, /* R44 - Analogue Left Input 0 */
87 0x0085, /* R45 - Analogue Right Input 0 */
88 0x0044, /* R46 - Analogue Left Input 1 */
89 0x0044, /* R47 - Analogue Right Input 1 */
90 0x0000, /* R48 */
91 0x0000, /* R49 */
92 0x0008, /* R50 - Analogue Left Mix 0 */
93 0x0004, /* R51 - Analogue Right Mix 0 */
94 0x0000, /* R52 - Analogue Spk Mix Left 0 */
95 0x0000, /* R53 - Analogue Spk Mix Left 1 */
96 0x0000, /* R54 - Analogue Spk Mix Right 0 */
97 0x0000, /* R55 - Analogue Spk Mix Right 1 */
98 0x0000, /* R56 */
99 0x002D, /* R57 - Analogue OUT1 Left */
100 0x002D, /* R58 - Analogue OUT1 Right */
101 0x0039, /* R59 - Analogue OUT2 Left */
102 0x0039, /* R60 - Analogue OUT2 Right */
103 0x0100, /* R61 */
104 0x0139, /* R62 - Analogue OUT3 Left */
105 0x0139, /* R63 - Analogue OUT3 Right */
106 0x0000, /* R64 */
107 0x0000, /* R65 - Analogue SPK Output Control 0 */
108 0x0000, /* R66 */
109 0x0010, /* R67 - DC Servo 0 */
110 0x0100, /* R68 */
111 0x00A4, /* R69 - DC Servo 2 */
112 0x0807, /* R70 */
113 0x0000, /* R71 */
114 0x0000, /* R72 */
115 0x0000, /* R73 */
116 0x0000, /* R74 */
117 0x0000, /* R75 */
118 0x0000, /* R76 */
119 0x0000, /* R77 */
120 0x0000, /* R78 */
121 0x000E, /* R79 */
122 0x0000, /* R80 */
123 0x0000, /* R81 */
124 0x0000, /* R82 */
125 0x0000, /* R83 */
126 0x0000, /* R84 */
127 0x0000, /* R85 */
128 0x0000, /* R86 */
129 0x0006, /* R87 */
130 0x0000, /* R88 */
131 0x0000, /* R89 */
132 0x0000, /* R90 - Analogue HP 0 */
133 0x0060, /* R91 */
134 0x0000, /* R92 */
135 0x0000, /* R93 */
136 0x0000, /* R94 - Analogue Lineout 0 */
137 0x0060, /* R95 */
138 0x0000, /* R96 */
139 0x0000, /* R97 */
140 0x0000, /* R98 - Charge Pump 0 */
141 0x1F25, /* R99 */
142 0x2B19, /* R100 */
143 0x01C0, /* R101 */
144 0x01EF, /* R102 */
145 0x2B00, /* R103 */
146 0x0000, /* R104 - Class W 0 */
147 0x01C0, /* R105 */
148 0x1C10, /* R106 */
149 0x0000, /* R107 */
150 0x0000, /* R108 - Write Sequencer 0 */
151 0x0000, /* R109 - Write Sequencer 1 */
152 0x0000, /* R110 - Write Sequencer 2 */
153 0x0000, /* R111 - Write Sequencer 3 */
154 0x0000, /* R112 - Write Sequencer 4 */
155 0x0000, /* R113 */
156 0x0000, /* R114 - Control Interface */
157 0x0000, /* R115 */
158 0x00A8, /* R116 - GPIO Control 1 */
159 0x00A8, /* R117 - GPIO Control 2 */
160 0x00A8, /* R118 - GPIO Control 3 */
161 0x0220, /* R119 - GPIO Control 4 */
162 0x01A0, /* R120 - GPIO Control 5 */
163 0x0000, /* R121 - Interrupt Status 1 */
164 0xFFFF, /* R122 - Interrupt Status 1 Mask */
165 0x0000, /* R123 - Interrupt Polarity 1 */
166 0x0000, /* R124 */
167 0x0003, /* R125 */
168 0x0000, /* R126 - Interrupt Control */
169 0x0000, /* R127 */
170 0x0005, /* R128 */
171 0x0000, /* R129 - Control Interface Test 1 */
172 0x0000, /* R130 */
173 0x0000, /* R131 */
174 0x0000, /* R132 */
175 0x0000, /* R133 */
176 0x0000, /* R134 */
177 0x03FF, /* R135 */
178 0x0007, /* R136 */
179 0x0040, /* R137 */
180 0x0000, /* R138 */
181 0x0000, /* R139 */
182 0x0000, /* R140 */
183 0x0000, /* R141 */
184 0x0000, /* R142 */
185 0x0000, /* R143 */
186 0x0000, /* R144 */
187 0x0000, /* R145 */
188 0x0000, /* R146 */
189 0x0000, /* R147 */
190 0x4000, /* R148 */
191 0x6810, /* R149 - Charge Pump Test 1 */
192 0x0004, /* R150 */
193 0x0000, /* R151 */
194 0x0000, /* R152 */
195 0x0000, /* R153 */
196 0x0000, /* R154 */
197 0x0000, /* R155 */
198 0x0000, /* R156 */
199 0x0000, /* R157 */
200 0x0000, /* R158 */
201 0x0000, /* R159 */
202 0x0000, /* R160 */
203 0x0000, /* R161 */
204 0x0000, /* R162 */
205 0x0000, /* R163 */
206 0x0028, /* R164 - Clock Rate Test 4 */
207 0x0004, /* R165 */
208 0x0000, /* R166 */
209 0x0060, /* R167 */
210 0x0000, /* R168 */
211 0x0000, /* R169 */
212 0x0000, /* R170 */
213 0x0000, /* R171 */
214 0x0000, /* R172 - Analogue Output Bias 0 */
215 };
216
217 struct wm8903_priv {
218 struct snd_soc_codec *codec;
219
220 int sysclk;
221 int irq;
222
223 int fs;
224 int deemph;
225
226 /* Reference count */
227 int class_w_users;
228
229 struct completion wseq;
230
231 struct snd_soc_jack *mic_jack;
232 int mic_det;
233 int mic_short;
234 int mic_last_report;
235 int mic_delay;
236
237 #ifdef CONFIG_GPIOLIB
238 struct gpio_chip gpio_chip;
239 #endif
240 };
241
242 static int wm8903_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
243 {
244 switch (reg) {
245 case WM8903_SW_RESET_AND_ID:
246 case WM8903_REVISION_NUMBER:
247 case WM8903_INTERRUPT_STATUS_1:
248 case WM8903_WRITE_SEQUENCER_4:
249 case WM8903_POWER_MANAGEMENT_3:
250 case WM8903_POWER_MANAGEMENT_2:
251 return 1;
252
253 default:
254 return 0;
255 }
256 }
257
258 static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
259 {
260 u16 reg[5];
261 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
262
263 BUG_ON(start > 48);
264
265 /* Enable the sequencer if it's not already on */
266 reg[0] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_0);
267 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0,
268 reg[0] | WM8903_WSEQ_ENA);
269
270 dev_dbg(codec->dev, "Starting sequence at %d\n", start);
271
272 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_3,
273 start | WM8903_WSEQ_START);
274
275 /* Wait for it to complete. If we have the interrupt wired up then
276 * that will break us out of the poll early.
277 */
278 do {
279 wait_for_completion_timeout(&wm8903->wseq,
280 msecs_to_jiffies(10));
281
282 reg[4] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_4);
283 } while (reg[4] & WM8903_WSEQ_BUSY);
284
285 dev_dbg(codec->dev, "Sequence complete\n");
286
287 /* Disable the sequencer again if we enabled it */
288 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]);
289
290 return 0;
291 }
292
293 static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache)
294 {
295 int i;
296
297 /* There really ought to be something better we can do here :/ */
298 for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
299 cache[i] = codec->hw_read(codec, i);
300 }
301
302 static void wm8903_reset(struct snd_soc_codec *codec)
303 {
304 snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0);
305 memcpy(codec->reg_cache, wm8903_reg_defaults,
306 sizeof(wm8903_reg_defaults));
307 }
308
309 static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
310 struct snd_kcontrol *kcontrol, int event)
311 {
312 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
313 mdelay(4);
314
315 return 0;
316 }
317
318 /*
319 * When used with DAC outputs only the WM8903 charge pump supports
320 * operation in class W mode, providing very low power consumption
321 * when used with digital sources. Enable and disable this mode
322 * automatically depending on the mixer configuration.
323 *
324 * All the relevant controls are simple switches.
325 */
326 static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
327 struct snd_ctl_elem_value *ucontrol)
328 {
329 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
330 struct snd_soc_codec *codec = widget->codec;
331 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
332 u16 reg;
333 int ret;
334
335 reg = snd_soc_read(codec, WM8903_CLASS_W_0);
336
337 /* Turn it off if we're about to enable bypass */
338 if (ucontrol->value.integer.value[0]) {
339 if (wm8903->class_w_users == 0) {
340 dev_dbg(codec->dev, "Disabling Class W\n");
341 snd_soc_write(codec, WM8903_CLASS_W_0, reg &
342 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
343 }
344 wm8903->class_w_users++;
345 }
346
347 /* Implement the change */
348 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
349
350 /* If we've just disabled the last bypass path turn Class W on */
351 if (!ucontrol->value.integer.value[0]) {
352 if (wm8903->class_w_users == 1) {
353 dev_dbg(codec->dev, "Enabling Class W\n");
354 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
355 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
356 }
357 wm8903->class_w_users--;
358 }
359
360 dev_dbg(codec->dev, "Bypass use count now %d\n",
361 wm8903->class_w_users);
362
363 return ret;
364 }
365
366 #define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
367 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
368 .info = snd_soc_info_volsw, \
369 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
370 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
371
372
373 static int wm8903_deemph[] = { 0, 32000, 44100, 48000 };
374
375 static int wm8903_set_deemph(struct snd_soc_codec *codec)
376 {
377 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
378 int val, i, best;
379
380 /* If we're using deemphasis select the nearest available sample
381 * rate.
382 */
383 if (wm8903->deemph) {
384 best = 1;
385 for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) {
386 if (abs(wm8903_deemph[i] - wm8903->fs) <
387 abs(wm8903_deemph[best] - wm8903->fs))
388 best = i;
389 }
390
391 val = best << WM8903_DEEMPH_SHIFT;
392 } else {
393 best = 0;
394 val = 0;
395 }
396
397 dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n",
398 best, wm8903_deemph[best]);
399
400 return snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
401 WM8903_DEEMPH_MASK, val);
402 }
403
404 static int wm8903_get_deemph(struct snd_kcontrol *kcontrol,
405 struct snd_ctl_elem_value *ucontrol)
406 {
407 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
408 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
409
410 ucontrol->value.enumerated.item[0] = wm8903->deemph;
411
412 return 0;
413 }
414
415 static int wm8903_put_deemph(struct snd_kcontrol *kcontrol,
416 struct snd_ctl_elem_value *ucontrol)
417 {
418 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
419 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
420 int deemph = ucontrol->value.enumerated.item[0];
421 int ret = 0;
422
423 if (deemph > 1)
424 return -EINVAL;
425
426 mutex_lock(&codec->mutex);
427 if (wm8903->deemph != deemph) {
428 wm8903->deemph = deemph;
429
430 wm8903_set_deemph(codec);
431
432 ret = 1;
433 }
434 mutex_unlock(&codec->mutex);
435
436 return ret;
437 }
438
439 /* ALSA can only do steps of .01dB */
440 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
441
442 static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
443 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
444
445 static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
446 static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
447 static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
448 static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
449 static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
450
451 static const char *hpf_mode_text[] = {
452 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
453 };
454
455 static const struct soc_enum hpf_mode =
456 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0, 5, 4, hpf_mode_text);
457
458 static const char *osr_text[] = {
459 "Low power", "High performance"
460 };
461
462 static const struct soc_enum adc_osr =
463 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0, 0, 2, osr_text);
464
465 static const struct soc_enum dac_osr =
466 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 0, 2, osr_text);
467
468 static const char *drc_slope_text[] = {
469 "1", "1/2", "1/4", "1/8", "1/16", "0"
470 };
471
472 static const struct soc_enum drc_slope_r0 =
473 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
474
475 static const struct soc_enum drc_slope_r1 =
476 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
477
478 static const char *drc_attack_text[] = {
479 "instantaneous",
480 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
481 "46.4ms", "92.8ms", "185.6ms"
482 };
483
484 static const struct soc_enum drc_attack =
485 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
486
487 static const char *drc_decay_text[] = {
488 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
489 "23.87s", "47.56s"
490 };
491
492 static const struct soc_enum drc_decay =
493 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
494
495 static const char *drc_ff_delay_text[] = {
496 "5 samples", "9 samples"
497 };
498
499 static const struct soc_enum drc_ff_delay =
500 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
501
502 static const char *drc_qr_decay_text[] = {
503 "0.725ms", "1.45ms", "5.8ms"
504 };
505
506 static const struct soc_enum drc_qr_decay =
507 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
508
509 static const char *drc_smoothing_text[] = {
510 "Low", "Medium", "High"
511 };
512
513 static const struct soc_enum drc_smoothing =
514 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
515
516 static const char *soft_mute_text[] = {
517 "Fast (fs/2)", "Slow (fs/32)"
518 };
519
520 static const struct soc_enum soft_mute =
521 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
522
523 static const char *mute_mode_text[] = {
524 "Hard", "Soft"
525 };
526
527 static const struct soc_enum mute_mode =
528 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
529
530 static const char *companding_text[] = {
531 "ulaw", "alaw"
532 };
533
534 static const struct soc_enum dac_companding =
535 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
536
537 static const struct soc_enum adc_companding =
538 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
539
540 static const char *input_mode_text[] = {
541 "Single-Ended", "Differential Line", "Differential Mic"
542 };
543
544 static const struct soc_enum linput_mode_enum =
545 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
546
547 static const struct soc_enum rinput_mode_enum =
548 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
549
550 static const char *linput_mux_text[] = {
551 "IN1L", "IN2L", "IN3L"
552 };
553
554 static const struct soc_enum linput_enum =
555 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
556
557 static const struct soc_enum linput_inv_enum =
558 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
559
560 static const char *rinput_mux_text[] = {
561 "IN1R", "IN2R", "IN3R"
562 };
563
564 static const struct soc_enum rinput_enum =
565 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
566
567 static const struct soc_enum rinput_inv_enum =
568 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
569
570
571 static const char *sidetone_text[] = {
572 "None", "Left", "Right"
573 };
574
575 static const struct soc_enum lsidetone_enum =
576 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text);
577
578 static const struct soc_enum rsidetone_enum =
579 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text);
580
581 static const char *aif_text[] = {
582 "Left", "Right"
583 };
584
585 static const struct soc_enum lcapture_enum =
586 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 7, 2, aif_text);
587
588 static const struct soc_enum rcapture_enum =
589 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 6, 2, aif_text);
590
591 static const struct soc_enum lplay_enum =
592 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 5, 2, aif_text);
593
594 static const struct soc_enum rplay_enum =
595 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 4, 2, aif_text);
596
597 static const struct snd_kcontrol_new wm8903_snd_controls[] = {
598
599 /* Input PGAs - No TLV since the scale depends on PGA mode */
600 SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
601 7, 1, 1),
602 SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
603 0, 31, 0),
604 SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
605 6, 1, 0),
606
607 SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
608 7, 1, 1),
609 SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
610 0, 31, 0),
611 SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
612 6, 1, 0),
613
614 /* ADCs */
615 SOC_ENUM("ADC OSR", adc_osr),
616 SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),
617 SOC_ENUM("HPF Mode", hpf_mode),
618 SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
619 SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
620 SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
621 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
622 drc_tlv_thresh),
623 SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
624 SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
625 SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
626 SOC_ENUM("DRC Attack Rate", drc_attack),
627 SOC_ENUM("DRC Decay Rate", drc_decay),
628 SOC_ENUM("DRC FF Delay", drc_ff_delay),
629 SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
630 SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
631 SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
632 SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
633 SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
634 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
635 SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
636 SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
637
638 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
639 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
640 SOC_ENUM("ADC Companding Mode", adc_companding),
641 SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
642
643 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
644 12, 0, digital_sidetone_tlv),
645
646 /* DAC */
647 SOC_ENUM("DAC OSR", dac_osr),
648 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
649 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
650 SOC_ENUM("DAC Soft Mute Rate", soft_mute),
651 SOC_ENUM("DAC Mute Mode", mute_mode),
652 SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
653 SOC_ENUM("DAC Companding Mode", dac_companding),
654 SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
655 SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
656 wm8903_get_deemph, wm8903_put_deemph),
657
658 /* Headphones */
659 SOC_DOUBLE_R("Headphone Switch",
660 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
661 8, 1, 1),
662 SOC_DOUBLE_R("Headphone ZC Switch",
663 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
664 6, 1, 0),
665 SOC_DOUBLE_R_TLV("Headphone Volume",
666 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
667 0, 63, 0, out_tlv),
668
669 /* Line out */
670 SOC_DOUBLE_R("Line Out Switch",
671 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
672 8, 1, 1),
673 SOC_DOUBLE_R("Line Out ZC Switch",
674 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
675 6, 1, 0),
676 SOC_DOUBLE_R_TLV("Line Out Volume",
677 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
678 0, 63, 0, out_tlv),
679
680 /* Speaker */
681 SOC_DOUBLE_R("Speaker Switch",
682 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
683 SOC_DOUBLE_R("Speaker ZC Switch",
684 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
685 SOC_DOUBLE_R_TLV("Speaker Volume",
686 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
687 0, 63, 0, out_tlv),
688 };
689
690 static const struct snd_kcontrol_new linput_mode_mux =
691 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
692
693 static const struct snd_kcontrol_new rinput_mode_mux =
694 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
695
696 static const struct snd_kcontrol_new linput_mux =
697 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
698
699 static const struct snd_kcontrol_new linput_inv_mux =
700 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
701
702 static const struct snd_kcontrol_new rinput_mux =
703 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
704
705 static const struct snd_kcontrol_new rinput_inv_mux =
706 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
707
708 static const struct snd_kcontrol_new lsidetone_mux =
709 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
710
711 static const struct snd_kcontrol_new rsidetone_mux =
712 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
713
714 static const struct snd_kcontrol_new lcapture_mux =
715 SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum);
716
717 static const struct snd_kcontrol_new rcapture_mux =
718 SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum);
719
720 static const struct snd_kcontrol_new lplay_mux =
721 SOC_DAPM_ENUM("Left Playback Mux", lplay_enum);
722
723 static const struct snd_kcontrol_new rplay_mux =
724 SOC_DAPM_ENUM("Right Playback Mux", rplay_enum);
725
726 static const struct snd_kcontrol_new left_output_mixer[] = {
727 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
728 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
729 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
730 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
731 };
732
733 static const struct snd_kcontrol_new right_output_mixer[] = {
734 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
735 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
736 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
737 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
738 };
739
740 static const struct snd_kcontrol_new left_speaker_mixer[] = {
741 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
742 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
743 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
744 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
745 0, 1, 0),
746 };
747
748 static const struct snd_kcontrol_new right_speaker_mixer[] = {
749 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
750 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
751 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
752 1, 1, 0),
753 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
754 0, 1, 0),
755 };
756
757 static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
758 SND_SOC_DAPM_INPUT("IN1L"),
759 SND_SOC_DAPM_INPUT("IN1R"),
760 SND_SOC_DAPM_INPUT("IN2L"),
761 SND_SOC_DAPM_INPUT("IN2R"),
762 SND_SOC_DAPM_INPUT("IN3L"),
763 SND_SOC_DAPM_INPUT("IN3R"),
764
765 SND_SOC_DAPM_OUTPUT("HPOUTL"),
766 SND_SOC_DAPM_OUTPUT("HPOUTR"),
767 SND_SOC_DAPM_OUTPUT("LINEOUTL"),
768 SND_SOC_DAPM_OUTPUT("LINEOUTR"),
769 SND_SOC_DAPM_OUTPUT("LOP"),
770 SND_SOC_DAPM_OUTPUT("LON"),
771 SND_SOC_DAPM_OUTPUT("ROP"),
772 SND_SOC_DAPM_OUTPUT("RON"),
773
774 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0),
775
776 SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
777 SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
778 &linput_inv_mux),
779 SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
780
781 SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
782 SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
783 &rinput_inv_mux),
784 SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
785
786 SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
787 SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
788
789 SND_SOC_DAPM_ADC("ADCL", NULL, WM8903_POWER_MANAGEMENT_6, 1, 0),
790 SND_SOC_DAPM_ADC("ADCR", NULL, WM8903_POWER_MANAGEMENT_6, 0, 0),
791
792 SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lcapture_mux),
793 SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rcapture_mux),
794
795 SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
796 SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
797
798 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
799 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
800
801 SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM, 0, 0),
802 SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM, 0, 0),
803
804 SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM, 0, 0, &lplay_mux),
805 SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM, 0, 0, &rplay_mux),
806
807 SND_SOC_DAPM_DAC("DACL", NULL, WM8903_POWER_MANAGEMENT_6, 3, 0),
808 SND_SOC_DAPM_DAC("DACR", NULL, WM8903_POWER_MANAGEMENT_6, 2, 0),
809
810 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
811 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
812 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
813 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
814
815 SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
816 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
817 SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
818 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
819
820 SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_ANALOGUE_HP_0,
821 4, 0, NULL, 0),
822 SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_ANALOGUE_HP_0,
823 0, 0, NULL, 0),
824
825 SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_ANALOGUE_LINEOUT_0, 4, 0,
826 NULL, 0),
827 SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_ANALOGUE_LINEOUT_0, 0, 0,
828 NULL, 0),
829
830 SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 7, 0, NULL, 0),
831 SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 6, 0, NULL, 0),
832 SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 1, WM8903_ANALOGUE_HP_0, 5, 0, NULL, 0),
833 SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 3, 0, NULL, 0),
834 SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 2, 0, NULL, 0),
835 SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 1, WM8903_ANALOGUE_HP_0, 1, 0, NULL, 0),
836
837 SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 7, 0,
838 NULL, 0),
839 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 6, 0,
840 NULL, 0),
841 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 1, WM8903_ANALOGUE_LINEOUT_0, 5, 0,
842 NULL, 0),
843 SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 3, 0,
844 NULL, 0),
845 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 2, 0,
846 NULL, 0),
847 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 1, WM8903_ANALOGUE_LINEOUT_0, 1, 0,
848 NULL, 0),
849
850 SND_SOC_DAPM_PGA_S("HPL_DCS", 3, WM8903_DC_SERVO_0, 3, 0, NULL, 0),
851 SND_SOC_DAPM_PGA_S("HPR_DCS", 3, WM8903_DC_SERVO_0, 2, 0, NULL, 0),
852 SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, WM8903_DC_SERVO_0, 1, 0, NULL, 0),
853 SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, WM8903_DC_SERVO_0, 0, 0, NULL, 0),
854
855 SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
856 NULL, 0),
857 SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
858 NULL, 0),
859
860 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
861 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
862 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
863 };
864
865 static const struct snd_soc_dapm_route intercon[] = {
866
867 { "Left Input Mux", "IN1L", "IN1L" },
868 { "Left Input Mux", "IN2L", "IN2L" },
869 { "Left Input Mux", "IN3L", "IN3L" },
870
871 { "Left Input Inverting Mux", "IN1L", "IN1L" },
872 { "Left Input Inverting Mux", "IN2L", "IN2L" },
873 { "Left Input Inverting Mux", "IN3L", "IN3L" },
874
875 { "Right Input Mux", "IN1R", "IN1R" },
876 { "Right Input Mux", "IN2R", "IN2R" },
877 { "Right Input Mux", "IN3R", "IN3R" },
878
879 { "Right Input Inverting Mux", "IN1R", "IN1R" },
880 { "Right Input Inverting Mux", "IN2R", "IN2R" },
881 { "Right Input Inverting Mux", "IN3R", "IN3R" },
882
883 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
884 { "Left Input Mode Mux", "Differential Line",
885 "Left Input Mux" },
886 { "Left Input Mode Mux", "Differential Line",
887 "Left Input Inverting Mux" },
888 { "Left Input Mode Mux", "Differential Mic",
889 "Left Input Mux" },
890 { "Left Input Mode Mux", "Differential Mic",
891 "Left Input Inverting Mux" },
892
893 { "Right Input Mode Mux", "Single-Ended",
894 "Right Input Inverting Mux" },
895 { "Right Input Mode Mux", "Differential Line",
896 "Right Input Mux" },
897 { "Right Input Mode Mux", "Differential Line",
898 "Right Input Inverting Mux" },
899 { "Right Input Mode Mux", "Differential Mic",
900 "Right Input Mux" },
901 { "Right Input Mode Mux", "Differential Mic",
902 "Right Input Inverting Mux" },
903
904 { "Left Input PGA", NULL, "Left Input Mode Mux" },
905 { "Right Input PGA", NULL, "Right Input Mode Mux" },
906
907 { "Left Capture Mux", "Left", "ADCL" },
908 { "Left Capture Mux", "Right", "ADCR" },
909
910 { "Right Capture Mux", "Left", "ADCL" },
911 { "Right Capture Mux", "Right", "ADCR" },
912
913 { "AIFTXL", NULL, "Left Capture Mux" },
914 { "AIFTXR", NULL, "Right Capture Mux" },
915
916 { "ADCL", NULL, "Left Input PGA" },
917 { "ADCL", NULL, "CLK_DSP" },
918 { "ADCR", NULL, "Right Input PGA" },
919 { "ADCR", NULL, "CLK_DSP" },
920
921 { "Left Playback Mux", "Left", "AIFRXL" },
922 { "Left Playback Mux", "Right", "AIFRXR" },
923
924 { "Right Playback Mux", "Left", "AIFRXL" },
925 { "Right Playback Mux", "Right", "AIFRXR" },
926
927 { "DACL Sidetone", "Left", "ADCL" },
928 { "DACL Sidetone", "Right", "ADCR" },
929 { "DACR Sidetone", "Left", "ADCL" },
930 { "DACR Sidetone", "Right", "ADCR" },
931
932 { "DACL", NULL, "Left Playback Mux" },
933 { "DACL", NULL, "DACL Sidetone" },
934 { "DACL", NULL, "CLK_DSP" },
935
936 { "DACR", NULL, "Right Playback Mux" },
937 { "DACR", NULL, "DACR Sidetone" },
938 { "DACR", NULL, "CLK_DSP" },
939
940 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
941 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
942 { "Left Output Mixer", "DACL Switch", "DACL" },
943 { "Left Output Mixer", "DACR Switch", "DACR" },
944
945 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
946 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
947 { "Right Output Mixer", "DACL Switch", "DACL" },
948 { "Right Output Mixer", "DACR Switch", "DACR" },
949
950 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
951 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
952 { "Left Speaker Mixer", "DACL Switch", "DACL" },
953 { "Left Speaker Mixer", "DACR Switch", "DACR" },
954
955 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
956 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
957 { "Right Speaker Mixer", "DACL Switch", "DACL" },
958 { "Right Speaker Mixer", "DACR Switch", "DACR" },
959
960 { "Left Line Output PGA", NULL, "Left Output Mixer" },
961 { "Right Line Output PGA", NULL, "Right Output Mixer" },
962
963 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
964 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
965
966 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
967 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
968
969 { "HPL_ENA_DLY", NULL, "Left Headphone Output PGA" },
970 { "HPR_ENA_DLY", NULL, "Right Headphone Output PGA" },
971 { "LINEOUTL_ENA_DLY", NULL, "Left Line Output PGA" },
972 { "LINEOUTR_ENA_DLY", NULL, "Right Line Output PGA" },
973
974 { "HPL_DCS", NULL, "HPL_ENA_DLY" },
975 { "HPR_DCS", NULL, "HPR_ENA_DLY" },
976 { "LINEOUTL_DCS", NULL, "LINEOUTL_ENA_DLY" },
977 { "LINEOUTR_DCS", NULL, "LINEOUTR_ENA_DLY" },
978
979 { "HPL_ENA_OUTP", NULL, "HPL_DCS" },
980 { "HPR_ENA_OUTP", NULL, "HPR_DCS" },
981 { "LINEOUTL_ENA_OUTP", NULL, "LINEOUTL_DCS" },
982 { "LINEOUTR_ENA_OUTP", NULL, "LINEOUTR_DCS" },
983
984 { "HPL_RMV_SHORT", NULL, "HPL_ENA_OUTP" },
985 { "HPR_RMV_SHORT", NULL, "HPR_ENA_OUTP" },
986 { "LINEOUTL_RMV_SHORT", NULL, "LINEOUTL_ENA_OUTP" },
987 { "LINEOUTR_RMV_SHORT", NULL, "LINEOUTR_ENA_OUTP" },
988
989 { "HPOUTL", NULL, "HPL_RMV_SHORT" },
990 { "HPOUTR", NULL, "HPR_RMV_SHORT" },
991 { "LINEOUTL", NULL, "LINEOUTL_RMV_SHORT" },
992 { "LINEOUTR", NULL, "LINEOUTR_RMV_SHORT" },
993
994 { "LOP", NULL, "Left Speaker PGA" },
995 { "LON", NULL, "Left Speaker PGA" },
996
997 { "ROP", NULL, "Right Speaker PGA" },
998 { "RON", NULL, "Right Speaker PGA" },
999
1000 { "Left Headphone Output PGA", NULL, "Charge Pump" },
1001 { "Right Headphone Output PGA", NULL, "Charge Pump" },
1002 { "Left Line Output PGA", NULL, "Charge Pump" },
1003 { "Right Line Output PGA", NULL, "Charge Pump" },
1004 };
1005
1006 static int wm8903_add_widgets(struct snd_soc_codec *codec)
1007 {
1008 struct snd_soc_dapm_context *dapm = &codec->dapm;
1009
1010 snd_soc_dapm_new_controls(dapm, wm8903_dapm_widgets,
1011 ARRAY_SIZE(wm8903_dapm_widgets));
1012 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
1013
1014 return 0;
1015 }
1016
1017 static int wm8903_set_bias_level(struct snd_soc_codec *codec,
1018 enum snd_soc_bias_level level)
1019 {
1020 u16 reg;
1021
1022 switch (level) {
1023 case SND_SOC_BIAS_ON:
1024 case SND_SOC_BIAS_PREPARE:
1025 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
1026 reg &= ~(WM8903_VMID_RES_MASK);
1027 reg |= WM8903_VMID_RES_50K;
1028 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
1029 break;
1030
1031 case SND_SOC_BIAS_STANDBY:
1032 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1033 snd_soc_write(codec, WM8903_CLOCK_RATES_2,
1034 WM8903_CLK_SYS_ENA);
1035
1036 /* Change DC servo dither level in startup sequence */
1037 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11);
1038 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257);
1039 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2);
1040
1041 wm8903_run_sequence(codec, 0);
1042 wm8903_sync_reg_cache(codec, codec->reg_cache);
1043
1044 /* By default no bypass paths are enabled so
1045 * enable Class W support.
1046 */
1047 dev_dbg(codec->dev, "Enabling Class W\n");
1048 snd_soc_update_bits(codec, WM8903_CLASS_W_0,
1049 WM8903_CP_DYN_FREQ |
1050 WM8903_CP_DYN_V,
1051 WM8903_CP_DYN_FREQ |
1052 WM8903_CP_DYN_V);
1053 }
1054
1055 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
1056 reg &= ~(WM8903_VMID_RES_MASK);
1057 reg |= WM8903_VMID_RES_250K;
1058 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
1059 break;
1060
1061 case SND_SOC_BIAS_OFF:
1062 wm8903_run_sequence(codec, 32);
1063 reg = snd_soc_read(codec, WM8903_CLOCK_RATES_2);
1064 reg &= ~WM8903_CLK_SYS_ENA;
1065 snd_soc_write(codec, WM8903_CLOCK_RATES_2, reg);
1066 break;
1067 }
1068
1069 codec->dapm.bias_level = level;
1070
1071 return 0;
1072 }
1073
1074 static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1075 int clk_id, unsigned int freq, int dir)
1076 {
1077 struct snd_soc_codec *codec = codec_dai->codec;
1078 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1079
1080 wm8903->sysclk = freq;
1081
1082 return 0;
1083 }
1084
1085 static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1086 unsigned int fmt)
1087 {
1088 struct snd_soc_codec *codec = codec_dai->codec;
1089 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1090
1091 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1092 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1093
1094 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1095 case SND_SOC_DAIFMT_CBS_CFS:
1096 break;
1097 case SND_SOC_DAIFMT_CBS_CFM:
1098 aif1 |= WM8903_LRCLK_DIR;
1099 break;
1100 case SND_SOC_DAIFMT_CBM_CFM:
1101 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1102 break;
1103 case SND_SOC_DAIFMT_CBM_CFS:
1104 aif1 |= WM8903_BCLK_DIR;
1105 break;
1106 default:
1107 return -EINVAL;
1108 }
1109
1110 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1111 case SND_SOC_DAIFMT_DSP_A:
1112 aif1 |= 0x3;
1113 break;
1114 case SND_SOC_DAIFMT_DSP_B:
1115 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1116 break;
1117 case SND_SOC_DAIFMT_I2S:
1118 aif1 |= 0x2;
1119 break;
1120 case SND_SOC_DAIFMT_RIGHT_J:
1121 aif1 |= 0x1;
1122 break;
1123 case SND_SOC_DAIFMT_LEFT_J:
1124 break;
1125 default:
1126 return -EINVAL;
1127 }
1128
1129 /* Clock inversion */
1130 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1131 case SND_SOC_DAIFMT_DSP_A:
1132 case SND_SOC_DAIFMT_DSP_B:
1133 /* frame inversion not valid for DSP modes */
1134 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1135 case SND_SOC_DAIFMT_NB_NF:
1136 break;
1137 case SND_SOC_DAIFMT_IB_NF:
1138 aif1 |= WM8903_AIF_BCLK_INV;
1139 break;
1140 default:
1141 return -EINVAL;
1142 }
1143 break;
1144 case SND_SOC_DAIFMT_I2S:
1145 case SND_SOC_DAIFMT_RIGHT_J:
1146 case SND_SOC_DAIFMT_LEFT_J:
1147 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1148 case SND_SOC_DAIFMT_NB_NF:
1149 break;
1150 case SND_SOC_DAIFMT_IB_IF:
1151 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1152 break;
1153 case SND_SOC_DAIFMT_IB_NF:
1154 aif1 |= WM8903_AIF_BCLK_INV;
1155 break;
1156 case SND_SOC_DAIFMT_NB_IF:
1157 aif1 |= WM8903_AIF_LRCLK_INV;
1158 break;
1159 default:
1160 return -EINVAL;
1161 }
1162 break;
1163 default:
1164 return -EINVAL;
1165 }
1166
1167 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1168
1169 return 0;
1170 }
1171
1172 static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1173 {
1174 struct snd_soc_codec *codec = codec_dai->codec;
1175 u16 reg;
1176
1177 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
1178
1179 if (mute)
1180 reg |= WM8903_DAC_MUTE;
1181 else
1182 reg &= ~WM8903_DAC_MUTE;
1183
1184 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
1185
1186 return 0;
1187 }
1188
1189 /* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1190 * for optimal performance so we list the lower rates first and match
1191 * on the last match we find. */
1192 static struct {
1193 int div;
1194 int rate;
1195 int mode;
1196 int mclk_div;
1197 } clk_sys_ratios[] = {
1198 { 64, 0x0, 0x0, 1 },
1199 { 68, 0x0, 0x1, 1 },
1200 { 125, 0x0, 0x2, 1 },
1201 { 128, 0x1, 0x0, 1 },
1202 { 136, 0x1, 0x1, 1 },
1203 { 192, 0x2, 0x0, 1 },
1204 { 204, 0x2, 0x1, 1 },
1205
1206 { 64, 0x0, 0x0, 2 },
1207 { 68, 0x0, 0x1, 2 },
1208 { 125, 0x0, 0x2, 2 },
1209 { 128, 0x1, 0x0, 2 },
1210 { 136, 0x1, 0x1, 2 },
1211 { 192, 0x2, 0x0, 2 },
1212 { 204, 0x2, 0x1, 2 },
1213
1214 { 250, 0x2, 0x2, 1 },
1215 { 256, 0x3, 0x0, 1 },
1216 { 272, 0x3, 0x1, 1 },
1217 { 384, 0x4, 0x0, 1 },
1218 { 408, 0x4, 0x1, 1 },
1219 { 375, 0x4, 0x2, 1 },
1220 { 512, 0x5, 0x0, 1 },
1221 { 544, 0x5, 0x1, 1 },
1222 { 500, 0x5, 0x2, 1 },
1223 { 768, 0x6, 0x0, 1 },
1224 { 816, 0x6, 0x1, 1 },
1225 { 750, 0x6, 0x2, 1 },
1226 { 1024, 0x7, 0x0, 1 },
1227 { 1088, 0x7, 0x1, 1 },
1228 { 1000, 0x7, 0x2, 1 },
1229 { 1408, 0x8, 0x0, 1 },
1230 { 1496, 0x8, 0x1, 1 },
1231 { 1536, 0x9, 0x0, 1 },
1232 { 1632, 0x9, 0x1, 1 },
1233 { 1500, 0x9, 0x2, 1 },
1234
1235 { 250, 0x2, 0x2, 2 },
1236 { 256, 0x3, 0x0, 2 },
1237 { 272, 0x3, 0x1, 2 },
1238 { 384, 0x4, 0x0, 2 },
1239 { 408, 0x4, 0x1, 2 },
1240 { 375, 0x4, 0x2, 2 },
1241 { 512, 0x5, 0x0, 2 },
1242 { 544, 0x5, 0x1, 2 },
1243 { 500, 0x5, 0x2, 2 },
1244 { 768, 0x6, 0x0, 2 },
1245 { 816, 0x6, 0x1, 2 },
1246 { 750, 0x6, 0x2, 2 },
1247 { 1024, 0x7, 0x0, 2 },
1248 { 1088, 0x7, 0x1, 2 },
1249 { 1000, 0x7, 0x2, 2 },
1250 { 1408, 0x8, 0x0, 2 },
1251 { 1496, 0x8, 0x1, 2 },
1252 { 1536, 0x9, 0x0, 2 },
1253 { 1632, 0x9, 0x1, 2 },
1254 { 1500, 0x9, 0x2, 2 },
1255 };
1256
1257 /* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1258 static struct {
1259 int ratio;
1260 int div;
1261 } bclk_divs[] = {
1262 { 10, 0 },
1263 { 20, 2 },
1264 { 30, 3 },
1265 { 40, 4 },
1266 { 50, 5 },
1267 { 60, 7 },
1268 { 80, 8 },
1269 { 100, 9 },
1270 { 120, 11 },
1271 { 160, 12 },
1272 { 200, 13 },
1273 { 220, 14 },
1274 { 240, 15 },
1275 { 300, 17 },
1276 { 320, 18 },
1277 { 440, 19 },
1278 { 480, 20 },
1279 };
1280
1281 /* Sample rates for DSP */
1282 static struct {
1283 int rate;
1284 int value;
1285 } sample_rates[] = {
1286 { 8000, 0 },
1287 { 11025, 1 },
1288 { 12000, 2 },
1289 { 16000, 3 },
1290 { 22050, 4 },
1291 { 24000, 5 },
1292 { 32000, 6 },
1293 { 44100, 7 },
1294 { 48000, 8 },
1295 { 88200, 9 },
1296 { 96000, 10 },
1297 { 0, 0 },
1298 };
1299
1300 static int wm8903_hw_params(struct snd_pcm_substream *substream,
1301 struct snd_pcm_hw_params *params,
1302 struct snd_soc_dai *dai)
1303 {
1304 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1305 struct snd_soc_codec *codec =rtd->codec;
1306 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1307 int fs = params_rate(params);
1308 int bclk;
1309 int bclk_div;
1310 int i;
1311 int dsp_config;
1312 int clk_config;
1313 int best_val;
1314 int cur_val;
1315 int clk_sys;
1316
1317 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1318 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1319 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1320 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1321 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1322 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
1323
1324 /* Enable sloping stopband filter for low sample rates */
1325 if (fs <= 24000)
1326 dac_digital1 |= WM8903_DAC_SB_FILT;
1327 else
1328 dac_digital1 &= ~WM8903_DAC_SB_FILT;
1329
1330 /* Configure sample rate logic for DSP - choose nearest rate */
1331 dsp_config = 0;
1332 best_val = abs(sample_rates[dsp_config].rate - fs);
1333 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1334 cur_val = abs(sample_rates[i].rate - fs);
1335 if (cur_val <= best_val) {
1336 dsp_config = i;
1337 best_val = cur_val;
1338 }
1339 }
1340
1341 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
1342 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1343 clock1 |= sample_rates[dsp_config].value;
1344
1345 aif1 &= ~WM8903_AIF_WL_MASK;
1346 bclk = 2 * fs;
1347 switch (params_format(params)) {
1348 case SNDRV_PCM_FORMAT_S16_LE:
1349 bclk *= 16;
1350 break;
1351 case SNDRV_PCM_FORMAT_S20_3LE:
1352 bclk *= 20;
1353 aif1 |= 0x4;
1354 break;
1355 case SNDRV_PCM_FORMAT_S24_LE:
1356 bclk *= 24;
1357 aif1 |= 0x8;
1358 break;
1359 case SNDRV_PCM_FORMAT_S32_LE:
1360 bclk *= 32;
1361 aif1 |= 0xc;
1362 break;
1363 default:
1364 return -EINVAL;
1365 }
1366
1367 dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n",
1368 wm8903->sysclk, fs);
1369
1370 /* We may not have an MCLK which allows us to generate exactly
1371 * the clock we want, particularly with USB derived inputs, so
1372 * approximate.
1373 */
1374 clk_config = 0;
1375 best_val = abs((wm8903->sysclk /
1376 (clk_sys_ratios[0].mclk_div *
1377 clk_sys_ratios[0].div)) - fs);
1378 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1379 cur_val = abs((wm8903->sysclk /
1380 (clk_sys_ratios[i].mclk_div *
1381 clk_sys_ratios[i].div)) - fs);
1382
1383 if (cur_val <= best_val) {
1384 clk_config = i;
1385 best_val = cur_val;
1386 }
1387 }
1388
1389 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1390 clock0 |= WM8903_MCLKDIV2;
1391 clk_sys = wm8903->sysclk / 2;
1392 } else {
1393 clock0 &= ~WM8903_MCLKDIV2;
1394 clk_sys = wm8903->sysclk;
1395 }
1396
1397 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1398 WM8903_CLK_SYS_MODE_MASK);
1399 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1400 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1401
1402 dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
1403 clk_sys_ratios[clk_config].rate,
1404 clk_sys_ratios[clk_config].mode,
1405 clk_sys_ratios[clk_config].div);
1406
1407 dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
1408
1409 /* We may not get quite the right frequency if using
1410 * approximate clocks so look for the closest match that is
1411 * higher than the target (we need to ensure that there enough
1412 * BCLKs to clock out the samples).
1413 */
1414 bclk_div = 0;
1415 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1416 i = 1;
1417 while (i < ARRAY_SIZE(bclk_divs)) {
1418 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1419 if (cur_val < 0) /* BCLK table is sorted */
1420 break;
1421 bclk_div = i;
1422 best_val = cur_val;
1423 i++;
1424 }
1425
1426 aif2 &= ~WM8903_BCLK_DIV_MASK;
1427 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1428
1429 dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
1430 bclk_divs[bclk_div].ratio / 10, bclk,
1431 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1432
1433 aif2 |= bclk_divs[bclk_div].div;
1434 aif3 |= bclk / fs;
1435
1436 wm8903->fs = params_rate(params);
1437 wm8903_set_deemph(codec);
1438
1439 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1440 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1441 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1442 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1443 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1444 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
1445
1446 return 0;
1447 }
1448
1449 /**
1450 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1451 *
1452 * @codec: WM8903 codec
1453 * @jack: jack to report detection events on
1454 * @det: value to report for presence detection
1455 * @shrt: value to report for short detection
1456 *
1457 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1458 * being used to bring out signals to the processor then only platform
1459 * data configuration is needed for WM8903 and processor GPIOs should
1460 * be configured using snd_soc_jack_add_gpios() instead.
1461 *
1462 * The current threasholds for detection should be configured using
1463 * micdet_cfg in the platform data. Using this function will force on
1464 * the microphone bias for the device.
1465 */
1466 int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
1467 int det, int shrt)
1468 {
1469 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1470 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;
1471
1472 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n",
1473 det, shrt);
1474
1475 /* Store the configuration */
1476 wm8903->mic_jack = jack;
1477 wm8903->mic_det = det;
1478 wm8903->mic_short = shrt;
1479
1480 /* Enable interrupts we've got a report configured for */
1481 if (det)
1482 irq_mask &= ~WM8903_MICDET_EINT;
1483 if (shrt)
1484 irq_mask &= ~WM8903_MICSHRT_EINT;
1485
1486 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1487 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
1488 irq_mask);
1489
1490 if (det && shrt) {
1491 /* Enable mic detection, this may not have been set through
1492 * platform data (eg, if the defaults are OK). */
1493 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1494 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1495 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1496 WM8903_MICDET_ENA, WM8903_MICDET_ENA);
1497 } else {
1498 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1499 WM8903_MICDET_ENA, 0);
1500 }
1501
1502 return 0;
1503 }
1504 EXPORT_SYMBOL_GPL(wm8903_mic_detect);
1505
1506 static irqreturn_t wm8903_irq(int irq, void *data)
1507 {
1508 struct snd_soc_codec *codec = data;
1509 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1510 int mic_report;
1511 int int_pol;
1512 int int_val = 0;
1513 int mask = ~snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1_MASK);
1514
1515 int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask;
1516
1517 if (int_val & WM8903_WSEQ_BUSY_EINT) {
1518 dev_dbg(codec->dev, "Write sequencer done\n");
1519 complete(&wm8903->wseq);
1520 }
1521
1522 /*
1523 * The rest is microphone jack detection. We need to manually
1524 * invert the polarity of the interrupt after each event - to
1525 * simplify the code keep track of the last state we reported
1526 * and just invert the relevant bits in both the report and
1527 * the polarity register.
1528 */
1529 mic_report = wm8903->mic_last_report;
1530 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1);
1531
1532 #ifndef CONFIG_SND_SOC_WM8903_MODULE
1533 if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT))
1534 trace_snd_soc_jack_irq(dev_name(codec->dev));
1535 #endif
1536
1537 if (int_val & WM8903_MICSHRT_EINT) {
1538 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol);
1539
1540 mic_report ^= wm8903->mic_short;
1541 int_pol ^= WM8903_MICSHRT_INV;
1542 }
1543
1544 if (int_val & WM8903_MICDET_EINT) {
1545 dev_dbg(codec->dev, "Microphone detect (pol=%x)\n", int_pol);
1546
1547 mic_report ^= wm8903->mic_det;
1548 int_pol ^= WM8903_MICDET_INV;
1549
1550 msleep(wm8903->mic_delay);
1551 }
1552
1553 snd_soc_update_bits(codec, WM8903_INTERRUPT_POLARITY_1,
1554 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
1555
1556 snd_soc_jack_report(wm8903->mic_jack, mic_report,
1557 wm8903->mic_short | wm8903->mic_det);
1558
1559 wm8903->mic_last_report = mic_report;
1560
1561 return IRQ_HANDLED;
1562 }
1563
1564 #define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1565 SNDRV_PCM_RATE_11025 | \
1566 SNDRV_PCM_RATE_16000 | \
1567 SNDRV_PCM_RATE_22050 | \
1568 SNDRV_PCM_RATE_32000 | \
1569 SNDRV_PCM_RATE_44100 | \
1570 SNDRV_PCM_RATE_48000 | \
1571 SNDRV_PCM_RATE_88200 | \
1572 SNDRV_PCM_RATE_96000)
1573
1574 #define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1575 SNDRV_PCM_RATE_11025 | \
1576 SNDRV_PCM_RATE_16000 | \
1577 SNDRV_PCM_RATE_22050 | \
1578 SNDRV_PCM_RATE_32000 | \
1579 SNDRV_PCM_RATE_44100 | \
1580 SNDRV_PCM_RATE_48000)
1581
1582 #define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1583 SNDRV_PCM_FMTBIT_S20_3LE |\
1584 SNDRV_PCM_FMTBIT_S24_LE)
1585
1586 static struct snd_soc_dai_ops wm8903_dai_ops = {
1587 .hw_params = wm8903_hw_params,
1588 .digital_mute = wm8903_digital_mute,
1589 .set_fmt = wm8903_set_dai_fmt,
1590 .set_sysclk = wm8903_set_dai_sysclk,
1591 };
1592
1593 static struct snd_soc_dai_driver wm8903_dai = {
1594 .name = "wm8903-hifi",
1595 .playback = {
1596 .stream_name = "Playback",
1597 .channels_min = 2,
1598 .channels_max = 2,
1599 .rates = WM8903_PLAYBACK_RATES,
1600 .formats = WM8903_FORMATS,
1601 },
1602 .capture = {
1603 .stream_name = "Capture",
1604 .channels_min = 2,
1605 .channels_max = 2,
1606 .rates = WM8903_CAPTURE_RATES,
1607 .formats = WM8903_FORMATS,
1608 },
1609 .ops = &wm8903_dai_ops,
1610 .symmetric_rates = 1,
1611 };
1612
1613 static int wm8903_suspend(struct snd_soc_codec *codec, pm_message_t state)
1614 {
1615 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1616
1617 return 0;
1618 }
1619
1620 static int wm8903_resume(struct snd_soc_codec *codec)
1621 {
1622 int i;
1623 u16 *reg_cache = codec->reg_cache;
1624 u16 *tmp_cache = kmemdup(reg_cache, sizeof(wm8903_reg_defaults),
1625 GFP_KERNEL);
1626
1627 /* Bring the codec back up to standby first to minimise pop/clicks */
1628 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1629
1630 /* Sync back everything else */
1631 if (tmp_cache) {
1632 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
1633 if (tmp_cache[i] != reg_cache[i])
1634 snd_soc_write(codec, i, tmp_cache[i]);
1635 kfree(tmp_cache);
1636 } else {
1637 dev_err(codec->dev, "Failed to allocate temporary cache\n");
1638 }
1639
1640 return 0;
1641 }
1642
1643 #ifdef CONFIG_GPIOLIB
1644 static inline struct wm8903_priv *gpio_to_wm8903(struct gpio_chip *chip)
1645 {
1646 return container_of(chip, struct wm8903_priv, gpio_chip);
1647 }
1648
1649 static int wm8903_gpio_request(struct gpio_chip *chip, unsigned offset)
1650 {
1651 if (offset >= WM8903_NUM_GPIO)
1652 return -EINVAL;
1653
1654 return 0;
1655 }
1656
1657 static int wm8903_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
1658 {
1659 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1660 struct snd_soc_codec *codec = wm8903->codec;
1661 unsigned int mask, val;
1662
1663 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK;
1664 val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) |
1665 WM8903_GP1_DIR;
1666
1667 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1668 mask, val);
1669 }
1670
1671 static int wm8903_gpio_get(struct gpio_chip *chip, unsigned offset)
1672 {
1673 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1674 struct snd_soc_codec *codec = wm8903->codec;
1675 int reg;
1676
1677 reg = snd_soc_read(codec, WM8903_GPIO_CONTROL_1 + offset);
1678
1679 return (reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT;
1680 }
1681
1682 static int wm8903_gpio_direction_out(struct gpio_chip *chip,
1683 unsigned offset, int value)
1684 {
1685 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1686 struct snd_soc_codec *codec = wm8903->codec;
1687 unsigned int mask, val;
1688
1689 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK;
1690 val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) |
1691 (value << WM8903_GP2_LVL_SHIFT);
1692
1693 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1694 mask, val);
1695 }
1696
1697 static void wm8903_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1698 {
1699 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1700 struct snd_soc_codec *codec = wm8903->codec;
1701
1702 snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1703 WM8903_GP1_LVL_MASK,
1704 !!value << WM8903_GP1_LVL_SHIFT);
1705 }
1706
1707 static struct gpio_chip wm8903_template_chip = {
1708 .label = "wm8903",
1709 .owner = THIS_MODULE,
1710 .request = wm8903_gpio_request,
1711 .direction_input = wm8903_gpio_direction_in,
1712 .get = wm8903_gpio_get,
1713 .direction_output = wm8903_gpio_direction_out,
1714 .set = wm8903_gpio_set,
1715 .can_sleep = 1,
1716 };
1717
1718 static void wm8903_init_gpio(struct snd_soc_codec *codec)
1719 {
1720 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1721 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1722 int ret;
1723
1724 wm8903->gpio_chip = wm8903_template_chip;
1725 wm8903->gpio_chip.ngpio = WM8903_NUM_GPIO;
1726 wm8903->gpio_chip.dev = codec->dev;
1727
1728 if (pdata && pdata->gpio_base)
1729 wm8903->gpio_chip.base = pdata->gpio_base;
1730 else
1731 wm8903->gpio_chip.base = -1;
1732
1733 ret = gpiochip_add(&wm8903->gpio_chip);
1734 if (ret != 0)
1735 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
1736 }
1737
1738 static void wm8903_free_gpio(struct snd_soc_codec *codec)
1739 {
1740 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1741 int ret;
1742
1743 ret = gpiochip_remove(&wm8903->gpio_chip);
1744 if (ret != 0)
1745 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
1746 }
1747 #else
1748 static void wm8903_init_gpio(struct snd_soc_codec *codec)
1749 {
1750 }
1751
1752 static void wm8903_free_gpio(struct snd_soc_codec *codec)
1753 {
1754 }
1755 #endif
1756
1757 static int wm8903_probe(struct snd_soc_codec *codec)
1758 {
1759 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1760 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1761 int ret, i;
1762 int trigger, irq_pol;
1763 u16 val;
1764
1765 wm8903->codec = codec;
1766 init_completion(&wm8903->wseq);
1767
1768 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1769 if (ret != 0) {
1770 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1771 return ret;
1772 }
1773
1774 val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID);
1775 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
1776 dev_err(codec->dev,
1777 "Device with ID register %x is not a WM8903\n", val);
1778 return -ENODEV;
1779 }
1780
1781 val = snd_soc_read(codec, WM8903_REVISION_NUMBER);
1782 dev_info(codec->dev, "WM8903 revision %c\n",
1783 (val & WM8903_CHIP_REV_MASK) + 'A');
1784
1785 wm8903_reset(codec);
1786
1787 /* Set up GPIOs and microphone detection */
1788 if (pdata) {
1789 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
1790 if (pdata->gpio_cfg[i] == WM8903_GPIO_NO_CONFIG)
1791 continue;
1792
1793 snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i,
1794 pdata->gpio_cfg[i] & 0xffff);
1795 }
1796
1797 snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0,
1798 pdata->micdet_cfg);
1799
1800 /* Microphone detection needs the WSEQ clock */
1801 if (pdata->micdet_cfg)
1802 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1803 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1804
1805 wm8903->mic_delay = pdata->micdet_delay;
1806 }
1807
1808 if (wm8903->irq) {
1809 if (pdata && pdata->irq_active_low) {
1810 trigger = IRQF_TRIGGER_LOW;
1811 irq_pol = WM8903_IRQ_POL;
1812 } else {
1813 trigger = IRQF_TRIGGER_HIGH;
1814 irq_pol = 0;
1815 }
1816
1817 snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL,
1818 WM8903_IRQ_POL, irq_pol);
1819
1820 ret = request_threaded_irq(wm8903->irq, NULL, wm8903_irq,
1821 trigger | IRQF_ONESHOT,
1822 "wm8903", codec);
1823 if (ret != 0) {
1824 dev_err(codec->dev, "Failed to request IRQ: %d\n",
1825 ret);
1826 return ret;
1827 }
1828
1829 /* Enable write sequencer interrupts */
1830 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1831 WM8903_IM_WSEQ_BUSY_EINT, 0);
1832 }
1833
1834 /* power on device */
1835 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1836
1837 /* Latch volume update bits */
1838 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
1839 val |= WM8903_ADCVU;
1840 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1841 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
1842
1843 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
1844 val |= WM8903_DACVU;
1845 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
1846 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
1847
1848 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
1849 val |= WM8903_HPOUTVU;
1850 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
1851 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
1852
1853 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
1854 val |= WM8903_LINEOUTVU;
1855 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
1856 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
1857
1858 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
1859 val |= WM8903_SPKVU;
1860 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
1861 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
1862
1863 /* Enable DAC soft mute by default */
1864 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
1865 val |= WM8903_DAC_MUTEMODE;
1866 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, val);
1867
1868 snd_soc_add_controls(codec, wm8903_snd_controls,
1869 ARRAY_SIZE(wm8903_snd_controls));
1870 wm8903_add_widgets(codec);
1871
1872 wm8903_init_gpio(codec);
1873
1874 return ret;
1875 }
1876
1877 /* power down chip */
1878 static int wm8903_remove(struct snd_soc_codec *codec)
1879 {
1880 wm8903_free_gpio(codec);
1881 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1882 return 0;
1883 }
1884
1885 static struct snd_soc_codec_driver soc_codec_dev_wm8903 = {
1886 .probe = wm8903_probe,
1887 .remove = wm8903_remove,
1888 .suspend = wm8903_suspend,
1889 .resume = wm8903_resume,
1890 .set_bias_level = wm8903_set_bias_level,
1891 .reg_cache_size = ARRAY_SIZE(wm8903_reg_defaults),
1892 .reg_word_size = sizeof(u16),
1893 .reg_cache_default = wm8903_reg_defaults,
1894 .volatile_register = wm8903_volatile_register,
1895 };
1896
1897 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1898 static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
1899 const struct i2c_device_id *id)
1900 {
1901 struct wm8903_priv *wm8903;
1902 int ret;
1903
1904 wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
1905 if (wm8903 == NULL)
1906 return -ENOMEM;
1907
1908 i2c_set_clientdata(i2c, wm8903);
1909 wm8903->irq = i2c->irq;
1910
1911 ret = snd_soc_register_codec(&i2c->dev,
1912 &soc_codec_dev_wm8903, &wm8903_dai, 1);
1913 if (ret < 0)
1914 kfree(wm8903);
1915 return ret;
1916 }
1917
1918 static __devexit int wm8903_i2c_remove(struct i2c_client *client)
1919 {
1920 snd_soc_unregister_codec(&client->dev);
1921 kfree(i2c_get_clientdata(client));
1922 return 0;
1923 }
1924
1925 static const struct i2c_device_id wm8903_i2c_id[] = {
1926 { "wm8903", 0 },
1927 { }
1928 };
1929 MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
1930
1931 static struct i2c_driver wm8903_i2c_driver = {
1932 .driver = {
1933 .name = "wm8903",
1934 .owner = THIS_MODULE,
1935 },
1936 .probe = wm8903_i2c_probe,
1937 .remove = __devexit_p(wm8903_i2c_remove),
1938 .id_table = wm8903_i2c_id,
1939 };
1940 #endif
1941
1942 static int __init wm8903_modinit(void)
1943 {
1944 int ret = 0;
1945 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1946 ret = i2c_add_driver(&wm8903_i2c_driver);
1947 if (ret != 0) {
1948 printk(KERN_ERR "Failed to register wm8903 I2C driver: %d\n",
1949 ret);
1950 }
1951 #endif
1952 return ret;
1953 }
1954 module_init(wm8903_modinit);
1955
1956 static void __exit wm8903_exit(void)
1957 {
1958 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1959 i2c_del_driver(&wm8903_i2c_driver);
1960 #endif
1961 }
1962 module_exit(wm8903_exit);
1963
1964 MODULE_DESCRIPTION("ASoC WM8903 driver");
1965 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
1966 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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