2 * wm8903.c -- WM8903 ALSA SoC Audio driver
4 * Copyright 2008 Wolfson Microelectronics
5 * Copyright 2011 NVIDIA, Inc.
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * - TDM mode configuration.
15 * - Digital microphone support.
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/init.h>
21 #include <linux/completion.h>
22 #include <linux/delay.h>
23 #include <linux/gpio.h>
25 #include <linux/i2c.h>
26 #include <linux/platform_device.h>
27 #include <linux/slab.h>
28 #include <sound/core.h>
29 #include <sound/jack.h>
30 #include <sound/pcm.h>
31 #include <sound/pcm_params.h>
32 #include <sound/tlv.h>
33 #include <sound/soc.h>
34 #include <sound/initval.h>
35 #include <sound/wm8903.h>
36 #include <trace/events/asoc.h>
40 /* Register defaults at reset */
41 static u16 wm8903_reg_defaults
[] = {
42 0x8903, /* R0 - SW Reset and ID */
43 0x0000, /* R1 - Revision Number */
46 0x0018, /* R4 - Bias Control 0 */
47 0x0000, /* R5 - VMID Control 0 */
48 0x0000, /* R6 - Mic Bias Control 0 */
50 0x0001, /* R8 - Analogue DAC 0 */
52 0x0001, /* R10 - Analogue ADC 0 */
54 0x0000, /* R12 - Power Management 0 */
55 0x0000, /* R13 - Power Management 1 */
56 0x0000, /* R14 - Power Management 2 */
57 0x0000, /* R15 - Power Management 3 */
58 0x0000, /* R16 - Power Management 4 */
59 0x0000, /* R17 - Power Management 5 */
60 0x0000, /* R18 - Power Management 6 */
62 0x0400, /* R20 - Clock Rates 0 */
63 0x0D07, /* R21 - Clock Rates 1 */
64 0x0000, /* R22 - Clock Rates 2 */
66 0x0050, /* R24 - Audio Interface 0 */
67 0x0242, /* R25 - Audio Interface 1 */
68 0x0008, /* R26 - Audio Interface 2 */
69 0x0022, /* R27 - Audio Interface 3 */
72 0x00C0, /* R30 - DAC Digital Volume Left */
73 0x00C0, /* R31 - DAC Digital Volume Right */
74 0x0000, /* R32 - DAC Digital 0 */
75 0x0000, /* R33 - DAC Digital 1 */
78 0x00C0, /* R36 - ADC Digital Volume Left */
79 0x00C0, /* R37 - ADC Digital Volume Right */
80 0x0000, /* R38 - ADC Digital 0 */
81 0x0073, /* R39 - Digital Microphone 0 */
82 0x09BF, /* R40 - DRC 0 */
83 0x3241, /* R41 - DRC 1 */
84 0x0020, /* R42 - DRC 2 */
85 0x0000, /* R43 - DRC 3 */
86 0x0085, /* R44 - Analogue Left Input 0 */
87 0x0085, /* R45 - Analogue Right Input 0 */
88 0x0044, /* R46 - Analogue Left Input 1 */
89 0x0044, /* R47 - Analogue Right Input 1 */
92 0x0008, /* R50 - Analogue Left Mix 0 */
93 0x0004, /* R51 - Analogue Right Mix 0 */
94 0x0000, /* R52 - Analogue Spk Mix Left 0 */
95 0x0000, /* R53 - Analogue Spk Mix Left 1 */
96 0x0000, /* R54 - Analogue Spk Mix Right 0 */
97 0x0000, /* R55 - Analogue Spk Mix Right 1 */
99 0x002D, /* R57 - Analogue OUT1 Left */
100 0x002D, /* R58 - Analogue OUT1 Right */
101 0x0039, /* R59 - Analogue OUT2 Left */
102 0x0039, /* R60 - Analogue OUT2 Right */
104 0x0139, /* R62 - Analogue OUT3 Left */
105 0x0139, /* R63 - Analogue OUT3 Right */
107 0x0000, /* R65 - Analogue SPK Output Control 0 */
109 0x0010, /* R67 - DC Servo 0 */
111 0x00A4, /* R69 - DC Servo 2 */
132 0x0000, /* R90 - Analogue HP 0 */
136 0x0000, /* R94 - Analogue Lineout 0 */
140 0x0000, /* R98 - Charge Pump 0 */
146 0x0000, /* R104 - Class W 0 */
150 0x0000, /* R108 - Write Sequencer 0 */
151 0x0000, /* R109 - Write Sequencer 1 */
152 0x0000, /* R110 - Write Sequencer 2 */
153 0x0000, /* R111 - Write Sequencer 3 */
154 0x0000, /* R112 - Write Sequencer 4 */
156 0x0000, /* R114 - Control Interface */
158 0x00A8, /* R116 - GPIO Control 1 */
159 0x00A8, /* R117 - GPIO Control 2 */
160 0x00A8, /* R118 - GPIO Control 3 */
161 0x0220, /* R119 - GPIO Control 4 */
162 0x01A0, /* R120 - GPIO Control 5 */
163 0x0000, /* R121 - Interrupt Status 1 */
164 0xFFFF, /* R122 - Interrupt Status 1 Mask */
165 0x0000, /* R123 - Interrupt Polarity 1 */
168 0x0000, /* R126 - Interrupt Control */
171 0x0000, /* R129 - Control Interface Test 1 */
191 0x6810, /* R149 - Charge Pump Test 1 */
206 0x0028, /* R164 - Clock Rate Test 4 */
214 0x0000, /* R172 - Analogue Output Bias 0 */
218 struct snd_soc_codec
*codec
;
229 /* Reference count */
232 struct snd_soc_jack
*mic_jack
;
238 #ifdef CONFIG_GPIOLIB
239 struct gpio_chip gpio_chip
;
243 static int wm8903_volatile_register(struct snd_soc_codec
*codec
, unsigned int reg
)
246 case WM8903_SW_RESET_AND_ID
:
247 case WM8903_REVISION_NUMBER
:
248 case WM8903_INTERRUPT_STATUS_1
:
249 case WM8903_WRITE_SEQUENCER_4
:
250 case WM8903_DC_SERVO_READBACK_1
:
251 case WM8903_DC_SERVO_READBACK_2
:
252 case WM8903_DC_SERVO_READBACK_3
:
253 case WM8903_DC_SERVO_READBACK_4
:
261 static void wm8903_reset(struct snd_soc_codec
*codec
)
263 snd_soc_write(codec
, WM8903_SW_RESET_AND_ID
, 0);
264 memcpy(codec
->reg_cache
, wm8903_reg_defaults
,
265 sizeof(wm8903_reg_defaults
));
268 static int wm8903_cp_event(struct snd_soc_dapm_widget
*w
,
269 struct snd_kcontrol
*kcontrol
, int event
)
271 WARN_ON(event
!= SND_SOC_DAPM_POST_PMU
);
277 static int wm8903_dcs_event(struct snd_soc_dapm_widget
*w
,
278 struct snd_kcontrol
*kcontrol
, int event
)
280 struct snd_soc_codec
*codec
= w
->codec
;
281 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
284 case SND_SOC_DAPM_POST_PMU
:
285 wm8903
->dcs_pending
|= 1 << w
->shift
;
287 case SND_SOC_DAPM_PRE_PMD
:
288 snd_soc_update_bits(codec
, WM8903_DC_SERVO_0
,
296 #define WM8903_DCS_MODE_WRITE_STOP 0
297 #define WM8903_DCS_MODE_START_STOP 2
299 static void wm8903_seq_notifier(struct snd_soc_dapm_context
*dapm
,
300 enum snd_soc_dapm_type event
, int subseq
)
302 struct snd_soc_codec
*codec
= container_of(dapm
,
303 struct snd_soc_codec
, dapm
);
304 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
305 int dcs_mode
= WM8903_DCS_MODE_WRITE_STOP
;
308 /* Complete any pending DC servo starts */
309 if (wm8903
->dcs_pending
) {
310 dev_dbg(codec
->dev
, "Starting DC servo for %x\n",
311 wm8903
->dcs_pending
);
313 /* If we've no cached values then we need to do startup */
314 for (i
= 0; i
< ARRAY_SIZE(wm8903
->dcs_cache
); i
++) {
315 if (!(wm8903
->dcs_pending
& (1 << i
)))
318 if (wm8903
->dcs_cache
[i
]) {
320 "Restore DC servo %d value %x\n",
321 3 - i
, wm8903
->dcs_cache
[i
]);
323 snd_soc_write(codec
, WM8903_DC_SERVO_4
+ i
,
324 wm8903
->dcs_cache
[i
] & 0xff);
327 "Calibrate DC servo %d\n", 3 - i
);
328 dcs_mode
= WM8903_DCS_MODE_START_STOP
;
332 /* Don't trust the cache for analogue */
333 if (wm8903
->class_w_users
)
334 dcs_mode
= WM8903_DCS_MODE_START_STOP
;
336 snd_soc_update_bits(codec
, WM8903_DC_SERVO_2
,
337 WM8903_DCS_MODE_MASK
, dcs_mode
);
339 snd_soc_update_bits(codec
, WM8903_DC_SERVO_0
,
340 WM8903_DCS_ENA_MASK
, wm8903
->dcs_pending
);
343 case WM8903_DCS_MODE_WRITE_STOP
:
346 case WM8903_DCS_MODE_START_STOP
:
349 /* Cache the measured offsets for digital */
350 if (wm8903
->class_w_users
)
353 for (i
= 0; i
< ARRAY_SIZE(wm8903
->dcs_cache
); i
++) {
354 if (!(wm8903
->dcs_pending
& (1 << i
)))
357 val
= snd_soc_read(codec
,
358 WM8903_DC_SERVO_READBACK_1
+ i
);
359 dev_dbg(codec
->dev
, "DC servo %d: %x\n",
361 wm8903
->dcs_cache
[i
] = val
;
366 pr_warn("DCS mode %d delay not set\n", dcs_mode
);
370 wm8903
->dcs_pending
= 0;
375 * When used with DAC outputs only the WM8903 charge pump supports
376 * operation in class W mode, providing very low power consumption
377 * when used with digital sources. Enable and disable this mode
378 * automatically depending on the mixer configuration.
380 * All the relevant controls are simple switches.
382 static int wm8903_class_w_put(struct snd_kcontrol
*kcontrol
,
383 struct snd_ctl_elem_value
*ucontrol
)
385 struct snd_soc_dapm_widget
*widget
= snd_kcontrol_chip(kcontrol
);
386 struct snd_soc_codec
*codec
= widget
->codec
;
387 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
391 reg
= snd_soc_read(codec
, WM8903_CLASS_W_0
);
393 /* Turn it off if we're about to enable bypass */
394 if (ucontrol
->value
.integer
.value
[0]) {
395 if (wm8903
->class_w_users
== 0) {
396 dev_dbg(codec
->dev
, "Disabling Class W\n");
397 snd_soc_write(codec
, WM8903_CLASS_W_0
, reg
&
398 ~(WM8903_CP_DYN_FREQ
| WM8903_CP_DYN_V
));
400 wm8903
->class_w_users
++;
403 /* Implement the change */
404 ret
= snd_soc_dapm_put_volsw(kcontrol
, ucontrol
);
406 /* If we've just disabled the last bypass path turn Class W on */
407 if (!ucontrol
->value
.integer
.value
[0]) {
408 if (wm8903
->class_w_users
== 1) {
409 dev_dbg(codec
->dev
, "Enabling Class W\n");
410 snd_soc_write(codec
, WM8903_CLASS_W_0
, reg
|
411 WM8903_CP_DYN_FREQ
| WM8903_CP_DYN_V
);
413 wm8903
->class_w_users
--;
416 dev_dbg(codec
->dev
, "Bypass use count now %d\n",
417 wm8903
->class_w_users
);
422 #define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
423 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
424 .info = snd_soc_info_volsw, \
425 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
426 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
429 static int wm8903_deemph
[] = { 0, 32000, 44100, 48000 };
431 static int wm8903_set_deemph(struct snd_soc_codec
*codec
)
433 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
436 /* If we're using deemphasis select the nearest available sample
439 if (wm8903
->deemph
) {
441 for (i
= 2; i
< ARRAY_SIZE(wm8903_deemph
); i
++) {
442 if (abs(wm8903_deemph
[i
] - wm8903
->fs
) <
443 abs(wm8903_deemph
[best
] - wm8903
->fs
))
447 val
= best
<< WM8903_DEEMPH_SHIFT
;
453 dev_dbg(codec
->dev
, "Set deemphasis %d (%dHz)\n",
454 best
, wm8903_deemph
[best
]);
456 return snd_soc_update_bits(codec
, WM8903_DAC_DIGITAL_1
,
457 WM8903_DEEMPH_MASK
, val
);
460 static int wm8903_get_deemph(struct snd_kcontrol
*kcontrol
,
461 struct snd_ctl_elem_value
*ucontrol
)
463 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
464 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
466 ucontrol
->value
.enumerated
.item
[0] = wm8903
->deemph
;
471 static int wm8903_put_deemph(struct snd_kcontrol
*kcontrol
,
472 struct snd_ctl_elem_value
*ucontrol
)
474 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
475 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
476 int deemph
= ucontrol
->value
.enumerated
.item
[0];
482 mutex_lock(&codec
->mutex
);
483 if (wm8903
->deemph
!= deemph
) {
484 wm8903
->deemph
= deemph
;
486 wm8903_set_deemph(codec
);
490 mutex_unlock(&codec
->mutex
);
495 /* ALSA can only do steps of .01dB */
496 static const DECLARE_TLV_DB_SCALE(digital_tlv
, -7200, 75, 1);
498 static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv
, -3600, 300, 0);
499 static const DECLARE_TLV_DB_SCALE(out_tlv
, -5700, 100, 0);
501 static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh
, 0, 75, 0);
502 static const DECLARE_TLV_DB_SCALE(drc_tlv_amp
, -2250, 75, 0);
503 static const DECLARE_TLV_DB_SCALE(drc_tlv_min
, 0, 600, 0);
504 static const DECLARE_TLV_DB_SCALE(drc_tlv_max
, 1200, 600, 0);
505 static const DECLARE_TLV_DB_SCALE(drc_tlv_startup
, -300, 50, 0);
507 static const char *hpf_mode_text
[] = {
508 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
511 static const struct soc_enum hpf_mode
=
512 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0
, 5, 4, hpf_mode_text
);
514 static const char *osr_text
[] = {
515 "Low power", "High performance"
518 static const struct soc_enum adc_osr
=
519 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0
, 0, 2, osr_text
);
521 static const struct soc_enum dac_osr
=
522 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1
, 0, 2, osr_text
);
524 static const char *drc_slope_text
[] = {
525 "1", "1/2", "1/4", "1/8", "1/16", "0"
528 static const struct soc_enum drc_slope_r0
=
529 SOC_ENUM_SINGLE(WM8903_DRC_2
, 3, 6, drc_slope_text
);
531 static const struct soc_enum drc_slope_r1
=
532 SOC_ENUM_SINGLE(WM8903_DRC_2
, 0, 6, drc_slope_text
);
534 static const char *drc_attack_text
[] = {
536 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
537 "46.4ms", "92.8ms", "185.6ms"
540 static const struct soc_enum drc_attack
=
541 SOC_ENUM_SINGLE(WM8903_DRC_1
, 12, 11, drc_attack_text
);
543 static const char *drc_decay_text
[] = {
544 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
548 static const struct soc_enum drc_decay
=
549 SOC_ENUM_SINGLE(WM8903_DRC_1
, 8, 9, drc_decay_text
);
551 static const char *drc_ff_delay_text
[] = {
552 "5 samples", "9 samples"
555 static const struct soc_enum drc_ff_delay
=
556 SOC_ENUM_SINGLE(WM8903_DRC_0
, 5, 2, drc_ff_delay_text
);
558 static const char *drc_qr_decay_text
[] = {
559 "0.725ms", "1.45ms", "5.8ms"
562 static const struct soc_enum drc_qr_decay
=
563 SOC_ENUM_SINGLE(WM8903_DRC_1
, 4, 3, drc_qr_decay_text
);
565 static const char *drc_smoothing_text
[] = {
566 "Low", "Medium", "High"
569 static const struct soc_enum drc_smoothing
=
570 SOC_ENUM_SINGLE(WM8903_DRC_0
, 11, 3, drc_smoothing_text
);
572 static const char *soft_mute_text
[] = {
573 "Fast (fs/2)", "Slow (fs/32)"
576 static const struct soc_enum soft_mute
=
577 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1
, 10, 2, soft_mute_text
);
579 static const char *mute_mode_text
[] = {
583 static const struct soc_enum mute_mode
=
584 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1
, 9, 2, mute_mode_text
);
586 static const char *companding_text
[] = {
590 static const struct soc_enum dac_companding
=
591 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 0, 2, companding_text
);
593 static const struct soc_enum adc_companding
=
594 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 2, 2, companding_text
);
596 static const char *input_mode_text
[] = {
597 "Single-Ended", "Differential Line", "Differential Mic"
600 static const struct soc_enum linput_mode_enum
=
601 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1
, 0, 3, input_mode_text
);
603 static const struct soc_enum rinput_mode_enum
=
604 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1
, 0, 3, input_mode_text
);
606 static const char *linput_mux_text
[] = {
607 "IN1L", "IN2L", "IN3L"
610 static const struct soc_enum linput_enum
=
611 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1
, 2, 3, linput_mux_text
);
613 static const struct soc_enum linput_inv_enum
=
614 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1
, 4, 3, linput_mux_text
);
616 static const char *rinput_mux_text
[] = {
617 "IN1R", "IN2R", "IN3R"
620 static const struct soc_enum rinput_enum
=
621 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1
, 2, 3, rinput_mux_text
);
623 static const struct soc_enum rinput_inv_enum
=
624 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1
, 4, 3, rinput_mux_text
);
627 static const char *sidetone_text
[] = {
628 "None", "Left", "Right"
631 static const struct soc_enum lsidetone_enum
=
632 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0
, 2, 3, sidetone_text
);
634 static const struct soc_enum rsidetone_enum
=
635 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0
, 0, 3, sidetone_text
);
637 static const char *aif_text
[] = {
641 static const struct soc_enum lcapture_enum
=
642 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 7, 2, aif_text
);
644 static const struct soc_enum rcapture_enum
=
645 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 6, 2, aif_text
);
647 static const struct soc_enum lplay_enum
=
648 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 5, 2, aif_text
);
650 static const struct soc_enum rplay_enum
=
651 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 4, 2, aif_text
);
653 static const struct snd_kcontrol_new wm8903_snd_controls
[] = {
655 /* Input PGAs - No TLV since the scale depends on PGA mode */
656 SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0
,
658 SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0
,
660 SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1
,
663 SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0
,
665 SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0
,
667 SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1
,
671 SOC_ENUM("ADC OSR", adc_osr
),
672 SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0
, 4, 1, 0),
673 SOC_ENUM("HPF Mode", hpf_mode
),
674 SOC_SINGLE("DRC Switch", WM8903_DRC_0
, 15, 1, 0),
675 SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0
),
676 SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1
),
677 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3
, 5, 124, 1,
679 SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3
, 0, 30, 1, drc_tlv_amp
),
680 SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1
, 2, 3, 1, drc_tlv_min
),
681 SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1
, 0, 3, 0, drc_tlv_max
),
682 SOC_ENUM("DRC Attack Rate", drc_attack
),
683 SOC_ENUM("DRC Decay Rate", drc_decay
),
684 SOC_ENUM("DRC FF Delay", drc_ff_delay
),
685 SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0
, 1, 1, 0),
686 SOC_SINGLE("DRC QR Switch", WM8903_DRC_0
, 2, 1, 0),
687 SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0
, 6, 3, 0, drc_tlv_max
),
688 SOC_ENUM("DRC QR Decay Rate", drc_qr_decay
),
689 SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0
, 3, 1, 0),
690 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0
, 0, 1, 0),
691 SOC_ENUM("DRC Smoothing Threshold", drc_smoothing
),
692 SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0
, 6, 18, 0, drc_tlv_startup
),
694 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT
,
695 WM8903_ADC_DIGITAL_VOLUME_RIGHT
, 1, 96, 0, digital_tlv
),
696 SOC_ENUM("ADC Companding Mode", adc_companding
),
697 SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0
, 3, 1, 0),
699 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0
, 4, 8,
700 12, 0, digital_sidetone_tlv
),
703 SOC_ENUM("DAC OSR", dac_osr
),
704 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT
,
705 WM8903_DAC_DIGITAL_VOLUME_RIGHT
, 1, 120, 0, digital_tlv
),
706 SOC_ENUM("DAC Soft Mute Rate", soft_mute
),
707 SOC_ENUM("DAC Mute Mode", mute_mode
),
708 SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1
, 12, 1, 0),
709 SOC_ENUM("DAC Companding Mode", dac_companding
),
710 SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0
, 1, 1, 0),
711 SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
712 wm8903_get_deemph
, wm8903_put_deemph
),
715 SOC_DOUBLE_R("Headphone Switch",
716 WM8903_ANALOGUE_OUT1_LEFT
, WM8903_ANALOGUE_OUT1_RIGHT
,
718 SOC_DOUBLE_R("Headphone ZC Switch",
719 WM8903_ANALOGUE_OUT1_LEFT
, WM8903_ANALOGUE_OUT1_RIGHT
,
721 SOC_DOUBLE_R_TLV("Headphone Volume",
722 WM8903_ANALOGUE_OUT1_LEFT
, WM8903_ANALOGUE_OUT1_RIGHT
,
726 SOC_DOUBLE_R("Line Out Switch",
727 WM8903_ANALOGUE_OUT2_LEFT
, WM8903_ANALOGUE_OUT2_RIGHT
,
729 SOC_DOUBLE_R("Line Out ZC Switch",
730 WM8903_ANALOGUE_OUT2_LEFT
, WM8903_ANALOGUE_OUT2_RIGHT
,
732 SOC_DOUBLE_R_TLV("Line Out Volume",
733 WM8903_ANALOGUE_OUT2_LEFT
, WM8903_ANALOGUE_OUT2_RIGHT
,
737 SOC_DOUBLE_R("Speaker Switch",
738 WM8903_ANALOGUE_OUT3_LEFT
, WM8903_ANALOGUE_OUT3_RIGHT
, 8, 1, 1),
739 SOC_DOUBLE_R("Speaker ZC Switch",
740 WM8903_ANALOGUE_OUT3_LEFT
, WM8903_ANALOGUE_OUT3_RIGHT
, 6, 1, 0),
741 SOC_DOUBLE_R_TLV("Speaker Volume",
742 WM8903_ANALOGUE_OUT3_LEFT
, WM8903_ANALOGUE_OUT3_RIGHT
,
746 static const struct snd_kcontrol_new linput_mode_mux
=
747 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum
);
749 static const struct snd_kcontrol_new rinput_mode_mux
=
750 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum
);
752 static const struct snd_kcontrol_new linput_mux
=
753 SOC_DAPM_ENUM("Left Input Mux", linput_enum
);
755 static const struct snd_kcontrol_new linput_inv_mux
=
756 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum
);
758 static const struct snd_kcontrol_new rinput_mux
=
759 SOC_DAPM_ENUM("Right Input Mux", rinput_enum
);
761 static const struct snd_kcontrol_new rinput_inv_mux
=
762 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum
);
764 static const struct snd_kcontrol_new lsidetone_mux
=
765 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum
);
767 static const struct snd_kcontrol_new rsidetone_mux
=
768 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum
);
770 static const struct snd_kcontrol_new lcapture_mux
=
771 SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum
);
773 static const struct snd_kcontrol_new rcapture_mux
=
774 SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum
);
776 static const struct snd_kcontrol_new lplay_mux
=
777 SOC_DAPM_ENUM("Left Playback Mux", lplay_enum
);
779 static const struct snd_kcontrol_new rplay_mux
=
780 SOC_DAPM_ENUM("Right Playback Mux", rplay_enum
);
782 static const struct snd_kcontrol_new left_output_mixer
[] = {
783 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 3, 1, 0),
784 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 2, 1, 0),
785 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 1, 1, 0),
786 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 0, 1, 0),
789 static const struct snd_kcontrol_new right_output_mixer
[] = {
790 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 3, 1, 0),
791 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 2, 1, 0),
792 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 1, 1, 0),
793 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 0, 1, 0),
796 static const struct snd_kcontrol_new left_speaker_mixer
[] = {
797 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
, 3, 1, 0),
798 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
, 2, 1, 0),
799 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
, 1, 1, 0),
800 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
,
804 static const struct snd_kcontrol_new right_speaker_mixer
[] = {
805 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
, 3, 1, 0),
806 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
, 2, 1, 0),
807 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
,
809 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
,
813 static const struct snd_soc_dapm_widget wm8903_dapm_widgets
[] = {
814 SND_SOC_DAPM_INPUT("IN1L"),
815 SND_SOC_DAPM_INPUT("IN1R"),
816 SND_SOC_DAPM_INPUT("IN2L"),
817 SND_SOC_DAPM_INPUT("IN2R"),
818 SND_SOC_DAPM_INPUT("IN3L"),
819 SND_SOC_DAPM_INPUT("IN3R"),
821 SND_SOC_DAPM_OUTPUT("HPOUTL"),
822 SND_SOC_DAPM_OUTPUT("HPOUTR"),
823 SND_SOC_DAPM_OUTPUT("LINEOUTL"),
824 SND_SOC_DAPM_OUTPUT("LINEOUTR"),
825 SND_SOC_DAPM_OUTPUT("LOP"),
826 SND_SOC_DAPM_OUTPUT("LON"),
827 SND_SOC_DAPM_OUTPUT("ROP"),
828 SND_SOC_DAPM_OUTPUT("RON"),
830 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0
, 0, 0),
832 SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM
, 0, 0, &linput_mux
),
833 SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM
, 0, 0,
835 SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM
, 0, 0, &linput_mode_mux
),
837 SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM
, 0, 0, &rinput_mux
),
838 SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM
, 0, 0,
840 SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM
, 0, 0, &rinput_mode_mux
),
842 SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0
, 1, 0, NULL
, 0),
843 SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0
, 0, 0, NULL
, 0),
845 SND_SOC_DAPM_ADC("ADCL", NULL
, WM8903_POWER_MANAGEMENT_6
, 1, 0),
846 SND_SOC_DAPM_ADC("ADCR", NULL
, WM8903_POWER_MANAGEMENT_6
, 0, 0),
848 SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM
, 0, 0, &lcapture_mux
),
849 SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM
, 0, 0, &rcapture_mux
),
851 SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM
, 0, 0),
852 SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM
, 0, 0),
854 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM
, 0, 0, &lsidetone_mux
),
855 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM
, 0, 0, &rsidetone_mux
),
857 SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM
, 0, 0),
858 SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM
, 0, 0),
860 SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM
, 0, 0, &lplay_mux
),
861 SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM
, 0, 0, &rplay_mux
),
863 SND_SOC_DAPM_DAC("DACL", NULL
, WM8903_POWER_MANAGEMENT_6
, 3, 0),
864 SND_SOC_DAPM_DAC("DACR", NULL
, WM8903_POWER_MANAGEMENT_6
, 2, 0),
866 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1
, 1, 0,
867 left_output_mixer
, ARRAY_SIZE(left_output_mixer
)),
868 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1
, 0, 0,
869 right_output_mixer
, ARRAY_SIZE(right_output_mixer
)),
871 SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4
, 1, 0,
872 left_speaker_mixer
, ARRAY_SIZE(left_speaker_mixer
)),
873 SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4
, 0, 0,
874 right_speaker_mixer
, ARRAY_SIZE(right_speaker_mixer
)),
876 SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2
,
878 SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2
,
881 SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3
, 1, 0,
883 SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3
, 0, 0,
886 SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0
, 7, 0, NULL
, 0),
887 SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0
, 6, 0, NULL
, 0),
888 SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 2, WM8903_ANALOGUE_HP_0
, 5, 0, NULL
, 0),
889 SND_SOC_DAPM_PGA_S("HPL_ENA", 1, WM8903_ANALOGUE_HP_0
, 4, 0, NULL
, 0),
890 SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0
, 3, 0, NULL
, 0),
891 SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0
, 2, 0, NULL
, 0),
892 SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 2, WM8903_ANALOGUE_HP_0
, 1, 0, NULL
, 0),
893 SND_SOC_DAPM_PGA_S("HPR_ENA", 1, WM8903_ANALOGUE_HP_0
, 0, 0, NULL
, 0),
895 SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0
, 7, 0,
897 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0
, 6, 0,
899 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0
, 5, 0,
901 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA", 1, WM8903_ANALOGUE_LINEOUT_0
, 4, 0,
903 SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0
, 3, 0,
905 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0
, 2, 0,
907 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0
, 1, 0,
909 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA", 1, WM8903_ANALOGUE_LINEOUT_0
, 0, 0,
912 SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0
, 4, 0, NULL
, 0),
913 SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM
, 3, 0, wm8903_dcs_event
,
914 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
915 SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM
, 2, 0, wm8903_dcs_event
,
916 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
917 SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM
, 1, 0, wm8903_dcs_event
,
918 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
919 SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM
, 0, 0, wm8903_dcs_event
,
920 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
922 SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5
, 1, 0,
924 SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5
, 0, 0,
927 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0
, 0, 0,
928 wm8903_cp_event
, SND_SOC_DAPM_POST_PMU
),
929 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2
, 1, 0, NULL
, 0),
930 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2
, 2, 0, NULL
, 0),
933 static const struct snd_soc_dapm_route intercon
[] = {
935 { "CLK_DSP", NULL
, "CLK_SYS" },
936 { "Mic Bias", NULL
, "CLK_SYS" },
937 { "HPL_DCS", NULL
, "CLK_SYS" },
938 { "HPR_DCS", NULL
, "CLK_SYS" },
939 { "LINEOUTL_DCS", NULL
, "CLK_SYS" },
940 { "LINEOUTR_DCS", NULL
, "CLK_SYS" },
942 { "Left Input Mux", "IN1L", "IN1L" },
943 { "Left Input Mux", "IN2L", "IN2L" },
944 { "Left Input Mux", "IN3L", "IN3L" },
946 { "Left Input Inverting Mux", "IN1L", "IN1L" },
947 { "Left Input Inverting Mux", "IN2L", "IN2L" },
948 { "Left Input Inverting Mux", "IN3L", "IN3L" },
950 { "Right Input Mux", "IN1R", "IN1R" },
951 { "Right Input Mux", "IN2R", "IN2R" },
952 { "Right Input Mux", "IN3R", "IN3R" },
954 { "Right Input Inverting Mux", "IN1R", "IN1R" },
955 { "Right Input Inverting Mux", "IN2R", "IN2R" },
956 { "Right Input Inverting Mux", "IN3R", "IN3R" },
958 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
959 { "Left Input Mode Mux", "Differential Line",
961 { "Left Input Mode Mux", "Differential Line",
962 "Left Input Inverting Mux" },
963 { "Left Input Mode Mux", "Differential Mic",
965 { "Left Input Mode Mux", "Differential Mic",
966 "Left Input Inverting Mux" },
968 { "Right Input Mode Mux", "Single-Ended",
969 "Right Input Inverting Mux" },
970 { "Right Input Mode Mux", "Differential Line",
972 { "Right Input Mode Mux", "Differential Line",
973 "Right Input Inverting Mux" },
974 { "Right Input Mode Mux", "Differential Mic",
976 { "Right Input Mode Mux", "Differential Mic",
977 "Right Input Inverting Mux" },
979 { "Left Input PGA", NULL
, "Left Input Mode Mux" },
980 { "Right Input PGA", NULL
, "Right Input Mode Mux" },
982 { "Left Capture Mux", "Left", "ADCL" },
983 { "Left Capture Mux", "Right", "ADCR" },
985 { "Right Capture Mux", "Left", "ADCL" },
986 { "Right Capture Mux", "Right", "ADCR" },
988 { "AIFTXL", NULL
, "Left Capture Mux" },
989 { "AIFTXR", NULL
, "Right Capture Mux" },
991 { "ADCL", NULL
, "Left Input PGA" },
992 { "ADCL", NULL
, "CLK_DSP" },
993 { "ADCR", NULL
, "Right Input PGA" },
994 { "ADCR", NULL
, "CLK_DSP" },
996 { "Left Playback Mux", "Left", "AIFRXL" },
997 { "Left Playback Mux", "Right", "AIFRXR" },
999 { "Right Playback Mux", "Left", "AIFRXL" },
1000 { "Right Playback Mux", "Right", "AIFRXR" },
1002 { "DACL Sidetone", "Left", "ADCL" },
1003 { "DACL Sidetone", "Right", "ADCR" },
1004 { "DACR Sidetone", "Left", "ADCL" },
1005 { "DACR Sidetone", "Right", "ADCR" },
1007 { "DACL", NULL
, "Left Playback Mux" },
1008 { "DACL", NULL
, "DACL Sidetone" },
1009 { "DACL", NULL
, "CLK_DSP" },
1011 { "DACR", NULL
, "Right Playback Mux" },
1012 { "DACR", NULL
, "DACR Sidetone" },
1013 { "DACR", NULL
, "CLK_DSP" },
1015 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1016 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1017 { "Left Output Mixer", "DACL Switch", "DACL" },
1018 { "Left Output Mixer", "DACR Switch", "DACR" },
1020 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1021 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1022 { "Right Output Mixer", "DACL Switch", "DACL" },
1023 { "Right Output Mixer", "DACR Switch", "DACR" },
1025 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1026 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1027 { "Left Speaker Mixer", "DACL Switch", "DACL" },
1028 { "Left Speaker Mixer", "DACR Switch", "DACR" },
1030 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1031 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1032 { "Right Speaker Mixer", "DACL Switch", "DACL" },
1033 { "Right Speaker Mixer", "DACR Switch", "DACR" },
1035 { "Left Line Output PGA", NULL
, "Left Output Mixer" },
1036 { "Right Line Output PGA", NULL
, "Right Output Mixer" },
1038 { "Left Headphone Output PGA", NULL
, "Left Output Mixer" },
1039 { "Right Headphone Output PGA", NULL
, "Right Output Mixer" },
1041 { "Left Speaker PGA", NULL
, "Left Speaker Mixer" },
1042 { "Right Speaker PGA", NULL
, "Right Speaker Mixer" },
1044 { "HPL_ENA", NULL
, "Left Headphone Output PGA" },
1045 { "HPR_ENA", NULL
, "Right Headphone Output PGA" },
1046 { "HPL_ENA_DLY", NULL
, "HPL_ENA" },
1047 { "HPR_ENA_DLY", NULL
, "HPR_ENA" },
1048 { "LINEOUTL_ENA", NULL
, "Left Line Output PGA" },
1049 { "LINEOUTR_ENA", NULL
, "Right Line Output PGA" },
1050 { "LINEOUTL_ENA_DLY", NULL
, "LINEOUTL_ENA" },
1051 { "LINEOUTR_ENA_DLY", NULL
, "LINEOUTR_ENA" },
1053 { "HPL_DCS", NULL
, "DCS Master" },
1054 { "HPR_DCS", NULL
, "DCS Master" },
1055 { "LINEOUTL_DCS", NULL
, "DCS Master" },
1056 { "LINEOUTR_DCS", NULL
, "DCS Master" },
1058 { "HPL_DCS", NULL
, "HPL_ENA_DLY" },
1059 { "HPR_DCS", NULL
, "HPR_ENA_DLY" },
1060 { "LINEOUTL_DCS", NULL
, "LINEOUTL_ENA_DLY" },
1061 { "LINEOUTR_DCS", NULL
, "LINEOUTR_ENA_DLY" },
1063 { "HPL_ENA_OUTP", NULL
, "HPL_DCS" },
1064 { "HPR_ENA_OUTP", NULL
, "HPR_DCS" },
1065 { "LINEOUTL_ENA_OUTP", NULL
, "LINEOUTL_DCS" },
1066 { "LINEOUTR_ENA_OUTP", NULL
, "LINEOUTR_DCS" },
1068 { "HPL_RMV_SHORT", NULL
, "HPL_ENA_OUTP" },
1069 { "HPR_RMV_SHORT", NULL
, "HPR_ENA_OUTP" },
1070 { "LINEOUTL_RMV_SHORT", NULL
, "LINEOUTL_ENA_OUTP" },
1071 { "LINEOUTR_RMV_SHORT", NULL
, "LINEOUTR_ENA_OUTP" },
1073 { "HPOUTL", NULL
, "HPL_RMV_SHORT" },
1074 { "HPOUTR", NULL
, "HPR_RMV_SHORT" },
1075 { "LINEOUTL", NULL
, "LINEOUTL_RMV_SHORT" },
1076 { "LINEOUTR", NULL
, "LINEOUTR_RMV_SHORT" },
1078 { "LOP", NULL
, "Left Speaker PGA" },
1079 { "LON", NULL
, "Left Speaker PGA" },
1081 { "ROP", NULL
, "Right Speaker PGA" },
1082 { "RON", NULL
, "Right Speaker PGA" },
1084 { "Left Headphone Output PGA", NULL
, "Charge Pump" },
1085 { "Right Headphone Output PGA", NULL
, "Charge Pump" },
1086 { "Left Line Output PGA", NULL
, "Charge Pump" },
1087 { "Right Line Output PGA", NULL
, "Charge Pump" },
1090 static int wm8903_add_widgets(struct snd_soc_codec
*codec
)
1092 struct snd_soc_dapm_context
*dapm
= &codec
->dapm
;
1094 snd_soc_dapm_new_controls(dapm
, wm8903_dapm_widgets
,
1095 ARRAY_SIZE(wm8903_dapm_widgets
));
1096 snd_soc_dapm_add_routes(dapm
, intercon
, ARRAY_SIZE(intercon
));
1101 static int wm8903_set_bias_level(struct snd_soc_codec
*codec
,
1102 enum snd_soc_bias_level level
)
1105 case SND_SOC_BIAS_ON
:
1108 case SND_SOC_BIAS_PREPARE
:
1109 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1110 WM8903_VMID_RES_MASK
,
1111 WM8903_VMID_RES_50K
);
1114 case SND_SOC_BIAS_STANDBY
:
1115 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
1116 snd_soc_update_bits(codec
, WM8903_BIAS_CONTROL_0
,
1117 WM8903_POBCTRL
| WM8903_ISEL_MASK
|
1118 WM8903_STARTUP_BIAS_ENA
|
1121 (2 << WM8903_ISEL_SHIFT
) |
1122 WM8903_STARTUP_BIAS_ENA
);
1124 snd_soc_update_bits(codec
,
1125 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0
,
1126 WM8903_SPK_DISCHARGE
,
1127 WM8903_SPK_DISCHARGE
);
1131 snd_soc_update_bits(codec
, WM8903_POWER_MANAGEMENT_5
,
1132 WM8903_SPKL_ENA
| WM8903_SPKR_ENA
,
1133 WM8903_SPKL_ENA
| WM8903_SPKR_ENA
);
1135 snd_soc_update_bits(codec
,
1136 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0
,
1137 WM8903_SPK_DISCHARGE
, 0);
1139 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1140 WM8903_VMID_TIE_ENA
|
1142 WM8903_VMID_IO_ENA
|
1143 WM8903_VMID_SOFT_MASK
|
1144 WM8903_VMID_RES_MASK
|
1145 WM8903_VMID_BUF_ENA
,
1146 WM8903_VMID_TIE_ENA
|
1148 WM8903_VMID_IO_ENA
|
1149 (2 << WM8903_VMID_SOFT_SHIFT
) |
1150 WM8903_VMID_RES_250K
|
1151 WM8903_VMID_BUF_ENA
);
1155 snd_soc_update_bits(codec
, WM8903_POWER_MANAGEMENT_5
,
1156 WM8903_SPKL_ENA
| WM8903_SPKR_ENA
,
1159 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1160 WM8903_VMID_SOFT_MASK
, 0);
1162 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1163 WM8903_VMID_RES_MASK
,
1164 WM8903_VMID_RES_50K
);
1166 snd_soc_update_bits(codec
, WM8903_BIAS_CONTROL_0
,
1167 WM8903_BIAS_ENA
| WM8903_POBCTRL
,
1170 /* By default no bypass paths are enabled so
1171 * enable Class W support.
1173 dev_dbg(codec
->dev
, "Enabling Class W\n");
1174 snd_soc_update_bits(codec
, WM8903_CLASS_W_0
,
1175 WM8903_CP_DYN_FREQ
|
1177 WM8903_CP_DYN_FREQ
|
1181 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1182 WM8903_VMID_RES_MASK
,
1183 WM8903_VMID_RES_250K
);
1186 case SND_SOC_BIAS_OFF
:
1187 snd_soc_update_bits(codec
, WM8903_BIAS_CONTROL_0
,
1188 WM8903_BIAS_ENA
, 0);
1190 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1191 WM8903_VMID_SOFT_MASK
,
1192 2 << WM8903_VMID_SOFT_SHIFT
);
1194 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1195 WM8903_VMID_BUF_ENA
, 0);
1199 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1200 WM8903_VMID_TIE_ENA
| WM8903_BUFIO_ENA
|
1201 WM8903_VMID_IO_ENA
| WM8903_VMID_RES_MASK
|
1202 WM8903_VMID_SOFT_MASK
|
1203 WM8903_VMID_BUF_ENA
, 0);
1205 snd_soc_update_bits(codec
, WM8903_BIAS_CONTROL_0
,
1206 WM8903_STARTUP_BIAS_ENA
, 0);
1210 codec
->dapm
.bias_level
= level
;
1215 static int wm8903_set_dai_sysclk(struct snd_soc_dai
*codec_dai
,
1216 int clk_id
, unsigned int freq
, int dir
)
1218 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1219 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1221 wm8903
->sysclk
= freq
;
1226 static int wm8903_set_dai_fmt(struct snd_soc_dai
*codec_dai
,
1229 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1230 u16 aif1
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_1
);
1232 aif1
&= ~(WM8903_LRCLK_DIR
| WM8903_BCLK_DIR
| WM8903_AIF_FMT_MASK
|
1233 WM8903_AIF_LRCLK_INV
| WM8903_AIF_BCLK_INV
);
1235 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
1236 case SND_SOC_DAIFMT_CBS_CFS
:
1238 case SND_SOC_DAIFMT_CBS_CFM
:
1239 aif1
|= WM8903_LRCLK_DIR
;
1241 case SND_SOC_DAIFMT_CBM_CFM
:
1242 aif1
|= WM8903_LRCLK_DIR
| WM8903_BCLK_DIR
;
1244 case SND_SOC_DAIFMT_CBM_CFS
:
1245 aif1
|= WM8903_BCLK_DIR
;
1251 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1252 case SND_SOC_DAIFMT_DSP_A
:
1255 case SND_SOC_DAIFMT_DSP_B
:
1256 aif1
|= 0x3 | WM8903_AIF_LRCLK_INV
;
1258 case SND_SOC_DAIFMT_I2S
:
1261 case SND_SOC_DAIFMT_RIGHT_J
:
1264 case SND_SOC_DAIFMT_LEFT_J
:
1270 /* Clock inversion */
1271 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1272 case SND_SOC_DAIFMT_DSP_A
:
1273 case SND_SOC_DAIFMT_DSP_B
:
1274 /* frame inversion not valid for DSP modes */
1275 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1276 case SND_SOC_DAIFMT_NB_NF
:
1278 case SND_SOC_DAIFMT_IB_NF
:
1279 aif1
|= WM8903_AIF_BCLK_INV
;
1285 case SND_SOC_DAIFMT_I2S
:
1286 case SND_SOC_DAIFMT_RIGHT_J
:
1287 case SND_SOC_DAIFMT_LEFT_J
:
1288 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1289 case SND_SOC_DAIFMT_NB_NF
:
1291 case SND_SOC_DAIFMT_IB_IF
:
1292 aif1
|= WM8903_AIF_BCLK_INV
| WM8903_AIF_LRCLK_INV
;
1294 case SND_SOC_DAIFMT_IB_NF
:
1295 aif1
|= WM8903_AIF_BCLK_INV
;
1297 case SND_SOC_DAIFMT_NB_IF
:
1298 aif1
|= WM8903_AIF_LRCLK_INV
;
1308 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_1
, aif1
);
1313 static int wm8903_digital_mute(struct snd_soc_dai
*codec_dai
, int mute
)
1315 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1318 reg
= snd_soc_read(codec
, WM8903_DAC_DIGITAL_1
);
1321 reg
|= WM8903_DAC_MUTE
;
1323 reg
&= ~WM8903_DAC_MUTE
;
1325 snd_soc_write(codec
, WM8903_DAC_DIGITAL_1
, reg
);
1330 /* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1331 * for optimal performance so we list the lower rates first and match
1332 * on the last match we find. */
1338 } clk_sys_ratios
[] = {
1339 { 64, 0x0, 0x0, 1 },
1340 { 68, 0x0, 0x1, 1 },
1341 { 125, 0x0, 0x2, 1 },
1342 { 128, 0x1, 0x0, 1 },
1343 { 136, 0x1, 0x1, 1 },
1344 { 192, 0x2, 0x0, 1 },
1345 { 204, 0x2, 0x1, 1 },
1347 { 64, 0x0, 0x0, 2 },
1348 { 68, 0x0, 0x1, 2 },
1349 { 125, 0x0, 0x2, 2 },
1350 { 128, 0x1, 0x0, 2 },
1351 { 136, 0x1, 0x1, 2 },
1352 { 192, 0x2, 0x0, 2 },
1353 { 204, 0x2, 0x1, 2 },
1355 { 250, 0x2, 0x2, 1 },
1356 { 256, 0x3, 0x0, 1 },
1357 { 272, 0x3, 0x1, 1 },
1358 { 384, 0x4, 0x0, 1 },
1359 { 408, 0x4, 0x1, 1 },
1360 { 375, 0x4, 0x2, 1 },
1361 { 512, 0x5, 0x0, 1 },
1362 { 544, 0x5, 0x1, 1 },
1363 { 500, 0x5, 0x2, 1 },
1364 { 768, 0x6, 0x0, 1 },
1365 { 816, 0x6, 0x1, 1 },
1366 { 750, 0x6, 0x2, 1 },
1367 { 1024, 0x7, 0x0, 1 },
1368 { 1088, 0x7, 0x1, 1 },
1369 { 1000, 0x7, 0x2, 1 },
1370 { 1408, 0x8, 0x0, 1 },
1371 { 1496, 0x8, 0x1, 1 },
1372 { 1536, 0x9, 0x0, 1 },
1373 { 1632, 0x9, 0x1, 1 },
1374 { 1500, 0x9, 0x2, 1 },
1376 { 250, 0x2, 0x2, 2 },
1377 { 256, 0x3, 0x0, 2 },
1378 { 272, 0x3, 0x1, 2 },
1379 { 384, 0x4, 0x0, 2 },
1380 { 408, 0x4, 0x1, 2 },
1381 { 375, 0x4, 0x2, 2 },
1382 { 512, 0x5, 0x0, 2 },
1383 { 544, 0x5, 0x1, 2 },
1384 { 500, 0x5, 0x2, 2 },
1385 { 768, 0x6, 0x0, 2 },
1386 { 816, 0x6, 0x1, 2 },
1387 { 750, 0x6, 0x2, 2 },
1388 { 1024, 0x7, 0x0, 2 },
1389 { 1088, 0x7, 0x1, 2 },
1390 { 1000, 0x7, 0x2, 2 },
1391 { 1408, 0x8, 0x0, 2 },
1392 { 1496, 0x8, 0x1, 2 },
1393 { 1536, 0x9, 0x0, 2 },
1394 { 1632, 0x9, 0x1, 2 },
1395 { 1500, 0x9, 0x2, 2 },
1398 /* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1422 /* Sample rates for DSP */
1426 } sample_rates
[] = {
1441 static int wm8903_hw_params(struct snd_pcm_substream
*substream
,
1442 struct snd_pcm_hw_params
*params
,
1443 struct snd_soc_dai
*dai
)
1445 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
1446 struct snd_soc_codec
*codec
=rtd
->codec
;
1447 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1448 int fs
= params_rate(params
);
1458 u16 aif1
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_1
);
1459 u16 aif2
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_2
);
1460 u16 aif3
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_3
);
1461 u16 clock0
= snd_soc_read(codec
, WM8903_CLOCK_RATES_0
);
1462 u16 clock1
= snd_soc_read(codec
, WM8903_CLOCK_RATES_1
);
1463 u16 dac_digital1
= snd_soc_read(codec
, WM8903_DAC_DIGITAL_1
);
1465 /* Enable sloping stopband filter for low sample rates */
1467 dac_digital1
|= WM8903_DAC_SB_FILT
;
1469 dac_digital1
&= ~WM8903_DAC_SB_FILT
;
1471 /* Configure sample rate logic for DSP - choose nearest rate */
1473 best_val
= abs(sample_rates
[dsp_config
].rate
- fs
);
1474 for (i
= 1; i
< ARRAY_SIZE(sample_rates
); i
++) {
1475 cur_val
= abs(sample_rates
[i
].rate
- fs
);
1476 if (cur_val
<= best_val
) {
1482 dev_dbg(codec
->dev
, "DSP fs = %dHz\n", sample_rates
[dsp_config
].rate
);
1483 clock1
&= ~WM8903_SAMPLE_RATE_MASK
;
1484 clock1
|= sample_rates
[dsp_config
].value
;
1486 aif1
&= ~WM8903_AIF_WL_MASK
;
1488 switch (params_format(params
)) {
1489 case SNDRV_PCM_FORMAT_S16_LE
:
1492 case SNDRV_PCM_FORMAT_S20_3LE
:
1496 case SNDRV_PCM_FORMAT_S24_LE
:
1500 case SNDRV_PCM_FORMAT_S32_LE
:
1508 dev_dbg(codec
->dev
, "MCLK = %dHz, target sample rate = %dHz\n",
1509 wm8903
->sysclk
, fs
);
1511 /* We may not have an MCLK which allows us to generate exactly
1512 * the clock we want, particularly with USB derived inputs, so
1516 best_val
= abs((wm8903
->sysclk
/
1517 (clk_sys_ratios
[0].mclk_div
*
1518 clk_sys_ratios
[0].div
)) - fs
);
1519 for (i
= 1; i
< ARRAY_SIZE(clk_sys_ratios
); i
++) {
1520 cur_val
= abs((wm8903
->sysclk
/
1521 (clk_sys_ratios
[i
].mclk_div
*
1522 clk_sys_ratios
[i
].div
)) - fs
);
1524 if (cur_val
<= best_val
) {
1530 if (clk_sys_ratios
[clk_config
].mclk_div
== 2) {
1531 clock0
|= WM8903_MCLKDIV2
;
1532 clk_sys
= wm8903
->sysclk
/ 2;
1534 clock0
&= ~WM8903_MCLKDIV2
;
1535 clk_sys
= wm8903
->sysclk
;
1538 clock1
&= ~(WM8903_CLK_SYS_RATE_MASK
|
1539 WM8903_CLK_SYS_MODE_MASK
);
1540 clock1
|= clk_sys_ratios
[clk_config
].rate
<< WM8903_CLK_SYS_RATE_SHIFT
;
1541 clock1
|= clk_sys_ratios
[clk_config
].mode
<< WM8903_CLK_SYS_MODE_SHIFT
;
1543 dev_dbg(codec
->dev
, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
1544 clk_sys_ratios
[clk_config
].rate
,
1545 clk_sys_ratios
[clk_config
].mode
,
1546 clk_sys_ratios
[clk_config
].div
);
1548 dev_dbg(codec
->dev
, "Actual CLK_SYS = %dHz\n", clk_sys
);
1550 /* We may not get quite the right frequency if using
1551 * approximate clocks so look for the closest match that is
1552 * higher than the target (we need to ensure that there enough
1553 * BCLKs to clock out the samples).
1556 best_val
= ((clk_sys
* 10) / bclk_divs
[0].ratio
) - bclk
;
1558 while (i
< ARRAY_SIZE(bclk_divs
)) {
1559 cur_val
= ((clk_sys
* 10) / bclk_divs
[i
].ratio
) - bclk
;
1560 if (cur_val
< 0) /* BCLK table is sorted */
1567 aif2
&= ~WM8903_BCLK_DIV_MASK
;
1568 aif3
&= ~WM8903_LRCLK_RATE_MASK
;
1570 dev_dbg(codec
->dev
, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
1571 bclk_divs
[bclk_div
].ratio
/ 10, bclk
,
1572 (clk_sys
* 10) / bclk_divs
[bclk_div
].ratio
);
1574 aif2
|= bclk_divs
[bclk_div
].div
;
1577 wm8903
->fs
= params_rate(params
);
1578 wm8903_set_deemph(codec
);
1580 snd_soc_write(codec
, WM8903_CLOCK_RATES_0
, clock0
);
1581 snd_soc_write(codec
, WM8903_CLOCK_RATES_1
, clock1
);
1582 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_1
, aif1
);
1583 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_2
, aif2
);
1584 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_3
, aif3
);
1585 snd_soc_write(codec
, WM8903_DAC_DIGITAL_1
, dac_digital1
);
1591 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1593 * @codec: WM8903 codec
1594 * @jack: jack to report detection events on
1595 * @det: value to report for presence detection
1596 * @shrt: value to report for short detection
1598 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1599 * being used to bring out signals to the processor then only platform
1600 * data configuration is needed for WM8903 and processor GPIOs should
1601 * be configured using snd_soc_jack_add_gpios() instead.
1603 * The current threasholds for detection should be configured using
1604 * micdet_cfg in the platform data. Using this function will force on
1605 * the microphone bias for the device.
1607 int wm8903_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
1610 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1611 int irq_mask
= WM8903_MICDET_EINT
| WM8903_MICSHRT_EINT
;
1613 dev_dbg(codec
->dev
, "Enabling microphone detection: %x %x\n",
1616 /* Store the configuration */
1617 wm8903
->mic_jack
= jack
;
1618 wm8903
->mic_det
= det
;
1619 wm8903
->mic_short
= shrt
;
1621 /* Enable interrupts we've got a report configured for */
1623 irq_mask
&= ~WM8903_MICDET_EINT
;
1625 irq_mask
&= ~WM8903_MICSHRT_EINT
;
1627 snd_soc_update_bits(codec
, WM8903_INTERRUPT_STATUS_1_MASK
,
1628 WM8903_MICDET_EINT
| WM8903_MICSHRT_EINT
,
1632 /* Enable mic detection, this may not have been set through
1633 * platform data (eg, if the defaults are OK). */
1634 snd_soc_update_bits(codec
, WM8903_WRITE_SEQUENCER_0
,
1635 WM8903_WSEQ_ENA
, WM8903_WSEQ_ENA
);
1636 snd_soc_update_bits(codec
, WM8903_MIC_BIAS_CONTROL_0
,
1637 WM8903_MICDET_ENA
, WM8903_MICDET_ENA
);
1639 snd_soc_update_bits(codec
, WM8903_MIC_BIAS_CONTROL_0
,
1640 WM8903_MICDET_ENA
, 0);
1645 EXPORT_SYMBOL_GPL(wm8903_mic_detect
);
1647 static irqreturn_t
wm8903_irq(int irq
, void *data
)
1649 struct snd_soc_codec
*codec
= data
;
1650 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1654 int mask
= ~snd_soc_read(codec
, WM8903_INTERRUPT_STATUS_1_MASK
);
1656 int_val
= snd_soc_read(codec
, WM8903_INTERRUPT_STATUS_1
) & mask
;
1658 if (int_val
& WM8903_WSEQ_BUSY_EINT
) {
1659 dev_warn(codec
->dev
, "Write sequencer done\n");
1663 * The rest is microphone jack detection. We need to manually
1664 * invert the polarity of the interrupt after each event - to
1665 * simplify the code keep track of the last state we reported
1666 * and just invert the relevant bits in both the report and
1667 * the polarity register.
1669 mic_report
= wm8903
->mic_last_report
;
1670 int_pol
= snd_soc_read(codec
, WM8903_INTERRUPT_POLARITY_1
);
1672 #ifndef CONFIG_SND_SOC_WM8903_MODULE
1673 if (int_val
& (WM8903_MICSHRT_EINT
| WM8903_MICDET_EINT
))
1674 trace_snd_soc_jack_irq(dev_name(codec
->dev
));
1677 if (int_val
& WM8903_MICSHRT_EINT
) {
1678 dev_dbg(codec
->dev
, "Microphone short (pol=%x)\n", int_pol
);
1680 mic_report
^= wm8903
->mic_short
;
1681 int_pol
^= WM8903_MICSHRT_INV
;
1684 if (int_val
& WM8903_MICDET_EINT
) {
1685 dev_dbg(codec
->dev
, "Microphone detect (pol=%x)\n", int_pol
);
1687 mic_report
^= wm8903
->mic_det
;
1688 int_pol
^= WM8903_MICDET_INV
;
1690 msleep(wm8903
->mic_delay
);
1693 snd_soc_update_bits(codec
, WM8903_INTERRUPT_POLARITY_1
,
1694 WM8903_MICSHRT_INV
| WM8903_MICDET_INV
, int_pol
);
1696 snd_soc_jack_report(wm8903
->mic_jack
, mic_report
,
1697 wm8903
->mic_short
| wm8903
->mic_det
);
1699 wm8903
->mic_last_report
= mic_report
;
1704 #define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1705 SNDRV_PCM_RATE_11025 | \
1706 SNDRV_PCM_RATE_16000 | \
1707 SNDRV_PCM_RATE_22050 | \
1708 SNDRV_PCM_RATE_32000 | \
1709 SNDRV_PCM_RATE_44100 | \
1710 SNDRV_PCM_RATE_48000 | \
1711 SNDRV_PCM_RATE_88200 | \
1712 SNDRV_PCM_RATE_96000)
1714 #define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1715 SNDRV_PCM_RATE_11025 | \
1716 SNDRV_PCM_RATE_16000 | \
1717 SNDRV_PCM_RATE_22050 | \
1718 SNDRV_PCM_RATE_32000 | \
1719 SNDRV_PCM_RATE_44100 | \
1720 SNDRV_PCM_RATE_48000)
1722 #define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1723 SNDRV_PCM_FMTBIT_S20_3LE |\
1724 SNDRV_PCM_FMTBIT_S24_LE)
1726 static struct snd_soc_dai_ops wm8903_dai_ops
= {
1727 .hw_params
= wm8903_hw_params
,
1728 .digital_mute
= wm8903_digital_mute
,
1729 .set_fmt
= wm8903_set_dai_fmt
,
1730 .set_sysclk
= wm8903_set_dai_sysclk
,
1733 static struct snd_soc_dai_driver wm8903_dai
= {
1734 .name
= "wm8903-hifi",
1736 .stream_name
= "Playback",
1739 .rates
= WM8903_PLAYBACK_RATES
,
1740 .formats
= WM8903_FORMATS
,
1743 .stream_name
= "Capture",
1746 .rates
= WM8903_CAPTURE_RATES
,
1747 .formats
= WM8903_FORMATS
,
1749 .ops
= &wm8903_dai_ops
,
1750 .symmetric_rates
= 1,
1753 static int wm8903_suspend(struct snd_soc_codec
*codec
, pm_message_t state
)
1755 wm8903_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1760 static int wm8903_resume(struct snd_soc_codec
*codec
)
1763 u16
*reg_cache
= codec
->reg_cache
;
1764 u16
*tmp_cache
= kmemdup(reg_cache
, sizeof(wm8903_reg_defaults
),
1767 /* Bring the codec back up to standby first to minimise pop/clicks */
1768 wm8903_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1770 /* Sync back everything else */
1772 for (i
= 2; i
< ARRAY_SIZE(wm8903_reg_defaults
); i
++)
1773 if (tmp_cache
[i
] != reg_cache
[i
])
1774 snd_soc_write(codec
, i
, tmp_cache
[i
]);
1777 dev_err(codec
->dev
, "Failed to allocate temporary cache\n");
1783 #ifdef CONFIG_GPIOLIB
1784 static inline struct wm8903_priv
*gpio_to_wm8903(struct gpio_chip
*chip
)
1786 return container_of(chip
, struct wm8903_priv
, gpio_chip
);
1789 static int wm8903_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
1791 if (offset
>= WM8903_NUM_GPIO
)
1797 static int wm8903_gpio_direction_in(struct gpio_chip
*chip
, unsigned offset
)
1799 struct wm8903_priv
*wm8903
= gpio_to_wm8903(chip
);
1800 struct snd_soc_codec
*codec
= wm8903
->codec
;
1801 unsigned int mask
, val
;
1803 mask
= WM8903_GP1_FN_MASK
| WM8903_GP1_DIR_MASK
;
1804 val
= (WM8903_GPn_FN_GPIO_INPUT
<< WM8903_GP1_FN_SHIFT
) |
1807 return snd_soc_update_bits(codec
, WM8903_GPIO_CONTROL_1
+ offset
,
1811 static int wm8903_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
1813 struct wm8903_priv
*wm8903
= gpio_to_wm8903(chip
);
1814 struct snd_soc_codec
*codec
= wm8903
->codec
;
1817 reg
= snd_soc_read(codec
, WM8903_GPIO_CONTROL_1
+ offset
);
1819 return (reg
& WM8903_GP1_LVL_MASK
) >> WM8903_GP1_LVL_SHIFT
;
1822 static int wm8903_gpio_direction_out(struct gpio_chip
*chip
,
1823 unsigned offset
, int value
)
1825 struct wm8903_priv
*wm8903
= gpio_to_wm8903(chip
);
1826 struct snd_soc_codec
*codec
= wm8903
->codec
;
1827 unsigned int mask
, val
;
1829 mask
= WM8903_GP1_FN_MASK
| WM8903_GP1_DIR_MASK
| WM8903_GP1_LVL_MASK
;
1830 val
= (WM8903_GPn_FN_GPIO_OUTPUT
<< WM8903_GP1_FN_SHIFT
) |
1831 (value
<< WM8903_GP2_LVL_SHIFT
);
1833 return snd_soc_update_bits(codec
, WM8903_GPIO_CONTROL_1
+ offset
,
1837 static void wm8903_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
1839 struct wm8903_priv
*wm8903
= gpio_to_wm8903(chip
);
1840 struct snd_soc_codec
*codec
= wm8903
->codec
;
1842 snd_soc_update_bits(codec
, WM8903_GPIO_CONTROL_1
+ offset
,
1843 WM8903_GP1_LVL_MASK
,
1844 !!value
<< WM8903_GP1_LVL_SHIFT
);
1847 static struct gpio_chip wm8903_template_chip
= {
1849 .owner
= THIS_MODULE
,
1850 .request
= wm8903_gpio_request
,
1851 .direction_input
= wm8903_gpio_direction_in
,
1852 .get
= wm8903_gpio_get
,
1853 .direction_output
= wm8903_gpio_direction_out
,
1854 .set
= wm8903_gpio_set
,
1858 static void wm8903_init_gpio(struct snd_soc_codec
*codec
)
1860 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1861 struct wm8903_platform_data
*pdata
= dev_get_platdata(codec
->dev
);
1864 wm8903
->gpio_chip
= wm8903_template_chip
;
1865 wm8903
->gpio_chip
.ngpio
= WM8903_NUM_GPIO
;
1866 wm8903
->gpio_chip
.dev
= codec
->dev
;
1868 if (pdata
&& pdata
->gpio_base
)
1869 wm8903
->gpio_chip
.base
= pdata
->gpio_base
;
1871 wm8903
->gpio_chip
.base
= -1;
1873 ret
= gpiochip_add(&wm8903
->gpio_chip
);
1875 dev_err(codec
->dev
, "Failed to add GPIOs: %d\n", ret
);
1878 static void wm8903_free_gpio(struct snd_soc_codec
*codec
)
1880 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1883 ret
= gpiochip_remove(&wm8903
->gpio_chip
);
1885 dev_err(codec
->dev
, "Failed to remove GPIOs: %d\n", ret
);
1888 static void wm8903_init_gpio(struct snd_soc_codec
*codec
)
1892 static void wm8903_free_gpio(struct snd_soc_codec
*codec
)
1897 static int wm8903_probe(struct snd_soc_codec
*codec
)
1899 struct wm8903_platform_data
*pdata
= dev_get_platdata(codec
->dev
);
1900 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1902 int trigger
, irq_pol
;
1905 wm8903
->codec
= codec
;
1907 ret
= snd_soc_codec_set_cache_io(codec
, 8, 16, SND_SOC_I2C
);
1909 dev_err(codec
->dev
, "Failed to set cache I/O: %d\n", ret
);
1913 val
= snd_soc_read(codec
, WM8903_SW_RESET_AND_ID
);
1914 if (val
!= wm8903_reg_defaults
[WM8903_SW_RESET_AND_ID
]) {
1916 "Device with ID register %x is not a WM8903\n", val
);
1920 val
= snd_soc_read(codec
, WM8903_REVISION_NUMBER
);
1921 dev_info(codec
->dev
, "WM8903 revision %c\n",
1922 (val
& WM8903_CHIP_REV_MASK
) + 'A');
1924 wm8903_reset(codec
);
1926 /* Set up GPIOs and microphone detection */
1928 bool mic_gpio
= false;
1930 for (i
= 0; i
< ARRAY_SIZE(pdata
->gpio_cfg
); i
++) {
1931 if (pdata
->gpio_cfg
[i
] == WM8903_GPIO_NO_CONFIG
)
1934 snd_soc_write(codec
, WM8903_GPIO_CONTROL_1
+ i
,
1935 pdata
->gpio_cfg
[i
] & 0xffff);
1937 val
= (pdata
->gpio_cfg
[i
] & WM8903_GP1_FN_MASK
)
1938 >> WM8903_GP1_FN_SHIFT
;
1941 case WM8903_GPn_FN_MICBIAS_CURRENT_DETECT
:
1942 case WM8903_GPn_FN_MICBIAS_SHORT_DETECT
:
1950 snd_soc_write(codec
, WM8903_MIC_BIAS_CONTROL_0
,
1953 /* Microphone detection needs the WSEQ clock */
1954 if (pdata
->micdet_cfg
)
1955 snd_soc_update_bits(codec
, WM8903_WRITE_SEQUENCER_0
,
1956 WM8903_WSEQ_ENA
, WM8903_WSEQ_ENA
);
1958 /* If microphone detection is enabled by pdata but
1959 * detected via IRQ then interrupts can be lost before
1960 * the machine driver has set up microphone detection
1961 * IRQs as the IRQs are clear on read. The detection
1962 * will be enabled when the machine driver configures.
1964 WARN_ON(!mic_gpio
&& (pdata
->micdet_cfg
& WM8903_MICDET_ENA
));
1966 wm8903
->mic_delay
= pdata
->micdet_delay
;
1970 if (pdata
&& pdata
->irq_active_low
) {
1971 trigger
= IRQF_TRIGGER_LOW
;
1972 irq_pol
= WM8903_IRQ_POL
;
1974 trigger
= IRQF_TRIGGER_HIGH
;
1978 snd_soc_update_bits(codec
, WM8903_INTERRUPT_CONTROL
,
1979 WM8903_IRQ_POL
, irq_pol
);
1981 ret
= request_threaded_irq(wm8903
->irq
, NULL
, wm8903_irq
,
1982 trigger
| IRQF_ONESHOT
,
1985 dev_err(codec
->dev
, "Failed to request IRQ: %d\n",
1990 /* Enable write sequencer interrupts */
1991 snd_soc_update_bits(codec
, WM8903_INTERRUPT_STATUS_1_MASK
,
1992 WM8903_IM_WSEQ_BUSY_EINT
, 0);
1995 /* power on device */
1996 wm8903_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1998 /* Latch volume update bits */
1999 val
= snd_soc_read(codec
, WM8903_ADC_DIGITAL_VOLUME_LEFT
);
2000 val
|= WM8903_ADCVU
;
2001 snd_soc_write(codec
, WM8903_ADC_DIGITAL_VOLUME_LEFT
, val
);
2002 snd_soc_write(codec
, WM8903_ADC_DIGITAL_VOLUME_RIGHT
, val
);
2004 val
= snd_soc_read(codec
, WM8903_DAC_DIGITAL_VOLUME_LEFT
);
2005 val
|= WM8903_DACVU
;
2006 snd_soc_write(codec
, WM8903_DAC_DIGITAL_VOLUME_LEFT
, val
);
2007 snd_soc_write(codec
, WM8903_DAC_DIGITAL_VOLUME_RIGHT
, val
);
2009 val
= snd_soc_read(codec
, WM8903_ANALOGUE_OUT1_LEFT
);
2010 val
|= WM8903_HPOUTVU
;
2011 snd_soc_write(codec
, WM8903_ANALOGUE_OUT1_LEFT
, val
);
2012 snd_soc_write(codec
, WM8903_ANALOGUE_OUT1_RIGHT
, val
);
2014 val
= snd_soc_read(codec
, WM8903_ANALOGUE_OUT2_LEFT
);
2015 val
|= WM8903_LINEOUTVU
;
2016 snd_soc_write(codec
, WM8903_ANALOGUE_OUT2_LEFT
, val
);
2017 snd_soc_write(codec
, WM8903_ANALOGUE_OUT2_RIGHT
, val
);
2019 val
= snd_soc_read(codec
, WM8903_ANALOGUE_OUT3_LEFT
);
2020 val
|= WM8903_SPKVU
;
2021 snd_soc_write(codec
, WM8903_ANALOGUE_OUT3_LEFT
, val
);
2022 snd_soc_write(codec
, WM8903_ANALOGUE_OUT3_RIGHT
, val
);
2024 /* Enable DAC soft mute by default */
2025 snd_soc_update_bits(codec
, WM8903_DAC_DIGITAL_1
,
2026 WM8903_DAC_MUTEMODE
| WM8903_DAC_MUTE
,
2027 WM8903_DAC_MUTEMODE
| WM8903_DAC_MUTE
);
2029 snd_soc_add_controls(codec
, wm8903_snd_controls
,
2030 ARRAY_SIZE(wm8903_snd_controls
));
2031 wm8903_add_widgets(codec
);
2033 wm8903_init_gpio(codec
);
2038 /* power down chip */
2039 static int wm8903_remove(struct snd_soc_codec
*codec
)
2041 wm8903_free_gpio(codec
);
2042 wm8903_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
2046 static struct snd_soc_codec_driver soc_codec_dev_wm8903
= {
2047 .probe
= wm8903_probe
,
2048 .remove
= wm8903_remove
,
2049 .suspend
= wm8903_suspend
,
2050 .resume
= wm8903_resume
,
2051 .set_bias_level
= wm8903_set_bias_level
,
2052 .reg_cache_size
= ARRAY_SIZE(wm8903_reg_defaults
),
2053 .reg_word_size
= sizeof(u16
),
2054 .reg_cache_default
= wm8903_reg_defaults
,
2055 .volatile_register
= wm8903_volatile_register
,
2056 .seq_notifier
= wm8903_seq_notifier
,
2059 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2060 static __devinit
int wm8903_i2c_probe(struct i2c_client
*i2c
,
2061 const struct i2c_device_id
*id
)
2063 struct wm8903_priv
*wm8903
;
2066 wm8903
= kzalloc(sizeof(struct wm8903_priv
), GFP_KERNEL
);
2070 i2c_set_clientdata(i2c
, wm8903
);
2071 wm8903
->irq
= i2c
->irq
;
2073 ret
= snd_soc_register_codec(&i2c
->dev
,
2074 &soc_codec_dev_wm8903
, &wm8903_dai
, 1);
2080 static __devexit
int wm8903_i2c_remove(struct i2c_client
*client
)
2082 snd_soc_unregister_codec(&client
->dev
);
2083 kfree(i2c_get_clientdata(client
));
2087 static const struct i2c_device_id wm8903_i2c_id
[] = {
2091 MODULE_DEVICE_TABLE(i2c
, wm8903_i2c_id
);
2093 static struct i2c_driver wm8903_i2c_driver
= {
2096 .owner
= THIS_MODULE
,
2098 .probe
= wm8903_i2c_probe
,
2099 .remove
= __devexit_p(wm8903_i2c_remove
),
2100 .id_table
= wm8903_i2c_id
,
2104 static int __init
wm8903_modinit(void)
2107 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2108 ret
= i2c_add_driver(&wm8903_i2c_driver
);
2110 printk(KERN_ERR
"Failed to register wm8903 I2C driver: %d\n",
2116 module_init(wm8903_modinit
);
2118 static void __exit
wm8903_exit(void)
2120 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2121 i2c_del_driver(&wm8903_i2c_driver
);
2124 module_exit(wm8903_exit
);
2126 MODULE_DESCRIPTION("ASoC WM8903 driver");
2127 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
2128 MODULE_LICENSE("GPL");