2 * wm8903.c -- WM8903 ALSA SoC Audio driver
4 * Copyright 2008 Wolfson Microelectronics
5 * Copyright 2011 NVIDIA, Inc.
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * - TDM mode configuration.
15 * - Digital microphone support.
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/init.h>
21 #include <linux/completion.h>
22 #include <linux/delay.h>
23 #include <linux/gpio.h>
25 #include <linux/i2c.h>
26 #include <linux/regmap.h>
27 #include <linux/slab.h>
28 #include <sound/core.h>
29 #include <sound/jack.h>
30 #include <sound/pcm.h>
31 #include <sound/pcm_params.h>
32 #include <sound/tlv.h>
33 #include <sound/soc.h>
34 #include <sound/initval.h>
35 #include <sound/wm8903.h>
36 #include <trace/events/asoc.h>
40 /* Register defaults at reset */
41 static const struct reg_default wm8903_reg_defaults
[] = {
42 { 4, 0x0018 }, /* R4 - Bias Control 0 */
43 { 5, 0x0000 }, /* R5 - VMID Control 0 */
44 { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */
45 { 8, 0x0001 }, /* R8 - Analogue DAC 0 */
46 { 10, 0x0001 }, /* R10 - Analogue ADC 0 */
47 { 12, 0x0000 }, /* R12 - Power Management 0 */
48 { 13, 0x0000 }, /* R13 - Power Management 1 */
49 { 14, 0x0000 }, /* R14 - Power Management 2 */
50 { 15, 0x0000 }, /* R15 - Power Management 3 */
51 { 16, 0x0000 }, /* R16 - Power Management 4 */
52 { 17, 0x0000 }, /* R17 - Power Management 5 */
53 { 18, 0x0000 }, /* R18 - Power Management 6 */
54 { 20, 0x0400 }, /* R20 - Clock Rates 0 */
55 { 21, 0x0D07 }, /* R21 - Clock Rates 1 */
56 { 22, 0x0000 }, /* R22 - Clock Rates 2 */
57 { 24, 0x0050 }, /* R24 - Audio Interface 0 */
58 { 25, 0x0242 }, /* R25 - Audio Interface 1 */
59 { 26, 0x0008 }, /* R26 - Audio Interface 2 */
60 { 27, 0x0022 }, /* R27 - Audio Interface 3 */
61 { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */
62 { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */
63 { 32, 0x0000 }, /* R32 - DAC Digital 0 */
64 { 33, 0x0000 }, /* R33 - DAC Digital 1 */
65 { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */
66 { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */
67 { 38, 0x0000 }, /* R38 - ADC Digital 0 */
68 { 39, 0x0073 }, /* R39 - Digital Microphone 0 */
69 { 40, 0x09BF }, /* R40 - DRC 0 */
70 { 41, 0x3241 }, /* R41 - DRC 1 */
71 { 42, 0x0020 }, /* R42 - DRC 2 */
72 { 43, 0x0000 }, /* R43 - DRC 3 */
73 { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */
74 { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */
75 { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */
76 { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */
77 { 50, 0x0008 }, /* R50 - Analogue Left Mix 0 */
78 { 51, 0x0004 }, /* R51 - Analogue Right Mix 0 */
79 { 52, 0x0000 }, /* R52 - Analogue Spk Mix Left 0 */
80 { 53, 0x0000 }, /* R53 - Analogue Spk Mix Left 1 */
81 { 54, 0x0000 }, /* R54 - Analogue Spk Mix Right 0 */
82 { 55, 0x0000 }, /* R55 - Analogue Spk Mix Right 1 */
83 { 57, 0x002D }, /* R57 - Analogue OUT1 Left */
84 { 58, 0x002D }, /* R58 - Analogue OUT1 Right */
85 { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */
86 { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */
87 { 62, 0x0139 }, /* R62 - Analogue OUT3 Left */
88 { 63, 0x0139 }, /* R63 - Analogue OUT3 Right */
89 { 64, 0x0000 }, /* R65 - Analogue SPK Output Control 0 */
90 { 67, 0x0010 }, /* R67 - DC Servo 0 */
91 { 69, 0x00A4 }, /* R69 - DC Servo 2 */
92 { 90, 0x0000 }, /* R90 - Analogue HP 0 */
93 { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */
94 { 98, 0x0000 }, /* R98 - Charge Pump 0 */
95 { 104, 0x0000 }, /* R104 - Class W 0 */
96 { 108, 0x0000 }, /* R108 - Write Sequencer 0 */
97 { 109, 0x0000 }, /* R109 - Write Sequencer 1 */
98 { 110, 0x0000 }, /* R110 - Write Sequencer 2 */
99 { 111, 0x0000 }, /* R111 - Write Sequencer 3 */
100 { 112, 0x0000 }, /* R112 - Write Sequencer 4 */
101 { 114, 0x0000 }, /* R114 - Control Interface */
102 { 116, 0x00A8 }, /* R116 - GPIO Control 1 */
103 { 117, 0x00A8 }, /* R117 - GPIO Control 2 */
104 { 118, 0x00A8 }, /* R118 - GPIO Control 3 */
105 { 119, 0x0220 }, /* R119 - GPIO Control 4 */
106 { 120, 0x01A0 }, /* R120 - GPIO Control 5 */
107 { 122, 0xFFFF }, /* R122 - Interrupt Status 1 Mask */
108 { 123, 0x0000 }, /* R123 - Interrupt Polarity 1 */
109 { 126, 0x0000 }, /* R126 - Interrupt Control */
110 { 129, 0x0000 }, /* R129 - Control Interface Test 1 */
111 { 149, 0x6810 }, /* R149 - Charge Pump Test 1 */
112 { 164, 0x0028 }, /* R164 - Clock Rate Test 4 */
113 { 172, 0x0000 }, /* R172 - Analogue Output Bias 0 */
117 struct wm8903_platform_data
*pdata
;
118 struct snd_soc_codec
*codec
;
119 struct regmap
*regmap
;
130 /* Reference count */
133 struct snd_soc_jack
*mic_jack
;
139 #ifdef CONFIG_GPIOLIB
140 struct gpio_chip gpio_chip
;
144 static bool wm8903_readable_register(struct device
*dev
, unsigned int reg
)
147 case WM8903_SW_RESET_AND_ID
:
148 case WM8903_REVISION_NUMBER
:
149 case WM8903_BIAS_CONTROL_0
:
150 case WM8903_VMID_CONTROL_0
:
151 case WM8903_MIC_BIAS_CONTROL_0
:
152 case WM8903_ANALOGUE_DAC_0
:
153 case WM8903_ANALOGUE_ADC_0
:
154 case WM8903_POWER_MANAGEMENT_0
:
155 case WM8903_POWER_MANAGEMENT_1
:
156 case WM8903_POWER_MANAGEMENT_2
:
157 case WM8903_POWER_MANAGEMENT_3
:
158 case WM8903_POWER_MANAGEMENT_4
:
159 case WM8903_POWER_MANAGEMENT_5
:
160 case WM8903_POWER_MANAGEMENT_6
:
161 case WM8903_CLOCK_RATES_0
:
162 case WM8903_CLOCK_RATES_1
:
163 case WM8903_CLOCK_RATES_2
:
164 case WM8903_AUDIO_INTERFACE_0
:
165 case WM8903_AUDIO_INTERFACE_1
:
166 case WM8903_AUDIO_INTERFACE_2
:
167 case WM8903_AUDIO_INTERFACE_3
:
168 case WM8903_DAC_DIGITAL_VOLUME_LEFT
:
169 case WM8903_DAC_DIGITAL_VOLUME_RIGHT
:
170 case WM8903_DAC_DIGITAL_0
:
171 case WM8903_DAC_DIGITAL_1
:
172 case WM8903_ADC_DIGITAL_VOLUME_LEFT
:
173 case WM8903_ADC_DIGITAL_VOLUME_RIGHT
:
174 case WM8903_ADC_DIGITAL_0
:
175 case WM8903_DIGITAL_MICROPHONE_0
:
180 case WM8903_ANALOGUE_LEFT_INPUT_0
:
181 case WM8903_ANALOGUE_RIGHT_INPUT_0
:
182 case WM8903_ANALOGUE_LEFT_INPUT_1
:
183 case WM8903_ANALOGUE_RIGHT_INPUT_1
:
184 case WM8903_ANALOGUE_LEFT_MIX_0
:
185 case WM8903_ANALOGUE_RIGHT_MIX_0
:
186 case WM8903_ANALOGUE_SPK_MIX_LEFT_0
:
187 case WM8903_ANALOGUE_SPK_MIX_LEFT_1
:
188 case WM8903_ANALOGUE_SPK_MIX_RIGHT_0
:
189 case WM8903_ANALOGUE_SPK_MIX_RIGHT_1
:
190 case WM8903_ANALOGUE_OUT1_LEFT
:
191 case WM8903_ANALOGUE_OUT1_RIGHT
:
192 case WM8903_ANALOGUE_OUT2_LEFT
:
193 case WM8903_ANALOGUE_OUT2_RIGHT
:
194 case WM8903_ANALOGUE_OUT3_LEFT
:
195 case WM8903_ANALOGUE_OUT3_RIGHT
:
196 case WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0
:
197 case WM8903_DC_SERVO_0
:
198 case WM8903_DC_SERVO_2
:
199 case WM8903_DC_SERVO_READBACK_1
:
200 case WM8903_DC_SERVO_READBACK_2
:
201 case WM8903_DC_SERVO_READBACK_3
:
202 case WM8903_DC_SERVO_READBACK_4
:
203 case WM8903_ANALOGUE_HP_0
:
204 case WM8903_ANALOGUE_LINEOUT_0
:
205 case WM8903_CHARGE_PUMP_0
:
206 case WM8903_CLASS_W_0
:
207 case WM8903_WRITE_SEQUENCER_0
:
208 case WM8903_WRITE_SEQUENCER_1
:
209 case WM8903_WRITE_SEQUENCER_2
:
210 case WM8903_WRITE_SEQUENCER_3
:
211 case WM8903_WRITE_SEQUENCER_4
:
212 case WM8903_CONTROL_INTERFACE
:
213 case WM8903_GPIO_CONTROL_1
:
214 case WM8903_GPIO_CONTROL_2
:
215 case WM8903_GPIO_CONTROL_3
:
216 case WM8903_GPIO_CONTROL_4
:
217 case WM8903_GPIO_CONTROL_5
:
218 case WM8903_INTERRUPT_STATUS_1
:
219 case WM8903_INTERRUPT_STATUS_1_MASK
:
220 case WM8903_INTERRUPT_POLARITY_1
:
221 case WM8903_INTERRUPT_CONTROL
:
222 case WM8903_CLOCK_RATE_TEST_4
:
223 case WM8903_ANALOGUE_OUTPUT_BIAS_0
:
230 static bool wm8903_volatile_register(struct device
*dev
, unsigned int reg
)
233 case WM8903_SW_RESET_AND_ID
:
234 case WM8903_REVISION_NUMBER
:
235 case WM8903_INTERRUPT_STATUS_1
:
236 case WM8903_WRITE_SEQUENCER_4
:
237 case WM8903_DC_SERVO_READBACK_1
:
238 case WM8903_DC_SERVO_READBACK_2
:
239 case WM8903_DC_SERVO_READBACK_3
:
240 case WM8903_DC_SERVO_READBACK_4
:
248 static int wm8903_cp_event(struct snd_soc_dapm_widget
*w
,
249 struct snd_kcontrol
*kcontrol
, int event
)
251 WARN_ON(event
!= SND_SOC_DAPM_POST_PMU
);
257 static int wm8903_dcs_event(struct snd_soc_dapm_widget
*w
,
258 struct snd_kcontrol
*kcontrol
, int event
)
260 struct snd_soc_codec
*codec
= w
->codec
;
261 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
264 case SND_SOC_DAPM_POST_PMU
:
265 wm8903
->dcs_pending
|= 1 << w
->shift
;
267 case SND_SOC_DAPM_PRE_PMD
:
268 snd_soc_update_bits(codec
, WM8903_DC_SERVO_0
,
276 #define WM8903_DCS_MODE_WRITE_STOP 0
277 #define WM8903_DCS_MODE_START_STOP 2
279 static void wm8903_seq_notifier(struct snd_soc_dapm_context
*dapm
,
280 enum snd_soc_dapm_type event
, int subseq
)
282 struct snd_soc_codec
*codec
= container_of(dapm
,
283 struct snd_soc_codec
, dapm
);
284 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
285 int dcs_mode
= WM8903_DCS_MODE_WRITE_STOP
;
288 /* Complete any pending DC servo starts */
289 if (wm8903
->dcs_pending
) {
290 dev_dbg(codec
->dev
, "Starting DC servo for %x\n",
291 wm8903
->dcs_pending
);
293 /* If we've no cached values then we need to do startup */
294 for (i
= 0; i
< ARRAY_SIZE(wm8903
->dcs_cache
); i
++) {
295 if (!(wm8903
->dcs_pending
& (1 << i
)))
298 if (wm8903
->dcs_cache
[i
]) {
300 "Restore DC servo %d value %x\n",
301 3 - i
, wm8903
->dcs_cache
[i
]);
303 snd_soc_write(codec
, WM8903_DC_SERVO_4
+ i
,
304 wm8903
->dcs_cache
[i
] & 0xff);
307 "Calibrate DC servo %d\n", 3 - i
);
308 dcs_mode
= WM8903_DCS_MODE_START_STOP
;
312 /* Don't trust the cache for analogue */
313 if (wm8903
->class_w_users
)
314 dcs_mode
= WM8903_DCS_MODE_START_STOP
;
316 snd_soc_update_bits(codec
, WM8903_DC_SERVO_2
,
317 WM8903_DCS_MODE_MASK
, dcs_mode
);
319 snd_soc_update_bits(codec
, WM8903_DC_SERVO_0
,
320 WM8903_DCS_ENA_MASK
, wm8903
->dcs_pending
);
323 case WM8903_DCS_MODE_WRITE_STOP
:
326 case WM8903_DCS_MODE_START_STOP
:
329 /* Cache the measured offsets for digital */
330 if (wm8903
->class_w_users
)
333 for (i
= 0; i
< ARRAY_SIZE(wm8903
->dcs_cache
); i
++) {
334 if (!(wm8903
->dcs_pending
& (1 << i
)))
337 val
= snd_soc_read(codec
,
338 WM8903_DC_SERVO_READBACK_1
+ i
);
339 dev_dbg(codec
->dev
, "DC servo %d: %x\n",
341 wm8903
->dcs_cache
[i
] = val
;
346 pr_warn("DCS mode %d delay not set\n", dcs_mode
);
350 wm8903
->dcs_pending
= 0;
355 * When used with DAC outputs only the WM8903 charge pump supports
356 * operation in class W mode, providing very low power consumption
357 * when used with digital sources. Enable and disable this mode
358 * automatically depending on the mixer configuration.
360 * All the relevant controls are simple switches.
362 static int wm8903_class_w_put(struct snd_kcontrol
*kcontrol
,
363 struct snd_ctl_elem_value
*ucontrol
)
365 struct snd_soc_dapm_widget_list
*wlist
= snd_kcontrol_chip(kcontrol
);
366 struct snd_soc_dapm_widget
*widget
= wlist
->widgets
[0];
367 struct snd_soc_codec
*codec
= widget
->codec
;
368 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
372 reg
= snd_soc_read(codec
, WM8903_CLASS_W_0
);
374 /* Turn it off if we're about to enable bypass */
375 if (ucontrol
->value
.integer
.value
[0]) {
376 if (wm8903
->class_w_users
== 0) {
377 dev_dbg(codec
->dev
, "Disabling Class W\n");
378 snd_soc_write(codec
, WM8903_CLASS_W_0
, reg
&
379 ~(WM8903_CP_DYN_FREQ
| WM8903_CP_DYN_V
));
381 wm8903
->class_w_users
++;
384 /* Implement the change */
385 ret
= snd_soc_dapm_put_volsw(kcontrol
, ucontrol
);
387 /* If we've just disabled the last bypass path turn Class W on */
388 if (!ucontrol
->value
.integer
.value
[0]) {
389 if (wm8903
->class_w_users
== 1) {
390 dev_dbg(codec
->dev
, "Enabling Class W\n");
391 snd_soc_write(codec
, WM8903_CLASS_W_0
, reg
|
392 WM8903_CP_DYN_FREQ
| WM8903_CP_DYN_V
);
394 wm8903
->class_w_users
--;
397 dev_dbg(codec
->dev
, "Bypass use count now %d\n",
398 wm8903
->class_w_users
);
403 #define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
404 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
405 .info = snd_soc_info_volsw, \
406 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
407 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
410 static int wm8903_deemph
[] = { 0, 32000, 44100, 48000 };
412 static int wm8903_set_deemph(struct snd_soc_codec
*codec
)
414 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
417 /* If we're using deemphasis select the nearest available sample
420 if (wm8903
->deemph
) {
422 for (i
= 2; i
< ARRAY_SIZE(wm8903_deemph
); i
++) {
423 if (abs(wm8903_deemph
[i
] - wm8903
->fs
) <
424 abs(wm8903_deemph
[best
] - wm8903
->fs
))
428 val
= best
<< WM8903_DEEMPH_SHIFT
;
434 dev_dbg(codec
->dev
, "Set deemphasis %d (%dHz)\n",
435 best
, wm8903_deemph
[best
]);
437 return snd_soc_update_bits(codec
, WM8903_DAC_DIGITAL_1
,
438 WM8903_DEEMPH_MASK
, val
);
441 static int wm8903_get_deemph(struct snd_kcontrol
*kcontrol
,
442 struct snd_ctl_elem_value
*ucontrol
)
444 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
445 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
447 ucontrol
->value
.enumerated
.item
[0] = wm8903
->deemph
;
452 static int wm8903_put_deemph(struct snd_kcontrol
*kcontrol
,
453 struct snd_ctl_elem_value
*ucontrol
)
455 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
456 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
457 int deemph
= ucontrol
->value
.enumerated
.item
[0];
463 mutex_lock(&codec
->mutex
);
464 if (wm8903
->deemph
!= deemph
) {
465 wm8903
->deemph
= deemph
;
467 wm8903_set_deemph(codec
);
471 mutex_unlock(&codec
->mutex
);
476 /* ALSA can only do steps of .01dB */
477 static const DECLARE_TLV_DB_SCALE(digital_tlv
, -7200, 75, 1);
479 static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv
, -3600, 300, 0);
480 static const DECLARE_TLV_DB_SCALE(out_tlv
, -5700, 100, 0);
482 static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh
, 0, 75, 0);
483 static const DECLARE_TLV_DB_SCALE(drc_tlv_amp
, -2250, 75, 0);
484 static const DECLARE_TLV_DB_SCALE(drc_tlv_min
, 0, 600, 0);
485 static const DECLARE_TLV_DB_SCALE(drc_tlv_max
, 1200, 600, 0);
486 static const DECLARE_TLV_DB_SCALE(drc_tlv_startup
, -300, 50, 0);
488 static const char *hpf_mode_text
[] = {
489 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
492 static const struct soc_enum hpf_mode
=
493 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0
, 5, 4, hpf_mode_text
);
495 static const char *osr_text
[] = {
496 "Low power", "High performance"
499 static const struct soc_enum adc_osr
=
500 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0
, 0, 2, osr_text
);
502 static const struct soc_enum dac_osr
=
503 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1
, 0, 2, osr_text
);
505 static const char *drc_slope_text
[] = {
506 "1", "1/2", "1/4", "1/8", "1/16", "0"
509 static const struct soc_enum drc_slope_r0
=
510 SOC_ENUM_SINGLE(WM8903_DRC_2
, 3, 6, drc_slope_text
);
512 static const struct soc_enum drc_slope_r1
=
513 SOC_ENUM_SINGLE(WM8903_DRC_2
, 0, 6, drc_slope_text
);
515 static const char *drc_attack_text
[] = {
517 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
518 "46.4ms", "92.8ms", "185.6ms"
521 static const struct soc_enum drc_attack
=
522 SOC_ENUM_SINGLE(WM8903_DRC_1
, 12, 11, drc_attack_text
);
524 static const char *drc_decay_text
[] = {
525 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
529 static const struct soc_enum drc_decay
=
530 SOC_ENUM_SINGLE(WM8903_DRC_1
, 8, 9, drc_decay_text
);
532 static const char *drc_ff_delay_text
[] = {
533 "5 samples", "9 samples"
536 static const struct soc_enum drc_ff_delay
=
537 SOC_ENUM_SINGLE(WM8903_DRC_0
, 5, 2, drc_ff_delay_text
);
539 static const char *drc_qr_decay_text
[] = {
540 "0.725ms", "1.45ms", "5.8ms"
543 static const struct soc_enum drc_qr_decay
=
544 SOC_ENUM_SINGLE(WM8903_DRC_1
, 4, 3, drc_qr_decay_text
);
546 static const char *drc_smoothing_text
[] = {
547 "Low", "Medium", "High"
550 static const struct soc_enum drc_smoothing
=
551 SOC_ENUM_SINGLE(WM8903_DRC_0
, 11, 3, drc_smoothing_text
);
553 static const char *soft_mute_text
[] = {
554 "Fast (fs/2)", "Slow (fs/32)"
557 static const struct soc_enum soft_mute
=
558 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1
, 10, 2, soft_mute_text
);
560 static const char *mute_mode_text
[] = {
564 static const struct soc_enum mute_mode
=
565 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1
, 9, 2, mute_mode_text
);
567 static const char *companding_text
[] = {
571 static const struct soc_enum dac_companding
=
572 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 0, 2, companding_text
);
574 static const struct soc_enum adc_companding
=
575 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 2, 2, companding_text
);
577 static const char *input_mode_text
[] = {
578 "Single-Ended", "Differential Line", "Differential Mic"
581 static const struct soc_enum linput_mode_enum
=
582 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1
, 0, 3, input_mode_text
);
584 static const struct soc_enum rinput_mode_enum
=
585 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1
, 0, 3, input_mode_text
);
587 static const char *linput_mux_text
[] = {
588 "IN1L", "IN2L", "IN3L"
591 static const struct soc_enum linput_enum
=
592 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1
, 2, 3, linput_mux_text
);
594 static const struct soc_enum linput_inv_enum
=
595 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1
, 4, 3, linput_mux_text
);
597 static const char *rinput_mux_text
[] = {
598 "IN1R", "IN2R", "IN3R"
601 static const struct soc_enum rinput_enum
=
602 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1
, 2, 3, rinput_mux_text
);
604 static const struct soc_enum rinput_inv_enum
=
605 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1
, 4, 3, rinput_mux_text
);
608 static const char *sidetone_text
[] = {
609 "None", "Left", "Right"
612 static const struct soc_enum lsidetone_enum
=
613 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0
, 2, 3, sidetone_text
);
615 static const struct soc_enum rsidetone_enum
=
616 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0
, 0, 3, sidetone_text
);
618 static const char *adcinput_text
[] = {
622 static const struct soc_enum adcinput_enum
=
623 SOC_ENUM_SINGLE(WM8903_CLOCK_RATE_TEST_4
, 9, 2, adcinput_text
);
625 static const char *aif_text
[] = {
629 static const struct soc_enum lcapture_enum
=
630 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 7, 2, aif_text
);
632 static const struct soc_enum rcapture_enum
=
633 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 6, 2, aif_text
);
635 static const struct soc_enum lplay_enum
=
636 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 5, 2, aif_text
);
638 static const struct soc_enum rplay_enum
=
639 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 4, 2, aif_text
);
641 static const struct snd_kcontrol_new wm8903_snd_controls
[] = {
643 /* Input PGAs - No TLV since the scale depends on PGA mode */
644 SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0
,
646 SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0
,
648 SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1
,
651 SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0
,
653 SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0
,
655 SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1
,
659 SOC_ENUM("ADC OSR", adc_osr
),
660 SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0
, 4, 1, 0),
661 SOC_ENUM("HPF Mode", hpf_mode
),
662 SOC_SINGLE("DRC Switch", WM8903_DRC_0
, 15, 1, 0),
663 SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0
),
664 SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1
),
665 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3
, 5, 124, 1,
667 SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3
, 0, 30, 1, drc_tlv_amp
),
668 SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1
, 2, 3, 1, drc_tlv_min
),
669 SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1
, 0, 3, 0, drc_tlv_max
),
670 SOC_ENUM("DRC Attack Rate", drc_attack
),
671 SOC_ENUM("DRC Decay Rate", drc_decay
),
672 SOC_ENUM("DRC FF Delay", drc_ff_delay
),
673 SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0
, 1, 1, 0),
674 SOC_SINGLE("DRC QR Switch", WM8903_DRC_0
, 2, 1, 0),
675 SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0
, 6, 3, 0, drc_tlv_max
),
676 SOC_ENUM("DRC QR Decay Rate", drc_qr_decay
),
677 SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0
, 3, 1, 0),
678 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0
, 0, 1, 0),
679 SOC_ENUM("DRC Smoothing Threshold", drc_smoothing
),
680 SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0
, 6, 18, 0, drc_tlv_startup
),
682 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT
,
683 WM8903_ADC_DIGITAL_VOLUME_RIGHT
, 1, 120, 0, digital_tlv
),
684 SOC_ENUM("ADC Companding Mode", adc_companding
),
685 SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0
, 3, 1, 0),
687 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0
, 4, 8,
688 12, 0, digital_sidetone_tlv
),
691 SOC_ENUM("DAC OSR", dac_osr
),
692 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT
,
693 WM8903_DAC_DIGITAL_VOLUME_RIGHT
, 1, 120, 0, digital_tlv
),
694 SOC_ENUM("DAC Soft Mute Rate", soft_mute
),
695 SOC_ENUM("DAC Mute Mode", mute_mode
),
696 SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1
, 12, 1, 0),
697 SOC_ENUM("DAC Companding Mode", dac_companding
),
698 SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0
, 1, 1, 0),
699 SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
700 wm8903_get_deemph
, wm8903_put_deemph
),
703 SOC_DOUBLE_R("Headphone Switch",
704 WM8903_ANALOGUE_OUT1_LEFT
, WM8903_ANALOGUE_OUT1_RIGHT
,
706 SOC_DOUBLE_R("Headphone ZC Switch",
707 WM8903_ANALOGUE_OUT1_LEFT
, WM8903_ANALOGUE_OUT1_RIGHT
,
709 SOC_DOUBLE_R_TLV("Headphone Volume",
710 WM8903_ANALOGUE_OUT1_LEFT
, WM8903_ANALOGUE_OUT1_RIGHT
,
714 SOC_DOUBLE_R("Line Out Switch",
715 WM8903_ANALOGUE_OUT2_LEFT
, WM8903_ANALOGUE_OUT2_RIGHT
,
717 SOC_DOUBLE_R("Line Out ZC Switch",
718 WM8903_ANALOGUE_OUT2_LEFT
, WM8903_ANALOGUE_OUT2_RIGHT
,
720 SOC_DOUBLE_R_TLV("Line Out Volume",
721 WM8903_ANALOGUE_OUT2_LEFT
, WM8903_ANALOGUE_OUT2_RIGHT
,
725 SOC_DOUBLE_R("Speaker Switch",
726 WM8903_ANALOGUE_OUT3_LEFT
, WM8903_ANALOGUE_OUT3_RIGHT
, 8, 1, 1),
727 SOC_DOUBLE_R("Speaker ZC Switch",
728 WM8903_ANALOGUE_OUT3_LEFT
, WM8903_ANALOGUE_OUT3_RIGHT
, 6, 1, 0),
729 SOC_DOUBLE_R_TLV("Speaker Volume",
730 WM8903_ANALOGUE_OUT3_LEFT
, WM8903_ANALOGUE_OUT3_RIGHT
,
734 static const struct snd_kcontrol_new linput_mode_mux
=
735 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum
);
737 static const struct snd_kcontrol_new rinput_mode_mux
=
738 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum
);
740 static const struct snd_kcontrol_new linput_mux
=
741 SOC_DAPM_ENUM("Left Input Mux", linput_enum
);
743 static const struct snd_kcontrol_new linput_inv_mux
=
744 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum
);
746 static const struct snd_kcontrol_new rinput_mux
=
747 SOC_DAPM_ENUM("Right Input Mux", rinput_enum
);
749 static const struct snd_kcontrol_new rinput_inv_mux
=
750 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum
);
752 static const struct snd_kcontrol_new lsidetone_mux
=
753 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum
);
755 static const struct snd_kcontrol_new rsidetone_mux
=
756 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum
);
758 static const struct snd_kcontrol_new adcinput_mux
=
759 SOC_DAPM_ENUM("ADC Input", adcinput_enum
);
761 static const struct snd_kcontrol_new lcapture_mux
=
762 SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum
);
764 static const struct snd_kcontrol_new rcapture_mux
=
765 SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum
);
767 static const struct snd_kcontrol_new lplay_mux
=
768 SOC_DAPM_ENUM("Left Playback Mux", lplay_enum
);
770 static const struct snd_kcontrol_new rplay_mux
=
771 SOC_DAPM_ENUM("Right Playback Mux", rplay_enum
);
773 static const struct snd_kcontrol_new left_output_mixer
[] = {
774 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 3, 1, 0),
775 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 2, 1, 0),
776 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 1, 1, 0),
777 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 0, 1, 0),
780 static const struct snd_kcontrol_new right_output_mixer
[] = {
781 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 3, 1, 0),
782 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 2, 1, 0),
783 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 1, 1, 0),
784 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 0, 1, 0),
787 static const struct snd_kcontrol_new left_speaker_mixer
[] = {
788 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
, 3, 1, 0),
789 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
, 2, 1, 0),
790 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
, 1, 1, 0),
791 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
,
795 static const struct snd_kcontrol_new right_speaker_mixer
[] = {
796 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
, 3, 1, 0),
797 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
, 2, 1, 0),
798 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
,
800 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
,
804 static const struct snd_soc_dapm_widget wm8903_dapm_widgets
[] = {
805 SND_SOC_DAPM_INPUT("IN1L"),
806 SND_SOC_DAPM_INPUT("IN1R"),
807 SND_SOC_DAPM_INPUT("IN2L"),
808 SND_SOC_DAPM_INPUT("IN2R"),
809 SND_SOC_DAPM_INPUT("IN3L"),
810 SND_SOC_DAPM_INPUT("IN3R"),
811 SND_SOC_DAPM_INPUT("DMICDAT"),
813 SND_SOC_DAPM_OUTPUT("HPOUTL"),
814 SND_SOC_DAPM_OUTPUT("HPOUTR"),
815 SND_SOC_DAPM_OUTPUT("LINEOUTL"),
816 SND_SOC_DAPM_OUTPUT("LINEOUTR"),
817 SND_SOC_DAPM_OUTPUT("LOP"),
818 SND_SOC_DAPM_OUTPUT("LON"),
819 SND_SOC_DAPM_OUTPUT("ROP"),
820 SND_SOC_DAPM_OUTPUT("RON"),
822 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8903_MIC_BIAS_CONTROL_0
, 0, 0, NULL
, 0),
824 SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM
, 0, 0, &linput_mux
),
825 SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM
, 0, 0,
827 SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM
, 0, 0, &linput_mode_mux
),
829 SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM
, 0, 0, &rinput_mux
),
830 SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM
, 0, 0,
832 SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM
, 0, 0, &rinput_mode_mux
),
834 SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0
, 1, 0, NULL
, 0),
835 SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0
, 0, 0, NULL
, 0),
837 SND_SOC_DAPM_MUX("Left ADC Input", SND_SOC_NOPM
, 0, 0, &adcinput_mux
),
838 SND_SOC_DAPM_MUX("Right ADC Input", SND_SOC_NOPM
, 0, 0, &adcinput_mux
),
840 SND_SOC_DAPM_ADC("ADCL", NULL
, WM8903_POWER_MANAGEMENT_6
, 1, 0),
841 SND_SOC_DAPM_ADC("ADCR", NULL
, WM8903_POWER_MANAGEMENT_6
, 0, 0),
843 SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM
, 0, 0, &lcapture_mux
),
844 SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM
, 0, 0, &rcapture_mux
),
846 SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM
, 0, 0),
847 SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM
, 0, 0),
849 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM
, 0, 0, &lsidetone_mux
),
850 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM
, 0, 0, &rsidetone_mux
),
852 SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM
, 0, 0),
853 SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM
, 0, 0),
855 SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM
, 0, 0, &lplay_mux
),
856 SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM
, 0, 0, &rplay_mux
),
858 SND_SOC_DAPM_DAC("DACL", NULL
, WM8903_POWER_MANAGEMENT_6
, 3, 0),
859 SND_SOC_DAPM_DAC("DACR", NULL
, WM8903_POWER_MANAGEMENT_6
, 2, 0),
861 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1
, 1, 0,
862 left_output_mixer
, ARRAY_SIZE(left_output_mixer
)),
863 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1
, 0, 0,
864 right_output_mixer
, ARRAY_SIZE(right_output_mixer
)),
866 SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4
, 1, 0,
867 left_speaker_mixer
, ARRAY_SIZE(left_speaker_mixer
)),
868 SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4
, 0, 0,
869 right_speaker_mixer
, ARRAY_SIZE(right_speaker_mixer
)),
871 SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2
,
873 SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2
,
876 SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3
, 1, 0,
878 SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3
, 0, 0,
881 SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0
, 7, 0, NULL
, 0),
882 SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0
, 6, 0, NULL
, 0),
883 SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 2, WM8903_ANALOGUE_HP_0
, 5, 0, NULL
, 0),
884 SND_SOC_DAPM_PGA_S("HPL_ENA", 1, WM8903_ANALOGUE_HP_0
, 4, 0, NULL
, 0),
885 SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0
, 3, 0, NULL
, 0),
886 SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0
, 2, 0, NULL
, 0),
887 SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 2, WM8903_ANALOGUE_HP_0
, 1, 0, NULL
, 0),
888 SND_SOC_DAPM_PGA_S("HPR_ENA", 1, WM8903_ANALOGUE_HP_0
, 0, 0, NULL
, 0),
890 SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0
, 7, 0,
892 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0
, 6, 0,
894 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0
, 5, 0,
896 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA", 1, WM8903_ANALOGUE_LINEOUT_0
, 4, 0,
898 SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0
, 3, 0,
900 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0
, 2, 0,
902 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0
, 1, 0,
904 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA", 1, WM8903_ANALOGUE_LINEOUT_0
, 0, 0,
907 SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0
, 4, 0, NULL
, 0),
908 SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM
, 3, 0, wm8903_dcs_event
,
909 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
910 SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM
, 2, 0, wm8903_dcs_event
,
911 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
912 SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM
, 1, 0, wm8903_dcs_event
,
913 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
914 SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM
, 0, 0, wm8903_dcs_event
,
915 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
917 SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5
, 1, 0,
919 SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5
, 0, 0,
922 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0
, 0, 0,
923 wm8903_cp_event
, SND_SOC_DAPM_POST_PMU
),
924 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2
, 1, 0, NULL
, 0),
925 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2
, 2, 0, NULL
, 0),
928 static const struct snd_soc_dapm_route wm8903_intercon
[] = {
930 { "CLK_DSP", NULL
, "CLK_SYS" },
931 { "MICBIAS", NULL
, "CLK_SYS" },
932 { "HPL_DCS", NULL
, "CLK_SYS" },
933 { "HPR_DCS", NULL
, "CLK_SYS" },
934 { "LINEOUTL_DCS", NULL
, "CLK_SYS" },
935 { "LINEOUTR_DCS", NULL
, "CLK_SYS" },
937 { "Left Input Mux", "IN1L", "IN1L" },
938 { "Left Input Mux", "IN2L", "IN2L" },
939 { "Left Input Mux", "IN3L", "IN3L" },
941 { "Left Input Inverting Mux", "IN1L", "IN1L" },
942 { "Left Input Inverting Mux", "IN2L", "IN2L" },
943 { "Left Input Inverting Mux", "IN3L", "IN3L" },
945 { "Right Input Mux", "IN1R", "IN1R" },
946 { "Right Input Mux", "IN2R", "IN2R" },
947 { "Right Input Mux", "IN3R", "IN3R" },
949 { "Right Input Inverting Mux", "IN1R", "IN1R" },
950 { "Right Input Inverting Mux", "IN2R", "IN2R" },
951 { "Right Input Inverting Mux", "IN3R", "IN3R" },
953 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
954 { "Left Input Mode Mux", "Differential Line",
956 { "Left Input Mode Mux", "Differential Line",
957 "Left Input Inverting Mux" },
958 { "Left Input Mode Mux", "Differential Mic",
960 { "Left Input Mode Mux", "Differential Mic",
961 "Left Input Inverting Mux" },
963 { "Right Input Mode Mux", "Single-Ended",
964 "Right Input Inverting Mux" },
965 { "Right Input Mode Mux", "Differential Line",
967 { "Right Input Mode Mux", "Differential Line",
968 "Right Input Inverting Mux" },
969 { "Right Input Mode Mux", "Differential Mic",
971 { "Right Input Mode Mux", "Differential Mic",
972 "Right Input Inverting Mux" },
974 { "Left Input PGA", NULL
, "Left Input Mode Mux" },
975 { "Right Input PGA", NULL
, "Right Input Mode Mux" },
977 { "Left ADC Input", "ADC", "Left Input PGA" },
978 { "Left ADC Input", "DMIC", "DMICDAT" },
979 { "Right ADC Input", "ADC", "Right Input PGA" },
980 { "Right ADC Input", "DMIC", "DMICDAT" },
982 { "Left Capture Mux", "Left", "ADCL" },
983 { "Left Capture Mux", "Right", "ADCR" },
985 { "Right Capture Mux", "Left", "ADCL" },
986 { "Right Capture Mux", "Right", "ADCR" },
988 { "AIFTXL", NULL
, "Left Capture Mux" },
989 { "AIFTXR", NULL
, "Right Capture Mux" },
991 { "ADCL", NULL
, "Left ADC Input" },
992 { "ADCL", NULL
, "CLK_DSP" },
993 { "ADCR", NULL
, "Right ADC Input" },
994 { "ADCR", NULL
, "CLK_DSP" },
996 { "Left Playback Mux", "Left", "AIFRXL" },
997 { "Left Playback Mux", "Right", "AIFRXR" },
999 { "Right Playback Mux", "Left", "AIFRXL" },
1000 { "Right Playback Mux", "Right", "AIFRXR" },
1002 { "DACL Sidetone", "Left", "ADCL" },
1003 { "DACL Sidetone", "Right", "ADCR" },
1004 { "DACR Sidetone", "Left", "ADCL" },
1005 { "DACR Sidetone", "Right", "ADCR" },
1007 { "DACL", NULL
, "Left Playback Mux" },
1008 { "DACL", NULL
, "DACL Sidetone" },
1009 { "DACL", NULL
, "CLK_DSP" },
1011 { "DACR", NULL
, "Right Playback Mux" },
1012 { "DACR", NULL
, "DACR Sidetone" },
1013 { "DACR", NULL
, "CLK_DSP" },
1015 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1016 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1017 { "Left Output Mixer", "DACL Switch", "DACL" },
1018 { "Left Output Mixer", "DACR Switch", "DACR" },
1020 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1021 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1022 { "Right Output Mixer", "DACL Switch", "DACL" },
1023 { "Right Output Mixer", "DACR Switch", "DACR" },
1025 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1026 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1027 { "Left Speaker Mixer", "DACL Switch", "DACL" },
1028 { "Left Speaker Mixer", "DACR Switch", "DACR" },
1030 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1031 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1032 { "Right Speaker Mixer", "DACL Switch", "DACL" },
1033 { "Right Speaker Mixer", "DACR Switch", "DACR" },
1035 { "Left Line Output PGA", NULL
, "Left Output Mixer" },
1036 { "Right Line Output PGA", NULL
, "Right Output Mixer" },
1038 { "Left Headphone Output PGA", NULL
, "Left Output Mixer" },
1039 { "Right Headphone Output PGA", NULL
, "Right Output Mixer" },
1041 { "Left Speaker PGA", NULL
, "Left Speaker Mixer" },
1042 { "Right Speaker PGA", NULL
, "Right Speaker Mixer" },
1044 { "HPL_ENA", NULL
, "Left Headphone Output PGA" },
1045 { "HPR_ENA", NULL
, "Right Headphone Output PGA" },
1046 { "HPL_ENA_DLY", NULL
, "HPL_ENA" },
1047 { "HPR_ENA_DLY", NULL
, "HPR_ENA" },
1048 { "LINEOUTL_ENA", NULL
, "Left Line Output PGA" },
1049 { "LINEOUTR_ENA", NULL
, "Right Line Output PGA" },
1050 { "LINEOUTL_ENA_DLY", NULL
, "LINEOUTL_ENA" },
1051 { "LINEOUTR_ENA_DLY", NULL
, "LINEOUTR_ENA" },
1053 { "HPL_DCS", NULL
, "DCS Master" },
1054 { "HPR_DCS", NULL
, "DCS Master" },
1055 { "LINEOUTL_DCS", NULL
, "DCS Master" },
1056 { "LINEOUTR_DCS", NULL
, "DCS Master" },
1058 { "HPL_DCS", NULL
, "HPL_ENA_DLY" },
1059 { "HPR_DCS", NULL
, "HPR_ENA_DLY" },
1060 { "LINEOUTL_DCS", NULL
, "LINEOUTL_ENA_DLY" },
1061 { "LINEOUTR_DCS", NULL
, "LINEOUTR_ENA_DLY" },
1063 { "HPL_ENA_OUTP", NULL
, "HPL_DCS" },
1064 { "HPR_ENA_OUTP", NULL
, "HPR_DCS" },
1065 { "LINEOUTL_ENA_OUTP", NULL
, "LINEOUTL_DCS" },
1066 { "LINEOUTR_ENA_OUTP", NULL
, "LINEOUTR_DCS" },
1068 { "HPL_RMV_SHORT", NULL
, "HPL_ENA_OUTP" },
1069 { "HPR_RMV_SHORT", NULL
, "HPR_ENA_OUTP" },
1070 { "LINEOUTL_RMV_SHORT", NULL
, "LINEOUTL_ENA_OUTP" },
1071 { "LINEOUTR_RMV_SHORT", NULL
, "LINEOUTR_ENA_OUTP" },
1073 { "HPOUTL", NULL
, "HPL_RMV_SHORT" },
1074 { "HPOUTR", NULL
, "HPR_RMV_SHORT" },
1075 { "LINEOUTL", NULL
, "LINEOUTL_RMV_SHORT" },
1076 { "LINEOUTR", NULL
, "LINEOUTR_RMV_SHORT" },
1078 { "LOP", NULL
, "Left Speaker PGA" },
1079 { "LON", NULL
, "Left Speaker PGA" },
1081 { "ROP", NULL
, "Right Speaker PGA" },
1082 { "RON", NULL
, "Right Speaker PGA" },
1084 { "Left Headphone Output PGA", NULL
, "Charge Pump" },
1085 { "Right Headphone Output PGA", NULL
, "Charge Pump" },
1086 { "Left Line Output PGA", NULL
, "Charge Pump" },
1087 { "Right Line Output PGA", NULL
, "Charge Pump" },
1090 static int wm8903_set_bias_level(struct snd_soc_codec
*codec
,
1091 enum snd_soc_bias_level level
)
1094 case SND_SOC_BIAS_ON
:
1097 case SND_SOC_BIAS_PREPARE
:
1098 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1099 WM8903_VMID_RES_MASK
,
1100 WM8903_VMID_RES_50K
);
1103 case SND_SOC_BIAS_STANDBY
:
1104 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
1105 snd_soc_update_bits(codec
, WM8903_BIAS_CONTROL_0
,
1106 WM8903_POBCTRL
| WM8903_ISEL_MASK
|
1107 WM8903_STARTUP_BIAS_ENA
|
1110 (2 << WM8903_ISEL_SHIFT
) |
1111 WM8903_STARTUP_BIAS_ENA
);
1113 snd_soc_update_bits(codec
,
1114 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0
,
1115 WM8903_SPK_DISCHARGE
,
1116 WM8903_SPK_DISCHARGE
);
1120 snd_soc_update_bits(codec
, WM8903_POWER_MANAGEMENT_5
,
1121 WM8903_SPKL_ENA
| WM8903_SPKR_ENA
,
1122 WM8903_SPKL_ENA
| WM8903_SPKR_ENA
);
1124 snd_soc_update_bits(codec
,
1125 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0
,
1126 WM8903_SPK_DISCHARGE
, 0);
1128 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1129 WM8903_VMID_TIE_ENA
|
1131 WM8903_VMID_IO_ENA
|
1132 WM8903_VMID_SOFT_MASK
|
1133 WM8903_VMID_RES_MASK
|
1134 WM8903_VMID_BUF_ENA
,
1135 WM8903_VMID_TIE_ENA
|
1137 WM8903_VMID_IO_ENA
|
1138 (2 << WM8903_VMID_SOFT_SHIFT
) |
1139 WM8903_VMID_RES_250K
|
1140 WM8903_VMID_BUF_ENA
);
1144 snd_soc_update_bits(codec
, WM8903_POWER_MANAGEMENT_5
,
1145 WM8903_SPKL_ENA
| WM8903_SPKR_ENA
,
1148 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1149 WM8903_VMID_SOFT_MASK
, 0);
1151 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1152 WM8903_VMID_RES_MASK
,
1153 WM8903_VMID_RES_50K
);
1155 snd_soc_update_bits(codec
, WM8903_BIAS_CONTROL_0
,
1156 WM8903_BIAS_ENA
| WM8903_POBCTRL
,
1159 /* By default no bypass paths are enabled so
1160 * enable Class W support.
1162 dev_dbg(codec
->dev
, "Enabling Class W\n");
1163 snd_soc_update_bits(codec
, WM8903_CLASS_W_0
,
1164 WM8903_CP_DYN_FREQ
|
1166 WM8903_CP_DYN_FREQ
|
1170 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1171 WM8903_VMID_RES_MASK
,
1172 WM8903_VMID_RES_250K
);
1175 case SND_SOC_BIAS_OFF
:
1176 snd_soc_update_bits(codec
, WM8903_BIAS_CONTROL_0
,
1177 WM8903_BIAS_ENA
, 0);
1179 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1180 WM8903_VMID_SOFT_MASK
,
1181 2 << WM8903_VMID_SOFT_SHIFT
);
1183 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1184 WM8903_VMID_BUF_ENA
, 0);
1188 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1189 WM8903_VMID_TIE_ENA
| WM8903_BUFIO_ENA
|
1190 WM8903_VMID_IO_ENA
| WM8903_VMID_RES_MASK
|
1191 WM8903_VMID_SOFT_MASK
|
1192 WM8903_VMID_BUF_ENA
, 0);
1194 snd_soc_update_bits(codec
, WM8903_BIAS_CONTROL_0
,
1195 WM8903_STARTUP_BIAS_ENA
, 0);
1199 codec
->dapm
.bias_level
= level
;
1204 static int wm8903_set_dai_sysclk(struct snd_soc_dai
*codec_dai
,
1205 int clk_id
, unsigned int freq
, int dir
)
1207 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1208 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1210 wm8903
->sysclk
= freq
;
1215 static int wm8903_set_dai_fmt(struct snd_soc_dai
*codec_dai
,
1218 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1219 u16 aif1
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_1
);
1221 aif1
&= ~(WM8903_LRCLK_DIR
| WM8903_BCLK_DIR
| WM8903_AIF_FMT_MASK
|
1222 WM8903_AIF_LRCLK_INV
| WM8903_AIF_BCLK_INV
);
1224 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
1225 case SND_SOC_DAIFMT_CBS_CFS
:
1227 case SND_SOC_DAIFMT_CBS_CFM
:
1228 aif1
|= WM8903_LRCLK_DIR
;
1230 case SND_SOC_DAIFMT_CBM_CFM
:
1231 aif1
|= WM8903_LRCLK_DIR
| WM8903_BCLK_DIR
;
1233 case SND_SOC_DAIFMT_CBM_CFS
:
1234 aif1
|= WM8903_BCLK_DIR
;
1240 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1241 case SND_SOC_DAIFMT_DSP_A
:
1244 case SND_SOC_DAIFMT_DSP_B
:
1245 aif1
|= 0x3 | WM8903_AIF_LRCLK_INV
;
1247 case SND_SOC_DAIFMT_I2S
:
1250 case SND_SOC_DAIFMT_RIGHT_J
:
1253 case SND_SOC_DAIFMT_LEFT_J
:
1259 /* Clock inversion */
1260 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1261 case SND_SOC_DAIFMT_DSP_A
:
1262 case SND_SOC_DAIFMT_DSP_B
:
1263 /* frame inversion not valid for DSP modes */
1264 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1265 case SND_SOC_DAIFMT_NB_NF
:
1267 case SND_SOC_DAIFMT_IB_NF
:
1268 aif1
|= WM8903_AIF_BCLK_INV
;
1274 case SND_SOC_DAIFMT_I2S
:
1275 case SND_SOC_DAIFMT_RIGHT_J
:
1276 case SND_SOC_DAIFMT_LEFT_J
:
1277 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1278 case SND_SOC_DAIFMT_NB_NF
:
1280 case SND_SOC_DAIFMT_IB_IF
:
1281 aif1
|= WM8903_AIF_BCLK_INV
| WM8903_AIF_LRCLK_INV
;
1283 case SND_SOC_DAIFMT_IB_NF
:
1284 aif1
|= WM8903_AIF_BCLK_INV
;
1286 case SND_SOC_DAIFMT_NB_IF
:
1287 aif1
|= WM8903_AIF_LRCLK_INV
;
1297 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_1
, aif1
);
1302 static int wm8903_digital_mute(struct snd_soc_dai
*codec_dai
, int mute
)
1304 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1307 reg
= snd_soc_read(codec
, WM8903_DAC_DIGITAL_1
);
1310 reg
|= WM8903_DAC_MUTE
;
1312 reg
&= ~WM8903_DAC_MUTE
;
1314 snd_soc_write(codec
, WM8903_DAC_DIGITAL_1
, reg
);
1319 /* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1320 * for optimal performance so we list the lower rates first and match
1321 * on the last match we find. */
1327 } clk_sys_ratios
[] = {
1328 { 64, 0x0, 0x0, 1 },
1329 { 68, 0x0, 0x1, 1 },
1330 { 125, 0x0, 0x2, 1 },
1331 { 128, 0x1, 0x0, 1 },
1332 { 136, 0x1, 0x1, 1 },
1333 { 192, 0x2, 0x0, 1 },
1334 { 204, 0x2, 0x1, 1 },
1336 { 64, 0x0, 0x0, 2 },
1337 { 68, 0x0, 0x1, 2 },
1338 { 125, 0x0, 0x2, 2 },
1339 { 128, 0x1, 0x0, 2 },
1340 { 136, 0x1, 0x1, 2 },
1341 { 192, 0x2, 0x0, 2 },
1342 { 204, 0x2, 0x1, 2 },
1344 { 250, 0x2, 0x2, 1 },
1345 { 256, 0x3, 0x0, 1 },
1346 { 272, 0x3, 0x1, 1 },
1347 { 384, 0x4, 0x0, 1 },
1348 { 408, 0x4, 0x1, 1 },
1349 { 375, 0x4, 0x2, 1 },
1350 { 512, 0x5, 0x0, 1 },
1351 { 544, 0x5, 0x1, 1 },
1352 { 500, 0x5, 0x2, 1 },
1353 { 768, 0x6, 0x0, 1 },
1354 { 816, 0x6, 0x1, 1 },
1355 { 750, 0x6, 0x2, 1 },
1356 { 1024, 0x7, 0x0, 1 },
1357 { 1088, 0x7, 0x1, 1 },
1358 { 1000, 0x7, 0x2, 1 },
1359 { 1408, 0x8, 0x0, 1 },
1360 { 1496, 0x8, 0x1, 1 },
1361 { 1536, 0x9, 0x0, 1 },
1362 { 1632, 0x9, 0x1, 1 },
1363 { 1500, 0x9, 0x2, 1 },
1365 { 250, 0x2, 0x2, 2 },
1366 { 256, 0x3, 0x0, 2 },
1367 { 272, 0x3, 0x1, 2 },
1368 { 384, 0x4, 0x0, 2 },
1369 { 408, 0x4, 0x1, 2 },
1370 { 375, 0x4, 0x2, 2 },
1371 { 512, 0x5, 0x0, 2 },
1372 { 544, 0x5, 0x1, 2 },
1373 { 500, 0x5, 0x2, 2 },
1374 { 768, 0x6, 0x0, 2 },
1375 { 816, 0x6, 0x1, 2 },
1376 { 750, 0x6, 0x2, 2 },
1377 { 1024, 0x7, 0x0, 2 },
1378 { 1088, 0x7, 0x1, 2 },
1379 { 1000, 0x7, 0x2, 2 },
1380 { 1408, 0x8, 0x0, 2 },
1381 { 1496, 0x8, 0x1, 2 },
1382 { 1536, 0x9, 0x0, 2 },
1383 { 1632, 0x9, 0x1, 2 },
1384 { 1500, 0x9, 0x2, 2 },
1387 /* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1411 /* Sample rates for DSP */
1415 } sample_rates
[] = {
1430 static int wm8903_hw_params(struct snd_pcm_substream
*substream
,
1431 struct snd_pcm_hw_params
*params
,
1432 struct snd_soc_dai
*dai
)
1434 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
1435 struct snd_soc_codec
*codec
=rtd
->codec
;
1436 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1437 int fs
= params_rate(params
);
1447 u16 aif1
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_1
);
1448 u16 aif2
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_2
);
1449 u16 aif3
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_3
);
1450 u16 clock0
= snd_soc_read(codec
, WM8903_CLOCK_RATES_0
);
1451 u16 clock1
= snd_soc_read(codec
, WM8903_CLOCK_RATES_1
);
1452 u16 dac_digital1
= snd_soc_read(codec
, WM8903_DAC_DIGITAL_1
);
1454 /* Enable sloping stopband filter for low sample rates */
1456 dac_digital1
|= WM8903_DAC_SB_FILT
;
1458 dac_digital1
&= ~WM8903_DAC_SB_FILT
;
1460 /* Configure sample rate logic for DSP - choose nearest rate */
1462 best_val
= abs(sample_rates
[dsp_config
].rate
- fs
);
1463 for (i
= 1; i
< ARRAY_SIZE(sample_rates
); i
++) {
1464 cur_val
= abs(sample_rates
[i
].rate
- fs
);
1465 if (cur_val
<= best_val
) {
1471 dev_dbg(codec
->dev
, "DSP fs = %dHz\n", sample_rates
[dsp_config
].rate
);
1472 clock1
&= ~WM8903_SAMPLE_RATE_MASK
;
1473 clock1
|= sample_rates
[dsp_config
].value
;
1475 aif1
&= ~WM8903_AIF_WL_MASK
;
1477 switch (params_format(params
)) {
1478 case SNDRV_PCM_FORMAT_S16_LE
:
1481 case SNDRV_PCM_FORMAT_S20_3LE
:
1485 case SNDRV_PCM_FORMAT_S24_LE
:
1489 case SNDRV_PCM_FORMAT_S32_LE
:
1497 dev_dbg(codec
->dev
, "MCLK = %dHz, target sample rate = %dHz\n",
1498 wm8903
->sysclk
, fs
);
1500 /* We may not have an MCLK which allows us to generate exactly
1501 * the clock we want, particularly with USB derived inputs, so
1505 best_val
= abs((wm8903
->sysclk
/
1506 (clk_sys_ratios
[0].mclk_div
*
1507 clk_sys_ratios
[0].div
)) - fs
);
1508 for (i
= 1; i
< ARRAY_SIZE(clk_sys_ratios
); i
++) {
1509 cur_val
= abs((wm8903
->sysclk
/
1510 (clk_sys_ratios
[i
].mclk_div
*
1511 clk_sys_ratios
[i
].div
)) - fs
);
1513 if (cur_val
<= best_val
) {
1519 if (clk_sys_ratios
[clk_config
].mclk_div
== 2) {
1520 clock0
|= WM8903_MCLKDIV2
;
1521 clk_sys
= wm8903
->sysclk
/ 2;
1523 clock0
&= ~WM8903_MCLKDIV2
;
1524 clk_sys
= wm8903
->sysclk
;
1527 clock1
&= ~(WM8903_CLK_SYS_RATE_MASK
|
1528 WM8903_CLK_SYS_MODE_MASK
);
1529 clock1
|= clk_sys_ratios
[clk_config
].rate
<< WM8903_CLK_SYS_RATE_SHIFT
;
1530 clock1
|= clk_sys_ratios
[clk_config
].mode
<< WM8903_CLK_SYS_MODE_SHIFT
;
1532 dev_dbg(codec
->dev
, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
1533 clk_sys_ratios
[clk_config
].rate
,
1534 clk_sys_ratios
[clk_config
].mode
,
1535 clk_sys_ratios
[clk_config
].div
);
1537 dev_dbg(codec
->dev
, "Actual CLK_SYS = %dHz\n", clk_sys
);
1539 /* We may not get quite the right frequency if using
1540 * approximate clocks so look for the closest match that is
1541 * higher than the target (we need to ensure that there enough
1542 * BCLKs to clock out the samples).
1545 best_val
= ((clk_sys
* 10) / bclk_divs
[0].ratio
) - bclk
;
1547 while (i
< ARRAY_SIZE(bclk_divs
)) {
1548 cur_val
= ((clk_sys
* 10) / bclk_divs
[i
].ratio
) - bclk
;
1549 if (cur_val
< 0) /* BCLK table is sorted */
1556 aif2
&= ~WM8903_BCLK_DIV_MASK
;
1557 aif3
&= ~WM8903_LRCLK_RATE_MASK
;
1559 dev_dbg(codec
->dev
, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
1560 bclk_divs
[bclk_div
].ratio
/ 10, bclk
,
1561 (clk_sys
* 10) / bclk_divs
[bclk_div
].ratio
);
1563 aif2
|= bclk_divs
[bclk_div
].div
;
1566 wm8903
->fs
= params_rate(params
);
1567 wm8903_set_deemph(codec
);
1569 snd_soc_write(codec
, WM8903_CLOCK_RATES_0
, clock0
);
1570 snd_soc_write(codec
, WM8903_CLOCK_RATES_1
, clock1
);
1571 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_1
, aif1
);
1572 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_2
, aif2
);
1573 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_3
, aif3
);
1574 snd_soc_write(codec
, WM8903_DAC_DIGITAL_1
, dac_digital1
);
1580 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1582 * @codec: WM8903 codec
1583 * @jack: jack to report detection events on
1584 * @det: value to report for presence detection
1585 * @shrt: value to report for short detection
1587 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1588 * being used to bring out signals to the processor then only platform
1589 * data configuration is needed for WM8903 and processor GPIOs should
1590 * be configured using snd_soc_jack_add_gpios() instead.
1592 * The current threasholds for detection should be configured using
1593 * micdet_cfg in the platform data. Using this function will force on
1594 * the microphone bias for the device.
1596 int wm8903_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
1599 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1600 int irq_mask
= WM8903_MICDET_EINT
| WM8903_MICSHRT_EINT
;
1602 dev_dbg(codec
->dev
, "Enabling microphone detection: %x %x\n",
1605 /* Store the configuration */
1606 wm8903
->mic_jack
= jack
;
1607 wm8903
->mic_det
= det
;
1608 wm8903
->mic_short
= shrt
;
1610 /* Enable interrupts we've got a report configured for */
1612 irq_mask
&= ~WM8903_MICDET_EINT
;
1614 irq_mask
&= ~WM8903_MICSHRT_EINT
;
1616 snd_soc_update_bits(codec
, WM8903_INTERRUPT_STATUS_1_MASK
,
1617 WM8903_MICDET_EINT
| WM8903_MICSHRT_EINT
,
1621 /* Enable mic detection, this may not have been set through
1622 * platform data (eg, if the defaults are OK). */
1623 snd_soc_update_bits(codec
, WM8903_WRITE_SEQUENCER_0
,
1624 WM8903_WSEQ_ENA
, WM8903_WSEQ_ENA
);
1625 snd_soc_update_bits(codec
, WM8903_MIC_BIAS_CONTROL_0
,
1626 WM8903_MICDET_ENA
, WM8903_MICDET_ENA
);
1628 snd_soc_update_bits(codec
, WM8903_MIC_BIAS_CONTROL_0
,
1629 WM8903_MICDET_ENA
, 0);
1634 EXPORT_SYMBOL_GPL(wm8903_mic_detect
);
1636 static irqreturn_t
wm8903_irq(int irq
, void *data
)
1638 struct snd_soc_codec
*codec
= data
;
1639 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1643 int mask
= ~snd_soc_read(codec
, WM8903_INTERRUPT_STATUS_1_MASK
);
1645 int_val
= snd_soc_read(codec
, WM8903_INTERRUPT_STATUS_1
) & mask
;
1647 if (int_val
& WM8903_WSEQ_BUSY_EINT
) {
1648 dev_warn(codec
->dev
, "Write sequencer done\n");
1652 * The rest is microphone jack detection. We need to manually
1653 * invert the polarity of the interrupt after each event - to
1654 * simplify the code keep track of the last state we reported
1655 * and just invert the relevant bits in both the report and
1656 * the polarity register.
1658 mic_report
= wm8903
->mic_last_report
;
1659 int_pol
= snd_soc_read(codec
, WM8903_INTERRUPT_POLARITY_1
);
1661 #ifndef CONFIG_SND_SOC_WM8903_MODULE
1662 if (int_val
& (WM8903_MICSHRT_EINT
| WM8903_MICDET_EINT
))
1663 trace_snd_soc_jack_irq(dev_name(codec
->dev
));
1666 if (int_val
& WM8903_MICSHRT_EINT
) {
1667 dev_dbg(codec
->dev
, "Microphone short (pol=%x)\n", int_pol
);
1669 mic_report
^= wm8903
->mic_short
;
1670 int_pol
^= WM8903_MICSHRT_INV
;
1673 if (int_val
& WM8903_MICDET_EINT
) {
1674 dev_dbg(codec
->dev
, "Microphone detect (pol=%x)\n", int_pol
);
1676 mic_report
^= wm8903
->mic_det
;
1677 int_pol
^= WM8903_MICDET_INV
;
1679 msleep(wm8903
->mic_delay
);
1682 snd_soc_update_bits(codec
, WM8903_INTERRUPT_POLARITY_1
,
1683 WM8903_MICSHRT_INV
| WM8903_MICDET_INV
, int_pol
);
1685 snd_soc_jack_report(wm8903
->mic_jack
, mic_report
,
1686 wm8903
->mic_short
| wm8903
->mic_det
);
1688 wm8903
->mic_last_report
= mic_report
;
1693 #define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1694 SNDRV_PCM_RATE_11025 | \
1695 SNDRV_PCM_RATE_16000 | \
1696 SNDRV_PCM_RATE_22050 | \
1697 SNDRV_PCM_RATE_32000 | \
1698 SNDRV_PCM_RATE_44100 | \
1699 SNDRV_PCM_RATE_48000 | \
1700 SNDRV_PCM_RATE_88200 | \
1701 SNDRV_PCM_RATE_96000)
1703 #define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1704 SNDRV_PCM_RATE_11025 | \
1705 SNDRV_PCM_RATE_16000 | \
1706 SNDRV_PCM_RATE_22050 | \
1707 SNDRV_PCM_RATE_32000 | \
1708 SNDRV_PCM_RATE_44100 | \
1709 SNDRV_PCM_RATE_48000)
1711 #define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1712 SNDRV_PCM_FMTBIT_S20_3LE |\
1713 SNDRV_PCM_FMTBIT_S24_LE)
1715 static const struct snd_soc_dai_ops wm8903_dai_ops
= {
1716 .hw_params
= wm8903_hw_params
,
1717 .digital_mute
= wm8903_digital_mute
,
1718 .set_fmt
= wm8903_set_dai_fmt
,
1719 .set_sysclk
= wm8903_set_dai_sysclk
,
1722 static struct snd_soc_dai_driver wm8903_dai
= {
1723 .name
= "wm8903-hifi",
1725 .stream_name
= "Playback",
1728 .rates
= WM8903_PLAYBACK_RATES
,
1729 .formats
= WM8903_FORMATS
,
1732 .stream_name
= "Capture",
1735 .rates
= WM8903_CAPTURE_RATES
,
1736 .formats
= WM8903_FORMATS
,
1738 .ops
= &wm8903_dai_ops
,
1739 .symmetric_rates
= 1,
1742 static int wm8903_suspend(struct snd_soc_codec
*codec
)
1744 wm8903_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1749 static int wm8903_resume(struct snd_soc_codec
*codec
)
1751 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1753 regcache_sync(wm8903
->regmap
);
1755 wm8903_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1760 #ifdef CONFIG_GPIOLIB
1761 static inline struct wm8903_priv
*gpio_to_wm8903(struct gpio_chip
*chip
)
1763 return container_of(chip
, struct wm8903_priv
, gpio_chip
);
1766 static int wm8903_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
1768 if (offset
>= WM8903_NUM_GPIO
)
1774 static int wm8903_gpio_direction_in(struct gpio_chip
*chip
, unsigned offset
)
1776 struct wm8903_priv
*wm8903
= gpio_to_wm8903(chip
);
1777 struct snd_soc_codec
*codec
= wm8903
->codec
;
1778 unsigned int mask
, val
;
1780 mask
= WM8903_GP1_FN_MASK
| WM8903_GP1_DIR_MASK
;
1781 val
= (WM8903_GPn_FN_GPIO_INPUT
<< WM8903_GP1_FN_SHIFT
) |
1784 return snd_soc_update_bits(codec
, WM8903_GPIO_CONTROL_1
+ offset
,
1788 static int wm8903_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
1790 struct wm8903_priv
*wm8903
= gpio_to_wm8903(chip
);
1791 struct snd_soc_codec
*codec
= wm8903
->codec
;
1794 reg
= snd_soc_read(codec
, WM8903_GPIO_CONTROL_1
+ offset
);
1796 return (reg
& WM8903_GP1_LVL_MASK
) >> WM8903_GP1_LVL_SHIFT
;
1799 static int wm8903_gpio_direction_out(struct gpio_chip
*chip
,
1800 unsigned offset
, int value
)
1802 struct wm8903_priv
*wm8903
= gpio_to_wm8903(chip
);
1803 struct snd_soc_codec
*codec
= wm8903
->codec
;
1804 unsigned int mask
, val
;
1806 mask
= WM8903_GP1_FN_MASK
| WM8903_GP1_DIR_MASK
| WM8903_GP1_LVL_MASK
;
1807 val
= (WM8903_GPn_FN_GPIO_OUTPUT
<< WM8903_GP1_FN_SHIFT
) |
1808 (value
<< WM8903_GP2_LVL_SHIFT
);
1810 return snd_soc_update_bits(codec
, WM8903_GPIO_CONTROL_1
+ offset
,
1814 static void wm8903_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
1816 struct wm8903_priv
*wm8903
= gpio_to_wm8903(chip
);
1817 struct snd_soc_codec
*codec
= wm8903
->codec
;
1819 snd_soc_update_bits(codec
, WM8903_GPIO_CONTROL_1
+ offset
,
1820 WM8903_GP1_LVL_MASK
,
1821 !!value
<< WM8903_GP1_LVL_SHIFT
);
1824 static struct gpio_chip wm8903_template_chip
= {
1826 .owner
= THIS_MODULE
,
1827 .request
= wm8903_gpio_request
,
1828 .direction_input
= wm8903_gpio_direction_in
,
1829 .get
= wm8903_gpio_get
,
1830 .direction_output
= wm8903_gpio_direction_out
,
1831 .set
= wm8903_gpio_set
,
1835 static void wm8903_init_gpio(struct snd_soc_codec
*codec
)
1837 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1838 struct wm8903_platform_data
*pdata
= wm8903
->pdata
;
1841 wm8903
->gpio_chip
= wm8903_template_chip
;
1842 wm8903
->gpio_chip
.ngpio
= WM8903_NUM_GPIO
;
1843 wm8903
->gpio_chip
.dev
= codec
->dev
;
1845 if (pdata
&& pdata
->gpio_base
)
1846 wm8903
->gpio_chip
.base
= pdata
->gpio_base
;
1848 wm8903
->gpio_chip
.base
= -1;
1850 ret
= gpiochip_add(&wm8903
->gpio_chip
);
1852 dev_err(codec
->dev
, "Failed to add GPIOs: %d\n", ret
);
1855 static void wm8903_free_gpio(struct snd_soc_codec
*codec
)
1857 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1860 ret
= gpiochip_remove(&wm8903
->gpio_chip
);
1862 dev_err(codec
->dev
, "Failed to remove GPIOs: %d\n", ret
);
1865 static void wm8903_init_gpio(struct snd_soc_codec
*codec
)
1869 static void wm8903_free_gpio(struct snd_soc_codec
*codec
)
1874 static int wm8903_probe(struct snd_soc_codec
*codec
)
1876 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1877 struct wm8903_platform_data
*pdata
= wm8903
->pdata
;
1879 int trigger
, irq_pol
;
1882 wm8903
->codec
= codec
;
1883 codec
->control_data
= wm8903
->regmap
;
1885 ret
= snd_soc_codec_set_cache_io(codec
, 8, 16, SND_SOC_REGMAP
);
1887 dev_err(codec
->dev
, "Failed to set cache I/O: %d\n", ret
);
1891 /* Set up GPIOs and microphone detection */
1893 bool mic_gpio
= false;
1895 for (i
= 0; i
< ARRAY_SIZE(pdata
->gpio_cfg
); i
++) {
1896 if (pdata
->gpio_cfg
[i
] > 0x7fff)
1899 snd_soc_write(codec
, WM8903_GPIO_CONTROL_1
+ i
,
1900 pdata
->gpio_cfg
[i
] & 0x7fff);
1902 val
= (pdata
->gpio_cfg
[i
] & WM8903_GP1_FN_MASK
)
1903 >> WM8903_GP1_FN_SHIFT
;
1906 case WM8903_GPn_FN_MICBIAS_CURRENT_DETECT
:
1907 case WM8903_GPn_FN_MICBIAS_SHORT_DETECT
:
1915 snd_soc_write(codec
, WM8903_MIC_BIAS_CONTROL_0
,
1918 /* Microphone detection needs the WSEQ clock */
1919 if (pdata
->micdet_cfg
)
1920 snd_soc_update_bits(codec
, WM8903_WRITE_SEQUENCER_0
,
1921 WM8903_WSEQ_ENA
, WM8903_WSEQ_ENA
);
1923 /* If microphone detection is enabled by pdata but
1924 * detected via IRQ then interrupts can be lost before
1925 * the machine driver has set up microphone detection
1926 * IRQs as the IRQs are clear on read. The detection
1927 * will be enabled when the machine driver configures.
1929 WARN_ON(!mic_gpio
&& (pdata
->micdet_cfg
& WM8903_MICDET_ENA
));
1931 wm8903
->mic_delay
= pdata
->micdet_delay
;
1935 if (pdata
&& pdata
->irq_active_low
) {
1936 trigger
= IRQF_TRIGGER_LOW
;
1937 irq_pol
= WM8903_IRQ_POL
;
1939 trigger
= IRQF_TRIGGER_HIGH
;
1943 snd_soc_update_bits(codec
, WM8903_INTERRUPT_CONTROL
,
1944 WM8903_IRQ_POL
, irq_pol
);
1946 ret
= request_threaded_irq(wm8903
->irq
, NULL
, wm8903_irq
,
1947 trigger
| IRQF_ONESHOT
,
1950 dev_err(codec
->dev
, "Failed to request IRQ: %d\n",
1955 /* Enable write sequencer interrupts */
1956 snd_soc_update_bits(codec
, WM8903_INTERRUPT_STATUS_1_MASK
,
1957 WM8903_IM_WSEQ_BUSY_EINT
, 0);
1960 /* power on device */
1961 wm8903_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1963 /* Latch volume update bits */
1964 val
= snd_soc_read(codec
, WM8903_ADC_DIGITAL_VOLUME_LEFT
);
1965 val
|= WM8903_ADCVU
;
1966 snd_soc_write(codec
, WM8903_ADC_DIGITAL_VOLUME_LEFT
, val
);
1967 snd_soc_write(codec
, WM8903_ADC_DIGITAL_VOLUME_RIGHT
, val
);
1969 val
= snd_soc_read(codec
, WM8903_DAC_DIGITAL_VOLUME_LEFT
);
1970 val
|= WM8903_DACVU
;
1971 snd_soc_write(codec
, WM8903_DAC_DIGITAL_VOLUME_LEFT
, val
);
1972 snd_soc_write(codec
, WM8903_DAC_DIGITAL_VOLUME_RIGHT
, val
);
1974 val
= snd_soc_read(codec
, WM8903_ANALOGUE_OUT1_LEFT
);
1975 val
|= WM8903_HPOUTVU
;
1976 snd_soc_write(codec
, WM8903_ANALOGUE_OUT1_LEFT
, val
);
1977 snd_soc_write(codec
, WM8903_ANALOGUE_OUT1_RIGHT
, val
);
1979 val
= snd_soc_read(codec
, WM8903_ANALOGUE_OUT2_LEFT
);
1980 val
|= WM8903_LINEOUTVU
;
1981 snd_soc_write(codec
, WM8903_ANALOGUE_OUT2_LEFT
, val
);
1982 snd_soc_write(codec
, WM8903_ANALOGUE_OUT2_RIGHT
, val
);
1984 val
= snd_soc_read(codec
, WM8903_ANALOGUE_OUT3_LEFT
);
1985 val
|= WM8903_SPKVU
;
1986 snd_soc_write(codec
, WM8903_ANALOGUE_OUT3_LEFT
, val
);
1987 snd_soc_write(codec
, WM8903_ANALOGUE_OUT3_RIGHT
, val
);
1989 /* Enable DAC soft mute by default */
1990 snd_soc_update_bits(codec
, WM8903_DAC_DIGITAL_1
,
1991 WM8903_DAC_MUTEMODE
| WM8903_DAC_MUTE
,
1992 WM8903_DAC_MUTEMODE
| WM8903_DAC_MUTE
);
1994 wm8903_init_gpio(codec
);
1999 /* power down chip */
2000 static int wm8903_remove(struct snd_soc_codec
*codec
)
2002 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
2004 wm8903_free_gpio(codec
);
2005 wm8903_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
2007 free_irq(wm8903
->irq
, codec
);
2012 static struct snd_soc_codec_driver soc_codec_dev_wm8903
= {
2013 .probe
= wm8903_probe
,
2014 .remove
= wm8903_remove
,
2015 .suspend
= wm8903_suspend
,
2016 .resume
= wm8903_resume
,
2017 .set_bias_level
= wm8903_set_bias_level
,
2018 .seq_notifier
= wm8903_seq_notifier
,
2019 .controls
= wm8903_snd_controls
,
2020 .num_controls
= ARRAY_SIZE(wm8903_snd_controls
),
2021 .dapm_widgets
= wm8903_dapm_widgets
,
2022 .num_dapm_widgets
= ARRAY_SIZE(wm8903_dapm_widgets
),
2023 .dapm_routes
= wm8903_intercon
,
2024 .num_dapm_routes
= ARRAY_SIZE(wm8903_intercon
),
2027 static const struct regmap_config wm8903_regmap
= {
2031 .max_register
= WM8903_MAX_REGISTER
,
2032 .volatile_reg
= wm8903_volatile_register
,
2033 .readable_reg
= wm8903_readable_register
,
2035 .cache_type
= REGCACHE_RBTREE
,
2036 .reg_defaults
= wm8903_reg_defaults
,
2037 .num_reg_defaults
= ARRAY_SIZE(wm8903_reg_defaults
),
2040 static __devinit
int wm8903_i2c_probe(struct i2c_client
*i2c
,
2041 const struct i2c_device_id
*id
)
2043 struct wm8903_platform_data
*pdata
= dev_get_platdata(&i2c
->dev
);
2044 struct wm8903_priv
*wm8903
;
2048 wm8903
= devm_kzalloc(&i2c
->dev
, sizeof(struct wm8903_priv
),
2053 wm8903
->regmap
= regmap_init_i2c(i2c
, &wm8903_regmap
);
2054 if (IS_ERR(wm8903
->regmap
)) {
2055 ret
= PTR_ERR(wm8903
->regmap
);
2056 dev_err(&i2c
->dev
, "Failed to allocate register map: %d\n",
2061 i2c_set_clientdata(i2c
, wm8903
);
2062 wm8903
->irq
= i2c
->irq
;
2064 /* If no platform data was supplied, create storage for defaults */
2066 wm8903
->pdata
= pdata
;
2068 wm8903
->pdata
= devm_kzalloc(&i2c
->dev
,
2069 sizeof(struct wm8903_platform_data
),
2071 if (wm8903
->pdata
== NULL
) {
2072 dev_err(&i2c
->dev
, "Failed to allocate pdata\n");
2077 ret
= regmap_read(wm8903
->regmap
, WM8903_SW_RESET_AND_ID
, &val
);
2079 dev_err(&i2c
->dev
, "Failed to read chip ID: %d\n", ret
);
2082 if (val
!= 0x8903) {
2083 dev_err(&i2c
->dev
, "Device with ID %x is not a WM8903\n", val
);
2088 ret
= regmap_read(wm8903
->regmap
, WM8903_REVISION_NUMBER
, &val
);
2090 dev_err(&i2c
->dev
, "Failed to read chip revision: %d\n", ret
);
2093 dev_info(&i2c
->dev
, "WM8903 revision %c\n",
2094 (val
& WM8903_CHIP_REV_MASK
) + 'A');
2096 /* Reset the device */
2097 regmap_write(wm8903
->regmap
, WM8903_SW_RESET_AND_ID
, 0x8903);
2099 ret
= snd_soc_register_codec(&i2c
->dev
,
2100 &soc_codec_dev_wm8903
, &wm8903_dai
, 1);
2106 regmap_exit(wm8903
->regmap
);
2110 static __devexit
int wm8903_i2c_remove(struct i2c_client
*client
)
2112 struct wm8903_priv
*wm8903
= i2c_get_clientdata(client
);
2114 regmap_exit(wm8903
->regmap
);
2115 snd_soc_unregister_codec(&client
->dev
);
2120 static const struct i2c_device_id wm8903_i2c_id
[] = {
2124 MODULE_DEVICE_TABLE(i2c
, wm8903_i2c_id
);
2126 static struct i2c_driver wm8903_i2c_driver
= {
2129 .owner
= THIS_MODULE
,
2131 .probe
= wm8903_i2c_probe
,
2132 .remove
= __devexit_p(wm8903_i2c_remove
),
2133 .id_table
= wm8903_i2c_id
,
2136 static int __init
wm8903_modinit(void)
2139 ret
= i2c_add_driver(&wm8903_i2c_driver
);
2141 printk(KERN_ERR
"Failed to register wm8903 I2C driver: %d\n",
2146 module_init(wm8903_modinit
);
2148 static void __exit
wm8903_exit(void)
2150 i2c_del_driver(&wm8903_i2c_driver
);
2152 module_exit(wm8903_exit
);
2154 MODULE_DESCRIPTION("ASoC WM8903 driver");
2155 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
2156 MODULE_LICENSE("GPL");