2 * wm8903.c -- WM8903 ALSA SoC Audio driver
4 * Copyright 2008 Wolfson Microelectronics
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * - TDM mode configuration.
14 * - Digital microphone support.
17 #include <linux/module.h>
18 #include <linux/moduleparam.h>
19 #include <linux/init.h>
20 #include <linux/completion.h>
21 #include <linux/delay.h>
23 #include <linux/i2c.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26 #include <sound/core.h>
27 #include <sound/jack.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/tlv.h>
31 #include <sound/soc.h>
32 #include <sound/initval.h>
33 #include <sound/wm8903.h>
34 #include <trace/events/asoc.h>
38 /* Register defaults at reset */
39 static u16 wm8903_reg_defaults
[] = {
40 0x8903, /* R0 - SW Reset and ID */
41 0x0000, /* R1 - Revision Number */
44 0x0018, /* R4 - Bias Control 0 */
45 0x0000, /* R5 - VMID Control 0 */
46 0x0000, /* R6 - Mic Bias Control 0 */
48 0x0001, /* R8 - Analogue DAC 0 */
50 0x0001, /* R10 - Analogue ADC 0 */
52 0x0000, /* R12 - Power Management 0 */
53 0x0000, /* R13 - Power Management 1 */
54 0x0000, /* R14 - Power Management 2 */
55 0x0000, /* R15 - Power Management 3 */
56 0x0000, /* R16 - Power Management 4 */
57 0x0000, /* R17 - Power Management 5 */
58 0x0000, /* R18 - Power Management 6 */
60 0x0400, /* R20 - Clock Rates 0 */
61 0x0D07, /* R21 - Clock Rates 1 */
62 0x0000, /* R22 - Clock Rates 2 */
64 0x0050, /* R24 - Audio Interface 0 */
65 0x0242, /* R25 - Audio Interface 1 */
66 0x0008, /* R26 - Audio Interface 2 */
67 0x0022, /* R27 - Audio Interface 3 */
70 0x00C0, /* R30 - DAC Digital Volume Left */
71 0x00C0, /* R31 - DAC Digital Volume Right */
72 0x0000, /* R32 - DAC Digital 0 */
73 0x0000, /* R33 - DAC Digital 1 */
76 0x00C0, /* R36 - ADC Digital Volume Left */
77 0x00C0, /* R37 - ADC Digital Volume Right */
78 0x0000, /* R38 - ADC Digital 0 */
79 0x0073, /* R39 - Digital Microphone 0 */
80 0x09BF, /* R40 - DRC 0 */
81 0x3241, /* R41 - DRC 1 */
82 0x0020, /* R42 - DRC 2 */
83 0x0000, /* R43 - DRC 3 */
84 0x0085, /* R44 - Analogue Left Input 0 */
85 0x0085, /* R45 - Analogue Right Input 0 */
86 0x0044, /* R46 - Analogue Left Input 1 */
87 0x0044, /* R47 - Analogue Right Input 1 */
90 0x0008, /* R50 - Analogue Left Mix 0 */
91 0x0004, /* R51 - Analogue Right Mix 0 */
92 0x0000, /* R52 - Analogue Spk Mix Left 0 */
93 0x0000, /* R53 - Analogue Spk Mix Left 1 */
94 0x0000, /* R54 - Analogue Spk Mix Right 0 */
95 0x0000, /* R55 - Analogue Spk Mix Right 1 */
97 0x002D, /* R57 - Analogue OUT1 Left */
98 0x002D, /* R58 - Analogue OUT1 Right */
99 0x0039, /* R59 - Analogue OUT2 Left */
100 0x0039, /* R60 - Analogue OUT2 Right */
102 0x0139, /* R62 - Analogue OUT3 Left */
103 0x0139, /* R63 - Analogue OUT3 Right */
105 0x0000, /* R65 - Analogue SPK Output Control 0 */
107 0x0010, /* R67 - DC Servo 0 */
109 0x00A4, /* R69 - DC Servo 2 */
130 0x0000, /* R90 - Analogue HP 0 */
134 0x0000, /* R94 - Analogue Lineout 0 */
138 0x0000, /* R98 - Charge Pump 0 */
144 0x0000, /* R104 - Class W 0 */
148 0x0000, /* R108 - Write Sequencer 0 */
149 0x0000, /* R109 - Write Sequencer 1 */
150 0x0000, /* R110 - Write Sequencer 2 */
151 0x0000, /* R111 - Write Sequencer 3 */
152 0x0000, /* R112 - Write Sequencer 4 */
154 0x0000, /* R114 - Control Interface */
156 0x00A8, /* R116 - GPIO Control 1 */
157 0x00A8, /* R117 - GPIO Control 2 */
158 0x00A8, /* R118 - GPIO Control 3 */
159 0x0220, /* R119 - GPIO Control 4 */
160 0x01A0, /* R120 - GPIO Control 5 */
161 0x0000, /* R121 - Interrupt Status 1 */
162 0xFFFF, /* R122 - Interrupt Status 1 Mask */
163 0x0000, /* R123 - Interrupt Polarity 1 */
166 0x0000, /* R126 - Interrupt Control */
169 0x0000, /* R129 - Control Interface Test 1 */
189 0x6810, /* R149 - Charge Pump Test 1 */
204 0x0028, /* R164 - Clock Rate Test 4 */
212 0x0000, /* R172 - Analogue Output Bias 0 */
217 u16 reg_cache
[ARRAY_SIZE(wm8903_reg_defaults
)];
225 /* Reference count */
228 struct completion wseq
;
230 struct snd_soc_jack
*mic_jack
;
237 static int wm8903_volatile_register(unsigned int reg
)
240 case WM8903_SW_RESET_AND_ID
:
241 case WM8903_REVISION_NUMBER
:
242 case WM8903_INTERRUPT_STATUS_1
:
243 case WM8903_WRITE_SEQUENCER_4
:
251 static int wm8903_run_sequence(struct snd_soc_codec
*codec
, unsigned int start
)
254 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
258 /* Enable the sequencer if it's not already on */
259 reg
[0] = snd_soc_read(codec
, WM8903_WRITE_SEQUENCER_0
);
260 snd_soc_write(codec
, WM8903_WRITE_SEQUENCER_0
,
261 reg
[0] | WM8903_WSEQ_ENA
);
263 dev_dbg(codec
->dev
, "Starting sequence at %d\n", start
);
265 snd_soc_write(codec
, WM8903_WRITE_SEQUENCER_3
,
266 start
| WM8903_WSEQ_START
);
268 /* Wait for it to complete. If we have the interrupt wired up then
269 * that will break us out of the poll early.
272 wait_for_completion_timeout(&wm8903
->wseq
,
273 msecs_to_jiffies(10));
275 reg
[4] = snd_soc_read(codec
, WM8903_WRITE_SEQUENCER_4
);
276 } while (reg
[4] & WM8903_WSEQ_BUSY
);
278 dev_dbg(codec
->dev
, "Sequence complete\n");
280 /* Disable the sequencer again if we enabled it */
281 snd_soc_write(codec
, WM8903_WRITE_SEQUENCER_0
, reg
[0]);
286 static void wm8903_sync_reg_cache(struct snd_soc_codec
*codec
, u16
*cache
)
290 /* There really ought to be something better we can do here :/ */
291 for (i
= 0; i
< ARRAY_SIZE(wm8903_reg_defaults
); i
++)
292 cache
[i
] = codec
->hw_read(codec
, i
);
295 static void wm8903_reset(struct snd_soc_codec
*codec
)
297 snd_soc_write(codec
, WM8903_SW_RESET_AND_ID
, 0);
298 memcpy(codec
->reg_cache
, wm8903_reg_defaults
,
299 sizeof(wm8903_reg_defaults
));
302 #define WM8903_OUTPUT_SHORT 0x8
303 #define WM8903_OUTPUT_OUT 0x4
304 #define WM8903_OUTPUT_INT 0x2
305 #define WM8903_OUTPUT_IN 0x1
307 static int wm8903_cp_event(struct snd_soc_dapm_widget
*w
,
308 struct snd_kcontrol
*kcontrol
, int event
)
310 WARN_ON(event
!= SND_SOC_DAPM_POST_PMU
);
317 * Event for headphone and line out amplifier power changes. Special
318 * power up/down sequences are required in order to maximise pop/click
321 static int wm8903_output_event(struct snd_soc_dapm_widget
*w
,
322 struct snd_kcontrol
*kcontrol
, int event
)
324 struct snd_soc_codec
*codec
= w
->codec
;
332 case WM8903_POWER_MANAGEMENT_2
:
333 reg
= WM8903_ANALOGUE_HP_0
;
334 dcs_bit
= 0 + w
->shift
;
336 case WM8903_POWER_MANAGEMENT_3
:
337 reg
= WM8903_ANALOGUE_LINEOUT_0
;
338 dcs_bit
= 2 + w
->shift
;
342 return -EINVAL
; /* Spurious warning from some compilers */
354 return -EINVAL
; /* Spurious warning from some compilers */
357 if (event
& SND_SOC_DAPM_PRE_PMU
) {
358 val
= snd_soc_read(codec
, reg
);
360 /* Short the output */
361 val
&= ~(WM8903_OUTPUT_SHORT
<< shift
);
362 snd_soc_write(codec
, reg
, val
);
365 if (event
& SND_SOC_DAPM_POST_PMU
) {
366 val
= snd_soc_read(codec
, reg
);
368 val
|= (WM8903_OUTPUT_IN
<< shift
);
369 snd_soc_write(codec
, reg
, val
);
371 val
|= (WM8903_OUTPUT_INT
<< shift
);
372 snd_soc_write(codec
, reg
, val
);
374 /* Turn on the output ENA_OUTP */
375 val
|= (WM8903_OUTPUT_OUT
<< shift
);
376 snd_soc_write(codec
, reg
, val
);
378 /* Enable the DC servo */
379 dcs_reg
= snd_soc_read(codec
, WM8903_DC_SERVO_0
);
381 snd_soc_write(codec
, WM8903_DC_SERVO_0
, dcs_reg
);
383 /* Remove the short */
384 val
|= (WM8903_OUTPUT_SHORT
<< shift
);
385 snd_soc_write(codec
, reg
, val
);
388 if (event
& SND_SOC_DAPM_PRE_PMD
) {
389 val
= snd_soc_read(codec
, reg
);
391 /* Short the output */
392 val
&= ~(WM8903_OUTPUT_SHORT
<< shift
);
393 snd_soc_write(codec
, reg
, val
);
395 /* Disable the DC servo */
396 dcs_reg
= snd_soc_read(codec
, WM8903_DC_SERVO_0
);
398 snd_soc_write(codec
, WM8903_DC_SERVO_0
, dcs_reg
);
400 /* Then disable the intermediate and output stages */
401 val
&= ~((WM8903_OUTPUT_OUT
| WM8903_OUTPUT_INT
|
402 WM8903_OUTPUT_IN
) << shift
);
403 snd_soc_write(codec
, reg
, val
);
410 * When used with DAC outputs only the WM8903 charge pump supports
411 * operation in class W mode, providing very low power consumption
412 * when used with digital sources. Enable and disable this mode
413 * automatically depending on the mixer configuration.
415 * All the relevant controls are simple switches.
417 static int wm8903_class_w_put(struct snd_kcontrol
*kcontrol
,
418 struct snd_ctl_elem_value
*ucontrol
)
420 struct snd_soc_dapm_widget
*widget
= snd_kcontrol_chip(kcontrol
);
421 struct snd_soc_codec
*codec
= widget
->codec
;
422 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
426 reg
= snd_soc_read(codec
, WM8903_CLASS_W_0
);
428 /* Turn it off if we're about to enable bypass */
429 if (ucontrol
->value
.integer
.value
[0]) {
430 if (wm8903
->class_w_users
== 0) {
431 dev_dbg(codec
->dev
, "Disabling Class W\n");
432 snd_soc_write(codec
, WM8903_CLASS_W_0
, reg
&
433 ~(WM8903_CP_DYN_FREQ
| WM8903_CP_DYN_V
));
435 wm8903
->class_w_users
++;
438 /* Implement the change */
439 ret
= snd_soc_dapm_put_volsw(kcontrol
, ucontrol
);
441 /* If we've just disabled the last bypass path turn Class W on */
442 if (!ucontrol
->value
.integer
.value
[0]) {
443 if (wm8903
->class_w_users
== 1) {
444 dev_dbg(codec
->dev
, "Enabling Class W\n");
445 snd_soc_write(codec
, WM8903_CLASS_W_0
, reg
|
446 WM8903_CP_DYN_FREQ
| WM8903_CP_DYN_V
);
448 wm8903
->class_w_users
--;
451 dev_dbg(codec
->dev
, "Bypass use count now %d\n",
452 wm8903
->class_w_users
);
457 #define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
458 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
459 .info = snd_soc_info_volsw, \
460 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
461 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
464 static int wm8903_deemph
[] = { 0, 32000, 44100, 48000 };
466 static int wm8903_set_deemph(struct snd_soc_codec
*codec
)
468 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
471 /* If we're using deemphasis select the nearest available sample
474 if (wm8903
->deemph
) {
476 for (i
= 2; i
< ARRAY_SIZE(wm8903_deemph
); i
++) {
477 if (abs(wm8903_deemph
[i
] - wm8903
->fs
) <
478 abs(wm8903_deemph
[best
] - wm8903
->fs
))
482 val
= best
<< WM8903_DEEMPH_SHIFT
;
488 dev_dbg(codec
->dev
, "Set deemphasis %d (%dHz)\n",
489 best
, wm8903_deemph
[best
]);
491 return snd_soc_update_bits(codec
, WM8903_DAC_DIGITAL_1
,
492 WM8903_DEEMPH_MASK
, val
);
495 static int wm8903_get_deemph(struct snd_kcontrol
*kcontrol
,
496 struct snd_ctl_elem_value
*ucontrol
)
498 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
499 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
501 ucontrol
->value
.enumerated
.item
[0] = wm8903
->deemph
;
506 static int wm8903_put_deemph(struct snd_kcontrol
*kcontrol
,
507 struct snd_ctl_elem_value
*ucontrol
)
509 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
510 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
511 int deemph
= ucontrol
->value
.enumerated
.item
[0];
517 mutex_lock(&codec
->mutex
);
518 if (wm8903
->deemph
!= deemph
) {
519 wm8903
->deemph
= deemph
;
521 wm8903_set_deemph(codec
);
525 mutex_unlock(&codec
->mutex
);
530 /* ALSA can only do steps of .01dB */
531 static const DECLARE_TLV_DB_SCALE(digital_tlv
, -7200, 75, 1);
533 static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv
, -3600, 300, 0);
534 static const DECLARE_TLV_DB_SCALE(out_tlv
, -5700, 100, 0);
536 static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh
, 0, 75, 0);
537 static const DECLARE_TLV_DB_SCALE(drc_tlv_amp
, -2250, 75, 0);
538 static const DECLARE_TLV_DB_SCALE(drc_tlv_min
, 0, 600, 0);
539 static const DECLARE_TLV_DB_SCALE(drc_tlv_max
, 1200, 600, 0);
540 static const DECLARE_TLV_DB_SCALE(drc_tlv_startup
, -300, 50, 0);
542 static const char *hpf_mode_text
[] = {
543 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
546 static const struct soc_enum hpf_mode
=
547 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0
, 5, 4, hpf_mode_text
);
549 static const char *osr_text
[] = {
550 "Low power", "High performance"
553 static const struct soc_enum adc_osr
=
554 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0
, 0, 2, osr_text
);
556 static const struct soc_enum dac_osr
=
557 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1
, 0, 2, osr_text
);
559 static const char *drc_slope_text
[] = {
560 "1", "1/2", "1/4", "1/8", "1/16", "0"
563 static const struct soc_enum drc_slope_r0
=
564 SOC_ENUM_SINGLE(WM8903_DRC_2
, 3, 6, drc_slope_text
);
566 static const struct soc_enum drc_slope_r1
=
567 SOC_ENUM_SINGLE(WM8903_DRC_2
, 0, 6, drc_slope_text
);
569 static const char *drc_attack_text
[] = {
571 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
572 "46.4ms", "92.8ms", "185.6ms"
575 static const struct soc_enum drc_attack
=
576 SOC_ENUM_SINGLE(WM8903_DRC_1
, 12, 11, drc_attack_text
);
578 static const char *drc_decay_text
[] = {
579 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
583 static const struct soc_enum drc_decay
=
584 SOC_ENUM_SINGLE(WM8903_DRC_1
, 8, 9, drc_decay_text
);
586 static const char *drc_ff_delay_text
[] = {
587 "5 samples", "9 samples"
590 static const struct soc_enum drc_ff_delay
=
591 SOC_ENUM_SINGLE(WM8903_DRC_0
, 5, 2, drc_ff_delay_text
);
593 static const char *drc_qr_decay_text
[] = {
594 "0.725ms", "1.45ms", "5.8ms"
597 static const struct soc_enum drc_qr_decay
=
598 SOC_ENUM_SINGLE(WM8903_DRC_1
, 4, 3, drc_qr_decay_text
);
600 static const char *drc_smoothing_text
[] = {
601 "Low", "Medium", "High"
604 static const struct soc_enum drc_smoothing
=
605 SOC_ENUM_SINGLE(WM8903_DRC_0
, 11, 3, drc_smoothing_text
);
607 static const char *soft_mute_text
[] = {
608 "Fast (fs/2)", "Slow (fs/32)"
611 static const struct soc_enum soft_mute
=
612 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1
, 10, 2, soft_mute_text
);
614 static const char *mute_mode_text
[] = {
618 static const struct soc_enum mute_mode
=
619 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1
, 9, 2, mute_mode_text
);
621 static const char *companding_text
[] = {
625 static const struct soc_enum dac_companding
=
626 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 0, 2, companding_text
);
628 static const struct soc_enum adc_companding
=
629 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 2, 2, companding_text
);
631 static const char *input_mode_text
[] = {
632 "Single-Ended", "Differential Line", "Differential Mic"
635 static const struct soc_enum linput_mode_enum
=
636 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1
, 0, 3, input_mode_text
);
638 static const struct soc_enum rinput_mode_enum
=
639 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1
, 0, 3, input_mode_text
);
641 static const char *linput_mux_text
[] = {
642 "IN1L", "IN2L", "IN3L"
645 static const struct soc_enum linput_enum
=
646 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1
, 2, 3, linput_mux_text
);
648 static const struct soc_enum linput_inv_enum
=
649 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1
, 4, 3, linput_mux_text
);
651 static const char *rinput_mux_text
[] = {
652 "IN1R", "IN2R", "IN3R"
655 static const struct soc_enum rinput_enum
=
656 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1
, 2, 3, rinput_mux_text
);
658 static const struct soc_enum rinput_inv_enum
=
659 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1
, 4, 3, rinput_mux_text
);
662 static const char *sidetone_text
[] = {
663 "None", "Left", "Right"
666 static const struct soc_enum lsidetone_enum
=
667 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0
, 2, 3, sidetone_text
);
669 static const struct soc_enum rsidetone_enum
=
670 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0
, 0, 3, sidetone_text
);
672 static const struct snd_kcontrol_new wm8903_snd_controls
[] = {
674 /* Input PGAs - No TLV since the scale depends on PGA mode */
675 SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0
,
677 SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0
,
679 SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1
,
682 SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0
,
684 SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0
,
686 SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1
,
690 SOC_ENUM("ADC OSR", adc_osr
),
691 SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0
, 4, 1, 0),
692 SOC_ENUM("HPF Mode", hpf_mode
),
693 SOC_SINGLE("DRC Switch", WM8903_DRC_0
, 15, 1, 0),
694 SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0
),
695 SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1
),
696 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3
, 5, 124, 1,
698 SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3
, 0, 30, 1, drc_tlv_amp
),
699 SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1
, 2, 3, 1, drc_tlv_min
),
700 SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1
, 0, 3, 0, drc_tlv_max
),
701 SOC_ENUM("DRC Attack Rate", drc_attack
),
702 SOC_ENUM("DRC Decay Rate", drc_decay
),
703 SOC_ENUM("DRC FF Delay", drc_ff_delay
),
704 SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0
, 1, 1, 0),
705 SOC_SINGLE("DRC QR Switch", WM8903_DRC_0
, 2, 1, 0),
706 SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0
, 6, 3, 0, drc_tlv_max
),
707 SOC_ENUM("DRC QR Decay Rate", drc_qr_decay
),
708 SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0
, 3, 1, 0),
709 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0
, 0, 1, 0),
710 SOC_ENUM("DRC Smoothing Threshold", drc_smoothing
),
711 SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0
, 6, 18, 0, drc_tlv_startup
),
713 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT
,
714 WM8903_ADC_DIGITAL_VOLUME_RIGHT
, 1, 96, 0, digital_tlv
),
715 SOC_ENUM("ADC Companding Mode", adc_companding
),
716 SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0
, 3, 1, 0),
718 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0
, 4, 8,
719 12, 0, digital_sidetone_tlv
),
722 SOC_ENUM("DAC OSR", dac_osr
),
723 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT
,
724 WM8903_DAC_DIGITAL_VOLUME_RIGHT
, 1, 120, 0, digital_tlv
),
725 SOC_ENUM("DAC Soft Mute Rate", soft_mute
),
726 SOC_ENUM("DAC Mute Mode", mute_mode
),
727 SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1
, 12, 1, 0),
728 SOC_ENUM("DAC Companding Mode", dac_companding
),
729 SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0
, 1, 1, 0),
730 SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
731 wm8903_get_deemph
, wm8903_put_deemph
),
734 SOC_DOUBLE_R("Headphone Switch",
735 WM8903_ANALOGUE_OUT1_LEFT
, WM8903_ANALOGUE_OUT1_RIGHT
,
737 SOC_DOUBLE_R("Headphone ZC Switch",
738 WM8903_ANALOGUE_OUT1_LEFT
, WM8903_ANALOGUE_OUT1_RIGHT
,
740 SOC_DOUBLE_R_TLV("Headphone Volume",
741 WM8903_ANALOGUE_OUT1_LEFT
, WM8903_ANALOGUE_OUT1_RIGHT
,
745 SOC_DOUBLE_R("Line Out Switch",
746 WM8903_ANALOGUE_OUT2_LEFT
, WM8903_ANALOGUE_OUT2_RIGHT
,
748 SOC_DOUBLE_R("Line Out ZC Switch",
749 WM8903_ANALOGUE_OUT2_LEFT
, WM8903_ANALOGUE_OUT2_RIGHT
,
751 SOC_DOUBLE_R_TLV("Line Out Volume",
752 WM8903_ANALOGUE_OUT2_LEFT
, WM8903_ANALOGUE_OUT2_RIGHT
,
756 SOC_DOUBLE_R("Speaker Switch",
757 WM8903_ANALOGUE_OUT3_LEFT
, WM8903_ANALOGUE_OUT3_RIGHT
, 8, 1, 1),
758 SOC_DOUBLE_R("Speaker ZC Switch",
759 WM8903_ANALOGUE_OUT3_LEFT
, WM8903_ANALOGUE_OUT3_RIGHT
, 6, 1, 0),
760 SOC_DOUBLE_R_TLV("Speaker Volume",
761 WM8903_ANALOGUE_OUT3_LEFT
, WM8903_ANALOGUE_OUT3_RIGHT
,
765 static const struct snd_kcontrol_new linput_mode_mux
=
766 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum
);
768 static const struct snd_kcontrol_new rinput_mode_mux
=
769 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum
);
771 static const struct snd_kcontrol_new linput_mux
=
772 SOC_DAPM_ENUM("Left Input Mux", linput_enum
);
774 static const struct snd_kcontrol_new linput_inv_mux
=
775 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum
);
777 static const struct snd_kcontrol_new rinput_mux
=
778 SOC_DAPM_ENUM("Right Input Mux", rinput_enum
);
780 static const struct snd_kcontrol_new rinput_inv_mux
=
781 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum
);
783 static const struct snd_kcontrol_new lsidetone_mux
=
784 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum
);
786 static const struct snd_kcontrol_new rsidetone_mux
=
787 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum
);
789 static const struct snd_kcontrol_new left_output_mixer
[] = {
790 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 3, 1, 0),
791 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 2, 1, 0),
792 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 1, 1, 0),
793 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 0, 1, 0),
796 static const struct snd_kcontrol_new right_output_mixer
[] = {
797 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 3, 1, 0),
798 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 2, 1, 0),
799 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 1, 1, 0),
800 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 0, 1, 0),
803 static const struct snd_kcontrol_new left_speaker_mixer
[] = {
804 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
, 3, 1, 0),
805 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
, 2, 1, 0),
806 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
, 1, 1, 0),
807 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
,
811 static const struct snd_kcontrol_new right_speaker_mixer
[] = {
812 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
, 3, 1, 0),
813 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
, 2, 1, 0),
814 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
,
816 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
,
820 static const struct snd_soc_dapm_widget wm8903_dapm_widgets
[] = {
821 SND_SOC_DAPM_INPUT("IN1L"),
822 SND_SOC_DAPM_INPUT("IN1R"),
823 SND_SOC_DAPM_INPUT("IN2L"),
824 SND_SOC_DAPM_INPUT("IN2R"),
825 SND_SOC_DAPM_INPUT("IN3L"),
826 SND_SOC_DAPM_INPUT("IN3R"),
828 SND_SOC_DAPM_OUTPUT("HPOUTL"),
829 SND_SOC_DAPM_OUTPUT("HPOUTR"),
830 SND_SOC_DAPM_OUTPUT("LINEOUTL"),
831 SND_SOC_DAPM_OUTPUT("LINEOUTR"),
832 SND_SOC_DAPM_OUTPUT("LOP"),
833 SND_SOC_DAPM_OUTPUT("LON"),
834 SND_SOC_DAPM_OUTPUT("ROP"),
835 SND_SOC_DAPM_OUTPUT("RON"),
837 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0
, 0, 0),
839 SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM
, 0, 0, &linput_mux
),
840 SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM
, 0, 0,
842 SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM
, 0, 0, &linput_mode_mux
),
844 SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM
, 0, 0, &rinput_mux
),
845 SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM
, 0, 0,
847 SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM
, 0, 0, &rinput_mode_mux
),
849 SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0
, 1, 0, NULL
, 0),
850 SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0
, 0, 0, NULL
, 0),
852 SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8903_POWER_MANAGEMENT_6
, 1, 0),
853 SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8903_POWER_MANAGEMENT_6
, 0, 0),
855 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM
, 0, 0, &lsidetone_mux
),
856 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM
, 0, 0, &rsidetone_mux
),
858 SND_SOC_DAPM_DAC("DACL", "Left Playback", WM8903_POWER_MANAGEMENT_6
, 3, 0),
859 SND_SOC_DAPM_DAC("DACR", "Right Playback", WM8903_POWER_MANAGEMENT_6
, 2, 0),
861 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1
, 1, 0,
862 left_output_mixer
, ARRAY_SIZE(left_output_mixer
)),
863 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1
, 0, 0,
864 right_output_mixer
, ARRAY_SIZE(right_output_mixer
)),
866 SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4
, 1, 0,
867 left_speaker_mixer
, ARRAY_SIZE(left_speaker_mixer
)),
868 SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4
, 0, 0,
869 right_speaker_mixer
, ARRAY_SIZE(right_speaker_mixer
)),
871 SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2
,
872 1, 0, NULL
, 0, wm8903_output_event
,
873 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMU
|
874 SND_SOC_DAPM_PRE_PMD
),
875 SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2
,
876 0, 0, NULL
, 0, wm8903_output_event
,
877 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMU
|
878 SND_SOC_DAPM_PRE_PMD
),
880 SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3
, 1, 0,
881 NULL
, 0, wm8903_output_event
,
882 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMU
|
883 SND_SOC_DAPM_PRE_PMD
),
884 SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3
, 0, 0,
885 NULL
, 0, wm8903_output_event
,
886 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMU
|
887 SND_SOC_DAPM_PRE_PMD
),
889 SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5
, 1, 0,
891 SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5
, 0, 0,
894 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0
, 0, 0,
895 wm8903_cp_event
, SND_SOC_DAPM_POST_PMU
),
896 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2
, 1, 0, NULL
, 0),
899 static const struct snd_soc_dapm_route intercon
[] = {
901 { "Left Input Mux", "IN1L", "IN1L" },
902 { "Left Input Mux", "IN2L", "IN2L" },
903 { "Left Input Mux", "IN3L", "IN3L" },
905 { "Left Input Inverting Mux", "IN1L", "IN1L" },
906 { "Left Input Inverting Mux", "IN2L", "IN2L" },
907 { "Left Input Inverting Mux", "IN3L", "IN3L" },
909 { "Right Input Mux", "IN1R", "IN1R" },
910 { "Right Input Mux", "IN2R", "IN2R" },
911 { "Right Input Mux", "IN3R", "IN3R" },
913 { "Right Input Inverting Mux", "IN1R", "IN1R" },
914 { "Right Input Inverting Mux", "IN2R", "IN2R" },
915 { "Right Input Inverting Mux", "IN3R", "IN3R" },
917 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
918 { "Left Input Mode Mux", "Differential Line",
920 { "Left Input Mode Mux", "Differential Line",
921 "Left Input Inverting Mux" },
922 { "Left Input Mode Mux", "Differential Mic",
924 { "Left Input Mode Mux", "Differential Mic",
925 "Left Input Inverting Mux" },
927 { "Right Input Mode Mux", "Single-Ended",
928 "Right Input Inverting Mux" },
929 { "Right Input Mode Mux", "Differential Line",
931 { "Right Input Mode Mux", "Differential Line",
932 "Right Input Inverting Mux" },
933 { "Right Input Mode Mux", "Differential Mic",
935 { "Right Input Mode Mux", "Differential Mic",
936 "Right Input Inverting Mux" },
938 { "Left Input PGA", NULL
, "Left Input Mode Mux" },
939 { "Right Input PGA", NULL
, "Right Input Mode Mux" },
941 { "ADCL", NULL
, "Left Input PGA" },
942 { "ADCL", NULL
, "CLK_DSP" },
943 { "ADCR", NULL
, "Right Input PGA" },
944 { "ADCR", NULL
, "CLK_DSP" },
946 { "DACL Sidetone", "Left", "ADCL" },
947 { "DACL Sidetone", "Right", "ADCR" },
948 { "DACR Sidetone", "Left", "ADCL" },
949 { "DACR Sidetone", "Right", "ADCR" },
951 { "DACL", NULL
, "DACL Sidetone" },
952 { "DACL", NULL
, "CLK_DSP" },
953 { "DACR", NULL
, "DACR Sidetone" },
954 { "DACR", NULL
, "CLK_DSP" },
956 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
957 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
958 { "Left Output Mixer", "DACL Switch", "DACL" },
959 { "Left Output Mixer", "DACR Switch", "DACR" },
961 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
962 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
963 { "Right Output Mixer", "DACL Switch", "DACL" },
964 { "Right Output Mixer", "DACR Switch", "DACR" },
966 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
967 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
968 { "Left Speaker Mixer", "DACL Switch", "DACL" },
969 { "Left Speaker Mixer", "DACR Switch", "DACR" },
971 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
972 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
973 { "Right Speaker Mixer", "DACL Switch", "DACL" },
974 { "Right Speaker Mixer", "DACR Switch", "DACR" },
976 { "Left Line Output PGA", NULL
, "Left Output Mixer" },
977 { "Right Line Output PGA", NULL
, "Right Output Mixer" },
979 { "Left Headphone Output PGA", NULL
, "Left Output Mixer" },
980 { "Right Headphone Output PGA", NULL
, "Right Output Mixer" },
982 { "Left Speaker PGA", NULL
, "Left Speaker Mixer" },
983 { "Right Speaker PGA", NULL
, "Right Speaker Mixer" },
985 { "HPOUTL", NULL
, "Left Headphone Output PGA" },
986 { "HPOUTR", NULL
, "Right Headphone Output PGA" },
988 { "LINEOUTL", NULL
, "Left Line Output PGA" },
989 { "LINEOUTR", NULL
, "Right Line Output PGA" },
991 { "LOP", NULL
, "Left Speaker PGA" },
992 { "LON", NULL
, "Left Speaker PGA" },
994 { "ROP", NULL
, "Right Speaker PGA" },
995 { "RON", NULL
, "Right Speaker PGA" },
997 { "Left Headphone Output PGA", NULL
, "Charge Pump" },
998 { "Right Headphone Output PGA", NULL
, "Charge Pump" },
999 { "Left Line Output PGA", NULL
, "Charge Pump" },
1000 { "Right Line Output PGA", NULL
, "Charge Pump" },
1003 static int wm8903_add_widgets(struct snd_soc_codec
*codec
)
1005 struct snd_soc_dapm_context
*dapm
= &codec
->dapm
;
1007 snd_soc_dapm_new_controls(dapm
, wm8903_dapm_widgets
,
1008 ARRAY_SIZE(wm8903_dapm_widgets
));
1009 snd_soc_dapm_add_routes(dapm
, intercon
, ARRAY_SIZE(intercon
));
1014 static int wm8903_set_bias_level(struct snd_soc_codec
*codec
,
1015 enum snd_soc_bias_level level
)
1020 case SND_SOC_BIAS_ON
:
1021 case SND_SOC_BIAS_PREPARE
:
1022 reg
= snd_soc_read(codec
, WM8903_VMID_CONTROL_0
);
1023 reg
&= ~(WM8903_VMID_RES_MASK
);
1024 reg
|= WM8903_VMID_RES_50K
;
1025 snd_soc_write(codec
, WM8903_VMID_CONTROL_0
, reg
);
1028 case SND_SOC_BIAS_STANDBY
:
1029 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
1030 snd_soc_write(codec
, WM8903_CLOCK_RATES_2
,
1031 WM8903_CLK_SYS_ENA
);
1033 /* Change DC servo dither level in startup sequence */
1034 snd_soc_write(codec
, WM8903_WRITE_SEQUENCER_0
, 0x11);
1035 snd_soc_write(codec
, WM8903_WRITE_SEQUENCER_1
, 0x1257);
1036 snd_soc_write(codec
, WM8903_WRITE_SEQUENCER_2
, 0x2);
1038 wm8903_run_sequence(codec
, 0);
1039 wm8903_sync_reg_cache(codec
, codec
->reg_cache
);
1041 /* Enable low impedence charge pump output */
1042 reg
= snd_soc_read(codec
,
1043 WM8903_CONTROL_INTERFACE_TEST_1
);
1044 snd_soc_write(codec
, WM8903_CONTROL_INTERFACE_TEST_1
,
1045 reg
| WM8903_TEST_KEY
);
1046 reg2
= snd_soc_read(codec
, WM8903_CHARGE_PUMP_TEST_1
);
1047 snd_soc_write(codec
, WM8903_CHARGE_PUMP_TEST_1
,
1048 reg2
| WM8903_CP_SW_KELVIN_MODE_MASK
);
1049 snd_soc_write(codec
, WM8903_CONTROL_INTERFACE_TEST_1
,
1052 /* By default no bypass paths are enabled so
1053 * enable Class W support.
1055 dev_dbg(codec
->dev
, "Enabling Class W\n");
1056 snd_soc_write(codec
, WM8903_CLASS_W_0
, reg
|
1057 WM8903_CP_DYN_FREQ
| WM8903_CP_DYN_V
);
1060 reg
= snd_soc_read(codec
, WM8903_VMID_CONTROL_0
);
1061 reg
&= ~(WM8903_VMID_RES_MASK
);
1062 reg
|= WM8903_VMID_RES_250K
;
1063 snd_soc_write(codec
, WM8903_VMID_CONTROL_0
, reg
);
1066 case SND_SOC_BIAS_OFF
:
1067 wm8903_run_sequence(codec
, 32);
1068 reg
= snd_soc_read(codec
, WM8903_CLOCK_RATES_2
);
1069 reg
&= ~WM8903_CLK_SYS_ENA
;
1070 snd_soc_write(codec
, WM8903_CLOCK_RATES_2
, reg
);
1074 codec
->dapm
.bias_level
= level
;
1079 static int wm8903_set_dai_sysclk(struct snd_soc_dai
*codec_dai
,
1080 int clk_id
, unsigned int freq
, int dir
)
1082 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1083 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1085 wm8903
->sysclk
= freq
;
1090 static int wm8903_set_dai_fmt(struct snd_soc_dai
*codec_dai
,
1093 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1094 u16 aif1
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_1
);
1096 aif1
&= ~(WM8903_LRCLK_DIR
| WM8903_BCLK_DIR
| WM8903_AIF_FMT_MASK
|
1097 WM8903_AIF_LRCLK_INV
| WM8903_AIF_BCLK_INV
);
1099 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
1100 case SND_SOC_DAIFMT_CBS_CFS
:
1102 case SND_SOC_DAIFMT_CBS_CFM
:
1103 aif1
|= WM8903_LRCLK_DIR
;
1105 case SND_SOC_DAIFMT_CBM_CFM
:
1106 aif1
|= WM8903_LRCLK_DIR
| WM8903_BCLK_DIR
;
1108 case SND_SOC_DAIFMT_CBM_CFS
:
1109 aif1
|= WM8903_BCLK_DIR
;
1115 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1116 case SND_SOC_DAIFMT_DSP_A
:
1119 case SND_SOC_DAIFMT_DSP_B
:
1120 aif1
|= 0x3 | WM8903_AIF_LRCLK_INV
;
1122 case SND_SOC_DAIFMT_I2S
:
1125 case SND_SOC_DAIFMT_RIGHT_J
:
1128 case SND_SOC_DAIFMT_LEFT_J
:
1134 /* Clock inversion */
1135 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1136 case SND_SOC_DAIFMT_DSP_A
:
1137 case SND_SOC_DAIFMT_DSP_B
:
1138 /* frame inversion not valid for DSP modes */
1139 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1140 case SND_SOC_DAIFMT_NB_NF
:
1142 case SND_SOC_DAIFMT_IB_NF
:
1143 aif1
|= WM8903_AIF_BCLK_INV
;
1149 case SND_SOC_DAIFMT_I2S
:
1150 case SND_SOC_DAIFMT_RIGHT_J
:
1151 case SND_SOC_DAIFMT_LEFT_J
:
1152 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1153 case SND_SOC_DAIFMT_NB_NF
:
1155 case SND_SOC_DAIFMT_IB_IF
:
1156 aif1
|= WM8903_AIF_BCLK_INV
| WM8903_AIF_LRCLK_INV
;
1158 case SND_SOC_DAIFMT_IB_NF
:
1159 aif1
|= WM8903_AIF_BCLK_INV
;
1161 case SND_SOC_DAIFMT_NB_IF
:
1162 aif1
|= WM8903_AIF_LRCLK_INV
;
1172 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_1
, aif1
);
1177 static int wm8903_digital_mute(struct snd_soc_dai
*codec_dai
, int mute
)
1179 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1182 reg
= snd_soc_read(codec
, WM8903_DAC_DIGITAL_1
);
1185 reg
|= WM8903_DAC_MUTE
;
1187 reg
&= ~WM8903_DAC_MUTE
;
1189 snd_soc_write(codec
, WM8903_DAC_DIGITAL_1
, reg
);
1194 /* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1195 * for optimal performance so we list the lower rates first and match
1196 * on the last match we find. */
1202 } clk_sys_ratios
[] = {
1203 { 64, 0x0, 0x0, 1 },
1204 { 68, 0x0, 0x1, 1 },
1205 { 125, 0x0, 0x2, 1 },
1206 { 128, 0x1, 0x0, 1 },
1207 { 136, 0x1, 0x1, 1 },
1208 { 192, 0x2, 0x0, 1 },
1209 { 204, 0x2, 0x1, 1 },
1211 { 64, 0x0, 0x0, 2 },
1212 { 68, 0x0, 0x1, 2 },
1213 { 125, 0x0, 0x2, 2 },
1214 { 128, 0x1, 0x0, 2 },
1215 { 136, 0x1, 0x1, 2 },
1216 { 192, 0x2, 0x0, 2 },
1217 { 204, 0x2, 0x1, 2 },
1219 { 250, 0x2, 0x2, 1 },
1220 { 256, 0x3, 0x0, 1 },
1221 { 272, 0x3, 0x1, 1 },
1222 { 384, 0x4, 0x0, 1 },
1223 { 408, 0x4, 0x1, 1 },
1224 { 375, 0x4, 0x2, 1 },
1225 { 512, 0x5, 0x0, 1 },
1226 { 544, 0x5, 0x1, 1 },
1227 { 500, 0x5, 0x2, 1 },
1228 { 768, 0x6, 0x0, 1 },
1229 { 816, 0x6, 0x1, 1 },
1230 { 750, 0x6, 0x2, 1 },
1231 { 1024, 0x7, 0x0, 1 },
1232 { 1088, 0x7, 0x1, 1 },
1233 { 1000, 0x7, 0x2, 1 },
1234 { 1408, 0x8, 0x0, 1 },
1235 { 1496, 0x8, 0x1, 1 },
1236 { 1536, 0x9, 0x0, 1 },
1237 { 1632, 0x9, 0x1, 1 },
1238 { 1500, 0x9, 0x2, 1 },
1240 { 250, 0x2, 0x2, 2 },
1241 { 256, 0x3, 0x0, 2 },
1242 { 272, 0x3, 0x1, 2 },
1243 { 384, 0x4, 0x0, 2 },
1244 { 408, 0x4, 0x1, 2 },
1245 { 375, 0x4, 0x2, 2 },
1246 { 512, 0x5, 0x0, 2 },
1247 { 544, 0x5, 0x1, 2 },
1248 { 500, 0x5, 0x2, 2 },
1249 { 768, 0x6, 0x0, 2 },
1250 { 816, 0x6, 0x1, 2 },
1251 { 750, 0x6, 0x2, 2 },
1252 { 1024, 0x7, 0x0, 2 },
1253 { 1088, 0x7, 0x1, 2 },
1254 { 1000, 0x7, 0x2, 2 },
1255 { 1408, 0x8, 0x0, 2 },
1256 { 1496, 0x8, 0x1, 2 },
1257 { 1536, 0x9, 0x0, 2 },
1258 { 1632, 0x9, 0x1, 2 },
1259 { 1500, 0x9, 0x2, 2 },
1262 /* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1286 /* Sample rates for DSP */
1290 } sample_rates
[] = {
1305 static int wm8903_hw_params(struct snd_pcm_substream
*substream
,
1306 struct snd_pcm_hw_params
*params
,
1307 struct snd_soc_dai
*dai
)
1309 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
1310 struct snd_soc_codec
*codec
=rtd
->codec
;
1311 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1312 int fs
= params_rate(params
);
1322 u16 aif1
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_1
);
1323 u16 aif2
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_2
);
1324 u16 aif3
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_3
);
1325 u16 clock0
= snd_soc_read(codec
, WM8903_CLOCK_RATES_0
);
1326 u16 clock1
= snd_soc_read(codec
, WM8903_CLOCK_RATES_1
);
1327 u16 dac_digital1
= snd_soc_read(codec
, WM8903_DAC_DIGITAL_1
);
1329 /* Enable sloping stopband filter for low sample rates */
1331 dac_digital1
|= WM8903_DAC_SB_FILT
;
1333 dac_digital1
&= ~WM8903_DAC_SB_FILT
;
1335 /* Configure sample rate logic for DSP - choose nearest rate */
1337 best_val
= abs(sample_rates
[dsp_config
].rate
- fs
);
1338 for (i
= 1; i
< ARRAY_SIZE(sample_rates
); i
++) {
1339 cur_val
= abs(sample_rates
[i
].rate
- fs
);
1340 if (cur_val
<= best_val
) {
1346 dev_dbg(codec
->dev
, "DSP fs = %dHz\n", sample_rates
[dsp_config
].rate
);
1347 clock1
&= ~WM8903_SAMPLE_RATE_MASK
;
1348 clock1
|= sample_rates
[dsp_config
].value
;
1350 aif1
&= ~WM8903_AIF_WL_MASK
;
1352 switch (params_format(params
)) {
1353 case SNDRV_PCM_FORMAT_S16_LE
:
1356 case SNDRV_PCM_FORMAT_S20_3LE
:
1360 case SNDRV_PCM_FORMAT_S24_LE
:
1364 case SNDRV_PCM_FORMAT_S32_LE
:
1372 dev_dbg(codec
->dev
, "MCLK = %dHz, target sample rate = %dHz\n",
1373 wm8903
->sysclk
, fs
);
1375 /* We may not have an MCLK which allows us to generate exactly
1376 * the clock we want, particularly with USB derived inputs, so
1380 best_val
= abs((wm8903
->sysclk
/
1381 (clk_sys_ratios
[0].mclk_div
*
1382 clk_sys_ratios
[0].div
)) - fs
);
1383 for (i
= 1; i
< ARRAY_SIZE(clk_sys_ratios
); i
++) {
1384 cur_val
= abs((wm8903
->sysclk
/
1385 (clk_sys_ratios
[i
].mclk_div
*
1386 clk_sys_ratios
[i
].div
)) - fs
);
1388 if (cur_val
<= best_val
) {
1394 if (clk_sys_ratios
[clk_config
].mclk_div
== 2) {
1395 clock0
|= WM8903_MCLKDIV2
;
1396 clk_sys
= wm8903
->sysclk
/ 2;
1398 clock0
&= ~WM8903_MCLKDIV2
;
1399 clk_sys
= wm8903
->sysclk
;
1402 clock1
&= ~(WM8903_CLK_SYS_RATE_MASK
|
1403 WM8903_CLK_SYS_MODE_MASK
);
1404 clock1
|= clk_sys_ratios
[clk_config
].rate
<< WM8903_CLK_SYS_RATE_SHIFT
;
1405 clock1
|= clk_sys_ratios
[clk_config
].mode
<< WM8903_CLK_SYS_MODE_SHIFT
;
1407 dev_dbg(codec
->dev
, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
1408 clk_sys_ratios
[clk_config
].rate
,
1409 clk_sys_ratios
[clk_config
].mode
,
1410 clk_sys_ratios
[clk_config
].div
);
1412 dev_dbg(codec
->dev
, "Actual CLK_SYS = %dHz\n", clk_sys
);
1414 /* We may not get quite the right frequency if using
1415 * approximate clocks so look for the closest match that is
1416 * higher than the target (we need to ensure that there enough
1417 * BCLKs to clock out the samples).
1420 best_val
= ((clk_sys
* 10) / bclk_divs
[0].ratio
) - bclk
;
1422 while (i
< ARRAY_SIZE(bclk_divs
)) {
1423 cur_val
= ((clk_sys
* 10) / bclk_divs
[i
].ratio
) - bclk
;
1424 if (cur_val
< 0) /* BCLK table is sorted */
1431 aif2
&= ~WM8903_BCLK_DIV_MASK
;
1432 aif3
&= ~WM8903_LRCLK_RATE_MASK
;
1434 dev_dbg(codec
->dev
, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
1435 bclk_divs
[bclk_div
].ratio
/ 10, bclk
,
1436 (clk_sys
* 10) / bclk_divs
[bclk_div
].ratio
);
1438 aif2
|= bclk_divs
[bclk_div
].div
;
1441 wm8903
->fs
= params_rate(params
);
1442 wm8903_set_deemph(codec
);
1444 snd_soc_write(codec
, WM8903_CLOCK_RATES_0
, clock0
);
1445 snd_soc_write(codec
, WM8903_CLOCK_RATES_1
, clock1
);
1446 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_1
, aif1
);
1447 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_2
, aif2
);
1448 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_3
, aif3
);
1449 snd_soc_write(codec
, WM8903_DAC_DIGITAL_1
, dac_digital1
);
1455 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1457 * @codec: WM8903 codec
1458 * @jack: jack to report detection events on
1459 * @det: value to report for presence detection
1460 * @shrt: value to report for short detection
1462 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1463 * being used to bring out signals to the processor then only platform
1464 * data configuration is needed for WM8903 and processor GPIOs should
1465 * be configured using snd_soc_jack_add_gpios() instead.
1467 * The current threasholds for detection should be configured using
1468 * micdet_cfg in the platform data. Using this function will force on
1469 * the microphone bias for the device.
1471 int wm8903_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
1474 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1475 int irq_mask
= WM8903_MICDET_EINT
| WM8903_MICSHRT_EINT
;
1477 dev_dbg(codec
->dev
, "Enabling microphone detection: %x %x\n",
1480 /* Store the configuration */
1481 wm8903
->mic_jack
= jack
;
1482 wm8903
->mic_det
= det
;
1483 wm8903
->mic_short
= shrt
;
1485 /* Enable interrupts we've got a report configured for */
1487 irq_mask
&= ~WM8903_MICDET_EINT
;
1489 irq_mask
&= ~WM8903_MICSHRT_EINT
;
1491 snd_soc_update_bits(codec
, WM8903_INTERRUPT_STATUS_1_MASK
,
1492 WM8903_MICDET_EINT
| WM8903_MICSHRT_EINT
,
1496 /* Enable mic detection, this may not have been set through
1497 * platform data (eg, if the defaults are OK). */
1498 snd_soc_update_bits(codec
, WM8903_WRITE_SEQUENCER_0
,
1499 WM8903_WSEQ_ENA
, WM8903_WSEQ_ENA
);
1500 snd_soc_update_bits(codec
, WM8903_MIC_BIAS_CONTROL_0
,
1501 WM8903_MICDET_ENA
, WM8903_MICDET_ENA
);
1503 snd_soc_update_bits(codec
, WM8903_MIC_BIAS_CONTROL_0
,
1504 WM8903_MICDET_ENA
, 0);
1509 EXPORT_SYMBOL_GPL(wm8903_mic_detect
);
1511 static irqreturn_t
wm8903_irq(int irq
, void *data
)
1513 struct snd_soc_codec
*codec
= data
;
1514 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1518 int mask
= ~snd_soc_read(codec
, WM8903_INTERRUPT_STATUS_1_MASK
);
1520 int_val
= snd_soc_read(codec
, WM8903_INTERRUPT_STATUS_1
) & mask
;
1522 if (int_val
& WM8903_WSEQ_BUSY_EINT
) {
1523 dev_dbg(codec
->dev
, "Write sequencer done\n");
1524 complete(&wm8903
->wseq
);
1528 * The rest is microphone jack detection. We need to manually
1529 * invert the polarity of the interrupt after each event - to
1530 * simplify the code keep track of the last state we reported
1531 * and just invert the relevant bits in both the report and
1532 * the polarity register.
1534 mic_report
= wm8903
->mic_last_report
;
1535 int_pol
= snd_soc_read(codec
, WM8903_INTERRUPT_POLARITY_1
);
1537 #ifndef CONFIG_SND_SOC_WM8903_MODULE
1538 if (int_val
& (WM8903_MICSHRT_EINT
| WM8903_MICDET_EINT
))
1539 trace_snd_soc_jack_irq(dev_name(codec
->dev
));
1542 if (int_val
& WM8903_MICSHRT_EINT
) {
1543 dev_dbg(codec
->dev
, "Microphone short (pol=%x)\n", int_pol
);
1545 mic_report
^= wm8903
->mic_short
;
1546 int_pol
^= WM8903_MICSHRT_INV
;
1549 if (int_val
& WM8903_MICDET_EINT
) {
1550 dev_dbg(codec
->dev
, "Microphone detect (pol=%x)\n", int_pol
);
1552 mic_report
^= wm8903
->mic_det
;
1553 int_pol
^= WM8903_MICDET_INV
;
1555 msleep(wm8903
->mic_delay
);
1558 snd_soc_update_bits(codec
, WM8903_INTERRUPT_POLARITY_1
,
1559 WM8903_MICSHRT_INV
| WM8903_MICDET_INV
, int_pol
);
1561 snd_soc_jack_report(wm8903
->mic_jack
, mic_report
,
1562 wm8903
->mic_short
| wm8903
->mic_det
);
1564 wm8903
->mic_last_report
= mic_report
;
1569 #define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1570 SNDRV_PCM_RATE_11025 | \
1571 SNDRV_PCM_RATE_16000 | \
1572 SNDRV_PCM_RATE_22050 | \
1573 SNDRV_PCM_RATE_32000 | \
1574 SNDRV_PCM_RATE_44100 | \
1575 SNDRV_PCM_RATE_48000 | \
1576 SNDRV_PCM_RATE_88200 | \
1577 SNDRV_PCM_RATE_96000)
1579 #define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1580 SNDRV_PCM_RATE_11025 | \
1581 SNDRV_PCM_RATE_16000 | \
1582 SNDRV_PCM_RATE_22050 | \
1583 SNDRV_PCM_RATE_32000 | \
1584 SNDRV_PCM_RATE_44100 | \
1585 SNDRV_PCM_RATE_48000)
1587 #define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1588 SNDRV_PCM_FMTBIT_S20_3LE |\
1589 SNDRV_PCM_FMTBIT_S24_LE)
1591 static struct snd_soc_dai_ops wm8903_dai_ops
= {
1592 .hw_params
= wm8903_hw_params
,
1593 .digital_mute
= wm8903_digital_mute
,
1594 .set_fmt
= wm8903_set_dai_fmt
,
1595 .set_sysclk
= wm8903_set_dai_sysclk
,
1598 static struct snd_soc_dai_driver wm8903_dai
= {
1599 .name
= "wm8903-hifi",
1601 .stream_name
= "Playback",
1604 .rates
= WM8903_PLAYBACK_RATES
,
1605 .formats
= WM8903_FORMATS
,
1608 .stream_name
= "Capture",
1611 .rates
= WM8903_CAPTURE_RATES
,
1612 .formats
= WM8903_FORMATS
,
1614 .ops
= &wm8903_dai_ops
,
1615 .symmetric_rates
= 1,
1618 static int wm8903_suspend(struct snd_soc_codec
*codec
, pm_message_t state
)
1620 wm8903_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1625 static int wm8903_resume(struct snd_soc_codec
*codec
)
1628 u16
*reg_cache
= codec
->reg_cache
;
1629 u16
*tmp_cache
= kmemdup(reg_cache
, sizeof(wm8903_reg_defaults
),
1632 /* Bring the codec back up to standby first to minimise pop/clicks */
1633 wm8903_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1635 /* Sync back everything else */
1637 for (i
= 2; i
< ARRAY_SIZE(wm8903_reg_defaults
); i
++)
1638 if (tmp_cache
[i
] != reg_cache
[i
])
1639 snd_soc_write(codec
, i
, tmp_cache
[i
]);
1642 dev_err(codec
->dev
, "Failed to allocate temporary cache\n");
1648 static int wm8903_probe(struct snd_soc_codec
*codec
)
1650 struct wm8903_platform_data
*pdata
= dev_get_platdata(codec
->dev
);
1651 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1653 int trigger
, irq_pol
;
1656 init_completion(&wm8903
->wseq
);
1658 ret
= snd_soc_codec_set_cache_io(codec
, 8, 16, SND_SOC_I2C
);
1660 dev_err(codec
->dev
, "Failed to set cache I/O: %d\n", ret
);
1664 val
= snd_soc_read(codec
, WM8903_SW_RESET_AND_ID
);
1665 if (val
!= wm8903_reg_defaults
[WM8903_SW_RESET_AND_ID
]) {
1667 "Device with ID register %x is not a WM8903\n", val
);
1671 val
= snd_soc_read(codec
, WM8903_REVISION_NUMBER
);
1672 dev_info(codec
->dev
, "WM8903 revision %d\n",
1673 val
& WM8903_CHIP_REV_MASK
);
1675 wm8903_reset(codec
);
1677 /* Set up GPIOs and microphone detection */
1679 for (i
= 0; i
< ARRAY_SIZE(pdata
->gpio_cfg
); i
++) {
1680 if (!pdata
->gpio_cfg
[i
])
1683 snd_soc_write(codec
, WM8903_GPIO_CONTROL_1
+ i
,
1684 pdata
->gpio_cfg
[i
] & 0xffff);
1687 snd_soc_write(codec
, WM8903_MIC_BIAS_CONTROL_0
,
1690 /* Microphone detection needs the WSEQ clock */
1691 if (pdata
->micdet_cfg
)
1692 snd_soc_update_bits(codec
, WM8903_WRITE_SEQUENCER_0
,
1693 WM8903_WSEQ_ENA
, WM8903_WSEQ_ENA
);
1695 wm8903
->mic_delay
= pdata
->micdet_delay
;
1699 if (pdata
&& pdata
->irq_active_low
) {
1700 trigger
= IRQF_TRIGGER_LOW
;
1701 irq_pol
= WM8903_IRQ_POL
;
1703 trigger
= IRQF_TRIGGER_HIGH
;
1707 snd_soc_update_bits(codec
, WM8903_INTERRUPT_CONTROL
,
1708 WM8903_IRQ_POL
, irq_pol
);
1710 ret
= request_threaded_irq(wm8903
->irq
, NULL
, wm8903_irq
,
1711 trigger
| IRQF_ONESHOT
,
1714 dev_err(codec
->dev
, "Failed to request IRQ: %d\n",
1719 /* Enable write sequencer interrupts */
1720 snd_soc_update_bits(codec
, WM8903_INTERRUPT_STATUS_1_MASK
,
1721 WM8903_IM_WSEQ_BUSY_EINT
, 0);
1724 /* power on device */
1725 wm8903_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1727 /* Latch volume update bits */
1728 val
= snd_soc_read(codec
, WM8903_ADC_DIGITAL_VOLUME_LEFT
);
1729 val
|= WM8903_ADCVU
;
1730 snd_soc_write(codec
, WM8903_ADC_DIGITAL_VOLUME_LEFT
, val
);
1731 snd_soc_write(codec
, WM8903_ADC_DIGITAL_VOLUME_RIGHT
, val
);
1733 val
= snd_soc_read(codec
, WM8903_DAC_DIGITAL_VOLUME_LEFT
);
1734 val
|= WM8903_DACVU
;
1735 snd_soc_write(codec
, WM8903_DAC_DIGITAL_VOLUME_LEFT
, val
);
1736 snd_soc_write(codec
, WM8903_DAC_DIGITAL_VOLUME_RIGHT
, val
);
1738 val
= snd_soc_read(codec
, WM8903_ANALOGUE_OUT1_LEFT
);
1739 val
|= WM8903_HPOUTVU
;
1740 snd_soc_write(codec
, WM8903_ANALOGUE_OUT1_LEFT
, val
);
1741 snd_soc_write(codec
, WM8903_ANALOGUE_OUT1_RIGHT
, val
);
1743 val
= snd_soc_read(codec
, WM8903_ANALOGUE_OUT2_LEFT
);
1744 val
|= WM8903_LINEOUTVU
;
1745 snd_soc_write(codec
, WM8903_ANALOGUE_OUT2_LEFT
, val
);
1746 snd_soc_write(codec
, WM8903_ANALOGUE_OUT2_RIGHT
, val
);
1748 val
= snd_soc_read(codec
, WM8903_ANALOGUE_OUT3_LEFT
);
1749 val
|= WM8903_SPKVU
;
1750 snd_soc_write(codec
, WM8903_ANALOGUE_OUT3_LEFT
, val
);
1751 snd_soc_write(codec
, WM8903_ANALOGUE_OUT3_RIGHT
, val
);
1753 /* Enable DAC soft mute by default */
1754 val
= snd_soc_read(codec
, WM8903_DAC_DIGITAL_1
);
1755 val
|= WM8903_DAC_MUTEMODE
;
1756 snd_soc_write(codec
, WM8903_DAC_DIGITAL_1
, val
);
1758 snd_soc_add_controls(codec
, wm8903_snd_controls
,
1759 ARRAY_SIZE(wm8903_snd_controls
));
1760 wm8903_add_widgets(codec
);
1765 /* power down chip */
1766 static int wm8903_remove(struct snd_soc_codec
*codec
)
1768 wm8903_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1772 static struct snd_soc_codec_driver soc_codec_dev_wm8903
= {
1773 .probe
= wm8903_probe
,
1774 .remove
= wm8903_remove
,
1775 .suspend
= wm8903_suspend
,
1776 .resume
= wm8903_resume
,
1777 .set_bias_level
= wm8903_set_bias_level
,
1778 .reg_cache_size
= ARRAY_SIZE(wm8903_reg_defaults
),
1779 .reg_word_size
= sizeof(u16
),
1780 .reg_cache_default
= wm8903_reg_defaults
,
1781 .volatile_register
= wm8903_volatile_register
,
1784 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1785 static __devinit
int wm8903_i2c_probe(struct i2c_client
*i2c
,
1786 const struct i2c_device_id
*id
)
1788 struct wm8903_priv
*wm8903
;
1791 wm8903
= kzalloc(sizeof(struct wm8903_priv
), GFP_KERNEL
);
1795 i2c_set_clientdata(i2c
, wm8903
);
1796 wm8903
->irq
= i2c
->irq
;
1798 ret
= snd_soc_register_codec(&i2c
->dev
,
1799 &soc_codec_dev_wm8903
, &wm8903_dai
, 1);
1805 static __devexit
int wm8903_i2c_remove(struct i2c_client
*client
)
1807 snd_soc_unregister_codec(&client
->dev
);
1808 kfree(i2c_get_clientdata(client
));
1812 static const struct i2c_device_id wm8903_i2c_id
[] = {
1816 MODULE_DEVICE_TABLE(i2c
, wm8903_i2c_id
);
1818 static struct i2c_driver wm8903_i2c_driver
= {
1820 .name
= "wm8903-codec",
1821 .owner
= THIS_MODULE
,
1823 .probe
= wm8903_i2c_probe
,
1824 .remove
= __devexit_p(wm8903_i2c_remove
),
1825 .id_table
= wm8903_i2c_id
,
1829 static int __init
wm8903_modinit(void)
1832 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1833 ret
= i2c_add_driver(&wm8903_i2c_driver
);
1835 printk(KERN_ERR
"Failed to register wm8903 I2C driver: %d\n",
1841 module_init(wm8903_modinit
);
1843 static void __exit
wm8903_exit(void)
1845 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1846 i2c_del_driver(&wm8903_i2c_driver
);
1849 module_exit(wm8903_exit
);
1851 MODULE_DESCRIPTION("ASoC WM8903 driver");
1852 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
1853 MODULE_LICENSE("GPL");