2 * wm8903.c -- WM8903 ALSA SoC Audio driver
4 * Copyright 2008 Wolfson Microelectronics
5 * Copyright 2011 NVIDIA, Inc.
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * - TDM mode configuration.
15 * - Digital microphone support.
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/init.h>
21 #include <linux/completion.h>
22 #include <linux/delay.h>
23 #include <linux/gpio.h>
25 #include <linux/i2c.h>
26 #include <linux/platform_device.h>
27 #include <linux/slab.h>
28 #include <sound/core.h>
29 #include <sound/jack.h>
30 #include <sound/pcm.h>
31 #include <sound/pcm_params.h>
32 #include <sound/tlv.h>
33 #include <sound/soc.h>
34 #include <sound/initval.h>
35 #include <sound/wm8903.h>
36 #include <trace/events/asoc.h>
40 /* Register defaults at reset */
41 static u16 wm8903_reg_defaults
[] = {
42 0x8903, /* R0 - SW Reset and ID */
43 0x0000, /* R1 - Revision Number */
46 0x0018, /* R4 - Bias Control 0 */
47 0x0000, /* R5 - VMID Control 0 */
48 0x0000, /* R6 - Mic Bias Control 0 */
50 0x0001, /* R8 - Analogue DAC 0 */
52 0x0001, /* R10 - Analogue ADC 0 */
54 0x0000, /* R12 - Power Management 0 */
55 0x0000, /* R13 - Power Management 1 */
56 0x0000, /* R14 - Power Management 2 */
57 0x0000, /* R15 - Power Management 3 */
58 0x0000, /* R16 - Power Management 4 */
59 0x0000, /* R17 - Power Management 5 */
60 0x0000, /* R18 - Power Management 6 */
62 0x0400, /* R20 - Clock Rates 0 */
63 0x0D07, /* R21 - Clock Rates 1 */
64 0x0000, /* R22 - Clock Rates 2 */
66 0x0050, /* R24 - Audio Interface 0 */
67 0x0242, /* R25 - Audio Interface 1 */
68 0x0008, /* R26 - Audio Interface 2 */
69 0x0022, /* R27 - Audio Interface 3 */
72 0x00C0, /* R30 - DAC Digital Volume Left */
73 0x00C0, /* R31 - DAC Digital Volume Right */
74 0x0000, /* R32 - DAC Digital 0 */
75 0x0000, /* R33 - DAC Digital 1 */
78 0x00C0, /* R36 - ADC Digital Volume Left */
79 0x00C0, /* R37 - ADC Digital Volume Right */
80 0x0000, /* R38 - ADC Digital 0 */
81 0x0073, /* R39 - Digital Microphone 0 */
82 0x09BF, /* R40 - DRC 0 */
83 0x3241, /* R41 - DRC 1 */
84 0x0020, /* R42 - DRC 2 */
85 0x0000, /* R43 - DRC 3 */
86 0x0085, /* R44 - Analogue Left Input 0 */
87 0x0085, /* R45 - Analogue Right Input 0 */
88 0x0044, /* R46 - Analogue Left Input 1 */
89 0x0044, /* R47 - Analogue Right Input 1 */
92 0x0008, /* R50 - Analogue Left Mix 0 */
93 0x0004, /* R51 - Analogue Right Mix 0 */
94 0x0000, /* R52 - Analogue Spk Mix Left 0 */
95 0x0000, /* R53 - Analogue Spk Mix Left 1 */
96 0x0000, /* R54 - Analogue Spk Mix Right 0 */
97 0x0000, /* R55 - Analogue Spk Mix Right 1 */
99 0x002D, /* R57 - Analogue OUT1 Left */
100 0x002D, /* R58 - Analogue OUT1 Right */
101 0x0039, /* R59 - Analogue OUT2 Left */
102 0x0039, /* R60 - Analogue OUT2 Right */
104 0x0139, /* R62 - Analogue OUT3 Left */
105 0x0139, /* R63 - Analogue OUT3 Right */
107 0x0000, /* R65 - Analogue SPK Output Control 0 */
109 0x0010, /* R67 - DC Servo 0 */
111 0x00A4, /* R69 - DC Servo 2 */
132 0x0000, /* R90 - Analogue HP 0 */
136 0x0000, /* R94 - Analogue Lineout 0 */
140 0x0000, /* R98 - Charge Pump 0 */
146 0x0000, /* R104 - Class W 0 */
150 0x0000, /* R108 - Write Sequencer 0 */
151 0x0000, /* R109 - Write Sequencer 1 */
152 0x0000, /* R110 - Write Sequencer 2 */
153 0x0000, /* R111 - Write Sequencer 3 */
154 0x0000, /* R112 - Write Sequencer 4 */
156 0x0000, /* R114 - Control Interface */
158 0x00A8, /* R116 - GPIO Control 1 */
159 0x00A8, /* R117 - GPIO Control 2 */
160 0x00A8, /* R118 - GPIO Control 3 */
161 0x0220, /* R119 - GPIO Control 4 */
162 0x01A0, /* R120 - GPIO Control 5 */
163 0x0000, /* R121 - Interrupt Status 1 */
164 0xFFFF, /* R122 - Interrupt Status 1 Mask */
165 0x0000, /* R123 - Interrupt Polarity 1 */
168 0x0000, /* R126 - Interrupt Control */
171 0x0000, /* R129 - Control Interface Test 1 */
191 0x6810, /* R149 - Charge Pump Test 1 */
206 0x0028, /* R164 - Clock Rate Test 4 */
214 0x0000, /* R172 - Analogue Output Bias 0 */
218 struct snd_soc_codec
*codec
;
226 /* Reference count */
229 struct completion wseq
;
231 struct snd_soc_jack
*mic_jack
;
237 #ifdef CONFIG_GPIOLIB
238 struct gpio_chip gpio_chip
;
242 static int wm8903_volatile_register(struct snd_soc_codec
*codec
, unsigned int reg
)
245 case WM8903_SW_RESET_AND_ID
:
246 case WM8903_REVISION_NUMBER
:
247 case WM8903_INTERRUPT_STATUS_1
:
248 case WM8903_WRITE_SEQUENCER_4
:
249 case WM8903_POWER_MANAGEMENT_3
:
250 case WM8903_POWER_MANAGEMENT_2
:
258 static int wm8903_run_sequence(struct snd_soc_codec
*codec
, unsigned int start
)
261 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
265 /* Enable the sequencer if it's not already on */
266 reg
[0] = snd_soc_read(codec
, WM8903_WRITE_SEQUENCER_0
);
267 snd_soc_write(codec
, WM8903_WRITE_SEQUENCER_0
,
268 reg
[0] | WM8903_WSEQ_ENA
);
270 dev_dbg(codec
->dev
, "Starting sequence at %d\n", start
);
272 snd_soc_write(codec
, WM8903_WRITE_SEQUENCER_3
,
273 start
| WM8903_WSEQ_START
);
275 /* Wait for it to complete. If we have the interrupt wired up then
276 * that will break us out of the poll early.
279 wait_for_completion_timeout(&wm8903
->wseq
,
280 msecs_to_jiffies(10));
282 reg
[4] = snd_soc_read(codec
, WM8903_WRITE_SEQUENCER_4
);
283 } while (reg
[4] & WM8903_WSEQ_BUSY
);
285 dev_dbg(codec
->dev
, "Sequence complete\n");
287 /* Disable the sequencer again if we enabled it */
288 snd_soc_write(codec
, WM8903_WRITE_SEQUENCER_0
, reg
[0]);
293 static void wm8903_sync_reg_cache(struct snd_soc_codec
*codec
, u16
*cache
)
297 /* There really ought to be something better we can do here :/ */
298 for (i
= 0; i
< ARRAY_SIZE(wm8903_reg_defaults
); i
++)
299 cache
[i
] = codec
->hw_read(codec
, i
);
302 static void wm8903_reset(struct snd_soc_codec
*codec
)
304 snd_soc_write(codec
, WM8903_SW_RESET_AND_ID
, 0);
305 memcpy(codec
->reg_cache
, wm8903_reg_defaults
,
306 sizeof(wm8903_reg_defaults
));
309 static int wm8903_cp_event(struct snd_soc_dapm_widget
*w
,
310 struct snd_kcontrol
*kcontrol
, int event
)
312 WARN_ON(event
!= SND_SOC_DAPM_POST_PMU
);
319 * When used with DAC outputs only the WM8903 charge pump supports
320 * operation in class W mode, providing very low power consumption
321 * when used with digital sources. Enable and disable this mode
322 * automatically depending on the mixer configuration.
324 * All the relevant controls are simple switches.
326 static int wm8903_class_w_put(struct snd_kcontrol
*kcontrol
,
327 struct snd_ctl_elem_value
*ucontrol
)
329 struct snd_soc_dapm_widget
*widget
= snd_kcontrol_chip(kcontrol
);
330 struct snd_soc_codec
*codec
= widget
->codec
;
331 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
335 reg
= snd_soc_read(codec
, WM8903_CLASS_W_0
);
337 /* Turn it off if we're about to enable bypass */
338 if (ucontrol
->value
.integer
.value
[0]) {
339 if (wm8903
->class_w_users
== 0) {
340 dev_dbg(codec
->dev
, "Disabling Class W\n");
341 snd_soc_write(codec
, WM8903_CLASS_W_0
, reg
&
342 ~(WM8903_CP_DYN_FREQ
| WM8903_CP_DYN_V
));
344 wm8903
->class_w_users
++;
347 /* Implement the change */
348 ret
= snd_soc_dapm_put_volsw(kcontrol
, ucontrol
);
350 /* If we've just disabled the last bypass path turn Class W on */
351 if (!ucontrol
->value
.integer
.value
[0]) {
352 if (wm8903
->class_w_users
== 1) {
353 dev_dbg(codec
->dev
, "Enabling Class W\n");
354 snd_soc_write(codec
, WM8903_CLASS_W_0
, reg
|
355 WM8903_CP_DYN_FREQ
| WM8903_CP_DYN_V
);
357 wm8903
->class_w_users
--;
360 dev_dbg(codec
->dev
, "Bypass use count now %d\n",
361 wm8903
->class_w_users
);
366 #define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
367 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
368 .info = snd_soc_info_volsw, \
369 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
370 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
373 static int wm8903_deemph
[] = { 0, 32000, 44100, 48000 };
375 static int wm8903_set_deemph(struct snd_soc_codec
*codec
)
377 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
380 /* If we're using deemphasis select the nearest available sample
383 if (wm8903
->deemph
) {
385 for (i
= 2; i
< ARRAY_SIZE(wm8903_deemph
); i
++) {
386 if (abs(wm8903_deemph
[i
] - wm8903
->fs
) <
387 abs(wm8903_deemph
[best
] - wm8903
->fs
))
391 val
= best
<< WM8903_DEEMPH_SHIFT
;
397 dev_dbg(codec
->dev
, "Set deemphasis %d (%dHz)\n",
398 best
, wm8903_deemph
[best
]);
400 return snd_soc_update_bits(codec
, WM8903_DAC_DIGITAL_1
,
401 WM8903_DEEMPH_MASK
, val
);
404 static int wm8903_get_deemph(struct snd_kcontrol
*kcontrol
,
405 struct snd_ctl_elem_value
*ucontrol
)
407 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
408 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
410 ucontrol
->value
.enumerated
.item
[0] = wm8903
->deemph
;
415 static int wm8903_put_deemph(struct snd_kcontrol
*kcontrol
,
416 struct snd_ctl_elem_value
*ucontrol
)
418 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
419 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
420 int deemph
= ucontrol
->value
.enumerated
.item
[0];
426 mutex_lock(&codec
->mutex
);
427 if (wm8903
->deemph
!= deemph
) {
428 wm8903
->deemph
= deemph
;
430 wm8903_set_deemph(codec
);
434 mutex_unlock(&codec
->mutex
);
439 /* ALSA can only do steps of .01dB */
440 static const DECLARE_TLV_DB_SCALE(digital_tlv
, -7200, 75, 1);
442 static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv
, -3600, 300, 0);
443 static const DECLARE_TLV_DB_SCALE(out_tlv
, -5700, 100, 0);
445 static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh
, 0, 75, 0);
446 static const DECLARE_TLV_DB_SCALE(drc_tlv_amp
, -2250, 75, 0);
447 static const DECLARE_TLV_DB_SCALE(drc_tlv_min
, 0, 600, 0);
448 static const DECLARE_TLV_DB_SCALE(drc_tlv_max
, 1200, 600, 0);
449 static const DECLARE_TLV_DB_SCALE(drc_tlv_startup
, -300, 50, 0);
451 static const char *hpf_mode_text
[] = {
452 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
455 static const struct soc_enum hpf_mode
=
456 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0
, 5, 4, hpf_mode_text
);
458 static const char *osr_text
[] = {
459 "Low power", "High performance"
462 static const struct soc_enum adc_osr
=
463 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0
, 0, 2, osr_text
);
465 static const struct soc_enum dac_osr
=
466 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1
, 0, 2, osr_text
);
468 static const char *drc_slope_text
[] = {
469 "1", "1/2", "1/4", "1/8", "1/16", "0"
472 static const struct soc_enum drc_slope_r0
=
473 SOC_ENUM_SINGLE(WM8903_DRC_2
, 3, 6, drc_slope_text
);
475 static const struct soc_enum drc_slope_r1
=
476 SOC_ENUM_SINGLE(WM8903_DRC_2
, 0, 6, drc_slope_text
);
478 static const char *drc_attack_text
[] = {
480 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
481 "46.4ms", "92.8ms", "185.6ms"
484 static const struct soc_enum drc_attack
=
485 SOC_ENUM_SINGLE(WM8903_DRC_1
, 12, 11, drc_attack_text
);
487 static const char *drc_decay_text
[] = {
488 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
492 static const struct soc_enum drc_decay
=
493 SOC_ENUM_SINGLE(WM8903_DRC_1
, 8, 9, drc_decay_text
);
495 static const char *drc_ff_delay_text
[] = {
496 "5 samples", "9 samples"
499 static const struct soc_enum drc_ff_delay
=
500 SOC_ENUM_SINGLE(WM8903_DRC_0
, 5, 2, drc_ff_delay_text
);
502 static const char *drc_qr_decay_text
[] = {
503 "0.725ms", "1.45ms", "5.8ms"
506 static const struct soc_enum drc_qr_decay
=
507 SOC_ENUM_SINGLE(WM8903_DRC_1
, 4, 3, drc_qr_decay_text
);
509 static const char *drc_smoothing_text
[] = {
510 "Low", "Medium", "High"
513 static const struct soc_enum drc_smoothing
=
514 SOC_ENUM_SINGLE(WM8903_DRC_0
, 11, 3, drc_smoothing_text
);
516 static const char *soft_mute_text
[] = {
517 "Fast (fs/2)", "Slow (fs/32)"
520 static const struct soc_enum soft_mute
=
521 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1
, 10, 2, soft_mute_text
);
523 static const char *mute_mode_text
[] = {
527 static const struct soc_enum mute_mode
=
528 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1
, 9, 2, mute_mode_text
);
530 static const char *companding_text
[] = {
534 static const struct soc_enum dac_companding
=
535 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 0, 2, companding_text
);
537 static const struct soc_enum adc_companding
=
538 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 2, 2, companding_text
);
540 static const char *input_mode_text
[] = {
541 "Single-Ended", "Differential Line", "Differential Mic"
544 static const struct soc_enum linput_mode_enum
=
545 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1
, 0, 3, input_mode_text
);
547 static const struct soc_enum rinput_mode_enum
=
548 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1
, 0, 3, input_mode_text
);
550 static const char *linput_mux_text
[] = {
551 "IN1L", "IN2L", "IN3L"
554 static const struct soc_enum linput_enum
=
555 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1
, 2, 3, linput_mux_text
);
557 static const struct soc_enum linput_inv_enum
=
558 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1
, 4, 3, linput_mux_text
);
560 static const char *rinput_mux_text
[] = {
561 "IN1R", "IN2R", "IN3R"
564 static const struct soc_enum rinput_enum
=
565 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1
, 2, 3, rinput_mux_text
);
567 static const struct soc_enum rinput_inv_enum
=
568 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1
, 4, 3, rinput_mux_text
);
571 static const char *sidetone_text
[] = {
572 "None", "Left", "Right"
575 static const struct soc_enum lsidetone_enum
=
576 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0
, 2, 3, sidetone_text
);
578 static const struct soc_enum rsidetone_enum
=
579 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0
, 0, 3, sidetone_text
);
581 static const char *aif_text
[] = {
585 static const struct soc_enum lcapture_enum
=
586 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 7, 2, aif_text
);
588 static const struct soc_enum rcapture_enum
=
589 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 6, 2, aif_text
);
591 static const struct soc_enum lplay_enum
=
592 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 5, 2, aif_text
);
594 static const struct soc_enum rplay_enum
=
595 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 4, 2, aif_text
);
597 static const struct snd_kcontrol_new wm8903_snd_controls
[] = {
599 /* Input PGAs - No TLV since the scale depends on PGA mode */
600 SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0
,
602 SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0
,
604 SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1
,
607 SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0
,
609 SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0
,
611 SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1
,
615 SOC_ENUM("ADC OSR", adc_osr
),
616 SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0
, 4, 1, 0),
617 SOC_ENUM("HPF Mode", hpf_mode
),
618 SOC_SINGLE("DRC Switch", WM8903_DRC_0
, 15, 1, 0),
619 SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0
),
620 SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1
),
621 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3
, 5, 124, 1,
623 SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3
, 0, 30, 1, drc_tlv_amp
),
624 SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1
, 2, 3, 1, drc_tlv_min
),
625 SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1
, 0, 3, 0, drc_tlv_max
),
626 SOC_ENUM("DRC Attack Rate", drc_attack
),
627 SOC_ENUM("DRC Decay Rate", drc_decay
),
628 SOC_ENUM("DRC FF Delay", drc_ff_delay
),
629 SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0
, 1, 1, 0),
630 SOC_SINGLE("DRC QR Switch", WM8903_DRC_0
, 2, 1, 0),
631 SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0
, 6, 3, 0, drc_tlv_max
),
632 SOC_ENUM("DRC QR Decay Rate", drc_qr_decay
),
633 SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0
, 3, 1, 0),
634 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0
, 0, 1, 0),
635 SOC_ENUM("DRC Smoothing Threshold", drc_smoothing
),
636 SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0
, 6, 18, 0, drc_tlv_startup
),
638 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT
,
639 WM8903_ADC_DIGITAL_VOLUME_RIGHT
, 1, 96, 0, digital_tlv
),
640 SOC_ENUM("ADC Companding Mode", adc_companding
),
641 SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0
, 3, 1, 0),
643 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0
, 4, 8,
644 12, 0, digital_sidetone_tlv
),
647 SOC_ENUM("DAC OSR", dac_osr
),
648 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT
,
649 WM8903_DAC_DIGITAL_VOLUME_RIGHT
, 1, 120, 0, digital_tlv
),
650 SOC_ENUM("DAC Soft Mute Rate", soft_mute
),
651 SOC_ENUM("DAC Mute Mode", mute_mode
),
652 SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1
, 12, 1, 0),
653 SOC_ENUM("DAC Companding Mode", dac_companding
),
654 SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0
, 1, 1, 0),
655 SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
656 wm8903_get_deemph
, wm8903_put_deemph
),
659 SOC_DOUBLE_R("Headphone Switch",
660 WM8903_ANALOGUE_OUT1_LEFT
, WM8903_ANALOGUE_OUT1_RIGHT
,
662 SOC_DOUBLE_R("Headphone ZC Switch",
663 WM8903_ANALOGUE_OUT1_LEFT
, WM8903_ANALOGUE_OUT1_RIGHT
,
665 SOC_DOUBLE_R_TLV("Headphone Volume",
666 WM8903_ANALOGUE_OUT1_LEFT
, WM8903_ANALOGUE_OUT1_RIGHT
,
670 SOC_DOUBLE_R("Line Out Switch",
671 WM8903_ANALOGUE_OUT2_LEFT
, WM8903_ANALOGUE_OUT2_RIGHT
,
673 SOC_DOUBLE_R("Line Out ZC Switch",
674 WM8903_ANALOGUE_OUT2_LEFT
, WM8903_ANALOGUE_OUT2_RIGHT
,
676 SOC_DOUBLE_R_TLV("Line Out Volume",
677 WM8903_ANALOGUE_OUT2_LEFT
, WM8903_ANALOGUE_OUT2_RIGHT
,
681 SOC_DOUBLE_R("Speaker Switch",
682 WM8903_ANALOGUE_OUT3_LEFT
, WM8903_ANALOGUE_OUT3_RIGHT
, 8, 1, 1),
683 SOC_DOUBLE_R("Speaker ZC Switch",
684 WM8903_ANALOGUE_OUT3_LEFT
, WM8903_ANALOGUE_OUT3_RIGHT
, 6, 1, 0),
685 SOC_DOUBLE_R_TLV("Speaker Volume",
686 WM8903_ANALOGUE_OUT3_LEFT
, WM8903_ANALOGUE_OUT3_RIGHT
,
690 static const struct snd_kcontrol_new linput_mode_mux
=
691 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum
);
693 static const struct snd_kcontrol_new rinput_mode_mux
=
694 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum
);
696 static const struct snd_kcontrol_new linput_mux
=
697 SOC_DAPM_ENUM("Left Input Mux", linput_enum
);
699 static const struct snd_kcontrol_new linput_inv_mux
=
700 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum
);
702 static const struct snd_kcontrol_new rinput_mux
=
703 SOC_DAPM_ENUM("Right Input Mux", rinput_enum
);
705 static const struct snd_kcontrol_new rinput_inv_mux
=
706 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum
);
708 static const struct snd_kcontrol_new lsidetone_mux
=
709 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum
);
711 static const struct snd_kcontrol_new rsidetone_mux
=
712 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum
);
714 static const struct snd_kcontrol_new lcapture_mux
=
715 SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum
);
717 static const struct snd_kcontrol_new rcapture_mux
=
718 SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum
);
720 static const struct snd_kcontrol_new lplay_mux
=
721 SOC_DAPM_ENUM("Left Playback Mux", lplay_enum
);
723 static const struct snd_kcontrol_new rplay_mux
=
724 SOC_DAPM_ENUM("Right Playback Mux", rplay_enum
);
726 static const struct snd_kcontrol_new left_output_mixer
[] = {
727 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 3, 1, 0),
728 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 2, 1, 0),
729 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 1, 1, 0),
730 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 0, 1, 0),
733 static const struct snd_kcontrol_new right_output_mixer
[] = {
734 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 3, 1, 0),
735 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 2, 1, 0),
736 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 1, 1, 0),
737 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 0, 1, 0),
740 static const struct snd_kcontrol_new left_speaker_mixer
[] = {
741 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
, 3, 1, 0),
742 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
, 2, 1, 0),
743 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
, 1, 1, 0),
744 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
,
748 static const struct snd_kcontrol_new right_speaker_mixer
[] = {
749 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
, 3, 1, 0),
750 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
, 2, 1, 0),
751 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
,
753 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
,
757 static const struct snd_soc_dapm_widget wm8903_dapm_widgets
[] = {
758 SND_SOC_DAPM_INPUT("IN1L"),
759 SND_SOC_DAPM_INPUT("IN1R"),
760 SND_SOC_DAPM_INPUT("IN2L"),
761 SND_SOC_DAPM_INPUT("IN2R"),
762 SND_SOC_DAPM_INPUT("IN3L"),
763 SND_SOC_DAPM_INPUT("IN3R"),
765 SND_SOC_DAPM_OUTPUT("HPOUTL"),
766 SND_SOC_DAPM_OUTPUT("HPOUTR"),
767 SND_SOC_DAPM_OUTPUT("LINEOUTL"),
768 SND_SOC_DAPM_OUTPUT("LINEOUTR"),
769 SND_SOC_DAPM_OUTPUT("LOP"),
770 SND_SOC_DAPM_OUTPUT("LON"),
771 SND_SOC_DAPM_OUTPUT("ROP"),
772 SND_SOC_DAPM_OUTPUT("RON"),
774 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0
, 0, 0),
776 SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM
, 0, 0, &linput_mux
),
777 SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM
, 0, 0,
779 SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM
, 0, 0, &linput_mode_mux
),
781 SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM
, 0, 0, &rinput_mux
),
782 SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM
, 0, 0,
784 SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM
, 0, 0, &rinput_mode_mux
),
786 SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0
, 1, 0, NULL
, 0),
787 SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0
, 0, 0, NULL
, 0),
789 SND_SOC_DAPM_ADC("ADCL", NULL
, WM8903_POWER_MANAGEMENT_6
, 1, 0),
790 SND_SOC_DAPM_ADC("ADCR", NULL
, WM8903_POWER_MANAGEMENT_6
, 0, 0),
792 SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM
, 0, 0, &lcapture_mux
),
793 SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM
, 0, 0, &rcapture_mux
),
795 SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM
, 0, 0),
796 SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM
, 0, 0),
798 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM
, 0, 0, &lsidetone_mux
),
799 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM
, 0, 0, &rsidetone_mux
),
801 SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM
, 0, 0),
802 SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM
, 0, 0),
804 SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM
, 0, 0, &lplay_mux
),
805 SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM
, 0, 0, &rplay_mux
),
807 SND_SOC_DAPM_DAC("DACL", NULL
, WM8903_POWER_MANAGEMENT_6
, 3, 0),
808 SND_SOC_DAPM_DAC("DACR", NULL
, WM8903_POWER_MANAGEMENT_6
, 2, 0),
810 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1
, 1, 0,
811 left_output_mixer
, ARRAY_SIZE(left_output_mixer
)),
812 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1
, 0, 0,
813 right_output_mixer
, ARRAY_SIZE(right_output_mixer
)),
815 SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4
, 1, 0,
816 left_speaker_mixer
, ARRAY_SIZE(left_speaker_mixer
)),
817 SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4
, 0, 0,
818 right_speaker_mixer
, ARRAY_SIZE(right_speaker_mixer
)),
820 SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_ANALOGUE_HP_0
,
822 SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_ANALOGUE_HP_0
,
825 SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_ANALOGUE_LINEOUT_0
, 4, 0,
827 SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_ANALOGUE_LINEOUT_0
, 0, 0,
830 SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0
, 7, 0, NULL
, 0),
831 SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0
, 6, 0, NULL
, 0),
832 SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 1, WM8903_ANALOGUE_HP_0
, 5, 0, NULL
, 0),
833 SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0
, 3, 0, NULL
, 0),
834 SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0
, 2, 0, NULL
, 0),
835 SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 1, WM8903_ANALOGUE_HP_0
, 1, 0, NULL
, 0),
837 SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0
, 7, 0,
839 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0
, 6, 0,
841 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 1, WM8903_ANALOGUE_LINEOUT_0
, 5, 0,
843 SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0
, 3, 0,
845 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0
, 2, 0,
847 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 1, WM8903_ANALOGUE_LINEOUT_0
, 1, 0,
850 SND_SOC_DAPM_PGA_S("HPL_DCS", 3, WM8903_DC_SERVO_0
, 3, 0, NULL
, 0),
851 SND_SOC_DAPM_PGA_S("HPR_DCS", 3, WM8903_DC_SERVO_0
, 2, 0, NULL
, 0),
852 SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, WM8903_DC_SERVO_0
, 1, 0, NULL
, 0),
853 SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, WM8903_DC_SERVO_0
, 0, 0, NULL
, 0),
855 SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5
, 1, 0,
857 SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5
, 0, 0,
860 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0
, 0, 0,
861 wm8903_cp_event
, SND_SOC_DAPM_POST_PMU
),
862 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2
, 1, 0, NULL
, 0),
863 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2
, 2, 0, NULL
, 0),
866 static const struct snd_soc_dapm_route intercon
[] = {
868 { "CLK_DSP", NULL
, "CLK_SYS" },
869 { "Mic Bias", NULL
, "CLK_SYS" },
870 { "HPL_DCS", NULL
, "CLK_SYS" },
871 { "HPR_DCS", NULL
, "CLK_SYS" },
872 { "LINEOUTL_DCS", NULL
, "CLK_SYS" },
873 { "LINEOUTR_DCS", NULL
, "CLK_SYS" },
875 { "Left Input Mux", "IN1L", "IN1L" },
876 { "Left Input Mux", "IN2L", "IN2L" },
877 { "Left Input Mux", "IN3L", "IN3L" },
879 { "Left Input Inverting Mux", "IN1L", "IN1L" },
880 { "Left Input Inverting Mux", "IN2L", "IN2L" },
881 { "Left Input Inverting Mux", "IN3L", "IN3L" },
883 { "Right Input Mux", "IN1R", "IN1R" },
884 { "Right Input Mux", "IN2R", "IN2R" },
885 { "Right Input Mux", "IN3R", "IN3R" },
887 { "Right Input Inverting Mux", "IN1R", "IN1R" },
888 { "Right Input Inverting Mux", "IN2R", "IN2R" },
889 { "Right Input Inverting Mux", "IN3R", "IN3R" },
891 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
892 { "Left Input Mode Mux", "Differential Line",
894 { "Left Input Mode Mux", "Differential Line",
895 "Left Input Inverting Mux" },
896 { "Left Input Mode Mux", "Differential Mic",
898 { "Left Input Mode Mux", "Differential Mic",
899 "Left Input Inverting Mux" },
901 { "Right Input Mode Mux", "Single-Ended",
902 "Right Input Inverting Mux" },
903 { "Right Input Mode Mux", "Differential Line",
905 { "Right Input Mode Mux", "Differential Line",
906 "Right Input Inverting Mux" },
907 { "Right Input Mode Mux", "Differential Mic",
909 { "Right Input Mode Mux", "Differential Mic",
910 "Right Input Inverting Mux" },
912 { "Left Input PGA", NULL
, "Left Input Mode Mux" },
913 { "Right Input PGA", NULL
, "Right Input Mode Mux" },
915 { "Left Capture Mux", "Left", "ADCL" },
916 { "Left Capture Mux", "Right", "ADCR" },
918 { "Right Capture Mux", "Left", "ADCL" },
919 { "Right Capture Mux", "Right", "ADCR" },
921 { "AIFTXL", NULL
, "Left Capture Mux" },
922 { "AIFTXR", NULL
, "Right Capture Mux" },
924 { "ADCL", NULL
, "Left Input PGA" },
925 { "ADCL", NULL
, "CLK_DSP" },
926 { "ADCR", NULL
, "Right Input PGA" },
927 { "ADCR", NULL
, "CLK_DSP" },
929 { "Left Playback Mux", "Left", "AIFRXL" },
930 { "Left Playback Mux", "Right", "AIFRXR" },
932 { "Right Playback Mux", "Left", "AIFRXL" },
933 { "Right Playback Mux", "Right", "AIFRXR" },
935 { "DACL Sidetone", "Left", "ADCL" },
936 { "DACL Sidetone", "Right", "ADCR" },
937 { "DACR Sidetone", "Left", "ADCL" },
938 { "DACR Sidetone", "Right", "ADCR" },
940 { "DACL", NULL
, "Left Playback Mux" },
941 { "DACL", NULL
, "DACL Sidetone" },
942 { "DACL", NULL
, "CLK_DSP" },
944 { "DACR", NULL
, "Right Playback Mux" },
945 { "DACR", NULL
, "DACR Sidetone" },
946 { "DACR", NULL
, "CLK_DSP" },
948 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
949 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
950 { "Left Output Mixer", "DACL Switch", "DACL" },
951 { "Left Output Mixer", "DACR Switch", "DACR" },
953 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
954 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
955 { "Right Output Mixer", "DACL Switch", "DACL" },
956 { "Right Output Mixer", "DACR Switch", "DACR" },
958 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
959 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
960 { "Left Speaker Mixer", "DACL Switch", "DACL" },
961 { "Left Speaker Mixer", "DACR Switch", "DACR" },
963 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
964 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
965 { "Right Speaker Mixer", "DACL Switch", "DACL" },
966 { "Right Speaker Mixer", "DACR Switch", "DACR" },
968 { "Left Line Output PGA", NULL
, "Left Output Mixer" },
969 { "Right Line Output PGA", NULL
, "Right Output Mixer" },
971 { "Left Headphone Output PGA", NULL
, "Left Output Mixer" },
972 { "Right Headphone Output PGA", NULL
, "Right Output Mixer" },
974 { "Left Speaker PGA", NULL
, "Left Speaker Mixer" },
975 { "Right Speaker PGA", NULL
, "Right Speaker Mixer" },
977 { "HPL_ENA_DLY", NULL
, "Left Headphone Output PGA" },
978 { "HPR_ENA_DLY", NULL
, "Right Headphone Output PGA" },
979 { "LINEOUTL_ENA_DLY", NULL
, "Left Line Output PGA" },
980 { "LINEOUTR_ENA_DLY", NULL
, "Right Line Output PGA" },
982 { "HPL_DCS", NULL
, "HPL_ENA_DLY" },
983 { "HPR_DCS", NULL
, "HPR_ENA_DLY" },
984 { "LINEOUTL_DCS", NULL
, "LINEOUTL_ENA_DLY" },
985 { "LINEOUTR_DCS", NULL
, "LINEOUTR_ENA_DLY" },
987 { "HPL_ENA_OUTP", NULL
, "HPL_DCS" },
988 { "HPR_ENA_OUTP", NULL
, "HPR_DCS" },
989 { "LINEOUTL_ENA_OUTP", NULL
, "LINEOUTL_DCS" },
990 { "LINEOUTR_ENA_OUTP", NULL
, "LINEOUTR_DCS" },
992 { "HPL_RMV_SHORT", NULL
, "HPL_ENA_OUTP" },
993 { "HPR_RMV_SHORT", NULL
, "HPR_ENA_OUTP" },
994 { "LINEOUTL_RMV_SHORT", NULL
, "LINEOUTL_ENA_OUTP" },
995 { "LINEOUTR_RMV_SHORT", NULL
, "LINEOUTR_ENA_OUTP" },
997 { "HPOUTL", NULL
, "HPL_RMV_SHORT" },
998 { "HPOUTR", NULL
, "HPR_RMV_SHORT" },
999 { "LINEOUTL", NULL
, "LINEOUTL_RMV_SHORT" },
1000 { "LINEOUTR", NULL
, "LINEOUTR_RMV_SHORT" },
1002 { "LOP", NULL
, "Left Speaker PGA" },
1003 { "LON", NULL
, "Left Speaker PGA" },
1005 { "ROP", NULL
, "Right Speaker PGA" },
1006 { "RON", NULL
, "Right Speaker PGA" },
1008 { "Left Headphone Output PGA", NULL
, "Charge Pump" },
1009 { "Right Headphone Output PGA", NULL
, "Charge Pump" },
1010 { "Left Line Output PGA", NULL
, "Charge Pump" },
1011 { "Right Line Output PGA", NULL
, "Charge Pump" },
1014 static int wm8903_add_widgets(struct snd_soc_codec
*codec
)
1016 struct snd_soc_dapm_context
*dapm
= &codec
->dapm
;
1018 snd_soc_dapm_new_controls(dapm
, wm8903_dapm_widgets
,
1019 ARRAY_SIZE(wm8903_dapm_widgets
));
1020 snd_soc_dapm_add_routes(dapm
, intercon
, ARRAY_SIZE(intercon
));
1025 static int wm8903_set_bias_level(struct snd_soc_codec
*codec
,
1026 enum snd_soc_bias_level level
)
1031 case SND_SOC_BIAS_ON
:
1032 case SND_SOC_BIAS_PREPARE
:
1033 reg
= snd_soc_read(codec
, WM8903_VMID_CONTROL_0
);
1034 reg
&= ~(WM8903_VMID_RES_MASK
);
1035 reg
|= WM8903_VMID_RES_50K
;
1036 snd_soc_write(codec
, WM8903_VMID_CONTROL_0
, reg
);
1039 case SND_SOC_BIAS_STANDBY
:
1040 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
1041 snd_soc_write(codec
, WM8903_CLOCK_RATES_2
,
1042 WM8903_CLK_SYS_ENA
);
1044 /* Change DC servo dither level in startup sequence */
1045 snd_soc_write(codec
, WM8903_WRITE_SEQUENCER_0
, 0x11);
1046 snd_soc_write(codec
, WM8903_WRITE_SEQUENCER_1
, 0x1257);
1047 snd_soc_write(codec
, WM8903_WRITE_SEQUENCER_2
, 0x2);
1049 wm8903_run_sequence(codec
, 0);
1050 wm8903_sync_reg_cache(codec
, codec
->reg_cache
);
1052 /* By default no bypass paths are enabled so
1053 * enable Class W support.
1055 dev_dbg(codec
->dev
, "Enabling Class W\n");
1056 snd_soc_update_bits(codec
, WM8903_CLASS_W_0
,
1057 WM8903_CP_DYN_FREQ
|
1059 WM8903_CP_DYN_FREQ
|
1063 reg
= snd_soc_read(codec
, WM8903_VMID_CONTROL_0
);
1064 reg
&= ~(WM8903_VMID_RES_MASK
);
1065 reg
|= WM8903_VMID_RES_250K
;
1066 snd_soc_write(codec
, WM8903_VMID_CONTROL_0
, reg
);
1069 case SND_SOC_BIAS_OFF
:
1070 snd_soc_update_bits(codec
, WM8903_CLOCK_RATES_2
,
1071 WM8903_CLK_SYS_ENA
, WM8903_CLK_SYS_ENA
);
1072 wm8903_run_sequence(codec
, 32);
1073 snd_soc_update_bits(codec
, WM8903_CLOCK_RATES_2
,
1074 WM8903_CLK_SYS_ENA
, 0);
1078 codec
->dapm
.bias_level
= level
;
1083 static int wm8903_set_dai_sysclk(struct snd_soc_dai
*codec_dai
,
1084 int clk_id
, unsigned int freq
, int dir
)
1086 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1087 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1089 wm8903
->sysclk
= freq
;
1094 static int wm8903_set_dai_fmt(struct snd_soc_dai
*codec_dai
,
1097 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1098 u16 aif1
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_1
);
1100 aif1
&= ~(WM8903_LRCLK_DIR
| WM8903_BCLK_DIR
| WM8903_AIF_FMT_MASK
|
1101 WM8903_AIF_LRCLK_INV
| WM8903_AIF_BCLK_INV
);
1103 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
1104 case SND_SOC_DAIFMT_CBS_CFS
:
1106 case SND_SOC_DAIFMT_CBS_CFM
:
1107 aif1
|= WM8903_LRCLK_DIR
;
1109 case SND_SOC_DAIFMT_CBM_CFM
:
1110 aif1
|= WM8903_LRCLK_DIR
| WM8903_BCLK_DIR
;
1112 case SND_SOC_DAIFMT_CBM_CFS
:
1113 aif1
|= WM8903_BCLK_DIR
;
1119 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1120 case SND_SOC_DAIFMT_DSP_A
:
1123 case SND_SOC_DAIFMT_DSP_B
:
1124 aif1
|= 0x3 | WM8903_AIF_LRCLK_INV
;
1126 case SND_SOC_DAIFMT_I2S
:
1129 case SND_SOC_DAIFMT_RIGHT_J
:
1132 case SND_SOC_DAIFMT_LEFT_J
:
1138 /* Clock inversion */
1139 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1140 case SND_SOC_DAIFMT_DSP_A
:
1141 case SND_SOC_DAIFMT_DSP_B
:
1142 /* frame inversion not valid for DSP modes */
1143 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1144 case SND_SOC_DAIFMT_NB_NF
:
1146 case SND_SOC_DAIFMT_IB_NF
:
1147 aif1
|= WM8903_AIF_BCLK_INV
;
1153 case SND_SOC_DAIFMT_I2S
:
1154 case SND_SOC_DAIFMT_RIGHT_J
:
1155 case SND_SOC_DAIFMT_LEFT_J
:
1156 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1157 case SND_SOC_DAIFMT_NB_NF
:
1159 case SND_SOC_DAIFMT_IB_IF
:
1160 aif1
|= WM8903_AIF_BCLK_INV
| WM8903_AIF_LRCLK_INV
;
1162 case SND_SOC_DAIFMT_IB_NF
:
1163 aif1
|= WM8903_AIF_BCLK_INV
;
1165 case SND_SOC_DAIFMT_NB_IF
:
1166 aif1
|= WM8903_AIF_LRCLK_INV
;
1176 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_1
, aif1
);
1181 static int wm8903_digital_mute(struct snd_soc_dai
*codec_dai
, int mute
)
1183 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1186 reg
= snd_soc_read(codec
, WM8903_DAC_DIGITAL_1
);
1189 reg
|= WM8903_DAC_MUTE
;
1191 reg
&= ~WM8903_DAC_MUTE
;
1193 snd_soc_write(codec
, WM8903_DAC_DIGITAL_1
, reg
);
1198 /* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1199 * for optimal performance so we list the lower rates first and match
1200 * on the last match we find. */
1206 } clk_sys_ratios
[] = {
1207 { 64, 0x0, 0x0, 1 },
1208 { 68, 0x0, 0x1, 1 },
1209 { 125, 0x0, 0x2, 1 },
1210 { 128, 0x1, 0x0, 1 },
1211 { 136, 0x1, 0x1, 1 },
1212 { 192, 0x2, 0x0, 1 },
1213 { 204, 0x2, 0x1, 1 },
1215 { 64, 0x0, 0x0, 2 },
1216 { 68, 0x0, 0x1, 2 },
1217 { 125, 0x0, 0x2, 2 },
1218 { 128, 0x1, 0x0, 2 },
1219 { 136, 0x1, 0x1, 2 },
1220 { 192, 0x2, 0x0, 2 },
1221 { 204, 0x2, 0x1, 2 },
1223 { 250, 0x2, 0x2, 1 },
1224 { 256, 0x3, 0x0, 1 },
1225 { 272, 0x3, 0x1, 1 },
1226 { 384, 0x4, 0x0, 1 },
1227 { 408, 0x4, 0x1, 1 },
1228 { 375, 0x4, 0x2, 1 },
1229 { 512, 0x5, 0x0, 1 },
1230 { 544, 0x5, 0x1, 1 },
1231 { 500, 0x5, 0x2, 1 },
1232 { 768, 0x6, 0x0, 1 },
1233 { 816, 0x6, 0x1, 1 },
1234 { 750, 0x6, 0x2, 1 },
1235 { 1024, 0x7, 0x0, 1 },
1236 { 1088, 0x7, 0x1, 1 },
1237 { 1000, 0x7, 0x2, 1 },
1238 { 1408, 0x8, 0x0, 1 },
1239 { 1496, 0x8, 0x1, 1 },
1240 { 1536, 0x9, 0x0, 1 },
1241 { 1632, 0x9, 0x1, 1 },
1242 { 1500, 0x9, 0x2, 1 },
1244 { 250, 0x2, 0x2, 2 },
1245 { 256, 0x3, 0x0, 2 },
1246 { 272, 0x3, 0x1, 2 },
1247 { 384, 0x4, 0x0, 2 },
1248 { 408, 0x4, 0x1, 2 },
1249 { 375, 0x4, 0x2, 2 },
1250 { 512, 0x5, 0x0, 2 },
1251 { 544, 0x5, 0x1, 2 },
1252 { 500, 0x5, 0x2, 2 },
1253 { 768, 0x6, 0x0, 2 },
1254 { 816, 0x6, 0x1, 2 },
1255 { 750, 0x6, 0x2, 2 },
1256 { 1024, 0x7, 0x0, 2 },
1257 { 1088, 0x7, 0x1, 2 },
1258 { 1000, 0x7, 0x2, 2 },
1259 { 1408, 0x8, 0x0, 2 },
1260 { 1496, 0x8, 0x1, 2 },
1261 { 1536, 0x9, 0x0, 2 },
1262 { 1632, 0x9, 0x1, 2 },
1263 { 1500, 0x9, 0x2, 2 },
1266 /* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1290 /* Sample rates for DSP */
1294 } sample_rates
[] = {
1309 static int wm8903_hw_params(struct snd_pcm_substream
*substream
,
1310 struct snd_pcm_hw_params
*params
,
1311 struct snd_soc_dai
*dai
)
1313 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
1314 struct snd_soc_codec
*codec
=rtd
->codec
;
1315 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1316 int fs
= params_rate(params
);
1326 u16 aif1
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_1
);
1327 u16 aif2
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_2
);
1328 u16 aif3
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_3
);
1329 u16 clock0
= snd_soc_read(codec
, WM8903_CLOCK_RATES_0
);
1330 u16 clock1
= snd_soc_read(codec
, WM8903_CLOCK_RATES_1
);
1331 u16 dac_digital1
= snd_soc_read(codec
, WM8903_DAC_DIGITAL_1
);
1333 /* Enable sloping stopband filter for low sample rates */
1335 dac_digital1
|= WM8903_DAC_SB_FILT
;
1337 dac_digital1
&= ~WM8903_DAC_SB_FILT
;
1339 /* Configure sample rate logic for DSP - choose nearest rate */
1341 best_val
= abs(sample_rates
[dsp_config
].rate
- fs
);
1342 for (i
= 1; i
< ARRAY_SIZE(sample_rates
); i
++) {
1343 cur_val
= abs(sample_rates
[i
].rate
- fs
);
1344 if (cur_val
<= best_val
) {
1350 dev_dbg(codec
->dev
, "DSP fs = %dHz\n", sample_rates
[dsp_config
].rate
);
1351 clock1
&= ~WM8903_SAMPLE_RATE_MASK
;
1352 clock1
|= sample_rates
[dsp_config
].value
;
1354 aif1
&= ~WM8903_AIF_WL_MASK
;
1356 switch (params_format(params
)) {
1357 case SNDRV_PCM_FORMAT_S16_LE
:
1360 case SNDRV_PCM_FORMAT_S20_3LE
:
1364 case SNDRV_PCM_FORMAT_S24_LE
:
1368 case SNDRV_PCM_FORMAT_S32_LE
:
1376 dev_dbg(codec
->dev
, "MCLK = %dHz, target sample rate = %dHz\n",
1377 wm8903
->sysclk
, fs
);
1379 /* We may not have an MCLK which allows us to generate exactly
1380 * the clock we want, particularly with USB derived inputs, so
1384 best_val
= abs((wm8903
->sysclk
/
1385 (clk_sys_ratios
[0].mclk_div
*
1386 clk_sys_ratios
[0].div
)) - fs
);
1387 for (i
= 1; i
< ARRAY_SIZE(clk_sys_ratios
); i
++) {
1388 cur_val
= abs((wm8903
->sysclk
/
1389 (clk_sys_ratios
[i
].mclk_div
*
1390 clk_sys_ratios
[i
].div
)) - fs
);
1392 if (cur_val
<= best_val
) {
1398 if (clk_sys_ratios
[clk_config
].mclk_div
== 2) {
1399 clock0
|= WM8903_MCLKDIV2
;
1400 clk_sys
= wm8903
->sysclk
/ 2;
1402 clock0
&= ~WM8903_MCLKDIV2
;
1403 clk_sys
= wm8903
->sysclk
;
1406 clock1
&= ~(WM8903_CLK_SYS_RATE_MASK
|
1407 WM8903_CLK_SYS_MODE_MASK
);
1408 clock1
|= clk_sys_ratios
[clk_config
].rate
<< WM8903_CLK_SYS_RATE_SHIFT
;
1409 clock1
|= clk_sys_ratios
[clk_config
].mode
<< WM8903_CLK_SYS_MODE_SHIFT
;
1411 dev_dbg(codec
->dev
, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
1412 clk_sys_ratios
[clk_config
].rate
,
1413 clk_sys_ratios
[clk_config
].mode
,
1414 clk_sys_ratios
[clk_config
].div
);
1416 dev_dbg(codec
->dev
, "Actual CLK_SYS = %dHz\n", clk_sys
);
1418 /* We may not get quite the right frequency if using
1419 * approximate clocks so look for the closest match that is
1420 * higher than the target (we need to ensure that there enough
1421 * BCLKs to clock out the samples).
1424 best_val
= ((clk_sys
* 10) / bclk_divs
[0].ratio
) - bclk
;
1426 while (i
< ARRAY_SIZE(bclk_divs
)) {
1427 cur_val
= ((clk_sys
* 10) / bclk_divs
[i
].ratio
) - bclk
;
1428 if (cur_val
< 0) /* BCLK table is sorted */
1435 aif2
&= ~WM8903_BCLK_DIV_MASK
;
1436 aif3
&= ~WM8903_LRCLK_RATE_MASK
;
1438 dev_dbg(codec
->dev
, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
1439 bclk_divs
[bclk_div
].ratio
/ 10, bclk
,
1440 (clk_sys
* 10) / bclk_divs
[bclk_div
].ratio
);
1442 aif2
|= bclk_divs
[bclk_div
].div
;
1445 wm8903
->fs
= params_rate(params
);
1446 wm8903_set_deemph(codec
);
1448 snd_soc_write(codec
, WM8903_CLOCK_RATES_0
, clock0
);
1449 snd_soc_write(codec
, WM8903_CLOCK_RATES_1
, clock1
);
1450 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_1
, aif1
);
1451 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_2
, aif2
);
1452 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_3
, aif3
);
1453 snd_soc_write(codec
, WM8903_DAC_DIGITAL_1
, dac_digital1
);
1459 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1461 * @codec: WM8903 codec
1462 * @jack: jack to report detection events on
1463 * @det: value to report for presence detection
1464 * @shrt: value to report for short detection
1466 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1467 * being used to bring out signals to the processor then only platform
1468 * data configuration is needed for WM8903 and processor GPIOs should
1469 * be configured using snd_soc_jack_add_gpios() instead.
1471 * The current threasholds for detection should be configured using
1472 * micdet_cfg in the platform data. Using this function will force on
1473 * the microphone bias for the device.
1475 int wm8903_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
1478 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1479 int irq_mask
= WM8903_MICDET_EINT
| WM8903_MICSHRT_EINT
;
1481 dev_dbg(codec
->dev
, "Enabling microphone detection: %x %x\n",
1484 /* Store the configuration */
1485 wm8903
->mic_jack
= jack
;
1486 wm8903
->mic_det
= det
;
1487 wm8903
->mic_short
= shrt
;
1489 /* Enable interrupts we've got a report configured for */
1491 irq_mask
&= ~WM8903_MICDET_EINT
;
1493 irq_mask
&= ~WM8903_MICSHRT_EINT
;
1495 snd_soc_update_bits(codec
, WM8903_INTERRUPT_STATUS_1_MASK
,
1496 WM8903_MICDET_EINT
| WM8903_MICSHRT_EINT
,
1500 /* Enable mic detection, this may not have been set through
1501 * platform data (eg, if the defaults are OK). */
1502 snd_soc_update_bits(codec
, WM8903_WRITE_SEQUENCER_0
,
1503 WM8903_WSEQ_ENA
, WM8903_WSEQ_ENA
);
1504 snd_soc_update_bits(codec
, WM8903_MIC_BIAS_CONTROL_0
,
1505 WM8903_MICDET_ENA
, WM8903_MICDET_ENA
);
1507 snd_soc_update_bits(codec
, WM8903_MIC_BIAS_CONTROL_0
,
1508 WM8903_MICDET_ENA
, 0);
1513 EXPORT_SYMBOL_GPL(wm8903_mic_detect
);
1515 static irqreturn_t
wm8903_irq(int irq
, void *data
)
1517 struct snd_soc_codec
*codec
= data
;
1518 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1522 int mask
= ~snd_soc_read(codec
, WM8903_INTERRUPT_STATUS_1_MASK
);
1524 int_val
= snd_soc_read(codec
, WM8903_INTERRUPT_STATUS_1
) & mask
;
1526 if (int_val
& WM8903_WSEQ_BUSY_EINT
) {
1527 dev_dbg(codec
->dev
, "Write sequencer done\n");
1528 complete(&wm8903
->wseq
);
1532 * The rest is microphone jack detection. We need to manually
1533 * invert the polarity of the interrupt after each event - to
1534 * simplify the code keep track of the last state we reported
1535 * and just invert the relevant bits in both the report and
1536 * the polarity register.
1538 mic_report
= wm8903
->mic_last_report
;
1539 int_pol
= snd_soc_read(codec
, WM8903_INTERRUPT_POLARITY_1
);
1541 #ifndef CONFIG_SND_SOC_WM8903_MODULE
1542 if (int_val
& (WM8903_MICSHRT_EINT
| WM8903_MICDET_EINT
))
1543 trace_snd_soc_jack_irq(dev_name(codec
->dev
));
1546 if (int_val
& WM8903_MICSHRT_EINT
) {
1547 dev_dbg(codec
->dev
, "Microphone short (pol=%x)\n", int_pol
);
1549 mic_report
^= wm8903
->mic_short
;
1550 int_pol
^= WM8903_MICSHRT_INV
;
1553 if (int_val
& WM8903_MICDET_EINT
) {
1554 dev_dbg(codec
->dev
, "Microphone detect (pol=%x)\n", int_pol
);
1556 mic_report
^= wm8903
->mic_det
;
1557 int_pol
^= WM8903_MICDET_INV
;
1559 msleep(wm8903
->mic_delay
);
1562 snd_soc_update_bits(codec
, WM8903_INTERRUPT_POLARITY_1
,
1563 WM8903_MICSHRT_INV
| WM8903_MICDET_INV
, int_pol
);
1565 snd_soc_jack_report(wm8903
->mic_jack
, mic_report
,
1566 wm8903
->mic_short
| wm8903
->mic_det
);
1568 wm8903
->mic_last_report
= mic_report
;
1573 #define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1574 SNDRV_PCM_RATE_11025 | \
1575 SNDRV_PCM_RATE_16000 | \
1576 SNDRV_PCM_RATE_22050 | \
1577 SNDRV_PCM_RATE_32000 | \
1578 SNDRV_PCM_RATE_44100 | \
1579 SNDRV_PCM_RATE_48000 | \
1580 SNDRV_PCM_RATE_88200 | \
1581 SNDRV_PCM_RATE_96000)
1583 #define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1584 SNDRV_PCM_RATE_11025 | \
1585 SNDRV_PCM_RATE_16000 | \
1586 SNDRV_PCM_RATE_22050 | \
1587 SNDRV_PCM_RATE_32000 | \
1588 SNDRV_PCM_RATE_44100 | \
1589 SNDRV_PCM_RATE_48000)
1591 #define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1592 SNDRV_PCM_FMTBIT_S20_3LE |\
1593 SNDRV_PCM_FMTBIT_S24_LE)
1595 static struct snd_soc_dai_ops wm8903_dai_ops
= {
1596 .hw_params
= wm8903_hw_params
,
1597 .digital_mute
= wm8903_digital_mute
,
1598 .set_fmt
= wm8903_set_dai_fmt
,
1599 .set_sysclk
= wm8903_set_dai_sysclk
,
1602 static struct snd_soc_dai_driver wm8903_dai
= {
1603 .name
= "wm8903-hifi",
1605 .stream_name
= "Playback",
1608 .rates
= WM8903_PLAYBACK_RATES
,
1609 .formats
= WM8903_FORMATS
,
1612 .stream_name
= "Capture",
1615 .rates
= WM8903_CAPTURE_RATES
,
1616 .formats
= WM8903_FORMATS
,
1618 .ops
= &wm8903_dai_ops
,
1619 .symmetric_rates
= 1,
1622 static int wm8903_suspend(struct snd_soc_codec
*codec
, pm_message_t state
)
1624 wm8903_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1629 static int wm8903_resume(struct snd_soc_codec
*codec
)
1632 u16
*reg_cache
= codec
->reg_cache
;
1633 u16
*tmp_cache
= kmemdup(reg_cache
, sizeof(wm8903_reg_defaults
),
1636 /* Bring the codec back up to standby first to minimise pop/clicks */
1637 wm8903_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1639 /* Sync back everything else */
1641 for (i
= 2; i
< ARRAY_SIZE(wm8903_reg_defaults
); i
++)
1642 if (tmp_cache
[i
] != reg_cache
[i
])
1643 snd_soc_write(codec
, i
, tmp_cache
[i
]);
1646 dev_err(codec
->dev
, "Failed to allocate temporary cache\n");
1652 #ifdef CONFIG_GPIOLIB
1653 static inline struct wm8903_priv
*gpio_to_wm8903(struct gpio_chip
*chip
)
1655 return container_of(chip
, struct wm8903_priv
, gpio_chip
);
1658 static int wm8903_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
1660 if (offset
>= WM8903_NUM_GPIO
)
1666 static int wm8903_gpio_direction_in(struct gpio_chip
*chip
, unsigned offset
)
1668 struct wm8903_priv
*wm8903
= gpio_to_wm8903(chip
);
1669 struct snd_soc_codec
*codec
= wm8903
->codec
;
1670 unsigned int mask
, val
;
1672 mask
= WM8903_GP1_FN_MASK
| WM8903_GP1_DIR_MASK
;
1673 val
= (WM8903_GPn_FN_GPIO_INPUT
<< WM8903_GP1_FN_SHIFT
) |
1676 return snd_soc_update_bits(codec
, WM8903_GPIO_CONTROL_1
+ offset
,
1680 static int wm8903_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
1682 struct wm8903_priv
*wm8903
= gpio_to_wm8903(chip
);
1683 struct snd_soc_codec
*codec
= wm8903
->codec
;
1686 reg
= snd_soc_read(codec
, WM8903_GPIO_CONTROL_1
+ offset
);
1688 return (reg
& WM8903_GP1_LVL_MASK
) >> WM8903_GP1_LVL_SHIFT
;
1691 static int wm8903_gpio_direction_out(struct gpio_chip
*chip
,
1692 unsigned offset
, int value
)
1694 struct wm8903_priv
*wm8903
= gpio_to_wm8903(chip
);
1695 struct snd_soc_codec
*codec
= wm8903
->codec
;
1696 unsigned int mask
, val
;
1698 mask
= WM8903_GP1_FN_MASK
| WM8903_GP1_DIR_MASK
| WM8903_GP1_LVL_MASK
;
1699 val
= (WM8903_GPn_FN_GPIO_OUTPUT
<< WM8903_GP1_FN_SHIFT
) |
1700 (value
<< WM8903_GP2_LVL_SHIFT
);
1702 return snd_soc_update_bits(codec
, WM8903_GPIO_CONTROL_1
+ offset
,
1706 static void wm8903_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
1708 struct wm8903_priv
*wm8903
= gpio_to_wm8903(chip
);
1709 struct snd_soc_codec
*codec
= wm8903
->codec
;
1711 snd_soc_update_bits(codec
, WM8903_GPIO_CONTROL_1
+ offset
,
1712 WM8903_GP1_LVL_MASK
,
1713 !!value
<< WM8903_GP1_LVL_SHIFT
);
1716 static struct gpio_chip wm8903_template_chip
= {
1718 .owner
= THIS_MODULE
,
1719 .request
= wm8903_gpio_request
,
1720 .direction_input
= wm8903_gpio_direction_in
,
1721 .get
= wm8903_gpio_get
,
1722 .direction_output
= wm8903_gpio_direction_out
,
1723 .set
= wm8903_gpio_set
,
1727 static void wm8903_init_gpio(struct snd_soc_codec
*codec
)
1729 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1730 struct wm8903_platform_data
*pdata
= dev_get_platdata(codec
->dev
);
1733 wm8903
->gpio_chip
= wm8903_template_chip
;
1734 wm8903
->gpio_chip
.ngpio
= WM8903_NUM_GPIO
;
1735 wm8903
->gpio_chip
.dev
= codec
->dev
;
1737 if (pdata
&& pdata
->gpio_base
)
1738 wm8903
->gpio_chip
.base
= pdata
->gpio_base
;
1740 wm8903
->gpio_chip
.base
= -1;
1742 ret
= gpiochip_add(&wm8903
->gpio_chip
);
1744 dev_err(codec
->dev
, "Failed to add GPIOs: %d\n", ret
);
1747 static void wm8903_free_gpio(struct snd_soc_codec
*codec
)
1749 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1752 ret
= gpiochip_remove(&wm8903
->gpio_chip
);
1754 dev_err(codec
->dev
, "Failed to remove GPIOs: %d\n", ret
);
1757 static void wm8903_init_gpio(struct snd_soc_codec
*codec
)
1761 static void wm8903_free_gpio(struct snd_soc_codec
*codec
)
1766 static int wm8903_probe(struct snd_soc_codec
*codec
)
1768 struct wm8903_platform_data
*pdata
= dev_get_platdata(codec
->dev
);
1769 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1771 int trigger
, irq_pol
;
1774 wm8903
->codec
= codec
;
1775 init_completion(&wm8903
->wseq
);
1777 ret
= snd_soc_codec_set_cache_io(codec
, 8, 16, SND_SOC_I2C
);
1779 dev_err(codec
->dev
, "Failed to set cache I/O: %d\n", ret
);
1783 val
= snd_soc_read(codec
, WM8903_SW_RESET_AND_ID
);
1784 if (val
!= wm8903_reg_defaults
[WM8903_SW_RESET_AND_ID
]) {
1786 "Device with ID register %x is not a WM8903\n", val
);
1790 val
= snd_soc_read(codec
, WM8903_REVISION_NUMBER
);
1791 dev_info(codec
->dev
, "WM8903 revision %c\n",
1792 (val
& WM8903_CHIP_REV_MASK
) + 'A');
1794 wm8903_reset(codec
);
1796 /* Set up GPIOs and microphone detection */
1798 for (i
= 0; i
< ARRAY_SIZE(pdata
->gpio_cfg
); i
++) {
1799 if (pdata
->gpio_cfg
[i
] == WM8903_GPIO_NO_CONFIG
)
1802 snd_soc_write(codec
, WM8903_GPIO_CONTROL_1
+ i
,
1803 pdata
->gpio_cfg
[i
] & 0xffff);
1806 snd_soc_write(codec
, WM8903_MIC_BIAS_CONTROL_0
,
1809 /* Microphone detection needs the WSEQ clock */
1810 if (pdata
->micdet_cfg
)
1811 snd_soc_update_bits(codec
, WM8903_WRITE_SEQUENCER_0
,
1812 WM8903_WSEQ_ENA
, WM8903_WSEQ_ENA
);
1814 wm8903
->mic_delay
= pdata
->micdet_delay
;
1818 if (pdata
&& pdata
->irq_active_low
) {
1819 trigger
= IRQF_TRIGGER_LOW
;
1820 irq_pol
= WM8903_IRQ_POL
;
1822 trigger
= IRQF_TRIGGER_HIGH
;
1826 snd_soc_update_bits(codec
, WM8903_INTERRUPT_CONTROL
,
1827 WM8903_IRQ_POL
, irq_pol
);
1829 ret
= request_threaded_irq(wm8903
->irq
, NULL
, wm8903_irq
,
1830 trigger
| IRQF_ONESHOT
,
1833 dev_err(codec
->dev
, "Failed to request IRQ: %d\n",
1838 /* Enable write sequencer interrupts */
1839 snd_soc_update_bits(codec
, WM8903_INTERRUPT_STATUS_1_MASK
,
1840 WM8903_IM_WSEQ_BUSY_EINT
, 0);
1843 /* power on device */
1844 wm8903_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1846 /* Latch volume update bits */
1847 val
= snd_soc_read(codec
, WM8903_ADC_DIGITAL_VOLUME_LEFT
);
1848 val
|= WM8903_ADCVU
;
1849 snd_soc_write(codec
, WM8903_ADC_DIGITAL_VOLUME_LEFT
, val
);
1850 snd_soc_write(codec
, WM8903_ADC_DIGITAL_VOLUME_RIGHT
, val
);
1852 val
= snd_soc_read(codec
, WM8903_DAC_DIGITAL_VOLUME_LEFT
);
1853 val
|= WM8903_DACVU
;
1854 snd_soc_write(codec
, WM8903_DAC_DIGITAL_VOLUME_LEFT
, val
);
1855 snd_soc_write(codec
, WM8903_DAC_DIGITAL_VOLUME_RIGHT
, val
);
1857 val
= snd_soc_read(codec
, WM8903_ANALOGUE_OUT1_LEFT
);
1858 val
|= WM8903_HPOUTVU
;
1859 snd_soc_write(codec
, WM8903_ANALOGUE_OUT1_LEFT
, val
);
1860 snd_soc_write(codec
, WM8903_ANALOGUE_OUT1_RIGHT
, val
);
1862 val
= snd_soc_read(codec
, WM8903_ANALOGUE_OUT2_LEFT
);
1863 val
|= WM8903_LINEOUTVU
;
1864 snd_soc_write(codec
, WM8903_ANALOGUE_OUT2_LEFT
, val
);
1865 snd_soc_write(codec
, WM8903_ANALOGUE_OUT2_RIGHT
, val
);
1867 val
= snd_soc_read(codec
, WM8903_ANALOGUE_OUT3_LEFT
);
1868 val
|= WM8903_SPKVU
;
1869 snd_soc_write(codec
, WM8903_ANALOGUE_OUT3_LEFT
, val
);
1870 snd_soc_write(codec
, WM8903_ANALOGUE_OUT3_RIGHT
, val
);
1872 /* Enable DAC soft mute by default */
1873 snd_soc_update_bits(codec
, WM8903_DAC_DIGITAL_1
,
1874 WM8903_DAC_MUTEMODE
| WM8903_DAC_MUTE
,
1875 WM8903_DAC_MUTEMODE
| WM8903_DAC_MUTE
);
1877 snd_soc_add_controls(codec
, wm8903_snd_controls
,
1878 ARRAY_SIZE(wm8903_snd_controls
));
1879 wm8903_add_widgets(codec
);
1881 wm8903_init_gpio(codec
);
1886 /* power down chip */
1887 static int wm8903_remove(struct snd_soc_codec
*codec
)
1889 wm8903_free_gpio(codec
);
1890 wm8903_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1894 static struct snd_soc_codec_driver soc_codec_dev_wm8903
= {
1895 .probe
= wm8903_probe
,
1896 .remove
= wm8903_remove
,
1897 .suspend
= wm8903_suspend
,
1898 .resume
= wm8903_resume
,
1899 .set_bias_level
= wm8903_set_bias_level
,
1900 .reg_cache_size
= ARRAY_SIZE(wm8903_reg_defaults
),
1901 .reg_word_size
= sizeof(u16
),
1902 .reg_cache_default
= wm8903_reg_defaults
,
1903 .volatile_register
= wm8903_volatile_register
,
1906 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1907 static __devinit
int wm8903_i2c_probe(struct i2c_client
*i2c
,
1908 const struct i2c_device_id
*id
)
1910 struct wm8903_priv
*wm8903
;
1913 wm8903
= kzalloc(sizeof(struct wm8903_priv
), GFP_KERNEL
);
1917 i2c_set_clientdata(i2c
, wm8903
);
1918 wm8903
->irq
= i2c
->irq
;
1920 ret
= snd_soc_register_codec(&i2c
->dev
,
1921 &soc_codec_dev_wm8903
, &wm8903_dai
, 1);
1927 static __devexit
int wm8903_i2c_remove(struct i2c_client
*client
)
1929 snd_soc_unregister_codec(&client
->dev
);
1930 kfree(i2c_get_clientdata(client
));
1934 static const struct i2c_device_id wm8903_i2c_id
[] = {
1938 MODULE_DEVICE_TABLE(i2c
, wm8903_i2c_id
);
1940 static struct i2c_driver wm8903_i2c_driver
= {
1943 .owner
= THIS_MODULE
,
1945 .probe
= wm8903_i2c_probe
,
1946 .remove
= __devexit_p(wm8903_i2c_remove
),
1947 .id_table
= wm8903_i2c_id
,
1951 static int __init
wm8903_modinit(void)
1954 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1955 ret
= i2c_add_driver(&wm8903_i2c_driver
);
1957 printk(KERN_ERR
"Failed to register wm8903 I2C driver: %d\n",
1963 module_init(wm8903_modinit
);
1965 static void __exit
wm8903_exit(void)
1967 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1968 i2c_del_driver(&wm8903_i2c_driver
);
1971 module_exit(wm8903_exit
);
1973 MODULE_DESCRIPTION("ASoC WM8903 driver");
1974 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
1975 MODULE_LICENSE("GPL");