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ASoC: Optimise WM8904 output stage power control
[deliverable/linux.git] / sound / soc / codecs / wm8904.c
1 /*
2 * wm8904.c -- WM8904 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/regulator/consumer.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29 #include <sound/wm8904.h>
30
31 #include "wm8904.h"
32
33 static struct snd_soc_codec *wm8904_codec;
34 struct snd_soc_codec_device soc_codec_dev_wm8904;
35
36 #define WM8904_NUM_DCS_CHANNELS 4
37
38 #define WM8904_NUM_SUPPLIES 5
39 static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = {
40 "DCVDD",
41 "DBVDD",
42 "AVDD",
43 "CPVDD",
44 "MICVDD",
45 };
46
47 /* codec private data */
48 struct wm8904_priv {
49 struct snd_soc_codec codec;
50 u16 reg_cache[WM8904_MAX_REGISTER + 1];
51
52 struct regulator_bulk_data supplies[WM8904_NUM_SUPPLIES];
53
54 struct wm8904_pdata *pdata;
55
56 int deemph;
57
58 /* Platform provided DRC configuration */
59 const char **drc_texts;
60 int drc_cfg;
61 struct soc_enum drc_enum;
62
63 /* Platform provided ReTune mobile configuration */
64 int num_retune_mobile_texts;
65 const char **retune_mobile_texts;
66 int retune_mobile_cfg;
67 struct soc_enum retune_mobile_enum;
68
69 /* FLL setup */
70 int fll_src;
71 int fll_fref;
72 int fll_fout;
73
74 /* Clocking configuration */
75 unsigned int mclk_rate;
76 int sysclk_src;
77 unsigned int sysclk_rate;
78
79 int tdm_width;
80 int tdm_slots;
81 int bclk;
82 int fs;
83
84 /* DC servo configuration - cached offset values */
85 int dcs_state[WM8904_NUM_DCS_CHANNELS];
86 };
87
88 static const u16 wm8904_reg[WM8904_MAX_REGISTER + 1] = {
89 0x8904, /* R0 - SW Reset and ID */
90 0x0000, /* R1 - Revision */
91 0x0000, /* R2 */
92 0x0000, /* R3 */
93 0x0018, /* R4 - Bias Control 0 */
94 0x0000, /* R5 - VMID Control 0 */
95 0x0000, /* R6 - Mic Bias Control 0 */
96 0x0000, /* R7 - Mic Bias Control 1 */
97 0x0001, /* R8 - Analogue DAC 0 */
98 0x9696, /* R9 - mic Filter Control */
99 0x0001, /* R10 - Analogue ADC 0 */
100 0x0000, /* R11 */
101 0x0000, /* R12 - Power Management 0 */
102 0x0000, /* R13 */
103 0x0000, /* R14 - Power Management 2 */
104 0x0000, /* R15 - Power Management 3 */
105 0x0000, /* R16 */
106 0x0000, /* R17 */
107 0x0000, /* R18 - Power Management 6 */
108 0x0000, /* R19 */
109 0x945E, /* R20 - Clock Rates 0 */
110 0x0C05, /* R21 - Clock Rates 1 */
111 0x0006, /* R22 - Clock Rates 2 */
112 0x0000, /* R23 */
113 0x0050, /* R24 - Audio Interface 0 */
114 0x000A, /* R25 - Audio Interface 1 */
115 0x00E4, /* R26 - Audio Interface 2 */
116 0x0040, /* R27 - Audio Interface 3 */
117 0x0000, /* R28 */
118 0x0000, /* R29 */
119 0x00C0, /* R30 - DAC Digital Volume Left */
120 0x00C0, /* R31 - DAC Digital Volume Right */
121 0x0000, /* R32 - DAC Digital 0 */
122 0x0008, /* R33 - DAC Digital 1 */
123 0x0000, /* R34 */
124 0x0000, /* R35 */
125 0x00C0, /* R36 - ADC Digital Volume Left */
126 0x00C0, /* R37 - ADC Digital Volume Right */
127 0x0010, /* R38 - ADC Digital 0 */
128 0x0000, /* R39 - Digital Microphone 0 */
129 0x01AF, /* R40 - DRC 0 */
130 0x3248, /* R41 - DRC 1 */
131 0x0000, /* R42 - DRC 2 */
132 0x0000, /* R43 - DRC 3 */
133 0x0085, /* R44 - Analogue Left Input 0 */
134 0x0085, /* R45 - Analogue Right Input 0 */
135 0x0044, /* R46 - Analogue Left Input 1 */
136 0x0044, /* R47 - Analogue Right Input 1 */
137 0x0000, /* R48 */
138 0x0000, /* R49 */
139 0x0000, /* R50 */
140 0x0000, /* R51 */
141 0x0000, /* R52 */
142 0x0000, /* R53 */
143 0x0000, /* R54 */
144 0x0000, /* R55 */
145 0x0000, /* R56 */
146 0x002D, /* R57 - Analogue OUT1 Left */
147 0x002D, /* R58 - Analogue OUT1 Right */
148 0x0039, /* R59 - Analogue OUT2 Left */
149 0x0039, /* R60 - Analogue OUT2 Right */
150 0x0000, /* R61 - Analogue OUT12 ZC */
151 0x0000, /* R62 */
152 0x0000, /* R63 */
153 0x0000, /* R64 */
154 0x0000, /* R65 */
155 0x0000, /* R66 */
156 0x0000, /* R67 - DC Servo 0 */
157 0x0000, /* R68 - DC Servo 1 */
158 0xAAAA, /* R69 - DC Servo 2 */
159 0x0000, /* R70 */
160 0xAAAA, /* R71 - DC Servo 4 */
161 0xAAAA, /* R72 - DC Servo 5 */
162 0x0000, /* R73 - DC Servo 6 */
163 0x0000, /* R74 - DC Servo 7 */
164 0x0000, /* R75 - DC Servo 8 */
165 0x0000, /* R76 - DC Servo 9 */
166 0x0000, /* R77 - DC Servo Readback 0 */
167 0x0000, /* R78 */
168 0x0000, /* R79 */
169 0x0000, /* R80 */
170 0x0000, /* R81 */
171 0x0000, /* R82 */
172 0x0000, /* R83 */
173 0x0000, /* R84 */
174 0x0000, /* R85 */
175 0x0000, /* R86 */
176 0x0000, /* R87 */
177 0x0000, /* R88 */
178 0x0000, /* R89 */
179 0x0000, /* R90 - Analogue HP 0 */
180 0x0000, /* R91 */
181 0x0000, /* R92 */
182 0x0000, /* R93 */
183 0x0000, /* R94 - Analogue Lineout 0 */
184 0x0000, /* R95 */
185 0x0000, /* R96 */
186 0x0000, /* R97 */
187 0x0000, /* R98 - Charge Pump 0 */
188 0x0000, /* R99 */
189 0x0000, /* R100 */
190 0x0000, /* R101 */
191 0x0000, /* R102 */
192 0x0000, /* R103 */
193 0x0004, /* R104 - Class W 0 */
194 0x0000, /* R105 */
195 0x0000, /* R106 */
196 0x0000, /* R107 */
197 0x0000, /* R108 - Write Sequencer 0 */
198 0x0000, /* R109 - Write Sequencer 1 */
199 0x0000, /* R110 - Write Sequencer 2 */
200 0x0000, /* R111 - Write Sequencer 3 */
201 0x0000, /* R112 - Write Sequencer 4 */
202 0x0000, /* R113 */
203 0x0000, /* R114 */
204 0x0000, /* R115 */
205 0x0000, /* R116 - FLL Control 1 */
206 0x0007, /* R117 - FLL Control 2 */
207 0x0000, /* R118 - FLL Control 3 */
208 0x2EE0, /* R119 - FLL Control 4 */
209 0x0004, /* R120 - FLL Control 5 */
210 0x0014, /* R121 - GPIO Control 1 */
211 0x0010, /* R122 - GPIO Control 2 */
212 0x0010, /* R123 - GPIO Control 3 */
213 0x0000, /* R124 - GPIO Control 4 */
214 0x0000, /* R125 */
215 0x0000, /* R126 - Digital Pulls */
216 0x0000, /* R127 - Interrupt Status */
217 0xFFFF, /* R128 - Interrupt Status Mask */
218 0x0000, /* R129 - Interrupt Polarity */
219 0x0000, /* R130 - Interrupt Debounce */
220 0x0000, /* R131 */
221 0x0000, /* R132 */
222 0x0000, /* R133 */
223 0x0000, /* R134 - EQ1 */
224 0x000C, /* R135 - EQ2 */
225 0x000C, /* R136 - EQ3 */
226 0x000C, /* R137 - EQ4 */
227 0x000C, /* R138 - EQ5 */
228 0x000C, /* R139 - EQ6 */
229 0x0FCA, /* R140 - EQ7 */
230 0x0400, /* R141 - EQ8 */
231 0x00D8, /* R142 - EQ9 */
232 0x1EB5, /* R143 - EQ10 */
233 0xF145, /* R144 - EQ11 */
234 0x0B75, /* R145 - EQ12 */
235 0x01C5, /* R146 - EQ13 */
236 0x1C58, /* R147 - EQ14 */
237 0xF373, /* R148 - EQ15 */
238 0x0A54, /* R149 - EQ16 */
239 0x0558, /* R150 - EQ17 */
240 0x168E, /* R151 - EQ18 */
241 0xF829, /* R152 - EQ19 */
242 0x07AD, /* R153 - EQ20 */
243 0x1103, /* R154 - EQ21 */
244 0x0564, /* R155 - EQ22 */
245 0x0559, /* R156 - EQ23 */
246 0x4000, /* R157 - EQ24 */
247 0x0000, /* R158 */
248 0x0000, /* R159 */
249 0x0000, /* R160 */
250 0x0000, /* R161 - Control Interface Test 1 */
251 0x0000, /* R162 */
252 0x0000, /* R163 */
253 0x0000, /* R164 */
254 0x0000, /* R165 */
255 0x0000, /* R166 */
256 0x0000, /* R167 */
257 0x0000, /* R168 */
258 0x0000, /* R169 */
259 0x0000, /* R170 */
260 0x0000, /* R171 */
261 0x0000, /* R172 */
262 0x0000, /* R173 */
263 0x0000, /* R174 */
264 0x0000, /* R175 */
265 0x0000, /* R176 */
266 0x0000, /* R177 */
267 0x0000, /* R178 */
268 0x0000, /* R179 */
269 0x0000, /* R180 */
270 0x0000, /* R181 */
271 0x0000, /* R182 */
272 0x0000, /* R183 */
273 0x0000, /* R184 */
274 0x0000, /* R185 */
275 0x0000, /* R186 */
276 0x0000, /* R187 */
277 0x0000, /* R188 */
278 0x0000, /* R189 */
279 0x0000, /* R190 */
280 0x0000, /* R191 */
281 0x0000, /* R192 */
282 0x0000, /* R193 */
283 0x0000, /* R194 */
284 0x0000, /* R195 */
285 0x0000, /* R196 */
286 0x0000, /* R197 */
287 0x0000, /* R198 */
288 0x0000, /* R199 */
289 0x0000, /* R200 */
290 0x0000, /* R201 */
291 0x0000, /* R202 */
292 0x0000, /* R203 */
293 0x0000, /* R204 - Analogue Output Bias 0 */
294 0x0000, /* R205 */
295 0x0000, /* R206 */
296 0x0000, /* R207 */
297 0x0000, /* R208 */
298 0x0000, /* R209 */
299 0x0000, /* R210 */
300 0x0000, /* R211 */
301 0x0000, /* R212 */
302 0x0000, /* R213 */
303 0x0000, /* R214 */
304 0x0000, /* R215 */
305 0x0000, /* R216 */
306 0x0000, /* R217 */
307 0x0000, /* R218 */
308 0x0000, /* R219 */
309 0x0000, /* R220 */
310 0x0000, /* R221 */
311 0x0000, /* R222 */
312 0x0000, /* R223 */
313 0x0000, /* R224 */
314 0x0000, /* R225 */
315 0x0000, /* R226 */
316 0x0000, /* R227 */
317 0x0000, /* R228 */
318 0x0000, /* R229 */
319 0x0000, /* R230 */
320 0x0000, /* R231 */
321 0x0000, /* R232 */
322 0x0000, /* R233 */
323 0x0000, /* R234 */
324 0x0000, /* R235 */
325 0x0000, /* R236 */
326 0x0000, /* R237 */
327 0x0000, /* R238 */
328 0x0000, /* R239 */
329 0x0000, /* R240 */
330 0x0000, /* R241 */
331 0x0000, /* R242 */
332 0x0000, /* R243 */
333 0x0000, /* R244 */
334 0x0000, /* R245 */
335 0x0000, /* R246 */
336 0x0000, /* R247 - FLL NCO Test 0 */
337 0x0019, /* R248 - FLL NCO Test 1 */
338 };
339
340 static struct {
341 int readable;
342 int writable;
343 int vol;
344 } wm8904_access[] = {
345 { 0xFFFF, 0xFFFF, 1 }, /* R0 - SW Reset and ID */
346 { 0x0000, 0x0000, 0 }, /* R1 - Revision */
347 { 0x0000, 0x0000, 0 }, /* R2 */
348 { 0x0000, 0x0000, 0 }, /* R3 */
349 { 0x001F, 0x001F, 0 }, /* R4 - Bias Control 0 */
350 { 0x0047, 0x0047, 0 }, /* R5 - VMID Control 0 */
351 { 0x007F, 0x007F, 0 }, /* R6 - Mic Bias Control 0 */
352 { 0xC007, 0xC007, 0 }, /* R7 - Mic Bias Control 1 */
353 { 0x001E, 0x001E, 0 }, /* R8 - Analogue DAC 0 */
354 { 0xFFFF, 0xFFFF, 0 }, /* R9 - mic Filter Control */
355 { 0x0001, 0x0001, 0 }, /* R10 - Analogue ADC 0 */
356 { 0x0000, 0x0000, 0 }, /* R11 */
357 { 0x0003, 0x0003, 0 }, /* R12 - Power Management 0 */
358 { 0x0000, 0x0000, 0 }, /* R13 */
359 { 0x0003, 0x0003, 0 }, /* R14 - Power Management 2 */
360 { 0x0003, 0x0003, 0 }, /* R15 - Power Management 3 */
361 { 0x0000, 0x0000, 0 }, /* R16 */
362 { 0x0000, 0x0000, 0 }, /* R17 */
363 { 0x000F, 0x000F, 0 }, /* R18 - Power Management 6 */
364 { 0x0000, 0x0000, 0 }, /* R19 */
365 { 0x7001, 0x7001, 0 }, /* R20 - Clock Rates 0 */
366 { 0x3C07, 0x3C07, 0 }, /* R21 - Clock Rates 1 */
367 { 0xD00F, 0xD00F, 0 }, /* R22 - Clock Rates 2 */
368 { 0x0000, 0x0000, 0 }, /* R23 */
369 { 0x1FFF, 0x1FFF, 0 }, /* R24 - Audio Interface 0 */
370 { 0x3DDF, 0x3DDF, 0 }, /* R25 - Audio Interface 1 */
371 { 0x0F1F, 0x0F1F, 0 }, /* R26 - Audio Interface 2 */
372 { 0x0FFF, 0x0FFF, 0 }, /* R27 - Audio Interface 3 */
373 { 0x0000, 0x0000, 0 }, /* R28 */
374 { 0x0000, 0x0000, 0 }, /* R29 */
375 { 0x00FF, 0x01FF, 0 }, /* R30 - DAC Digital Volume Left */
376 { 0x00FF, 0x01FF, 0 }, /* R31 - DAC Digital Volume Right */
377 { 0x0FFF, 0x0FFF, 0 }, /* R32 - DAC Digital 0 */
378 { 0x1E4E, 0x1E4E, 0 }, /* R33 - DAC Digital 1 */
379 { 0x0000, 0x0000, 0 }, /* R34 */
380 { 0x0000, 0x0000, 0 }, /* R35 */
381 { 0x00FF, 0x01FF, 0 }, /* R36 - ADC Digital Volume Left */
382 { 0x00FF, 0x01FF, 0 }, /* R37 - ADC Digital Volume Right */
383 { 0x0073, 0x0073, 0 }, /* R38 - ADC Digital 0 */
384 { 0x1800, 0x1800, 0 }, /* R39 - Digital Microphone 0 */
385 { 0xDFEF, 0xDFEF, 0 }, /* R40 - DRC 0 */
386 { 0xFFFF, 0xFFFF, 0 }, /* R41 - DRC 1 */
387 { 0x003F, 0x003F, 0 }, /* R42 - DRC 2 */
388 { 0x07FF, 0x07FF, 0 }, /* R43 - DRC 3 */
389 { 0x009F, 0x009F, 0 }, /* R44 - Analogue Left Input 0 */
390 { 0x009F, 0x009F, 0 }, /* R45 - Analogue Right Input 0 */
391 { 0x007F, 0x007F, 0 }, /* R46 - Analogue Left Input 1 */
392 { 0x007F, 0x007F, 0 }, /* R47 - Analogue Right Input 1 */
393 { 0x0000, 0x0000, 0 }, /* R48 */
394 { 0x0000, 0x0000, 0 }, /* R49 */
395 { 0x0000, 0x0000, 0 }, /* R50 */
396 { 0x0000, 0x0000, 0 }, /* R51 */
397 { 0x0000, 0x0000, 0 }, /* R52 */
398 { 0x0000, 0x0000, 0 }, /* R53 */
399 { 0x0000, 0x0000, 0 }, /* R54 */
400 { 0x0000, 0x0000, 0 }, /* R55 */
401 { 0x0000, 0x0000, 0 }, /* R56 */
402 { 0x017F, 0x01FF, 0 }, /* R57 - Analogue OUT1 Left */
403 { 0x017F, 0x01FF, 0 }, /* R58 - Analogue OUT1 Right */
404 { 0x017F, 0x01FF, 0 }, /* R59 - Analogue OUT2 Left */
405 { 0x017F, 0x01FF, 0 }, /* R60 - Analogue OUT2 Right */
406 { 0x000F, 0x000F, 0 }, /* R61 - Analogue OUT12 ZC */
407 { 0x0000, 0x0000, 0 }, /* R62 */
408 { 0x0000, 0x0000, 0 }, /* R63 */
409 { 0x0000, 0x0000, 0 }, /* R64 */
410 { 0x0000, 0x0000, 0 }, /* R65 */
411 { 0x0000, 0x0000, 0 }, /* R66 */
412 { 0x000F, 0x000F, 0 }, /* R67 - DC Servo 0 */
413 { 0xFFFF, 0xFFFF, 1 }, /* R68 - DC Servo 1 */
414 { 0x0F0F, 0x0F0F, 0 }, /* R69 - DC Servo 2 */
415 { 0x0000, 0x0000, 0 }, /* R70 */
416 { 0x007F, 0x007F, 0 }, /* R71 - DC Servo 4 */
417 { 0x007F, 0x007F, 0 }, /* R72 - DC Servo 5 */
418 { 0x00FF, 0x00FF, 1 }, /* R73 - DC Servo 6 */
419 { 0x00FF, 0x00FF, 1 }, /* R74 - DC Servo 7 */
420 { 0x00FF, 0x00FF, 1 }, /* R75 - DC Servo 8 */
421 { 0x00FF, 0x00FF, 1 }, /* R76 - DC Servo 9 */
422 { 0x0FFF, 0x0000, 1 }, /* R77 - DC Servo Readback 0 */
423 { 0x0000, 0x0000, 0 }, /* R78 */
424 { 0x0000, 0x0000, 0 }, /* R79 */
425 { 0x0000, 0x0000, 0 }, /* R80 */
426 { 0x0000, 0x0000, 0 }, /* R81 */
427 { 0x0000, 0x0000, 0 }, /* R82 */
428 { 0x0000, 0x0000, 0 }, /* R83 */
429 { 0x0000, 0x0000, 0 }, /* R84 */
430 { 0x0000, 0x0000, 0 }, /* R85 */
431 { 0x0000, 0x0000, 0 }, /* R86 */
432 { 0x0000, 0x0000, 0 }, /* R87 */
433 { 0x0000, 0x0000, 0 }, /* R88 */
434 { 0x0000, 0x0000, 0 }, /* R89 */
435 { 0x00FF, 0x00FF, 0 }, /* R90 - Analogue HP 0 */
436 { 0x0000, 0x0000, 0 }, /* R91 */
437 { 0x0000, 0x0000, 0 }, /* R92 */
438 { 0x0000, 0x0000, 0 }, /* R93 */
439 { 0x00FF, 0x00FF, 0 }, /* R94 - Analogue Lineout 0 */
440 { 0x0000, 0x0000, 0 }, /* R95 */
441 { 0x0000, 0x0000, 0 }, /* R96 */
442 { 0x0000, 0x0000, 0 }, /* R97 */
443 { 0x0001, 0x0001, 0 }, /* R98 - Charge Pump 0 */
444 { 0x0000, 0x0000, 0 }, /* R99 */
445 { 0x0000, 0x0000, 0 }, /* R100 */
446 { 0x0000, 0x0000, 0 }, /* R101 */
447 { 0x0000, 0x0000, 0 }, /* R102 */
448 { 0x0000, 0x0000, 0 }, /* R103 */
449 { 0x0001, 0x0001, 0 }, /* R104 - Class W 0 */
450 { 0x0000, 0x0000, 0 }, /* R105 */
451 { 0x0000, 0x0000, 0 }, /* R106 */
452 { 0x0000, 0x0000, 0 }, /* R107 */
453 { 0x011F, 0x011F, 0 }, /* R108 - Write Sequencer 0 */
454 { 0x7FFF, 0x7FFF, 0 }, /* R109 - Write Sequencer 1 */
455 { 0x4FFF, 0x4FFF, 0 }, /* R110 - Write Sequencer 2 */
456 { 0x003F, 0x033F, 0 }, /* R111 - Write Sequencer 3 */
457 { 0x03F1, 0x0000, 0 }, /* R112 - Write Sequencer 4 */
458 { 0x0000, 0x0000, 0 }, /* R113 */
459 { 0x0000, 0x0000, 0 }, /* R114 */
460 { 0x0000, 0x0000, 0 }, /* R115 */
461 { 0x0007, 0x0007, 0 }, /* R116 - FLL Control 1 */
462 { 0x3F77, 0x3F77, 0 }, /* R117 - FLL Control 2 */
463 { 0xFFFF, 0xFFFF, 0 }, /* R118 - FLL Control 3 */
464 { 0x7FEF, 0x7FEF, 0 }, /* R119 - FLL Control 4 */
465 { 0x001B, 0x001B, 0 }, /* R120 - FLL Control 5 */
466 { 0x003F, 0x003F, 0 }, /* R121 - GPIO Control 1 */
467 { 0x003F, 0x003F, 0 }, /* R122 - GPIO Control 2 */
468 { 0x003F, 0x003F, 0 }, /* R123 - GPIO Control 3 */
469 { 0x038F, 0x038F, 0 }, /* R124 - GPIO Control 4 */
470 { 0x0000, 0x0000, 0 }, /* R125 */
471 { 0x00FF, 0x00FF, 0 }, /* R126 - Digital Pulls */
472 { 0x07FF, 0x03FF, 1 }, /* R127 - Interrupt Status */
473 { 0x03FF, 0x03FF, 0 }, /* R128 - Interrupt Status Mask */
474 { 0x03FF, 0x03FF, 0 }, /* R129 - Interrupt Polarity */
475 { 0x03FF, 0x03FF, 0 }, /* R130 - Interrupt Debounce */
476 { 0x0000, 0x0000, 0 }, /* R131 */
477 { 0x0000, 0x0000, 0 }, /* R132 */
478 { 0x0000, 0x0000, 0 }, /* R133 */
479 { 0x0001, 0x0001, 0 }, /* R134 - EQ1 */
480 { 0x001F, 0x001F, 0 }, /* R135 - EQ2 */
481 { 0x001F, 0x001F, 0 }, /* R136 - EQ3 */
482 { 0x001F, 0x001F, 0 }, /* R137 - EQ4 */
483 { 0x001F, 0x001F, 0 }, /* R138 - EQ5 */
484 { 0x001F, 0x001F, 0 }, /* R139 - EQ6 */
485 { 0xFFFF, 0xFFFF, 0 }, /* R140 - EQ7 */
486 { 0xFFFF, 0xFFFF, 0 }, /* R141 - EQ8 */
487 { 0xFFFF, 0xFFFF, 0 }, /* R142 - EQ9 */
488 { 0xFFFF, 0xFFFF, 0 }, /* R143 - EQ10 */
489 { 0xFFFF, 0xFFFF, 0 }, /* R144 - EQ11 */
490 { 0xFFFF, 0xFFFF, 0 }, /* R145 - EQ12 */
491 { 0xFFFF, 0xFFFF, 0 }, /* R146 - EQ13 */
492 { 0xFFFF, 0xFFFF, 0 }, /* R147 - EQ14 */
493 { 0xFFFF, 0xFFFF, 0 }, /* R148 - EQ15 */
494 { 0xFFFF, 0xFFFF, 0 }, /* R149 - EQ16 */
495 { 0xFFFF, 0xFFFF, 0 }, /* R150 - EQ17 */
496 { 0xFFFF, 0xFFFF, 0 }, /* R151wm8523_dai - EQ18 */
497 { 0xFFFF, 0xFFFF, 0 }, /* R152 - EQ19 */
498 { 0xFFFF, 0xFFFF, 0 }, /* R153 - EQ20 */
499 { 0xFFFF, 0xFFFF, 0 }, /* R154 - EQ21 */
500 { 0xFFFF, 0xFFFF, 0 }, /* R155 - EQ22 */
501 { 0xFFFF, 0xFFFF, 0 }, /* R156 - EQ23 */
502 { 0xFFFF, 0xFFFF, 0 }, /* R157 - EQ24 */
503 { 0x0000, 0x0000, 0 }, /* R158 */
504 { 0x0000, 0x0000, 0 }, /* R159 */
505 { 0x0000, 0x0000, 0 }, /* R160 */
506 { 0x0002, 0x0002, 0 }, /* R161 - Control Interface Test 1 */
507 { 0x0000, 0x0000, 0 }, /* R162 */
508 { 0x0000, 0x0000, 0 }, /* R163 */
509 { 0x0000, 0x0000, 0 }, /* R164 */
510 { 0x0000, 0x0000, 0 }, /* R165 */
511 { 0x0000, 0x0000, 0 }, /* R166 */
512 { 0x0000, 0x0000, 0 }, /* R167 */
513 { 0x0000, 0x0000, 0 }, /* R168 */
514 { 0x0000, 0x0000, 0 }, /* R169 */
515 { 0x0000, 0x0000, 0 }, /* R170 */
516 { 0x0000, 0x0000, 0 }, /* R171 */
517 { 0x0000, 0x0000, 0 }, /* R172 */
518 { 0x0000, 0x0000, 0 }, /* R173 */
519 { 0x0000, 0x0000, 0 }, /* R174 */
520 { 0x0000, 0x0000, 0 }, /* R175 */
521 { 0x0000, 0x0000, 0 }, /* R176 */
522 { 0x0000, 0x0000, 0 }, /* R177 */
523 { 0x0000, 0x0000, 0 }, /* R178 */
524 { 0x0000, 0x0000, 0 }, /* R179 */
525 { 0x0000, 0x0000, 0 }, /* R180 */
526 { 0x0000, 0x0000, 0 }, /* R181 */
527 { 0x0000, 0x0000, 0 }, /* R182 */
528 { 0x0000, 0x0000, 0 }, /* R183 */
529 { 0x0000, 0x0000, 0 }, /* R184 */
530 { 0x0000, 0x0000, 0 }, /* R185 */
531 { 0x0000, 0x0000, 0 }, /* R186 */
532 { 0x0000, 0x0000, 0 }, /* R187 */
533 { 0x0000, 0x0000, 0 }, /* R188 */
534 { 0x0000, 0x0000, 0 }, /* R189 */
535 { 0x0000, 0x0000, 0 }, /* R190 */
536 { 0x0000, 0x0000, 0 }, /* R191 */
537 { 0x0000, 0x0000, 0 }, /* R192 */
538 { 0x0000, 0x0000, 0 }, /* R193 */
539 { 0x0000, 0x0000, 0 }, /* R194 */
540 { 0x0000, 0x0000, 0 }, /* R195 */
541 { 0x0000, 0x0000, 0 }, /* R196 */
542 { 0x0000, 0x0000, 0 }, /* R197 */
543 { 0x0000, 0x0000, 0 }, /* R198 */
544 { 0x0000, 0x0000, 0 }, /* R199 */
545 { 0x0000, 0x0000, 0 }, /* R200 */
546 { 0x0000, 0x0000, 0 }, /* R201 */
547 { 0x0000, 0x0000, 0 }, /* R202 */
548 { 0x0000, 0x0000, 0 }, /* R203 */
549 { 0x0070, 0x0070, 0 }, /* R204 - Analogue Output Bias 0 */
550 { 0x0000, 0x0000, 0 }, /* R205 */
551 { 0x0000, 0x0000, 0 }, /* R206 */
552 { 0x0000, 0x0000, 0 }, /* R207 */
553 { 0x0000, 0x0000, 0 }, /* R208 */
554 { 0x0000, 0x0000, 0 }, /* R209 */
555 { 0x0000, 0x0000, 0 }, /* R210 */
556 { 0x0000, 0x0000, 0 }, /* R211 */
557 { 0x0000, 0x0000, 0 }, /* R212 */
558 { 0x0000, 0x0000, 0 }, /* R213 */
559 { 0x0000, 0x0000, 0 }, /* R214 */
560 { 0x0000, 0x0000, 0 }, /* R215 */
561 { 0x0000, 0x0000, 0 }, /* R216 */
562 { 0x0000, 0x0000, 0 }, /* R217 */
563 { 0x0000, 0x0000, 0 }, /* R218 */
564 { 0x0000, 0x0000, 0 }, /* R219 */
565 { 0x0000, 0x0000, 0 }, /* R220 */
566 { 0x0000, 0x0000, 0 }, /* R221 */
567 { 0x0000, 0x0000, 0 }, /* R222 */
568 { 0x0000, 0x0000, 0 }, /* R223 */
569 { 0x0000, 0x0000, 0 }, /* R224 */
570 { 0x0000, 0x0000, 0 }, /* R225 */
571 { 0x0000, 0x0000, 0 }, /* R226 */
572 { 0x0000, 0x0000, 0 }, /* R227 */
573 { 0x0000, 0x0000, 0 }, /* R228 */
574 { 0x0000, 0x0000, 0 }, /* R229 */
575 { 0x0000, 0x0000, 0 }, /* R230 */
576 { 0x0000, 0x0000, 0 }, /* R231 */
577 { 0x0000, 0x0000, 0 }, /* R232 */
578 { 0x0000, 0x0000, 0 }, /* R233 */
579 { 0x0000, 0x0000, 0 }, /* R234 */
580 { 0x0000, 0x0000, 0 }, /* R235 */
581 { 0x0000, 0x0000, 0 }, /* R236 */
582 { 0x0000, 0x0000, 0 }, /* R237 */
583 { 0x0000, 0x0000, 0 }, /* R238 */
584 { 0x0000, 0x0000, 0 }, /* R239 */
585 { 0x0000, 0x0000, 0 }, /* R240 */
586 { 0x0000, 0x0000, 0 }, /* R241 */
587 { 0x0000, 0x0000, 0 }, /* R242 */
588 { 0x0000, 0x0000, 0 }, /* R243 */
589 { 0x0000, 0x0000, 0 }, /* R244 */
590 { 0x0000, 0x0000, 0 }, /* R245 */
591 { 0x0000, 0x0000, 0 }, /* R246 */
592 { 0x0001, 0x0001, 0 }, /* R247 - FLL NCO Test 0 */
593 { 0x003F, 0x003F, 0 }, /* R248 - FLL NCO Test 1 */
594 };
595
596 static int wm8904_volatile_register(unsigned int reg)
597 {
598 return wm8904_access[reg].vol;
599 }
600
601 static int wm8904_reset(struct snd_soc_codec *codec)
602 {
603 return snd_soc_write(codec, WM8904_SW_RESET_AND_ID, 0);
604 }
605
606 static int wm8904_configure_clocking(struct snd_soc_codec *codec)
607 {
608 struct wm8904_priv *wm8904 = codec->private_data;
609 unsigned int clock0, clock2, rate;
610
611 /* Gate the clock while we're updating to avoid misclocking */
612 clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2);
613 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
614 WM8904_SYSCLK_SRC, 0);
615
616 /* This should be done on init() for bypass paths */
617 switch (wm8904->sysclk_src) {
618 case WM8904_CLK_MCLK:
619 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8904->mclk_rate);
620
621 clock2 &= ~WM8904_SYSCLK_SRC;
622 rate = wm8904->mclk_rate;
623
624 /* Ensure the FLL is stopped */
625 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
626 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
627 break;
628
629 case WM8904_CLK_FLL:
630 dev_dbg(codec->dev, "Using %dHz FLL clock\n",
631 wm8904->fll_fout);
632
633 clock2 |= WM8904_SYSCLK_SRC;
634 rate = wm8904->fll_fout;
635 break;
636
637 default:
638 dev_err(codec->dev, "System clock not configured\n");
639 return -EINVAL;
640 }
641
642 /* SYSCLK shouldn't be over 13.5MHz */
643 if (rate > 13500000) {
644 clock0 = WM8904_MCLK_DIV;
645 wm8904->sysclk_rate = rate / 2;
646 } else {
647 clock0 = 0;
648 wm8904->sysclk_rate = rate;
649 }
650
651 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_0, WM8904_MCLK_DIV,
652 clock0);
653
654 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
655 WM8904_CLK_SYS_ENA | WM8904_SYSCLK_SRC, clock2);
656
657 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8904->sysclk_rate);
658
659 return 0;
660 }
661
662 static void wm8904_set_drc(struct snd_soc_codec *codec)
663 {
664 struct wm8904_priv *wm8904 = codec->private_data;
665 struct wm8904_pdata *pdata = wm8904->pdata;
666 int save, i;
667
668 /* Save any enables; the configuration should clear them. */
669 save = snd_soc_read(codec, WM8904_DRC_0);
670
671 for (i = 0; i < WM8904_DRC_REGS; i++)
672 snd_soc_update_bits(codec, WM8904_DRC_0 + i, 0xffff,
673 pdata->drc_cfgs[wm8904->drc_cfg].regs[i]);
674
675 /* Reenable the DRC */
676 snd_soc_update_bits(codec, WM8904_DRC_0,
677 WM8904_DRC_ENA | WM8904_DRC_DAC_PATH, save);
678 }
679
680 static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol,
681 struct snd_ctl_elem_value *ucontrol)
682 {
683 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
684 struct wm8904_priv *wm8904 = codec->private_data;
685 struct wm8904_pdata *pdata = wm8904->pdata;
686 int value = ucontrol->value.integer.value[0];
687
688 if (value >= pdata->num_drc_cfgs)
689 return -EINVAL;
690
691 wm8904->drc_cfg = value;
692
693 wm8904_set_drc(codec);
694
695 return 0;
696 }
697
698 static int wm8904_get_drc_enum(struct snd_kcontrol *kcontrol,
699 struct snd_ctl_elem_value *ucontrol)
700 {
701 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
702 struct wm8904_priv *wm8904 = codec->private_data;
703
704 ucontrol->value.enumerated.item[0] = wm8904->drc_cfg;
705
706 return 0;
707 }
708
709 static void wm8904_set_retune_mobile(struct snd_soc_codec *codec)
710 {
711 struct wm8904_priv *wm8904 = codec->private_data;
712 struct wm8904_pdata *pdata = wm8904->pdata;
713 int best, best_val, save, i, cfg;
714
715 if (!pdata || !wm8904->num_retune_mobile_texts)
716 return;
717
718 /* Find the version of the currently selected configuration
719 * with the nearest sample rate. */
720 cfg = wm8904->retune_mobile_cfg;
721 best = 0;
722 best_val = INT_MAX;
723 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
724 if (strcmp(pdata->retune_mobile_cfgs[i].name,
725 wm8904->retune_mobile_texts[cfg]) == 0 &&
726 abs(pdata->retune_mobile_cfgs[i].rate
727 - wm8904->fs) < best_val) {
728 best = i;
729 best_val = abs(pdata->retune_mobile_cfgs[i].rate
730 - wm8904->fs);
731 }
732 }
733
734 dev_dbg(codec->dev, "ReTune Mobile %s/%dHz for %dHz sample rate\n",
735 pdata->retune_mobile_cfgs[best].name,
736 pdata->retune_mobile_cfgs[best].rate,
737 wm8904->fs);
738
739 /* The EQ will be disabled while reconfiguring it, remember the
740 * current configuration.
741 */
742 save = snd_soc_read(codec, WM8904_EQ1);
743
744 for (i = 0; i < WM8904_EQ_REGS; i++)
745 snd_soc_update_bits(codec, WM8904_EQ1 + i, 0xffff,
746 pdata->retune_mobile_cfgs[best].regs[i]);
747
748 snd_soc_update_bits(codec, WM8904_EQ1, WM8904_EQ_ENA, save);
749 }
750
751 static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
752 struct snd_ctl_elem_value *ucontrol)
753 {
754 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
755 struct wm8904_priv *wm8904 = codec->private_data;
756 struct wm8904_pdata *pdata = wm8904->pdata;
757 int value = ucontrol->value.integer.value[0];
758
759 if (value >= pdata->num_retune_mobile_cfgs)
760 return -EINVAL;
761
762 wm8904->retune_mobile_cfg = value;
763
764 wm8904_set_retune_mobile(codec);
765
766 return 0;
767 }
768
769 static int wm8904_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
770 struct snd_ctl_elem_value *ucontrol)
771 {
772 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
773 struct wm8904_priv *wm8904 = codec->private_data;
774
775 ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg;
776
777 return 0;
778 }
779
780 static int deemph_settings[] = { 0, 32000, 44100, 48000 };
781
782 static int wm8904_set_deemph(struct snd_soc_codec *codec)
783 {
784 struct wm8904_priv *wm8904 = codec->private_data;
785 int val, i, best;
786
787 /* If we're using deemphasis select the nearest available sample
788 * rate.
789 */
790 if (wm8904->deemph) {
791 best = 1;
792 for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
793 if (abs(deemph_settings[i] - wm8904->fs) <
794 abs(deemph_settings[best] - wm8904->fs))
795 best = i;
796 }
797
798 val = best << WM8904_DEEMPH_SHIFT;
799 } else {
800 val = 0;
801 }
802
803 dev_dbg(codec->dev, "Set deemphasis %d\n", val);
804
805 return snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1,
806 WM8904_DEEMPH_MASK, val);
807 }
808
809 static int wm8904_get_deemph(struct snd_kcontrol *kcontrol,
810 struct snd_ctl_elem_value *ucontrol)
811 {
812 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
813 struct wm8904_priv *wm8904 = codec->private_data;
814
815 return wm8904->deemph;
816 }
817
818 static int wm8904_put_deemph(struct snd_kcontrol *kcontrol,
819 struct snd_ctl_elem_value *ucontrol)
820 {
821 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
822 struct wm8904_priv *wm8904 = codec->private_data;
823 int deemph = ucontrol->value.enumerated.item[0];
824
825 if (deemph > 1)
826 return -EINVAL;
827
828 wm8904->deemph = deemph;
829
830 return wm8904_set_deemph(codec);
831 }
832
833 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
834 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
835 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
836 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
837 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
838
839 static const char *input_mode_text[] = {
840 "Single-Ended", "Differential Line", "Differential Mic"
841 };
842
843 static const struct soc_enum lin_mode =
844 SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
845
846 static const struct soc_enum rin_mode =
847 SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
848
849 static const char *hpf_mode_text[] = {
850 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
851 };
852
853 static const struct soc_enum hpf_mode =
854 SOC_ENUM_SINGLE(WM8904_ADC_DIGITAL_0, 5, 4, hpf_mode_text);
855
856 static const struct snd_kcontrol_new wm8904_adc_snd_controls[] = {
857 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8904_ADC_DIGITAL_VOLUME_LEFT,
858 WM8904_ADC_DIGITAL_VOLUME_RIGHT, 1, 119, 0, digital_tlv),
859
860 SOC_ENUM("Left Caputure Mode", lin_mode),
861 SOC_ENUM("Right Capture Mode", rin_mode),
862
863 /* No TLV since it depends on mode */
864 SOC_DOUBLE_R("Capture Volume", WM8904_ANALOGUE_LEFT_INPUT_0,
865 WM8904_ANALOGUE_RIGHT_INPUT_0, 0, 31, 0),
866 SOC_DOUBLE_R("Capture Switch", WM8904_ANALOGUE_LEFT_INPUT_0,
867 WM8904_ANALOGUE_RIGHT_INPUT_0, 7, 1, 0),
868
869 SOC_SINGLE("High Pass Filter Switch", WM8904_ADC_DIGITAL_0, 4, 1, 0),
870 SOC_ENUM("High Pass Filter Mode", hpf_mode),
871
872 SOC_SINGLE("ADC 128x OSR Switch", WM8904_ANALOGUE_ADC_0, 0, 1, 0),
873 };
874
875 static const char *drc_path_text[] = {
876 "ADC", "DAC"
877 };
878
879 static const struct soc_enum drc_path =
880 SOC_ENUM_SINGLE(WM8904_DRC_0, 14, 2, drc_path_text);
881
882 static const struct snd_kcontrol_new wm8904_dac_snd_controls[] = {
883 SOC_SINGLE_TLV("Digital Playback Boost Volume",
884 WM8904_AUDIO_INTERFACE_0, 9, 3, 0, dac_boost_tlv),
885 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8904_DAC_DIGITAL_VOLUME_LEFT,
886 WM8904_DAC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
887
888 SOC_DOUBLE_R_TLV("Headphone Volume", WM8904_ANALOGUE_OUT1_LEFT,
889 WM8904_ANALOGUE_OUT1_RIGHT, 0, 63, 0, out_tlv),
890 SOC_DOUBLE_R("Headphone Switch", WM8904_ANALOGUE_OUT1_LEFT,
891 WM8904_ANALOGUE_OUT1_RIGHT, 8, 1, 1),
892 SOC_DOUBLE_R("Headphone ZC Switch", WM8904_ANALOGUE_OUT1_LEFT,
893 WM8904_ANALOGUE_OUT1_RIGHT, 6, 1, 0),
894
895 SOC_DOUBLE_R_TLV("Line Output Volume", WM8904_ANALOGUE_OUT2_LEFT,
896 WM8904_ANALOGUE_OUT2_RIGHT, 0, 63, 0, out_tlv),
897 SOC_DOUBLE_R("Line Output Switch", WM8904_ANALOGUE_OUT2_LEFT,
898 WM8904_ANALOGUE_OUT2_RIGHT, 8, 1, 1),
899 SOC_DOUBLE_R("Line Output ZC Switch", WM8904_ANALOGUE_OUT2_LEFT,
900 WM8904_ANALOGUE_OUT2_RIGHT, 6, 1, 0),
901
902 SOC_SINGLE("EQ Switch", WM8904_EQ1, 0, 1, 0),
903 SOC_SINGLE("DRC Switch", WM8904_DRC_0, 15, 1, 0),
904 SOC_ENUM("DRC Path", drc_path),
905 SOC_SINGLE("DAC OSRx2 Switch", WM8904_DAC_DIGITAL_1, 6, 1, 0),
906 SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
907 wm8904_get_deemph, wm8904_put_deemph),
908 };
909
910 static const struct snd_kcontrol_new wm8904_snd_controls[] = {
911 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8904_DAC_DIGITAL_0, 4, 8, 15, 0,
912 sidetone_tlv),
913 };
914
915 static const struct snd_kcontrol_new wm8904_eq_controls[] = {
916 SOC_SINGLE_TLV("EQ1 Volume", WM8904_EQ2, 0, 24, 0, eq_tlv),
917 SOC_SINGLE_TLV("EQ2 Volume", WM8904_EQ3, 0, 24, 0, eq_tlv),
918 SOC_SINGLE_TLV("EQ3 Volume", WM8904_EQ4, 0, 24, 0, eq_tlv),
919 SOC_SINGLE_TLV("EQ4 Volume", WM8904_EQ5, 0, 24, 0, eq_tlv),
920 SOC_SINGLE_TLV("EQ5 Volume", WM8904_EQ6, 0, 24, 0, eq_tlv),
921 };
922
923 static int cp_event(struct snd_soc_dapm_widget *w,
924 struct snd_kcontrol *kcontrol, int event)
925 {
926 BUG_ON(event != SND_SOC_DAPM_POST_PMU);
927
928 /* Maximum startup time */
929 udelay(500);
930
931 return 0;
932 }
933
934 static int sysclk_event(struct snd_soc_dapm_widget *w,
935 struct snd_kcontrol *kcontrol, int event)
936 {
937 struct snd_soc_codec *codec = w->codec;
938 struct wm8904_priv *wm8904 = codec->private_data;
939
940 switch (event) {
941 case SND_SOC_DAPM_PRE_PMU:
942 /* If we're using the FLL then we only start it when
943 * required; we assume that the configuration has been
944 * done previously and all we need to do is kick it
945 * off.
946 */
947 switch (wm8904->sysclk_src) {
948 case WM8904_CLK_FLL:
949 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
950 WM8904_FLL_OSC_ENA,
951 WM8904_FLL_OSC_ENA);
952
953 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
954 WM8904_FLL_ENA,
955 WM8904_FLL_ENA);
956 break;
957
958 default:
959 break;
960 }
961 break;
962
963 case SND_SOC_DAPM_POST_PMD:
964 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
965 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
966 break;
967 }
968
969 return 0;
970 }
971
972 static int out_pga_event(struct snd_soc_dapm_widget *w,
973 struct snd_kcontrol *kcontrol, int event)
974 {
975 struct snd_soc_codec *codec = w->codec;
976 struct wm8904_priv *wm8904 = codec->private_data;
977 int reg, val;
978 int dcs_mask;
979 int dcs_l, dcs_r;
980 int dcs_l_reg, dcs_r_reg;
981 int timeout;
982 int pwr_reg;
983
984 /* This code is shared between HP and LINEOUT; we do all our
985 * power management in stereo pairs to avoid latency issues so
986 * we reuse shift to identify which rather than strcmp() the
987 * name. */
988 reg = w->shift;
989
990 switch (reg) {
991 case WM8904_ANALOGUE_HP_0:
992 pwr_reg = WM8904_POWER_MANAGEMENT_2;
993 dcs_mask = WM8904_DCS_ENA_CHAN_0 | WM8904_DCS_ENA_CHAN_1;
994 dcs_r_reg = WM8904_DC_SERVO_8;
995 dcs_l_reg = WM8904_DC_SERVO_9;
996 dcs_l = 0;
997 dcs_r = 1;
998 break;
999 case WM8904_ANALOGUE_LINEOUT_0:
1000 pwr_reg = WM8904_POWER_MANAGEMENT_3;
1001 dcs_mask = WM8904_DCS_ENA_CHAN_2 | WM8904_DCS_ENA_CHAN_3;
1002 dcs_r_reg = WM8904_DC_SERVO_6;
1003 dcs_l_reg = WM8904_DC_SERVO_7;
1004 dcs_l = 2;
1005 dcs_r = 3;
1006 break;
1007 default:
1008 BUG();
1009 return -EINVAL;
1010 }
1011
1012 switch (event) {
1013 case SND_SOC_DAPM_PRE_PMU:
1014 /* Power on the PGAs */
1015 snd_soc_update_bits(codec, pwr_reg,
1016 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
1017 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA);
1018
1019 /* Power on the amplifier */
1020 snd_soc_update_bits(codec, reg,
1021 WM8904_HPL_ENA | WM8904_HPR_ENA,
1022 WM8904_HPL_ENA | WM8904_HPR_ENA);
1023
1024
1025 /* Enable the first stage */
1026 snd_soc_update_bits(codec, reg,
1027 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY,
1028 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY);
1029
1030 /* Power up the DC servo */
1031 snd_soc_update_bits(codec, WM8904_DC_SERVO_0,
1032 dcs_mask, dcs_mask);
1033
1034 /* Either calibrate the DC servo or restore cached state
1035 * if we have that.
1036 */
1037 if (wm8904->dcs_state[dcs_l] || wm8904->dcs_state[dcs_r]) {
1038 dev_dbg(codec->dev, "Restoring DC servo state\n");
1039
1040 snd_soc_write(codec, dcs_l_reg,
1041 wm8904->dcs_state[dcs_l]);
1042 snd_soc_write(codec, dcs_r_reg,
1043 wm8904->dcs_state[dcs_r]);
1044
1045 snd_soc_write(codec, WM8904_DC_SERVO_1, dcs_mask);
1046
1047 timeout = 20;
1048 } else {
1049 dev_dbg(codec->dev, "Calibrating DC servo\n");
1050
1051 snd_soc_write(codec, WM8904_DC_SERVO_1,
1052 dcs_mask << WM8904_DCS_TRIG_STARTUP_0_SHIFT);
1053
1054 timeout = 500;
1055 }
1056
1057 /* Wait for DC servo to complete */
1058 dcs_mask <<= WM8904_DCS_CAL_COMPLETE_SHIFT;
1059 do {
1060 val = snd_soc_read(codec, WM8904_DC_SERVO_READBACK_0);
1061 if ((val & dcs_mask) == dcs_mask)
1062 break;
1063
1064 msleep(1);
1065 } while (--timeout);
1066
1067 if ((val & dcs_mask) != dcs_mask)
1068 dev_warn(codec->dev, "DC servo timed out\n");
1069 else
1070 dev_dbg(codec->dev, "DC servo ready\n");
1071
1072 /* Enable the output stage */
1073 snd_soc_update_bits(codec, reg,
1074 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
1075 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP);
1076 break;
1077
1078 case SND_SOC_DAPM_POST_PMU:
1079 /* Unshort the output itself */
1080 snd_soc_update_bits(codec, reg,
1081 WM8904_HPL_RMV_SHORT |
1082 WM8904_HPR_RMV_SHORT,
1083 WM8904_HPL_RMV_SHORT |
1084 WM8904_HPR_RMV_SHORT);
1085
1086 break;
1087
1088 case SND_SOC_DAPM_PRE_PMD:
1089 /* Short the output */
1090 snd_soc_update_bits(codec, reg,
1091 WM8904_HPL_RMV_SHORT |
1092 WM8904_HPR_RMV_SHORT, 0);
1093 break;
1094
1095 case SND_SOC_DAPM_POST_PMD:
1096 /* Cache the DC servo configuration; this will be
1097 * invalidated if we change the configuration. */
1098 wm8904->dcs_state[dcs_l] = snd_soc_read(codec, dcs_l_reg);
1099 wm8904->dcs_state[dcs_r] = snd_soc_read(codec, dcs_r_reg);
1100
1101 snd_soc_update_bits(codec, WM8904_DC_SERVO_0,
1102 dcs_mask, 0);
1103
1104 /* Disable the amplifier input and output stages */
1105 snd_soc_update_bits(codec, reg,
1106 WM8904_HPL_ENA | WM8904_HPR_ENA |
1107 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY |
1108 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
1109 0);
1110
1111 /* PGAs too */
1112 snd_soc_update_bits(codec, pwr_reg,
1113 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
1114 0);
1115 break;
1116 }
1117
1118 return 0;
1119 }
1120
1121 static const char *lin_text[] = {
1122 "IN1L", "IN2L", "IN3L"
1123 };
1124
1125 static const struct soc_enum lin_enum =
1126 SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 2, 3, lin_text);
1127
1128 static const struct snd_kcontrol_new lin_mux =
1129 SOC_DAPM_ENUM("Left Capture Mux", lin_enum);
1130
1131 static const struct soc_enum lin_inv_enum =
1132 SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 4, 3, lin_text);
1133
1134 static const struct snd_kcontrol_new lin_inv_mux =
1135 SOC_DAPM_ENUM("Left Capture Inveting Mux", lin_inv_enum);
1136
1137 static const char *rin_text[] = {
1138 "IN1R", "IN2R", "IN3R"
1139 };
1140
1141 static const struct soc_enum rin_enum =
1142 SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 2, 3, rin_text);
1143
1144 static const struct snd_kcontrol_new rin_mux =
1145 SOC_DAPM_ENUM("Right Capture Mux", rin_enum);
1146
1147 static const struct soc_enum rin_inv_enum =
1148 SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 4, 3, rin_text);
1149
1150 static const struct snd_kcontrol_new rin_inv_mux =
1151 SOC_DAPM_ENUM("Right Capture Inveting Mux", rin_inv_enum);
1152
1153 static const char *aif_text[] = {
1154 "Left", "Right"
1155 };
1156
1157 static const struct soc_enum aifoutl_enum =
1158 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 7, 2, aif_text);
1159
1160 static const struct snd_kcontrol_new aifoutl_mux =
1161 SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
1162
1163 static const struct soc_enum aifoutr_enum =
1164 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 6, 2, aif_text);
1165
1166 static const struct snd_kcontrol_new aifoutr_mux =
1167 SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
1168
1169 static const struct soc_enum aifinl_enum =
1170 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 5, 2, aif_text);
1171
1172 static const struct snd_kcontrol_new aifinl_mux =
1173 SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
1174
1175 static const struct soc_enum aifinr_enum =
1176 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 4, 2, aif_text);
1177
1178 static const struct snd_kcontrol_new aifinr_mux =
1179 SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
1180
1181 static const struct snd_soc_dapm_widget wm8904_core_dapm_widgets[] = {
1182 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8904_CLOCK_RATES_2, 2, 0, sysclk_event,
1183 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1184 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8904_CLOCK_RATES_2, 1, 0, NULL, 0),
1185 SND_SOC_DAPM_SUPPLY("TOCLK", WM8904_CLOCK_RATES_2, 0, 0, NULL, 0),
1186 };
1187
1188 static const struct snd_soc_dapm_widget wm8904_adc_dapm_widgets[] = {
1189 SND_SOC_DAPM_INPUT("IN1L"),
1190 SND_SOC_DAPM_INPUT("IN1R"),
1191 SND_SOC_DAPM_INPUT("IN2L"),
1192 SND_SOC_DAPM_INPUT("IN2R"),
1193 SND_SOC_DAPM_INPUT("IN3L"),
1194 SND_SOC_DAPM_INPUT("IN3R"),
1195
1196 SND_SOC_DAPM_MICBIAS("MICBIAS", WM8904_MIC_BIAS_CONTROL_0, 0, 0),
1197
1198 SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lin_mux),
1199 SND_SOC_DAPM_MUX("Left Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
1200 &lin_inv_mux),
1201 SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rin_mux),
1202 SND_SOC_DAPM_MUX("Right Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
1203 &rin_inv_mux),
1204
1205 SND_SOC_DAPM_PGA("Left Capture PGA", WM8904_POWER_MANAGEMENT_0, 1, 0,
1206 NULL, 0),
1207 SND_SOC_DAPM_PGA("Right Capture PGA", WM8904_POWER_MANAGEMENT_0, 0, 0,
1208 NULL, 0),
1209
1210 SND_SOC_DAPM_ADC("ADCL", NULL, WM8904_POWER_MANAGEMENT_6, 1, 0),
1211 SND_SOC_DAPM_ADC("ADCR", NULL, WM8904_POWER_MANAGEMENT_6, 0, 0),
1212
1213 SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
1214 SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
1215
1216 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
1217 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
1218 };
1219
1220 static const struct snd_soc_dapm_widget wm8904_dac_dapm_widgets[] = {
1221 SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
1222 SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
1223
1224 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
1225 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
1226
1227 SND_SOC_DAPM_DAC("DACL", NULL, WM8904_POWER_MANAGEMENT_6, 3, 0),
1228 SND_SOC_DAPM_DAC("DACR", NULL, WM8904_POWER_MANAGEMENT_6, 2, 0),
1229
1230 SND_SOC_DAPM_SUPPLY("Charge pump", WM8904_CHARGE_PUMP_0, 0, 0, cp_event,
1231 SND_SOC_DAPM_POST_PMU),
1232
1233 SND_SOC_DAPM_PGA("HPL PGA", SND_SOC_NOPM, 1, 0, NULL, 0),
1234 SND_SOC_DAPM_PGA("HPR PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
1235
1236 SND_SOC_DAPM_PGA("LINEL PGA", SND_SOC_NOPM, 1, 0, NULL, 0),
1237 SND_SOC_DAPM_PGA("LINER PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
1238
1239 SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM, WM8904_ANALOGUE_HP_0,
1240 0, NULL, 0, out_pga_event,
1241 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1242 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1243 SND_SOC_DAPM_PGA_E("Line Output", SND_SOC_NOPM, WM8904_ANALOGUE_LINEOUT_0,
1244 0, NULL, 0, out_pga_event,
1245 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1246 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1247
1248 SND_SOC_DAPM_OUTPUT("HPOUTL"),
1249 SND_SOC_DAPM_OUTPUT("HPOUTR"),
1250 SND_SOC_DAPM_OUTPUT("LINEOUTL"),
1251 SND_SOC_DAPM_OUTPUT("LINEOUTR"),
1252 };
1253
1254 static const char *out_mux_text[] = {
1255 "DAC", "Bypass"
1256 };
1257
1258 static const struct soc_enum hpl_enum =
1259 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 3, 2, out_mux_text);
1260
1261 static const struct snd_kcontrol_new hpl_mux =
1262 SOC_DAPM_ENUM("HPL Mux", hpl_enum);
1263
1264 static const struct soc_enum hpr_enum =
1265 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 2, 2, out_mux_text);
1266
1267 static const struct snd_kcontrol_new hpr_mux =
1268 SOC_DAPM_ENUM("HPR Mux", hpr_enum);
1269
1270 static const struct soc_enum linel_enum =
1271 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 1, 2, out_mux_text);
1272
1273 static const struct snd_kcontrol_new linel_mux =
1274 SOC_DAPM_ENUM("LINEL Mux", linel_enum);
1275
1276 static const struct soc_enum liner_enum =
1277 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 0, 2, out_mux_text);
1278
1279 static const struct snd_kcontrol_new liner_mux =
1280 SOC_DAPM_ENUM("LINEL Mux", liner_enum);
1281
1282 static const char *sidetone_text[] = {
1283 "None", "Left", "Right"
1284 };
1285
1286 static const struct soc_enum dacl_sidetone_enum =
1287 SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0, 2, 3, sidetone_text);
1288
1289 static const struct snd_kcontrol_new dacl_sidetone_mux =
1290 SOC_DAPM_ENUM("Left Sidetone Mux", dacl_sidetone_enum);
1291
1292 static const struct soc_enum dacr_sidetone_enum =
1293 SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0, 0, 3, sidetone_text);
1294
1295 static const struct snd_kcontrol_new dacr_sidetone_mux =
1296 SOC_DAPM_ENUM("Right Sidetone Mux", dacr_sidetone_enum);
1297
1298 static const struct snd_soc_dapm_widget wm8904_dapm_widgets[] = {
1299 SND_SOC_DAPM_SUPPLY("Class G", WM8904_CLASS_W_0, 0, 1, NULL, 0),
1300 SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
1301 SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
1302
1303 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &dacl_sidetone_mux),
1304 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &dacr_sidetone_mux),
1305
1306 SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1307 SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1308 SND_SOC_DAPM_MUX("LINEL Mux", SND_SOC_NOPM, 0, 0, &linel_mux),
1309 SND_SOC_DAPM_MUX("LINER Mux", SND_SOC_NOPM, 0, 0, &liner_mux),
1310 };
1311
1312 static const struct snd_soc_dapm_route core_intercon[] = {
1313 { "CLK_DSP", NULL, "SYSCLK" },
1314 { "TOCLK", NULL, "SYSCLK" },
1315 };
1316
1317 static const struct snd_soc_dapm_route adc_intercon[] = {
1318 { "Left Capture Mux", "IN1L", "IN1L" },
1319 { "Left Capture Mux", "IN2L", "IN2L" },
1320 { "Left Capture Mux", "IN3L", "IN3L" },
1321
1322 { "Left Capture Inverting Mux", "IN1L", "IN1L" },
1323 { "Left Capture Inverting Mux", "IN2L", "IN2L" },
1324 { "Left Capture Inverting Mux", "IN3L", "IN3L" },
1325
1326 { "Right Capture Mux", "IN1R", "IN1R" },
1327 { "Right Capture Mux", "IN2R", "IN2R" },
1328 { "Right Capture Mux", "IN3R", "IN3R" },
1329
1330 { "Right Capture Inverting Mux", "IN1R", "IN1R" },
1331 { "Right Capture Inverting Mux", "IN2R", "IN2R" },
1332 { "Right Capture Inverting Mux", "IN3R", "IN3R" },
1333
1334 { "Left Capture PGA", NULL, "Left Capture Mux" },
1335 { "Left Capture PGA", NULL, "Left Capture Inverting Mux" },
1336
1337 { "Right Capture PGA", NULL, "Right Capture Mux" },
1338 { "Right Capture PGA", NULL, "Right Capture Inverting Mux" },
1339
1340 { "AIFOUTL", "Left", "ADCL" },
1341 { "AIFOUTL", "Right", "ADCR" },
1342 { "AIFOUTR", "Left", "ADCL" },
1343 { "AIFOUTR", "Right", "ADCR" },
1344
1345 { "ADCL", NULL, "CLK_DSP" },
1346 { "ADCL", NULL, "Left Capture PGA" },
1347
1348 { "ADCR", NULL, "CLK_DSP" },
1349 { "ADCR", NULL, "Right Capture PGA" },
1350 };
1351
1352 static const struct snd_soc_dapm_route dac_intercon[] = {
1353 { "DACL", "Right", "AIFINR" },
1354 { "DACL", "Left", "AIFINL" },
1355 { "DACL", NULL, "CLK_DSP" },
1356
1357 { "DACR", "Right", "AIFINR" },
1358 { "DACR", "Left", "AIFINL" },
1359 { "DACR", NULL, "CLK_DSP" },
1360
1361 { "Charge pump", NULL, "SYSCLK" },
1362
1363 { "Headphone Output", NULL, "HPL PGA" },
1364 { "Headphone Output", NULL, "HPR PGA" },
1365 { "Headphone Output", NULL, "Charge pump" },
1366 { "Headphone Output", NULL, "TOCLK" },
1367
1368 { "Line Output", NULL, "LINEL PGA" },
1369 { "Line Output", NULL, "LINER PGA" },
1370 { "Line Output", NULL, "Charge pump" },
1371 { "Line Output", NULL, "TOCLK" },
1372
1373 { "HPOUTL", NULL, "Headphone Output" },
1374 { "HPOUTR", NULL, "Headphone Output" },
1375
1376 { "LINEOUTL", NULL, "Line Output" },
1377 { "LINEOUTR", NULL, "Line Output" },
1378 };
1379
1380 static const struct snd_soc_dapm_route wm8904_intercon[] = {
1381 { "Left Sidetone", "Left", "ADCL" },
1382 { "Left Sidetone", "Right", "ADCR" },
1383 { "DACL", NULL, "Left Sidetone" },
1384
1385 { "Right Sidetone", "Left", "ADCL" },
1386 { "Right Sidetone", "Right", "ADCR" },
1387 { "DACR", NULL, "Right Sidetone" },
1388
1389 { "Left Bypass", NULL, "Class G" },
1390 { "Left Bypass", NULL, "Left Capture PGA" },
1391
1392 { "Right Bypass", NULL, "Class G" },
1393 { "Right Bypass", NULL, "Right Capture PGA" },
1394
1395 { "HPL Mux", "DAC", "DACL" },
1396 { "HPL Mux", "Bypass", "Left Bypass" },
1397
1398 { "HPR Mux", "DAC", "DACR" },
1399 { "HPR Mux", "Bypass", "Right Bypass" },
1400
1401 { "LINEL Mux", "DAC", "DACL" },
1402 { "LINEL Mux", "Bypass", "Left Bypass" },
1403
1404 { "LINER Mux", "DAC", "DACR" },
1405 { "LINER Mux", "Bypass", "Right Bypass" },
1406
1407 { "HPL PGA", NULL, "HPL Mux" },
1408 { "HPR PGA", NULL, "HPR Mux" },
1409
1410 { "LINEL PGA", NULL, "LINEL Mux" },
1411 { "LINER PGA", NULL, "LINER Mux" },
1412 };
1413
1414 static int wm8904_add_widgets(struct snd_soc_codec *codec)
1415 {
1416 snd_soc_add_controls(codec, wm8904_adc_snd_controls,
1417 ARRAY_SIZE(wm8904_adc_snd_controls));
1418 snd_soc_add_controls(codec, wm8904_dac_snd_controls,
1419 ARRAY_SIZE(wm8904_dac_snd_controls));
1420 snd_soc_add_controls(codec, wm8904_snd_controls,
1421 ARRAY_SIZE(wm8904_snd_controls));
1422
1423 snd_soc_dapm_new_controls(codec, wm8904_core_dapm_widgets,
1424 ARRAY_SIZE(wm8904_core_dapm_widgets));
1425 snd_soc_dapm_new_controls(codec, wm8904_adc_dapm_widgets,
1426 ARRAY_SIZE(wm8904_adc_dapm_widgets));
1427 snd_soc_dapm_new_controls(codec, wm8904_dac_dapm_widgets,
1428 ARRAY_SIZE(wm8904_dac_dapm_widgets));
1429 snd_soc_dapm_new_controls(codec, wm8904_dapm_widgets,
1430 ARRAY_SIZE(wm8904_dapm_widgets));
1431
1432 snd_soc_dapm_add_routes(codec, core_intercon,
1433 ARRAY_SIZE(core_intercon));
1434 snd_soc_dapm_add_routes(codec, adc_intercon, ARRAY_SIZE(adc_intercon));
1435 snd_soc_dapm_add_routes(codec, dac_intercon, ARRAY_SIZE(dac_intercon));
1436 snd_soc_dapm_add_routes(codec, wm8904_intercon,
1437 ARRAY_SIZE(wm8904_intercon));
1438
1439 snd_soc_dapm_new_widgets(codec);
1440 return 0;
1441 }
1442
1443 static struct {
1444 int ratio;
1445 unsigned int clk_sys_rate;
1446 } clk_sys_rates[] = {
1447 { 64, 0 },
1448 { 128, 1 },
1449 { 192, 2 },
1450 { 256, 3 },
1451 { 384, 4 },
1452 { 512, 5 },
1453 { 786, 6 },
1454 { 1024, 7 },
1455 { 1408, 8 },
1456 { 1536, 9 },
1457 };
1458
1459 static struct {
1460 int rate;
1461 int sample_rate;
1462 } sample_rates[] = {
1463 { 8000, 0 },
1464 { 11025, 1 },
1465 { 12000, 1 },
1466 { 16000, 2 },
1467 { 22050, 3 },
1468 { 24000, 3 },
1469 { 32000, 4 },
1470 { 44100, 5 },
1471 { 48000, 5 },
1472 };
1473
1474 static struct {
1475 int div; /* *10 due to .5s */
1476 int bclk_div;
1477 } bclk_divs[] = {
1478 { 10, 0 },
1479 { 15, 1 },
1480 { 20, 2 },
1481 { 30, 3 },
1482 { 40, 4 },
1483 { 50, 5 },
1484 { 55, 6 },
1485 { 60, 7 },
1486 { 80, 8 },
1487 { 100, 9 },
1488 { 110, 10 },
1489 { 120, 11 },
1490 { 160, 12 },
1491 { 200, 13 },
1492 { 220, 14 },
1493 { 240, 16 },
1494 { 200, 17 },
1495 { 320, 18 },
1496 { 440, 19 },
1497 { 480, 20 },
1498 };
1499
1500
1501 static int wm8904_hw_params(struct snd_pcm_substream *substream,
1502 struct snd_pcm_hw_params *params,
1503 struct snd_soc_dai *dai)
1504 {
1505 struct snd_soc_codec *codec = dai->codec;
1506 struct wm8904_priv *wm8904 = codec->private_data;
1507 int ret, i, best, best_val, cur_val;
1508 unsigned int aif1 = 0;
1509 unsigned int aif2 = 0;
1510 unsigned int aif3 = 0;
1511 unsigned int clock1 = 0;
1512 unsigned int dac_digital1 = 0;
1513
1514 /* What BCLK do we need? */
1515 wm8904->fs = params_rate(params);
1516 if (wm8904->tdm_slots) {
1517 dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n",
1518 wm8904->tdm_slots, wm8904->tdm_width);
1519 wm8904->bclk = snd_soc_calc_bclk(wm8904->fs,
1520 wm8904->tdm_width, 2,
1521 wm8904->tdm_slots);
1522 } else {
1523 wm8904->bclk = snd_soc_params_to_bclk(params);
1524 }
1525
1526 switch (params_format(params)) {
1527 case SNDRV_PCM_FORMAT_S16_LE:
1528 break;
1529 case SNDRV_PCM_FORMAT_S20_3LE:
1530 aif1 |= 0x40;
1531 break;
1532 case SNDRV_PCM_FORMAT_S24_LE:
1533 aif1 |= 0x80;
1534 break;
1535 case SNDRV_PCM_FORMAT_S32_LE:
1536 aif1 |= 0xc0;
1537 break;
1538 default:
1539 return -EINVAL;
1540 }
1541
1542
1543 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8904->bclk);
1544
1545 ret = wm8904_configure_clocking(codec);
1546 if (ret != 0)
1547 return ret;
1548
1549 /* Select nearest CLK_SYS_RATE */
1550 best = 0;
1551 best_val = abs((wm8904->sysclk_rate / clk_sys_rates[0].ratio)
1552 - wm8904->fs);
1553 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1554 cur_val = abs((wm8904->sysclk_rate /
1555 clk_sys_rates[i].ratio) - wm8904->fs);;
1556 if (cur_val < best_val) {
1557 best = i;
1558 best_val = cur_val;
1559 }
1560 }
1561 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1562 clk_sys_rates[best].ratio);
1563 clock1 |= (clk_sys_rates[best].clk_sys_rate
1564 << WM8904_CLK_SYS_RATE_SHIFT);
1565
1566 /* SAMPLE_RATE */
1567 best = 0;
1568 best_val = abs(wm8904->fs - sample_rates[0].rate);
1569 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1570 /* Closest match */
1571 cur_val = abs(wm8904->fs - sample_rates[i].rate);
1572 if (cur_val < best_val) {
1573 best = i;
1574 best_val = cur_val;
1575 }
1576 }
1577 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1578 sample_rates[best].rate);
1579 clock1 |= (sample_rates[best].sample_rate
1580 << WM8904_SAMPLE_RATE_SHIFT);
1581
1582 /* Enable sloping stopband filter for low sample rates */
1583 if (wm8904->fs <= 24000)
1584 dac_digital1 |= WM8904_DAC_SB_FILT;
1585
1586 /* BCLK_DIV */
1587 best = 0;
1588 best_val = INT_MAX;
1589 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1590 cur_val = ((wm8904->sysclk_rate * 10) / bclk_divs[i].div)
1591 - wm8904->bclk;
1592 if (cur_val < 0) /* Table is sorted */
1593 break;
1594 if (cur_val < best_val) {
1595 best = i;
1596 best_val = cur_val;
1597 }
1598 }
1599 wm8904->bclk = (wm8904->sysclk_rate * 10) / bclk_divs[best].div;
1600 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1601 bclk_divs[best].div, wm8904->bclk);
1602 aif2 |= bclk_divs[best].bclk_div;
1603
1604 /* LRCLK is a simple fraction of BCLK */
1605 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8904->bclk / wm8904->fs);
1606 aif3 |= wm8904->bclk / wm8904->fs;
1607
1608 /* Apply the settings */
1609 snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1,
1610 WM8904_DAC_SB_FILT, dac_digital1);
1611 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
1612 WM8904_AIF_WL_MASK, aif1);
1613 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_2,
1614 WM8904_BCLK_DIV_MASK, aif2);
1615 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3,
1616 WM8904_LRCLK_RATE_MASK, aif3);
1617 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_1,
1618 WM8904_SAMPLE_RATE_MASK |
1619 WM8904_CLK_SYS_RATE_MASK, clock1);
1620
1621 /* Update filters for the new settings */
1622 wm8904_set_retune_mobile(codec);
1623 wm8904_set_deemph(codec);
1624
1625 return 0;
1626 }
1627
1628
1629 static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id,
1630 unsigned int freq, int dir)
1631 {
1632 struct snd_soc_codec *codec = dai->codec;
1633 struct wm8904_priv *priv = codec->private_data;
1634
1635 switch (clk_id) {
1636 case WM8904_CLK_MCLK:
1637 priv->sysclk_src = clk_id;
1638 priv->mclk_rate = freq;
1639 break;
1640
1641 case WM8904_CLK_FLL:
1642 priv->sysclk_src = clk_id;
1643 break;
1644
1645 default:
1646 return -EINVAL;
1647 }
1648
1649 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
1650
1651 wm8904_configure_clocking(codec);
1652
1653 return 0;
1654 }
1655
1656 static int wm8904_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1657 {
1658 struct snd_soc_codec *codec = dai->codec;
1659 unsigned int aif1 = 0;
1660 unsigned int aif3 = 0;
1661
1662 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1663 case SND_SOC_DAIFMT_CBS_CFS:
1664 break;
1665 case SND_SOC_DAIFMT_CBS_CFM:
1666 aif3 |= WM8904_LRCLK_DIR;
1667 break;
1668 case SND_SOC_DAIFMT_CBM_CFS:
1669 aif1 |= WM8904_BCLK_DIR;
1670 break;
1671 case SND_SOC_DAIFMT_CBM_CFM:
1672 aif1 |= WM8904_BCLK_DIR;
1673 aif3 |= WM8904_LRCLK_DIR;
1674 break;
1675 default:
1676 return -EINVAL;
1677 }
1678
1679 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1680 case SND_SOC_DAIFMT_DSP_B:
1681 aif1 |= WM8904_AIF_LRCLK_INV;
1682 case SND_SOC_DAIFMT_DSP_A:
1683 aif1 |= 0x3;
1684 break;
1685 case SND_SOC_DAIFMT_I2S:
1686 aif1 |= 0x2;
1687 break;
1688 case SND_SOC_DAIFMT_RIGHT_J:
1689 break;
1690 case SND_SOC_DAIFMT_LEFT_J:
1691 aif1 |= 0x1;
1692 break;
1693 default:
1694 return -EINVAL;
1695 }
1696
1697 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1698 case SND_SOC_DAIFMT_DSP_A:
1699 case SND_SOC_DAIFMT_DSP_B:
1700 /* frame inversion not valid for DSP modes */
1701 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1702 case SND_SOC_DAIFMT_NB_NF:
1703 break;
1704 case SND_SOC_DAIFMT_IB_NF:
1705 aif1 |= WM8904_AIF_BCLK_INV;
1706 break;
1707 default:
1708 return -EINVAL;
1709 }
1710 break;
1711
1712 case SND_SOC_DAIFMT_I2S:
1713 case SND_SOC_DAIFMT_RIGHT_J:
1714 case SND_SOC_DAIFMT_LEFT_J:
1715 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1716 case SND_SOC_DAIFMT_NB_NF:
1717 break;
1718 case SND_SOC_DAIFMT_IB_IF:
1719 aif1 |= WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV;
1720 break;
1721 case SND_SOC_DAIFMT_IB_NF:
1722 aif1 |= WM8904_AIF_BCLK_INV;
1723 break;
1724 case SND_SOC_DAIFMT_NB_IF:
1725 aif1 |= WM8904_AIF_LRCLK_INV;
1726 break;
1727 default:
1728 return -EINVAL;
1729 }
1730 break;
1731 default:
1732 return -EINVAL;
1733 }
1734
1735 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
1736 WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV |
1737 WM8904_AIF_FMT_MASK | WM8904_BCLK_DIR, aif1);
1738 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3,
1739 WM8904_LRCLK_DIR, aif3);
1740
1741 return 0;
1742 }
1743
1744
1745 static int wm8904_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1746 unsigned int rx_mask, int slots, int slot_width)
1747 {
1748 struct snd_soc_codec *codec = dai->codec;
1749 struct wm8904_priv *wm8904 = codec->private_data;
1750 int aif1 = 0;
1751
1752 /* Don't need to validate anything if we're turning off TDM */
1753 if (slots == 0)
1754 goto out;
1755
1756 /* Note that we allow configurations we can't handle ourselves -
1757 * for example, we can generate clocks for slots 2 and up even if
1758 * we can't use those slots ourselves.
1759 */
1760 aif1 |= WM8904_AIFADC_TDM | WM8904_AIFDAC_TDM;
1761
1762 switch (rx_mask) {
1763 case 3:
1764 break;
1765 case 0xc:
1766 aif1 |= WM8904_AIFADC_TDM_CHAN;
1767 break;
1768 default:
1769 return -EINVAL;
1770 }
1771
1772
1773 switch (tx_mask) {
1774 case 3:
1775 break;
1776 case 0xc:
1777 aif1 |= WM8904_AIFDAC_TDM_CHAN;
1778 break;
1779 default:
1780 return -EINVAL;
1781 }
1782
1783 out:
1784 wm8904->tdm_width = slot_width;
1785 wm8904->tdm_slots = slots / 2;
1786
1787 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
1788 WM8904_AIFADC_TDM | WM8904_AIFADC_TDM_CHAN |
1789 WM8904_AIFDAC_TDM | WM8904_AIFDAC_TDM_CHAN, aif1);
1790
1791 return 0;
1792 }
1793
1794 struct _fll_div {
1795 u16 fll_fratio;
1796 u16 fll_outdiv;
1797 u16 fll_clk_ref_div;
1798 u16 n;
1799 u16 k;
1800 };
1801
1802 /* The size in bits of the FLL divide multiplied by 10
1803 * to allow rounding later */
1804 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1805
1806 static struct {
1807 unsigned int min;
1808 unsigned int max;
1809 u16 fll_fratio;
1810 int ratio;
1811 } fll_fratios[] = {
1812 { 0, 64000, 4, 16 },
1813 { 64000, 128000, 3, 8 },
1814 { 128000, 256000, 2, 4 },
1815 { 256000, 1000000, 1, 2 },
1816 { 1000000, 13500000, 0, 1 },
1817 };
1818
1819 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1820 unsigned int Fout)
1821 {
1822 u64 Kpart;
1823 unsigned int K, Ndiv, Nmod, target;
1824 unsigned int div;
1825 int i;
1826
1827 /* Fref must be <=13.5MHz */
1828 div = 1;
1829 fll_div->fll_clk_ref_div = 0;
1830 while ((Fref / div) > 13500000) {
1831 div *= 2;
1832 fll_div->fll_clk_ref_div++;
1833
1834 if (div > 8) {
1835 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1836 Fref);
1837 return -EINVAL;
1838 }
1839 }
1840
1841 pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
1842
1843 /* Apply the division for our remaining calculations */
1844 Fref /= div;
1845
1846 /* Fvco should be 90-100MHz; don't check the upper bound */
1847 div = 4;
1848 while (Fout * div < 90000000) {
1849 div++;
1850 if (div > 64) {
1851 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1852 Fout);
1853 return -EINVAL;
1854 }
1855 }
1856 target = Fout * div;
1857 fll_div->fll_outdiv = div - 1;
1858
1859 pr_debug("Fvco=%dHz\n", target);
1860
1861 /* Find an appropraite FLL_FRATIO and factor it out of the target */
1862 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1863 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1864 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1865 target /= fll_fratios[i].ratio;
1866 break;
1867 }
1868 }
1869 if (i == ARRAY_SIZE(fll_fratios)) {
1870 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1871 return -EINVAL;
1872 }
1873
1874 /* Now, calculate N.K */
1875 Ndiv = target / Fref;
1876
1877 fll_div->n = Ndiv;
1878 Nmod = target % Fref;
1879 pr_debug("Nmod=%d\n", Nmod);
1880
1881 /* Calculate fractional part - scale up so we can round. */
1882 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1883
1884 do_div(Kpart, Fref);
1885
1886 K = Kpart & 0xFFFFFFFF;
1887
1888 if ((K % 10) >= 5)
1889 K += 5;
1890
1891 /* Move down to proper range now rounding is done */
1892 fll_div->k = K / 10;
1893
1894 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
1895 fll_div->n, fll_div->k,
1896 fll_div->fll_fratio, fll_div->fll_outdiv,
1897 fll_div->fll_clk_ref_div);
1898
1899 return 0;
1900 }
1901
1902 static int wm8904_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
1903 unsigned int Fref, unsigned int Fout)
1904 {
1905 struct snd_soc_codec *codec = dai->codec;
1906 struct wm8904_priv *wm8904 = codec->private_data;
1907 struct _fll_div fll_div;
1908 int ret, val;
1909 int clock2, fll1;
1910
1911 /* Any change? */
1912 if (source == wm8904->fll_src && Fref == wm8904->fll_fref &&
1913 Fout == wm8904->fll_fout)
1914 return 0;
1915
1916 clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2);
1917
1918 if (Fout == 0) {
1919 dev_dbg(codec->dev, "FLL disabled\n");
1920
1921 wm8904->fll_fref = 0;
1922 wm8904->fll_fout = 0;
1923
1924 /* Gate SYSCLK to avoid glitches */
1925 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
1926 WM8904_CLK_SYS_ENA, 0);
1927
1928 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1929 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
1930
1931 goto out;
1932 }
1933
1934 /* Validate the FLL ID */
1935 switch (source) {
1936 case WM8904_FLL_MCLK:
1937 case WM8904_FLL_LRCLK:
1938 case WM8904_FLL_BCLK:
1939 ret = fll_factors(&fll_div, Fref, Fout);
1940 if (ret != 0)
1941 return ret;
1942 break;
1943
1944 case WM8904_FLL_FREE_RUNNING:
1945 dev_dbg(codec->dev, "Using free running FLL\n");
1946 /* Force 12MHz and output/4 for now */
1947 Fout = 12000000;
1948 Fref = 12000000;
1949
1950 memset(&fll_div, 0, sizeof(fll_div));
1951 fll_div.fll_outdiv = 3;
1952 break;
1953
1954 default:
1955 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
1956 return -EINVAL;
1957 }
1958
1959 /* Save current state then disable the FLL and SYSCLK to avoid
1960 * misclocking */
1961 fll1 = snd_soc_read(codec, WM8904_FLL_CONTROL_1);
1962 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
1963 WM8904_CLK_SYS_ENA, 0);
1964 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1965 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
1966
1967 /* Unlock forced oscilator control to switch it on/off */
1968 snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1,
1969 WM8904_USER_KEY, WM8904_USER_KEY);
1970
1971 if (fll_id == WM8904_FLL_FREE_RUNNING) {
1972 val = WM8904_FLL_FRC_NCO;
1973 } else {
1974 val = 0;
1975 }
1976
1977 snd_soc_update_bits(codec, WM8904_FLL_NCO_TEST_1, WM8904_FLL_FRC_NCO,
1978 val);
1979 snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1,
1980 WM8904_USER_KEY, 0);
1981
1982 switch (fll_id) {
1983 case WM8904_FLL_MCLK:
1984 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
1985 WM8904_FLL_CLK_REF_SRC_MASK, 0);
1986 break;
1987
1988 case WM8904_FLL_LRCLK:
1989 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
1990 WM8904_FLL_CLK_REF_SRC_MASK, 1);
1991 break;
1992
1993 case WM8904_FLL_BCLK:
1994 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
1995 WM8904_FLL_CLK_REF_SRC_MASK, 2);
1996 break;
1997 }
1998
1999 if (fll_div.k)
2000 val = WM8904_FLL_FRACN_ENA;
2001 else
2002 val = 0;
2003 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
2004 WM8904_FLL_FRACN_ENA, val);
2005
2006 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_2,
2007 WM8904_FLL_OUTDIV_MASK | WM8904_FLL_FRATIO_MASK,
2008 (fll_div.fll_outdiv << WM8904_FLL_OUTDIV_SHIFT) |
2009 (fll_div.fll_fratio << WM8904_FLL_FRATIO_SHIFT));
2010
2011 snd_soc_write(codec, WM8904_FLL_CONTROL_3, fll_div.k);
2012
2013 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_4, WM8904_FLL_N_MASK,
2014 fll_div.n << WM8904_FLL_N_SHIFT);
2015
2016 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
2017 WM8904_FLL_CLK_REF_DIV_MASK,
2018 fll_div.fll_clk_ref_div
2019 << WM8904_FLL_CLK_REF_DIV_SHIFT);
2020
2021 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2022
2023 wm8904->fll_fref = Fref;
2024 wm8904->fll_fout = Fout;
2025 wm8904->fll_src = source;
2026
2027 /* Enable the FLL if it was previously active */
2028 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
2029 WM8904_FLL_OSC_ENA, fll1);
2030 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
2031 WM8904_FLL_ENA, fll1);
2032
2033 out:
2034 /* Reenable SYSCLK if it was previously active */
2035 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
2036 WM8904_CLK_SYS_ENA, clock2);
2037
2038 return 0;
2039 }
2040
2041 static int wm8904_digital_mute(struct snd_soc_dai *codec_dai, int mute)
2042 {
2043 struct snd_soc_codec *codec = codec_dai->codec;
2044 int val;
2045
2046 if (mute)
2047 val = WM8904_DAC_MUTE;
2048 else
2049 val = 0;
2050
2051 snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, WM8904_DAC_MUTE, val);
2052
2053 return 0;
2054 }
2055
2056 static void wm8904_sync_cache(struct snd_soc_codec *codec)
2057 {
2058 struct wm8904_priv *wm8904 = codec->private_data;
2059 int i;
2060
2061 if (!codec->cache_sync)
2062 return;
2063
2064 codec->cache_only = 0;
2065
2066 /* Sync back cached values if they're different from the
2067 * hardware default.
2068 */
2069 for (i = 1; i < ARRAY_SIZE(wm8904->reg_cache); i++) {
2070 if (!wm8904_access[i].writable)
2071 continue;
2072
2073 if (wm8904->reg_cache[i] == wm8904_reg[i])
2074 continue;
2075
2076 snd_soc_write(codec, i, wm8904->reg_cache[i]);
2077 }
2078
2079 codec->cache_sync = 0;
2080 }
2081
2082 static int wm8904_set_bias_level(struct snd_soc_codec *codec,
2083 enum snd_soc_bias_level level)
2084 {
2085 struct wm8904_priv *wm8904 = codec->private_data;
2086 int ret;
2087
2088 switch (level) {
2089 case SND_SOC_BIAS_ON:
2090 break;
2091
2092 case SND_SOC_BIAS_PREPARE:
2093 /* VMID resistance 2*50k */
2094 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
2095 WM8904_VMID_RES_MASK,
2096 0x1 << WM8904_VMID_RES_SHIFT);
2097
2098 /* Normal bias current */
2099 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
2100 WM8904_ISEL_MASK, 2 << WM8904_ISEL_SHIFT);
2101 break;
2102
2103 case SND_SOC_BIAS_STANDBY:
2104 if (codec->bias_level == SND_SOC_BIAS_OFF) {
2105 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
2106 wm8904->supplies);
2107 if (ret != 0) {
2108 dev_err(codec->dev,
2109 "Failed to enable supplies: %d\n",
2110 ret);
2111 return ret;
2112 }
2113
2114 wm8904_sync_cache(codec);
2115
2116 /* Enable bias */
2117 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
2118 WM8904_BIAS_ENA, WM8904_BIAS_ENA);
2119
2120 /* Enable VMID, VMID buffering, 2*5k resistance */
2121 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
2122 WM8904_VMID_ENA |
2123 WM8904_VMID_RES_MASK,
2124 WM8904_VMID_ENA |
2125 0x3 << WM8904_VMID_RES_SHIFT);
2126
2127 /* Let VMID ramp */
2128 msleep(1);
2129 }
2130
2131 /* Maintain VMID with 2*250k */
2132 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
2133 WM8904_VMID_RES_MASK,
2134 0x2 << WM8904_VMID_RES_SHIFT);
2135
2136 /* Bias current *0.5 */
2137 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
2138 WM8904_ISEL_MASK, 0);
2139 break;
2140
2141 case SND_SOC_BIAS_OFF:
2142 /* Turn off VMID */
2143 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
2144 WM8904_VMID_RES_MASK | WM8904_VMID_ENA, 0);
2145
2146 /* Stop bias generation */
2147 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
2148 WM8904_BIAS_ENA, 0);
2149
2150 #ifdef CONFIG_REGULATOR
2151 /* Post 2.6.34 we will be able to get a callback when
2152 * the regulators are disabled which we can use but
2153 * for now just assume that the power will be cut if
2154 * the regulator API is in use.
2155 */
2156 codec->cache_sync = 1;
2157 #endif
2158
2159 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies),
2160 wm8904->supplies);
2161 break;
2162 }
2163 codec->bias_level = level;
2164 return 0;
2165 }
2166
2167 #define WM8904_RATES SNDRV_PCM_RATE_8000_96000
2168
2169 #define WM8904_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2170 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2171
2172 static struct snd_soc_dai_ops wm8904_dai_ops = {
2173 .set_sysclk = wm8904_set_sysclk,
2174 .set_fmt = wm8904_set_fmt,
2175 .set_tdm_slot = wm8904_set_tdm_slot,
2176 .set_pll = wm8904_set_fll,
2177 .hw_params = wm8904_hw_params,
2178 .digital_mute = wm8904_digital_mute,
2179 };
2180
2181 struct snd_soc_dai wm8904_dai = {
2182 .name = "WM8904",
2183 .playback = {
2184 .stream_name = "Playback",
2185 .channels_min = 2,
2186 .channels_max = 2,
2187 .rates = WM8904_RATES,
2188 .formats = WM8904_FORMATS,
2189 },
2190 .capture = {
2191 .stream_name = "Capture",
2192 .channels_min = 2,
2193 .channels_max = 2,
2194 .rates = WM8904_RATES,
2195 .formats = WM8904_FORMATS,
2196 },
2197 .ops = &wm8904_dai_ops,
2198 .symmetric_rates = 1,
2199 };
2200 EXPORT_SYMBOL_GPL(wm8904_dai);
2201
2202 #ifdef CONFIG_PM
2203 static int wm8904_suspend(struct platform_device *pdev, pm_message_t state)
2204 {
2205 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2206 struct snd_soc_codec *codec = socdev->card->codec;
2207
2208 wm8904_set_bias_level(codec, SND_SOC_BIAS_OFF);
2209
2210 return 0;
2211 }
2212
2213 static int wm8904_resume(struct platform_device *pdev)
2214 {
2215 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2216 struct snd_soc_codec *codec = socdev->card->codec;
2217
2218 wm8904_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2219
2220 return 0;
2221 }
2222 #else
2223 #define wm8904_suspend NULL
2224 #define wm8904_resume NULL
2225 #endif
2226
2227 static void wm8904_handle_retune_mobile_pdata(struct wm8904_priv *wm8904)
2228 {
2229 struct snd_soc_codec *codec = &wm8904->codec;
2230 struct wm8904_pdata *pdata = wm8904->pdata;
2231 struct snd_kcontrol_new control =
2232 SOC_ENUM_EXT("EQ Mode",
2233 wm8904->retune_mobile_enum,
2234 wm8904_get_retune_mobile_enum,
2235 wm8904_put_retune_mobile_enum);
2236 int ret, i, j;
2237 const char **t;
2238
2239 /* We need an array of texts for the enum API but the number
2240 * of texts is likely to be less than the number of
2241 * configurations due to the sample rate dependency of the
2242 * configurations. */
2243 wm8904->num_retune_mobile_texts = 0;
2244 wm8904->retune_mobile_texts = NULL;
2245 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2246 for (j = 0; j < wm8904->num_retune_mobile_texts; j++) {
2247 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2248 wm8904->retune_mobile_texts[j]) == 0)
2249 break;
2250 }
2251
2252 if (j != wm8904->num_retune_mobile_texts)
2253 continue;
2254
2255 /* Expand the array... */
2256 t = krealloc(wm8904->retune_mobile_texts,
2257 sizeof(char *) *
2258 (wm8904->num_retune_mobile_texts + 1),
2259 GFP_KERNEL);
2260 if (t == NULL)
2261 continue;
2262
2263 /* ...store the new entry... */
2264 t[wm8904->num_retune_mobile_texts] =
2265 pdata->retune_mobile_cfgs[i].name;
2266
2267 /* ...and remember the new version. */
2268 wm8904->num_retune_mobile_texts++;
2269 wm8904->retune_mobile_texts = t;
2270 }
2271
2272 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2273 wm8904->num_retune_mobile_texts);
2274
2275 wm8904->retune_mobile_enum.max = wm8904->num_retune_mobile_texts;
2276 wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts;
2277
2278 ret = snd_soc_add_controls(&wm8904->codec, &control, 1);
2279 if (ret != 0)
2280 dev_err(wm8904->codec.dev,
2281 "Failed to add ReTune Mobile control: %d\n", ret);
2282 }
2283
2284 static void wm8904_handle_pdata(struct wm8904_priv *wm8904)
2285 {
2286 struct snd_soc_codec *codec = &wm8904->codec;
2287 struct wm8904_pdata *pdata = wm8904->pdata;
2288 int ret, i;
2289
2290 if (!pdata) {
2291 snd_soc_add_controls(&wm8904->codec, wm8904_eq_controls,
2292 ARRAY_SIZE(wm8904_eq_controls));
2293 return;
2294 }
2295
2296 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2297
2298 if (pdata->num_drc_cfgs) {
2299 struct snd_kcontrol_new control =
2300 SOC_ENUM_EXT("DRC Mode", wm8904->drc_enum,
2301 wm8904_get_drc_enum, wm8904_put_drc_enum);
2302
2303 /* We need an array of texts for the enum API */
2304 wm8904->drc_texts = kmalloc(sizeof(char *)
2305 * pdata->num_drc_cfgs, GFP_KERNEL);
2306 if (!wm8904->drc_texts) {
2307 dev_err(wm8904->codec.dev,
2308 "Failed to allocate %d DRC config texts\n",
2309 pdata->num_drc_cfgs);
2310 return;
2311 }
2312
2313 for (i = 0; i < pdata->num_drc_cfgs; i++)
2314 wm8904->drc_texts[i] = pdata->drc_cfgs[i].name;
2315
2316 wm8904->drc_enum.max = pdata->num_drc_cfgs;
2317 wm8904->drc_enum.texts = wm8904->drc_texts;
2318
2319 ret = snd_soc_add_controls(&wm8904->codec, &control, 1);
2320 if (ret != 0)
2321 dev_err(wm8904->codec.dev,
2322 "Failed to add DRC mode control: %d\n", ret);
2323
2324 wm8904_set_drc(codec);
2325 }
2326
2327 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2328 pdata->num_retune_mobile_cfgs);
2329
2330 if (pdata->num_retune_mobile_cfgs)
2331 wm8904_handle_retune_mobile_pdata(wm8904);
2332 else
2333 snd_soc_add_controls(&wm8904->codec, wm8904_eq_controls,
2334 ARRAY_SIZE(wm8904_eq_controls));
2335 }
2336
2337 static int wm8904_probe(struct platform_device *pdev)
2338 {
2339 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2340 struct snd_soc_codec *codec;
2341 int ret = 0;
2342
2343 if (wm8904_codec == NULL) {
2344 dev_err(&pdev->dev, "Codec device not registered\n");
2345 return -ENODEV;
2346 }
2347
2348 socdev->card->codec = wm8904_codec;
2349 codec = wm8904_codec;
2350
2351 /* register pcms */
2352 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
2353 if (ret < 0) {
2354 dev_err(codec->dev, "failed to create pcms: %d\n", ret);
2355 goto pcm_err;
2356 }
2357
2358 wm8904_handle_pdata(codec->private_data);
2359
2360 wm8904_add_widgets(codec);
2361
2362 return ret;
2363
2364 pcm_err:
2365 return ret;
2366 }
2367
2368 static int wm8904_remove(struct platform_device *pdev)
2369 {
2370 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2371
2372 snd_soc_free_pcms(socdev);
2373 snd_soc_dapm_free(socdev);
2374
2375 return 0;
2376 }
2377
2378 struct snd_soc_codec_device soc_codec_dev_wm8904 = {
2379 .probe = wm8904_probe,
2380 .remove = wm8904_remove,
2381 .suspend = wm8904_suspend,
2382 .resume = wm8904_resume,
2383 };
2384 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8904);
2385
2386 static int wm8904_register(struct wm8904_priv *wm8904,
2387 enum snd_soc_control_type control)
2388 {
2389 int ret;
2390 struct snd_soc_codec *codec = &wm8904->codec;
2391 int i;
2392
2393 if (wm8904_codec) {
2394 dev_err(codec->dev, "Another WM8904 is registered\n");
2395 return -EINVAL;
2396 }
2397
2398 mutex_init(&codec->mutex);
2399 INIT_LIST_HEAD(&codec->dapm_widgets);
2400 INIT_LIST_HEAD(&codec->dapm_paths);
2401
2402 codec->private_data = wm8904;
2403 codec->name = "WM8904";
2404 codec->owner = THIS_MODULE;
2405 codec->bias_level = SND_SOC_BIAS_OFF;
2406 codec->set_bias_level = wm8904_set_bias_level;
2407 codec->dai = &wm8904_dai;
2408 codec->num_dai = 1;
2409 codec->reg_cache_size = WM8904_MAX_REGISTER;
2410 codec->reg_cache = &wm8904->reg_cache;
2411 codec->volatile_register = wm8904_volatile_register;
2412 codec->cache_sync = 1;
2413 codec->idle_bias_off = 1;
2414
2415 memcpy(codec->reg_cache, wm8904_reg, sizeof(wm8904_reg));
2416
2417 ret = snd_soc_codec_set_cache_io(codec, 8, 16, control);
2418 if (ret != 0) {
2419 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2420 goto err;
2421 }
2422
2423 for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++)
2424 wm8904->supplies[i].supply = wm8904_supply_names[i];
2425
2426 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8904->supplies),
2427 wm8904->supplies);
2428 if (ret != 0) {
2429 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
2430 goto err;
2431 }
2432
2433 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
2434 wm8904->supplies);
2435 if (ret != 0) {
2436 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
2437 goto err_get;
2438 }
2439
2440 ret = snd_soc_read(codec, WM8904_SW_RESET_AND_ID);
2441 if (ret < 0) {
2442 dev_err(codec->dev, "Failed to read ID register\n");
2443 goto err_enable;
2444 }
2445 if (ret != wm8904_reg[WM8904_SW_RESET_AND_ID]) {
2446 dev_err(codec->dev, "Device is not a WM8904, ID is %x\n", ret);
2447 ret = -EINVAL;
2448 goto err_enable;
2449 }
2450
2451 ret = snd_soc_read(codec, WM8904_REVISION);
2452 if (ret < 0) {
2453 dev_err(codec->dev, "Failed to read device revision: %d\n",
2454 ret);
2455 goto err_enable;
2456 }
2457 dev_info(codec->dev, "revision %c\n", ret + 'A');
2458
2459 ret = wm8904_reset(codec);
2460 if (ret < 0) {
2461 dev_err(codec->dev, "Failed to issue reset\n");
2462 goto err_enable;
2463 }
2464
2465 wm8904_dai.dev = codec->dev;
2466
2467 /* Change some default settings - latch VU and enable ZC */
2468 wm8904->reg_cache[WM8904_ADC_DIGITAL_VOLUME_LEFT] |= WM8904_ADC_VU;
2469 wm8904->reg_cache[WM8904_ADC_DIGITAL_VOLUME_RIGHT] |= WM8904_ADC_VU;
2470 wm8904->reg_cache[WM8904_DAC_DIGITAL_VOLUME_LEFT] |= WM8904_DAC_VU;
2471 wm8904->reg_cache[WM8904_DAC_DIGITAL_VOLUME_RIGHT] |= WM8904_DAC_VU;
2472 wm8904->reg_cache[WM8904_ANALOGUE_OUT1_LEFT] |= WM8904_HPOUT_VU |
2473 WM8904_HPOUTLZC;
2474 wm8904->reg_cache[WM8904_ANALOGUE_OUT1_RIGHT] |= WM8904_HPOUT_VU |
2475 WM8904_HPOUTRZC;
2476 wm8904->reg_cache[WM8904_ANALOGUE_OUT2_LEFT] |= WM8904_LINEOUT_VU |
2477 WM8904_LINEOUTLZC;
2478 wm8904->reg_cache[WM8904_ANALOGUE_OUT2_RIGHT] |= WM8904_LINEOUT_VU |
2479 WM8904_LINEOUTRZC;
2480 wm8904->reg_cache[WM8904_CLOCK_RATES_0] &= ~WM8904_SR_MODE;
2481
2482 /* Set Class W by default - this will be managed by the Class
2483 * G widget at runtime where bypass paths are available.
2484 */
2485 wm8904->reg_cache[WM8904_CLASS_W_0] |= WM8904_CP_DYN_PWR;
2486
2487 /* Use normal bias source */
2488 wm8904->reg_cache[WM8904_BIAS_CONTROL_0] &= ~WM8904_POBCTRL;
2489
2490 wm8904_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2491
2492 /* Bias level configuration will have done an extra enable */
2493 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
2494
2495 wm8904_codec = codec;
2496
2497 ret = snd_soc_register_codec(codec);
2498 if (ret != 0) {
2499 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
2500 return ret;
2501 }
2502
2503 ret = snd_soc_register_dai(&wm8904_dai);
2504 if (ret != 0) {
2505 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
2506 snd_soc_unregister_codec(codec);
2507 return ret;
2508 }
2509
2510 return 0;
2511
2512 err_enable:
2513 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
2514 err_get:
2515 regulator_bulk_free(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
2516 err:
2517 kfree(wm8904);
2518 return ret;
2519 }
2520
2521 static void wm8904_unregister(struct wm8904_priv *wm8904)
2522 {
2523 wm8904_set_bias_level(&wm8904->codec, SND_SOC_BIAS_OFF);
2524 regulator_bulk_free(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
2525 snd_soc_unregister_dai(&wm8904_dai);
2526 snd_soc_unregister_codec(&wm8904->codec);
2527 kfree(wm8904);
2528 wm8904_codec = NULL;
2529 }
2530
2531 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2532 static __devinit int wm8904_i2c_probe(struct i2c_client *i2c,
2533 const struct i2c_device_id *id)
2534 {
2535 struct wm8904_priv *wm8904;
2536 struct snd_soc_codec *codec;
2537
2538 wm8904 = kzalloc(sizeof(struct wm8904_priv), GFP_KERNEL);
2539 if (wm8904 == NULL)
2540 return -ENOMEM;
2541
2542 codec = &wm8904->codec;
2543 codec->hw_write = (hw_write_t)i2c_master_send;
2544
2545 i2c_set_clientdata(i2c, wm8904);
2546 codec->control_data = i2c;
2547 wm8904->pdata = i2c->dev.platform_data;
2548
2549 codec->dev = &i2c->dev;
2550
2551 return wm8904_register(wm8904, SND_SOC_I2C);
2552 }
2553
2554 static __devexit int wm8904_i2c_remove(struct i2c_client *client)
2555 {
2556 struct wm8904_priv *wm8904 = i2c_get_clientdata(client);
2557 wm8904_unregister(wm8904);
2558 return 0;
2559 }
2560
2561 static const struct i2c_device_id wm8904_i2c_id[] = {
2562 { "wm8904", 0 },
2563 { }
2564 };
2565 MODULE_DEVICE_TABLE(i2c, wm8904_i2c_id);
2566
2567 static struct i2c_driver wm8904_i2c_driver = {
2568 .driver = {
2569 .name = "WM8904",
2570 .owner = THIS_MODULE,
2571 },
2572 .probe = wm8904_i2c_probe,
2573 .remove = __devexit_p(wm8904_i2c_remove),
2574 .id_table = wm8904_i2c_id,
2575 };
2576 #endif
2577
2578 static int __init wm8904_modinit(void)
2579 {
2580 int ret;
2581 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2582 ret = i2c_add_driver(&wm8904_i2c_driver);
2583 if (ret != 0) {
2584 printk(KERN_ERR "Failed to register WM8904 I2C driver: %d\n",
2585 ret);
2586 }
2587 #endif
2588 return 0;
2589 }
2590 module_init(wm8904_modinit);
2591
2592 static void __exit wm8904_exit(void)
2593 {
2594 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2595 i2c_del_driver(&wm8904_i2c_driver);
2596 #endif
2597 }
2598 module_exit(wm8904_exit);
2599
2600 MODULE_DESCRIPTION("ASoC WM8904 driver");
2601 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2602 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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