2 * wm8904.c -- WM8904 ALSA SoC Audio driver
4 * Copyright 2009 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
19 #include <linux/i2c.h>
20 #include <linux/regmap.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/slab.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29 #include <sound/wm8904.h>
38 #define WM8904_NUM_DCS_CHANNELS 4
40 #define WM8904_NUM_SUPPLIES 5
41 static const char *wm8904_supply_names
[WM8904_NUM_SUPPLIES
] = {
49 /* codec private data */
51 struct regmap
*regmap
;
53 enum wm8904_type devtype
;
55 struct regulator_bulk_data supplies
[WM8904_NUM_SUPPLIES
];
57 struct wm8904_pdata
*pdata
;
61 /* Platform provided DRC configuration */
62 const char **drc_texts
;
64 struct soc_enum drc_enum
;
66 /* Platform provided ReTune mobile configuration */
67 int num_retune_mobile_texts
;
68 const char **retune_mobile_texts
;
69 int retune_mobile_cfg
;
70 struct soc_enum retune_mobile_enum
;
77 /* Clocking configuration */
78 unsigned int mclk_rate
;
80 unsigned int sysclk_rate
;
87 /* DC servo configuration - cached offset values */
88 int dcs_state
[WM8904_NUM_DCS_CHANNELS
];
91 static const struct reg_default wm8904_reg_defaults
[] = {
92 { 4, 0x0018 }, /* R4 - Bias Control 0 */
93 { 5, 0x0000 }, /* R5 - VMID Control 0 */
94 { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */
95 { 7, 0x0000 }, /* R7 - Mic Bias Control 1 */
96 { 8, 0x0001 }, /* R8 - Analogue DAC 0 */
97 { 9, 0x9696 }, /* R9 - mic Filter Control */
98 { 10, 0x0001 }, /* R10 - Analogue ADC 0 */
99 { 12, 0x0000 }, /* R12 - Power Management 0 */
100 { 14, 0x0000 }, /* R14 - Power Management 2 */
101 { 15, 0x0000 }, /* R15 - Power Management 3 */
102 { 18, 0x0000 }, /* R18 - Power Management 6 */
103 { 19, 0x945E }, /* R20 - Clock Rates 0 */
104 { 21, 0x0C05 }, /* R21 - Clock Rates 1 */
105 { 22, 0x0006 }, /* R22 - Clock Rates 2 */
106 { 24, 0x0050 }, /* R24 - Audio Interface 0 */
107 { 25, 0x000A }, /* R25 - Audio Interface 1 */
108 { 26, 0x00E4 }, /* R26 - Audio Interface 2 */
109 { 27, 0x0040 }, /* R27 - Audio Interface 3 */
110 { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */
111 { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */
112 { 32, 0x0000 }, /* R32 - DAC Digital 0 */
113 { 33, 0x0008 }, /* R33 - DAC Digital 1 */
114 { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */
115 { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */
116 { 38, 0x0010 }, /* R38 - ADC Digital 0 */
117 { 39, 0x0000 }, /* R39 - Digital Microphone 0 */
118 { 40, 0x01AF }, /* R40 - DRC 0 */
119 { 41, 0x3248 }, /* R41 - DRC 1 */
120 { 42, 0x0000 }, /* R42 - DRC 2 */
121 { 43, 0x0000 }, /* R43 - DRC 3 */
122 { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */
123 { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */
124 { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */
125 { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */
126 { 57, 0x002D }, /* R57 - Analogue OUT1 Left */
127 { 58, 0x002D }, /* R58 - Analogue OUT1 Right */
128 { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */
129 { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */
130 { 61, 0x0000 }, /* R61 - Analogue OUT12 ZC */
131 { 67, 0x0000 }, /* R67 - DC Servo 0 */
132 { 69, 0xAAAA }, /* R69 - DC Servo 2 */
133 { 71, 0xAAAA }, /* R71 - DC Servo 4 */
134 { 72, 0xAAAA }, /* R72 - DC Servo 5 */
135 { 90, 0x0000 }, /* R90 - Analogue HP 0 */
136 { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */
137 { 98, 0x0000 }, /* R98 - Charge Pump 0 */
138 { 104, 0x0004 }, /* R104 - Class W 0 */
139 { 108, 0x0000 }, /* R108 - Write Sequencer 0 */
140 { 109, 0x0000 }, /* R109 - Write Sequencer 1 */
141 { 110, 0x0000 }, /* R110 - Write Sequencer 2 */
142 { 111, 0x0000 }, /* R111 - Write Sequencer 3 */
143 { 112, 0x0000 }, /* R112 - Write Sequencer 4 */
144 { 116, 0x0000 }, /* R116 - FLL Control 1 */
145 { 117, 0x0007 }, /* R117 - FLL Control 2 */
146 { 118, 0x0000 }, /* R118 - FLL Control 3 */
147 { 119, 0x2EE0 }, /* R119 - FLL Control 4 */
148 { 120, 0x0004 }, /* R120 - FLL Control 5 */
149 { 121, 0x0014 }, /* R121 - GPIO Control 1 */
150 { 122, 0x0010 }, /* R122 - GPIO Control 2 */
151 { 123, 0x0010 }, /* R123 - GPIO Control 3 */
152 { 124, 0x0000 }, /* R124 - GPIO Control 4 */
153 { 126, 0x0000 }, /* R126 - Digital Pulls */
154 { 128, 0xFFFF }, /* R128 - Interrupt Status Mask */
155 { 129, 0x0000 }, /* R129 - Interrupt Polarity */
156 { 130, 0x0000 }, /* R130 - Interrupt Debounce */
157 { 134, 0x0000 }, /* R134 - EQ1 */
158 { 135, 0x000C }, /* R135 - EQ2 */
159 { 136, 0x000C }, /* R136 - EQ3 */
160 { 137, 0x000C }, /* R137 - EQ4 */
161 { 138, 0x000C }, /* R138 - EQ5 */
162 { 139, 0x000C }, /* R139 - EQ6 */
163 { 140, 0x0FCA }, /* R140 - EQ7 */
164 { 141, 0x0400 }, /* R141 - EQ8 */
165 { 142, 0x00D8 }, /* R142 - EQ9 */
166 { 143, 0x1EB5 }, /* R143 - EQ10 */
167 { 144, 0xF145 }, /* R144 - EQ11 */
168 { 145, 0x0B75 }, /* R145 - EQ12 */
169 { 146, 0x01C5 }, /* R146 - EQ13 */
170 { 147, 0x1C58 }, /* R147 - EQ14 */
171 { 148, 0xF373 }, /* R148 - EQ15 */
172 { 149, 0x0A54 }, /* R149 - EQ16 */
173 { 150, 0x0558 }, /* R150 - EQ17 */
174 { 151, 0x168E }, /* R151 - EQ18 */
175 { 152, 0xF829 }, /* R152 - EQ19 */
176 { 153, 0x07AD }, /* R153 - EQ20 */
177 { 154, 0x1103 }, /* R154 - EQ21 */
178 { 155, 0x0564 }, /* R155 - EQ22 */
179 { 156, 0x0559 }, /* R156 - EQ23 */
180 { 157, 0x4000 }, /* R157 - EQ24 */
181 { 161, 0x0000 }, /* R161 - Control Interface Test 1 */
182 { 204, 0x0000 }, /* R204 - Analogue Output Bias 0 */
183 { 247, 0x0000 }, /* R247 - FLL NCO Test 0 */
184 { 248, 0x0019 }, /* R248 - FLL NCO Test 1 */
187 static bool wm8904_volatile_register(struct device
*dev
, unsigned int reg
)
190 case WM8904_SW_RESET_AND_ID
:
191 case WM8904_REVISION
:
192 case WM8904_DC_SERVO_1
:
193 case WM8904_DC_SERVO_6
:
194 case WM8904_DC_SERVO_7
:
195 case WM8904_DC_SERVO_8
:
196 case WM8904_DC_SERVO_9
:
197 case WM8904_DC_SERVO_READBACK_0
:
198 case WM8904_INTERRUPT_STATUS
:
205 static bool wm8904_readable_register(struct device
*dev
, unsigned int reg
)
208 case WM8904_SW_RESET_AND_ID
:
209 case WM8904_REVISION
:
210 case WM8904_BIAS_CONTROL_0
:
211 case WM8904_VMID_CONTROL_0
:
212 case WM8904_MIC_BIAS_CONTROL_0
:
213 case WM8904_MIC_BIAS_CONTROL_1
:
214 case WM8904_ANALOGUE_DAC_0
:
215 case WM8904_MIC_FILTER_CONTROL
:
216 case WM8904_ANALOGUE_ADC_0
:
217 case WM8904_POWER_MANAGEMENT_0
:
218 case WM8904_POWER_MANAGEMENT_2
:
219 case WM8904_POWER_MANAGEMENT_3
:
220 case WM8904_POWER_MANAGEMENT_6
:
221 case WM8904_CLOCK_RATES_0
:
222 case WM8904_CLOCK_RATES_1
:
223 case WM8904_CLOCK_RATES_2
:
224 case WM8904_AUDIO_INTERFACE_0
:
225 case WM8904_AUDIO_INTERFACE_1
:
226 case WM8904_AUDIO_INTERFACE_2
:
227 case WM8904_AUDIO_INTERFACE_3
:
228 case WM8904_DAC_DIGITAL_VOLUME_LEFT
:
229 case WM8904_DAC_DIGITAL_VOLUME_RIGHT
:
230 case WM8904_DAC_DIGITAL_0
:
231 case WM8904_DAC_DIGITAL_1
:
232 case WM8904_ADC_DIGITAL_VOLUME_LEFT
:
233 case WM8904_ADC_DIGITAL_VOLUME_RIGHT
:
234 case WM8904_ADC_DIGITAL_0
:
235 case WM8904_DIGITAL_MICROPHONE_0
:
240 case WM8904_ANALOGUE_LEFT_INPUT_0
:
241 case WM8904_ANALOGUE_RIGHT_INPUT_0
:
242 case WM8904_ANALOGUE_LEFT_INPUT_1
:
243 case WM8904_ANALOGUE_RIGHT_INPUT_1
:
244 case WM8904_ANALOGUE_OUT1_LEFT
:
245 case WM8904_ANALOGUE_OUT1_RIGHT
:
246 case WM8904_ANALOGUE_OUT2_LEFT
:
247 case WM8904_ANALOGUE_OUT2_RIGHT
:
248 case WM8904_ANALOGUE_OUT12_ZC
:
249 case WM8904_DC_SERVO_0
:
250 case WM8904_DC_SERVO_1
:
251 case WM8904_DC_SERVO_2
:
252 case WM8904_DC_SERVO_4
:
253 case WM8904_DC_SERVO_5
:
254 case WM8904_DC_SERVO_6
:
255 case WM8904_DC_SERVO_7
:
256 case WM8904_DC_SERVO_8
:
257 case WM8904_DC_SERVO_9
:
258 case WM8904_DC_SERVO_READBACK_0
:
259 case WM8904_ANALOGUE_HP_0
:
260 case WM8904_ANALOGUE_LINEOUT_0
:
261 case WM8904_CHARGE_PUMP_0
:
262 case WM8904_CLASS_W_0
:
263 case WM8904_WRITE_SEQUENCER_0
:
264 case WM8904_WRITE_SEQUENCER_1
:
265 case WM8904_WRITE_SEQUENCER_2
:
266 case WM8904_WRITE_SEQUENCER_3
:
267 case WM8904_WRITE_SEQUENCER_4
:
268 case WM8904_FLL_CONTROL_1
:
269 case WM8904_FLL_CONTROL_2
:
270 case WM8904_FLL_CONTROL_3
:
271 case WM8904_FLL_CONTROL_4
:
272 case WM8904_FLL_CONTROL_5
:
273 case WM8904_GPIO_CONTROL_1
:
274 case WM8904_GPIO_CONTROL_2
:
275 case WM8904_GPIO_CONTROL_3
:
276 case WM8904_GPIO_CONTROL_4
:
277 case WM8904_DIGITAL_PULLS
:
278 case WM8904_INTERRUPT_STATUS
:
279 case WM8904_INTERRUPT_STATUS_MASK
:
280 case WM8904_INTERRUPT_POLARITY
:
281 case WM8904_INTERRUPT_DEBOUNCE
:
306 case WM8904_CONTROL_INTERFACE_TEST_1
:
307 case WM8904_ANALOGUE_OUTPUT_BIAS_0
:
308 case WM8904_FLL_NCO_TEST_0
:
309 case WM8904_FLL_NCO_TEST_1
:
316 static int wm8904_reset(struct snd_soc_codec
*codec
)
318 return snd_soc_write(codec
, WM8904_SW_RESET_AND_ID
, 0);
321 static int wm8904_configure_clocking(struct snd_soc_codec
*codec
)
323 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
324 unsigned int clock0
, clock2
, rate
;
326 /* Gate the clock while we're updating to avoid misclocking */
327 clock2
= snd_soc_read(codec
, WM8904_CLOCK_RATES_2
);
328 snd_soc_update_bits(codec
, WM8904_CLOCK_RATES_2
,
329 WM8904_SYSCLK_SRC
, 0);
331 /* This should be done on init() for bypass paths */
332 switch (wm8904
->sysclk_src
) {
333 case WM8904_CLK_MCLK
:
334 dev_dbg(codec
->dev
, "Using %dHz MCLK\n", wm8904
->mclk_rate
);
336 clock2
&= ~WM8904_SYSCLK_SRC
;
337 rate
= wm8904
->mclk_rate
;
339 /* Ensure the FLL is stopped */
340 snd_soc_update_bits(codec
, WM8904_FLL_CONTROL_1
,
341 WM8904_FLL_OSC_ENA
| WM8904_FLL_ENA
, 0);
345 dev_dbg(codec
->dev
, "Using %dHz FLL clock\n",
348 clock2
|= WM8904_SYSCLK_SRC
;
349 rate
= wm8904
->fll_fout
;
353 dev_err(codec
->dev
, "System clock not configured\n");
357 /* SYSCLK shouldn't be over 13.5MHz */
358 if (rate
> 13500000) {
359 clock0
= WM8904_MCLK_DIV
;
360 wm8904
->sysclk_rate
= rate
/ 2;
363 wm8904
->sysclk_rate
= rate
;
366 snd_soc_update_bits(codec
, WM8904_CLOCK_RATES_0
, WM8904_MCLK_DIV
,
369 snd_soc_update_bits(codec
, WM8904_CLOCK_RATES_2
,
370 WM8904_CLK_SYS_ENA
| WM8904_SYSCLK_SRC
, clock2
);
372 dev_dbg(codec
->dev
, "CLK_SYS is %dHz\n", wm8904
->sysclk_rate
);
377 static void wm8904_set_drc(struct snd_soc_codec
*codec
)
379 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
380 struct wm8904_pdata
*pdata
= wm8904
->pdata
;
383 /* Save any enables; the configuration should clear them. */
384 save
= snd_soc_read(codec
, WM8904_DRC_0
);
386 for (i
= 0; i
< WM8904_DRC_REGS
; i
++)
387 snd_soc_update_bits(codec
, WM8904_DRC_0
+ i
, 0xffff,
388 pdata
->drc_cfgs
[wm8904
->drc_cfg
].regs
[i
]);
390 /* Reenable the DRC */
391 snd_soc_update_bits(codec
, WM8904_DRC_0
,
392 WM8904_DRC_ENA
| WM8904_DRC_DAC_PATH
, save
);
395 static int wm8904_put_drc_enum(struct snd_kcontrol
*kcontrol
,
396 struct snd_ctl_elem_value
*ucontrol
)
398 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
399 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
400 struct wm8904_pdata
*pdata
= wm8904
->pdata
;
401 int value
= ucontrol
->value
.integer
.value
[0];
403 if (value
>= pdata
->num_drc_cfgs
)
406 wm8904
->drc_cfg
= value
;
408 wm8904_set_drc(codec
);
413 static int wm8904_get_drc_enum(struct snd_kcontrol
*kcontrol
,
414 struct snd_ctl_elem_value
*ucontrol
)
416 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
417 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
419 ucontrol
->value
.enumerated
.item
[0] = wm8904
->drc_cfg
;
424 static void wm8904_set_retune_mobile(struct snd_soc_codec
*codec
)
426 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
427 struct wm8904_pdata
*pdata
= wm8904
->pdata
;
428 int best
, best_val
, save
, i
, cfg
;
430 if (!pdata
|| !wm8904
->num_retune_mobile_texts
)
433 /* Find the version of the currently selected configuration
434 * with the nearest sample rate. */
435 cfg
= wm8904
->retune_mobile_cfg
;
438 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
439 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
440 wm8904
->retune_mobile_texts
[cfg
]) == 0 &&
441 abs(pdata
->retune_mobile_cfgs
[i
].rate
442 - wm8904
->fs
) < best_val
) {
444 best_val
= abs(pdata
->retune_mobile_cfgs
[i
].rate
449 dev_dbg(codec
->dev
, "ReTune Mobile %s/%dHz for %dHz sample rate\n",
450 pdata
->retune_mobile_cfgs
[best
].name
,
451 pdata
->retune_mobile_cfgs
[best
].rate
,
454 /* The EQ will be disabled while reconfiguring it, remember the
455 * current configuration.
457 save
= snd_soc_read(codec
, WM8904_EQ1
);
459 for (i
= 0; i
< WM8904_EQ_REGS
; i
++)
460 snd_soc_update_bits(codec
, WM8904_EQ1
+ i
, 0xffff,
461 pdata
->retune_mobile_cfgs
[best
].regs
[i
]);
463 snd_soc_update_bits(codec
, WM8904_EQ1
, WM8904_EQ_ENA
, save
);
466 static int wm8904_put_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
467 struct snd_ctl_elem_value
*ucontrol
)
469 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
470 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
471 struct wm8904_pdata
*pdata
= wm8904
->pdata
;
472 int value
= ucontrol
->value
.integer
.value
[0];
474 if (value
>= pdata
->num_retune_mobile_cfgs
)
477 wm8904
->retune_mobile_cfg
= value
;
479 wm8904_set_retune_mobile(codec
);
484 static int wm8904_get_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
485 struct snd_ctl_elem_value
*ucontrol
)
487 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
488 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
490 ucontrol
->value
.enumerated
.item
[0] = wm8904
->retune_mobile_cfg
;
495 static int deemph_settings
[] = { 0, 32000, 44100, 48000 };
497 static int wm8904_set_deemph(struct snd_soc_codec
*codec
)
499 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
502 /* If we're using deemphasis select the nearest available sample
505 if (wm8904
->deemph
) {
507 for (i
= 2; i
< ARRAY_SIZE(deemph_settings
); i
++) {
508 if (abs(deemph_settings
[i
] - wm8904
->fs
) <
509 abs(deemph_settings
[best
] - wm8904
->fs
))
513 val
= best
<< WM8904_DEEMPH_SHIFT
;
518 dev_dbg(codec
->dev
, "Set deemphasis %d\n", val
);
520 return snd_soc_update_bits(codec
, WM8904_DAC_DIGITAL_1
,
521 WM8904_DEEMPH_MASK
, val
);
524 static int wm8904_get_deemph(struct snd_kcontrol
*kcontrol
,
525 struct snd_ctl_elem_value
*ucontrol
)
527 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
528 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
530 ucontrol
->value
.enumerated
.item
[0] = wm8904
->deemph
;
534 static int wm8904_put_deemph(struct snd_kcontrol
*kcontrol
,
535 struct snd_ctl_elem_value
*ucontrol
)
537 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
538 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
539 int deemph
= ucontrol
->value
.enumerated
.item
[0];
544 wm8904
->deemph
= deemph
;
546 return wm8904_set_deemph(codec
);
549 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv
, 0, 600, 0);
550 static const DECLARE_TLV_DB_SCALE(digital_tlv
, -7200, 75, 1);
551 static const DECLARE_TLV_DB_SCALE(out_tlv
, -5700, 100, 0);
552 static const DECLARE_TLV_DB_SCALE(sidetone_tlv
, -3600, 300, 0);
553 static const DECLARE_TLV_DB_SCALE(eq_tlv
, -1200, 100, 0);
555 static const char *input_mode_text
[] = {
556 "Single-Ended", "Differential Line", "Differential Mic"
559 static const struct soc_enum lin_mode
=
560 SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1
, 0, 3, input_mode_text
);
562 static const struct soc_enum rin_mode
=
563 SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1
, 0, 3, input_mode_text
);
565 static const char *hpf_mode_text
[] = {
566 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
569 static const struct soc_enum hpf_mode
=
570 SOC_ENUM_SINGLE(WM8904_ADC_DIGITAL_0
, 5, 4, hpf_mode_text
);
572 static const struct snd_kcontrol_new wm8904_adc_snd_controls
[] = {
573 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8904_ADC_DIGITAL_VOLUME_LEFT
,
574 WM8904_ADC_DIGITAL_VOLUME_RIGHT
, 1, 119, 0, digital_tlv
),
576 SOC_ENUM("Left Caputure Mode", lin_mode
),
577 SOC_ENUM("Right Capture Mode", rin_mode
),
579 /* No TLV since it depends on mode */
580 SOC_DOUBLE_R("Capture Volume", WM8904_ANALOGUE_LEFT_INPUT_0
,
581 WM8904_ANALOGUE_RIGHT_INPUT_0
, 0, 31, 0),
582 SOC_DOUBLE_R("Capture Switch", WM8904_ANALOGUE_LEFT_INPUT_0
,
583 WM8904_ANALOGUE_RIGHT_INPUT_0
, 7, 1, 1),
585 SOC_SINGLE("High Pass Filter Switch", WM8904_ADC_DIGITAL_0
, 4, 1, 0),
586 SOC_ENUM("High Pass Filter Mode", hpf_mode
),
588 SOC_SINGLE("ADC 128x OSR Switch", WM8904_ANALOGUE_ADC_0
, 0, 1, 0),
591 static const char *drc_path_text
[] = {
595 static const struct soc_enum drc_path
=
596 SOC_ENUM_SINGLE(WM8904_DRC_0
, 14, 2, drc_path_text
);
598 static const struct snd_kcontrol_new wm8904_dac_snd_controls
[] = {
599 SOC_SINGLE_TLV("Digital Playback Boost Volume",
600 WM8904_AUDIO_INTERFACE_0
, 9, 3, 0, dac_boost_tlv
),
601 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8904_DAC_DIGITAL_VOLUME_LEFT
,
602 WM8904_DAC_DIGITAL_VOLUME_RIGHT
, 1, 96, 0, digital_tlv
),
604 SOC_DOUBLE_R_TLV("Headphone Volume", WM8904_ANALOGUE_OUT1_LEFT
,
605 WM8904_ANALOGUE_OUT1_RIGHT
, 0, 63, 0, out_tlv
),
606 SOC_DOUBLE_R("Headphone Switch", WM8904_ANALOGUE_OUT1_LEFT
,
607 WM8904_ANALOGUE_OUT1_RIGHT
, 8, 1, 1),
608 SOC_DOUBLE_R("Headphone ZC Switch", WM8904_ANALOGUE_OUT1_LEFT
,
609 WM8904_ANALOGUE_OUT1_RIGHT
, 6, 1, 0),
611 SOC_DOUBLE_R_TLV("Line Output Volume", WM8904_ANALOGUE_OUT2_LEFT
,
612 WM8904_ANALOGUE_OUT2_RIGHT
, 0, 63, 0, out_tlv
),
613 SOC_DOUBLE_R("Line Output Switch", WM8904_ANALOGUE_OUT2_LEFT
,
614 WM8904_ANALOGUE_OUT2_RIGHT
, 8, 1, 1),
615 SOC_DOUBLE_R("Line Output ZC Switch", WM8904_ANALOGUE_OUT2_LEFT
,
616 WM8904_ANALOGUE_OUT2_RIGHT
, 6, 1, 0),
618 SOC_SINGLE("EQ Switch", WM8904_EQ1
, 0, 1, 0),
619 SOC_SINGLE("DRC Switch", WM8904_DRC_0
, 15, 1, 0),
620 SOC_ENUM("DRC Path", drc_path
),
621 SOC_SINGLE("DAC OSRx2 Switch", WM8904_DAC_DIGITAL_1
, 6, 1, 0),
622 SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
623 wm8904_get_deemph
, wm8904_put_deemph
),
626 static const struct snd_kcontrol_new wm8904_snd_controls
[] = {
627 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8904_DAC_DIGITAL_0
, 4, 8, 15, 0,
631 static const struct snd_kcontrol_new wm8904_eq_controls
[] = {
632 SOC_SINGLE_TLV("EQ1 Volume", WM8904_EQ2
, 0, 24, 0, eq_tlv
),
633 SOC_SINGLE_TLV("EQ2 Volume", WM8904_EQ3
, 0, 24, 0, eq_tlv
),
634 SOC_SINGLE_TLV("EQ3 Volume", WM8904_EQ4
, 0, 24, 0, eq_tlv
),
635 SOC_SINGLE_TLV("EQ4 Volume", WM8904_EQ5
, 0, 24, 0, eq_tlv
),
636 SOC_SINGLE_TLV("EQ5 Volume", WM8904_EQ6
, 0, 24, 0, eq_tlv
),
639 static int cp_event(struct snd_soc_dapm_widget
*w
,
640 struct snd_kcontrol
*kcontrol
, int event
)
642 BUG_ON(event
!= SND_SOC_DAPM_POST_PMU
);
644 /* Maximum startup time */
650 static int sysclk_event(struct snd_soc_dapm_widget
*w
,
651 struct snd_kcontrol
*kcontrol
, int event
)
653 struct snd_soc_codec
*codec
= w
->codec
;
654 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
657 case SND_SOC_DAPM_PRE_PMU
:
658 /* If we're using the FLL then we only start it when
659 * required; we assume that the configuration has been
660 * done previously and all we need to do is kick it
663 switch (wm8904
->sysclk_src
) {
665 snd_soc_update_bits(codec
, WM8904_FLL_CONTROL_1
,
669 snd_soc_update_bits(codec
, WM8904_FLL_CONTROL_1
,
679 case SND_SOC_DAPM_POST_PMD
:
680 snd_soc_update_bits(codec
, WM8904_FLL_CONTROL_1
,
681 WM8904_FLL_OSC_ENA
| WM8904_FLL_ENA
, 0);
688 static int out_pga_event(struct snd_soc_dapm_widget
*w
,
689 struct snd_kcontrol
*kcontrol
, int event
)
691 struct snd_soc_codec
*codec
= w
->codec
;
692 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
696 int dcs_l_reg
, dcs_r_reg
;
700 /* This code is shared between HP and LINEOUT; we do all our
701 * power management in stereo pairs to avoid latency issues so
702 * we reuse shift to identify which rather than strcmp() the
707 case WM8904_ANALOGUE_HP_0
:
708 pwr_reg
= WM8904_POWER_MANAGEMENT_2
;
709 dcs_mask
= WM8904_DCS_ENA_CHAN_0
| WM8904_DCS_ENA_CHAN_1
;
710 dcs_r_reg
= WM8904_DC_SERVO_8
;
711 dcs_l_reg
= WM8904_DC_SERVO_9
;
715 case WM8904_ANALOGUE_LINEOUT_0
:
716 pwr_reg
= WM8904_POWER_MANAGEMENT_3
;
717 dcs_mask
= WM8904_DCS_ENA_CHAN_2
| WM8904_DCS_ENA_CHAN_3
;
718 dcs_r_reg
= WM8904_DC_SERVO_6
;
719 dcs_l_reg
= WM8904_DC_SERVO_7
;
729 case SND_SOC_DAPM_PRE_PMU
:
730 /* Power on the PGAs */
731 snd_soc_update_bits(codec
, pwr_reg
,
732 WM8904_HPL_PGA_ENA
| WM8904_HPR_PGA_ENA
,
733 WM8904_HPL_PGA_ENA
| WM8904_HPR_PGA_ENA
);
735 /* Power on the amplifier */
736 snd_soc_update_bits(codec
, reg
,
737 WM8904_HPL_ENA
| WM8904_HPR_ENA
,
738 WM8904_HPL_ENA
| WM8904_HPR_ENA
);
741 /* Enable the first stage */
742 snd_soc_update_bits(codec
, reg
,
743 WM8904_HPL_ENA_DLY
| WM8904_HPR_ENA_DLY
,
744 WM8904_HPL_ENA_DLY
| WM8904_HPR_ENA_DLY
);
746 /* Power up the DC servo */
747 snd_soc_update_bits(codec
, WM8904_DC_SERVO_0
,
750 /* Either calibrate the DC servo or restore cached state
753 if (wm8904
->dcs_state
[dcs_l
] || wm8904
->dcs_state
[dcs_r
]) {
754 dev_dbg(codec
->dev
, "Restoring DC servo state\n");
756 snd_soc_write(codec
, dcs_l_reg
,
757 wm8904
->dcs_state
[dcs_l
]);
758 snd_soc_write(codec
, dcs_r_reg
,
759 wm8904
->dcs_state
[dcs_r
]);
761 snd_soc_write(codec
, WM8904_DC_SERVO_1
, dcs_mask
);
765 dev_dbg(codec
->dev
, "Calibrating DC servo\n");
767 snd_soc_write(codec
, WM8904_DC_SERVO_1
,
768 dcs_mask
<< WM8904_DCS_TRIG_STARTUP_0_SHIFT
);
773 /* Wait for DC servo to complete */
774 dcs_mask
<<= WM8904_DCS_CAL_COMPLETE_SHIFT
;
776 val
= snd_soc_read(codec
, WM8904_DC_SERVO_READBACK_0
);
777 if ((val
& dcs_mask
) == dcs_mask
)
783 if ((val
& dcs_mask
) != dcs_mask
)
784 dev_warn(codec
->dev
, "DC servo timed out\n");
786 dev_dbg(codec
->dev
, "DC servo ready\n");
788 /* Enable the output stage */
789 snd_soc_update_bits(codec
, reg
,
790 WM8904_HPL_ENA_OUTP
| WM8904_HPR_ENA_OUTP
,
791 WM8904_HPL_ENA_OUTP
| WM8904_HPR_ENA_OUTP
);
794 case SND_SOC_DAPM_POST_PMU
:
795 /* Unshort the output itself */
796 snd_soc_update_bits(codec
, reg
,
797 WM8904_HPL_RMV_SHORT
|
798 WM8904_HPR_RMV_SHORT
,
799 WM8904_HPL_RMV_SHORT
|
800 WM8904_HPR_RMV_SHORT
);
804 case SND_SOC_DAPM_PRE_PMD
:
805 /* Short the output */
806 snd_soc_update_bits(codec
, reg
,
807 WM8904_HPL_RMV_SHORT
|
808 WM8904_HPR_RMV_SHORT
, 0);
811 case SND_SOC_DAPM_POST_PMD
:
812 /* Cache the DC servo configuration; this will be
813 * invalidated if we change the configuration. */
814 wm8904
->dcs_state
[dcs_l
] = snd_soc_read(codec
, dcs_l_reg
);
815 wm8904
->dcs_state
[dcs_r
] = snd_soc_read(codec
, dcs_r_reg
);
817 snd_soc_update_bits(codec
, WM8904_DC_SERVO_0
,
820 /* Disable the amplifier input and output stages */
821 snd_soc_update_bits(codec
, reg
,
822 WM8904_HPL_ENA
| WM8904_HPR_ENA
|
823 WM8904_HPL_ENA_DLY
| WM8904_HPR_ENA_DLY
|
824 WM8904_HPL_ENA_OUTP
| WM8904_HPR_ENA_OUTP
,
828 snd_soc_update_bits(codec
, pwr_reg
,
829 WM8904_HPL_PGA_ENA
| WM8904_HPR_PGA_ENA
,
837 static const char *lin_text
[] = {
838 "IN1L", "IN2L", "IN3L"
841 static const struct soc_enum lin_enum
=
842 SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1
, 2, 3, lin_text
);
844 static const struct snd_kcontrol_new lin_mux
=
845 SOC_DAPM_ENUM("Left Capture Mux", lin_enum
);
847 static const struct soc_enum lin_inv_enum
=
848 SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1
, 4, 3, lin_text
);
850 static const struct snd_kcontrol_new lin_inv_mux
=
851 SOC_DAPM_ENUM("Left Capture Inveting Mux", lin_inv_enum
);
853 static const char *rin_text
[] = {
854 "IN1R", "IN2R", "IN3R"
857 static const struct soc_enum rin_enum
=
858 SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1
, 2, 3, rin_text
);
860 static const struct snd_kcontrol_new rin_mux
=
861 SOC_DAPM_ENUM("Right Capture Mux", rin_enum
);
863 static const struct soc_enum rin_inv_enum
=
864 SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1
, 4, 3, rin_text
);
866 static const struct snd_kcontrol_new rin_inv_mux
=
867 SOC_DAPM_ENUM("Right Capture Inveting Mux", rin_inv_enum
);
869 static const char *aif_text
[] = {
873 static const struct soc_enum aifoutl_enum
=
874 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0
, 7, 2, aif_text
);
876 static const struct snd_kcontrol_new aifoutl_mux
=
877 SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum
);
879 static const struct soc_enum aifoutr_enum
=
880 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0
, 6, 2, aif_text
);
882 static const struct snd_kcontrol_new aifoutr_mux
=
883 SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum
);
885 static const struct soc_enum aifinl_enum
=
886 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0
, 5, 2, aif_text
);
888 static const struct snd_kcontrol_new aifinl_mux
=
889 SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum
);
891 static const struct soc_enum aifinr_enum
=
892 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0
, 4, 2, aif_text
);
894 static const struct snd_kcontrol_new aifinr_mux
=
895 SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum
);
897 static const struct snd_soc_dapm_widget wm8904_core_dapm_widgets
[] = {
898 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8904_CLOCK_RATES_2
, 2, 0, sysclk_event
,
899 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
900 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8904_CLOCK_RATES_2
, 1, 0, NULL
, 0),
901 SND_SOC_DAPM_SUPPLY("TOCLK", WM8904_CLOCK_RATES_2
, 0, 0, NULL
, 0),
904 static const struct snd_soc_dapm_widget wm8904_adc_dapm_widgets
[] = {
905 SND_SOC_DAPM_INPUT("IN1L"),
906 SND_SOC_DAPM_INPUT("IN1R"),
907 SND_SOC_DAPM_INPUT("IN2L"),
908 SND_SOC_DAPM_INPUT("IN2R"),
909 SND_SOC_DAPM_INPUT("IN3L"),
910 SND_SOC_DAPM_INPUT("IN3R"),
912 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8904_MIC_BIAS_CONTROL_0
, 0, 0, NULL
, 0),
914 SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM
, 0, 0, &lin_mux
),
915 SND_SOC_DAPM_MUX("Left Capture Inverting Mux", SND_SOC_NOPM
, 0, 0,
917 SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM
, 0, 0, &rin_mux
),
918 SND_SOC_DAPM_MUX("Right Capture Inverting Mux", SND_SOC_NOPM
, 0, 0,
921 SND_SOC_DAPM_PGA("Left Capture PGA", WM8904_POWER_MANAGEMENT_0
, 1, 0,
923 SND_SOC_DAPM_PGA("Right Capture PGA", WM8904_POWER_MANAGEMENT_0
, 0, 0,
926 SND_SOC_DAPM_ADC("ADCL", NULL
, WM8904_POWER_MANAGEMENT_6
, 1, 0),
927 SND_SOC_DAPM_ADC("ADCR", NULL
, WM8904_POWER_MANAGEMENT_6
, 0, 0),
929 SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM
, 0, 0, &aifoutl_mux
),
930 SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM
, 0, 0, &aifoutr_mux
),
932 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM
, 0, 0),
933 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM
, 0, 0),
936 static const struct snd_soc_dapm_widget wm8904_dac_dapm_widgets
[] = {
937 SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM
, 0, 0),
938 SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM
, 0, 0),
940 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM
, 0, 0, &aifinl_mux
),
941 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM
, 0, 0, &aifinr_mux
),
943 SND_SOC_DAPM_DAC("DACL", NULL
, WM8904_POWER_MANAGEMENT_6
, 3, 0),
944 SND_SOC_DAPM_DAC("DACR", NULL
, WM8904_POWER_MANAGEMENT_6
, 2, 0),
946 SND_SOC_DAPM_SUPPLY("Charge pump", WM8904_CHARGE_PUMP_0
, 0, 0, cp_event
,
947 SND_SOC_DAPM_POST_PMU
),
949 SND_SOC_DAPM_PGA("HPL PGA", SND_SOC_NOPM
, 1, 0, NULL
, 0),
950 SND_SOC_DAPM_PGA("HPR PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0),
952 SND_SOC_DAPM_PGA("LINEL PGA", SND_SOC_NOPM
, 1, 0, NULL
, 0),
953 SND_SOC_DAPM_PGA("LINER PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0),
955 SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM
, WM8904_ANALOGUE_HP_0
,
956 0, NULL
, 0, out_pga_event
,
957 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMU
|
958 SND_SOC_DAPM_PRE_PMD
| SND_SOC_DAPM_POST_PMD
),
959 SND_SOC_DAPM_PGA_E("Line Output", SND_SOC_NOPM
, WM8904_ANALOGUE_LINEOUT_0
,
960 0, NULL
, 0, out_pga_event
,
961 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMU
|
962 SND_SOC_DAPM_PRE_PMD
| SND_SOC_DAPM_POST_PMD
),
964 SND_SOC_DAPM_OUTPUT("HPOUTL"),
965 SND_SOC_DAPM_OUTPUT("HPOUTR"),
966 SND_SOC_DAPM_OUTPUT("LINEOUTL"),
967 SND_SOC_DAPM_OUTPUT("LINEOUTR"),
970 static const char *out_mux_text
[] = {
974 static const struct soc_enum hpl_enum
=
975 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC
, 3, 2, out_mux_text
);
977 static const struct snd_kcontrol_new hpl_mux
=
978 SOC_DAPM_ENUM("HPL Mux", hpl_enum
);
980 static const struct soc_enum hpr_enum
=
981 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC
, 2, 2, out_mux_text
);
983 static const struct snd_kcontrol_new hpr_mux
=
984 SOC_DAPM_ENUM("HPR Mux", hpr_enum
);
986 static const struct soc_enum linel_enum
=
987 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC
, 1, 2, out_mux_text
);
989 static const struct snd_kcontrol_new linel_mux
=
990 SOC_DAPM_ENUM("LINEL Mux", linel_enum
);
992 static const struct soc_enum liner_enum
=
993 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC
, 0, 2, out_mux_text
);
995 static const struct snd_kcontrol_new liner_mux
=
996 SOC_DAPM_ENUM("LINEL Mux", liner_enum
);
998 static const char *sidetone_text
[] = {
999 "None", "Left", "Right"
1002 static const struct soc_enum dacl_sidetone_enum
=
1003 SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0
, 2, 3, sidetone_text
);
1005 static const struct snd_kcontrol_new dacl_sidetone_mux
=
1006 SOC_DAPM_ENUM("Left Sidetone Mux", dacl_sidetone_enum
);
1008 static const struct soc_enum dacr_sidetone_enum
=
1009 SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0
, 0, 3, sidetone_text
);
1011 static const struct snd_kcontrol_new dacr_sidetone_mux
=
1012 SOC_DAPM_ENUM("Right Sidetone Mux", dacr_sidetone_enum
);
1014 static const struct snd_soc_dapm_widget wm8904_dapm_widgets
[] = {
1015 SND_SOC_DAPM_SUPPLY("Class G", WM8904_CLASS_W_0
, 0, 1, NULL
, 0),
1016 SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM
, 0, 0, NULL
, 0),
1017 SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM
, 0, 0, NULL
, 0),
1019 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM
, 0, 0, &dacl_sidetone_mux
),
1020 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM
, 0, 0, &dacr_sidetone_mux
),
1022 SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM
, 0, 0, &hpl_mux
),
1023 SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM
, 0, 0, &hpr_mux
),
1024 SND_SOC_DAPM_MUX("LINEL Mux", SND_SOC_NOPM
, 0, 0, &linel_mux
),
1025 SND_SOC_DAPM_MUX("LINER Mux", SND_SOC_NOPM
, 0, 0, &liner_mux
),
1028 static const struct snd_soc_dapm_route core_intercon
[] = {
1029 { "CLK_DSP", NULL
, "SYSCLK" },
1030 { "TOCLK", NULL
, "SYSCLK" },
1033 static const struct snd_soc_dapm_route adc_intercon
[] = {
1034 { "Left Capture Mux", "IN1L", "IN1L" },
1035 { "Left Capture Mux", "IN2L", "IN2L" },
1036 { "Left Capture Mux", "IN3L", "IN3L" },
1038 { "Left Capture Inverting Mux", "IN1L", "IN1L" },
1039 { "Left Capture Inverting Mux", "IN2L", "IN2L" },
1040 { "Left Capture Inverting Mux", "IN3L", "IN3L" },
1042 { "Right Capture Mux", "IN1R", "IN1R" },
1043 { "Right Capture Mux", "IN2R", "IN2R" },
1044 { "Right Capture Mux", "IN3R", "IN3R" },
1046 { "Right Capture Inverting Mux", "IN1R", "IN1R" },
1047 { "Right Capture Inverting Mux", "IN2R", "IN2R" },
1048 { "Right Capture Inverting Mux", "IN3R", "IN3R" },
1050 { "Left Capture PGA", NULL
, "Left Capture Mux" },
1051 { "Left Capture PGA", NULL
, "Left Capture Inverting Mux" },
1053 { "Right Capture PGA", NULL
, "Right Capture Mux" },
1054 { "Right Capture PGA", NULL
, "Right Capture Inverting Mux" },
1056 { "AIFOUTL", "Left", "ADCL" },
1057 { "AIFOUTL", "Right", "ADCR" },
1058 { "AIFOUTR", "Left", "ADCL" },
1059 { "AIFOUTR", "Right", "ADCR" },
1061 { "ADCL", NULL
, "CLK_DSP" },
1062 { "ADCL", NULL
, "Left Capture PGA" },
1064 { "ADCR", NULL
, "CLK_DSP" },
1065 { "ADCR", NULL
, "Right Capture PGA" },
1068 static const struct snd_soc_dapm_route dac_intercon
[] = {
1069 { "DACL", "Right", "AIFINR" },
1070 { "DACL", "Left", "AIFINL" },
1071 { "DACL", NULL
, "CLK_DSP" },
1073 { "DACR", "Right", "AIFINR" },
1074 { "DACR", "Left", "AIFINL" },
1075 { "DACR", NULL
, "CLK_DSP" },
1077 { "Charge pump", NULL
, "SYSCLK" },
1079 { "Headphone Output", NULL
, "HPL PGA" },
1080 { "Headphone Output", NULL
, "HPR PGA" },
1081 { "Headphone Output", NULL
, "Charge pump" },
1082 { "Headphone Output", NULL
, "TOCLK" },
1084 { "Line Output", NULL
, "LINEL PGA" },
1085 { "Line Output", NULL
, "LINER PGA" },
1086 { "Line Output", NULL
, "Charge pump" },
1087 { "Line Output", NULL
, "TOCLK" },
1089 { "HPOUTL", NULL
, "Headphone Output" },
1090 { "HPOUTR", NULL
, "Headphone Output" },
1092 { "LINEOUTL", NULL
, "Line Output" },
1093 { "LINEOUTR", NULL
, "Line Output" },
1096 static const struct snd_soc_dapm_route wm8904_intercon
[] = {
1097 { "Left Sidetone", "Left", "ADCL" },
1098 { "Left Sidetone", "Right", "ADCR" },
1099 { "DACL", NULL
, "Left Sidetone" },
1101 { "Right Sidetone", "Left", "ADCL" },
1102 { "Right Sidetone", "Right", "ADCR" },
1103 { "DACR", NULL
, "Right Sidetone" },
1105 { "Left Bypass", NULL
, "Class G" },
1106 { "Left Bypass", NULL
, "Left Capture PGA" },
1108 { "Right Bypass", NULL
, "Class G" },
1109 { "Right Bypass", NULL
, "Right Capture PGA" },
1111 { "HPL Mux", "DAC", "DACL" },
1112 { "HPL Mux", "Bypass", "Left Bypass" },
1114 { "HPR Mux", "DAC", "DACR" },
1115 { "HPR Mux", "Bypass", "Right Bypass" },
1117 { "LINEL Mux", "DAC", "DACL" },
1118 { "LINEL Mux", "Bypass", "Left Bypass" },
1120 { "LINER Mux", "DAC", "DACR" },
1121 { "LINER Mux", "Bypass", "Right Bypass" },
1123 { "HPL PGA", NULL
, "HPL Mux" },
1124 { "HPR PGA", NULL
, "HPR Mux" },
1126 { "LINEL PGA", NULL
, "LINEL Mux" },
1127 { "LINER PGA", NULL
, "LINER Mux" },
1130 static const struct snd_soc_dapm_route wm8912_intercon
[] = {
1131 { "HPL PGA", NULL
, "DACL" },
1132 { "HPR PGA", NULL
, "DACR" },
1134 { "LINEL PGA", NULL
, "DACL" },
1135 { "LINER PGA", NULL
, "DACR" },
1138 static int wm8904_add_widgets(struct snd_soc_codec
*codec
)
1140 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
1141 struct snd_soc_dapm_context
*dapm
= &codec
->dapm
;
1143 snd_soc_dapm_new_controls(dapm
, wm8904_core_dapm_widgets
,
1144 ARRAY_SIZE(wm8904_core_dapm_widgets
));
1145 snd_soc_dapm_add_routes(dapm
, core_intercon
,
1146 ARRAY_SIZE(core_intercon
));
1148 switch (wm8904
->devtype
) {
1150 snd_soc_add_controls(codec
, wm8904_adc_snd_controls
,
1151 ARRAY_SIZE(wm8904_adc_snd_controls
));
1152 snd_soc_add_controls(codec
, wm8904_dac_snd_controls
,
1153 ARRAY_SIZE(wm8904_dac_snd_controls
));
1154 snd_soc_add_controls(codec
, wm8904_snd_controls
,
1155 ARRAY_SIZE(wm8904_snd_controls
));
1157 snd_soc_dapm_new_controls(dapm
, wm8904_adc_dapm_widgets
,
1158 ARRAY_SIZE(wm8904_adc_dapm_widgets
));
1159 snd_soc_dapm_new_controls(dapm
, wm8904_dac_dapm_widgets
,
1160 ARRAY_SIZE(wm8904_dac_dapm_widgets
));
1161 snd_soc_dapm_new_controls(dapm
, wm8904_dapm_widgets
,
1162 ARRAY_SIZE(wm8904_dapm_widgets
));
1164 snd_soc_dapm_add_routes(dapm
, core_intercon
,
1165 ARRAY_SIZE(core_intercon
));
1166 snd_soc_dapm_add_routes(dapm
, adc_intercon
,
1167 ARRAY_SIZE(adc_intercon
));
1168 snd_soc_dapm_add_routes(dapm
, dac_intercon
,
1169 ARRAY_SIZE(dac_intercon
));
1170 snd_soc_dapm_add_routes(dapm
, wm8904_intercon
,
1171 ARRAY_SIZE(wm8904_intercon
));
1175 snd_soc_add_controls(codec
, wm8904_dac_snd_controls
,
1176 ARRAY_SIZE(wm8904_dac_snd_controls
));
1178 snd_soc_dapm_new_controls(dapm
, wm8904_dac_dapm_widgets
,
1179 ARRAY_SIZE(wm8904_dac_dapm_widgets
));
1181 snd_soc_dapm_add_routes(dapm
, dac_intercon
,
1182 ARRAY_SIZE(dac_intercon
));
1183 snd_soc_dapm_add_routes(dapm
, wm8912_intercon
,
1184 ARRAY_SIZE(wm8912_intercon
));
1188 snd_soc_dapm_new_widgets(dapm
);
1194 unsigned int clk_sys_rate
;
1195 } clk_sys_rates
[] = {
1211 } sample_rates
[] = {
1224 int div
; /* *10 due to .5s */
1250 static int wm8904_hw_params(struct snd_pcm_substream
*substream
,
1251 struct snd_pcm_hw_params
*params
,
1252 struct snd_soc_dai
*dai
)
1254 struct snd_soc_codec
*codec
= dai
->codec
;
1255 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
1256 int ret
, i
, best
, best_val
, cur_val
;
1257 unsigned int aif1
= 0;
1258 unsigned int aif2
= 0;
1259 unsigned int aif3
= 0;
1260 unsigned int clock1
= 0;
1261 unsigned int dac_digital1
= 0;
1263 /* What BCLK do we need? */
1264 wm8904
->fs
= params_rate(params
);
1265 if (wm8904
->tdm_slots
) {
1266 dev_dbg(codec
->dev
, "Configuring for %d %d bit TDM slots\n",
1267 wm8904
->tdm_slots
, wm8904
->tdm_width
);
1268 wm8904
->bclk
= snd_soc_calc_bclk(wm8904
->fs
,
1269 wm8904
->tdm_width
, 2,
1272 wm8904
->bclk
= snd_soc_params_to_bclk(params
);
1275 switch (params_format(params
)) {
1276 case SNDRV_PCM_FORMAT_S16_LE
:
1278 case SNDRV_PCM_FORMAT_S20_3LE
:
1281 case SNDRV_PCM_FORMAT_S24_LE
:
1284 case SNDRV_PCM_FORMAT_S32_LE
:
1292 dev_dbg(codec
->dev
, "Target BCLK is %dHz\n", wm8904
->bclk
);
1294 ret
= wm8904_configure_clocking(codec
);
1298 /* Select nearest CLK_SYS_RATE */
1300 best_val
= abs((wm8904
->sysclk_rate
/ clk_sys_rates
[0].ratio
)
1302 for (i
= 1; i
< ARRAY_SIZE(clk_sys_rates
); i
++) {
1303 cur_val
= abs((wm8904
->sysclk_rate
/
1304 clk_sys_rates
[i
].ratio
) - wm8904
->fs
);
1305 if (cur_val
< best_val
) {
1310 dev_dbg(codec
->dev
, "Selected CLK_SYS_RATIO of %d\n",
1311 clk_sys_rates
[best
].ratio
);
1312 clock1
|= (clk_sys_rates
[best
].clk_sys_rate
1313 << WM8904_CLK_SYS_RATE_SHIFT
);
1317 best_val
= abs(wm8904
->fs
- sample_rates
[0].rate
);
1318 for (i
= 1; i
< ARRAY_SIZE(sample_rates
); i
++) {
1320 cur_val
= abs(wm8904
->fs
- sample_rates
[i
].rate
);
1321 if (cur_val
< best_val
) {
1326 dev_dbg(codec
->dev
, "Selected SAMPLE_RATE of %dHz\n",
1327 sample_rates
[best
].rate
);
1328 clock1
|= (sample_rates
[best
].sample_rate
1329 << WM8904_SAMPLE_RATE_SHIFT
);
1331 /* Enable sloping stopband filter for low sample rates */
1332 if (wm8904
->fs
<= 24000)
1333 dac_digital1
|= WM8904_DAC_SB_FILT
;
1338 for (i
= 0; i
< ARRAY_SIZE(bclk_divs
); i
++) {
1339 cur_val
= ((wm8904
->sysclk_rate
* 10) / bclk_divs
[i
].div
)
1341 if (cur_val
< 0) /* Table is sorted */
1343 if (cur_val
< best_val
) {
1348 wm8904
->bclk
= (wm8904
->sysclk_rate
* 10) / bclk_divs
[best
].div
;
1349 dev_dbg(codec
->dev
, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1350 bclk_divs
[best
].div
, wm8904
->bclk
);
1351 aif2
|= bclk_divs
[best
].bclk_div
;
1353 /* LRCLK is a simple fraction of BCLK */
1354 dev_dbg(codec
->dev
, "LRCLK_RATE is %d\n", wm8904
->bclk
/ wm8904
->fs
);
1355 aif3
|= wm8904
->bclk
/ wm8904
->fs
;
1357 /* Apply the settings */
1358 snd_soc_update_bits(codec
, WM8904_DAC_DIGITAL_1
,
1359 WM8904_DAC_SB_FILT
, dac_digital1
);
1360 snd_soc_update_bits(codec
, WM8904_AUDIO_INTERFACE_1
,
1361 WM8904_AIF_WL_MASK
, aif1
);
1362 snd_soc_update_bits(codec
, WM8904_AUDIO_INTERFACE_2
,
1363 WM8904_BCLK_DIV_MASK
, aif2
);
1364 snd_soc_update_bits(codec
, WM8904_AUDIO_INTERFACE_3
,
1365 WM8904_LRCLK_RATE_MASK
, aif3
);
1366 snd_soc_update_bits(codec
, WM8904_CLOCK_RATES_1
,
1367 WM8904_SAMPLE_RATE_MASK
|
1368 WM8904_CLK_SYS_RATE_MASK
, clock1
);
1370 /* Update filters for the new settings */
1371 wm8904_set_retune_mobile(codec
);
1372 wm8904_set_deemph(codec
);
1378 static int wm8904_set_sysclk(struct snd_soc_dai
*dai
, int clk_id
,
1379 unsigned int freq
, int dir
)
1381 struct snd_soc_codec
*codec
= dai
->codec
;
1382 struct wm8904_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
1385 case WM8904_CLK_MCLK
:
1386 priv
->sysclk_src
= clk_id
;
1387 priv
->mclk_rate
= freq
;
1390 case WM8904_CLK_FLL
:
1391 priv
->sysclk_src
= clk_id
;
1398 dev_dbg(dai
->dev
, "Clock source is %d at %uHz\n", clk_id
, freq
);
1400 wm8904_configure_clocking(codec
);
1405 static int wm8904_set_fmt(struct snd_soc_dai
*dai
, unsigned int fmt
)
1407 struct snd_soc_codec
*codec
= dai
->codec
;
1408 unsigned int aif1
= 0;
1409 unsigned int aif3
= 0;
1411 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
1412 case SND_SOC_DAIFMT_CBS_CFS
:
1414 case SND_SOC_DAIFMT_CBS_CFM
:
1415 aif3
|= WM8904_LRCLK_DIR
;
1417 case SND_SOC_DAIFMT_CBM_CFS
:
1418 aif1
|= WM8904_BCLK_DIR
;
1420 case SND_SOC_DAIFMT_CBM_CFM
:
1421 aif1
|= WM8904_BCLK_DIR
;
1422 aif3
|= WM8904_LRCLK_DIR
;
1428 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1429 case SND_SOC_DAIFMT_DSP_B
:
1430 aif1
|= WM8904_AIF_LRCLK_INV
;
1431 case SND_SOC_DAIFMT_DSP_A
:
1434 case SND_SOC_DAIFMT_I2S
:
1437 case SND_SOC_DAIFMT_RIGHT_J
:
1439 case SND_SOC_DAIFMT_LEFT_J
:
1446 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1447 case SND_SOC_DAIFMT_DSP_A
:
1448 case SND_SOC_DAIFMT_DSP_B
:
1449 /* frame inversion not valid for DSP modes */
1450 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1451 case SND_SOC_DAIFMT_NB_NF
:
1453 case SND_SOC_DAIFMT_IB_NF
:
1454 aif1
|= WM8904_AIF_BCLK_INV
;
1461 case SND_SOC_DAIFMT_I2S
:
1462 case SND_SOC_DAIFMT_RIGHT_J
:
1463 case SND_SOC_DAIFMT_LEFT_J
:
1464 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1465 case SND_SOC_DAIFMT_NB_NF
:
1467 case SND_SOC_DAIFMT_IB_IF
:
1468 aif1
|= WM8904_AIF_BCLK_INV
| WM8904_AIF_LRCLK_INV
;
1470 case SND_SOC_DAIFMT_IB_NF
:
1471 aif1
|= WM8904_AIF_BCLK_INV
;
1473 case SND_SOC_DAIFMT_NB_IF
:
1474 aif1
|= WM8904_AIF_LRCLK_INV
;
1484 snd_soc_update_bits(codec
, WM8904_AUDIO_INTERFACE_1
,
1485 WM8904_AIF_BCLK_INV
| WM8904_AIF_LRCLK_INV
|
1486 WM8904_AIF_FMT_MASK
| WM8904_BCLK_DIR
, aif1
);
1487 snd_soc_update_bits(codec
, WM8904_AUDIO_INTERFACE_3
,
1488 WM8904_LRCLK_DIR
, aif3
);
1494 static int wm8904_set_tdm_slot(struct snd_soc_dai
*dai
, unsigned int tx_mask
,
1495 unsigned int rx_mask
, int slots
, int slot_width
)
1497 struct snd_soc_codec
*codec
= dai
->codec
;
1498 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
1501 /* Don't need to validate anything if we're turning off TDM */
1505 /* Note that we allow configurations we can't handle ourselves -
1506 * for example, we can generate clocks for slots 2 and up even if
1507 * we can't use those slots ourselves.
1509 aif1
|= WM8904_AIFADC_TDM
| WM8904_AIFDAC_TDM
;
1515 aif1
|= WM8904_AIFADC_TDM_CHAN
;
1526 aif1
|= WM8904_AIFDAC_TDM_CHAN
;
1533 wm8904
->tdm_width
= slot_width
;
1534 wm8904
->tdm_slots
= slots
/ 2;
1536 snd_soc_update_bits(codec
, WM8904_AUDIO_INTERFACE_1
,
1537 WM8904_AIFADC_TDM
| WM8904_AIFADC_TDM_CHAN
|
1538 WM8904_AIFDAC_TDM
| WM8904_AIFDAC_TDM_CHAN
, aif1
);
1546 u16 fll_clk_ref_div
;
1551 /* The size in bits of the FLL divide multiplied by 10
1552 * to allow rounding later */
1553 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1561 { 0, 64000, 4, 16 },
1562 { 64000, 128000, 3, 8 },
1563 { 128000, 256000, 2, 4 },
1564 { 256000, 1000000, 1, 2 },
1565 { 1000000, 13500000, 0, 1 },
1568 static int fll_factors(struct _fll_div
*fll_div
, unsigned int Fref
,
1572 unsigned int K
, Ndiv
, Nmod
, target
;
1576 /* Fref must be <=13.5MHz */
1578 fll_div
->fll_clk_ref_div
= 0;
1579 while ((Fref
/ div
) > 13500000) {
1581 fll_div
->fll_clk_ref_div
++;
1584 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1590 pr_debug("Fref=%u Fout=%u\n", Fref
, Fout
);
1592 /* Apply the division for our remaining calculations */
1595 /* Fvco should be 90-100MHz; don't check the upper bound */
1597 while (Fout
* div
< 90000000) {
1600 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1605 target
= Fout
* div
;
1606 fll_div
->fll_outdiv
= div
- 1;
1608 pr_debug("Fvco=%dHz\n", target
);
1610 /* Find an appropriate FLL_FRATIO and factor it out of the target */
1611 for (i
= 0; i
< ARRAY_SIZE(fll_fratios
); i
++) {
1612 if (fll_fratios
[i
].min
<= Fref
&& Fref
<= fll_fratios
[i
].max
) {
1613 fll_div
->fll_fratio
= fll_fratios
[i
].fll_fratio
;
1614 target
/= fll_fratios
[i
].ratio
;
1618 if (i
== ARRAY_SIZE(fll_fratios
)) {
1619 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref
);
1623 /* Now, calculate N.K */
1624 Ndiv
= target
/ Fref
;
1627 Nmod
= target
% Fref
;
1628 pr_debug("Nmod=%d\n", Nmod
);
1630 /* Calculate fractional part - scale up so we can round. */
1631 Kpart
= FIXED_FLL_SIZE
* (long long)Nmod
;
1633 do_div(Kpart
, Fref
);
1635 K
= Kpart
& 0xFFFFFFFF;
1640 /* Move down to proper range now rounding is done */
1641 fll_div
->k
= K
/ 10;
1643 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
1644 fll_div
->n
, fll_div
->k
,
1645 fll_div
->fll_fratio
, fll_div
->fll_outdiv
,
1646 fll_div
->fll_clk_ref_div
);
1651 static int wm8904_set_fll(struct snd_soc_dai
*dai
, int fll_id
, int source
,
1652 unsigned int Fref
, unsigned int Fout
)
1654 struct snd_soc_codec
*codec
= dai
->codec
;
1655 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
1656 struct _fll_div fll_div
;
1661 if (source
== wm8904
->fll_src
&& Fref
== wm8904
->fll_fref
&&
1662 Fout
== wm8904
->fll_fout
)
1665 clock2
= snd_soc_read(codec
, WM8904_CLOCK_RATES_2
);
1668 dev_dbg(codec
->dev
, "FLL disabled\n");
1670 wm8904
->fll_fref
= 0;
1671 wm8904
->fll_fout
= 0;
1673 /* Gate SYSCLK to avoid glitches */
1674 snd_soc_update_bits(codec
, WM8904_CLOCK_RATES_2
,
1675 WM8904_CLK_SYS_ENA
, 0);
1677 snd_soc_update_bits(codec
, WM8904_FLL_CONTROL_1
,
1678 WM8904_FLL_OSC_ENA
| WM8904_FLL_ENA
, 0);
1683 /* Validate the FLL ID */
1685 case WM8904_FLL_MCLK
:
1686 case WM8904_FLL_LRCLK
:
1687 case WM8904_FLL_BCLK
:
1688 ret
= fll_factors(&fll_div
, Fref
, Fout
);
1693 case WM8904_FLL_FREE_RUNNING
:
1694 dev_dbg(codec
->dev
, "Using free running FLL\n");
1695 /* Force 12MHz and output/4 for now */
1699 memset(&fll_div
, 0, sizeof(fll_div
));
1700 fll_div
.fll_outdiv
= 3;
1704 dev_err(codec
->dev
, "Unknown FLL ID %d\n", fll_id
);
1708 /* Save current state then disable the FLL and SYSCLK to avoid
1710 fll1
= snd_soc_read(codec
, WM8904_FLL_CONTROL_1
);
1711 snd_soc_update_bits(codec
, WM8904_CLOCK_RATES_2
,
1712 WM8904_CLK_SYS_ENA
, 0);
1713 snd_soc_update_bits(codec
, WM8904_FLL_CONTROL_1
,
1714 WM8904_FLL_OSC_ENA
| WM8904_FLL_ENA
, 0);
1716 /* Unlock forced oscilator control to switch it on/off */
1717 snd_soc_update_bits(codec
, WM8904_CONTROL_INTERFACE_TEST_1
,
1718 WM8904_USER_KEY
, WM8904_USER_KEY
);
1720 if (fll_id
== WM8904_FLL_FREE_RUNNING
) {
1721 val
= WM8904_FLL_FRC_NCO
;
1726 snd_soc_update_bits(codec
, WM8904_FLL_NCO_TEST_1
, WM8904_FLL_FRC_NCO
,
1728 snd_soc_update_bits(codec
, WM8904_CONTROL_INTERFACE_TEST_1
,
1729 WM8904_USER_KEY
, 0);
1732 case WM8904_FLL_MCLK
:
1733 snd_soc_update_bits(codec
, WM8904_FLL_CONTROL_5
,
1734 WM8904_FLL_CLK_REF_SRC_MASK
, 0);
1737 case WM8904_FLL_LRCLK
:
1738 snd_soc_update_bits(codec
, WM8904_FLL_CONTROL_5
,
1739 WM8904_FLL_CLK_REF_SRC_MASK
, 1);
1742 case WM8904_FLL_BCLK
:
1743 snd_soc_update_bits(codec
, WM8904_FLL_CONTROL_5
,
1744 WM8904_FLL_CLK_REF_SRC_MASK
, 2);
1749 val
= WM8904_FLL_FRACN_ENA
;
1752 snd_soc_update_bits(codec
, WM8904_FLL_CONTROL_1
,
1753 WM8904_FLL_FRACN_ENA
, val
);
1755 snd_soc_update_bits(codec
, WM8904_FLL_CONTROL_2
,
1756 WM8904_FLL_OUTDIV_MASK
| WM8904_FLL_FRATIO_MASK
,
1757 (fll_div
.fll_outdiv
<< WM8904_FLL_OUTDIV_SHIFT
) |
1758 (fll_div
.fll_fratio
<< WM8904_FLL_FRATIO_SHIFT
));
1760 snd_soc_write(codec
, WM8904_FLL_CONTROL_3
, fll_div
.k
);
1762 snd_soc_update_bits(codec
, WM8904_FLL_CONTROL_4
, WM8904_FLL_N_MASK
,
1763 fll_div
.n
<< WM8904_FLL_N_SHIFT
);
1765 snd_soc_update_bits(codec
, WM8904_FLL_CONTROL_5
,
1766 WM8904_FLL_CLK_REF_DIV_MASK
,
1767 fll_div
.fll_clk_ref_div
1768 << WM8904_FLL_CLK_REF_DIV_SHIFT
);
1770 dev_dbg(codec
->dev
, "FLL configured for %dHz->%dHz\n", Fref
, Fout
);
1772 wm8904
->fll_fref
= Fref
;
1773 wm8904
->fll_fout
= Fout
;
1774 wm8904
->fll_src
= source
;
1776 /* Enable the FLL if it was previously active */
1777 snd_soc_update_bits(codec
, WM8904_FLL_CONTROL_1
,
1778 WM8904_FLL_OSC_ENA
, fll1
);
1779 snd_soc_update_bits(codec
, WM8904_FLL_CONTROL_1
,
1780 WM8904_FLL_ENA
, fll1
);
1783 /* Reenable SYSCLK if it was previously active */
1784 snd_soc_update_bits(codec
, WM8904_CLOCK_RATES_2
,
1785 WM8904_CLK_SYS_ENA
, clock2
);
1790 static int wm8904_digital_mute(struct snd_soc_dai
*codec_dai
, int mute
)
1792 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1796 val
= WM8904_DAC_MUTE
;
1800 snd_soc_update_bits(codec
, WM8904_DAC_DIGITAL_1
, WM8904_DAC_MUTE
, val
);
1805 static int wm8904_set_bias_level(struct snd_soc_codec
*codec
,
1806 enum snd_soc_bias_level level
)
1808 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
1812 case SND_SOC_BIAS_ON
:
1815 case SND_SOC_BIAS_PREPARE
:
1816 /* VMID resistance 2*50k */
1817 snd_soc_update_bits(codec
, WM8904_VMID_CONTROL_0
,
1818 WM8904_VMID_RES_MASK
,
1819 0x1 << WM8904_VMID_RES_SHIFT
);
1821 /* Normal bias current */
1822 snd_soc_update_bits(codec
, WM8904_BIAS_CONTROL_0
,
1823 WM8904_ISEL_MASK
, 2 << WM8904_ISEL_SHIFT
);
1826 case SND_SOC_BIAS_STANDBY
:
1827 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
1828 ret
= regulator_bulk_enable(ARRAY_SIZE(wm8904
->supplies
),
1832 "Failed to enable supplies: %d\n",
1837 regcache_sync(wm8904
->regmap
);
1840 snd_soc_update_bits(codec
, WM8904_BIAS_CONTROL_0
,
1841 WM8904_BIAS_ENA
, WM8904_BIAS_ENA
);
1843 /* Enable VMID, VMID buffering, 2*5k resistance */
1844 snd_soc_update_bits(codec
, WM8904_VMID_CONTROL_0
,
1846 WM8904_VMID_RES_MASK
,
1848 0x3 << WM8904_VMID_RES_SHIFT
);
1854 /* Maintain VMID with 2*250k */
1855 snd_soc_update_bits(codec
, WM8904_VMID_CONTROL_0
,
1856 WM8904_VMID_RES_MASK
,
1857 0x2 << WM8904_VMID_RES_SHIFT
);
1859 /* Bias current *0.5 */
1860 snd_soc_update_bits(codec
, WM8904_BIAS_CONTROL_0
,
1861 WM8904_ISEL_MASK
, 0);
1864 case SND_SOC_BIAS_OFF
:
1866 snd_soc_update_bits(codec
, WM8904_VMID_CONTROL_0
,
1867 WM8904_VMID_RES_MASK
| WM8904_VMID_ENA
, 0);
1869 /* Stop bias generation */
1870 snd_soc_update_bits(codec
, WM8904_BIAS_CONTROL_0
,
1871 WM8904_BIAS_ENA
, 0);
1873 #ifdef CONFIG_REGULATOR
1874 /* Post 2.6.34 we will be able to get a callback when
1875 * the regulators are disabled which we can use but
1876 * for now just assume that the power will be cut if
1877 * the regulator API is in use.
1879 codec
->cache_sync
= 1;
1882 regulator_bulk_disable(ARRAY_SIZE(wm8904
->supplies
),
1886 codec
->dapm
.bias_level
= level
;
1890 #define WM8904_RATES SNDRV_PCM_RATE_8000_96000
1892 #define WM8904_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1893 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1895 static const struct snd_soc_dai_ops wm8904_dai_ops
= {
1896 .set_sysclk
= wm8904_set_sysclk
,
1897 .set_fmt
= wm8904_set_fmt
,
1898 .set_tdm_slot
= wm8904_set_tdm_slot
,
1899 .set_pll
= wm8904_set_fll
,
1900 .hw_params
= wm8904_hw_params
,
1901 .digital_mute
= wm8904_digital_mute
,
1904 static struct snd_soc_dai_driver wm8904_dai
= {
1905 .name
= "wm8904-hifi",
1907 .stream_name
= "Playback",
1910 .rates
= WM8904_RATES
,
1911 .formats
= WM8904_FORMATS
,
1914 .stream_name
= "Capture",
1917 .rates
= WM8904_RATES
,
1918 .formats
= WM8904_FORMATS
,
1920 .ops
= &wm8904_dai_ops
,
1921 .symmetric_rates
= 1,
1925 static int wm8904_suspend(struct snd_soc_codec
*codec
)
1927 wm8904_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1932 static int wm8904_resume(struct snd_soc_codec
*codec
)
1934 wm8904_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1939 #define wm8904_suspend NULL
1940 #define wm8904_resume NULL
1943 static void wm8904_handle_retune_mobile_pdata(struct snd_soc_codec
*codec
)
1945 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
1946 struct wm8904_pdata
*pdata
= wm8904
->pdata
;
1947 struct snd_kcontrol_new control
=
1948 SOC_ENUM_EXT("EQ Mode",
1949 wm8904
->retune_mobile_enum
,
1950 wm8904_get_retune_mobile_enum
,
1951 wm8904_put_retune_mobile_enum
);
1955 /* We need an array of texts for the enum API but the number
1956 * of texts is likely to be less than the number of
1957 * configurations due to the sample rate dependency of the
1958 * configurations. */
1959 wm8904
->num_retune_mobile_texts
= 0;
1960 wm8904
->retune_mobile_texts
= NULL
;
1961 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
1962 for (j
= 0; j
< wm8904
->num_retune_mobile_texts
; j
++) {
1963 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
1964 wm8904
->retune_mobile_texts
[j
]) == 0)
1968 if (j
!= wm8904
->num_retune_mobile_texts
)
1971 /* Expand the array... */
1972 t
= krealloc(wm8904
->retune_mobile_texts
,
1974 (wm8904
->num_retune_mobile_texts
+ 1),
1979 /* ...store the new entry... */
1980 t
[wm8904
->num_retune_mobile_texts
] =
1981 pdata
->retune_mobile_cfgs
[i
].name
;
1983 /* ...and remember the new version. */
1984 wm8904
->num_retune_mobile_texts
++;
1985 wm8904
->retune_mobile_texts
= t
;
1988 dev_dbg(codec
->dev
, "Allocated %d unique ReTune Mobile names\n",
1989 wm8904
->num_retune_mobile_texts
);
1991 wm8904
->retune_mobile_enum
.max
= wm8904
->num_retune_mobile_texts
;
1992 wm8904
->retune_mobile_enum
.texts
= wm8904
->retune_mobile_texts
;
1994 ret
= snd_soc_add_controls(codec
, &control
, 1);
1997 "Failed to add ReTune Mobile control: %d\n", ret
);
2000 static void wm8904_handle_pdata(struct snd_soc_codec
*codec
)
2002 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
2003 struct wm8904_pdata
*pdata
= wm8904
->pdata
;
2007 snd_soc_add_controls(codec
, wm8904_eq_controls
,
2008 ARRAY_SIZE(wm8904_eq_controls
));
2012 dev_dbg(codec
->dev
, "%d DRC configurations\n", pdata
->num_drc_cfgs
);
2014 if (pdata
->num_drc_cfgs
) {
2015 struct snd_kcontrol_new control
=
2016 SOC_ENUM_EXT("DRC Mode", wm8904
->drc_enum
,
2017 wm8904_get_drc_enum
, wm8904_put_drc_enum
);
2019 /* We need an array of texts for the enum API */
2020 wm8904
->drc_texts
= kmalloc(sizeof(char *)
2021 * pdata
->num_drc_cfgs
, GFP_KERNEL
);
2022 if (!wm8904
->drc_texts
) {
2024 "Failed to allocate %d DRC config texts\n",
2025 pdata
->num_drc_cfgs
);
2029 for (i
= 0; i
< pdata
->num_drc_cfgs
; i
++)
2030 wm8904
->drc_texts
[i
] = pdata
->drc_cfgs
[i
].name
;
2032 wm8904
->drc_enum
.max
= pdata
->num_drc_cfgs
;
2033 wm8904
->drc_enum
.texts
= wm8904
->drc_texts
;
2035 ret
= snd_soc_add_controls(codec
, &control
, 1);
2038 "Failed to add DRC mode control: %d\n", ret
);
2040 wm8904_set_drc(codec
);
2043 dev_dbg(codec
->dev
, "%d ReTune Mobile configurations\n",
2044 pdata
->num_retune_mobile_cfgs
);
2046 if (pdata
->num_retune_mobile_cfgs
)
2047 wm8904_handle_retune_mobile_pdata(codec
);
2049 snd_soc_add_controls(codec
, wm8904_eq_controls
,
2050 ARRAY_SIZE(wm8904_eq_controls
));
2054 static int wm8904_probe(struct snd_soc_codec
*codec
)
2056 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
2057 struct wm8904_pdata
*pdata
= wm8904
->pdata
;
2058 u16
*reg_cache
= codec
->reg_cache
;
2061 codec
->cache_sync
= 1;
2062 codec
->dapm
.idle_bias_off
= 1;
2063 codec
->control_data
= wm8904
->regmap
;
2065 switch (wm8904
->devtype
) {
2069 memset(&wm8904_dai
.capture
, 0, sizeof(wm8904_dai
.capture
));
2072 dev_err(codec
->dev
, "Unknown device type %d\n",
2077 ret
= snd_soc_codec_set_cache_io(codec
, 8, 16, SND_SOC_REGMAP
);
2079 dev_err(codec
->dev
, "Failed to set cache I/O: %d\n", ret
);
2083 for (i
= 0; i
< ARRAY_SIZE(wm8904
->supplies
); i
++)
2084 wm8904
->supplies
[i
].supply
= wm8904_supply_names
[i
];
2086 ret
= regulator_bulk_get(codec
->dev
, ARRAY_SIZE(wm8904
->supplies
),
2089 dev_err(codec
->dev
, "Failed to request supplies: %d\n", ret
);
2093 ret
= regulator_bulk_enable(ARRAY_SIZE(wm8904
->supplies
),
2096 dev_err(codec
->dev
, "Failed to enable supplies: %d\n", ret
);
2100 ret
= snd_soc_read(codec
, WM8904_SW_RESET_AND_ID
);
2102 dev_err(codec
->dev
, "Failed to read ID register\n");
2105 if (ret
!= 0x8904) {
2106 dev_err(codec
->dev
, "Device is not a WM8904, ID is %x\n", ret
);
2111 ret
= snd_soc_read(codec
, WM8904_REVISION
);
2113 dev_err(codec
->dev
, "Failed to read device revision: %d\n",
2117 dev_info(codec
->dev
, "revision %c\n", ret
+ 'A');
2119 ret
= wm8904_reset(codec
);
2121 dev_err(codec
->dev
, "Failed to issue reset\n");
2125 /* Change some default settings - latch VU and enable ZC */
2126 snd_soc_update_bits(codec
, WM8904_ADC_DIGITAL_VOLUME_LEFT
,
2127 WM8904_ADC_VU
, WM8904_ADC_VU
);
2128 snd_soc_update_bits(codec
, WM8904_ADC_DIGITAL_VOLUME_RIGHT
,
2129 WM8904_ADC_VU
, WM8904_ADC_VU
);
2130 snd_soc_update_bits(codec
, WM8904_DAC_DIGITAL_VOLUME_LEFT
,
2131 WM8904_DAC_VU
, WM8904_DAC_VU
);
2132 snd_soc_update_bits(codec
, WM8904_DAC_DIGITAL_VOLUME_RIGHT
,
2133 WM8904_DAC_VU
, WM8904_DAC_VU
);
2134 snd_soc_update_bits(codec
, WM8904_ANALOGUE_OUT1_LEFT
,
2135 WM8904_HPOUT_VU
| WM8904_HPOUTLZC
,
2136 WM8904_HPOUT_VU
| WM8904_HPOUTLZC
);
2137 snd_soc_update_bits(codec
, WM8904_ANALOGUE_OUT1_RIGHT
,
2138 WM8904_HPOUT_VU
| WM8904_HPOUTRZC
,
2139 WM8904_HPOUT_VU
| WM8904_HPOUTRZC
);
2140 snd_soc_update_bits(codec
, WM8904_ANALOGUE_OUT2_LEFT
,
2141 WM8904_LINEOUT_VU
| WM8904_LINEOUTLZC
,
2142 WM8904_LINEOUT_VU
| WM8904_LINEOUTLZC
);
2143 snd_soc_update_bits(codec
, WM8904_ANALOGUE_OUT2_RIGHT
,
2144 WM8904_LINEOUT_VU
| WM8904_LINEOUTRZC
,
2145 WM8904_LINEOUT_VU
| WM8904_LINEOUTRZC
);
2146 snd_soc_update_bits(codec
, WM8904_CLOCK_RATES_0
,
2149 /* Apply configuration from the platform data. */
2150 if (wm8904
->pdata
) {
2151 for (i
= 0; i
< WM8904_GPIO_REGS
; i
++) {
2152 if (!pdata
->gpio_cfg
[i
])
2155 reg_cache
[WM8904_GPIO_CONTROL_1
+ i
]
2156 = pdata
->gpio_cfg
[i
] & 0xffff;
2159 /* Zero is the default value for these anyway */
2160 for (i
= 0; i
< WM8904_MIC_REGS
; i
++)
2161 reg_cache
[WM8904_MIC_BIAS_CONTROL_0
+ i
]
2162 = pdata
->mic_cfg
[i
];
2165 /* Set Class W by default - this will be managed by the Class
2166 * G widget at runtime where bypass paths are available.
2168 snd_soc_update_bits(codec
, WM8904_CLASS_W_0
,
2169 WM8904_CP_DYN_PWR
, WM8904_CP_DYN_PWR
);
2171 /* Use normal bias source */
2172 snd_soc_update_bits(codec
, WM8904_BIAS_CONTROL_0
,
2175 wm8904_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
2177 /* Bias level configuration will have done an extra enable */
2178 regulator_bulk_disable(ARRAY_SIZE(wm8904
->supplies
), wm8904
->supplies
);
2180 wm8904_handle_pdata(codec
);
2182 wm8904_add_widgets(codec
);
2187 regulator_bulk_disable(ARRAY_SIZE(wm8904
->supplies
), wm8904
->supplies
);
2189 regulator_bulk_free(ARRAY_SIZE(wm8904
->supplies
), wm8904
->supplies
);
2193 static int wm8904_remove(struct snd_soc_codec
*codec
)
2195 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
2197 wm8904_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
2198 regulator_bulk_free(ARRAY_SIZE(wm8904
->supplies
), wm8904
->supplies
);
2199 kfree(wm8904
->retune_mobile_texts
);
2200 kfree(wm8904
->drc_texts
);
2205 static struct snd_soc_codec_driver soc_codec_dev_wm8904
= {
2206 .probe
= wm8904_probe
,
2207 .remove
= wm8904_remove
,
2208 .suspend
= wm8904_suspend
,
2209 .resume
= wm8904_resume
,
2210 .set_bias_level
= wm8904_set_bias_level
,
2213 static const struct regmap_config wm8904_regmap
= {
2217 .max_register
= WM8904_MAX_REGISTER
,
2218 .volatile_reg
= wm8904_volatile_register
,
2219 .readable_reg
= wm8904_readable_register
,
2221 .cache_type
= REGCACHE_RBTREE
,
2222 .reg_defaults
= wm8904_reg_defaults
,
2223 .num_reg_defaults
= ARRAY_SIZE(wm8904_reg_defaults
),
2226 static __devinit
int wm8904_i2c_probe(struct i2c_client
*i2c
,
2227 const struct i2c_device_id
*id
)
2229 struct wm8904_priv
*wm8904
;
2232 wm8904
= devm_kzalloc(&i2c
->dev
, sizeof(struct wm8904_priv
),
2237 wm8904
->regmap
= regmap_init_i2c(i2c
, &wm8904_regmap
);
2238 if (IS_ERR(wm8904
->regmap
)) {
2239 ret
= PTR_ERR(wm8904
->regmap
);
2240 dev_err(&i2c
->dev
, "Failed to allocate register map: %d\n",
2245 wm8904
->devtype
= id
->driver_data
;
2246 i2c_set_clientdata(i2c
, wm8904
);
2247 wm8904
->pdata
= i2c
->dev
.platform_data
;
2249 ret
= snd_soc_register_codec(&i2c
->dev
,
2250 &soc_codec_dev_wm8904
, &wm8904_dai
, 1);
2257 regmap_exit(wm8904
->regmap
);
2261 static __devexit
int wm8904_i2c_remove(struct i2c_client
*client
)
2263 struct wm8904_priv
*wm8904
= i2c_get_clientdata(client
);
2264 snd_soc_unregister_codec(&client
->dev
);
2265 regmap_exit(wm8904
->regmap
);
2269 static const struct i2c_device_id wm8904_i2c_id
[] = {
2270 { "wm8904", WM8904
},
2271 { "wm8912", WM8912
},
2272 { "wm8918", WM8904
}, /* Actually a subset, updates to follow */
2275 MODULE_DEVICE_TABLE(i2c
, wm8904_i2c_id
);
2277 static struct i2c_driver wm8904_i2c_driver
= {
2280 .owner
= THIS_MODULE
,
2282 .probe
= wm8904_i2c_probe
,
2283 .remove
= __devexit_p(wm8904_i2c_remove
),
2284 .id_table
= wm8904_i2c_id
,
2287 static int __init
wm8904_modinit(void)
2290 ret
= i2c_add_driver(&wm8904_i2c_driver
);
2292 printk(KERN_ERR
"Failed to register wm8904 I2C driver: %d\n",
2297 module_init(wm8904_modinit
);
2299 static void __exit
wm8904_exit(void)
2301 i2c_del_driver(&wm8904_i2c_driver
);
2303 module_exit(wm8904_exit
);
2305 MODULE_DESCRIPTION("ASoC WM8904 driver");
2306 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2307 MODULE_LICENSE("GPL");