2 * wm8955.c -- WM8955 ALSA SoC Audio driver
4 * Copyright 2009 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
18 #include <linux/i2c.h>
19 #include <linux/platform_device.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/slab.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29 #include <sound/wm8955.h>
33 #define WM8955_NUM_SUPPLIES 4
34 static const char *wm8955_supply_names
[WM8955_NUM_SUPPLIES
] = {
41 /* codec private data */
43 enum snd_soc_control_type control_type
;
45 unsigned int mclk_rate
;
50 struct regulator_bulk_data supplies
[WM8955_NUM_SUPPLIES
];
53 static const u16 wm8955_reg
[WM8955_MAX_REGISTER
+ 1] = {
56 0x0079, /* R2 - LOUT1 volume */
57 0x0079, /* R3 - ROUT1 volume */
59 0x0008, /* R5 - DAC Control */
61 0x000A, /* R7 - Audio Interface */
62 0x0000, /* R8 - Sample Rate */
64 0x00FF, /* R10 - Left DAC volume */
65 0x00FF, /* R11 - Right DAC volume */
66 0x000F, /* R12 - Bass control */
67 0x000F, /* R13 - Treble control */
69 0x0000, /* R15 - Reset */
77 0x00C1, /* R23 - Additional control (1) */
78 0x0000, /* R24 - Additional control (2) */
79 0x0000, /* R25 - Power Management (1) */
80 0x0000, /* R26 - Power Management (2) */
81 0x0000, /* R27 - Additional Control (3) */
88 0x0050, /* R34 - Left out Mix (1) */
89 0x0050, /* R35 - Left out Mix (2) */
90 0x0050, /* R36 - Right out Mix (1) */
91 0x0050, /* R37 - Right Out Mix (2) */
92 0x0050, /* R38 - Mono out Mix (1) */
93 0x0050, /* R39 - Mono out Mix (2) */
94 0x0079, /* R40 - LOUT2 volume */
95 0x0079, /* R41 - ROUT2 volume */
96 0x0079, /* R42 - MONOOUT volume */
97 0x0000, /* R43 - Clocking / PLL */
98 0x0103, /* R44 - PLL Control 1 */
99 0x0024, /* R45 - PLL Control 2 */
100 0x01BA, /* R46 - PLL Control 3 */
113 0x0000, /* R59 - PLL Control 4 */
116 static int wm8955_reset(struct snd_soc_codec
*codec
)
118 return snd_soc_write(codec
, WM8955_RESET
, 0);
127 /* The size in bits of the FLL divide multiplied by 10
128 * to allow rounding later */
129 #define FIXED_FLL_SIZE ((1 << 22) * 10)
131 static int wm8995_pll_factors(struct device
*dev
,
132 int Fref
, int Fout
, struct pll_factors
*pll
)
135 unsigned int K
, Ndiv
, Nmod
, target
;
137 dev_dbg(dev
, "Fref=%u Fout=%u\n", Fref
, Fout
);
139 /* The oscilator should run at should be 90-100MHz, and
140 * there's a divide by 4 plus an optional divide by 2 in the
141 * output path to generate the system clock. The clock table
142 * is sortd so we should always generate a suitable target. */
144 if (target
< 90000000) {
151 WARN_ON(target
< 90000000 || target
> 100000000);
153 dev_dbg(dev
, "Fvco=%dHz\n", target
);
155 /* Now, calculate N.K */
156 Ndiv
= target
/ Fref
;
159 Nmod
= target
% Fref
;
160 dev_dbg(dev
, "Nmod=%d\n", Nmod
);
162 /* Calculate fractional part - scale up so we can round. */
163 Kpart
= FIXED_FLL_SIZE
* (long long)Nmod
;
167 K
= Kpart
& 0xFFFFFFFF;
172 /* Move down to proper range now rounding is done */
175 dev_dbg(dev
, "N=%x K=%x OUTDIV=%x\n", pll
->n
, pll
->k
, pll
->outdiv
);
180 /* Lookup table specifiying SRATE (table 25 in datasheet); some of the
181 * output frequencies have been rounded to the standard frequencies
182 * they are intended to match where the error is slight. */
189 { 18432000, 8000, 0, 3, },
190 { 18432000, 12000, 0, 9, },
191 { 18432000, 16000, 0, 11, },
192 { 18432000, 24000, 0, 29, },
193 { 18432000, 32000, 0, 13, },
194 { 18432000, 48000, 0, 1, },
195 { 18432000, 96000, 0, 15, },
197 { 16934400, 8018, 0, 19, },
198 { 16934400, 11025, 0, 25, },
199 { 16934400, 22050, 0, 27, },
200 { 16934400, 44100, 0, 17, },
201 { 16934400, 88200, 0, 31, },
203 { 12000000, 8000, 1, 2, },
204 { 12000000, 11025, 1, 25, },
205 { 12000000, 12000, 1, 8, },
206 { 12000000, 16000, 1, 10, },
207 { 12000000, 22050, 1, 27, },
208 { 12000000, 24000, 1, 28, },
209 { 12000000, 32000, 1, 12, },
210 { 12000000, 44100, 1, 17, },
211 { 12000000, 48000, 1, 0, },
212 { 12000000, 88200, 1, 31, },
213 { 12000000, 96000, 1, 14, },
215 { 12288000, 8000, 0, 2, },
216 { 12288000, 12000, 0, 8, },
217 { 12288000, 16000, 0, 10, },
218 { 12288000, 24000, 0, 28, },
219 { 12288000, 32000, 0, 12, },
220 { 12288000, 48000, 0, 0, },
221 { 12288000, 96000, 0, 14, },
223 { 12289600, 8018, 0, 18, },
224 { 12289600, 11025, 0, 24, },
225 { 12289600, 22050, 0, 26, },
226 { 11289600, 44100, 0, 16, },
227 { 11289600, 88200, 0, 31, },
230 static int wm8955_configure_clocking(struct snd_soc_codec
*codec
)
232 struct wm8955_priv
*wm8955
= snd_soc_codec_get_drvdata(codec
);
237 struct pll_factors pll
;
239 /* If we're not running a sample rate currently just pick one */
243 /* Can we generate an exact output? */
244 for (i
= 0; i
< ARRAY_SIZE(clock_cfgs
); i
++) {
245 if (wm8955
->fs
!= clock_cfgs
[i
].fs
)
249 if (wm8955
->mclk_rate
== clock_cfgs
[i
].mclk
)
253 /* We should never get here with an unsupported sample rate */
255 dev_err(codec
->dev
, "Sample rate %dHz unsupported\n",
261 if (i
== ARRAY_SIZE(clock_cfgs
)) {
262 /* If we can't generate the right clock from MCLK then
263 * we should configure the PLL to supply us with an
266 clocking
|= WM8955_MCLKSEL
;
268 /* Use the last divider configuration we saw for the
270 ret
= wm8995_pll_factors(codec
->dev
, wm8955
->mclk_rate
,
271 clock_cfgs
[sr
].mclk
, &pll
);
274 "Unable to generate %dHz from %dHz MCLK\n",
275 wm8955
->fs
, wm8955
->mclk_rate
);
279 snd_soc_update_bits(codec
, WM8955_PLL_CONTROL_1
,
280 WM8955_N_MASK
| WM8955_K_21_18_MASK
,
281 (pll
.n
<< WM8955_N_SHIFT
) |
283 snd_soc_update_bits(codec
, WM8955_PLL_CONTROL_2
,
285 (pll
.k
>> 9) & WM8955_K_17_9_MASK
);
286 snd_soc_update_bits(codec
, WM8955_PLL_CONTROL_2
,
288 pll
.k
& WM8955_K_8_0_MASK
);
290 snd_soc_update_bits(codec
, WM8955_PLL_CONTROL_4
,
291 WM8955_KEN
, WM8955_KEN
);
293 snd_soc_update_bits(codec
, WM8955_PLL_CONTROL_4
,
297 val
= WM8955_PLL_RB
| WM8955_PLLOUTDIV2
;
301 /* Now start the PLL running */
302 snd_soc_update_bits(codec
, WM8955_CLOCKING_PLL
,
303 WM8955_PLL_RB
| WM8955_PLLOUTDIV2
, val
);
304 snd_soc_update_bits(codec
, WM8955_CLOCKING_PLL
,
305 WM8955_PLLEN
, WM8955_PLLEN
);
308 srate
= clock_cfgs
[sr
].usb
| (clock_cfgs
[sr
].sr
<< WM8955_SR_SHIFT
);
310 snd_soc_update_bits(codec
, WM8955_SAMPLE_RATE
,
311 WM8955_USB
| WM8955_SR_MASK
, srate
);
312 snd_soc_update_bits(codec
, WM8955_CLOCKING_PLL
,
313 WM8955_MCLKSEL
, clocking
);
318 static int wm8955_sysclk(struct snd_soc_dapm_widget
*w
,
319 struct snd_kcontrol
*kcontrol
, int event
)
321 struct snd_soc_codec
*codec
= w
->codec
;
324 /* Always disable the clocks - if we're doing reconfiguration this
325 * avoids misclocking.
327 snd_soc_update_bits(codec
, WM8955_POWER_MANAGEMENT_1
,
329 snd_soc_update_bits(codec
, WM8955_CLOCKING_PLL
,
330 WM8955_PLL_RB
| WM8955_PLLEN
, 0);
333 case SND_SOC_DAPM_POST_PMD
:
335 case SND_SOC_DAPM_PRE_PMU
:
336 ret
= wm8955_configure_clocking(codec
);
346 static int deemph_settings
[] = { 0, 32000, 44100, 48000 };
348 static int wm8955_set_deemph(struct snd_soc_codec
*codec
)
350 struct wm8955_priv
*wm8955
= snd_soc_codec_get_drvdata(codec
);
353 /* If we're using deemphasis select the nearest available sample
356 if (wm8955
->deemph
) {
358 for (i
= 2; i
< ARRAY_SIZE(deemph_settings
); i
++) {
359 if (abs(deemph_settings
[i
] - wm8955
->fs
) <
360 abs(deemph_settings
[best
] - wm8955
->fs
))
364 val
= best
<< WM8955_DEEMPH_SHIFT
;
369 dev_dbg(codec
->dev
, "Set deemphasis %d\n", val
);
371 return snd_soc_update_bits(codec
, WM8955_DAC_CONTROL
,
372 WM8955_DEEMPH_MASK
, val
);
375 static int wm8955_get_deemph(struct snd_kcontrol
*kcontrol
,
376 struct snd_ctl_elem_value
*ucontrol
)
378 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
379 struct wm8955_priv
*wm8955
= snd_soc_codec_get_drvdata(codec
);
381 ucontrol
->value
.enumerated
.item
[0] = wm8955
->deemph
;
385 static int wm8955_put_deemph(struct snd_kcontrol
*kcontrol
,
386 struct snd_ctl_elem_value
*ucontrol
)
388 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
389 struct wm8955_priv
*wm8955
= snd_soc_codec_get_drvdata(codec
);
390 int deemph
= ucontrol
->value
.enumerated
.item
[0];
395 wm8955
->deemph
= deemph
;
397 return wm8955_set_deemph(codec
);
400 static const char *bass_mode_text
[] = {
401 "Linear", "Adaptive",
404 static const struct soc_enum bass_mode
=
405 SOC_ENUM_SINGLE(WM8955_BASS_CONTROL
, 7, 2, bass_mode_text
);
407 static const char *bass_cutoff_text
[] = {
411 static const struct soc_enum bass_cutoff
=
412 SOC_ENUM_SINGLE(WM8955_BASS_CONTROL
, 6, 2, bass_cutoff_text
);
414 static const char *treble_cutoff_text
[] = {
418 static const struct soc_enum treble_cutoff
=
419 SOC_ENUM_SINGLE(WM8955_TREBLE_CONTROL
, 6, 2, treble_cutoff_text
);
421 static const DECLARE_TLV_DB_SCALE(digital_tlv
, -12750, 50, 1);
422 static const DECLARE_TLV_DB_SCALE(atten_tlv
, -600, 600, 0);
423 static const DECLARE_TLV_DB_SCALE(bypass_tlv
, -1500, 300, 0);
424 static const DECLARE_TLV_DB_SCALE(mono_tlv
, -2100, 300, 0);
425 static const DECLARE_TLV_DB_SCALE(out_tlv
, -12100, 100, 1);
426 static const DECLARE_TLV_DB_SCALE(treble_tlv
, -1200, 150, 1);
428 static const struct snd_kcontrol_new wm8955_snd_controls
[] = {
429 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8955_LEFT_DAC_VOLUME
,
430 WM8955_RIGHT_DAC_VOLUME
, 0, 255, 0, digital_tlv
),
431 SOC_SINGLE_TLV("Playback Attenuation Volume", WM8955_DAC_CONTROL
, 7, 1, 1,
433 SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
434 wm8955_get_deemph
, wm8955_put_deemph
),
436 SOC_ENUM("Bass Mode", bass_mode
),
437 SOC_ENUM("Bass Cutoff", bass_cutoff
),
438 SOC_SINGLE("Bass Volume", WM8955_BASS_CONTROL
, 0, 15, 1),
440 SOC_ENUM("Treble Cutoff", treble_cutoff
),
441 SOC_SINGLE_TLV("Treble Volume", WM8955_TREBLE_CONTROL
, 0, 14, 1, treble_tlv
),
443 SOC_SINGLE_TLV("Left Bypass Volume", WM8955_LEFT_OUT_MIX_1
, 4, 7, 1,
445 SOC_SINGLE_TLV("Left Mono Volume", WM8955_LEFT_OUT_MIX_2
, 4, 7, 1,
448 SOC_SINGLE_TLV("Right Mono Volume", WM8955_RIGHT_OUT_MIX_1
, 4, 7, 1,
450 SOC_SINGLE_TLV("Right Bypass Volume", WM8955_RIGHT_OUT_MIX_2
, 4, 7, 1,
453 /* Not a stereo pair so they line up with the DAPM switches */
454 SOC_SINGLE_TLV("Mono Left Bypass Volume", WM8955_MONO_OUT_MIX_1
, 4, 7, 1,
456 SOC_SINGLE_TLV("Mono Right Bypass Volume", WM8955_MONO_OUT_MIX_2
, 4, 7, 1,
459 SOC_DOUBLE_R_TLV("Headphone Volume", WM8955_LOUT1_VOLUME
,
460 WM8955_ROUT1_VOLUME
, 0, 127, 0, out_tlv
),
461 SOC_DOUBLE_R("Headphone ZC Switch", WM8955_LOUT1_VOLUME
,
462 WM8955_ROUT1_VOLUME
, 7, 1, 0),
464 SOC_DOUBLE_R_TLV("Speaker Volume", WM8955_LOUT2_VOLUME
,
465 WM8955_ROUT2_VOLUME
, 0, 127, 0, out_tlv
),
466 SOC_DOUBLE_R("Speaker ZC Switch", WM8955_LOUT2_VOLUME
,
467 WM8955_ROUT2_VOLUME
, 7, 1, 0),
469 SOC_SINGLE_TLV("Mono Volume", WM8955_MONOOUT_VOLUME
, 0, 127, 0, out_tlv
),
470 SOC_SINGLE("Mono ZC Switch", WM8955_MONOOUT_VOLUME
, 7, 1, 0),
473 static const struct snd_kcontrol_new lmixer
[] = {
474 SOC_DAPM_SINGLE("Playback Switch", WM8955_LEFT_OUT_MIX_1
, 8, 1, 0),
475 SOC_DAPM_SINGLE("Bypass Switch", WM8955_LEFT_OUT_MIX_1
, 7, 1, 0),
476 SOC_DAPM_SINGLE("Right Playback Switch", WM8955_LEFT_OUT_MIX_2
, 8, 1, 0),
477 SOC_DAPM_SINGLE("Mono Switch", WM8955_LEFT_OUT_MIX_2
, 7, 1, 0),
480 static const struct snd_kcontrol_new rmixer
[] = {
481 SOC_DAPM_SINGLE("Left Playback Switch", WM8955_RIGHT_OUT_MIX_1
, 8, 1, 0),
482 SOC_DAPM_SINGLE("Mono Switch", WM8955_RIGHT_OUT_MIX_1
, 7, 1, 0),
483 SOC_DAPM_SINGLE("Playback Switch", WM8955_RIGHT_OUT_MIX_2
, 8, 1, 0),
484 SOC_DAPM_SINGLE("Bypass Switch", WM8955_RIGHT_OUT_MIX_2
, 7, 1, 0),
487 static const struct snd_kcontrol_new mmixer
[] = {
488 SOC_DAPM_SINGLE("Left Playback Switch", WM8955_MONO_OUT_MIX_1
, 8, 1, 0),
489 SOC_DAPM_SINGLE("Left Bypass Switch", WM8955_MONO_OUT_MIX_1
, 7, 1, 0),
490 SOC_DAPM_SINGLE("Right Playback Switch", WM8955_MONO_OUT_MIX_2
, 8, 1, 0),
491 SOC_DAPM_SINGLE("Right Bypass Switch", WM8955_MONO_OUT_MIX_2
, 7, 1, 0),
494 static const struct snd_soc_dapm_widget wm8955_dapm_widgets
[] = {
495 SND_SOC_DAPM_INPUT("MONOIN-"),
496 SND_SOC_DAPM_INPUT("MONOIN+"),
497 SND_SOC_DAPM_INPUT("LINEINR"),
498 SND_SOC_DAPM_INPUT("LINEINL"),
500 SND_SOC_DAPM_PGA("Mono Input", SND_SOC_NOPM
, 0, 0, NULL
, 0),
502 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8955_POWER_MANAGEMENT_1
, 0, 1, wm8955_sysclk
,
503 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
504 SND_SOC_DAPM_SUPPLY("TSDEN", WM8955_ADDITIONAL_CONTROL_1
, 8, 0, NULL
, 0),
506 SND_SOC_DAPM_DAC("DACL", "Playback", WM8955_POWER_MANAGEMENT_2
, 8, 0),
507 SND_SOC_DAPM_DAC("DACR", "Playback", WM8955_POWER_MANAGEMENT_2
, 7, 0),
509 SND_SOC_DAPM_PGA("LOUT1 PGA", WM8955_POWER_MANAGEMENT_2
, 6, 0, NULL
, 0),
510 SND_SOC_DAPM_PGA("ROUT1 PGA", WM8955_POWER_MANAGEMENT_2
, 5, 0, NULL
, 0),
511 SND_SOC_DAPM_PGA("LOUT2 PGA", WM8955_POWER_MANAGEMENT_2
, 4, 0, NULL
, 0),
512 SND_SOC_DAPM_PGA("ROUT2 PGA", WM8955_POWER_MANAGEMENT_2
, 3, 0, NULL
, 0),
513 SND_SOC_DAPM_PGA("MOUT PGA", WM8955_POWER_MANAGEMENT_2
, 2, 0, NULL
, 0),
514 SND_SOC_DAPM_PGA("OUT3 PGA", WM8955_POWER_MANAGEMENT_2
, 1, 0, NULL
, 0),
516 /* The names are chosen to make the control names nice */
517 SND_SOC_DAPM_MIXER("Left", SND_SOC_NOPM
, 0, 0,
518 lmixer
, ARRAY_SIZE(lmixer
)),
519 SND_SOC_DAPM_MIXER("Right", SND_SOC_NOPM
, 0, 0,
520 rmixer
, ARRAY_SIZE(rmixer
)),
521 SND_SOC_DAPM_MIXER("Mono", SND_SOC_NOPM
, 0, 0,
522 mmixer
, ARRAY_SIZE(mmixer
)),
524 SND_SOC_DAPM_OUTPUT("LOUT1"),
525 SND_SOC_DAPM_OUTPUT("ROUT1"),
526 SND_SOC_DAPM_OUTPUT("LOUT2"),
527 SND_SOC_DAPM_OUTPUT("ROUT2"),
528 SND_SOC_DAPM_OUTPUT("MONOOUT"),
529 SND_SOC_DAPM_OUTPUT("OUT3"),
532 static const struct snd_soc_dapm_route wm8955_intercon
[] = {
533 { "DACL", NULL
, "SYSCLK" },
534 { "DACR", NULL
, "SYSCLK" },
536 { "Mono Input", NULL
, "MONOIN-" },
537 { "Mono Input", NULL
, "MONOIN+" },
539 { "Left", "Playback Switch", "DACL" },
540 { "Left", "Right Playback Switch", "DACR" },
541 { "Left", "Bypass Switch", "LINEINL" },
542 { "Left", "Mono Switch", "Mono Input" },
544 { "Right", "Playback Switch", "DACR" },
545 { "Right", "Left Playback Switch", "DACL" },
546 { "Right", "Bypass Switch", "LINEINR" },
547 { "Right", "Mono Switch", "Mono Input" },
549 { "Mono", "Left Playback Switch", "DACL" },
550 { "Mono", "Right Playback Switch", "DACR" },
551 { "Mono", "Left Bypass Switch", "LINEINL" },
552 { "Mono", "Right Bypass Switch", "LINEINR" },
554 { "LOUT1 PGA", NULL
, "Left" },
555 { "LOUT1", NULL
, "TSDEN" },
556 { "LOUT1", NULL
, "LOUT1 PGA" },
558 { "ROUT1 PGA", NULL
, "Right" },
559 { "ROUT1", NULL
, "TSDEN" },
560 { "ROUT1", NULL
, "ROUT1 PGA" },
562 { "LOUT2 PGA", NULL
, "Left" },
563 { "LOUT2", NULL
, "TSDEN" },
564 { "LOUT2", NULL
, "LOUT2 PGA" },
566 { "ROUT2 PGA", NULL
, "Right" },
567 { "ROUT2", NULL
, "TSDEN" },
568 { "ROUT2", NULL
, "ROUT2 PGA" },
570 { "MOUT PGA", NULL
, "Mono" },
571 { "MONOOUT", NULL
, "MOUT PGA" },
573 /* OUT3 not currently implemented */
574 { "OUT3", NULL
, "OUT3 PGA" },
577 static int wm8955_add_widgets(struct snd_soc_codec
*codec
)
579 snd_soc_add_controls(codec
, wm8955_snd_controls
,
580 ARRAY_SIZE(wm8955_snd_controls
));
582 snd_soc_dapm_new_controls(codec
, wm8955_dapm_widgets
,
583 ARRAY_SIZE(wm8955_dapm_widgets
));
585 snd_soc_dapm_add_routes(codec
, wm8955_intercon
,
586 ARRAY_SIZE(wm8955_intercon
));
591 static int wm8955_hw_params(struct snd_pcm_substream
*substream
,
592 struct snd_pcm_hw_params
*params
,
593 struct snd_soc_dai
*dai
)
595 struct snd_soc_codec
*codec
= dai
->codec
;
596 struct wm8955_priv
*wm8955
= snd_soc_codec_get_drvdata(codec
);
600 switch (params_format(params
)) {
601 case SNDRV_PCM_FORMAT_S16_LE
:
604 case SNDRV_PCM_FORMAT_S20_3LE
:
607 case SNDRV_PCM_FORMAT_S24_LE
:
610 case SNDRV_PCM_FORMAT_S32_LE
:
616 snd_soc_update_bits(codec
, WM8955_AUDIO_INTERFACE
,
619 wm8955
->fs
= params_rate(params
);
620 wm8955_set_deemph(codec
);
622 /* If the chip is clocked then disable the clocks and force a
623 * reconfiguration, otherwise DAPM will power up the
624 * clocks for us later. */
625 ret
= snd_soc_read(codec
, WM8955_POWER_MANAGEMENT_1
);
628 if (ret
& WM8955_DIGENB
) {
629 snd_soc_update_bits(codec
, WM8955_POWER_MANAGEMENT_1
,
631 snd_soc_update_bits(codec
, WM8955_CLOCKING_PLL
,
632 WM8955_PLL_RB
| WM8955_PLLEN
, 0);
634 wm8955_configure_clocking(codec
);
641 static int wm8955_set_sysclk(struct snd_soc_dai
*dai
, int clk_id
,
642 unsigned int freq
, int dir
)
644 struct snd_soc_codec
*codec
= dai
->codec
;
645 struct wm8955_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
649 case WM8955_CLK_MCLK
:
650 if (freq
> 15000000) {
651 priv
->mclk_rate
= freq
/= 2;
652 div
= WM8955_MCLKDIV2
;
654 priv
->mclk_rate
= freq
;
658 snd_soc_update_bits(codec
, WM8955_SAMPLE_RATE
,
659 WM8955_MCLKDIV2
, div
);
666 dev_dbg(dai
->dev
, "Clock source is %d at %uHz\n", clk_id
, freq
);
671 static int wm8955_set_fmt(struct snd_soc_dai
*dai
, unsigned int fmt
)
673 struct snd_soc_codec
*codec
= dai
->codec
;
676 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
677 case SND_SOC_DAIFMT_CBS_CFS
:
679 case SND_SOC_DAIFMT_CBM_CFM
:
686 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
687 case SND_SOC_DAIFMT_DSP_B
:
689 case SND_SOC_DAIFMT_DSP_A
:
692 case SND_SOC_DAIFMT_I2S
:
695 case SND_SOC_DAIFMT_RIGHT_J
:
697 case SND_SOC_DAIFMT_LEFT_J
:
704 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
705 case SND_SOC_DAIFMT_DSP_A
:
706 case SND_SOC_DAIFMT_DSP_B
:
707 /* frame inversion not valid for DSP modes */
708 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
709 case SND_SOC_DAIFMT_NB_NF
:
711 case SND_SOC_DAIFMT_IB_NF
:
712 aif
|= WM8955_BCLKINV
;
719 case SND_SOC_DAIFMT_I2S
:
720 case SND_SOC_DAIFMT_RIGHT_J
:
721 case SND_SOC_DAIFMT_LEFT_J
:
722 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
723 case SND_SOC_DAIFMT_NB_NF
:
725 case SND_SOC_DAIFMT_IB_IF
:
726 aif
|= WM8955_BCLKINV
| WM8955_LRP
;
728 case SND_SOC_DAIFMT_IB_NF
:
729 aif
|= WM8955_BCLKINV
;
731 case SND_SOC_DAIFMT_NB_IF
:
742 snd_soc_update_bits(codec
, WM8955_AUDIO_INTERFACE
,
743 WM8955_MS
| WM8955_FORMAT_MASK
| WM8955_BCLKINV
|
750 static int wm8955_digital_mute(struct snd_soc_dai
*codec_dai
, int mute
)
752 struct snd_soc_codec
*codec
= codec_dai
->codec
;
760 snd_soc_update_bits(codec
, WM8955_DAC_CONTROL
, WM8955_DACMU
, val
);
765 static int wm8955_set_bias_level(struct snd_soc_codec
*codec
,
766 enum snd_soc_bias_level level
)
768 struct wm8955_priv
*wm8955
= snd_soc_codec_get_drvdata(codec
);
769 u16
*reg_cache
= codec
->reg_cache
;
773 case SND_SOC_BIAS_ON
:
776 case SND_SOC_BIAS_PREPARE
:
777 /* VMID resistance 2*50k */
778 snd_soc_update_bits(codec
, WM8955_POWER_MANAGEMENT_1
,
780 0x1 << WM8955_VMIDSEL_SHIFT
);
782 /* Default bias current */
783 snd_soc_update_bits(codec
, WM8955_ADDITIONAL_CONTROL_1
,
785 0x2 << WM8955_VSEL_SHIFT
);
788 case SND_SOC_BIAS_STANDBY
:
789 if (codec
->bias_level
== SND_SOC_BIAS_OFF
) {
790 ret
= regulator_bulk_enable(ARRAY_SIZE(wm8955
->supplies
),
794 "Failed to enable supplies: %d\n",
799 /* Sync back cached values if they're
800 * different from the hardware default.
802 for (i
= 0; i
< codec
->driver
->reg_cache_size
; i
++) {
803 if (i
== WM8955_RESET
)
806 if (reg_cache
[i
] == wm8955_reg
[i
])
809 snd_soc_write(codec
, i
, reg_cache
[i
]);
812 /* Enable VREF and VMID */
813 snd_soc_update_bits(codec
, WM8955_POWER_MANAGEMENT_1
,
817 0x3 << WM8955_VREF_SHIFT
);
822 /* High resistance VROI to maintain outputs */
823 snd_soc_update_bits(codec
,
824 WM8955_ADDITIONAL_CONTROL_3
,
825 WM8955_VROI
, WM8955_VROI
);
828 /* Maintain VMID with 2*250k */
829 snd_soc_update_bits(codec
, WM8955_POWER_MANAGEMENT_1
,
831 0x2 << WM8955_VMIDSEL_SHIFT
);
833 /* Minimum bias current */
834 snd_soc_update_bits(codec
, WM8955_ADDITIONAL_CONTROL_1
,
835 WM8955_VSEL_MASK
, 0);
838 case SND_SOC_BIAS_OFF
:
839 /* Low resistance VROI to help discharge */
840 snd_soc_update_bits(codec
,
841 WM8955_ADDITIONAL_CONTROL_3
,
844 /* Turn off VMID and VREF */
845 snd_soc_update_bits(codec
, WM8955_POWER_MANAGEMENT_1
,
847 WM8955_VMIDSEL_MASK
, 0);
849 regulator_bulk_disable(ARRAY_SIZE(wm8955
->supplies
),
853 codec
->bias_level
= level
;
857 #define WM8955_RATES SNDRV_PCM_RATE_8000_96000
859 #define WM8955_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
860 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
862 static struct snd_soc_dai_ops wm8955_dai_ops
= {
863 .set_sysclk
= wm8955_set_sysclk
,
864 .set_fmt
= wm8955_set_fmt
,
865 .hw_params
= wm8955_hw_params
,
866 .digital_mute
= wm8955_digital_mute
,
869 static struct snd_soc_dai_driver wm8955_dai
= {
870 .name
= "wm8955-hifi",
872 .stream_name
= "Playback",
875 .rates
= WM8955_RATES
,
876 .formats
= WM8955_FORMATS
,
878 .ops
= &wm8955_dai_ops
,
882 static int wm8955_suspend(struct snd_soc_codec
*codec
, pm_message_t state
)
884 wm8955_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
889 static int wm8955_resume(struct snd_soc_codec
*codec
)
891 wm8955_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
896 #define wm8955_suspend NULL
897 #define wm8955_resume NULL
900 static int wm8955_probe(struct snd_soc_codec
*codec
)
902 struct wm8955_priv
*wm8955
= snd_soc_codec_get_drvdata(codec
);
903 struct wm8955_pdata
*pdata
= dev_get_platdata(codec
->dev
);
904 u16
*reg_cache
= codec
->reg_cache
;
907 ret
= snd_soc_codec_set_cache_io(codec
, 7, 9, wm8955
->control_type
);
909 dev_err(codec
->dev
, "Failed to set cache I/O: %d\n", ret
);
913 for (i
= 0; i
< ARRAY_SIZE(wm8955
->supplies
); i
++)
914 wm8955
->supplies
[i
].supply
= wm8955_supply_names
[i
];
916 ret
= regulator_bulk_get(codec
->dev
, ARRAY_SIZE(wm8955
->supplies
),
919 dev_err(codec
->dev
, "Failed to request supplies: %d\n", ret
);
923 ret
= regulator_bulk_enable(ARRAY_SIZE(wm8955
->supplies
),
926 dev_err(codec
->dev
, "Failed to enable supplies: %d\n", ret
);
930 ret
= wm8955_reset(codec
);
932 dev_err(codec
->dev
, "Failed to issue reset: %d\n", ret
);
936 /* Change some default settings - latch VU and enable ZC */
937 reg_cache
[WM8955_LEFT_DAC_VOLUME
] |= WM8955_LDVU
;
938 reg_cache
[WM8955_RIGHT_DAC_VOLUME
] |= WM8955_RDVU
;
939 reg_cache
[WM8955_LOUT1_VOLUME
] |= WM8955_LO1VU
| WM8955_LO1ZC
;
940 reg_cache
[WM8955_ROUT1_VOLUME
] |= WM8955_RO1VU
| WM8955_RO1ZC
;
941 reg_cache
[WM8955_LOUT2_VOLUME
] |= WM8955_LO2VU
| WM8955_LO2ZC
;
942 reg_cache
[WM8955_ROUT2_VOLUME
] |= WM8955_RO2VU
| WM8955_RO2ZC
;
943 reg_cache
[WM8955_MONOOUT_VOLUME
] |= WM8955_MOZC
;
945 /* Also enable adaptive bass boost by default */
946 reg_cache
[WM8955_BASS_CONTROL
] |= WM8955_BB
;
948 /* Set platform data values */
950 if (pdata
->out2_speaker
)
951 reg_cache
[WM8955_ADDITIONAL_CONTROL_2
]
954 if (pdata
->monoin_diff
)
955 reg_cache
[WM8955_MONO_OUT_MIX_1
]
959 wm8955_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
961 /* Bias level configuration will have done an extra enable */
962 regulator_bulk_disable(ARRAY_SIZE(wm8955
->supplies
), wm8955
->supplies
);
964 wm8955_add_widgets(codec
);
968 regulator_bulk_disable(ARRAY_SIZE(wm8955
->supplies
), wm8955
->supplies
);
970 regulator_bulk_free(ARRAY_SIZE(wm8955
->supplies
), wm8955
->supplies
);
974 static int wm8955_remove(struct snd_soc_codec
*codec
)
976 struct wm8955_priv
*wm8955
= snd_soc_codec_get_drvdata(codec
);
978 wm8955_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
979 regulator_bulk_free(ARRAY_SIZE(wm8955
->supplies
), wm8955
->supplies
);
983 static struct snd_soc_codec_driver soc_codec_dev_wm8955
= {
984 .probe
= wm8955_probe
,
985 .remove
= wm8955_remove
,
986 .suspend
= wm8955_suspend
,
987 .resume
= wm8955_resume
,
988 .set_bias_level
= wm8955_set_bias_level
,
989 .reg_cache_size
= ARRAY_SIZE(wm8955_reg
),
990 .reg_word_size
= sizeof(u16
),
991 .reg_cache_default
= wm8955_reg
,
994 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
995 static __devinit
int wm8955_i2c_probe(struct i2c_client
*i2c
,
996 const struct i2c_device_id
*id
)
998 struct wm8955_priv
*wm8955
;
1001 wm8955
= kzalloc(sizeof(struct wm8955_priv
), GFP_KERNEL
);
1005 i2c_set_clientdata(i2c
, wm8955
);
1006 wm8955
->control_type
= SND_SOC_I2C
;
1008 ret
= snd_soc_register_codec(&i2c
->dev
,
1009 &soc_codec_dev_wm8955
, &wm8955_dai
, 1);
1015 static __devexit
int wm8955_i2c_remove(struct i2c_client
*client
)
1017 snd_soc_unregister_codec(&client
->dev
);
1018 kfree(i2c_get_clientdata(client
));
1022 static const struct i2c_device_id wm8955_i2c_id
[] = {
1026 MODULE_DEVICE_TABLE(i2c
, wm8955_i2c_id
);
1028 static struct i2c_driver wm8955_i2c_driver
= {
1030 .name
= "wm8955-codec",
1031 .owner
= THIS_MODULE
,
1033 .probe
= wm8955_i2c_probe
,
1034 .remove
= __devexit_p(wm8955_i2c_remove
),
1035 .id_table
= wm8955_i2c_id
,
1039 static int __init
wm8955_modinit(void)
1042 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1043 ret
= i2c_add_driver(&wm8955_i2c_driver
);
1045 printk(KERN_ERR
"Failed to register WM8955 I2C driver: %d\n",
1051 module_init(wm8955_modinit
);
1053 static void __exit
wm8955_exit(void)
1055 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1056 i2c_del_driver(&wm8955_i2c_driver
);
1059 module_exit(wm8955_exit
);
1061 MODULE_DESCRIPTION("ASoC WM8955 driver");
1062 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1063 MODULE_LICENSE("GPL");