projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
ASoC: Decouple DAPM from CODECs
[deliverable/linux.git] / sound / soc / codecs / wm8955.c
1 /*
2 * wm8955.c -- WM8955 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/pm.h>
18 #include <linux/i2c.h>
19 #include <linux/platform_device.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/slab.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29 #include <sound/wm8955.h>
30
31 #include "wm8955.h"
32
33 #define WM8955_NUM_SUPPLIES 4
34 static const char *wm8955_supply_names[WM8955_NUM_SUPPLIES] = {
35 "DCVDD",
36 "DBVDD",
37 "HPVDD",
38 "AVDD",
39 };
40
41 /* codec private data */
42 struct wm8955_priv {
43 enum snd_soc_control_type control_type;
44
45 u16 reg_cache[WM8955_MAX_REGISTER + 1];
46
47 unsigned int mclk_rate;
48
49 int deemph;
50 int fs;
51
52 struct regulator_bulk_data supplies[WM8955_NUM_SUPPLIES];
53 };
54
55 static const u16 wm8955_reg[WM8955_MAX_REGISTER + 1] = {
56 0x0000, /* R0 */
57 0x0000, /* R1 */
58 0x0079, /* R2 - LOUT1 volume */
59 0x0079, /* R3 - ROUT1 volume */
60 0x0000, /* R4 */
61 0x0008, /* R5 - DAC Control */
62 0x0000, /* R6 */
63 0x000A, /* R7 - Audio Interface */
64 0x0000, /* R8 - Sample Rate */
65 0x0000, /* R9 */
66 0x00FF, /* R10 - Left DAC volume */
67 0x00FF, /* R11 - Right DAC volume */
68 0x000F, /* R12 - Bass control */
69 0x000F, /* R13 - Treble control */
70 0x0000, /* R14 */
71 0x0000, /* R15 - Reset */
72 0x0000, /* R16 */
73 0x0000, /* R17 */
74 0x0000, /* R18 */
75 0x0000, /* R19 */
76 0x0000, /* R20 */
77 0x0000, /* R21 */
78 0x0000, /* R22 */
79 0x00C1, /* R23 - Additional control (1) */
80 0x0000, /* R24 - Additional control (2) */
81 0x0000, /* R25 - Power Management (1) */
82 0x0000, /* R26 - Power Management (2) */
83 0x0000, /* R27 - Additional Control (3) */
84 0x0000, /* R28 */
85 0x0000, /* R29 */
86 0x0000, /* R30 */
87 0x0000, /* R31 */
88 0x0000, /* R32 */
89 0x0000, /* R33 */
90 0x0050, /* R34 - Left out Mix (1) */
91 0x0050, /* R35 - Left out Mix (2) */
92 0x0050, /* R36 - Right out Mix (1) */
93 0x0050, /* R37 - Right Out Mix (2) */
94 0x0050, /* R38 - Mono out Mix (1) */
95 0x0050, /* R39 - Mono out Mix (2) */
96 0x0079, /* R40 - LOUT2 volume */
97 0x0079, /* R41 - ROUT2 volume */
98 0x0079, /* R42 - MONOOUT volume */
99 0x0000, /* R43 - Clocking / PLL */
100 0x0103, /* R44 - PLL Control 1 */
101 0x0024, /* R45 - PLL Control 2 */
102 0x01BA, /* R46 - PLL Control 3 */
103 0x0000, /* R47 */
104 0x0000, /* R48 */
105 0x0000, /* R49 */
106 0x0000, /* R50 */
107 0x0000, /* R51 */
108 0x0000, /* R52 */
109 0x0000, /* R53 */
110 0x0000, /* R54 */
111 0x0000, /* R55 */
112 0x0000, /* R56 */
113 0x0000, /* R57 */
114 0x0000, /* R58 */
115 0x0000, /* R59 - PLL Control 4 */
116 };
117
118 static int wm8955_reset(struct snd_soc_codec *codec)
119 {
120 return snd_soc_write(codec, WM8955_RESET, 0);
121 }
122
123 struct pll_factors {
124 int n;
125 int k;
126 int outdiv;
127 };
128
129 /* The size in bits of the FLL divide multiplied by 10
130 * to allow rounding later */
131 #define FIXED_FLL_SIZE ((1 << 22) * 10)
132
133 static int wm8995_pll_factors(struct device *dev,
134 int Fref, int Fout, struct pll_factors *pll)
135 {
136 u64 Kpart;
137 unsigned int K, Ndiv, Nmod, target;
138
139 dev_dbg(dev, "Fref=%u Fout=%u\n", Fref, Fout);
140
141 /* The oscilator should run at should be 90-100MHz, and
142 * there's a divide by 4 plus an optional divide by 2 in the
143 * output path to generate the system clock. The clock table
144 * is sortd so we should always generate a suitable target. */
145 target = Fout * 4;
146 if (target < 90000000) {
147 pll->outdiv = 1;
148 target *= 2;
149 } else {
150 pll->outdiv = 0;
151 }
152
153 WARN_ON(target < 90000000 || target > 100000000);
154
155 dev_dbg(dev, "Fvco=%dHz\n", target);
156
157 /* Now, calculate N.K */
158 Ndiv = target / Fref;
159
160 pll->n = Ndiv;
161 Nmod = target % Fref;
162 dev_dbg(dev, "Nmod=%d\n", Nmod);
163
164 /* Calculate fractional part - scale up so we can round. */
165 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
166
167 do_div(Kpart, Fref);
168
169 K = Kpart & 0xFFFFFFFF;
170
171 if ((K % 10) >= 5)
172 K += 5;
173
174 /* Move down to proper range now rounding is done */
175 pll->k = K / 10;
176
177 dev_dbg(dev, "N=%x K=%x OUTDIV=%x\n", pll->n, pll->k, pll->outdiv);
178
179 return 0;
180 }
181
182 /* Lookup table specifiying SRATE (table 25 in datasheet); some of the
183 * output frequencies have been rounded to the standard frequencies
184 * they are intended to match where the error is slight. */
185 static struct {
186 int mclk;
187 int fs;
188 int usb;
189 int sr;
190 } clock_cfgs[] = {
191 { 18432000, 8000, 0, 3, },
192 { 18432000, 12000, 0, 9, },
193 { 18432000, 16000, 0, 11, },
194 { 18432000, 24000, 0, 29, },
195 { 18432000, 32000, 0, 13, },
196 { 18432000, 48000, 0, 1, },
197 { 18432000, 96000, 0, 15, },
198
199 { 16934400, 8018, 0, 19, },
200 { 16934400, 11025, 0, 25, },
201 { 16934400, 22050, 0, 27, },
202 { 16934400, 44100, 0, 17, },
203 { 16934400, 88200, 0, 31, },
204
205 { 12000000, 8000, 1, 2, },
206 { 12000000, 11025, 1, 25, },
207 { 12000000, 12000, 1, 8, },
208 { 12000000, 16000, 1, 10, },
209 { 12000000, 22050, 1, 27, },
210 { 12000000, 24000, 1, 28, },
211 { 12000000, 32000, 1, 12, },
212 { 12000000, 44100, 1, 17, },
213 { 12000000, 48000, 1, 0, },
214 { 12000000, 88200, 1, 31, },
215 { 12000000, 96000, 1, 14, },
216
217 { 12288000, 8000, 0, 2, },
218 { 12288000, 12000, 0, 8, },
219 { 12288000, 16000, 0, 10, },
220 { 12288000, 24000, 0, 28, },
221 { 12288000, 32000, 0, 12, },
222 { 12288000, 48000, 0, 0, },
223 { 12288000, 96000, 0, 14, },
224
225 { 12289600, 8018, 0, 18, },
226 { 12289600, 11025, 0, 24, },
227 { 12289600, 22050, 0, 26, },
228 { 11289600, 44100, 0, 16, },
229 { 11289600, 88200, 0, 31, },
230 };
231
232 static int wm8955_configure_clocking(struct snd_soc_codec *codec)
233 {
234 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
235 int i, ret, val;
236 int clocking = 0;
237 int srate = 0;
238 int sr = -1;
239 struct pll_factors pll;
240
241 /* If we're not running a sample rate currently just pick one */
242 if (wm8955->fs == 0)
243 wm8955->fs = 8000;
244
245 /* Can we generate an exact output? */
246 for (i = 0; i < ARRAY_SIZE(clock_cfgs); i++) {
247 if (wm8955->fs != clock_cfgs[i].fs)
248 continue;
249 sr = i;
250
251 if (wm8955->mclk_rate == clock_cfgs[i].mclk)
252 break;
253 }
254
255 /* We should never get here with an unsupported sample rate */
256 if (sr == -1) {
257 dev_err(codec->dev, "Sample rate %dHz unsupported\n",
258 wm8955->fs);
259 WARN_ON(sr == -1);
260 return -EINVAL;
261 }
262
263 if (i == ARRAY_SIZE(clock_cfgs)) {
264 /* If we can't generate the right clock from MCLK then
265 * we should configure the PLL to supply us with an
266 * appropriate clock.
267 */
268 clocking |= WM8955_MCLKSEL;
269
270 /* Use the last divider configuration we saw for the
271 * sample rate. */
272 ret = wm8995_pll_factors(codec->dev, wm8955->mclk_rate,
273 clock_cfgs[sr].mclk, &pll);
274 if (ret != 0) {
275 dev_err(codec->dev,
276 "Unable to generate %dHz from %dHz MCLK\n",
277 wm8955->fs, wm8955->mclk_rate);
278 return -EINVAL;
279 }
280
281 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_1,
282 WM8955_N_MASK | WM8955_K_21_18_MASK,
283 (pll.n << WM8955_N_SHIFT) |
284 pll.k >> 18);
285 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_2,
286 WM8955_K_17_9_MASK,
287 (pll.k >> 9) & WM8955_K_17_9_MASK);
288 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_2,
289 WM8955_K_8_0_MASK,
290 pll.k & WM8955_K_8_0_MASK);
291 if (pll.k)
292 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_4,
293 WM8955_KEN, WM8955_KEN);
294 else
295 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_4,
296 WM8955_KEN, 0);
297
298 if (pll.outdiv)
299 val = WM8955_PLL_RB | WM8955_PLLOUTDIV2;
300 else
301 val = WM8955_PLL_RB;
302
303 /* Now start the PLL running */
304 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
305 WM8955_PLL_RB | WM8955_PLLOUTDIV2, val);
306 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
307 WM8955_PLLEN, WM8955_PLLEN);
308 }
309
310 srate = clock_cfgs[sr].usb | (clock_cfgs[sr].sr << WM8955_SR_SHIFT);
311
312 snd_soc_update_bits(codec, WM8955_SAMPLE_RATE,
313 WM8955_USB | WM8955_SR_MASK, srate);
314 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
315 WM8955_MCLKSEL, clocking);
316
317 return 0;
318 }
319
320 static int wm8955_sysclk(struct snd_soc_dapm_widget *w,
321 struct snd_kcontrol *kcontrol, int event)
322 {
323 struct snd_soc_codec *codec = w->codec;
324 int ret = 0;
325
326 /* Always disable the clocks - if we're doing reconfiguration this
327 * avoids misclocking.
328 */
329 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
330 WM8955_DIGENB, 0);
331 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
332 WM8955_PLL_RB | WM8955_PLLEN, 0);
333
334 switch (event) {
335 case SND_SOC_DAPM_POST_PMD:
336 break;
337 case SND_SOC_DAPM_PRE_PMU:
338 ret = wm8955_configure_clocking(codec);
339 break;
340 default:
341 ret = -EINVAL;
342 break;
343 }
344
345 return ret;
346 }
347
348 static int deemph_settings[] = { 0, 32000, 44100, 48000 };
349
350 static int wm8955_set_deemph(struct snd_soc_codec *codec)
351 {
352 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
353 int val, i, best;
354
355 /* If we're using deemphasis select the nearest available sample
356 * rate.
357 */
358 if (wm8955->deemph) {
359 best = 1;
360 for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
361 if (abs(deemph_settings[i] - wm8955->fs) <
362 abs(deemph_settings[best] - wm8955->fs))
363 best = i;
364 }
365
366 val = best << WM8955_DEEMPH_SHIFT;
367 } else {
368 val = 0;
369 }
370
371 dev_dbg(codec->dev, "Set deemphasis %d\n", val);
372
373 return snd_soc_update_bits(codec, WM8955_DAC_CONTROL,
374 WM8955_DEEMPH_MASK, val);
375 }
376
377 static int wm8955_get_deemph(struct snd_kcontrol *kcontrol,
378 struct snd_ctl_elem_value *ucontrol)
379 {
380 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
381 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
382
383 return wm8955->deemph;
384 }
385
386 static int wm8955_put_deemph(struct snd_kcontrol *kcontrol,
387 struct snd_ctl_elem_value *ucontrol)
388 {
389 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
390 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
391 int deemph = ucontrol->value.enumerated.item[0];
392
393 if (deemph > 1)
394 return -EINVAL;
395
396 wm8955->deemph = deemph;
397
398 return wm8955_set_deemph(codec);
399 }
400
401 static const char *bass_mode_text[] = {
402 "Linear", "Adaptive",
403 };
404
405 static const struct soc_enum bass_mode =
406 SOC_ENUM_SINGLE(WM8955_BASS_CONTROL, 7, 2, bass_mode_text);
407
408 static const char *bass_cutoff_text[] = {
409 "Low", "High"
410 };
411
412 static const struct soc_enum bass_cutoff =
413 SOC_ENUM_SINGLE(WM8955_BASS_CONTROL, 6, 2, bass_cutoff_text);
414
415 static const char *treble_cutoff_text[] = {
416 "High", "Low"
417 };
418
419 static const struct soc_enum treble_cutoff =
420 SOC_ENUM_SINGLE(WM8955_TREBLE_CONTROL, 6, 2, treble_cutoff_text);
421
422 static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
423 static const DECLARE_TLV_DB_SCALE(atten_tlv, -600, 600, 0);
424 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
425 static const DECLARE_TLV_DB_SCALE(mono_tlv, -2100, 300, 0);
426 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
427 static const DECLARE_TLV_DB_SCALE(treble_tlv, -1200, 150, 1);
428
429 static const struct snd_kcontrol_new wm8955_snd_controls[] = {
430 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8955_LEFT_DAC_VOLUME,
431 WM8955_RIGHT_DAC_VOLUME, 0, 255, 0, digital_tlv),
432 SOC_SINGLE_TLV("Playback Attenuation Volume", WM8955_DAC_CONTROL, 7, 1, 1,
433 atten_tlv),
434 SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
435 wm8955_get_deemph, wm8955_put_deemph),
436
437 SOC_ENUM("Bass Mode", bass_mode),
438 SOC_ENUM("Bass Cutoff", bass_cutoff),
439 SOC_SINGLE("Bass Volume", WM8955_BASS_CONTROL, 0, 15, 1),
440
441 SOC_ENUM("Treble Cutoff", treble_cutoff),
442 SOC_SINGLE_TLV("Treble Volume", WM8955_TREBLE_CONTROL, 0, 14, 1, treble_tlv),
443
444 SOC_SINGLE_TLV("Left Bypass Volume", WM8955_LEFT_OUT_MIX_1, 4, 7, 1,
445 bypass_tlv),
446 SOC_SINGLE_TLV("Left Mono Volume", WM8955_LEFT_OUT_MIX_2, 4, 7, 1,
447 bypass_tlv),
448
449 SOC_SINGLE_TLV("Right Mono Volume", WM8955_RIGHT_OUT_MIX_1, 4, 7, 1,
450 bypass_tlv),
451 SOC_SINGLE_TLV("Right Bypass Volume", WM8955_RIGHT_OUT_MIX_2, 4, 7, 1,
452 bypass_tlv),
453
454 /* Not a stereo pair so they line up with the DAPM switches */
455 SOC_SINGLE_TLV("Mono Left Bypass Volume", WM8955_MONO_OUT_MIX_1, 4, 7, 1,
456 mono_tlv),
457 SOC_SINGLE_TLV("Mono Right Bypass Volume", WM8955_MONO_OUT_MIX_2, 4, 7, 1,
458 mono_tlv),
459
460 SOC_DOUBLE_R_TLV("Headphone Volume", WM8955_LOUT1_VOLUME,
461 WM8955_ROUT1_VOLUME, 0, 127, 0, out_tlv),
462 SOC_DOUBLE_R("Headphone ZC Switch", WM8955_LOUT1_VOLUME,
463 WM8955_ROUT1_VOLUME, 7, 1, 0),
464
465 SOC_DOUBLE_R_TLV("Speaker Volume", WM8955_LOUT2_VOLUME,
466 WM8955_ROUT2_VOLUME, 0, 127, 0, out_tlv),
467 SOC_DOUBLE_R("Speaker ZC Switch", WM8955_LOUT2_VOLUME,
468 WM8955_ROUT2_VOLUME, 7, 1, 0),
469
470 SOC_SINGLE_TLV("Mono Volume", WM8955_MONOOUT_VOLUME, 0, 127, 0, out_tlv),
471 SOC_SINGLE("Mono ZC Switch", WM8955_MONOOUT_VOLUME, 7, 1, 0),
472 };
473
474 static const struct snd_kcontrol_new lmixer[] = {
475 SOC_DAPM_SINGLE("Playback Switch", WM8955_LEFT_OUT_MIX_1, 8, 1, 0),
476 SOC_DAPM_SINGLE("Bypass Switch", WM8955_LEFT_OUT_MIX_1, 7, 1, 0),
477 SOC_DAPM_SINGLE("Right Playback Switch", WM8955_LEFT_OUT_MIX_2, 8, 1, 0),
478 SOC_DAPM_SINGLE("Mono Switch", WM8955_LEFT_OUT_MIX_2, 7, 1, 0),
479 };
480
481 static const struct snd_kcontrol_new rmixer[] = {
482 SOC_DAPM_SINGLE("Left Playback Switch", WM8955_RIGHT_OUT_MIX_1, 8, 1, 0),
483 SOC_DAPM_SINGLE("Mono Switch", WM8955_RIGHT_OUT_MIX_1, 7, 1, 0),
484 SOC_DAPM_SINGLE("Playback Switch", WM8955_RIGHT_OUT_MIX_2, 8, 1, 0),
485 SOC_DAPM_SINGLE("Bypass Switch", WM8955_RIGHT_OUT_MIX_2, 7, 1, 0),
486 };
487
488 static const struct snd_kcontrol_new mmixer[] = {
489 SOC_DAPM_SINGLE("Left Playback Switch", WM8955_MONO_OUT_MIX_1, 8, 1, 0),
490 SOC_DAPM_SINGLE("Left Bypass Switch", WM8955_MONO_OUT_MIX_1, 7, 1, 0),
491 SOC_DAPM_SINGLE("Right Playback Switch", WM8955_MONO_OUT_MIX_2, 8, 1, 0),
492 SOC_DAPM_SINGLE("Right Bypass Switch", WM8955_MONO_OUT_MIX_2, 7, 1, 0),
493 };
494
495 static const struct snd_soc_dapm_widget wm8955_dapm_widgets[] = {
496 SND_SOC_DAPM_INPUT("MONOIN-"),
497 SND_SOC_DAPM_INPUT("MONOIN+"),
498 SND_SOC_DAPM_INPUT("LINEINR"),
499 SND_SOC_DAPM_INPUT("LINEINL"),
500
501 SND_SOC_DAPM_PGA("Mono Input", SND_SOC_NOPM, 0, 0, NULL, 0),
502
503 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8955_POWER_MANAGEMENT_1, 0, 1, wm8955_sysclk,
504 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
505 SND_SOC_DAPM_SUPPLY("TSDEN", WM8955_ADDITIONAL_CONTROL_1, 8, 0, NULL, 0),
506
507 SND_SOC_DAPM_DAC("DACL", "Playback", WM8955_POWER_MANAGEMENT_2, 8, 0),
508 SND_SOC_DAPM_DAC("DACR", "Playback", WM8955_POWER_MANAGEMENT_2, 7, 0),
509
510 SND_SOC_DAPM_PGA("LOUT1 PGA", WM8955_POWER_MANAGEMENT_2, 6, 0, NULL, 0),
511 SND_SOC_DAPM_PGA("ROUT1 PGA", WM8955_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
512 SND_SOC_DAPM_PGA("LOUT2 PGA", WM8955_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
513 SND_SOC_DAPM_PGA("ROUT2 PGA", WM8955_POWER_MANAGEMENT_2, 3, 0, NULL, 0),
514 SND_SOC_DAPM_PGA("MOUT PGA", WM8955_POWER_MANAGEMENT_2, 2, 0, NULL, 0),
515 SND_SOC_DAPM_PGA("OUT3 PGA", WM8955_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
516
517 /* The names are chosen to make the control names nice */
518 SND_SOC_DAPM_MIXER("Left", SND_SOC_NOPM, 0, 0,
519 lmixer, ARRAY_SIZE(lmixer)),
520 SND_SOC_DAPM_MIXER("Right", SND_SOC_NOPM, 0, 0,
521 rmixer, ARRAY_SIZE(rmixer)),
522 SND_SOC_DAPM_MIXER("Mono", SND_SOC_NOPM, 0, 0,
523 mmixer, ARRAY_SIZE(mmixer)),
524
525 SND_SOC_DAPM_OUTPUT("LOUT1"),
526 SND_SOC_DAPM_OUTPUT("ROUT1"),
527 SND_SOC_DAPM_OUTPUT("LOUT2"),
528 SND_SOC_DAPM_OUTPUT("ROUT2"),
529 SND_SOC_DAPM_OUTPUT("MONOOUT"),
530 SND_SOC_DAPM_OUTPUT("OUT3"),
531 };
532
533 static const struct snd_soc_dapm_route wm8955_intercon[] = {
534 { "DACL", NULL, "SYSCLK" },
535 { "DACR", NULL, "SYSCLK" },
536
537 { "Mono Input", NULL, "MONOIN-" },
538 { "Mono Input", NULL, "MONOIN+" },
539
540 { "Left", "Playback Switch", "DACL" },
541 { "Left", "Right Playback Switch", "DACR" },
542 { "Left", "Bypass Switch", "LINEINL" },
543 { "Left", "Mono Switch", "Mono Input" },
544
545 { "Right", "Playback Switch", "DACR" },
546 { "Right", "Left Playback Switch", "DACL" },
547 { "Right", "Bypass Switch", "LINEINR" },
548 { "Right", "Mono Switch", "Mono Input" },
549
550 { "Mono", "Left Playback Switch", "DACL" },
551 { "Mono", "Right Playback Switch", "DACR" },
552 { "Mono", "Left Bypass Switch", "LINEINL" },
553 { "Mono", "Right Bypass Switch", "LINEINR" },
554
555 { "LOUT1 PGA", NULL, "Left" },
556 { "LOUT1", NULL, "TSDEN" },
557 { "LOUT1", NULL, "LOUT1 PGA" },
558
559 { "ROUT1 PGA", NULL, "Right" },
560 { "ROUT1", NULL, "TSDEN" },
561 { "ROUT1", NULL, "ROUT1 PGA" },
562
563 { "LOUT2 PGA", NULL, "Left" },
564 { "LOUT2", NULL, "TSDEN" },
565 { "LOUT2", NULL, "LOUT2 PGA" },
566
567 { "ROUT2 PGA", NULL, "Right" },
568 { "ROUT2", NULL, "TSDEN" },
569 { "ROUT2", NULL, "ROUT2 PGA" },
570
571 { "MOUT PGA", NULL, "Mono" },
572 { "MONOOUT", NULL, "MOUT PGA" },
573
574 /* OUT3 not currently implemented */
575 { "OUT3", NULL, "OUT3 PGA" },
576 };
577
578 static int wm8955_add_widgets(struct snd_soc_codec *codec)
579 {
580 struct snd_soc_dapm_context *dapm = &codec->dapm;
581
582 snd_soc_add_controls(codec, wm8955_snd_controls,
583 ARRAY_SIZE(wm8955_snd_controls));
584
585 snd_soc_dapm_new_controls(dapm, wm8955_dapm_widgets,
586 ARRAY_SIZE(wm8955_dapm_widgets));
587 snd_soc_dapm_add_routes(dapm, wm8955_intercon,
588 ARRAY_SIZE(wm8955_intercon));
589
590 return 0;
591 }
592
593 static int wm8955_hw_params(struct snd_pcm_substream *substream,
594 struct snd_pcm_hw_params *params,
595 struct snd_soc_dai *dai)
596 {
597 struct snd_soc_codec *codec = dai->codec;
598 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
599 int ret;
600 int wl;
601
602 switch (params_format(params)) {
603 case SNDRV_PCM_FORMAT_S16_LE:
604 wl = 0;
605 break;
606 case SNDRV_PCM_FORMAT_S20_3LE:
607 wl = 0x4;
608 break;
609 case SNDRV_PCM_FORMAT_S24_LE:
610 wl = 0x8;
611 break;
612 case SNDRV_PCM_FORMAT_S32_LE:
613 wl = 0xc;
614 break;
615 default:
616 return -EINVAL;
617 }
618 snd_soc_update_bits(codec, WM8955_AUDIO_INTERFACE,
619 WM8955_WL_MASK, wl);
620
621 wm8955->fs = params_rate(params);
622 wm8955_set_deemph(codec);
623
624 /* If the chip is clocked then disable the clocks and force a
625 * reconfiguration, otherwise DAPM will power up the
626 * clocks for us later. */
627 ret = snd_soc_read(codec, WM8955_POWER_MANAGEMENT_1);
628 if (ret < 0)
629 return ret;
630 if (ret & WM8955_DIGENB) {
631 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
632 WM8955_DIGENB, 0);
633 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
634 WM8955_PLL_RB | WM8955_PLLEN, 0);
635
636 wm8955_configure_clocking(codec);
637 }
638
639 return 0;
640 }
641
642
643 static int wm8955_set_sysclk(struct snd_soc_dai *dai, int clk_id,
644 unsigned int freq, int dir)
645 {
646 struct snd_soc_codec *codec = dai->codec;
647 struct wm8955_priv *priv = snd_soc_codec_get_drvdata(codec);
648 int div;
649
650 switch (clk_id) {
651 case WM8955_CLK_MCLK:
652 if (freq > 15000000) {
653 priv->mclk_rate = freq /= 2;
654 div = WM8955_MCLKDIV2;
655 } else {
656 priv->mclk_rate = freq;
657 div = 0;
658 }
659
660 snd_soc_update_bits(codec, WM8955_SAMPLE_RATE,
661 WM8955_MCLKDIV2, div);
662 break;
663
664 default:
665 return -EINVAL;
666 }
667
668 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
669
670 return 0;
671 }
672
673 static int wm8955_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
674 {
675 struct snd_soc_codec *codec = dai->codec;
676 u16 aif = 0;
677
678 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
679 case SND_SOC_DAIFMT_CBS_CFS:
680 break;
681 case SND_SOC_DAIFMT_CBM_CFM:
682 aif |= WM8955_MS;
683 break;
684 default:
685 return -EINVAL;
686 }
687
688 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
689 case SND_SOC_DAIFMT_DSP_B:
690 aif |= WM8955_LRP;
691 case SND_SOC_DAIFMT_DSP_A:
692 aif |= 0x3;
693 break;
694 case SND_SOC_DAIFMT_I2S:
695 aif |= 0x2;
696 break;
697 case SND_SOC_DAIFMT_RIGHT_J:
698 break;
699 case SND_SOC_DAIFMT_LEFT_J:
700 aif |= 0x1;
701 break;
702 default:
703 return -EINVAL;
704 }
705
706 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
707 case SND_SOC_DAIFMT_DSP_A:
708 case SND_SOC_DAIFMT_DSP_B:
709 /* frame inversion not valid for DSP modes */
710 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
711 case SND_SOC_DAIFMT_NB_NF:
712 break;
713 case SND_SOC_DAIFMT_IB_NF:
714 aif |= WM8955_BCLKINV;
715 break;
716 default:
717 return -EINVAL;
718 }
719 break;
720
721 case SND_SOC_DAIFMT_I2S:
722 case SND_SOC_DAIFMT_RIGHT_J:
723 case SND_SOC_DAIFMT_LEFT_J:
724 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
725 case SND_SOC_DAIFMT_NB_NF:
726 break;
727 case SND_SOC_DAIFMT_IB_IF:
728 aif |= WM8955_BCLKINV | WM8955_LRP;
729 break;
730 case SND_SOC_DAIFMT_IB_NF:
731 aif |= WM8955_BCLKINV;
732 break;
733 case SND_SOC_DAIFMT_NB_IF:
734 aif |= WM8955_LRP;
735 break;
736 default:
737 return -EINVAL;
738 }
739 break;
740 default:
741 return -EINVAL;
742 }
743
744 snd_soc_update_bits(codec, WM8955_AUDIO_INTERFACE,
745 WM8955_MS | WM8955_FORMAT_MASK | WM8955_BCLKINV |
746 WM8955_LRP, aif);
747
748 return 0;
749 }
750
751
752 static int wm8955_digital_mute(struct snd_soc_dai *codec_dai, int mute)
753 {
754 struct snd_soc_codec *codec = codec_dai->codec;
755 int val;
756
757 if (mute)
758 val = WM8955_DACMU;
759 else
760 val = 0;
761
762 snd_soc_update_bits(codec, WM8955_DAC_CONTROL, WM8955_DACMU, val);
763
764 return 0;
765 }
766
767 static int wm8955_set_bias_level(struct snd_soc_codec *codec,
768 enum snd_soc_bias_level level)
769 {
770 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
771 int ret, i;
772
773 switch (level) {
774 case SND_SOC_BIAS_ON:
775 break;
776
777 case SND_SOC_BIAS_PREPARE:
778 /* VMID resistance 2*50k */
779 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
780 WM8955_VMIDSEL_MASK,
781 0x1 << WM8955_VMIDSEL_SHIFT);
782
783 /* Default bias current */
784 snd_soc_update_bits(codec, WM8955_ADDITIONAL_CONTROL_1,
785 WM8955_VSEL_MASK,
786 0x2 << WM8955_VSEL_SHIFT);
787 break;
788
789 case SND_SOC_BIAS_STANDBY:
790 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
791 ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies),
792 wm8955->supplies);
793 if (ret != 0) {
794 dev_err(codec->dev,
795 "Failed to enable supplies: %d\n",
796 ret);
797 return ret;
798 }
799
800 /* Sync back cached values if they're
801 * different from the hardware default.
802 */
803 for (i = 0; i < ARRAY_SIZE(wm8955->reg_cache); i++) {
804 if (i == WM8955_RESET)
805 continue;
806
807 if (wm8955->reg_cache[i] == wm8955_reg[i])
808 continue;
809
810 snd_soc_write(codec, i, wm8955->reg_cache[i]);
811 }
812
813 /* Enable VREF and VMID */
814 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
815 WM8955_VREF |
816 WM8955_VMIDSEL_MASK,
817 WM8955_VREF |
818 0x3 << WM8955_VREF_SHIFT);
819
820 /* Let VMID ramp */
821 msleep(500);
822
823 /* High resistance VROI to maintain outputs */
824 snd_soc_update_bits(codec,
825 WM8955_ADDITIONAL_CONTROL_3,
826 WM8955_VROI, WM8955_VROI);
827 }
828
829 /* Maintain VMID with 2*250k */
830 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
831 WM8955_VMIDSEL_MASK,
832 0x2 << WM8955_VMIDSEL_SHIFT);
833
834 /* Minimum bias current */
835 snd_soc_update_bits(codec, WM8955_ADDITIONAL_CONTROL_1,
836 WM8955_VSEL_MASK, 0);
837 break;
838
839 case SND_SOC_BIAS_OFF:
840 /* Low resistance VROI to help discharge */
841 snd_soc_update_bits(codec,
842 WM8955_ADDITIONAL_CONTROL_3,
843 WM8955_VROI, 0);
844
845 /* Turn off VMID and VREF */
846 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
847 WM8955_VREF |
848 WM8955_VMIDSEL_MASK, 0);
849
850 regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies),
851 wm8955->supplies);
852 break;
853 }
854 codec->dapm.bias_level = level;
855 return 0;
856 }
857
858 #define WM8955_RATES SNDRV_PCM_RATE_8000_96000
859
860 #define WM8955_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
861 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
862
863 static struct snd_soc_dai_ops wm8955_dai_ops = {
864 .set_sysclk = wm8955_set_sysclk,
865 .set_fmt = wm8955_set_fmt,
866 .hw_params = wm8955_hw_params,
867 .digital_mute = wm8955_digital_mute,
868 };
869
870 static struct snd_soc_dai_driver wm8955_dai = {
871 .name = "wm8955-hifi",
872 .playback = {
873 .stream_name = "Playback",
874 .channels_min = 2,
875 .channels_max = 2,
876 .rates = WM8955_RATES,
877 .formats = WM8955_FORMATS,
878 },
879 .ops = &wm8955_dai_ops,
880 };
881
882 #ifdef CONFIG_PM
883 static int wm8955_suspend(struct snd_soc_codec *codec, pm_message_t state)
884 {
885 wm8955_set_bias_level(codec, SND_SOC_BIAS_OFF);
886
887 return 0;
888 }
889
890 static int wm8955_resume(struct snd_soc_codec *codec)
891 {
892 wm8955_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
893
894 return 0;
895 }
896 #else
897 #define wm8955_suspend NULL
898 #define wm8955_resume NULL
899 #endif
900
901 static int wm8955_probe(struct snd_soc_codec *codec)
902 {
903 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
904 struct wm8955_pdata *pdata = dev_get_platdata(codec->dev);
905 int ret, i;
906
907 ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8955->control_type);
908 if (ret != 0) {
909 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
910 return ret;
911 }
912
913 for (i = 0; i < ARRAY_SIZE(wm8955->supplies); i++)
914 wm8955->supplies[i].supply = wm8955_supply_names[i];
915
916 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8955->supplies),
917 wm8955->supplies);
918 if (ret != 0) {
919 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
920 return ret;
921 }
922
923 ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies),
924 wm8955->supplies);
925 if (ret != 0) {
926 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
927 goto err_get;
928 }
929
930 ret = wm8955_reset(codec);
931 if (ret < 0) {
932 dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
933 goto err_enable;
934 }
935
936 /* Change some default settings - latch VU and enable ZC */
937 wm8955->reg_cache[WM8955_LEFT_DAC_VOLUME] |= WM8955_LDVU;
938 wm8955->reg_cache[WM8955_RIGHT_DAC_VOLUME] |= WM8955_RDVU;
939 wm8955->reg_cache[WM8955_LOUT1_VOLUME] |= WM8955_LO1VU | WM8955_LO1ZC;
940 wm8955->reg_cache[WM8955_ROUT1_VOLUME] |= WM8955_RO1VU | WM8955_RO1ZC;
941 wm8955->reg_cache[WM8955_LOUT2_VOLUME] |= WM8955_LO2VU | WM8955_LO2ZC;
942 wm8955->reg_cache[WM8955_ROUT2_VOLUME] |= WM8955_RO2VU | WM8955_RO2ZC;
943 wm8955->reg_cache[WM8955_MONOOUT_VOLUME] |= WM8955_MOZC;
944
945 /* Also enable adaptive bass boost by default */
946 wm8955->reg_cache[WM8955_BASS_CONTROL] |= WM8955_BB;
947
948 /* Set platform data values */
949 if (pdata) {
950 if (pdata->out2_speaker)
951 wm8955->reg_cache[WM8955_ADDITIONAL_CONTROL_2]
952 |= WM8955_ROUT2INV;
953
954 if (pdata->monoin_diff)
955 wm8955->reg_cache[WM8955_MONO_OUT_MIX_1]
956 |= WM8955_DMEN;
957 }
958
959 wm8955_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
960
961 /* Bias level configuration will have done an extra enable */
962 regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
963
964 wm8955_add_widgets(codec);
965 return 0;
966
967 err_enable:
968 regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
969 err_get:
970 regulator_bulk_free(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
971 return ret;
972 }
973
974 static int wm8955_remove(struct snd_soc_codec *codec)
975 {
976 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
977
978 wm8955_set_bias_level(codec, SND_SOC_BIAS_OFF);
979 regulator_bulk_free(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
980 return 0;
981 }
982
983 static struct snd_soc_codec_driver soc_codec_dev_wm8955 = {
984 .probe = wm8955_probe,
985 .remove = wm8955_remove,
986 .suspend = wm8955_suspend,
987 .resume = wm8955_resume,
988 .set_bias_level = wm8955_set_bias_level,
989 .reg_cache_size = ARRAY_SIZE(wm8955_reg),
990 .reg_word_size = sizeof(u16),
991 .reg_cache_default = wm8955_reg,
992 };
993
994 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
995 static __devinit int wm8955_i2c_probe(struct i2c_client *i2c,
996 const struct i2c_device_id *id)
997 {
998 struct wm8955_priv *wm8955;
999 int ret;
1000
1001 wm8955 = kzalloc(sizeof(struct wm8955_priv), GFP_KERNEL);
1002 if (wm8955 == NULL)
1003 return -ENOMEM;
1004
1005 i2c_set_clientdata(i2c, wm8955);
1006
1007 ret = snd_soc_register_codec(&i2c->dev,
1008 &soc_codec_dev_wm8955, &wm8955_dai, 1);
1009 if (ret < 0)
1010 kfree(wm8955);
1011 return ret;
1012 }
1013
1014 static __devexit int wm8955_i2c_remove(struct i2c_client *client)
1015 {
1016 snd_soc_unregister_codec(&client->dev);
1017 kfree(i2c_get_clientdata(client));
1018 return 0;
1019 }
1020
1021 static const struct i2c_device_id wm8955_i2c_id[] = {
1022 { "wm8955", 0 },
1023 { }
1024 };
1025 MODULE_DEVICE_TABLE(i2c, wm8955_i2c_id);
1026
1027 static struct i2c_driver wm8955_i2c_driver = {
1028 .driver = {
1029 .name = "wm8955-codec",
1030 .owner = THIS_MODULE,
1031 },
1032 .probe = wm8955_i2c_probe,
1033 .remove = __devexit_p(wm8955_i2c_remove),
1034 .id_table = wm8955_i2c_id,
1035 };
1036 #endif
1037
1038 static int __init wm8955_modinit(void)
1039 {
1040 int ret = 0;
1041 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1042 ret = i2c_add_driver(&wm8955_i2c_driver);
1043 if (ret != 0) {
1044 printk(KERN_ERR "Failed to register WM8955 I2C driver: %d\n",
1045 ret);
1046 }
1047 #endif
1048 return ret;
1049 }
1050 module_init(wm8955_modinit);
1051
1052 static void __exit wm8955_exit(void)
1053 {
1054 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1055 i2c_del_driver(&wm8955_i2c_driver);
1056 #endif
1057 }
1058 module_exit(wm8955_exit);
1059
1060 MODULE_DESCRIPTION("ASoC WM8955 driver");
1061 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1062 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.054264 seconds and 5 git commands to generate.