2 * wm8978.c -- WM8978 ALSA SoC Audio Codec driver
4 * Copyright (C) 2009-2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
5 * Copyright (C) 2007 Carlos Munoz <carlos@kenati.com>
6 * Copyright 2006-2009 Wolfson Microelectronics PLC.
7 * Based on wm8974 and wm8990 by Liam Girdwood <lrg@slimlogic.co.uk>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29 #include <asm/div64.h>
33 static struct snd_soc_codec
*wm8978_codec
;
35 /* wm8978 register cache. Note that register 0 is not included in the cache. */
36 static const u16 wm8978_reg
[WM8978_CACHEREGNUM
] = {
37 0x0000, 0x0000, 0x0000, 0x0000, /* 0x00...0x03 */
38 0x0050, 0x0000, 0x0140, 0x0000, /* 0x04...0x07 */
39 0x0000, 0x0000, 0x0000, 0x00ff, /* 0x08...0x0b */
40 0x00ff, 0x0000, 0x0100, 0x00ff, /* 0x0c...0x0f */
41 0x00ff, 0x0000, 0x012c, 0x002c, /* 0x10...0x13 */
42 0x002c, 0x002c, 0x002c, 0x0000, /* 0x14...0x17 */
43 0x0032, 0x0000, 0x0000, 0x0000, /* 0x18...0x1b */
44 0x0000, 0x0000, 0x0000, 0x0000, /* 0x1c...0x1f */
45 0x0038, 0x000b, 0x0032, 0x0000, /* 0x20...0x23 */
46 0x0008, 0x000c, 0x0093, 0x00e9, /* 0x24...0x27 */
47 0x0000, 0x0000, 0x0000, 0x0000, /* 0x28...0x2b */
48 0x0033, 0x0010, 0x0010, 0x0100, /* 0x2c...0x2f */
49 0x0100, 0x0002, 0x0001, 0x0001, /* 0x30...0x33 */
50 0x0039, 0x0039, 0x0039, 0x0039, /* 0x34...0x37 */
51 0x0001, 0x0001, /* 0x38...0x3b */
54 /* codec private data */
56 struct snd_soc_codec codec
;
57 unsigned int f_pllout
;
62 enum wm8978_sysclk_src sysclk
;
63 u16 reg_cache
[WM8978_CACHEREGNUM
];
66 static const char *wm8978_companding
[] = {"Off", "NC", "u-law", "A-law"};
67 static const char *wm8978_eqmode
[] = {"Capture", "Playback"};
68 static const char *wm8978_bw
[] = {"Narrow", "Wide"};
69 static const char *wm8978_eq1
[] = {"80Hz", "105Hz", "135Hz", "175Hz"};
70 static const char *wm8978_eq2
[] = {"230Hz", "300Hz", "385Hz", "500Hz"};
71 static const char *wm8978_eq3
[] = {"650Hz", "850Hz", "1.1kHz", "1.4kHz"};
72 static const char *wm8978_eq4
[] = {"1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"};
73 static const char *wm8978_eq5
[] = {"5.3kHz", "6.9kHz", "9kHz", "11.7kHz"};
74 static const char *wm8978_alc3
[] = {"ALC", "Limiter"};
75 static const char *wm8978_alc1
[] = {"Off", "Right", "Left", "Both"};
77 static const SOC_ENUM_SINGLE_DECL(adc_compand
, WM8978_COMPANDING_CONTROL
, 1,
79 static const SOC_ENUM_SINGLE_DECL(dac_compand
, WM8978_COMPANDING_CONTROL
, 3,
81 static const SOC_ENUM_SINGLE_DECL(eqmode
, WM8978_EQ1
, 8, wm8978_eqmode
);
82 static const SOC_ENUM_SINGLE_DECL(eq1
, WM8978_EQ1
, 5, wm8978_eq1
);
83 static const SOC_ENUM_SINGLE_DECL(eq2bw
, WM8978_EQ2
, 8, wm8978_bw
);
84 static const SOC_ENUM_SINGLE_DECL(eq2
, WM8978_EQ2
, 5, wm8978_eq2
);
85 static const SOC_ENUM_SINGLE_DECL(eq3bw
, WM8978_EQ3
, 8, wm8978_bw
);
86 static const SOC_ENUM_SINGLE_DECL(eq3
, WM8978_EQ3
, 5, wm8978_eq3
);
87 static const SOC_ENUM_SINGLE_DECL(eq4bw
, WM8978_EQ4
, 8, wm8978_bw
);
88 static const SOC_ENUM_SINGLE_DECL(eq4
, WM8978_EQ4
, 5, wm8978_eq4
);
89 static const SOC_ENUM_SINGLE_DECL(eq5
, WM8978_EQ5
, 5, wm8978_eq5
);
90 static const SOC_ENUM_SINGLE_DECL(alc3
, WM8978_ALC_CONTROL_3
, 8, wm8978_alc3
);
91 static const SOC_ENUM_SINGLE_DECL(alc1
, WM8978_ALC_CONTROL_1
, 7, wm8978_alc1
);
93 static const DECLARE_TLV_DB_SCALE(digital_tlv
, -12750, 50, 1);
94 static const DECLARE_TLV_DB_SCALE(eq_tlv
, -1200, 100, 0);
95 static const DECLARE_TLV_DB_SCALE(inpga_tlv
, -1200, 75, 0);
96 static const DECLARE_TLV_DB_SCALE(spk_tlv
, -5700, 100, 0);
97 static const DECLARE_TLV_DB_SCALE(boost_tlv
, -1500, 300, 1);
99 static const struct snd_kcontrol_new wm8978_snd_controls
[] = {
101 SOC_SINGLE("Digital Loopback Switch",
102 WM8978_COMPANDING_CONTROL
, 0, 1, 0),
104 SOC_ENUM("ADC Companding", adc_compand
),
105 SOC_ENUM("DAC Companding", dac_compand
),
107 SOC_DOUBLE("DAC Inversion Switch", WM8978_DAC_CONTROL
, 0, 1, 1, 0),
109 SOC_DOUBLE_R_TLV("PCM Volume",
110 WM8978_LEFT_DAC_DIGITAL_VOLUME
, WM8978_RIGHT_DAC_DIGITAL_VOLUME
,
111 0, 255, 0, digital_tlv
),
113 SOC_SINGLE("High Pass Filter Switch", WM8978_ADC_CONTROL
, 8, 1, 0),
114 SOC_SINGLE("High Pass Cut Off", WM8978_ADC_CONTROL
, 4, 7, 0),
115 SOC_DOUBLE("ADC Inversion Switch", WM8978_ADC_CONTROL
, 0, 1, 1, 0),
117 SOC_DOUBLE_R_TLV("ADC Volume",
118 WM8978_LEFT_ADC_DIGITAL_VOLUME
, WM8978_RIGHT_ADC_DIGITAL_VOLUME
,
119 0, 255, 0, digital_tlv
),
121 SOC_ENUM("Equaliser Function", eqmode
),
122 SOC_ENUM("EQ1 Cut Off", eq1
),
123 SOC_SINGLE_TLV("EQ1 Volume", WM8978_EQ1
, 0, 24, 1, eq_tlv
),
125 SOC_ENUM("Equaliser EQ2 Bandwith", eq2bw
),
126 SOC_ENUM("EQ2 Cut Off", eq2
),
127 SOC_SINGLE_TLV("EQ2 Volume", WM8978_EQ2
, 0, 24, 1, eq_tlv
),
129 SOC_ENUM("Equaliser EQ3 Bandwith", eq3bw
),
130 SOC_ENUM("EQ3 Cut Off", eq3
),
131 SOC_SINGLE_TLV("EQ3 Volume", WM8978_EQ3
, 0, 24, 1, eq_tlv
),
133 SOC_ENUM("Equaliser EQ4 Bandwith", eq4bw
),
134 SOC_ENUM("EQ4 Cut Off", eq4
),
135 SOC_SINGLE_TLV("EQ4 Volume", WM8978_EQ4
, 0, 24, 1, eq_tlv
),
137 SOC_ENUM("EQ5 Cut Off", eq5
),
138 SOC_SINGLE_TLV("EQ5 Volume", WM8978_EQ5
, 0, 24, 1, eq_tlv
),
140 SOC_SINGLE("DAC Playback Limiter Switch",
141 WM8978_DAC_LIMITER_1
, 8, 1, 0),
142 SOC_SINGLE("DAC Playback Limiter Decay",
143 WM8978_DAC_LIMITER_1
, 4, 15, 0),
144 SOC_SINGLE("DAC Playback Limiter Attack",
145 WM8978_DAC_LIMITER_1
, 0, 15, 0),
147 SOC_SINGLE("DAC Playback Limiter Threshold",
148 WM8978_DAC_LIMITER_2
, 4, 7, 0),
149 SOC_SINGLE("DAC Playback Limiter Boost",
150 WM8978_DAC_LIMITER_2
, 0, 15, 0),
152 SOC_ENUM("ALC Enable Switch", alc1
),
153 SOC_SINGLE("ALC Capture Min Gain", WM8978_ALC_CONTROL_1
, 0, 7, 0),
154 SOC_SINGLE("ALC Capture Max Gain", WM8978_ALC_CONTROL_1
, 3, 7, 0),
156 SOC_SINGLE("ALC Capture Hold", WM8978_ALC_CONTROL_2
, 4, 7, 0),
157 SOC_SINGLE("ALC Capture Target", WM8978_ALC_CONTROL_2
, 0, 15, 0),
159 SOC_ENUM("ALC Capture Mode", alc3
),
160 SOC_SINGLE("ALC Capture Decay", WM8978_ALC_CONTROL_3
, 4, 15, 0),
161 SOC_SINGLE("ALC Capture Attack", WM8978_ALC_CONTROL_3
, 0, 15, 0),
163 SOC_SINGLE("ALC Capture Noise Gate Switch", WM8978_NOISE_GATE
, 3, 1, 0),
164 SOC_SINGLE("ALC Capture Noise Gate Threshold",
165 WM8978_NOISE_GATE
, 0, 7, 0),
167 SOC_DOUBLE_R("Capture PGA ZC Switch",
168 WM8978_LEFT_INP_PGA_CONTROL
, WM8978_RIGHT_INP_PGA_CONTROL
,
171 /* OUT1 - Headphones */
172 SOC_DOUBLE_R("Headphone Playback ZC Switch",
173 WM8978_LOUT1_HP_CONTROL
, WM8978_ROUT1_HP_CONTROL
, 7, 1, 0),
175 SOC_DOUBLE_R_TLV("Headphone Playback Volume",
176 WM8978_LOUT1_HP_CONTROL
, WM8978_ROUT1_HP_CONTROL
,
179 /* OUT2 - Speakers */
180 SOC_DOUBLE_R("Speaker Playback ZC Switch",
181 WM8978_LOUT2_SPK_CONTROL
, WM8978_ROUT2_SPK_CONTROL
, 7, 1, 0),
183 SOC_DOUBLE_R_TLV("Speaker Playback Volume",
184 WM8978_LOUT2_SPK_CONTROL
, WM8978_ROUT2_SPK_CONTROL
,
187 /* OUT3/4 - Line Output */
188 SOC_DOUBLE_R("Line Playback Switch",
189 WM8978_OUT3_MIXER_CONTROL
, WM8978_OUT4_MIXER_CONTROL
, 6, 1, 1),
191 /* Mixer #3: Boost (Input) mixer */
192 SOC_DOUBLE_R("PGA Boost (+20dB)",
193 WM8978_LEFT_ADC_BOOST_CONTROL
, WM8978_RIGHT_ADC_BOOST_CONTROL
,
195 SOC_DOUBLE_R_TLV("L2/R2 Boost Volume",
196 WM8978_LEFT_ADC_BOOST_CONTROL
, WM8978_RIGHT_ADC_BOOST_CONTROL
,
198 SOC_DOUBLE_R_TLV("Aux Boost Volume",
199 WM8978_LEFT_ADC_BOOST_CONTROL
, WM8978_RIGHT_ADC_BOOST_CONTROL
,
202 /* Input PGA volume */
203 SOC_DOUBLE_R_TLV("Input PGA Volume",
204 WM8978_LEFT_INP_PGA_CONTROL
, WM8978_RIGHT_INP_PGA_CONTROL
,
205 0, 63, 0, inpga_tlv
),
208 SOC_DOUBLE_R("Headphone Switch",
209 WM8978_LOUT1_HP_CONTROL
, WM8978_ROUT1_HP_CONTROL
, 6, 1, 1),
212 SOC_DOUBLE_R("Speaker Switch",
213 WM8978_LOUT2_SPK_CONTROL
, WM8978_ROUT2_SPK_CONTROL
, 6, 1, 1),
215 /* DAC / ADC oversampling */
216 SOC_SINGLE("DAC 128x Oversampling Switch", WM8978_DAC_CONTROL
, 8, 1, 0),
217 SOC_SINGLE("ADC 128x Oversampling Switch", WM8978_ADC_CONTROL
, 8, 1, 0),
220 /* Mixer #1: Output (OUT1, OUT2) Mixer: mix AUX, Input mixer output and DAC */
221 static const struct snd_kcontrol_new wm8978_left_out_mixer
[] = {
222 SOC_DAPM_SINGLE("Line Bypass Switch", WM8978_LEFT_MIXER_CONTROL
, 1, 1, 0),
223 SOC_DAPM_SINGLE("Aux Playback Switch", WM8978_LEFT_MIXER_CONTROL
, 5, 1, 0),
224 SOC_DAPM_SINGLE("PCM Playback Switch", WM8978_LEFT_MIXER_CONTROL
, 0, 1, 0),
227 static const struct snd_kcontrol_new wm8978_right_out_mixer
[] = {
228 SOC_DAPM_SINGLE("Line Bypass Switch", WM8978_RIGHT_MIXER_CONTROL
, 1, 1, 0),
229 SOC_DAPM_SINGLE("Aux Playback Switch", WM8978_RIGHT_MIXER_CONTROL
, 5, 1, 0),
230 SOC_DAPM_SINGLE("PCM Playback Switch", WM8978_RIGHT_MIXER_CONTROL
, 0, 1, 0),
233 /* OUT3/OUT4 Mixer not implemented */
235 /* Mixer #2: Input PGA Mute */
236 static const struct snd_kcontrol_new wm8978_left_input_mixer
[] = {
237 SOC_DAPM_SINGLE("L2 Switch", WM8978_INPUT_CONTROL
, 2, 1, 0),
238 SOC_DAPM_SINGLE("MicN Switch", WM8978_INPUT_CONTROL
, 1, 1, 0),
239 SOC_DAPM_SINGLE("MicP Switch", WM8978_INPUT_CONTROL
, 0, 1, 0),
241 static const struct snd_kcontrol_new wm8978_right_input_mixer
[] = {
242 SOC_DAPM_SINGLE("R2 Switch", WM8978_INPUT_CONTROL
, 6, 1, 0),
243 SOC_DAPM_SINGLE("MicN Switch", WM8978_INPUT_CONTROL
, 5, 1, 0),
244 SOC_DAPM_SINGLE("MicP Switch", WM8978_INPUT_CONTROL
, 4, 1, 0),
247 static const struct snd_soc_dapm_widget wm8978_dapm_widgets
[] = {
248 SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback",
249 WM8978_POWER_MANAGEMENT_3
, 0, 0),
250 SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback",
251 WM8978_POWER_MANAGEMENT_3
, 1, 0),
252 SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture",
253 WM8978_POWER_MANAGEMENT_2
, 0, 0),
254 SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture",
255 WM8978_POWER_MANAGEMENT_2
, 1, 0),
257 /* Mixer #1: OUT1,2 */
258 SOC_MIXER_ARRAY("Left Output Mixer", WM8978_POWER_MANAGEMENT_3
,
259 2, 0, wm8978_left_out_mixer
),
260 SOC_MIXER_ARRAY("Right Output Mixer", WM8978_POWER_MANAGEMENT_3
,
261 3, 0, wm8978_right_out_mixer
),
263 SOC_MIXER_ARRAY("Left Input Mixer", WM8978_POWER_MANAGEMENT_2
,
264 2, 0, wm8978_left_input_mixer
),
265 SOC_MIXER_ARRAY("Right Input Mixer", WM8978_POWER_MANAGEMENT_2
,
266 3, 0, wm8978_right_input_mixer
),
268 SND_SOC_DAPM_PGA("Left Boost Mixer", WM8978_POWER_MANAGEMENT_2
,
270 SND_SOC_DAPM_PGA("Right Boost Mixer", WM8978_POWER_MANAGEMENT_2
,
273 SND_SOC_DAPM_PGA("Left Capture PGA", WM8978_LEFT_INP_PGA_CONTROL
,
275 SND_SOC_DAPM_PGA("Right Capture PGA", WM8978_RIGHT_INP_PGA_CONTROL
,
278 SND_SOC_DAPM_PGA("Left Headphone Out", WM8978_POWER_MANAGEMENT_2
,
280 SND_SOC_DAPM_PGA("Right Headphone Out", WM8978_POWER_MANAGEMENT_2
,
283 SND_SOC_DAPM_PGA("Left Speaker Out", WM8978_POWER_MANAGEMENT_3
,
285 SND_SOC_DAPM_PGA("Right Speaker Out", WM8978_POWER_MANAGEMENT_3
,
288 SND_SOC_DAPM_MIXER("OUT4 VMID", WM8978_POWER_MANAGEMENT_3
,
291 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8978_POWER_MANAGEMENT_1
, 4, 0),
293 SND_SOC_DAPM_INPUT("LMICN"),
294 SND_SOC_DAPM_INPUT("LMICP"),
295 SND_SOC_DAPM_INPUT("RMICN"),
296 SND_SOC_DAPM_INPUT("RMICP"),
297 SND_SOC_DAPM_INPUT("LAUX"),
298 SND_SOC_DAPM_INPUT("RAUX"),
299 SND_SOC_DAPM_INPUT("L2"),
300 SND_SOC_DAPM_INPUT("R2"),
301 SND_SOC_DAPM_OUTPUT("LHP"),
302 SND_SOC_DAPM_OUTPUT("RHP"),
303 SND_SOC_DAPM_OUTPUT("LSPK"),
304 SND_SOC_DAPM_OUTPUT("RSPK"),
307 static const struct snd_soc_dapm_route audio_map
[] = {
309 {"Right Output Mixer", "PCM Playback Switch", "Right DAC"},
310 {"Right Output Mixer", "Aux Playback Switch", "RAUX"},
311 {"Right Output Mixer", "Line Bypass Switch", "Right Boost Mixer"},
313 {"Left Output Mixer", "PCM Playback Switch", "Left DAC"},
314 {"Left Output Mixer", "Aux Playback Switch", "LAUX"},
315 {"Left Output Mixer", "Line Bypass Switch", "Left Boost Mixer"},
318 {"Right Headphone Out", NULL
, "Right Output Mixer"},
319 {"RHP", NULL
, "Right Headphone Out"},
321 {"Left Headphone Out", NULL
, "Left Output Mixer"},
322 {"LHP", NULL
, "Left Headphone Out"},
324 {"Right Speaker Out", NULL
, "Right Output Mixer"},
325 {"RSPK", NULL
, "Right Speaker Out"},
327 {"Left Speaker Out", NULL
, "Left Output Mixer"},
328 {"LSPK", NULL
, "Left Speaker Out"},
331 {"Right ADC", NULL
, "Right Boost Mixer"},
333 {"Right Boost Mixer", NULL
, "RAUX"},
334 {"Right Boost Mixer", NULL
, "Right Capture PGA"},
335 {"Right Boost Mixer", NULL
, "R2"},
337 {"Left ADC", NULL
, "Left Boost Mixer"},
339 {"Left Boost Mixer", NULL
, "LAUX"},
340 {"Left Boost Mixer", NULL
, "Left Capture PGA"},
341 {"Left Boost Mixer", NULL
, "L2"},
344 {"Right Capture PGA", NULL
, "Right Input Mixer"},
345 {"Left Capture PGA", NULL
, "Left Input Mixer"},
347 {"Right Input Mixer", "R2 Switch", "R2"},
348 {"Right Input Mixer", "MicN Switch", "RMICN"},
349 {"Right Input Mixer", "MicP Switch", "RMICP"},
351 {"Left Input Mixer", "L2 Switch", "L2"},
352 {"Left Input Mixer", "MicN Switch", "LMICN"},
353 {"Left Input Mixer", "MicP Switch", "LMICP"},
356 static int wm8978_add_widgets(struct snd_soc_codec
*codec
)
358 snd_soc_dapm_new_controls(codec
, wm8978_dapm_widgets
,
359 ARRAY_SIZE(wm8978_dapm_widgets
));
361 /* set up the WM8978 audio map */
362 snd_soc_dapm_add_routes(codec
, audio_map
, ARRAY_SIZE(audio_map
));
368 struct wm8978_pll_div
{
374 #define FIXED_PLL_SIZE (1 << 24)
376 static void pll_factors(struct wm8978_pll_div
*pll_div
, unsigned int target
,
380 unsigned int k
, n_div
, n_mod
;
382 n_div
= target
/ source
;
386 n_div
= target
/ source
;
391 if (n_div
< 6 || n_div
> 12)
392 dev_warn(wm8978_codec
->dev
,
393 "WM8978 N value exceeds recommended range! N = %u\n",
397 n_mod
= target
- source
* n_div
;
398 k_part
= FIXED_PLL_SIZE
* (long long)n_mod
+ source
/ 2;
400 do_div(k_part
, source
);
402 k
= k_part
& 0xFFFFFFFF;
408 static const int mclk_numerator
[] = {1, 3, 2, 3, 4, 6, 8, 12};
409 static const int mclk_denominator
[] = {1, 2, 1, 1, 1, 1, 1, 1};
412 * find index >= idx, such that, for a given f_out,
413 * 3 * f_mclk / 4 <= f_PLLOUT < 13 * f_mclk / 4
414 * f_out can be f_256fs or f_opclk, currently only used for f_256fs. Can be
415 * generalised for f_opclk with suitable coefficient arrays, but currently
416 * the OPCLK divisor is calculated directly, not iteratively.
418 static int wm8978_enum_mclk(unsigned int f_out
, unsigned int f_mclk
,
419 unsigned int *f_pllout
)
423 for (i
= 0; i
< ARRAY_SIZE(mclk_numerator
); i
++) {
424 unsigned int f_pllout_x4
= 4 * f_out
* mclk_numerator
[i
] /
426 if (3 * f_mclk
<= f_pllout_x4
&& f_pllout_x4
< 13 * f_mclk
) {
427 *f_pllout
= f_pllout_x4
/ 4;
436 * Calculate internal frequencies and dividers, according to Figure 40
437 * "PLL and Clock Select Circuit" in WM8978 datasheet Rev. 2.6
439 static int wm8978_configure_pll(struct snd_soc_codec
*codec
)
441 struct wm8978_priv
*wm8978
= codec
->private_data
;
442 struct wm8978_pll_div pll_div
;
443 unsigned int f_opclk
= wm8978
->f_opclk
, f_mclk
= wm8978
->f_mclk
,
444 f_256fs
= wm8978
->f_256fs
;
451 unsigned int opclk_div
;
452 /* Cannot set up MCLK divider now, do later */
453 wm8978
->mclk_idx
= -1;
456 * The user needs OPCLK. Choose OPCLKDIV to put
457 * 6 <= R = f2 / f1 < 13, 1 <= OPCLKDIV <= 4.
458 * f_opclk = f_mclk * prescale * R / 4 / OPCLKDIV, where
459 * prescale = 1, or prescale = 2. Prescale is calculated inside
460 * pll_factors(). We have to select f_PLLOUT, such that
461 * f_mclk * 3 / 4 <= f_PLLOUT < f_mclk * 13 / 4. Must be
462 * f_mclk * 3 / 16 <= f_opclk < f_mclk * 13 / 4.
464 if (16 * f_opclk
< 3 * f_mclk
|| 4 * f_opclk
>= 13 * f_mclk
)
467 if (4 * f_opclk
< 3 * f_mclk
)
468 /* Have to use OPCLKDIV */
469 opclk_div
= (3 * f_mclk
/ 4 + f_opclk
- 1) / f_opclk
;
473 dev_dbg(codec
->dev
, "%s: OPCLKDIV=%d\n", __func__
, opclk_div
);
475 snd_soc_update_bits(codec
, WM8978_GPIO_CONTROL
, 0x30,
476 (opclk_div
- 1) << 4);
478 wm8978
->f_pllout
= f_opclk
* opclk_div
;
479 } else if (f_256fs
) {
481 * Not using OPCLK, but PLL is used for the codec, choose R:
482 * 6 <= R = f2 / f1 < 13, to put 1 <= MCLKDIV <= 12.
483 * f_256fs = f_mclk * prescale * R / 4 / MCLKDIV, where
484 * prescale = 1, or prescale = 2. Prescale is calculated inside
485 * pll_factors(). We have to select f_PLLOUT, such that
486 * f_mclk * 3 / 4 <= f_PLLOUT < f_mclk * 13 / 4. Must be
487 * f_mclk * 3 / 48 <= f_256fs < f_mclk * 13 / 4. This means MCLK
488 * must be 3.781MHz <= f_MCLK <= 32.768MHz
490 int idx
= wm8978_enum_mclk(f_256fs
, f_mclk
, &wm8978
->f_pllout
);
494 wm8978
->mclk_idx
= idx
;
496 /* GPIO1 into default mode as input - before configuring PLL */
497 snd_soc_update_bits(codec
, WM8978_GPIO_CONTROL
, 7, 0);
502 f2
= wm8978
->f_pllout
* 4;
504 dev_dbg(codec
->dev
, "%s: f_MCLK=%uHz, f_PLLOUT=%uHz\n", __func__
,
505 wm8978
->f_mclk
, wm8978
->f_pllout
);
507 pll_factors(&pll_div
, f2
, wm8978
->f_mclk
);
509 dev_dbg(codec
->dev
, "%s: calculated PLL N=0x%x, K=0x%x, div2=%d\n",
510 __func__
, pll_div
.n
, pll_div
.k
, pll_div
.div2
);
512 /* Turn PLL off for configuration... */
513 snd_soc_update_bits(codec
, WM8978_POWER_MANAGEMENT_1
, 0x20, 0);
515 snd_soc_write(codec
, WM8978_PLL_N
, (pll_div
.div2
<< 4) | pll_div
.n
);
516 snd_soc_write(codec
, WM8978_PLL_K1
, pll_div
.k
>> 18);
517 snd_soc_write(codec
, WM8978_PLL_K2
, (pll_div
.k
>> 9) & 0x1ff);
518 snd_soc_write(codec
, WM8978_PLL_K3
, pll_div
.k
& 0x1ff);
520 /* ...and on again */
521 snd_soc_update_bits(codec
, WM8978_POWER_MANAGEMENT_1
, 0x20, 0x20);
524 /* Output PLL (OPCLK) to GPIO1 */
525 snd_soc_update_bits(codec
, WM8978_GPIO_CONTROL
, 7, 4);
531 * Configure WM8978 clock dividers.
533 static int wm8978_set_dai_clkdiv(struct snd_soc_dai
*codec_dai
,
536 struct snd_soc_codec
*codec
= codec_dai
->codec
;
537 struct wm8978_priv
*wm8978
= codec
->private_data
;
541 case WM8978_OPCLKRATE
:
542 wm8978
->f_opclk
= div
;
546 * We know the MCLK frequency, the user has requested
547 * OPCLK, configure the PLL based on that and start it
548 * and OPCLK immediately. We will configure PLL to match
549 * user-requested OPCLK frquency as good as possible.
550 * In fact, it is likely, that matching the sampling
551 * rate, when it becomes known, is more important, and
552 * we will not be reconfiguring PLL then, because we
553 * must not interrupt OPCLK. But it should be fine,
554 * because typically the user will request OPCLK to run
555 * at 256fs or 512fs, and for these cases we will also
556 * find an exact MCLK divider configuration - it will
557 * be equal to or double the OPCLK divisor.
559 ret
= wm8978_configure_pll(codec
);
564 snd_soc_update_bits(codec
, WM8978_CLOCKING
, 0x1c, div
);
570 dev_dbg(codec
->dev
, "%s: ID %d, value %u\n", __func__
, div_id
, div
);
576 * @freq: when .set_pll() us not used, freq is codec MCLK input frequency
578 static int wm8978_set_dai_sysclk(struct snd_soc_dai
*codec_dai
, int clk_id
,
579 unsigned int freq
, int dir
)
581 struct snd_soc_codec
*codec
= codec_dai
->codec
;
582 struct wm8978_priv
*wm8978
= codec
->private_data
;
585 dev_dbg(codec
->dev
, "%s: ID %d, freq %u\n", __func__
, clk_id
, freq
);
588 wm8978
->f_mclk
= freq
;
590 /* Even if MCLK is used for system clock, might have to drive OPCLK */
592 ret
= wm8978_configure_pll(codec
);
594 /* Our sysclk is fixed to 256 * fs, will configure in .hw_params() */
597 wm8978
->sysclk
= clk_id
;
600 if (wm8978
->sysclk
== WM8978_PLL
&& (!freq
|| clk_id
== WM8978_MCLK
)) {
601 /* Clock CODEC directly from MCLK */
602 snd_soc_update_bits(codec
, WM8978_CLOCKING
, 0x100, 0);
604 /* GPIO1 into default mode as input - before configuring PLL */
605 snd_soc_update_bits(codec
, WM8978_GPIO_CONTROL
, 7, 0);
608 snd_soc_update_bits(codec
, WM8978_POWER_MANAGEMENT_1
, 0x20, 0);
609 wm8978
->sysclk
= WM8978_MCLK
;
610 wm8978
->f_pllout
= 0;
618 * Set ADC and Voice DAC format.
620 static int wm8978_set_dai_fmt(struct snd_soc_dai
*codec_dai
, unsigned int fmt
)
622 struct snd_soc_codec
*codec
= codec_dai
->codec
;
624 * BCLK polarity mask = 0x100, LRC clock polarity mask = 0x80,
625 * Data Format mask = 0x18: all will be calculated anew
627 u16 iface
= snd_soc_read(codec
, WM8978_AUDIO_INTERFACE
) & ~0x198;
628 u16 clk
= snd_soc_read(codec
, WM8978_CLOCKING
);
630 dev_dbg(codec
->dev
, "%s\n", __func__
);
632 /* set master/slave audio interface */
633 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
634 case SND_SOC_DAIFMT_CBM_CFM
:
637 case SND_SOC_DAIFMT_CBS_CFS
:
644 /* interface format */
645 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
646 case SND_SOC_DAIFMT_I2S
:
649 case SND_SOC_DAIFMT_RIGHT_J
:
651 case SND_SOC_DAIFMT_LEFT_J
:
654 case SND_SOC_DAIFMT_DSP_A
:
661 /* clock inversion */
662 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
663 case SND_SOC_DAIFMT_NB_NF
:
665 case SND_SOC_DAIFMT_IB_IF
:
668 case SND_SOC_DAIFMT_IB_NF
:
671 case SND_SOC_DAIFMT_NB_IF
:
678 snd_soc_write(codec
, WM8978_AUDIO_INTERFACE
, iface
);
679 snd_soc_write(codec
, WM8978_CLOCKING
, clk
);
685 * Set PCM DAI bit size and sample rate.
687 static int wm8978_hw_params(struct snd_pcm_substream
*substream
,
688 struct snd_pcm_hw_params
*params
,
689 struct snd_soc_dai
*dai
)
691 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
692 struct snd_soc_device
*socdev
= rtd
->socdev
;
693 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
694 struct wm8978_priv
*wm8978
= codec
->private_data
;
695 /* Word length mask = 0x60 */
696 u16 iface_ctl
= snd_soc_read(codec
, WM8978_AUDIO_INTERFACE
) & ~0x60;
697 /* Sampling rate mask = 0xe (for filters) */
698 u16 add_ctl
= snd_soc_read(codec
, WM8978_ADDITIONAL_CONTROL
) & ~0xe;
699 u16 clking
= snd_soc_read(codec
, WM8978_CLOCKING
);
700 enum wm8978_sysclk_src current_clk_id
= clking
& 0x100 ?
701 WM8978_PLL
: WM8978_MCLK
;
702 unsigned int f_sel
, diff
, diff_best
= INT_MAX
;
709 switch (params_format(params
)) {
710 case SNDRV_PCM_FORMAT_S16_LE
:
712 case SNDRV_PCM_FORMAT_S20_3LE
:
715 case SNDRV_PCM_FORMAT_S24_LE
:
718 case SNDRV_PCM_FORMAT_S32_LE
:
723 /* filter coefficient */
724 switch (params_rate(params
)) {
745 /* Sampling rate is known now, can configure the MCLK divider */
746 wm8978
->f_256fs
= params_rate(params
) * 256;
748 if (wm8978
->sysclk
== WM8978_MCLK
) {
749 wm8978
->mclk_idx
= -1;
750 f_sel
= wm8978
->f_mclk
;
752 if (!wm8978
->f_pllout
) {
753 /* We only enter here, if OPCLK is not used */
754 int ret
= wm8978_configure_pll(codec
);
758 f_sel
= wm8978
->f_pllout
;
761 if (wm8978
->mclk_idx
< 0) {
762 /* Either MCLK is used directly, or OPCLK is used */
763 if (f_sel
< wm8978
->f_256fs
|| f_sel
> 12 * wm8978
->f_256fs
)
766 for (i
= 0; i
< ARRAY_SIZE(mclk_numerator
); i
++) {
767 diff
= abs(wm8978
->f_256fs
* 3 -
768 f_sel
* 3 * mclk_denominator
[i
] / mclk_numerator
[i
]);
770 if (diff
< diff_best
) {
779 /* OPCLK not used, codec driven by PLL */
780 best
= wm8978
->mclk_idx
;
785 dev_warn(codec
->dev
, "Imprecise sampling rate: %uHz%s\n",
786 f_sel
* mclk_denominator
[best
] / mclk_numerator
[best
] / 256,
787 wm8978
->sysclk
== WM8978_MCLK
?
788 ", consider using PLL" : "");
790 dev_dbg(codec
->dev
, "%s: fmt %d, rate %u, MCLK divisor #%d\n", __func__
,
791 params_format(params
), params_rate(params
), best
);
793 /* MCLK divisor mask = 0xe0 */
794 snd_soc_update_bits(codec
, WM8978_CLOCKING
, 0xe0, best
<< 5);
796 snd_soc_write(codec
, WM8978_AUDIO_INTERFACE
, iface_ctl
);
797 snd_soc_write(codec
, WM8978_ADDITIONAL_CONTROL
, add_ctl
);
799 if (wm8978
->sysclk
!= current_clk_id
) {
800 if (wm8978
->sysclk
== WM8978_PLL
)
801 /* Run CODEC from PLL instead of MCLK */
802 snd_soc_update_bits(codec
, WM8978_CLOCKING
,
805 /* Clock CODEC directly from MCLK */
806 snd_soc_update_bits(codec
, WM8978_CLOCKING
, 0x100, 0);
812 static int wm8978_mute(struct snd_soc_dai
*dai
, int mute
)
814 struct snd_soc_codec
*codec
= dai
->codec
;
816 dev_dbg(codec
->dev
, "%s: %d\n", __func__
, mute
);
819 snd_soc_update_bits(codec
, WM8978_DAC_CONTROL
, 0x40, 0x40);
821 snd_soc_update_bits(codec
, WM8978_DAC_CONTROL
, 0x40, 0);
826 static int wm8978_set_bias_level(struct snd_soc_codec
*codec
,
827 enum snd_soc_bias_level level
)
829 u16 power1
= snd_soc_read(codec
, WM8978_POWER_MANAGEMENT_1
) & ~3;
832 case SND_SOC_BIAS_ON
:
833 case SND_SOC_BIAS_PREPARE
:
834 power1
|= 1; /* VMID 75k */
835 snd_soc_write(codec
, WM8978_POWER_MANAGEMENT_1
, power1
);
837 case SND_SOC_BIAS_STANDBY
:
838 /* bit 3: enable bias, bit 2: enable I/O tie off buffer */
841 if (codec
->bias_level
== SND_SOC_BIAS_OFF
) {
842 /* Initial cap charge at VMID 5k */
843 snd_soc_write(codec
, WM8978_POWER_MANAGEMENT_1
,
848 power1
|= 0x2; /* VMID 500k */
849 snd_soc_write(codec
, WM8978_POWER_MANAGEMENT_1
, power1
);
851 case SND_SOC_BIAS_OFF
:
852 /* Preserve PLL - OPCLK may be used by someone */
853 snd_soc_update_bits(codec
, WM8978_POWER_MANAGEMENT_1
, ~0x20, 0);
854 snd_soc_write(codec
, WM8978_POWER_MANAGEMENT_2
, 0);
855 snd_soc_write(codec
, WM8978_POWER_MANAGEMENT_3
, 0);
859 dev_dbg(codec
->dev
, "%s: %d, %x\n", __func__
, level
, power1
);
861 codec
->bias_level
= level
;
865 #define WM8978_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
866 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
868 static struct snd_soc_dai_ops wm8978_dai_ops
= {
869 .hw_params
= wm8978_hw_params
,
870 .digital_mute
= wm8978_mute
,
871 .set_fmt
= wm8978_set_dai_fmt
,
872 .set_clkdiv
= wm8978_set_dai_clkdiv
,
873 .set_sysclk
= wm8978_set_dai_sysclk
,
876 /* Also supports 12kHz */
877 struct snd_soc_dai wm8978_dai
= {
878 .name
= "WM8978 HiFi",
881 .stream_name
= "Playback",
884 .rates
= SNDRV_PCM_RATE_8000_48000
,
885 .formats
= WM8978_FORMATS
,
888 .stream_name
= "Capture",
891 .rates
= SNDRV_PCM_RATE_8000_48000
,
892 .formats
= WM8978_FORMATS
,
894 .ops
= &wm8978_dai_ops
,
896 EXPORT_SYMBOL_GPL(wm8978_dai
);
898 static int wm8978_suspend(struct platform_device
*pdev
, pm_message_t state
)
900 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
901 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
903 wm8978_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
904 /* Also switch PLL off */
905 snd_soc_write(codec
, WM8978_POWER_MANAGEMENT_1
, 0);
910 static int wm8978_resume(struct platform_device
*pdev
)
912 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
913 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
914 struct wm8978_priv
*wm8978
= codec
->private_data
;
916 u16
*cache
= codec
->reg_cache
;
918 /* Sync reg_cache with the hardware */
919 for (i
= 0; i
< ARRAY_SIZE(wm8978_reg
); i
++) {
920 if (i
== WM8978_RESET
)
922 if (cache
[i
] != wm8978_reg
[i
])
923 snd_soc_write(codec
, i
, cache
[i
]);
926 wm8978_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
928 if (wm8978
->f_pllout
)
930 snd_soc_update_bits(codec
, WM8978_POWER_MANAGEMENT_1
, 0x20, 0x20);
935 static int wm8978_probe(struct platform_device
*pdev
)
937 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
938 struct snd_soc_codec
*codec
;
941 if (wm8978_codec
== NULL
) {
942 dev_err(&pdev
->dev
, "Codec device not registered\n");
946 socdev
->card
->codec
= wm8978_codec
;
947 codec
= wm8978_codec
;
950 ret
= snd_soc_new_pcms(socdev
, SNDRV_DEFAULT_IDX1
, SNDRV_DEFAULT_STR1
);
952 dev_err(codec
->dev
, "failed to create pcms: %d\n", ret
);
956 snd_soc_add_controls(codec
, wm8978_snd_controls
,
957 ARRAY_SIZE(wm8978_snd_controls
));
958 wm8978_add_widgets(codec
);
964 /* power down chip */
965 static int wm8978_remove(struct platform_device
*pdev
)
967 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
969 snd_soc_free_pcms(socdev
);
970 snd_soc_dapm_free(socdev
);
975 struct snd_soc_codec_device soc_codec_dev_wm8978
= {
976 .probe
= wm8978_probe
,
977 .remove
= wm8978_remove
,
978 .suspend
= wm8978_suspend
,
979 .resume
= wm8978_resume
,
981 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8978
);
984 * These registers contain an "update" bit - bit 8. This means, for example,
985 * that one can write new DAC digital volume for both channels, but only when
986 * the update bit is set, will also the volume be updated - simultaneously for
989 static const int update_reg
[] = {
990 WM8978_LEFT_DAC_DIGITAL_VOLUME
,
991 WM8978_RIGHT_DAC_DIGITAL_VOLUME
,
992 WM8978_LEFT_ADC_DIGITAL_VOLUME
,
993 WM8978_RIGHT_ADC_DIGITAL_VOLUME
,
994 WM8978_LEFT_INP_PGA_CONTROL
,
995 WM8978_RIGHT_INP_PGA_CONTROL
,
996 WM8978_LOUT1_HP_CONTROL
,
997 WM8978_ROUT1_HP_CONTROL
,
998 WM8978_LOUT2_SPK_CONTROL
,
999 WM8978_ROUT2_SPK_CONTROL
,
1002 static __devinit
int wm8978_register(struct wm8978_priv
*wm8978
)
1005 struct snd_soc_codec
*codec
= &wm8978
->codec
;
1008 dev_err(codec
->dev
, "Another WM8978 is registered\n");
1013 * Set default system clock to PLL, it is more precise, this is also the
1014 * default hardware setting
1016 wm8978
->sysclk
= WM8978_PLL
;
1018 mutex_init(&codec
->mutex
);
1019 INIT_LIST_HEAD(&codec
->dapm_widgets
);
1020 INIT_LIST_HEAD(&codec
->dapm_paths
);
1022 codec
->private_data
= wm8978
;
1023 codec
->name
= "WM8978";
1024 codec
->owner
= THIS_MODULE
;
1025 codec
->bias_level
= SND_SOC_BIAS_OFF
;
1026 codec
->set_bias_level
= wm8978_set_bias_level
;
1027 codec
->dai
= &wm8978_dai
;
1029 codec
->reg_cache_size
= WM8978_CACHEREGNUM
;
1030 codec
->reg_cache
= &wm8978
->reg_cache
;
1032 ret
= snd_soc_codec_set_cache_io(codec
, 7, 9, SND_SOC_I2C
);
1034 dev_err(codec
->dev
, "Failed to set cache I/O: %d\n", ret
);
1038 memcpy(codec
->reg_cache
, wm8978_reg
, sizeof(wm8978_reg
));
1041 * Set the update bit in all registers, that have one. This way all
1042 * writes to those registers will also cause the update bit to be
1045 for (i
= 0; i
< ARRAY_SIZE(update_reg
); i
++)
1046 ((u16
*)codec
->reg_cache
)[update_reg
[i
]] |= 0x100;
1048 /* Reset the codec */
1049 ret
= snd_soc_write(codec
, WM8978_RESET
, 0);
1051 dev_err(codec
->dev
, "Failed to issue reset\n");
1055 wm8978_dai
.dev
= codec
->dev
;
1057 wm8978_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1059 wm8978_codec
= codec
;
1061 ret
= snd_soc_register_codec(codec
);
1063 dev_err(codec
->dev
, "Failed to register codec: %d\n", ret
);
1067 ret
= snd_soc_register_dai(&wm8978_dai
);
1069 dev_err(codec
->dev
, "Failed to register DAI: %d\n", ret
);
1076 snd_soc_unregister_codec(codec
);
1082 static __devexit
void wm8978_unregister(struct wm8978_priv
*wm8978
)
1084 wm8978_set_bias_level(&wm8978
->codec
, SND_SOC_BIAS_OFF
);
1085 snd_soc_unregister_dai(&wm8978_dai
);
1086 snd_soc_unregister_codec(&wm8978
->codec
);
1088 wm8978_codec
= NULL
;
1091 static __devinit
int wm8978_i2c_probe(struct i2c_client
*i2c
,
1092 const struct i2c_device_id
*id
)
1094 struct wm8978_priv
*wm8978
;
1095 struct snd_soc_codec
*codec
;
1097 wm8978
= kzalloc(sizeof(struct wm8978_priv
), GFP_KERNEL
);
1101 codec
= &wm8978
->codec
;
1102 codec
->hw_write
= (hw_write_t
)i2c_master_send
;
1104 i2c_set_clientdata(i2c
, wm8978
);
1105 codec
->control_data
= i2c
;
1107 codec
->dev
= &i2c
->dev
;
1109 return wm8978_register(wm8978
);
1112 static __devexit
int wm8978_i2c_remove(struct i2c_client
*client
)
1114 struct wm8978_priv
*wm8978
= i2c_get_clientdata(client
);
1115 wm8978_unregister(wm8978
);
1119 static const struct i2c_device_id wm8978_i2c_id
[] = {
1123 MODULE_DEVICE_TABLE(i2c
, wm8978_i2c_id
);
1125 static struct i2c_driver wm8978_i2c_driver
= {
1128 .owner
= THIS_MODULE
,
1130 .probe
= wm8978_i2c_probe
,
1131 .remove
= __devexit_p(wm8978_i2c_remove
),
1132 .id_table
= wm8978_i2c_id
,
1135 static int __init
wm8978_modinit(void)
1137 return i2c_add_driver(&wm8978_i2c_driver
);
1139 module_init(wm8978_modinit
);
1141 static void __exit
wm8978_exit(void)
1143 i2c_del_driver(&wm8978_i2c_driver
);
1145 module_exit(wm8978_exit
);
1147 MODULE_DESCRIPTION("ASoC WM8978 codec driver");
1148 MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1149 MODULE_LICENSE("GPL");