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Merge branch 'fixes-gpio-to-irq' into fixes
[deliverable/linux.git] / sound / soc / codecs / wm8993.c
1 /*
2 * wm8993.c -- WM8993 ALSA SoC audio driver
3 *
4 * Copyright 2009, 2010 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/pm.h>
18 #include <linux/i2c.h>
19 #include <linux/regmap.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/spi/spi.h>
22 #include <linux/slab.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/tlv.h>
27 #include <sound/soc.h>
28 #include <sound/initval.h>
29 #include <sound/wm8993.h>
30
31 #include "wm8993.h"
32 #include "wm_hubs.h"
33
34 #define WM8993_NUM_SUPPLIES 6
35 static const char *wm8993_supply_names[WM8993_NUM_SUPPLIES] = {
36 "DCVDD",
37 "DBVDD",
38 "AVDD1",
39 "AVDD2",
40 "CPVDD",
41 "SPKVDD",
42 };
43
44 static struct reg_default wm8993_reg_defaults[] = {
45 { 1, 0x0000 }, /* R1 - Power Management (1) */
46 { 2, 0x6000 }, /* R2 - Power Management (2) */
47 { 3, 0x0000 }, /* R3 - Power Management (3) */
48 { 4, 0x4050 }, /* R4 - Audio Interface (1) */
49 { 5, 0x4000 }, /* R5 - Audio Interface (2) */
50 { 6, 0x01C8 }, /* R6 - Clocking 1 */
51 { 7, 0x0000 }, /* R7 - Clocking 2 */
52 { 8, 0x0000 }, /* R8 - Audio Interface (3) */
53 { 9, 0x0040 }, /* R9 - Audio Interface (4) */
54 { 10, 0x0004 }, /* R10 - DAC CTRL */
55 { 11, 0x00C0 }, /* R11 - Left DAC Digital Volume */
56 { 12, 0x00C0 }, /* R12 - Right DAC Digital Volume */
57 { 13, 0x0000 }, /* R13 - Digital Side Tone */
58 { 14, 0x0300 }, /* R14 - ADC CTRL */
59 { 15, 0x00C0 }, /* R15 - Left ADC Digital Volume */
60 { 16, 0x00C0 }, /* R16 - Right ADC Digital Volume */
61 { 18, 0x0000 }, /* R18 - GPIO CTRL 1 */
62 { 19, 0x0010 }, /* R19 - GPIO1 */
63 { 20, 0x0000 }, /* R20 - IRQ_DEBOUNCE */
64 { 21, 0x0000 }, /* R21 - Inputs Clamp */
65 { 22, 0x8000 }, /* R22 - GPIOCTRL 2 */
66 { 23, 0x0800 }, /* R23 - GPIO_POL */
67 { 24, 0x008B }, /* R24 - Left Line Input 1&2 Volume */
68 { 25, 0x008B }, /* R25 - Left Line Input 3&4 Volume */
69 { 26, 0x008B }, /* R26 - Right Line Input 1&2 Volume */
70 { 27, 0x008B }, /* R27 - Right Line Input 3&4 Volume */
71 { 28, 0x006D }, /* R28 - Left Output Volume */
72 { 29, 0x006D }, /* R29 - Right Output Volume */
73 { 30, 0x0066 }, /* R30 - Line Outputs Volume */
74 { 31, 0x0020 }, /* R31 - HPOUT2 Volume */
75 { 32, 0x0079 }, /* R32 - Left OPGA Volume */
76 { 33, 0x0079 }, /* R33 - Right OPGA Volume */
77 { 34, 0x0003 }, /* R34 - SPKMIXL Attenuation */
78 { 35, 0x0003 }, /* R35 - SPKMIXR Attenuation */
79 { 36, 0x0011 }, /* R36 - SPKOUT Mixers */
80 { 37, 0x0100 }, /* R37 - SPKOUT Boost */
81 { 38, 0x0079 }, /* R38 - Speaker Volume Left */
82 { 39, 0x0079 }, /* R39 - Speaker Volume Right */
83 { 40, 0x0000 }, /* R40 - Input Mixer2 */
84 { 41, 0x0000 }, /* R41 - Input Mixer3 */
85 { 42, 0x0000 }, /* R42 - Input Mixer4 */
86 { 43, 0x0000 }, /* R43 - Input Mixer5 */
87 { 44, 0x0000 }, /* R44 - Input Mixer6 */
88 { 45, 0x0000 }, /* R45 - Output Mixer1 */
89 { 46, 0x0000 }, /* R46 - Output Mixer2 */
90 { 47, 0x0000 }, /* R47 - Output Mixer3 */
91 { 48, 0x0000 }, /* R48 - Output Mixer4 */
92 { 49, 0x0000 }, /* R49 - Output Mixer5 */
93 { 50, 0x0000 }, /* R50 - Output Mixer6 */
94 { 51, 0x0000 }, /* R51 - HPOUT2 Mixer */
95 { 52, 0x0000 }, /* R52 - Line Mixer1 */
96 { 53, 0x0000 }, /* R53 - Line Mixer2 */
97 { 54, 0x0000 }, /* R54 - Speaker Mixer */
98 { 55, 0x0000 }, /* R55 - Additional Control */
99 { 56, 0x0000 }, /* R56 - AntiPOP1 */
100 { 57, 0x0000 }, /* R57 - AntiPOP2 */
101 { 58, 0x0000 }, /* R58 - MICBIAS */
102 { 60, 0x0000 }, /* R60 - FLL Control 1 */
103 { 61, 0x0000 }, /* R61 - FLL Control 2 */
104 { 62, 0x0000 }, /* R62 - FLL Control 3 */
105 { 63, 0x2EE0 }, /* R63 - FLL Control 4 */
106 { 64, 0x0002 }, /* R64 - FLL Control 5 */
107 { 65, 0x2287 }, /* R65 - Clocking 3 */
108 { 66, 0x025F }, /* R66 - Clocking 4 */
109 { 67, 0x0000 }, /* R67 - MW Slave Control */
110 { 69, 0x0002 }, /* R69 - Bus Control 1 */
111 { 70, 0x0000 }, /* R70 - Write Sequencer 0 */
112 { 71, 0x0000 }, /* R71 - Write Sequencer 1 */
113 { 72, 0x0000 }, /* R72 - Write Sequencer 2 */
114 { 73, 0x0000 }, /* R73 - Write Sequencer 3 */
115 { 74, 0x0000 }, /* R74 - Write Sequencer 4 */
116 { 75, 0x0000 }, /* R75 - Write Sequencer 5 */
117 { 76, 0x1F25 }, /* R76 - Charge Pump 1 */
118 { 81, 0x0000 }, /* R81 - Class W 0 */
119 { 85, 0x054A }, /* R85 - DC Servo 1 */
120 { 87, 0x0000 }, /* R87 - DC Servo 3 */
121 { 96, 0x0100 }, /* R96 - Analogue HP 0 */
122 { 98, 0x0000 }, /* R98 - EQ1 */
123 { 99, 0x000C }, /* R99 - EQ2 */
124 { 100, 0x000C }, /* R100 - EQ3 */
125 { 101, 0x000C }, /* R101 - EQ4 */
126 { 102, 0x000C }, /* R102 - EQ5 */
127 { 103, 0x000C }, /* R103 - EQ6 */
128 { 104, 0x0FCA }, /* R104 - EQ7 */
129 { 105, 0x0400 }, /* R105 - EQ8 */
130 { 106, 0x00D8 }, /* R106 - EQ9 */
131 { 107, 0x1EB5 }, /* R107 - EQ10 */
132 { 108, 0xF145 }, /* R108 - EQ11 */
133 { 109, 0x0B75 }, /* R109 - EQ12 */
134 { 110, 0x01C5 }, /* R110 - EQ13 */
135 { 111, 0x1C58 }, /* R111 - EQ14 */
136 { 112, 0xF373 }, /* R112 - EQ15 */
137 { 113, 0x0A54 }, /* R113 - EQ16 */
138 { 114, 0x0558 }, /* R114 - EQ17 */
139 { 115, 0x168E }, /* R115 - EQ18 */
140 { 116, 0xF829 }, /* R116 - EQ19 */
141 { 117, 0x07AD }, /* R117 - EQ20 */
142 { 118, 0x1103 }, /* R118 - EQ21 */
143 { 119, 0x0564 }, /* R119 - EQ22 */
144 { 120, 0x0559 }, /* R120 - EQ23 */
145 { 121, 0x4000 }, /* R121 - EQ24 */
146 { 122, 0x0000 }, /* R122 - Digital Pulls */
147 { 123, 0x0F08 }, /* R123 - DRC Control 1 */
148 { 124, 0x0000 }, /* R124 - DRC Control 2 */
149 { 125, 0x0080 }, /* R125 - DRC Control 3 */
150 { 126, 0x0000 }, /* R126 - DRC Control 4 */
151 };
152
153 static struct {
154 int ratio;
155 int clk_sys_rate;
156 } clk_sys_rates[] = {
157 { 64, 0 },
158 { 128, 1 },
159 { 192, 2 },
160 { 256, 3 },
161 { 384, 4 },
162 { 512, 5 },
163 { 768, 6 },
164 { 1024, 7 },
165 { 1408, 8 },
166 { 1536, 9 },
167 };
168
169 static struct {
170 int rate;
171 int sample_rate;
172 } sample_rates[] = {
173 { 8000, 0 },
174 { 11025, 1 },
175 { 12000, 1 },
176 { 16000, 2 },
177 { 22050, 3 },
178 { 24000, 3 },
179 { 32000, 4 },
180 { 44100, 5 },
181 { 48000, 5 },
182 };
183
184 static struct {
185 int div; /* *10 due to .5s */
186 int bclk_div;
187 } bclk_divs[] = {
188 { 10, 0 },
189 { 15, 1 },
190 { 20, 2 },
191 { 30, 3 },
192 { 40, 4 },
193 { 55, 5 },
194 { 60, 6 },
195 { 80, 7 },
196 { 110, 8 },
197 { 120, 9 },
198 { 160, 10 },
199 { 220, 11 },
200 { 240, 12 },
201 { 320, 13 },
202 { 440, 14 },
203 { 480, 15 },
204 };
205
206 struct wm8993_priv {
207 struct wm_hubs_data hubs_data;
208 struct device *dev;
209 struct regmap *regmap;
210 struct regulator_bulk_data supplies[WM8993_NUM_SUPPLIES];
211 struct wm8993_platform_data pdata;
212 struct completion fll_lock;
213 int master;
214 int sysclk_source;
215 int tdm_slots;
216 int tdm_width;
217 unsigned int mclk_rate;
218 unsigned int sysclk_rate;
219 unsigned int fs;
220 unsigned int bclk;
221 int class_w_users;
222 unsigned int fll_fref;
223 unsigned int fll_fout;
224 int fll_src;
225 };
226
227 static bool wm8993_volatile(struct device *dev, unsigned int reg)
228 {
229 switch (reg) {
230 case WM8993_SOFTWARE_RESET:
231 case WM8993_GPIO_CTRL_1:
232 case WM8993_DC_SERVO_0:
233 case WM8993_DC_SERVO_READBACK_0:
234 case WM8993_DC_SERVO_READBACK_1:
235 case WM8993_DC_SERVO_READBACK_2:
236 return true;
237 default:
238 return false;
239 }
240 }
241
242 static bool wm8993_readable(struct device *dev, unsigned int reg)
243 {
244 switch (reg) {
245 case WM8993_SOFTWARE_RESET:
246 case WM8993_POWER_MANAGEMENT_1:
247 case WM8993_POWER_MANAGEMENT_2:
248 case WM8993_POWER_MANAGEMENT_3:
249 case WM8993_AUDIO_INTERFACE_1:
250 case WM8993_AUDIO_INTERFACE_2:
251 case WM8993_CLOCKING_1:
252 case WM8993_CLOCKING_2:
253 case WM8993_AUDIO_INTERFACE_3:
254 case WM8993_AUDIO_INTERFACE_4:
255 case WM8993_DAC_CTRL:
256 case WM8993_LEFT_DAC_DIGITAL_VOLUME:
257 case WM8993_RIGHT_DAC_DIGITAL_VOLUME:
258 case WM8993_DIGITAL_SIDE_TONE:
259 case WM8993_ADC_CTRL:
260 case WM8993_LEFT_ADC_DIGITAL_VOLUME:
261 case WM8993_RIGHT_ADC_DIGITAL_VOLUME:
262 case WM8993_GPIO_CTRL_1:
263 case WM8993_GPIO1:
264 case WM8993_IRQ_DEBOUNCE:
265 case WM8993_GPIOCTRL_2:
266 case WM8993_GPIO_POL:
267 case WM8993_LEFT_LINE_INPUT_1_2_VOLUME:
268 case WM8993_LEFT_LINE_INPUT_3_4_VOLUME:
269 case WM8993_RIGHT_LINE_INPUT_1_2_VOLUME:
270 case WM8993_RIGHT_LINE_INPUT_3_4_VOLUME:
271 case WM8993_LEFT_OUTPUT_VOLUME:
272 case WM8993_RIGHT_OUTPUT_VOLUME:
273 case WM8993_LINE_OUTPUTS_VOLUME:
274 case WM8993_HPOUT2_VOLUME:
275 case WM8993_LEFT_OPGA_VOLUME:
276 case WM8993_RIGHT_OPGA_VOLUME:
277 case WM8993_SPKMIXL_ATTENUATION:
278 case WM8993_SPKMIXR_ATTENUATION:
279 case WM8993_SPKOUT_MIXERS:
280 case WM8993_SPKOUT_BOOST:
281 case WM8993_SPEAKER_VOLUME_LEFT:
282 case WM8993_SPEAKER_VOLUME_RIGHT:
283 case WM8993_INPUT_MIXER2:
284 case WM8993_INPUT_MIXER3:
285 case WM8993_INPUT_MIXER4:
286 case WM8993_INPUT_MIXER5:
287 case WM8993_INPUT_MIXER6:
288 case WM8993_OUTPUT_MIXER1:
289 case WM8993_OUTPUT_MIXER2:
290 case WM8993_OUTPUT_MIXER3:
291 case WM8993_OUTPUT_MIXER4:
292 case WM8993_OUTPUT_MIXER5:
293 case WM8993_OUTPUT_MIXER6:
294 case WM8993_HPOUT2_MIXER:
295 case WM8993_LINE_MIXER1:
296 case WM8993_LINE_MIXER2:
297 case WM8993_SPEAKER_MIXER:
298 case WM8993_ADDITIONAL_CONTROL:
299 case WM8993_ANTIPOP1:
300 case WM8993_ANTIPOP2:
301 case WM8993_MICBIAS:
302 case WM8993_FLL_CONTROL_1:
303 case WM8993_FLL_CONTROL_2:
304 case WM8993_FLL_CONTROL_3:
305 case WM8993_FLL_CONTROL_4:
306 case WM8993_FLL_CONTROL_5:
307 case WM8993_CLOCKING_3:
308 case WM8993_CLOCKING_4:
309 case WM8993_MW_SLAVE_CONTROL:
310 case WM8993_BUS_CONTROL_1:
311 case WM8993_WRITE_SEQUENCER_0:
312 case WM8993_WRITE_SEQUENCER_1:
313 case WM8993_WRITE_SEQUENCER_2:
314 case WM8993_WRITE_SEQUENCER_3:
315 case WM8993_WRITE_SEQUENCER_4:
316 case WM8993_WRITE_SEQUENCER_5:
317 case WM8993_CHARGE_PUMP_1:
318 case WM8993_CLASS_W_0:
319 case WM8993_DC_SERVO_0:
320 case WM8993_DC_SERVO_1:
321 case WM8993_DC_SERVO_3:
322 case WM8993_DC_SERVO_READBACK_0:
323 case WM8993_DC_SERVO_READBACK_1:
324 case WM8993_DC_SERVO_READBACK_2:
325 case WM8993_ANALOGUE_HP_0:
326 case WM8993_EQ1:
327 case WM8993_EQ2:
328 case WM8993_EQ3:
329 case WM8993_EQ4:
330 case WM8993_EQ5:
331 case WM8993_EQ6:
332 case WM8993_EQ7:
333 case WM8993_EQ8:
334 case WM8993_EQ9:
335 case WM8993_EQ10:
336 case WM8993_EQ11:
337 case WM8993_EQ12:
338 case WM8993_EQ13:
339 case WM8993_EQ14:
340 case WM8993_EQ15:
341 case WM8993_EQ16:
342 case WM8993_EQ17:
343 case WM8993_EQ18:
344 case WM8993_EQ19:
345 case WM8993_EQ20:
346 case WM8993_EQ21:
347 case WM8993_EQ22:
348 case WM8993_EQ23:
349 case WM8993_EQ24:
350 case WM8993_DIGITAL_PULLS:
351 case WM8993_DRC_CONTROL_1:
352 case WM8993_DRC_CONTROL_2:
353 case WM8993_DRC_CONTROL_3:
354 case WM8993_DRC_CONTROL_4:
355 return true;
356 default:
357 return false;
358 }
359 }
360
361 struct _fll_div {
362 u16 fll_fratio;
363 u16 fll_outdiv;
364 u16 fll_clk_ref_div;
365 u16 n;
366 u16 k;
367 };
368
369 /* The size in bits of the FLL divide multiplied by 10
370 * to allow rounding later */
371 #define FIXED_FLL_SIZE ((1 << 16) * 10)
372
373 static struct {
374 unsigned int min;
375 unsigned int max;
376 u16 fll_fratio;
377 int ratio;
378 } fll_fratios[] = {
379 { 0, 64000, 4, 16 },
380 { 64000, 128000, 3, 8 },
381 { 128000, 256000, 2, 4 },
382 { 256000, 1000000, 1, 2 },
383 { 1000000, 13500000, 0, 1 },
384 };
385
386 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
387 unsigned int Fout)
388 {
389 u64 Kpart;
390 unsigned int K, Ndiv, Nmod, target;
391 unsigned int div;
392 int i;
393
394 /* Fref must be <=13.5MHz */
395 div = 1;
396 fll_div->fll_clk_ref_div = 0;
397 while ((Fref / div) > 13500000) {
398 div *= 2;
399 fll_div->fll_clk_ref_div++;
400
401 if (div > 8) {
402 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
403 Fref);
404 return -EINVAL;
405 }
406 }
407
408 pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
409
410 /* Apply the division for our remaining calculations */
411 Fref /= div;
412
413 /* Fvco should be 90-100MHz; don't check the upper bound */
414 div = 0;
415 target = Fout * 2;
416 while (target < 90000000) {
417 div++;
418 target *= 2;
419 if (div > 7) {
420 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
421 Fout);
422 return -EINVAL;
423 }
424 }
425 fll_div->fll_outdiv = div;
426
427 pr_debug("Fvco=%dHz\n", target);
428
429 /* Find an appropriate FLL_FRATIO and factor it out of the target */
430 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
431 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
432 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
433 target /= fll_fratios[i].ratio;
434 break;
435 }
436 }
437 if (i == ARRAY_SIZE(fll_fratios)) {
438 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
439 return -EINVAL;
440 }
441
442 /* Now, calculate N.K */
443 Ndiv = target / Fref;
444
445 fll_div->n = Ndiv;
446 Nmod = target % Fref;
447 pr_debug("Nmod=%d\n", Nmod);
448
449 /* Calculate fractional part - scale up so we can round. */
450 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
451
452 do_div(Kpart, Fref);
453
454 K = Kpart & 0xFFFFFFFF;
455
456 if ((K % 10) >= 5)
457 K += 5;
458
459 /* Move down to proper range now rounding is done */
460 fll_div->k = K / 10;
461
462 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
463 fll_div->n, fll_div->k,
464 fll_div->fll_fratio, fll_div->fll_outdiv,
465 fll_div->fll_clk_ref_div);
466
467 return 0;
468 }
469
470 static int _wm8993_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
471 unsigned int Fref, unsigned int Fout)
472 {
473 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
474 struct i2c_client *i2c = to_i2c_client(codec->dev);
475 u16 reg1, reg4, reg5;
476 struct _fll_div fll_div;
477 unsigned int timeout;
478 int ret;
479
480 /* Any change? */
481 if (Fref == wm8993->fll_fref && Fout == wm8993->fll_fout)
482 return 0;
483
484 /* Disable the FLL */
485 if (Fout == 0) {
486 dev_dbg(codec->dev, "FLL disabled\n");
487 wm8993->fll_fref = 0;
488 wm8993->fll_fout = 0;
489
490 reg1 = snd_soc_read(codec, WM8993_FLL_CONTROL_1);
491 reg1 &= ~WM8993_FLL_ENA;
492 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1);
493
494 return 0;
495 }
496
497 ret = fll_factors(&fll_div, Fref, Fout);
498 if (ret != 0)
499 return ret;
500
501 reg5 = snd_soc_read(codec, WM8993_FLL_CONTROL_5);
502 reg5 &= ~WM8993_FLL_CLK_SRC_MASK;
503
504 switch (fll_id) {
505 case WM8993_FLL_MCLK:
506 break;
507
508 case WM8993_FLL_LRCLK:
509 reg5 |= 1;
510 break;
511
512 case WM8993_FLL_BCLK:
513 reg5 |= 2;
514 break;
515
516 default:
517 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
518 return -EINVAL;
519 }
520
521 /* Any FLL configuration change requires that the FLL be
522 * disabled first. */
523 reg1 = snd_soc_read(codec, WM8993_FLL_CONTROL_1);
524 reg1 &= ~WM8993_FLL_ENA;
525 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1);
526
527 /* Apply the configuration */
528 if (fll_div.k)
529 reg1 |= WM8993_FLL_FRAC_MASK;
530 else
531 reg1 &= ~WM8993_FLL_FRAC_MASK;
532 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1);
533
534 snd_soc_write(codec, WM8993_FLL_CONTROL_2,
535 (fll_div.fll_outdiv << WM8993_FLL_OUTDIV_SHIFT) |
536 (fll_div.fll_fratio << WM8993_FLL_FRATIO_SHIFT));
537 snd_soc_write(codec, WM8993_FLL_CONTROL_3, fll_div.k);
538
539 reg4 = snd_soc_read(codec, WM8993_FLL_CONTROL_4);
540 reg4 &= ~WM8993_FLL_N_MASK;
541 reg4 |= fll_div.n << WM8993_FLL_N_SHIFT;
542 snd_soc_write(codec, WM8993_FLL_CONTROL_4, reg4);
543
544 reg5 &= ~WM8993_FLL_CLK_REF_DIV_MASK;
545 reg5 |= fll_div.fll_clk_ref_div << WM8993_FLL_CLK_REF_DIV_SHIFT;
546 snd_soc_write(codec, WM8993_FLL_CONTROL_5, reg5);
547
548 /* If we've got an interrupt wired up make sure we get it */
549 if (i2c->irq)
550 timeout = msecs_to_jiffies(20);
551 else if (Fref < 1000000)
552 timeout = msecs_to_jiffies(3);
553 else
554 timeout = msecs_to_jiffies(1);
555
556 try_wait_for_completion(&wm8993->fll_lock);
557
558 /* Enable the FLL */
559 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1 | WM8993_FLL_ENA);
560
561 timeout = wait_for_completion_timeout(&wm8993->fll_lock, timeout);
562 if (i2c->irq && !timeout)
563 dev_warn(codec->dev, "Timed out waiting for FLL\n");
564
565 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
566
567 wm8993->fll_fref = Fref;
568 wm8993->fll_fout = Fout;
569 wm8993->fll_src = source;
570
571 return 0;
572 }
573
574 static int wm8993_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
575 unsigned int Fref, unsigned int Fout)
576 {
577 return _wm8993_set_fll(dai->codec, fll_id, source, Fref, Fout);
578 }
579
580 static int configure_clock(struct snd_soc_codec *codec)
581 {
582 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
583 unsigned int reg;
584
585 /* This should be done on init() for bypass paths */
586 switch (wm8993->sysclk_source) {
587 case WM8993_SYSCLK_MCLK:
588 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8993->mclk_rate);
589
590 reg = snd_soc_read(codec, WM8993_CLOCKING_2);
591 reg &= ~(WM8993_MCLK_DIV | WM8993_SYSCLK_SRC);
592 if (wm8993->mclk_rate > 13500000) {
593 reg |= WM8993_MCLK_DIV;
594 wm8993->sysclk_rate = wm8993->mclk_rate / 2;
595 } else {
596 reg &= ~WM8993_MCLK_DIV;
597 wm8993->sysclk_rate = wm8993->mclk_rate;
598 }
599 snd_soc_write(codec, WM8993_CLOCKING_2, reg);
600 break;
601
602 case WM8993_SYSCLK_FLL:
603 dev_dbg(codec->dev, "Using %dHz FLL clock\n",
604 wm8993->fll_fout);
605
606 reg = snd_soc_read(codec, WM8993_CLOCKING_2);
607 reg |= WM8993_SYSCLK_SRC;
608 if (wm8993->fll_fout > 13500000) {
609 reg |= WM8993_MCLK_DIV;
610 wm8993->sysclk_rate = wm8993->fll_fout / 2;
611 } else {
612 reg &= ~WM8993_MCLK_DIV;
613 wm8993->sysclk_rate = wm8993->fll_fout;
614 }
615 snd_soc_write(codec, WM8993_CLOCKING_2, reg);
616 break;
617
618 default:
619 dev_err(codec->dev, "System clock not configured\n");
620 return -EINVAL;
621 }
622
623 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8993->sysclk_rate);
624
625 return 0;
626 }
627
628 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
629 static const DECLARE_TLV_DB_SCALE(drc_comp_threash, -4500, 75, 0);
630 static const DECLARE_TLV_DB_SCALE(drc_comp_amp, -2250, 75, 0);
631 static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
632 static const unsigned int drc_max_tlv[] = {
633 TLV_DB_RANGE_HEAD(2),
634 0, 2, TLV_DB_SCALE_ITEM(1200, 600, 0),
635 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
636 };
637 static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
638 static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -1800, 300, 0);
639 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
640 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
641 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
642
643 static const char *dac_deemph_text[] = {
644 "None",
645 "32kHz",
646 "44.1kHz",
647 "48kHz",
648 };
649
650 static const struct soc_enum dac_deemph =
651 SOC_ENUM_SINGLE(WM8993_DAC_CTRL, 4, 4, dac_deemph_text);
652
653 static const char *adc_hpf_text[] = {
654 "Hi-Fi",
655 "Voice 1",
656 "Voice 2",
657 "Voice 3",
658 };
659
660 static const struct soc_enum adc_hpf =
661 SOC_ENUM_SINGLE(WM8993_ADC_CTRL, 5, 4, adc_hpf_text);
662
663 static const char *drc_path_text[] = {
664 "ADC",
665 "DAC"
666 };
667
668 static const struct soc_enum drc_path =
669 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1, 14, 2, drc_path_text);
670
671 static const char *drc_r0_text[] = {
672 "1",
673 "1/2",
674 "1/4",
675 "1/8",
676 "1/16",
677 "0",
678 };
679
680 static const struct soc_enum drc_r0 =
681 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 8, 6, drc_r0_text);
682
683 static const char *drc_r1_text[] = {
684 "1",
685 "1/2",
686 "1/4",
687 "1/8",
688 "0",
689 };
690
691 static const struct soc_enum drc_r1 =
692 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_4, 13, 5, drc_r1_text);
693
694 static const char *drc_attack_text[] = {
695 "Reserved",
696 "181us",
697 "363us",
698 "726us",
699 "1.45ms",
700 "2.9ms",
701 "5.8ms",
702 "11.6ms",
703 "23.2ms",
704 "46.4ms",
705 "92.8ms",
706 "185.6ms",
707 };
708
709 static const struct soc_enum drc_attack =
710 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2, 12, 12, drc_attack_text);
711
712 static const char *drc_decay_text[] = {
713 "186ms",
714 "372ms",
715 "743ms",
716 "1.49s",
717 "2.97ms",
718 "5.94ms",
719 "11.89ms",
720 "23.78ms",
721 "47.56ms",
722 };
723
724 static const struct soc_enum drc_decay =
725 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2, 8, 9, drc_decay_text);
726
727 static const char *drc_ff_text[] = {
728 "5 samples",
729 "9 samples",
730 };
731
732 static const struct soc_enum drc_ff =
733 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 7, 2, drc_ff_text);
734
735 static const char *drc_qr_rate_text[] = {
736 "0.725ms",
737 "1.45ms",
738 "5.8ms",
739 };
740
741 static const struct soc_enum drc_qr_rate =
742 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 0, 3, drc_qr_rate_text);
743
744 static const char *drc_smooth_text[] = {
745 "Low",
746 "Medium",
747 "High",
748 };
749
750 static const struct soc_enum drc_smooth =
751 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1, 4, 3, drc_smooth_text);
752
753 static const struct snd_kcontrol_new wm8993_snd_controls[] = {
754 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8993_DIGITAL_SIDE_TONE,
755 5, 9, 12, 0, sidetone_tlv),
756
757 SOC_SINGLE("DRC Switch", WM8993_DRC_CONTROL_1, 15, 1, 0),
758 SOC_ENUM("DRC Path", drc_path),
759 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8993_DRC_CONTROL_2,
760 2, 60, 1, drc_comp_threash),
761 SOC_SINGLE_TLV("DRC Compressor Amplitude Volume", WM8993_DRC_CONTROL_3,
762 11, 30, 1, drc_comp_amp),
763 SOC_ENUM("DRC R0", drc_r0),
764 SOC_ENUM("DRC R1", drc_r1),
765 SOC_SINGLE_TLV("DRC Minimum Volume", WM8993_DRC_CONTROL_1, 2, 3, 1,
766 drc_min_tlv),
767 SOC_SINGLE_TLV("DRC Maximum Volume", WM8993_DRC_CONTROL_1, 0, 3, 0,
768 drc_max_tlv),
769 SOC_ENUM("DRC Attack Rate", drc_attack),
770 SOC_ENUM("DRC Decay Rate", drc_decay),
771 SOC_ENUM("DRC FF Delay", drc_ff),
772 SOC_SINGLE("DRC Anti-clip Switch", WM8993_DRC_CONTROL_1, 9, 1, 0),
773 SOC_SINGLE("DRC Quick Release Switch", WM8993_DRC_CONTROL_1, 10, 1, 0),
774 SOC_SINGLE_TLV("DRC Quick Release Volume", WM8993_DRC_CONTROL_3, 2, 3, 0,
775 drc_qr_tlv),
776 SOC_ENUM("DRC Quick Release Rate", drc_qr_rate),
777 SOC_SINGLE("DRC Smoothing Switch", WM8993_DRC_CONTROL_1, 11, 1, 0),
778 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8993_DRC_CONTROL_1, 8, 1, 0),
779 SOC_ENUM("DRC Smoothing Hysteresis Threshold", drc_smooth),
780 SOC_SINGLE_TLV("DRC Startup Volume", WM8993_DRC_CONTROL_4, 8, 18, 0,
781 drc_startup_tlv),
782
783 SOC_SINGLE("EQ Switch", WM8993_EQ1, 0, 1, 0),
784
785 SOC_DOUBLE_R_TLV("Capture Volume", WM8993_LEFT_ADC_DIGITAL_VOLUME,
786 WM8993_RIGHT_ADC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
787 SOC_SINGLE("ADC High Pass Filter Switch", WM8993_ADC_CTRL, 8, 1, 0),
788 SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
789
790 SOC_DOUBLE_R_TLV("Playback Volume", WM8993_LEFT_DAC_DIGITAL_VOLUME,
791 WM8993_RIGHT_DAC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
792 SOC_SINGLE_TLV("Playback Boost Volume", WM8993_AUDIO_INTERFACE_2, 10, 3, 0,
793 dac_boost_tlv),
794 SOC_ENUM("DAC Deemphasis", dac_deemph),
795
796 SOC_SINGLE_TLV("SPKL DAC Volume", WM8993_SPKMIXL_ATTENUATION,
797 2, 1, 1, wm_hubs_spkmix_tlv),
798
799 SOC_SINGLE_TLV("SPKR DAC Volume", WM8993_SPKMIXR_ATTENUATION,
800 2, 1, 1, wm_hubs_spkmix_tlv),
801 };
802
803 static const struct snd_kcontrol_new wm8993_eq_controls[] = {
804 SOC_SINGLE_TLV("EQ1 Volume", WM8993_EQ2, 0, 24, 0, eq_tlv),
805 SOC_SINGLE_TLV("EQ2 Volume", WM8993_EQ3, 0, 24, 0, eq_tlv),
806 SOC_SINGLE_TLV("EQ3 Volume", WM8993_EQ4, 0, 24, 0, eq_tlv),
807 SOC_SINGLE_TLV("EQ4 Volume", WM8993_EQ5, 0, 24, 0, eq_tlv),
808 SOC_SINGLE_TLV("EQ5 Volume", WM8993_EQ6, 0, 24, 0, eq_tlv),
809 };
810
811 static int clk_sys_event(struct snd_soc_dapm_widget *w,
812 struct snd_kcontrol *kcontrol, int event)
813 {
814 struct snd_soc_codec *codec = w->codec;
815
816 switch (event) {
817 case SND_SOC_DAPM_PRE_PMU:
818 return configure_clock(codec);
819
820 case SND_SOC_DAPM_POST_PMD:
821 break;
822 }
823
824 return 0;
825 }
826
827 /*
828 * When used with DAC outputs only the WM8993 charge pump supports
829 * operation in class W mode, providing very low power consumption
830 * when used with digital sources. Enable and disable this mode
831 * automatically depending on the mixer configuration.
832 *
833 * Currently the only supported paths are the direct DAC->headphone
834 * paths (which provide minimum power consumption anyway).
835 */
836 static int class_w_put(struct snd_kcontrol *kcontrol,
837 struct snd_ctl_elem_value *ucontrol)
838 {
839 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
840 struct snd_soc_dapm_widget *widget = wlist->widgets[0];
841 struct snd_soc_codec *codec = widget->codec;
842 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
843 int ret;
844
845 /* Turn it off if we're using the main output mixer */
846 if (ucontrol->value.integer.value[0] == 0) {
847 if (wm8993->class_w_users == 0) {
848 dev_dbg(codec->dev, "Disabling Class W\n");
849 snd_soc_update_bits(codec, WM8993_CLASS_W_0,
850 WM8993_CP_DYN_FREQ |
851 WM8993_CP_DYN_V,
852 0);
853 }
854 wm8993->class_w_users++;
855 wm8993->hubs_data.class_w = true;
856 }
857
858 /* Implement the change */
859 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
860
861 /* Enable it if we're using the direct DAC path */
862 if (ucontrol->value.integer.value[0] == 1) {
863 if (wm8993->class_w_users == 1) {
864 dev_dbg(codec->dev, "Enabling Class W\n");
865 snd_soc_update_bits(codec, WM8993_CLASS_W_0,
866 WM8993_CP_DYN_FREQ |
867 WM8993_CP_DYN_V,
868 WM8993_CP_DYN_FREQ |
869 WM8993_CP_DYN_V);
870 }
871 wm8993->class_w_users--;
872 wm8993->hubs_data.class_w = false;
873 }
874
875 dev_dbg(codec->dev, "Indirect DAC use count now %d\n",
876 wm8993->class_w_users);
877
878 return ret;
879 }
880
881 #define SOC_DAPM_ENUM_W(xname, xenum) \
882 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
883 .info = snd_soc_info_enum_double, \
884 .get = snd_soc_dapm_get_enum_double, \
885 .put = class_w_put, \
886 .private_value = (unsigned long)&xenum }
887
888 static const char *hp_mux_text[] = {
889 "Mixer",
890 "DAC",
891 };
892
893 static const struct soc_enum hpl_enum =
894 SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER1, 8, 2, hp_mux_text);
895
896 static const struct snd_kcontrol_new hpl_mux =
897 SOC_DAPM_ENUM_W("Left Headphone Mux", hpl_enum);
898
899 static const struct soc_enum hpr_enum =
900 SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER2, 8, 2, hp_mux_text);
901
902 static const struct snd_kcontrol_new hpr_mux =
903 SOC_DAPM_ENUM_W("Right Headphone Mux", hpr_enum);
904
905 static const struct snd_kcontrol_new left_speaker_mixer[] = {
906 SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 7, 1, 0),
907 SOC_DAPM_SINGLE("IN1LP Switch", WM8993_SPEAKER_MIXER, 5, 1, 0),
908 SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 3, 1, 0),
909 SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
910 };
911
912 static const struct snd_kcontrol_new right_speaker_mixer[] = {
913 SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
914 SOC_DAPM_SINGLE("IN1RP Switch", WM8993_SPEAKER_MIXER, 4, 1, 0),
915 SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 2, 1, 0),
916 SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 0, 1, 0),
917 };
918
919 static const char *aif_text[] = {
920 "Left", "Right"
921 };
922
923 static const struct soc_enum aifoutl_enum =
924 SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_1, 15, 2, aif_text);
925
926 static const struct snd_kcontrol_new aifoutl_mux =
927 SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
928
929 static const struct soc_enum aifoutr_enum =
930 SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_1, 14, 2, aif_text);
931
932 static const struct snd_kcontrol_new aifoutr_mux =
933 SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
934
935 static const struct soc_enum aifinl_enum =
936 SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_2, 15, 2, aif_text);
937
938 static const struct snd_kcontrol_new aifinl_mux =
939 SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
940
941 static const struct soc_enum aifinr_enum =
942 SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_2, 14, 2, aif_text);
943
944 static const struct snd_kcontrol_new aifinr_mux =
945 SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
946
947 static const char *sidetone_text[] = {
948 "None", "Left", "Right"
949 };
950
951 static const struct soc_enum sidetonel_enum =
952 SOC_ENUM_SINGLE(WM8993_DIGITAL_SIDE_TONE, 2, 3, sidetone_text);
953
954 static const struct snd_kcontrol_new sidetonel_mux =
955 SOC_DAPM_ENUM("Left Sidetone", sidetonel_enum);
956
957 static const struct soc_enum sidetoner_enum =
958 SOC_ENUM_SINGLE(WM8993_DIGITAL_SIDE_TONE, 0, 3, sidetone_text);
959
960 static const struct snd_kcontrol_new sidetoner_mux =
961 SOC_DAPM_ENUM("Right Sidetone", sidetoner_enum);
962
963 static const struct snd_soc_dapm_widget wm8993_dapm_widgets[] = {
964 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8993_BUS_CONTROL_1, 1, 0, clk_sys_event,
965 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
966 SND_SOC_DAPM_SUPPLY("TOCLK", WM8993_CLOCKING_1, 14, 0, NULL, 0),
967 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8993_CLOCKING_3, 0, 0, NULL, 0),
968 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, NULL, 0),
969
970 SND_SOC_DAPM_ADC("ADCL", NULL, WM8993_POWER_MANAGEMENT_2, 1, 0),
971 SND_SOC_DAPM_ADC("ADCR", NULL, WM8993_POWER_MANAGEMENT_2, 0, 0),
972
973 SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
974 SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
975
976 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
977 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
978
979 SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
980 SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
981
982 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
983 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
984
985 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &sidetonel_mux),
986 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &sidetoner_mux),
987
988 SND_SOC_DAPM_DAC("DACL", NULL, WM8993_POWER_MANAGEMENT_3, 1, 0),
989 SND_SOC_DAPM_DAC("DACR", NULL, WM8993_POWER_MANAGEMENT_3, 0, 0),
990
991 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
992 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
993
994 SND_SOC_DAPM_MIXER("SPKL", WM8993_POWER_MANAGEMENT_3, 8, 0,
995 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
996 SND_SOC_DAPM_MIXER("SPKR", WM8993_POWER_MANAGEMENT_3, 9, 0,
997 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
998 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
999 };
1000
1001 static const struct snd_soc_dapm_route routes[] = {
1002 { "MICBIAS1", NULL, "VMID" },
1003 { "MICBIAS2", NULL, "VMID" },
1004
1005 { "ADCL", NULL, "CLK_SYS" },
1006 { "ADCL", NULL, "CLK_DSP" },
1007 { "ADCR", NULL, "CLK_SYS" },
1008 { "ADCR", NULL, "CLK_DSP" },
1009
1010 { "AIFOUTL Mux", "Left", "ADCL" },
1011 { "AIFOUTL Mux", "Right", "ADCR" },
1012 { "AIFOUTR Mux", "Left", "ADCL" },
1013 { "AIFOUTR Mux", "Right", "ADCR" },
1014
1015 { "AIFOUTL", NULL, "AIFOUTL Mux" },
1016 { "AIFOUTR", NULL, "AIFOUTR Mux" },
1017
1018 { "DACL Mux", "Left", "AIFINL" },
1019 { "DACL Mux", "Right", "AIFINR" },
1020 { "DACR Mux", "Left", "AIFINL" },
1021 { "DACR Mux", "Right", "AIFINR" },
1022
1023 { "DACL Sidetone", "Left", "ADCL" },
1024 { "DACL Sidetone", "Right", "ADCR" },
1025 { "DACR Sidetone", "Left", "ADCL" },
1026 { "DACR Sidetone", "Right", "ADCR" },
1027
1028 { "DACL", NULL, "CLK_SYS" },
1029 { "DACL", NULL, "CLK_DSP" },
1030 { "DACL", NULL, "DACL Mux" },
1031 { "DACL", NULL, "DACL Sidetone" },
1032 { "DACR", NULL, "CLK_SYS" },
1033 { "DACR", NULL, "CLK_DSP" },
1034 { "DACR", NULL, "DACR Mux" },
1035 { "DACR", NULL, "DACR Sidetone" },
1036
1037 { "Left Output Mixer", "DAC Switch", "DACL" },
1038
1039 { "Right Output Mixer", "DAC Switch", "DACR" },
1040
1041 { "Left Output PGA", NULL, "CLK_SYS" },
1042
1043 { "Right Output PGA", NULL, "CLK_SYS" },
1044
1045 { "SPKL", "DAC Switch", "DACL" },
1046 { "SPKL", NULL, "CLK_SYS" },
1047
1048 { "SPKR", "DAC Switch", "DACR" },
1049 { "SPKR", NULL, "CLK_SYS" },
1050
1051 { "Left Headphone Mux", "DAC", "DACL" },
1052 { "Right Headphone Mux", "DAC", "DACR" },
1053 };
1054
1055 static int wm8993_set_bias_level(struct snd_soc_codec *codec,
1056 enum snd_soc_bias_level level)
1057 {
1058 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1059 int ret;
1060
1061 wm_hubs_set_bias_level(codec, level);
1062
1063 switch (level) {
1064 case SND_SOC_BIAS_ON:
1065 case SND_SOC_BIAS_PREPARE:
1066 /* VMID=2*40k */
1067 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1068 WM8993_VMID_SEL_MASK, 0x2);
1069 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2,
1070 WM8993_TSHUT_ENA, WM8993_TSHUT_ENA);
1071 break;
1072
1073 case SND_SOC_BIAS_STANDBY:
1074 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1075 ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies),
1076 wm8993->supplies);
1077 if (ret != 0)
1078 return ret;
1079
1080 regcache_cache_only(wm8993->regmap, false);
1081 regcache_sync(wm8993->regmap);
1082
1083 wm_hubs_vmid_ena(codec);
1084
1085 /* Bring up VMID with fast soft start */
1086 snd_soc_update_bits(codec, WM8993_ANTIPOP2,
1087 WM8993_STARTUP_BIAS_ENA |
1088 WM8993_VMID_BUF_ENA |
1089 WM8993_VMID_RAMP_MASK |
1090 WM8993_BIAS_SRC,
1091 WM8993_STARTUP_BIAS_ENA |
1092 WM8993_VMID_BUF_ENA |
1093 WM8993_VMID_RAMP_MASK |
1094 WM8993_BIAS_SRC);
1095
1096 /* If either line output is single ended we
1097 * need the VMID buffer */
1098 if (!wm8993->pdata.lineout1_diff ||
1099 !wm8993->pdata.lineout2_diff)
1100 snd_soc_update_bits(codec, WM8993_ANTIPOP1,
1101 WM8993_LINEOUT_VMID_BUF_ENA,
1102 WM8993_LINEOUT_VMID_BUF_ENA);
1103
1104 /* VMID=2*40k */
1105 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1106 WM8993_VMID_SEL_MASK |
1107 WM8993_BIAS_ENA,
1108 WM8993_BIAS_ENA | 0x2);
1109 msleep(32);
1110
1111 /* Switch to normal bias */
1112 snd_soc_update_bits(codec, WM8993_ANTIPOP2,
1113 WM8993_BIAS_SRC |
1114 WM8993_STARTUP_BIAS_ENA, 0);
1115 }
1116
1117 /* VMID=2*240k */
1118 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1119 WM8993_VMID_SEL_MASK, 0x4);
1120
1121 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2,
1122 WM8993_TSHUT_ENA, 0);
1123 break;
1124
1125 case SND_SOC_BIAS_OFF:
1126 snd_soc_update_bits(codec, WM8993_ANTIPOP1,
1127 WM8993_LINEOUT_VMID_BUF_ENA, 0);
1128
1129 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1130 WM8993_VMID_SEL_MASK | WM8993_BIAS_ENA,
1131 0);
1132
1133 snd_soc_update_bits(codec, WM8993_ANTIPOP2,
1134 WM8993_STARTUP_BIAS_ENA |
1135 WM8993_VMID_BUF_ENA |
1136 WM8993_VMID_RAMP_MASK |
1137 WM8993_BIAS_SRC, 0);
1138
1139 regcache_cache_only(wm8993->regmap, true);
1140 regcache_mark_dirty(wm8993->regmap);
1141
1142 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies),
1143 wm8993->supplies);
1144 break;
1145 }
1146
1147 codec->dapm.bias_level = level;
1148
1149 return 0;
1150 }
1151
1152 static int wm8993_set_sysclk(struct snd_soc_dai *codec_dai,
1153 int clk_id, unsigned int freq, int dir)
1154 {
1155 struct snd_soc_codec *codec = codec_dai->codec;
1156 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1157
1158 switch (clk_id) {
1159 case WM8993_SYSCLK_MCLK:
1160 wm8993->mclk_rate = freq;
1161 case WM8993_SYSCLK_FLL:
1162 wm8993->sysclk_source = clk_id;
1163 break;
1164
1165 default:
1166 return -EINVAL;
1167 }
1168
1169 return 0;
1170 }
1171
1172 static int wm8993_set_dai_fmt(struct snd_soc_dai *dai,
1173 unsigned int fmt)
1174 {
1175 struct snd_soc_codec *codec = dai->codec;
1176 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1177 unsigned int aif1 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_1);
1178 unsigned int aif4 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_4);
1179
1180 aif1 &= ~(WM8993_BCLK_DIR | WM8993_AIF_BCLK_INV |
1181 WM8993_AIF_LRCLK_INV | WM8993_AIF_FMT_MASK);
1182 aif4 &= ~WM8993_LRCLK_DIR;
1183
1184 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1185 case SND_SOC_DAIFMT_CBS_CFS:
1186 wm8993->master = 0;
1187 break;
1188 case SND_SOC_DAIFMT_CBS_CFM:
1189 aif4 |= WM8993_LRCLK_DIR;
1190 wm8993->master = 1;
1191 break;
1192 case SND_SOC_DAIFMT_CBM_CFS:
1193 aif1 |= WM8993_BCLK_DIR;
1194 wm8993->master = 1;
1195 break;
1196 case SND_SOC_DAIFMT_CBM_CFM:
1197 aif1 |= WM8993_BCLK_DIR;
1198 aif4 |= WM8993_LRCLK_DIR;
1199 wm8993->master = 1;
1200 break;
1201 default:
1202 return -EINVAL;
1203 }
1204
1205 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1206 case SND_SOC_DAIFMT_DSP_B:
1207 aif1 |= WM8993_AIF_LRCLK_INV;
1208 case SND_SOC_DAIFMT_DSP_A:
1209 aif1 |= 0x18;
1210 break;
1211 case SND_SOC_DAIFMT_I2S:
1212 aif1 |= 0x10;
1213 break;
1214 case SND_SOC_DAIFMT_RIGHT_J:
1215 break;
1216 case SND_SOC_DAIFMT_LEFT_J:
1217 aif1 |= 0x8;
1218 break;
1219 default:
1220 return -EINVAL;
1221 }
1222
1223 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1224 case SND_SOC_DAIFMT_DSP_A:
1225 case SND_SOC_DAIFMT_DSP_B:
1226 /* frame inversion not valid for DSP modes */
1227 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1228 case SND_SOC_DAIFMT_NB_NF:
1229 break;
1230 case SND_SOC_DAIFMT_IB_NF:
1231 aif1 |= WM8993_AIF_BCLK_INV;
1232 break;
1233 default:
1234 return -EINVAL;
1235 }
1236 break;
1237
1238 case SND_SOC_DAIFMT_I2S:
1239 case SND_SOC_DAIFMT_RIGHT_J:
1240 case SND_SOC_DAIFMT_LEFT_J:
1241 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1242 case SND_SOC_DAIFMT_NB_NF:
1243 break;
1244 case SND_SOC_DAIFMT_IB_IF:
1245 aif1 |= WM8993_AIF_BCLK_INV | WM8993_AIF_LRCLK_INV;
1246 break;
1247 case SND_SOC_DAIFMT_IB_NF:
1248 aif1 |= WM8993_AIF_BCLK_INV;
1249 break;
1250 case SND_SOC_DAIFMT_NB_IF:
1251 aif1 |= WM8993_AIF_LRCLK_INV;
1252 break;
1253 default:
1254 return -EINVAL;
1255 }
1256 break;
1257 default:
1258 return -EINVAL;
1259 }
1260
1261 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_1, aif1);
1262 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_4, aif4);
1263
1264 return 0;
1265 }
1266
1267 static int wm8993_hw_params(struct snd_pcm_substream *substream,
1268 struct snd_pcm_hw_params *params,
1269 struct snd_soc_dai *dai)
1270 {
1271 struct snd_soc_codec *codec = dai->codec;
1272 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1273 int ret, i, best, best_val, cur_val;
1274 unsigned int clocking1, clocking3, aif1, aif4;
1275
1276 clocking1 = snd_soc_read(codec, WM8993_CLOCKING_1);
1277 clocking1 &= ~WM8993_BCLK_DIV_MASK;
1278
1279 clocking3 = snd_soc_read(codec, WM8993_CLOCKING_3);
1280 clocking3 &= ~(WM8993_CLK_SYS_RATE_MASK | WM8993_SAMPLE_RATE_MASK);
1281
1282 aif1 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_1);
1283 aif1 &= ~WM8993_AIF_WL_MASK;
1284
1285 aif4 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_4);
1286 aif4 &= ~WM8993_LRCLK_RATE_MASK;
1287
1288 /* What BCLK do we need? */
1289 wm8993->fs = params_rate(params);
1290 wm8993->bclk = 2 * wm8993->fs;
1291 if (wm8993->tdm_slots) {
1292 dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n",
1293 wm8993->tdm_slots, wm8993->tdm_width);
1294 wm8993->bclk *= wm8993->tdm_width * wm8993->tdm_slots;
1295 } else {
1296 switch (params_format(params)) {
1297 case SNDRV_PCM_FORMAT_S16_LE:
1298 wm8993->bclk *= 16;
1299 break;
1300 case SNDRV_PCM_FORMAT_S20_3LE:
1301 wm8993->bclk *= 20;
1302 aif1 |= 0x8;
1303 break;
1304 case SNDRV_PCM_FORMAT_S24_LE:
1305 wm8993->bclk *= 24;
1306 aif1 |= 0x10;
1307 break;
1308 case SNDRV_PCM_FORMAT_S32_LE:
1309 wm8993->bclk *= 32;
1310 aif1 |= 0x18;
1311 break;
1312 default:
1313 return -EINVAL;
1314 }
1315 }
1316
1317 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8993->bclk);
1318
1319 ret = configure_clock(codec);
1320 if (ret != 0)
1321 return ret;
1322
1323 /* Select nearest CLK_SYS_RATE */
1324 best = 0;
1325 best_val = abs((wm8993->sysclk_rate / clk_sys_rates[0].ratio)
1326 - wm8993->fs);
1327 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1328 cur_val = abs((wm8993->sysclk_rate /
1329 clk_sys_rates[i].ratio) - wm8993->fs);
1330 if (cur_val < best_val) {
1331 best = i;
1332 best_val = cur_val;
1333 }
1334 }
1335 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1336 clk_sys_rates[best].ratio);
1337 clocking3 |= (clk_sys_rates[best].clk_sys_rate
1338 << WM8993_CLK_SYS_RATE_SHIFT);
1339
1340 /* SAMPLE_RATE */
1341 best = 0;
1342 best_val = abs(wm8993->fs - sample_rates[0].rate);
1343 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1344 /* Closest match */
1345 cur_val = abs(wm8993->fs - sample_rates[i].rate);
1346 if (cur_val < best_val) {
1347 best = i;
1348 best_val = cur_val;
1349 }
1350 }
1351 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1352 sample_rates[best].rate);
1353 clocking3 |= (sample_rates[best].sample_rate
1354 << WM8993_SAMPLE_RATE_SHIFT);
1355
1356 /* BCLK_DIV */
1357 best = 0;
1358 best_val = INT_MAX;
1359 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1360 cur_val = ((wm8993->sysclk_rate * 10) / bclk_divs[i].div)
1361 - wm8993->bclk;
1362 if (cur_val < 0) /* Table is sorted */
1363 break;
1364 if (cur_val < best_val) {
1365 best = i;
1366 best_val = cur_val;
1367 }
1368 }
1369 wm8993->bclk = (wm8993->sysclk_rate * 10) / bclk_divs[best].div;
1370 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1371 bclk_divs[best].div, wm8993->bclk);
1372 clocking1 |= bclk_divs[best].bclk_div << WM8993_BCLK_DIV_SHIFT;
1373
1374 /* LRCLK is a simple fraction of BCLK */
1375 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8993->bclk / wm8993->fs);
1376 aif4 |= wm8993->bclk / wm8993->fs;
1377
1378 snd_soc_write(codec, WM8993_CLOCKING_1, clocking1);
1379 snd_soc_write(codec, WM8993_CLOCKING_3, clocking3);
1380 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_1, aif1);
1381 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_4, aif4);
1382
1383 /* ReTune Mobile? */
1384 if (wm8993->pdata.num_retune_configs) {
1385 u16 eq1 = snd_soc_read(codec, WM8993_EQ1);
1386 struct wm8993_retune_mobile_setting *s;
1387
1388 best = 0;
1389 best_val = abs(wm8993->pdata.retune_configs[0].rate
1390 - wm8993->fs);
1391 for (i = 0; i < wm8993->pdata.num_retune_configs; i++) {
1392 cur_val = abs(wm8993->pdata.retune_configs[i].rate
1393 - wm8993->fs);
1394 if (cur_val < best_val) {
1395 best_val = cur_val;
1396 best = i;
1397 }
1398 }
1399 s = &wm8993->pdata.retune_configs[best];
1400
1401 dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
1402 s->name, s->rate);
1403
1404 /* Disable EQ while we reconfigure */
1405 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, 0);
1406
1407 for (i = 1; i < ARRAY_SIZE(s->config); i++)
1408 snd_soc_write(codec, WM8993_EQ1 + i, s->config[i]);
1409
1410 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, eq1);
1411 }
1412
1413 return 0;
1414 }
1415
1416 static int wm8993_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1417 {
1418 struct snd_soc_codec *codec = codec_dai->codec;
1419 unsigned int reg;
1420
1421 reg = snd_soc_read(codec, WM8993_DAC_CTRL);
1422
1423 if (mute)
1424 reg |= WM8993_DAC_MUTE;
1425 else
1426 reg &= ~WM8993_DAC_MUTE;
1427
1428 snd_soc_write(codec, WM8993_DAC_CTRL, reg);
1429
1430 return 0;
1431 }
1432
1433 static int wm8993_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1434 unsigned int rx_mask, int slots, int slot_width)
1435 {
1436 struct snd_soc_codec *codec = dai->codec;
1437 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1438 int aif1 = 0;
1439 int aif2 = 0;
1440
1441 /* Don't need to validate anything if we're turning off TDM */
1442 if (slots == 0) {
1443 wm8993->tdm_slots = 0;
1444 goto out;
1445 }
1446
1447 /* Note that we allow configurations we can't handle ourselves -
1448 * for example, we can generate clocks for slots 2 and up even if
1449 * we can't use those slots ourselves.
1450 */
1451 aif1 |= WM8993_AIFADC_TDM;
1452 aif2 |= WM8993_AIFDAC_TDM;
1453
1454 switch (rx_mask) {
1455 case 3:
1456 break;
1457 case 0xc:
1458 aif1 |= WM8993_AIFADC_TDM_CHAN;
1459 break;
1460 default:
1461 return -EINVAL;
1462 }
1463
1464
1465 switch (tx_mask) {
1466 case 3:
1467 break;
1468 case 0xc:
1469 aif2 |= WM8993_AIFDAC_TDM_CHAN;
1470 break;
1471 default:
1472 return -EINVAL;
1473 }
1474
1475 out:
1476 wm8993->tdm_width = slot_width;
1477 wm8993->tdm_slots = slots / 2;
1478
1479 snd_soc_update_bits(codec, WM8993_AUDIO_INTERFACE_1,
1480 WM8993_AIFADC_TDM | WM8993_AIFADC_TDM_CHAN, aif1);
1481 snd_soc_update_bits(codec, WM8993_AUDIO_INTERFACE_2,
1482 WM8993_AIFDAC_TDM | WM8993_AIFDAC_TDM_CHAN, aif2);
1483
1484 return 0;
1485 }
1486
1487 static irqreturn_t wm8993_irq(int irq, void *data)
1488 {
1489 struct wm8993_priv *wm8993 = data;
1490 int mask, val, ret;
1491
1492 ret = regmap_read(wm8993->regmap, WM8993_GPIO_CTRL_1, &val);
1493 if (ret != 0) {
1494 dev_err(wm8993->dev, "Failed to read interrupt status: %d\n",
1495 ret);
1496 return IRQ_NONE;
1497 }
1498
1499 ret = regmap_read(wm8993->regmap, WM8993_GPIOCTRL_2, &mask);
1500 if (ret != 0) {
1501 dev_err(wm8993->dev, "Failed to read interrupt mask: %d\n",
1502 ret);
1503 return IRQ_NONE;
1504 }
1505
1506 /* The IRQ pin status is visible in the register too */
1507 val &= ~(mask | WM8993_IRQ);
1508 if (!val)
1509 return IRQ_NONE;
1510
1511 if (val & WM8993_TEMPOK_EINT)
1512 dev_crit(wm8993->dev, "Thermal warning\n");
1513
1514 if (val & WM8993_FLL_LOCK_EINT) {
1515 dev_dbg(wm8993->dev, "FLL locked\n");
1516 complete(&wm8993->fll_lock);
1517 }
1518
1519 ret = regmap_write(wm8993->regmap, WM8993_GPIO_CTRL_1, val);
1520 if (ret != 0)
1521 dev_err(wm8993->dev, "Failed to ack interrupt: %d\n", ret);
1522
1523 return IRQ_HANDLED;
1524 }
1525
1526 static const struct snd_soc_dai_ops wm8993_ops = {
1527 .set_sysclk = wm8993_set_sysclk,
1528 .set_fmt = wm8993_set_dai_fmt,
1529 .hw_params = wm8993_hw_params,
1530 .digital_mute = wm8993_digital_mute,
1531 .set_pll = wm8993_set_fll,
1532 .set_tdm_slot = wm8993_set_tdm_slot,
1533 };
1534
1535 #define WM8993_RATES SNDRV_PCM_RATE_8000_48000
1536
1537 #define WM8993_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1538 SNDRV_PCM_FMTBIT_S20_3LE |\
1539 SNDRV_PCM_FMTBIT_S24_LE |\
1540 SNDRV_PCM_FMTBIT_S32_LE)
1541
1542 static struct snd_soc_dai_driver wm8993_dai = {
1543 .name = "wm8993-hifi",
1544 .playback = {
1545 .stream_name = "Playback",
1546 .channels_min = 1,
1547 .channels_max = 2,
1548 .rates = WM8993_RATES,
1549 .formats = WM8993_FORMATS,
1550 .sig_bits = 24,
1551 },
1552 .capture = {
1553 .stream_name = "Capture",
1554 .channels_min = 1,
1555 .channels_max = 2,
1556 .rates = WM8993_RATES,
1557 .formats = WM8993_FORMATS,
1558 .sig_bits = 24,
1559 },
1560 .ops = &wm8993_ops,
1561 .symmetric_rates = 1,
1562 };
1563
1564 static int wm8993_probe(struct snd_soc_codec *codec)
1565 {
1566 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1567 struct snd_soc_dapm_context *dapm = &codec->dapm;
1568 int ret;
1569
1570 wm8993->hubs_data.hp_startup_mode = 1;
1571 wm8993->hubs_data.dcs_codes_l = -2;
1572 wm8993->hubs_data.dcs_codes_r = -2;
1573 wm8993->hubs_data.series_startup = 1;
1574
1575 codec->control_data = wm8993->regmap;
1576 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP);
1577 if (ret != 0) {
1578 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1579 return ret;
1580 }
1581
1582 /* By default we're using the output mixers */
1583 wm8993->class_w_users = 2;
1584
1585 /* Latch volume update bits and default ZC on */
1586 snd_soc_update_bits(codec, WM8993_RIGHT_DAC_DIGITAL_VOLUME,
1587 WM8993_DAC_VU, WM8993_DAC_VU);
1588 snd_soc_update_bits(codec, WM8993_RIGHT_ADC_DIGITAL_VOLUME,
1589 WM8993_ADC_VU, WM8993_ADC_VU);
1590
1591 /* Manualy manage the HPOUT sequencing for independent stereo
1592 * control. */
1593 snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0,
1594 WM8993_HPOUT1_AUTO_PU, 0);
1595
1596 /* Use automatic clock configuration */
1597 snd_soc_update_bits(codec, WM8993_CLOCKING_4, WM8993_SR_MODE, 0);
1598
1599 wm_hubs_handle_analogue_pdata(codec, wm8993->pdata.lineout1_diff,
1600 wm8993->pdata.lineout2_diff,
1601 wm8993->pdata.lineout1fb,
1602 wm8993->pdata.lineout2fb,
1603 wm8993->pdata.jd_scthr,
1604 wm8993->pdata.jd_thr,
1605 wm8993->pdata.micbias1_lvl,
1606 wm8993->pdata.micbias2_lvl);
1607
1608 ret = wm8993_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1609 if (ret != 0)
1610 return ret;
1611
1612 snd_soc_add_codec_controls(codec, wm8993_snd_controls,
1613 ARRAY_SIZE(wm8993_snd_controls));
1614 if (wm8993->pdata.num_retune_configs != 0) {
1615 dev_dbg(codec->dev, "Using ReTune Mobile\n");
1616 } else {
1617 dev_dbg(codec->dev, "No ReTune Mobile, using normal EQ\n");
1618 snd_soc_add_codec_controls(codec, wm8993_eq_controls,
1619 ARRAY_SIZE(wm8993_eq_controls));
1620 }
1621
1622 snd_soc_dapm_new_controls(dapm, wm8993_dapm_widgets,
1623 ARRAY_SIZE(wm8993_dapm_widgets));
1624 wm_hubs_add_analogue_controls(codec);
1625
1626 snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes));
1627 wm_hubs_add_analogue_routes(codec, wm8993->pdata.lineout1_diff,
1628 wm8993->pdata.lineout2_diff);
1629
1630 /* If the line outputs are differential then we aren't presenting
1631 * VMID as an output and can disable it.
1632 */
1633 if (wm8993->pdata.lineout1_diff && wm8993->pdata.lineout2_diff)
1634 codec->dapm.idle_bias_off = 1;
1635
1636 return 0;
1637
1638 }
1639
1640 static int wm8993_remove(struct snd_soc_codec *codec)
1641 {
1642 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1643
1644 wm8993_set_bias_level(codec, SND_SOC_BIAS_OFF);
1645 regulator_bulk_free(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1646 return 0;
1647 }
1648
1649 #ifdef CONFIG_PM
1650 static int wm8993_suspend(struct snd_soc_codec *codec)
1651 {
1652 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1653 int fll_fout = wm8993->fll_fout;
1654 int fll_fref = wm8993->fll_fref;
1655 int ret;
1656
1657 /* Stop the FLL in an orderly fashion */
1658 ret = _wm8993_set_fll(codec, 0, 0, 0, 0);
1659 if (ret != 0) {
1660 dev_err(codec->dev, "Failed to stop FLL\n");
1661 return ret;
1662 }
1663
1664 wm8993->fll_fout = fll_fout;
1665 wm8993->fll_fref = fll_fref;
1666
1667 wm8993_set_bias_level(codec, SND_SOC_BIAS_OFF);
1668
1669 return 0;
1670 }
1671
1672 static int wm8993_resume(struct snd_soc_codec *codec)
1673 {
1674 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1675 int ret;
1676
1677 wm8993_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1678
1679 /* Restart the FLL? */
1680 if (wm8993->fll_fout) {
1681 int fll_fout = wm8993->fll_fout;
1682 int fll_fref = wm8993->fll_fref;
1683
1684 wm8993->fll_fref = 0;
1685 wm8993->fll_fout = 0;
1686
1687 ret = _wm8993_set_fll(codec, 0, wm8993->fll_src,
1688 fll_fref, fll_fout);
1689 if (ret != 0)
1690 dev_err(codec->dev, "Failed to restart FLL\n");
1691 }
1692
1693 return 0;
1694 }
1695 #else
1696 #define wm8993_suspend NULL
1697 #define wm8993_resume NULL
1698 #endif
1699
1700 /* Tune DC servo configuration */
1701 static struct reg_default wm8993_regmap_patch[] = {
1702 { 0x44, 3 },
1703 { 0x56, 3 },
1704 { 0x44, 0 },
1705 };
1706
1707 static const struct regmap_config wm8993_regmap = {
1708 .reg_bits = 8,
1709 .val_bits = 16,
1710
1711 .max_register = WM8993_MAX_REGISTER,
1712 .volatile_reg = wm8993_volatile,
1713 .readable_reg = wm8993_readable,
1714
1715 .cache_type = REGCACHE_RBTREE,
1716 .reg_defaults = wm8993_reg_defaults,
1717 .num_reg_defaults = ARRAY_SIZE(wm8993_reg_defaults),
1718 };
1719
1720 static struct snd_soc_codec_driver soc_codec_dev_wm8993 = {
1721 .probe = wm8993_probe,
1722 .remove = wm8993_remove,
1723 .suspend = wm8993_suspend,
1724 .resume = wm8993_resume,
1725 .set_bias_level = wm8993_set_bias_level,
1726 };
1727
1728 static __devinit int wm8993_i2c_probe(struct i2c_client *i2c,
1729 const struct i2c_device_id *id)
1730 {
1731 struct wm8993_priv *wm8993;
1732 unsigned int reg;
1733 int ret, i;
1734
1735 wm8993 = devm_kzalloc(&i2c->dev, sizeof(struct wm8993_priv),
1736 GFP_KERNEL);
1737 if (wm8993 == NULL)
1738 return -ENOMEM;
1739
1740 wm8993->dev = &i2c->dev;
1741 init_completion(&wm8993->fll_lock);
1742
1743 wm8993->regmap = regmap_init_i2c(i2c, &wm8993_regmap);
1744 if (IS_ERR(wm8993->regmap)) {
1745 ret = PTR_ERR(wm8993->regmap);
1746 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
1747 return ret;
1748 }
1749
1750 i2c_set_clientdata(i2c, wm8993);
1751
1752 for (i = 0; i < ARRAY_SIZE(wm8993->supplies); i++)
1753 wm8993->supplies[i].supply = wm8993_supply_names[i];
1754
1755 ret = regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8993->supplies),
1756 wm8993->supplies);
1757 if (ret != 0) {
1758 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
1759 goto err;
1760 }
1761
1762 ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies),
1763 wm8993->supplies);
1764 if (ret != 0) {
1765 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
1766 goto err_get;
1767 }
1768
1769 ret = regmap_read(wm8993->regmap, WM8993_SOFTWARE_RESET, &reg);
1770 if (ret != 0) {
1771 dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
1772 goto err_enable;
1773 }
1774
1775 if (reg != 0x8993) {
1776 dev_err(&i2c->dev, "Invalid ID register value %x\n", reg);
1777 ret = -EINVAL;
1778 goto err_enable;
1779 }
1780
1781 ret = regmap_write(wm8993->regmap, WM8993_SOFTWARE_RESET, 0xffff);
1782 if (ret != 0)
1783 goto err_enable;
1784
1785 ret = regmap_register_patch(wm8993->regmap, wm8993_regmap_patch,
1786 ARRAY_SIZE(wm8993_regmap_patch));
1787 if (ret != 0)
1788 dev_warn(wm8993->dev, "Failed to apply regmap patch: %d\n",
1789 ret);
1790
1791 if (i2c->irq) {
1792 /* Put GPIO1 into interrupt mode (only GPIO1 can output IRQ) */
1793 ret = regmap_update_bits(wm8993->regmap, WM8993_GPIO1,
1794 WM8993_GPIO1_PD |
1795 WM8993_GPIO1_SEL_MASK, 7);
1796 if (ret != 0)
1797 goto err_enable;
1798
1799 ret = request_threaded_irq(i2c->irq, NULL, wm8993_irq,
1800 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1801 "wm8993", wm8993);
1802 if (ret != 0)
1803 goto err_enable;
1804
1805 }
1806
1807 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1808
1809 regcache_cache_only(wm8993->regmap, true);
1810
1811 ret = snd_soc_register_codec(&i2c->dev,
1812 &soc_codec_dev_wm8993, &wm8993_dai, 1);
1813 if (ret != 0) {
1814 dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
1815 goto err_irq;
1816 }
1817
1818 return 0;
1819
1820 err_irq:
1821 if (i2c->irq)
1822 free_irq(i2c->irq, wm8993);
1823 err_enable:
1824 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1825 err_get:
1826 regulator_bulk_free(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1827 err:
1828 regmap_exit(wm8993->regmap);
1829 return ret;
1830 }
1831
1832 static __devexit int wm8993_i2c_remove(struct i2c_client *i2c)
1833 {
1834 struct wm8993_priv *wm8993 = i2c_get_clientdata(i2c);
1835
1836 snd_soc_unregister_codec(&i2c->dev);
1837 if (i2c->irq)
1838 free_irq(i2c->irq, wm8993);
1839 regmap_exit(wm8993->regmap);
1840 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1841 regulator_bulk_free(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1842
1843 return 0;
1844 }
1845
1846 static const struct i2c_device_id wm8993_i2c_id[] = {
1847 { "wm8993", 0 },
1848 { }
1849 };
1850 MODULE_DEVICE_TABLE(i2c, wm8993_i2c_id);
1851
1852 static struct i2c_driver wm8993_i2c_driver = {
1853 .driver = {
1854 .name = "wm8993",
1855 .owner = THIS_MODULE,
1856 },
1857 .probe = wm8993_i2c_probe,
1858 .remove = __devexit_p(wm8993_i2c_remove),
1859 .id_table = wm8993_i2c_id,
1860 };
1861
1862 module_i2c_driver(wm8993_i2c_driver);
1863
1864 MODULE_DESCRIPTION("ASoC WM8993 driver");
1865 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1866 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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