2 * wm8994.c -- WM8994 ALSA SoC Audio driver
4 * Copyright 2009 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/jack.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <trace/events/asoc.h>
33 #include <linux/mfd/wm8994/core.h>
34 #include <linux/mfd/wm8994/registers.h>
35 #include <linux/mfd/wm8994/pdata.h>
36 #include <linux/mfd/wm8994/gpio.h>
41 #define WM1811_JACKDET_MODE_NONE 0x0000
42 #define WM1811_JACKDET_MODE_JACK 0x0100
43 #define WM1811_JACKDET_MODE_MIC 0x0080
44 #define WM1811_JACKDET_MODE_AUDIO 0x0180
46 #define WM8994_NUM_DRC 3
47 #define WM8994_NUM_EQ 3
49 static int wm8994_drc_base
[] = {
55 static int wm8994_retune_mobile_base
[] = {
56 WM8994_AIF1_DAC1_EQ_GAINS_1
,
57 WM8994_AIF1_DAC2_EQ_GAINS_1
,
58 WM8994_AIF2_EQ_GAINS_1
,
61 static void wm8958_default_micdet(u16 status
, void *data
);
63 static const struct wm8958_micd_rate micdet_rates
[] = {
64 { 32768, true, 1, 4 },
65 { 32768, false, 1, 1 },
66 { 44100 * 256, true, 7, 10 },
67 { 44100 * 256, false, 7, 10 },
70 static const struct wm8958_micd_rate jackdet_rates
[] = {
71 { 32768, true, 0, 1 },
72 { 32768, false, 0, 1 },
73 { 44100 * 256, true, 7, 10 },
74 { 44100 * 256, false, 7, 10 },
77 static void wm8958_micd_set_rate(struct snd_soc_codec
*codec
)
79 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
80 int best
, i
, sysclk
, val
;
82 const struct wm8958_micd_rate
*rates
;
85 if (wm8994
->jack_cb
!= wm8958_default_micdet
)
88 idle
= !wm8994
->jack_mic
;
90 sysclk
= snd_soc_read(codec
, WM8994_CLOCKING_1
);
91 if (sysclk
& WM8994_SYSCLK_SRC
)
92 sysclk
= wm8994
->aifclk
[1];
94 sysclk
= wm8994
->aifclk
[0];
96 if (wm8994
->pdata
&& wm8994
->pdata
->micd_rates
) {
97 rates
= wm8994
->pdata
->micd_rates
;
98 num_rates
= wm8994
->pdata
->num_micd_rates
;
99 } else if (wm8994
->jackdet
) {
100 rates
= jackdet_rates
;
101 num_rates
= ARRAY_SIZE(jackdet_rates
);
103 rates
= micdet_rates
;
104 num_rates
= ARRAY_SIZE(micdet_rates
);
108 for (i
= 0; i
< num_rates
; i
++) {
109 if (rates
[i
].idle
!= idle
)
111 if (abs(rates
[i
].sysclk
- sysclk
) <
112 abs(rates
[best
].sysclk
- sysclk
))
114 else if (rates
[best
].idle
!= idle
)
118 val
= rates
[best
].start
<< WM8958_MICD_BIAS_STARTTIME_SHIFT
119 | rates
[best
].rate
<< WM8958_MICD_RATE_SHIFT
;
121 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
122 WM8958_MICD_BIAS_STARTTIME_MASK
|
123 WM8958_MICD_RATE_MASK
, val
);
126 static int wm8994_readable(struct snd_soc_codec
*codec
, unsigned int reg
)
128 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
129 struct wm8994
*control
= wm8994
->wm8994
;
143 case WM8994_INTERRUPT_STATUS_1
:
144 case WM8994_INTERRUPT_STATUS_2
:
145 case WM8994_INTERRUPT_RAW_STATUS_2
:
148 case WM8958_DSP2_PROGRAM
:
149 case WM8958_DSP2_CONFIG
:
150 case WM8958_DSP2_EXECCONTROL
:
151 if (control
->type
== WM8958
)
160 if (reg
>= WM8994_CACHE_SIZE
)
162 return wm8994_access_masks
[reg
].readable
!= 0;
165 static int wm8994_volatile(struct snd_soc_codec
*codec
, unsigned int reg
)
167 if (reg
>= WM8994_CACHE_SIZE
)
171 case WM8994_SOFTWARE_RESET
:
172 case WM8994_CHIP_REVISION
:
173 case WM8994_DC_SERVO_1
:
174 case WM8994_DC_SERVO_READBACK
:
175 case WM8994_RATE_STATUS
:
178 case WM8958_DSP2_EXECCONTROL
:
179 case WM8958_MIC_DETECT_3
:
180 case WM8994_DC_SERVO_4E
:
187 static int wm8994_write(struct snd_soc_codec
*codec
, unsigned int reg
,
192 BUG_ON(reg
> WM8994_MAX_REGISTER
);
194 if (!wm8994_volatile(codec
, reg
)) {
195 ret
= snd_soc_cache_write(codec
, reg
, value
);
197 dev_err(codec
->dev
, "Cache write to %x failed: %d\n",
201 return wm8994_reg_write(codec
->control_data
, reg
, value
);
204 static unsigned int wm8994_read(struct snd_soc_codec
*codec
,
210 BUG_ON(reg
> WM8994_MAX_REGISTER
);
212 if (!wm8994_volatile(codec
, reg
) && wm8994_readable(codec
, reg
) &&
213 reg
< codec
->driver
->reg_cache_size
) {
214 ret
= snd_soc_cache_read(codec
, reg
, &val
);
218 dev_err(codec
->dev
, "Cache read from %x failed: %d\n",
222 return wm8994_reg_read(codec
->control_data
, reg
);
225 static int configure_aif_clock(struct snd_soc_codec
*codec
, int aif
)
227 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
237 switch (wm8994
->sysclk
[aif
]) {
238 case WM8994_SYSCLK_MCLK1
:
239 rate
= wm8994
->mclk
[0];
242 case WM8994_SYSCLK_MCLK2
:
244 rate
= wm8994
->mclk
[1];
247 case WM8994_SYSCLK_FLL1
:
249 rate
= wm8994
->fll
[0].out
;
252 case WM8994_SYSCLK_FLL2
:
254 rate
= wm8994
->fll
[1].out
;
261 if (rate
>= 13500000) {
263 reg1
|= WM8994_AIF1CLK_DIV
;
265 dev_dbg(codec
->dev
, "Dividing AIF%d clock to %dHz\n",
269 wm8994
->aifclk
[aif
] = rate
;
271 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
+ offset
,
272 WM8994_AIF1CLK_SRC_MASK
| WM8994_AIF1CLK_DIV
,
278 static int configure_clock(struct snd_soc_codec
*codec
)
280 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
283 /* Bring up the AIF clocks first */
284 configure_aif_clock(codec
, 0);
285 configure_aif_clock(codec
, 1);
287 /* Then switch CLK_SYS over to the higher of them; a change
288 * can only happen as a result of a clocking change which can
289 * only be made outside of DAPM so we can safely redo the
293 /* If they're equal it doesn't matter which is used */
294 if (wm8994
->aifclk
[0] == wm8994
->aifclk
[1]) {
295 wm8958_micd_set_rate(codec
);
299 if (wm8994
->aifclk
[0] < wm8994
->aifclk
[1])
300 new = WM8994_SYSCLK_SRC
;
304 change
= snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
305 WM8994_SYSCLK_SRC
, new);
307 snd_soc_dapm_sync(&codec
->dapm
);
309 wm8958_micd_set_rate(codec
);
314 static int check_clk_sys(struct snd_soc_dapm_widget
*source
,
315 struct snd_soc_dapm_widget
*sink
)
317 int reg
= snd_soc_read(source
->codec
, WM8994_CLOCKING_1
);
320 /* Check what we're currently using for CLK_SYS */
321 if (reg
& WM8994_SYSCLK_SRC
)
326 return strcmp(source
->name
, clk
) == 0;
329 static const char *sidetone_hpf_text
[] = {
330 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
333 static const struct soc_enum sidetone_hpf
=
334 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 7, 7, sidetone_hpf_text
);
336 static const char *adc_hpf_text
[] = {
337 "HiFi", "Voice 1", "Voice 2", "Voice 3"
340 static const struct soc_enum aif1adc1_hpf
=
341 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS
, 13, 4, adc_hpf_text
);
343 static const struct soc_enum aif1adc2_hpf
=
344 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS
, 13, 4, adc_hpf_text
);
346 static const struct soc_enum aif2adc_hpf
=
347 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS
, 13, 4, adc_hpf_text
);
349 static const DECLARE_TLV_DB_SCALE(aif_tlv
, 0, 600, 0);
350 static const DECLARE_TLV_DB_SCALE(digital_tlv
, -7200, 75, 1);
351 static const DECLARE_TLV_DB_SCALE(st_tlv
, -3600, 300, 0);
352 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv
, -1600, 183, 0);
353 static const DECLARE_TLV_DB_SCALE(eq_tlv
, -1200, 100, 0);
354 static const DECLARE_TLV_DB_SCALE(ng_tlv
, -10200, 600, 0);
355 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv
, 0, 900, 0);
357 #define WM8994_DRC_SWITCH(xname, reg, shift) \
358 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
359 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
360 .put = wm8994_put_drc_sw, \
361 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
363 static int wm8994_put_drc_sw(struct snd_kcontrol
*kcontrol
,
364 struct snd_ctl_elem_value
*ucontrol
)
366 struct soc_mixer_control
*mc
=
367 (struct soc_mixer_control
*)kcontrol
->private_value
;
368 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
371 /* Can't enable both ADC and DAC paths simultaneously */
372 if (mc
->shift
== WM8994_AIF1DAC1_DRC_ENA_SHIFT
)
373 mask
= WM8994_AIF1ADC1L_DRC_ENA_MASK
|
374 WM8994_AIF1ADC1R_DRC_ENA_MASK
;
376 mask
= WM8994_AIF1DAC1_DRC_ENA_MASK
;
378 ret
= snd_soc_read(codec
, mc
->reg
);
384 return snd_soc_put_volsw(kcontrol
, ucontrol
);
387 static void wm8994_set_drc(struct snd_soc_codec
*codec
, int drc
)
389 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
390 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
391 int base
= wm8994_drc_base
[drc
];
392 int cfg
= wm8994
->drc_cfg
[drc
];
395 /* Save any enables; the configuration should clear them. */
396 save
= snd_soc_read(codec
, base
);
397 save
&= WM8994_AIF1DAC1_DRC_ENA
| WM8994_AIF1ADC1L_DRC_ENA
|
398 WM8994_AIF1ADC1R_DRC_ENA
;
400 for (i
= 0; i
< WM8994_DRC_REGS
; i
++)
401 snd_soc_update_bits(codec
, base
+ i
, 0xffff,
402 pdata
->drc_cfgs
[cfg
].regs
[i
]);
404 snd_soc_update_bits(codec
, base
, WM8994_AIF1DAC1_DRC_ENA
|
405 WM8994_AIF1ADC1L_DRC_ENA
|
406 WM8994_AIF1ADC1R_DRC_ENA
, save
);
409 /* Icky as hell but saves code duplication */
410 static int wm8994_get_drc(const char *name
)
412 if (strcmp(name
, "AIF1DRC1 Mode") == 0)
414 if (strcmp(name
, "AIF1DRC2 Mode") == 0)
416 if (strcmp(name
, "AIF2DRC Mode") == 0)
421 static int wm8994_put_drc_enum(struct snd_kcontrol
*kcontrol
,
422 struct snd_ctl_elem_value
*ucontrol
)
424 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
425 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
426 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
427 int drc
= wm8994_get_drc(kcontrol
->id
.name
);
428 int value
= ucontrol
->value
.integer
.value
[0];
433 if (value
>= pdata
->num_drc_cfgs
)
436 wm8994
->drc_cfg
[drc
] = value
;
438 wm8994_set_drc(codec
, drc
);
443 static int wm8994_get_drc_enum(struct snd_kcontrol
*kcontrol
,
444 struct snd_ctl_elem_value
*ucontrol
)
446 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
447 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
448 int drc
= wm8994_get_drc(kcontrol
->id
.name
);
450 ucontrol
->value
.enumerated
.item
[0] = wm8994
->drc_cfg
[drc
];
455 static void wm8994_set_retune_mobile(struct snd_soc_codec
*codec
, int block
)
457 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
458 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
459 int base
= wm8994_retune_mobile_base
[block
];
460 int iface
, best
, best_val
, save
, i
, cfg
;
462 if (!pdata
|| !wm8994
->num_retune_mobile_texts
)
477 /* Find the version of the currently selected configuration
478 * with the nearest sample rate. */
479 cfg
= wm8994
->retune_mobile_cfg
[block
];
482 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
483 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
484 wm8994
->retune_mobile_texts
[cfg
]) == 0 &&
485 abs(pdata
->retune_mobile_cfgs
[i
].rate
486 - wm8994
->dac_rates
[iface
]) < best_val
) {
488 best_val
= abs(pdata
->retune_mobile_cfgs
[i
].rate
489 - wm8994
->dac_rates
[iface
]);
493 dev_dbg(codec
->dev
, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
495 pdata
->retune_mobile_cfgs
[best
].name
,
496 pdata
->retune_mobile_cfgs
[best
].rate
,
497 wm8994
->dac_rates
[iface
]);
499 /* The EQ will be disabled while reconfiguring it, remember the
500 * current configuration.
502 save
= snd_soc_read(codec
, base
);
503 save
&= WM8994_AIF1DAC1_EQ_ENA
;
505 for (i
= 0; i
< WM8994_EQ_REGS
; i
++)
506 snd_soc_update_bits(codec
, base
+ i
, 0xffff,
507 pdata
->retune_mobile_cfgs
[best
].regs
[i
]);
509 snd_soc_update_bits(codec
, base
, WM8994_AIF1DAC1_EQ_ENA
, save
);
512 /* Icky as hell but saves code duplication */
513 static int wm8994_get_retune_mobile_block(const char *name
)
515 if (strcmp(name
, "AIF1.1 EQ Mode") == 0)
517 if (strcmp(name
, "AIF1.2 EQ Mode") == 0)
519 if (strcmp(name
, "AIF2 EQ Mode") == 0)
524 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
525 struct snd_ctl_elem_value
*ucontrol
)
527 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
528 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
529 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
530 int block
= wm8994_get_retune_mobile_block(kcontrol
->id
.name
);
531 int value
= ucontrol
->value
.integer
.value
[0];
536 if (value
>= pdata
->num_retune_mobile_cfgs
)
539 wm8994
->retune_mobile_cfg
[block
] = value
;
541 wm8994_set_retune_mobile(codec
, block
);
546 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
547 struct snd_ctl_elem_value
*ucontrol
)
549 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
550 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
551 int block
= wm8994_get_retune_mobile_block(kcontrol
->id
.name
);
553 ucontrol
->value
.enumerated
.item
[0] = wm8994
->retune_mobile_cfg
[block
];
558 static const char *aif_chan_src_text
[] = {
562 static const struct soc_enum aif1adcl_src
=
563 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1
, 15, 2, aif_chan_src_text
);
565 static const struct soc_enum aif1adcr_src
=
566 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1
, 14, 2, aif_chan_src_text
);
568 static const struct soc_enum aif2adcl_src
=
569 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1
, 15, 2, aif_chan_src_text
);
571 static const struct soc_enum aif2adcr_src
=
572 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1
, 14, 2, aif_chan_src_text
);
574 static const struct soc_enum aif1dacl_src
=
575 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2
, 15, 2, aif_chan_src_text
);
577 static const struct soc_enum aif1dacr_src
=
578 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2
, 14, 2, aif_chan_src_text
);
580 static const struct soc_enum aif2dacl_src
=
581 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2
, 15, 2, aif_chan_src_text
);
583 static const struct soc_enum aif2dacr_src
=
584 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2
, 14, 2, aif_chan_src_text
);
586 static const char *osr_text
[] = {
587 "Low Power", "High Performance",
590 static const struct soc_enum dac_osr
=
591 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING
, 0, 2, osr_text
);
593 static const struct soc_enum adc_osr
=
594 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING
, 1, 2, osr_text
);
596 static const struct snd_kcontrol_new wm8994_snd_controls
[] = {
597 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME
,
598 WM8994_AIF1_ADC1_RIGHT_VOLUME
,
599 1, 119, 0, digital_tlv
),
600 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME
,
601 WM8994_AIF1_ADC2_RIGHT_VOLUME
,
602 1, 119, 0, digital_tlv
),
603 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME
,
604 WM8994_AIF2_ADC_RIGHT_VOLUME
,
605 1, 119, 0, digital_tlv
),
607 SOC_ENUM("AIF1ADCL Source", aif1adcl_src
),
608 SOC_ENUM("AIF1ADCR Source", aif1adcr_src
),
609 SOC_ENUM("AIF2ADCL Source", aif2adcl_src
),
610 SOC_ENUM("AIF2ADCR Source", aif2adcr_src
),
612 SOC_ENUM("AIF1DACL Source", aif1dacl_src
),
613 SOC_ENUM("AIF1DACR Source", aif1dacr_src
),
614 SOC_ENUM("AIF2DACL Source", aif2dacl_src
),
615 SOC_ENUM("AIF2DACR Source", aif2dacr_src
),
617 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME
,
618 WM8994_AIF1_DAC1_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
619 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME
,
620 WM8994_AIF1_DAC2_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
621 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME
,
622 WM8994_AIF2_DAC_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
624 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2
, 10, 3, 0, aif_tlv
),
625 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2
, 10, 3, 0, aif_tlv
),
627 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1
, 0, 1, 0),
628 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1
, 0, 1, 0),
629 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1
, 0, 1, 0),
631 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1
, 2),
632 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1
, 1),
633 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1
, 0),
635 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1
, 2),
636 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1
, 1),
637 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1
, 0),
639 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1
, 2),
640 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1
, 1),
641 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1
, 0),
643 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES
,
645 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES
,
647 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES
,
649 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES
,
651 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf
),
652 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE
, 6, 1, 0),
654 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf
),
655 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS
, 12, 11, 1, 0),
657 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf
),
658 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS
, 12, 11, 1, 0),
660 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf
),
661 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS
, 12, 11, 1, 0),
663 SOC_ENUM("ADC OSR", adc_osr
),
664 SOC_ENUM("DAC OSR", dac_osr
),
666 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME
,
667 WM8994_DAC1_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
668 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME
,
669 WM8994_DAC1_RIGHT_VOLUME
, 9, 1, 1),
671 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME
,
672 WM8994_DAC2_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
673 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME
,
674 WM8994_DAC2_RIGHT_VOLUME
, 9, 1, 1),
676 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION
,
677 6, 1, 1, wm_hubs_spkmix_tlv
),
678 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION
,
679 2, 1, 1, wm_hubs_spkmix_tlv
),
681 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION
,
682 6, 1, 1, wm_hubs_spkmix_tlv
),
683 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION
,
684 2, 1, 1, wm_hubs_spkmix_tlv
),
686 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2
,
687 10, 15, 0, wm8994_3d_tlv
),
688 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2
,
690 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2
,
691 10, 15, 0, wm8994_3d_tlv
),
692 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2
,
694 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2
,
695 10, 15, 0, wm8994_3d_tlv
),
696 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2
,
700 static const struct snd_kcontrol_new wm8994_eq_controls
[] = {
701 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 11, 31, 0,
703 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 6, 31, 0,
705 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 1, 31, 0,
707 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2
, 11, 31, 0,
709 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2
, 6, 31, 0,
712 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 11, 31, 0,
714 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 6, 31, 0,
716 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 1, 31, 0,
718 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2
, 11, 31, 0,
720 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2
, 6, 31, 0,
723 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1
, 11, 31, 0,
725 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1
, 6, 31, 0,
727 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1
, 1, 31, 0,
729 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2
, 11, 31, 0,
731 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2
, 6, 31, 0,
735 static const char *wm8958_ng_text
[] = {
736 "30ms", "125ms", "250ms", "500ms",
739 static const struct soc_enum wm8958_aif1dac1_ng_hold
=
740 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE
,
741 WM8958_AIF1DAC1_NG_THR_SHIFT
, 4, wm8958_ng_text
);
743 static const struct soc_enum wm8958_aif1dac2_ng_hold
=
744 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE
,
745 WM8958_AIF1DAC2_NG_THR_SHIFT
, 4, wm8958_ng_text
);
747 static const struct soc_enum wm8958_aif2dac_ng_hold
=
748 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE
,
749 WM8958_AIF2DAC_NG_THR_SHIFT
, 4, wm8958_ng_text
);
751 static const struct snd_kcontrol_new wm8958_snd_controls
[] = {
752 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2
, 10, 3, 0, aif_tlv
),
754 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE
,
755 WM8958_AIF1DAC1_NG_ENA_SHIFT
, 1, 0),
756 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold
),
757 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
758 WM8958_AIF1_DAC1_NOISE_GATE
, WM8958_AIF1DAC1_NG_THR_SHIFT
,
761 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE
,
762 WM8958_AIF1DAC2_NG_ENA_SHIFT
, 1, 0),
763 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold
),
764 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
765 WM8958_AIF1_DAC2_NOISE_GATE
, WM8958_AIF1DAC2_NG_THR_SHIFT
,
768 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE
,
769 WM8958_AIF2DAC_NG_ENA_SHIFT
, 1, 0),
770 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold
),
771 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
772 WM8958_AIF2_DAC_NOISE_GATE
, WM8958_AIF2DAC_NG_THR_SHIFT
,
776 static const struct snd_kcontrol_new wm1811_snd_controls
[] = {
777 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1
, 7, 1, 0,
779 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1
, 8, 1, 0,
783 /* We run all mode setting through a function to enforce audio mode */
784 static void wm1811_jackdet_set_mode(struct snd_soc_codec
*codec
, u16 mode
)
786 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
788 if (wm8994
->active_refcount
)
789 mode
= WM1811_JACKDET_MODE_AUDIO
;
791 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
792 WM1811_JACKDET_MODE_MASK
, mode
);
794 if (mode
== WM1811_JACKDET_MODE_MIC
)
798 static void active_reference(struct snd_soc_codec
*codec
)
800 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
802 mutex_lock(&wm8994
->accdet_lock
);
804 wm8994
->active_refcount
++;
806 dev_dbg(codec
->dev
, "Active refcount incremented, now %d\n",
807 wm8994
->active_refcount
);
809 if (wm8994
->active_refcount
== 1) {
810 /* If we're using jack detection go into audio mode */
811 if (wm8994
->jackdet
&& wm8994
->jack_cb
) {
812 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
813 WM1811_JACKDET_MODE_MASK
,
814 WM1811_JACKDET_MODE_AUDIO
);
819 mutex_unlock(&wm8994
->accdet_lock
);
822 static void active_dereference(struct snd_soc_codec
*codec
)
824 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
827 mutex_lock(&wm8994
->accdet_lock
);
829 wm8994
->active_refcount
--;
831 dev_dbg(codec
->dev
, "Active refcount decremented, now %d\n",
832 wm8994
->active_refcount
);
834 if (wm8994
->active_refcount
== 0) {
835 /* Go into appropriate detection only mode */
836 if (wm8994
->jackdet
&& wm8994
->jack_cb
) {
837 if (wm8994
->jack_mic
|| wm8994
->mic_detecting
)
838 mode
= WM1811_JACKDET_MODE_MIC
;
840 mode
= WM1811_JACKDET_MODE_JACK
;
842 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
843 WM1811_JACKDET_MODE_MASK
,
848 mutex_unlock(&wm8994
->accdet_lock
);
851 static int clk_sys_event(struct snd_soc_dapm_widget
*w
,
852 struct snd_kcontrol
*kcontrol
, int event
)
854 struct snd_soc_codec
*codec
= w
->codec
;
857 case SND_SOC_DAPM_PRE_PMU
:
858 return configure_clock(codec
);
860 case SND_SOC_DAPM_POST_PMD
:
861 configure_clock(codec
);
868 static void vmid_reference(struct snd_soc_codec
*codec
)
870 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
872 wm8994
->vmid_refcount
++;
874 dev_dbg(codec
->dev
, "Referencing VMID, refcount is now %d\n",
875 wm8994
->vmid_refcount
);
877 if (wm8994
->vmid_refcount
== 1) {
878 /* Startup bias, VMID ramp & buffer */
879 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
880 WM8994_STARTUP_BIAS_ENA
|
881 WM8994_VMID_BUF_ENA
|
882 WM8994_VMID_RAMP_MASK
,
883 WM8994_STARTUP_BIAS_ENA
|
884 WM8994_VMID_BUF_ENA
|
885 (0x11 << WM8994_VMID_RAMP_SHIFT
));
887 /* Main bias enable, VMID=2x40k */
888 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
890 WM8994_VMID_SEL_MASK
,
891 WM8994_BIAS_ENA
| 0x2);
897 static void vmid_dereference(struct snd_soc_codec
*codec
)
899 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
901 wm8994
->vmid_refcount
--;
903 dev_dbg(codec
->dev
, "Dereferencing VMID, refcount is now %d\n",
904 wm8994
->vmid_refcount
);
906 if (wm8994
->vmid_refcount
== 0) {
907 /* Switch over to startup biases */
908 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
910 WM8994_STARTUP_BIAS_ENA
|
911 WM8994_VMID_BUF_ENA
|
912 WM8994_VMID_RAMP_MASK
,
914 WM8994_STARTUP_BIAS_ENA
|
915 WM8994_VMID_BUF_ENA
|
916 (1 << WM8994_VMID_RAMP_SHIFT
));
918 /* Disable main biases */
919 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
921 WM8994_VMID_SEL_MASK
, 0);
924 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
925 WM8994_LINEOUT1_DISCH
|
926 WM8994_LINEOUT2_DISCH
,
927 WM8994_LINEOUT1_DISCH
|
928 WM8994_LINEOUT2_DISCH
);
932 /* Switch off startup biases */
933 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
935 WM8994_STARTUP_BIAS_ENA
|
936 WM8994_VMID_BUF_ENA
|
937 WM8994_VMID_RAMP_MASK
, 0);
941 static int vmid_event(struct snd_soc_dapm_widget
*w
,
942 struct snd_kcontrol
*kcontrol
, int event
)
944 struct snd_soc_codec
*codec
= w
->codec
;
947 case SND_SOC_DAPM_PRE_PMU
:
948 vmid_reference(codec
);
951 case SND_SOC_DAPM_POST_PMD
:
952 vmid_dereference(codec
);
959 static void wm8994_update_class_w(struct snd_soc_codec
*codec
)
961 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
963 int source
= 0; /* GCC flow analysis can't track enable */
966 /* Only support direct DAC->headphone paths */
967 reg
= snd_soc_read(codec
, WM8994_OUTPUT_MIXER_1
);
968 if (!(reg
& WM8994_DAC1L_TO_HPOUT1L
)) {
969 dev_vdbg(codec
->dev
, "HPL connected to output mixer\n");
973 reg
= snd_soc_read(codec
, WM8994_OUTPUT_MIXER_2
);
974 if (!(reg
& WM8994_DAC1R_TO_HPOUT1R
)) {
975 dev_vdbg(codec
->dev
, "HPR connected to output mixer\n");
979 /* We also need the same setting for L/R and only one path */
980 reg
= snd_soc_read(codec
, WM8994_DAC1_LEFT_MIXER_ROUTING
);
982 case WM8994_AIF2DACL_TO_DAC1L
:
983 dev_vdbg(codec
->dev
, "Class W source AIF2DAC\n");
984 source
= 2 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
986 case WM8994_AIF1DAC2L_TO_DAC1L
:
987 dev_vdbg(codec
->dev
, "Class W source AIF1DAC2\n");
988 source
= 1 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
990 case WM8994_AIF1DAC1L_TO_DAC1L
:
991 dev_vdbg(codec
->dev
, "Class W source AIF1DAC1\n");
992 source
= 0 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
995 dev_vdbg(codec
->dev
, "DAC mixer setting: %x\n", reg
);
1000 reg_r
= snd_soc_read(codec
, WM8994_DAC1_RIGHT_MIXER_ROUTING
);
1002 dev_vdbg(codec
->dev
, "Left and right DAC mixers different\n");
1007 dev_dbg(codec
->dev
, "Class W enabled\n");
1008 snd_soc_update_bits(codec
, WM8994_CLASS_W_1
,
1010 WM8994_CP_DYN_SRC_SEL_MASK
,
1011 source
| WM8994_CP_DYN_PWR
);
1012 wm8994
->hubs
.class_w
= true;
1015 dev_dbg(codec
->dev
, "Class W disabled\n");
1016 snd_soc_update_bits(codec
, WM8994_CLASS_W_1
,
1017 WM8994_CP_DYN_PWR
, 0);
1018 wm8994
->hubs
.class_w
= false;
1022 static int late_enable_ev(struct snd_soc_dapm_widget
*w
,
1023 struct snd_kcontrol
*kcontrol
, int event
)
1025 struct snd_soc_codec
*codec
= w
->codec
;
1026 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1029 case SND_SOC_DAPM_PRE_PMU
:
1030 if (wm8994
->aif1clk_enable
) {
1031 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
1032 WM8994_AIF1CLK_ENA_MASK
,
1033 WM8994_AIF1CLK_ENA
);
1034 wm8994
->aif1clk_enable
= 0;
1036 if (wm8994
->aif2clk_enable
) {
1037 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
1038 WM8994_AIF2CLK_ENA_MASK
,
1039 WM8994_AIF2CLK_ENA
);
1040 wm8994
->aif2clk_enable
= 0;
1045 /* We may also have postponed startup of DSP, handle that. */
1046 wm8958_aif_ev(w
, kcontrol
, event
);
1051 static int late_disable_ev(struct snd_soc_dapm_widget
*w
,
1052 struct snd_kcontrol
*kcontrol
, int event
)
1054 struct snd_soc_codec
*codec
= w
->codec
;
1055 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1058 case SND_SOC_DAPM_POST_PMD
:
1059 if (wm8994
->aif1clk_disable
) {
1060 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
1061 WM8994_AIF1CLK_ENA_MASK
, 0);
1062 wm8994
->aif1clk_disable
= 0;
1064 if (wm8994
->aif2clk_disable
) {
1065 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
1066 WM8994_AIF2CLK_ENA_MASK
, 0);
1067 wm8994
->aif2clk_disable
= 0;
1075 static int aif1clk_ev(struct snd_soc_dapm_widget
*w
,
1076 struct snd_kcontrol
*kcontrol
, int event
)
1078 struct snd_soc_codec
*codec
= w
->codec
;
1079 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1082 case SND_SOC_DAPM_PRE_PMU
:
1083 wm8994
->aif1clk_enable
= 1;
1085 case SND_SOC_DAPM_POST_PMD
:
1086 wm8994
->aif1clk_disable
= 1;
1093 static int aif2clk_ev(struct snd_soc_dapm_widget
*w
,
1094 struct snd_kcontrol
*kcontrol
, int event
)
1096 struct snd_soc_codec
*codec
= w
->codec
;
1097 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1100 case SND_SOC_DAPM_PRE_PMU
:
1101 wm8994
->aif2clk_enable
= 1;
1103 case SND_SOC_DAPM_POST_PMD
:
1104 wm8994
->aif2clk_disable
= 1;
1111 static int adc_mux_ev(struct snd_soc_dapm_widget
*w
,
1112 struct snd_kcontrol
*kcontrol
, int event
)
1114 late_enable_ev(w
, kcontrol
, event
);
1118 static int micbias_ev(struct snd_soc_dapm_widget
*w
,
1119 struct snd_kcontrol
*kcontrol
, int event
)
1121 late_enable_ev(w
, kcontrol
, event
);
1125 static int dac_ev(struct snd_soc_dapm_widget
*w
,
1126 struct snd_kcontrol
*kcontrol
, int event
)
1128 struct snd_soc_codec
*codec
= w
->codec
;
1129 unsigned int mask
= 1 << w
->shift
;
1131 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1136 static const char *hp_mux_text
[] = {
1141 #define WM8994_HP_ENUM(xname, xenum) \
1142 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1143 .info = snd_soc_info_enum_double, \
1144 .get = snd_soc_dapm_get_enum_double, \
1145 .put = wm8994_put_hp_enum, \
1146 .private_value = (unsigned long)&xenum }
1148 static int wm8994_put_hp_enum(struct snd_kcontrol
*kcontrol
,
1149 struct snd_ctl_elem_value
*ucontrol
)
1151 struct snd_soc_dapm_widget_list
*wlist
= snd_kcontrol_chip(kcontrol
);
1152 struct snd_soc_dapm_widget
*w
= wlist
->widgets
[0];
1153 struct snd_soc_codec
*codec
= w
->codec
;
1156 ret
= snd_soc_dapm_put_enum_double(kcontrol
, ucontrol
);
1158 wm8994_update_class_w(codec
);
1163 static const struct soc_enum hpl_enum
=
1164 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1
, 8, 2, hp_mux_text
);
1166 static const struct snd_kcontrol_new hpl_mux
=
1167 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum
);
1169 static const struct soc_enum hpr_enum
=
1170 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2
, 8, 2, hp_mux_text
);
1172 static const struct snd_kcontrol_new hpr_mux
=
1173 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum
);
1175 static const char *adc_mux_text
[] = {
1180 static const struct soc_enum adc_enum
=
1181 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text
);
1183 static const struct snd_kcontrol_new adcl_mux
=
1184 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum
);
1186 static const struct snd_kcontrol_new adcr_mux
=
1187 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum
);
1189 static const struct snd_kcontrol_new left_speaker_mixer
[] = {
1190 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER
, 9, 1, 0),
1191 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER
, 7, 1, 0),
1192 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER
, 5, 1, 0),
1193 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER
, 3, 1, 0),
1194 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER
, 1, 1, 0),
1197 static const struct snd_kcontrol_new right_speaker_mixer
[] = {
1198 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER
, 8, 1, 0),
1199 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER
, 6, 1, 0),
1200 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER
, 4, 1, 0),
1201 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER
, 2, 1, 0),
1202 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER
, 0, 1, 0),
1205 /* Debugging; dump chip status after DAPM transitions */
1206 static int post_ev(struct snd_soc_dapm_widget
*w
,
1207 struct snd_kcontrol
*kcontrol
, int event
)
1209 struct snd_soc_codec
*codec
= w
->codec
;
1210 dev_dbg(codec
->dev
, "SRC status: %x\n",
1212 WM8994_RATE_STATUS
));
1216 static const struct snd_kcontrol_new aif1adc1l_mix
[] = {
1217 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING
,
1219 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING
,
1223 static const struct snd_kcontrol_new aif1adc1r_mix
[] = {
1224 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING
,
1226 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING
,
1230 static const struct snd_kcontrol_new aif1adc2l_mix
[] = {
1231 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING
,
1233 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING
,
1237 static const struct snd_kcontrol_new aif1adc2r_mix
[] = {
1238 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING
,
1240 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING
,
1244 static const struct snd_kcontrol_new aif2dac2l_mix
[] = {
1245 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1247 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1249 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1251 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1253 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1257 static const struct snd_kcontrol_new aif2dac2r_mix
[] = {
1258 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1260 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1262 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1264 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1266 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1270 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1271 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1272 .info = snd_soc_info_volsw, \
1273 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1274 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1276 static int wm8994_put_class_w(struct snd_kcontrol
*kcontrol
,
1277 struct snd_ctl_elem_value
*ucontrol
)
1279 struct snd_soc_dapm_widget_list
*wlist
= snd_kcontrol_chip(kcontrol
);
1280 struct snd_soc_dapm_widget
*w
= wlist
->widgets
[0];
1281 struct snd_soc_codec
*codec
= w
->codec
;
1284 ret
= snd_soc_dapm_put_volsw(kcontrol
, ucontrol
);
1286 wm8994_update_class_w(codec
);
1291 static const struct snd_kcontrol_new dac1l_mix
[] = {
1292 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1294 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1296 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1298 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1300 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1304 static const struct snd_kcontrol_new dac1r_mix
[] = {
1305 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1307 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1309 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1311 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1313 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1317 static const char *sidetone_text
[] = {
1318 "ADC/DMIC1", "DMIC2",
1321 static const struct soc_enum sidetone1_enum
=
1322 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 0, 2, sidetone_text
);
1324 static const struct snd_kcontrol_new sidetone1_mux
=
1325 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum
);
1327 static const struct soc_enum sidetone2_enum
=
1328 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 1, 2, sidetone_text
);
1330 static const struct snd_kcontrol_new sidetone2_mux
=
1331 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum
);
1333 static const char *aif1dac_text
[] = {
1334 "AIF1DACDAT", "AIF3DACDAT",
1337 static const struct soc_enum aif1dac_enum
=
1338 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 0, 2, aif1dac_text
);
1340 static const struct snd_kcontrol_new aif1dac_mux
=
1341 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum
);
1343 static const char *aif2dac_text
[] = {
1344 "AIF2DACDAT", "AIF3DACDAT",
1347 static const struct soc_enum aif2dac_enum
=
1348 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 1, 2, aif2dac_text
);
1350 static const struct snd_kcontrol_new aif2dac_mux
=
1351 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum
);
1353 static const char *aif2adc_text
[] = {
1354 "AIF2ADCDAT", "AIF3DACDAT",
1357 static const struct soc_enum aif2adc_enum
=
1358 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 2, 2, aif2adc_text
);
1360 static const struct snd_kcontrol_new aif2adc_mux
=
1361 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum
);
1363 static const char *aif3adc_text
[] = {
1364 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1367 static const struct soc_enum wm8994_aif3adc_enum
=
1368 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 3, 3, aif3adc_text
);
1370 static const struct snd_kcontrol_new wm8994_aif3adc_mux
=
1371 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum
);
1373 static const struct soc_enum wm8958_aif3adc_enum
=
1374 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 3, 4, aif3adc_text
);
1376 static const struct snd_kcontrol_new wm8958_aif3adc_mux
=
1377 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum
);
1379 static const char *mono_pcm_out_text
[] = {
1380 "None", "AIF2ADCL", "AIF2ADCR",
1383 static const struct soc_enum mono_pcm_out_enum
=
1384 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 9, 3, mono_pcm_out_text
);
1386 static const struct snd_kcontrol_new mono_pcm_out_mux
=
1387 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum
);
1389 static const char *aif2dac_src_text
[] = {
1393 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1394 static const struct soc_enum aif2dacl_src_enum
=
1395 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 7, 2, aif2dac_src_text
);
1397 static const struct snd_kcontrol_new aif2dacl_src_mux
=
1398 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum
);
1400 static const struct soc_enum aif2dacr_src_enum
=
1401 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 8, 2, aif2dac_src_text
);
1403 static const struct snd_kcontrol_new aif2dacr_src_mux
=
1404 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum
);
1406 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets
[] = {
1407 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM
, 0, 0, aif1clk_ev
,
1408 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1409 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM
, 0, 0, aif2clk_ev
,
1410 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1412 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1413 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1414 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1415 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1416 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1417 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1418 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1419 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1420 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1421 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1423 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3
, 8, 0,
1424 left_speaker_mixer
, ARRAY_SIZE(left_speaker_mixer
),
1425 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1426 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3
, 9, 0,
1427 right_speaker_mixer
, ARRAY_SIZE(right_speaker_mixer
),
1428 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1429 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM
, 0, 0, &hpl_mux
,
1430 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1431 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM
, 0, 0, &hpr_mux
,
1432 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1434 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev
)
1437 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets
[] = {
1438 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1
, 0, 0, NULL
, 0),
1439 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1
, 0, 0, NULL
, 0),
1440 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM
, 0, 0, NULL
, 0),
1441 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3
, 8, 0,
1442 left_speaker_mixer
, ARRAY_SIZE(left_speaker_mixer
)),
1443 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3
, 9, 0,
1444 right_speaker_mixer
, ARRAY_SIZE(right_speaker_mixer
)),
1445 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM
, 0, 0, &hpl_mux
),
1446 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM
, 0, 0, &hpr_mux
),
1449 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets
[] = {
1450 SND_SOC_DAPM_DAC_E("DAC2L", NULL
, SND_SOC_NOPM
, 3, 0,
1451 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1452 SND_SOC_DAPM_DAC_E("DAC2R", NULL
, SND_SOC_NOPM
, 2, 0,
1453 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1454 SND_SOC_DAPM_DAC_E("DAC1L", NULL
, SND_SOC_NOPM
, 1, 0,
1455 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1456 SND_SOC_DAPM_DAC_E("DAC1R", NULL
, SND_SOC_NOPM
, 0, 0,
1457 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1460 static const struct snd_soc_dapm_widget wm8994_dac_widgets
[] = {
1461 SND_SOC_DAPM_DAC("DAC2L", NULL
, WM8994_POWER_MANAGEMENT_5
, 3, 0),
1462 SND_SOC_DAPM_DAC("DAC2R", NULL
, WM8994_POWER_MANAGEMENT_5
, 2, 0),
1463 SND_SOC_DAPM_DAC("DAC1L", NULL
, WM8994_POWER_MANAGEMENT_5
, 1, 0),
1464 SND_SOC_DAPM_DAC("DAC1R", NULL
, WM8994_POWER_MANAGEMENT_5
, 0, 0),
1467 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets
[] = {
1468 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4
, 1, 0, &adcl_mux
,
1469 adc_mux_ev
, SND_SOC_DAPM_PRE_PMU
),
1470 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4
, 0, 0, &adcr_mux
,
1471 adc_mux_ev
, SND_SOC_DAPM_PRE_PMU
),
1474 static const struct snd_soc_dapm_widget wm8994_adc_widgets
[] = {
1475 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4
, 1, 0, &adcl_mux
),
1476 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4
, 0, 0, &adcr_mux
),
1479 static const struct snd_soc_dapm_widget wm8994_dapm_widgets
[] = {
1480 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1481 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1482 SND_SOC_DAPM_INPUT("Clock"),
1484 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM
, 0, 0, micbias_ev
,
1485 SND_SOC_DAPM_PRE_PMU
),
1486 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM
, 0, 0, vmid_event
,
1487 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1489 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM
, 0, 0, clk_sys_event
,
1490 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1492 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1
, 3, 0, NULL
, 0),
1493 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1
, 2, 0, NULL
, 0),
1494 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1
, 1, 0, NULL
, 0),
1496 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL
,
1497 0, WM8994_POWER_MANAGEMENT_4
, 9, 0),
1498 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL
,
1499 0, WM8994_POWER_MANAGEMENT_4
, 8, 0),
1500 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL
, 0,
1501 WM8994_POWER_MANAGEMENT_5
, 9, 0, wm8958_aif_ev
,
1502 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1503 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL
, 0,
1504 WM8994_POWER_MANAGEMENT_5
, 8, 0, wm8958_aif_ev
,
1505 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1507 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL
,
1508 0, WM8994_POWER_MANAGEMENT_4
, 11, 0),
1509 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL
,
1510 0, WM8994_POWER_MANAGEMENT_4
, 10, 0),
1511 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL
, 0,
1512 WM8994_POWER_MANAGEMENT_5
, 11, 0, wm8958_aif_ev
,
1513 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1514 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL
, 0,
1515 WM8994_POWER_MANAGEMENT_5
, 10, 0, wm8958_aif_ev
,
1516 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1518 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM
, 0, 0,
1519 aif1adc1l_mix
, ARRAY_SIZE(aif1adc1l_mix
)),
1520 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM
, 0, 0,
1521 aif1adc1r_mix
, ARRAY_SIZE(aif1adc1r_mix
)),
1523 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM
, 0, 0,
1524 aif1adc2l_mix
, ARRAY_SIZE(aif1adc2l_mix
)),
1525 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM
, 0, 0,
1526 aif1adc2r_mix
, ARRAY_SIZE(aif1adc2r_mix
)),
1528 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM
, 0, 0,
1529 aif2dac2l_mix
, ARRAY_SIZE(aif2dac2l_mix
)),
1530 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM
, 0, 0,
1531 aif2dac2r_mix
, ARRAY_SIZE(aif2dac2r_mix
)),
1533 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM
, 0, 0, &sidetone1_mux
),
1534 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM
, 0, 0, &sidetone2_mux
),
1536 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM
, 0, 0,
1537 dac1l_mix
, ARRAY_SIZE(dac1l_mix
)),
1538 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM
, 0, 0,
1539 dac1r_mix
, ARRAY_SIZE(dac1r_mix
)),
1541 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL
, 0,
1542 WM8994_POWER_MANAGEMENT_4
, 13, 0),
1543 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL
, 0,
1544 WM8994_POWER_MANAGEMENT_4
, 12, 0),
1545 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL
, 0,
1546 WM8994_POWER_MANAGEMENT_5
, 13, 0, wm8958_aif_ev
,
1547 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1548 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL
, 0,
1549 WM8994_POWER_MANAGEMENT_5
, 12, 0, wm8958_aif_ev
,
1550 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1552 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM
, 0, 0),
1553 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM
, 0, 0),
1554 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM
, 0, 0),
1555 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM
, 0, 0),
1557 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM
, 0, 0, &aif1dac_mux
),
1558 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM
, 0, 0, &aif2dac_mux
),
1559 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM
, 0, 0, &aif2adc_mux
),
1561 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM
, 0, 0),
1562 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM
, 0, 0),
1564 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1
, 4, 0, NULL
, 0),
1566 SND_SOC_DAPM_ADC("DMIC2L", NULL
, WM8994_POWER_MANAGEMENT_4
, 5, 0),
1567 SND_SOC_DAPM_ADC("DMIC2R", NULL
, WM8994_POWER_MANAGEMENT_4
, 4, 0),
1568 SND_SOC_DAPM_ADC("DMIC1L", NULL
, WM8994_POWER_MANAGEMENT_4
, 3, 0),
1569 SND_SOC_DAPM_ADC("DMIC1R", NULL
, WM8994_POWER_MANAGEMENT_4
, 2, 0),
1571 /* Power is done with the muxes since the ADC power also controls the
1572 * downsampling chain, the chip will automatically manage the analogue
1573 * specific portions.
1575 SND_SOC_DAPM_ADC("ADCL", NULL
, SND_SOC_NOPM
, 1, 0),
1576 SND_SOC_DAPM_ADC("ADCR", NULL
, SND_SOC_NOPM
, 0, 0),
1578 SND_SOC_DAPM_POST("Debug log", post_ev
),
1581 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets
[] = {
1582 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM
, 0, 0, &wm8994_aif3adc_mux
),
1585 static const struct snd_soc_dapm_widget wm8958_dapm_widgets
[] = {
1586 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM
, 0, 0, &mono_pcm_out_mux
),
1587 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM
, 0, 0, &aif2dacl_src_mux
),
1588 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM
, 0, 0, &aif2dacr_src_mux
),
1589 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM
, 0, 0, &wm8958_aif3adc_mux
),
1592 static const struct snd_soc_dapm_route intercon
[] = {
1593 { "CLK_SYS", NULL
, "AIF1CLK", check_clk_sys
},
1594 { "CLK_SYS", NULL
, "AIF2CLK", check_clk_sys
},
1596 { "DSP1CLK", NULL
, "CLK_SYS" },
1597 { "DSP2CLK", NULL
, "CLK_SYS" },
1598 { "DSPINTCLK", NULL
, "CLK_SYS" },
1600 { "AIF1ADC1L", NULL
, "AIF1CLK" },
1601 { "AIF1ADC1L", NULL
, "DSP1CLK" },
1602 { "AIF1ADC1R", NULL
, "AIF1CLK" },
1603 { "AIF1ADC1R", NULL
, "DSP1CLK" },
1604 { "AIF1ADC1R", NULL
, "DSPINTCLK" },
1606 { "AIF1DAC1L", NULL
, "AIF1CLK" },
1607 { "AIF1DAC1L", NULL
, "DSP1CLK" },
1608 { "AIF1DAC1R", NULL
, "AIF1CLK" },
1609 { "AIF1DAC1R", NULL
, "DSP1CLK" },
1610 { "AIF1DAC1R", NULL
, "DSPINTCLK" },
1612 { "AIF1ADC2L", NULL
, "AIF1CLK" },
1613 { "AIF1ADC2L", NULL
, "DSP1CLK" },
1614 { "AIF1ADC2R", NULL
, "AIF1CLK" },
1615 { "AIF1ADC2R", NULL
, "DSP1CLK" },
1616 { "AIF1ADC2R", NULL
, "DSPINTCLK" },
1618 { "AIF1DAC2L", NULL
, "AIF1CLK" },
1619 { "AIF1DAC2L", NULL
, "DSP1CLK" },
1620 { "AIF1DAC2R", NULL
, "AIF1CLK" },
1621 { "AIF1DAC2R", NULL
, "DSP1CLK" },
1622 { "AIF1DAC2R", NULL
, "DSPINTCLK" },
1624 { "AIF2ADCL", NULL
, "AIF2CLK" },
1625 { "AIF2ADCL", NULL
, "DSP2CLK" },
1626 { "AIF2ADCR", NULL
, "AIF2CLK" },
1627 { "AIF2ADCR", NULL
, "DSP2CLK" },
1628 { "AIF2ADCR", NULL
, "DSPINTCLK" },
1630 { "AIF2DACL", NULL
, "AIF2CLK" },
1631 { "AIF2DACL", NULL
, "DSP2CLK" },
1632 { "AIF2DACR", NULL
, "AIF2CLK" },
1633 { "AIF2DACR", NULL
, "DSP2CLK" },
1634 { "AIF2DACR", NULL
, "DSPINTCLK" },
1636 { "DMIC1L", NULL
, "DMIC1DAT" },
1637 { "DMIC1L", NULL
, "CLK_SYS" },
1638 { "DMIC1R", NULL
, "DMIC1DAT" },
1639 { "DMIC1R", NULL
, "CLK_SYS" },
1640 { "DMIC2L", NULL
, "DMIC2DAT" },
1641 { "DMIC2L", NULL
, "CLK_SYS" },
1642 { "DMIC2R", NULL
, "DMIC2DAT" },
1643 { "DMIC2R", NULL
, "CLK_SYS" },
1645 { "ADCL", NULL
, "AIF1CLK" },
1646 { "ADCL", NULL
, "DSP1CLK" },
1647 { "ADCL", NULL
, "DSPINTCLK" },
1649 { "ADCR", NULL
, "AIF1CLK" },
1650 { "ADCR", NULL
, "DSP1CLK" },
1651 { "ADCR", NULL
, "DSPINTCLK" },
1653 { "ADCL Mux", "ADC", "ADCL" },
1654 { "ADCL Mux", "DMIC", "DMIC1L" },
1655 { "ADCR Mux", "ADC", "ADCR" },
1656 { "ADCR Mux", "DMIC", "DMIC1R" },
1658 { "DAC1L", NULL
, "AIF1CLK" },
1659 { "DAC1L", NULL
, "DSP1CLK" },
1660 { "DAC1L", NULL
, "DSPINTCLK" },
1662 { "DAC1R", NULL
, "AIF1CLK" },
1663 { "DAC1R", NULL
, "DSP1CLK" },
1664 { "DAC1R", NULL
, "DSPINTCLK" },
1666 { "DAC2L", NULL
, "AIF2CLK" },
1667 { "DAC2L", NULL
, "DSP2CLK" },
1668 { "DAC2L", NULL
, "DSPINTCLK" },
1670 { "DAC2R", NULL
, "AIF2DACR" },
1671 { "DAC2R", NULL
, "AIF2CLK" },
1672 { "DAC2R", NULL
, "DSP2CLK" },
1673 { "DAC2R", NULL
, "DSPINTCLK" },
1675 { "TOCLK", NULL
, "CLK_SYS" },
1678 { "AIF1ADC1L", NULL
, "AIF1ADC1L Mixer" },
1679 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1680 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1682 { "AIF1ADC1R", NULL
, "AIF1ADC1R Mixer" },
1683 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1684 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1686 { "AIF1ADC2L", NULL
, "AIF1ADC2L Mixer" },
1687 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1688 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1690 { "AIF1ADC2R", NULL
, "AIF1ADC2R Mixer" },
1691 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1692 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1694 /* Pin level routing for AIF3 */
1695 { "AIF1DAC1L", NULL
, "AIF1DAC Mux" },
1696 { "AIF1DAC1R", NULL
, "AIF1DAC Mux" },
1697 { "AIF1DAC2L", NULL
, "AIF1DAC Mux" },
1698 { "AIF1DAC2R", NULL
, "AIF1DAC Mux" },
1700 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1701 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1702 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1703 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1704 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1705 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1706 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1709 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1710 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1711 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1712 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1713 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1715 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1716 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1717 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1718 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1719 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1721 /* DAC2/AIF2 outputs */
1722 { "AIF2ADCL", NULL
, "AIF2DAC2L Mixer" },
1723 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1724 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1725 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1726 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1727 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1729 { "AIF2ADCR", NULL
, "AIF2DAC2R Mixer" },
1730 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1731 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1732 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1733 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1734 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1736 { "AIF1ADCDAT", NULL
, "AIF1ADC1L" },
1737 { "AIF1ADCDAT", NULL
, "AIF1ADC1R" },
1738 { "AIF1ADCDAT", NULL
, "AIF1ADC2L" },
1739 { "AIF1ADCDAT", NULL
, "AIF1ADC2R" },
1741 { "AIF2ADCDAT", NULL
, "AIF2ADC Mux" },
1744 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1745 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1746 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1747 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1748 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1749 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1750 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1751 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1754 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1755 { "Left Sidetone", "DMIC2", "DMIC2L" },
1756 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1757 { "Right Sidetone", "DMIC2", "DMIC2R" },
1760 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1761 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1763 { "SPKL", "DAC1 Switch", "DAC1L" },
1764 { "SPKL", "DAC2 Switch", "DAC2L" },
1766 { "SPKR", "DAC1 Switch", "DAC1R" },
1767 { "SPKR", "DAC2 Switch", "DAC2R" },
1769 { "Left Headphone Mux", "DAC", "DAC1L" },
1770 { "Right Headphone Mux", "DAC", "DAC1R" },
1773 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon
[] = {
1774 { "DAC1L", NULL
, "Late DAC1L Enable PGA" },
1775 { "Late DAC1L Enable PGA", NULL
, "DAC1L Mixer" },
1776 { "DAC1R", NULL
, "Late DAC1R Enable PGA" },
1777 { "Late DAC1R Enable PGA", NULL
, "DAC1R Mixer" },
1778 { "DAC2L", NULL
, "Late DAC2L Enable PGA" },
1779 { "Late DAC2L Enable PGA", NULL
, "AIF2DAC2L Mixer" },
1780 { "DAC2R", NULL
, "Late DAC2R Enable PGA" },
1781 { "Late DAC2R Enable PGA", NULL
, "AIF2DAC2R Mixer" }
1784 static const struct snd_soc_dapm_route wm8994_lateclk_intercon
[] = {
1785 { "DAC1L", NULL
, "DAC1L Mixer" },
1786 { "DAC1R", NULL
, "DAC1R Mixer" },
1787 { "DAC2L", NULL
, "AIF2DAC2L Mixer" },
1788 { "DAC2R", NULL
, "AIF2DAC2R Mixer" },
1791 static const struct snd_soc_dapm_route wm8994_revd_intercon
[] = {
1792 { "AIF1DACDAT", NULL
, "AIF2DACDAT" },
1793 { "AIF2DACDAT", NULL
, "AIF1DACDAT" },
1794 { "AIF1ADCDAT", NULL
, "AIF2ADCDAT" },
1795 { "AIF2ADCDAT", NULL
, "AIF1ADCDAT" },
1796 { "MICBIAS1", NULL
, "CLK_SYS" },
1797 { "MICBIAS1", NULL
, "MICBIAS Supply" },
1798 { "MICBIAS2", NULL
, "CLK_SYS" },
1799 { "MICBIAS2", NULL
, "MICBIAS Supply" },
1802 static const struct snd_soc_dapm_route wm8994_intercon
[] = {
1803 { "AIF2DACL", NULL
, "AIF2DAC Mux" },
1804 { "AIF2DACR", NULL
, "AIF2DAC Mux" },
1805 { "MICBIAS1", NULL
, "VMID" },
1806 { "MICBIAS2", NULL
, "VMID" },
1809 static const struct snd_soc_dapm_route wm8958_intercon
[] = {
1810 { "AIF2DACL", NULL
, "AIF2DACL Mux" },
1811 { "AIF2DACR", NULL
, "AIF2DACR Mux" },
1813 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1814 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1815 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1816 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1818 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1819 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1821 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1824 /* The size in bits of the FLL divide multiplied by 10
1825 * to allow rounding later */
1826 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1836 static int wm8994_get_fll_config(struct fll_div
*fll
,
1837 int freq_in
, int freq_out
)
1840 unsigned int K
, Ndiv
, Nmod
;
1842 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in
, freq_out
);
1844 /* Scale the input frequency down to <= 13.5MHz */
1845 fll
->clk_ref_div
= 0;
1846 while (freq_in
> 13500000) {
1850 if (fll
->clk_ref_div
> 3)
1853 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll
->clk_ref_div
, freq_in
);
1855 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1857 while (freq_out
* (fll
->outdiv
+ 1) < 90000000) {
1859 if (fll
->outdiv
> 63)
1862 freq_out
*= fll
->outdiv
+ 1;
1863 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll
->outdiv
, freq_out
);
1865 if (freq_in
> 1000000) {
1866 fll
->fll_fratio
= 0;
1867 } else if (freq_in
> 256000) {
1868 fll
->fll_fratio
= 1;
1870 } else if (freq_in
> 128000) {
1871 fll
->fll_fratio
= 2;
1873 } else if (freq_in
> 64000) {
1874 fll
->fll_fratio
= 3;
1877 fll
->fll_fratio
= 4;
1880 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll
->fll_fratio
, freq_in
);
1882 /* Now, calculate N.K */
1883 Ndiv
= freq_out
/ freq_in
;
1886 Nmod
= freq_out
% freq_in
;
1887 pr_debug("Nmod=%d\n", Nmod
);
1889 /* Calculate fractional part - scale up so we can round. */
1890 Kpart
= FIXED_FLL_SIZE
* (long long)Nmod
;
1892 do_div(Kpart
, freq_in
);
1894 K
= Kpart
& 0xFFFFFFFF;
1899 /* Move down to proper range now rounding is done */
1902 pr_debug("N=%x K=%x\n", fll
->n
, fll
->k
);
1907 static int _wm8994_set_fll(struct snd_soc_codec
*codec
, int id
, int src
,
1908 unsigned int freq_in
, unsigned int freq_out
)
1910 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1911 struct wm8994
*control
= wm8994
->wm8994
;
1912 int reg_offset
, ret
;
1914 u16 reg
, aif1
, aif2
;
1915 unsigned long timeout
;
1918 aif1
= snd_soc_read(codec
, WM8994_AIF1_CLOCKING_1
)
1919 & WM8994_AIF1CLK_ENA
;
1921 aif2
= snd_soc_read(codec
, WM8994_AIF2_CLOCKING_1
)
1922 & WM8994_AIF2CLK_ENA
;
1937 reg
= snd_soc_read(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
);
1938 was_enabled
= reg
& WM8994_FLL1_ENA
;
1942 /* Allow no source specification when stopping */
1945 src
= wm8994
->fll
[id
].src
;
1947 case WM8994_FLL_SRC_MCLK1
:
1948 case WM8994_FLL_SRC_MCLK2
:
1949 case WM8994_FLL_SRC_LRCLK
:
1950 case WM8994_FLL_SRC_BCLK
:
1956 /* Are we changing anything? */
1957 if (wm8994
->fll
[id
].src
== src
&&
1958 wm8994
->fll
[id
].in
== freq_in
&& wm8994
->fll
[id
].out
== freq_out
)
1961 /* If we're stopping the FLL redo the old config - no
1962 * registers will actually be written but we avoid GCC flow
1963 * analysis bugs spewing warnings.
1966 ret
= wm8994_get_fll_config(&fll
, freq_in
, freq_out
);
1968 ret
= wm8994_get_fll_config(&fll
, wm8994
->fll
[id
].in
,
1969 wm8994
->fll
[id
].out
);
1973 /* Gate the AIF clocks while we reclock */
1974 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
1975 WM8994_AIF1CLK_ENA
, 0);
1976 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
1977 WM8994_AIF2CLK_ENA
, 0);
1979 /* We always need to disable the FLL while reconfiguring */
1980 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
,
1981 WM8994_FLL1_ENA
, 0);
1983 reg
= (fll
.outdiv
<< WM8994_FLL1_OUTDIV_SHIFT
) |
1984 (fll
.fll_fratio
<< WM8994_FLL1_FRATIO_SHIFT
);
1985 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_2
+ reg_offset
,
1986 WM8994_FLL1_OUTDIV_MASK
|
1987 WM8994_FLL1_FRATIO_MASK
, reg
);
1989 snd_soc_write(codec
, WM8994_FLL1_CONTROL_3
+ reg_offset
, fll
.k
);
1991 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_4
+ reg_offset
,
1993 fll
.n
<< WM8994_FLL1_N_SHIFT
);
1995 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_5
+ reg_offset
,
1996 WM8994_FLL1_REFCLK_DIV_MASK
|
1997 WM8994_FLL1_REFCLK_SRC_MASK
,
1998 (fll
.clk_ref_div
<< WM8994_FLL1_REFCLK_DIV_SHIFT
) |
2001 /* Clear any pending completion from a previous failure */
2002 try_wait_for_completion(&wm8994
->fll_locked
[id
]);
2004 /* Enable (with fractional mode if required) */
2006 /* Enable VMID if we need it */
2008 active_reference(codec
);
2010 switch (control
->type
) {
2012 vmid_reference(codec
);
2015 if (wm8994
->revision
< 1)
2016 vmid_reference(codec
);
2024 reg
= WM8994_FLL1_ENA
| WM8994_FLL1_FRAC
;
2026 reg
= WM8994_FLL1_ENA
;
2027 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
,
2028 WM8994_FLL1_ENA
| WM8994_FLL1_FRAC
,
2031 if (wm8994
->fll_locked_irq
) {
2032 timeout
= wait_for_completion_timeout(&wm8994
->fll_locked
[id
],
2033 msecs_to_jiffies(10));
2035 dev_warn(codec
->dev
,
2036 "Timed out waiting for FLL lock\n");
2042 switch (control
->type
) {
2044 vmid_dereference(codec
);
2047 if (wm8994
->revision
< 1)
2048 vmid_dereference(codec
);
2054 active_dereference(codec
);
2058 wm8994
->fll
[id
].in
= freq_in
;
2059 wm8994
->fll
[id
].out
= freq_out
;
2060 wm8994
->fll
[id
].src
= src
;
2062 /* Enable any gated AIF clocks */
2063 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
2064 WM8994_AIF1CLK_ENA
, aif1
);
2065 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
2066 WM8994_AIF2CLK_ENA
, aif2
);
2068 configure_clock(codec
);
2073 static irqreturn_t
wm8994_fll_locked_irq(int irq
, void *data
)
2075 struct completion
*completion
= data
;
2077 complete(completion
);
2082 static int opclk_divs
[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2084 static int wm8994_set_fll(struct snd_soc_dai
*dai
, int id
, int src
,
2085 unsigned int freq_in
, unsigned int freq_out
)
2087 return _wm8994_set_fll(dai
->codec
, id
, src
, freq_in
, freq_out
);
2090 static int wm8994_set_dai_sysclk(struct snd_soc_dai
*dai
,
2091 int clk_id
, unsigned int freq
, int dir
)
2093 struct snd_soc_codec
*codec
= dai
->codec
;
2094 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2103 /* AIF3 shares clocking with AIF1/2 */
2108 case WM8994_SYSCLK_MCLK1
:
2109 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_MCLK1
;
2110 wm8994
->mclk
[0] = freq
;
2111 dev_dbg(dai
->dev
, "AIF%d using MCLK1 at %uHz\n",
2115 case WM8994_SYSCLK_MCLK2
:
2116 /* TODO: Set GPIO AF */
2117 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_MCLK2
;
2118 wm8994
->mclk
[1] = freq
;
2119 dev_dbg(dai
->dev
, "AIF%d using MCLK2 at %uHz\n",
2123 case WM8994_SYSCLK_FLL1
:
2124 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_FLL1
;
2125 dev_dbg(dai
->dev
, "AIF%d using FLL1\n", dai
->id
);
2128 case WM8994_SYSCLK_FLL2
:
2129 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_FLL2
;
2130 dev_dbg(dai
->dev
, "AIF%d using FLL2\n", dai
->id
);
2133 case WM8994_SYSCLK_OPCLK
:
2134 /* Special case - a division (times 10) is given and
2135 * no effect on main clocking.
2138 for (i
= 0; i
< ARRAY_SIZE(opclk_divs
); i
++)
2139 if (opclk_divs
[i
] == freq
)
2141 if (i
== ARRAY_SIZE(opclk_divs
))
2143 snd_soc_update_bits(codec
, WM8994_CLOCKING_2
,
2144 WM8994_OPCLK_DIV_MASK
, i
);
2145 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_2
,
2146 WM8994_OPCLK_ENA
, WM8994_OPCLK_ENA
);
2148 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_2
,
2149 WM8994_OPCLK_ENA
, 0);
2156 configure_clock(codec
);
2161 static int wm8994_set_bias_level(struct snd_soc_codec
*codec
,
2162 enum snd_soc_bias_level level
)
2164 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2165 struct wm8994
*control
= wm8994
->wm8994
;
2168 case SND_SOC_BIAS_ON
:
2171 case SND_SOC_BIAS_PREPARE
:
2172 /* MICBIAS into regulating mode */
2173 switch (control
->type
) {
2176 snd_soc_update_bits(codec
, WM8958_MICBIAS1
,
2177 WM8958_MICB1_MODE
, 0);
2178 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
2179 WM8958_MICB2_MODE
, 0);
2185 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_STANDBY
)
2186 active_reference(codec
);
2189 case SND_SOC_BIAS_STANDBY
:
2190 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
2191 pm_runtime_get_sync(codec
->dev
);
2193 switch (control
->type
) {
2195 if (wm8994
->revision
< 4) {
2196 /* Tweak DC servo and DSP
2197 * configuration for improved
2199 snd_soc_write(codec
, 0x102, 0x3);
2200 snd_soc_write(codec
, 0x56, 0x3);
2201 snd_soc_write(codec
, 0x817, 0);
2202 snd_soc_write(codec
, 0x102, 0);
2207 if (wm8994
->revision
== 0) {
2208 /* Optimise performance for rev A */
2209 snd_soc_write(codec
, 0x102, 0x3);
2210 snd_soc_write(codec
, 0xcb, 0x81);
2211 snd_soc_write(codec
, 0x817, 0);
2212 snd_soc_write(codec
, 0x102, 0);
2214 snd_soc_update_bits(codec
,
2215 WM8958_CHARGE_PUMP_2
,
2222 if (wm8994
->revision
< 2) {
2223 snd_soc_write(codec
, 0x102, 0x3);
2224 snd_soc_write(codec
, 0x5d, 0x7e);
2225 snd_soc_write(codec
, 0x5e, 0x0);
2226 snd_soc_write(codec
, 0x102, 0x0);
2231 /* Discharge LINEOUT1 & 2 */
2232 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
2233 WM8994_LINEOUT1_DISCH
|
2234 WM8994_LINEOUT2_DISCH
,
2235 WM8994_LINEOUT1_DISCH
|
2236 WM8994_LINEOUT2_DISCH
);
2239 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_PREPARE
)
2240 active_dereference(codec
);
2242 /* MICBIAS into bypass mode on newer devices */
2243 switch (control
->type
) {
2246 snd_soc_update_bits(codec
, WM8958_MICBIAS1
,
2249 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
2258 case SND_SOC_BIAS_OFF
:
2259 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_STANDBY
) {
2260 wm8994
->cur_fw
= NULL
;
2262 pm_runtime_put(codec
->dev
);
2266 codec
->dapm
.bias_level
= level
;
2271 static int wm8994_set_dai_fmt(struct snd_soc_dai
*dai
, unsigned int fmt
)
2273 struct snd_soc_codec
*codec
= dai
->codec
;
2274 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2275 struct wm8994
*control
= wm8994
->wm8994
;
2283 ms_reg
= WM8994_AIF1_MASTER_SLAVE
;
2284 aif1_reg
= WM8994_AIF1_CONTROL_1
;
2287 ms_reg
= WM8994_AIF2_MASTER_SLAVE
;
2288 aif1_reg
= WM8994_AIF2_CONTROL_1
;
2294 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
2295 case SND_SOC_DAIFMT_CBS_CFS
:
2297 case SND_SOC_DAIFMT_CBM_CFM
:
2298 ms
= WM8994_AIF1_MSTR
;
2304 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
2305 case SND_SOC_DAIFMT_DSP_B
:
2306 aif1
|= WM8994_AIF1_LRCLK_INV
;
2307 case SND_SOC_DAIFMT_DSP_A
:
2310 case SND_SOC_DAIFMT_I2S
:
2313 case SND_SOC_DAIFMT_RIGHT_J
:
2315 case SND_SOC_DAIFMT_LEFT_J
:
2322 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
2323 case SND_SOC_DAIFMT_DSP_A
:
2324 case SND_SOC_DAIFMT_DSP_B
:
2325 /* frame inversion not valid for DSP modes */
2326 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
2327 case SND_SOC_DAIFMT_NB_NF
:
2329 case SND_SOC_DAIFMT_IB_NF
:
2330 aif1
|= WM8994_AIF1_BCLK_INV
;
2337 case SND_SOC_DAIFMT_I2S
:
2338 case SND_SOC_DAIFMT_RIGHT_J
:
2339 case SND_SOC_DAIFMT_LEFT_J
:
2340 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
2341 case SND_SOC_DAIFMT_NB_NF
:
2343 case SND_SOC_DAIFMT_IB_IF
:
2344 aif1
|= WM8994_AIF1_BCLK_INV
| WM8994_AIF1_LRCLK_INV
;
2346 case SND_SOC_DAIFMT_IB_NF
:
2347 aif1
|= WM8994_AIF1_BCLK_INV
;
2349 case SND_SOC_DAIFMT_NB_IF
:
2350 aif1
|= WM8994_AIF1_LRCLK_INV
;
2360 /* The AIF2 format configuration needs to be mirrored to AIF3
2361 * on WM8958 if it's in use so just do it all the time. */
2362 switch (control
->type
) {
2366 snd_soc_update_bits(codec
, WM8958_AIF3_CONTROL_1
,
2367 WM8994_AIF1_LRCLK_INV
|
2368 WM8958_AIF3_FMT_MASK
, aif1
);
2375 snd_soc_update_bits(codec
, aif1_reg
,
2376 WM8994_AIF1_BCLK_INV
| WM8994_AIF1_LRCLK_INV
|
2377 WM8994_AIF1_FMT_MASK
,
2379 snd_soc_update_bits(codec
, ms_reg
, WM8994_AIF1_MSTR
,
2401 static int fs_ratios
[] = {
2402 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2405 static int bclk_divs
[] = {
2406 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2407 640, 880, 960, 1280, 1760, 1920
2410 static int wm8994_hw_params(struct snd_pcm_substream
*substream
,
2411 struct snd_pcm_hw_params
*params
,
2412 struct snd_soc_dai
*dai
)
2414 struct snd_soc_codec
*codec
= dai
->codec
;
2415 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2426 int id
= dai
->id
- 1;
2428 int i
, cur_val
, best_val
, bclk_rate
, best
;
2432 aif1_reg
= WM8994_AIF1_CONTROL_1
;
2433 aif2_reg
= WM8994_AIF1_CONTROL_2
;
2434 bclk_reg
= WM8994_AIF1_BCLK
;
2435 rate_reg
= WM8994_AIF1_RATE
;
2436 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
||
2437 wm8994
->lrclk_shared
[0]) {
2438 lrclk_reg
= WM8994_AIF1DAC_LRCLK
;
2440 lrclk_reg
= WM8994_AIF1ADC_LRCLK
;
2441 dev_dbg(codec
->dev
, "AIF1 using split LRCLK\n");
2445 aif1_reg
= WM8994_AIF2_CONTROL_1
;
2446 aif2_reg
= WM8994_AIF2_CONTROL_2
;
2447 bclk_reg
= WM8994_AIF2_BCLK
;
2448 rate_reg
= WM8994_AIF2_RATE
;
2449 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
||
2450 wm8994
->lrclk_shared
[1]) {
2451 lrclk_reg
= WM8994_AIF2DAC_LRCLK
;
2453 lrclk_reg
= WM8994_AIF2ADC_LRCLK
;
2454 dev_dbg(codec
->dev
, "AIF2 using split LRCLK\n");
2461 bclk_rate
= params_rate(params
) * 2;
2462 switch (params_format(params
)) {
2463 case SNDRV_PCM_FORMAT_S16_LE
:
2466 case SNDRV_PCM_FORMAT_S20_3LE
:
2470 case SNDRV_PCM_FORMAT_S24_LE
:
2474 case SNDRV_PCM_FORMAT_S32_LE
:
2482 /* Try to find an appropriate sample rate; look for an exact match. */
2483 for (i
= 0; i
< ARRAY_SIZE(srs
); i
++)
2484 if (srs
[i
].rate
== params_rate(params
))
2486 if (i
== ARRAY_SIZE(srs
))
2488 rate_val
|= srs
[i
].val
<< WM8994_AIF1_SR_SHIFT
;
2490 dev_dbg(dai
->dev
, "Sample rate is %dHz\n", srs
[i
].rate
);
2491 dev_dbg(dai
->dev
, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2492 dai
->id
, wm8994
->aifclk
[id
], bclk_rate
);
2494 if (params_channels(params
) == 1 &&
2495 (snd_soc_read(codec
, aif1_reg
) & 0x18) == 0x18)
2496 aif2
|= WM8994_AIF1_MONO
;
2498 if (wm8994
->aifclk
[id
] == 0) {
2499 dev_err(dai
->dev
, "AIF%dCLK not configured\n", dai
->id
);
2503 /* AIFCLK/fs ratio; look for a close match in either direction */
2505 best_val
= abs((fs_ratios
[0] * params_rate(params
))
2506 - wm8994
->aifclk
[id
]);
2507 for (i
= 1; i
< ARRAY_SIZE(fs_ratios
); i
++) {
2508 cur_val
= abs((fs_ratios
[i
] * params_rate(params
))
2509 - wm8994
->aifclk
[id
]);
2510 if (cur_val
>= best_val
)
2515 dev_dbg(dai
->dev
, "Selected AIF%dCLK/fs = %d\n",
2516 dai
->id
, fs_ratios
[best
]);
2519 /* We may not get quite the right frequency if using
2520 * approximate clocks so look for the closest match that is
2521 * higher than the target (we need to ensure that there enough
2522 * BCLKs to clock out the samples).
2525 for (i
= 0; i
< ARRAY_SIZE(bclk_divs
); i
++) {
2526 cur_val
= (wm8994
->aifclk
[id
] * 10 / bclk_divs
[i
]) - bclk_rate
;
2527 if (cur_val
< 0) /* BCLK table is sorted */
2531 bclk_rate
= wm8994
->aifclk
[id
] * 10 / bclk_divs
[best
];
2532 dev_dbg(dai
->dev
, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2533 bclk_divs
[best
], bclk_rate
);
2534 bclk
|= best
<< WM8994_AIF1_BCLK_DIV_SHIFT
;
2536 lrclk
= bclk_rate
/ params_rate(params
);
2538 dev_err(dai
->dev
, "Unable to generate LRCLK from %dHz BCLK\n",
2542 dev_dbg(dai
->dev
, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2543 lrclk
, bclk_rate
/ lrclk
);
2545 snd_soc_update_bits(codec
, aif1_reg
, WM8994_AIF1_WL_MASK
, aif1
);
2546 snd_soc_update_bits(codec
, aif2_reg
, WM8994_AIF1_MONO
, aif2
);
2547 snd_soc_update_bits(codec
, bclk_reg
, WM8994_AIF1_BCLK_DIV_MASK
, bclk
);
2548 snd_soc_update_bits(codec
, lrclk_reg
, WM8994_AIF1DAC_RATE_MASK
,
2550 snd_soc_update_bits(codec
, rate_reg
, WM8994_AIF1_SR_MASK
|
2551 WM8994_AIF1CLK_RATE_MASK
, rate_val
);
2553 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
2556 wm8994
->dac_rates
[0] = params_rate(params
);
2557 wm8994_set_retune_mobile(codec
, 0);
2558 wm8994_set_retune_mobile(codec
, 1);
2561 wm8994
->dac_rates
[1] = params_rate(params
);
2562 wm8994_set_retune_mobile(codec
, 2);
2570 static int wm8994_aif3_hw_params(struct snd_pcm_substream
*substream
,
2571 struct snd_pcm_hw_params
*params
,
2572 struct snd_soc_dai
*dai
)
2574 struct snd_soc_codec
*codec
= dai
->codec
;
2575 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2576 struct wm8994
*control
= wm8994
->wm8994
;
2582 switch (control
->type
) {
2585 aif1_reg
= WM8958_AIF3_CONTROL_1
;
2594 switch (params_format(params
)) {
2595 case SNDRV_PCM_FORMAT_S16_LE
:
2597 case SNDRV_PCM_FORMAT_S20_3LE
:
2600 case SNDRV_PCM_FORMAT_S24_LE
:
2603 case SNDRV_PCM_FORMAT_S32_LE
:
2610 return snd_soc_update_bits(codec
, aif1_reg
, WM8994_AIF1_WL_MASK
, aif1
);
2613 static void wm8994_aif_shutdown(struct snd_pcm_substream
*substream
,
2614 struct snd_soc_dai
*dai
)
2616 struct snd_soc_codec
*codec
= dai
->codec
;
2621 rate_reg
= WM8994_AIF1_RATE
;
2624 rate_reg
= WM8994_AIF2_RATE
;
2630 /* If the DAI is idle then configure the divider tree for the
2631 * lowest output rate to save a little power if the clock is
2632 * still active (eg, because it is system clock).
2634 if (rate_reg
&& !dai
->playback_active
&& !dai
->capture_active
)
2635 snd_soc_update_bits(codec
, rate_reg
,
2636 WM8994_AIF1_SR_MASK
|
2637 WM8994_AIF1CLK_RATE_MASK
, 0x9);
2640 static int wm8994_aif_mute(struct snd_soc_dai
*codec_dai
, int mute
)
2642 struct snd_soc_codec
*codec
= codec_dai
->codec
;
2646 switch (codec_dai
->id
) {
2648 mute_reg
= WM8994_AIF1_DAC1_FILTERS_1
;
2651 mute_reg
= WM8994_AIF2_DAC_FILTERS_1
;
2658 reg
= WM8994_AIF1DAC1_MUTE
;
2662 snd_soc_update_bits(codec
, mute_reg
, WM8994_AIF1DAC1_MUTE
, reg
);
2667 static int wm8994_set_tristate(struct snd_soc_dai
*codec_dai
, int tristate
)
2669 struct snd_soc_codec
*codec
= codec_dai
->codec
;
2672 switch (codec_dai
->id
) {
2674 reg
= WM8994_AIF1_MASTER_SLAVE
;
2675 mask
= WM8994_AIF1_TRI
;
2678 reg
= WM8994_AIF2_MASTER_SLAVE
;
2679 mask
= WM8994_AIF2_TRI
;
2682 reg
= WM8994_POWER_MANAGEMENT_6
;
2683 mask
= WM8994_AIF3_TRI
;
2694 return snd_soc_update_bits(codec
, reg
, mask
, val
);
2697 static int wm8994_aif2_probe(struct snd_soc_dai
*dai
)
2699 struct snd_soc_codec
*codec
= dai
->codec
;
2701 /* Disable the pulls on the AIF if we're using it to save power. */
2702 snd_soc_update_bits(codec
, WM8994_GPIO_3
,
2703 WM8994_GPN_PU
| WM8994_GPN_PD
, 0);
2704 snd_soc_update_bits(codec
, WM8994_GPIO_4
,
2705 WM8994_GPN_PU
| WM8994_GPN_PD
, 0);
2706 snd_soc_update_bits(codec
, WM8994_GPIO_5
,
2707 WM8994_GPN_PU
| WM8994_GPN_PD
, 0);
2712 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2714 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2715 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2717 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops
= {
2718 .set_sysclk
= wm8994_set_dai_sysclk
,
2719 .set_fmt
= wm8994_set_dai_fmt
,
2720 .hw_params
= wm8994_hw_params
,
2721 .shutdown
= wm8994_aif_shutdown
,
2722 .digital_mute
= wm8994_aif_mute
,
2723 .set_pll
= wm8994_set_fll
,
2724 .set_tristate
= wm8994_set_tristate
,
2727 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops
= {
2728 .set_sysclk
= wm8994_set_dai_sysclk
,
2729 .set_fmt
= wm8994_set_dai_fmt
,
2730 .hw_params
= wm8994_hw_params
,
2731 .shutdown
= wm8994_aif_shutdown
,
2732 .digital_mute
= wm8994_aif_mute
,
2733 .set_pll
= wm8994_set_fll
,
2734 .set_tristate
= wm8994_set_tristate
,
2737 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops
= {
2738 .hw_params
= wm8994_aif3_hw_params
,
2739 .set_tristate
= wm8994_set_tristate
,
2742 static struct snd_soc_dai_driver wm8994_dai
[] = {
2744 .name
= "wm8994-aif1",
2747 .stream_name
= "AIF1 Playback",
2750 .rates
= WM8994_RATES
,
2751 .formats
= WM8994_FORMATS
,
2754 .stream_name
= "AIF1 Capture",
2757 .rates
= WM8994_RATES
,
2758 .formats
= WM8994_FORMATS
,
2760 .ops
= &wm8994_aif1_dai_ops
,
2763 .name
= "wm8994-aif2",
2766 .stream_name
= "AIF2 Playback",
2769 .rates
= WM8994_RATES
,
2770 .formats
= WM8994_FORMATS
,
2773 .stream_name
= "AIF2 Capture",
2776 .rates
= WM8994_RATES
,
2777 .formats
= WM8994_FORMATS
,
2779 .probe
= wm8994_aif2_probe
,
2780 .ops
= &wm8994_aif2_dai_ops
,
2783 .name
= "wm8994-aif3",
2786 .stream_name
= "AIF3 Playback",
2789 .rates
= WM8994_RATES
,
2790 .formats
= WM8994_FORMATS
,
2793 .stream_name
= "AIF3 Capture",
2796 .rates
= WM8994_RATES
,
2797 .formats
= WM8994_FORMATS
,
2799 .ops
= &wm8994_aif3_dai_ops
,
2804 static int wm8994_suspend(struct snd_soc_codec
*codec
)
2806 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2807 struct wm8994
*control
= wm8994
->wm8994
;
2810 switch (control
->type
) {
2812 snd_soc_update_bits(codec
, WM8994_MICBIAS
, WM8994_MICD_ENA
, 0);
2815 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
2816 WM1811_JACKDET_MODE_MASK
, 0);
2819 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
2820 WM8958_MICD_ENA
, 0);
2824 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll
); i
++) {
2825 memcpy(&wm8994
->fll_suspend
[i
], &wm8994
->fll
[i
],
2826 sizeof(struct wm8994_fll_config
));
2827 ret
= _wm8994_set_fll(codec
, i
+ 1, 0, 0, 0);
2829 dev_warn(codec
->dev
, "Failed to stop FLL%d: %d\n",
2833 wm8994_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
2838 static int wm8994_resume(struct snd_soc_codec
*codec
)
2840 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2841 struct wm8994
*control
= wm8994
->wm8994
;
2843 unsigned int val
, mask
;
2845 if (wm8994
->revision
< 4) {
2846 /* force a HW read */
2847 val
= wm8994_reg_read(codec
->control_data
,
2848 WM8994_POWER_MANAGEMENT_5
);
2850 /* modify the cache only */
2851 codec
->cache_only
= 1;
2852 mask
= WM8994_DAC1R_ENA
| WM8994_DAC1L_ENA
|
2853 WM8994_DAC2R_ENA
| WM8994_DAC2L_ENA
;
2855 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
2857 codec
->cache_only
= 0;
2860 /* Restore the registers */
2861 ret
= snd_soc_cache_sync(codec
);
2863 dev_err(codec
->dev
, "Failed to sync cache: %d\n", ret
);
2865 wm8994_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
2867 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll
); i
++) {
2868 if (!wm8994
->fll_suspend
[i
].out
)
2871 ret
= _wm8994_set_fll(codec
, i
+ 1,
2872 wm8994
->fll_suspend
[i
].src
,
2873 wm8994
->fll_suspend
[i
].in
,
2874 wm8994
->fll_suspend
[i
].out
);
2876 dev_warn(codec
->dev
, "Failed to restore FLL%d: %d\n",
2880 switch (control
->type
) {
2882 if (wm8994
->micdet
[0].jack
|| wm8994
->micdet
[1].jack
)
2883 snd_soc_update_bits(codec
, WM8994_MICBIAS
,
2884 WM8994_MICD_ENA
, WM8994_MICD_ENA
);
2887 if (wm8994
->jackdet
&& wm8994
->jack_cb
) {
2888 /* Restart from idle */
2889 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
2890 WM1811_JACKDET_MODE_MASK
,
2891 WM1811_JACKDET_MODE_JACK
);
2895 if (wm8994
->jack_cb
)
2896 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
2897 WM8958_MICD_ENA
, WM8958_MICD_ENA
);
2904 #define wm8994_suspend NULL
2905 #define wm8994_resume NULL
2908 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv
*wm8994
)
2910 struct snd_soc_codec
*codec
= wm8994
->codec
;
2911 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
2912 struct snd_kcontrol_new controls
[] = {
2913 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2914 wm8994
->retune_mobile_enum
,
2915 wm8994_get_retune_mobile_enum
,
2916 wm8994_put_retune_mobile_enum
),
2917 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2918 wm8994
->retune_mobile_enum
,
2919 wm8994_get_retune_mobile_enum
,
2920 wm8994_put_retune_mobile_enum
),
2921 SOC_ENUM_EXT("AIF2 EQ Mode",
2922 wm8994
->retune_mobile_enum
,
2923 wm8994_get_retune_mobile_enum
,
2924 wm8994_put_retune_mobile_enum
),
2929 /* We need an array of texts for the enum API but the number
2930 * of texts is likely to be less than the number of
2931 * configurations due to the sample rate dependency of the
2932 * configurations. */
2933 wm8994
->num_retune_mobile_texts
= 0;
2934 wm8994
->retune_mobile_texts
= NULL
;
2935 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
2936 for (j
= 0; j
< wm8994
->num_retune_mobile_texts
; j
++) {
2937 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
2938 wm8994
->retune_mobile_texts
[j
]) == 0)
2942 if (j
!= wm8994
->num_retune_mobile_texts
)
2945 /* Expand the array... */
2946 t
= krealloc(wm8994
->retune_mobile_texts
,
2948 (wm8994
->num_retune_mobile_texts
+ 1),
2953 /* ...store the new entry... */
2954 t
[wm8994
->num_retune_mobile_texts
] =
2955 pdata
->retune_mobile_cfgs
[i
].name
;
2957 /* ...and remember the new version. */
2958 wm8994
->num_retune_mobile_texts
++;
2959 wm8994
->retune_mobile_texts
= t
;
2962 dev_dbg(codec
->dev
, "Allocated %d unique ReTune Mobile names\n",
2963 wm8994
->num_retune_mobile_texts
);
2965 wm8994
->retune_mobile_enum
.max
= wm8994
->num_retune_mobile_texts
;
2966 wm8994
->retune_mobile_enum
.texts
= wm8994
->retune_mobile_texts
;
2968 ret
= snd_soc_add_controls(wm8994
->codec
, controls
,
2969 ARRAY_SIZE(controls
));
2971 dev_err(wm8994
->codec
->dev
,
2972 "Failed to add ReTune Mobile controls: %d\n", ret
);
2975 static void wm8994_handle_pdata(struct wm8994_priv
*wm8994
)
2977 struct snd_soc_codec
*codec
= wm8994
->codec
;
2978 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
2984 wm_hubs_handle_analogue_pdata(codec
, pdata
->lineout1_diff
,
2985 pdata
->lineout2_diff
,
2990 pdata
->micbias1_lvl
,
2991 pdata
->micbias2_lvl
);
2993 dev_dbg(codec
->dev
, "%d DRC configurations\n", pdata
->num_drc_cfgs
);
2995 if (pdata
->num_drc_cfgs
) {
2996 struct snd_kcontrol_new controls
[] = {
2997 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994
->drc_enum
,
2998 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
2999 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994
->drc_enum
,
3000 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
3001 SOC_ENUM_EXT("AIF2DRC Mode", wm8994
->drc_enum
,
3002 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
3005 /* We need an array of texts for the enum API */
3006 wm8994
->drc_texts
= devm_kzalloc(wm8994
->codec
->dev
,
3007 sizeof(char *) * pdata
->num_drc_cfgs
, GFP_KERNEL
);
3008 if (!wm8994
->drc_texts
) {
3009 dev_err(wm8994
->codec
->dev
,
3010 "Failed to allocate %d DRC config texts\n",
3011 pdata
->num_drc_cfgs
);
3015 for (i
= 0; i
< pdata
->num_drc_cfgs
; i
++)
3016 wm8994
->drc_texts
[i
] = pdata
->drc_cfgs
[i
].name
;
3018 wm8994
->drc_enum
.max
= pdata
->num_drc_cfgs
;
3019 wm8994
->drc_enum
.texts
= wm8994
->drc_texts
;
3021 ret
= snd_soc_add_controls(wm8994
->codec
, controls
,
3022 ARRAY_SIZE(controls
));
3024 dev_err(wm8994
->codec
->dev
,
3025 "Failed to add DRC mode controls: %d\n", ret
);
3027 for (i
= 0; i
< WM8994_NUM_DRC
; i
++)
3028 wm8994_set_drc(codec
, i
);
3031 dev_dbg(codec
->dev
, "%d ReTune Mobile configurations\n",
3032 pdata
->num_retune_mobile_cfgs
);
3034 if (pdata
->num_retune_mobile_cfgs
)
3035 wm8994_handle_retune_mobile_pdata(wm8994
);
3037 snd_soc_add_controls(wm8994
->codec
, wm8994_eq_controls
,
3038 ARRAY_SIZE(wm8994_eq_controls
));
3040 for (i
= 0; i
< ARRAY_SIZE(pdata
->micbias
); i
++) {
3041 if (pdata
->micbias
[i
]) {
3042 snd_soc_write(codec
, WM8958_MICBIAS1
+ i
,
3043 pdata
->micbias
[i
] & 0xffff);
3049 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3051 * @codec: WM8994 codec
3052 * @jack: jack to report detection events on
3053 * @micbias: microphone bias to detect on
3054 * @det: value to report for presence detection
3055 * @shrt: value to report for short detection
3057 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3058 * being used to bring out signals to the processor then only platform
3059 * data configuration is needed for WM8994 and processor GPIOs should
3060 * be configured using snd_soc_jack_add_gpios() instead.
3062 * Configuration of detection levels is available via the micbias1_lvl
3063 * and micbias2_lvl platform data members.
3065 int wm8994_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
3066 int micbias
, int det
, int shrt
)
3068 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3069 struct wm8994_micdet
*micdet
;
3070 struct wm8994
*control
= wm8994
->wm8994
;
3073 if (control
->type
!= WM8994
)
3078 micdet
= &wm8994
->micdet
[0];
3081 micdet
= &wm8994
->micdet
[1];
3087 dev_dbg(codec
->dev
, "Configuring microphone detection on %d: %x %x\n",
3088 micbias
, det
, shrt
);
3090 /* Store the configuration */
3091 micdet
->jack
= jack
;
3093 micdet
->shrt
= shrt
;
3095 /* If either of the jacks is set up then enable detection */
3096 if (wm8994
->micdet
[0].jack
|| wm8994
->micdet
[1].jack
)
3097 reg
= WM8994_MICD_ENA
;
3101 snd_soc_update_bits(codec
, WM8994_MICBIAS
, WM8994_MICD_ENA
, reg
);
3105 EXPORT_SYMBOL_GPL(wm8994_mic_detect
);
3107 static irqreturn_t
wm8994_mic_irq(int irq
, void *data
)
3109 struct wm8994_priv
*priv
= data
;
3110 struct snd_soc_codec
*codec
= priv
->codec
;
3114 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3115 trace_snd_soc_jack_irq(dev_name(codec
->dev
));
3118 reg
= snd_soc_read(codec
, WM8994_INTERRUPT_RAW_STATUS_2
);
3120 dev_err(codec
->dev
, "Failed to read microphone status: %d\n",
3125 dev_dbg(codec
->dev
, "Microphone status: %x\n", reg
);
3128 if (reg
& WM8994_MIC1_DET_STS
)
3129 report
|= priv
->micdet
[0].det
;
3130 if (reg
& WM8994_MIC1_SHRT_STS
)
3131 report
|= priv
->micdet
[0].shrt
;
3132 snd_soc_jack_report(priv
->micdet
[0].jack
, report
,
3133 priv
->micdet
[0].det
| priv
->micdet
[0].shrt
);
3136 if (reg
& WM8994_MIC2_DET_STS
)
3137 report
|= priv
->micdet
[1].det
;
3138 if (reg
& WM8994_MIC2_SHRT_STS
)
3139 report
|= priv
->micdet
[1].shrt
;
3140 snd_soc_jack_report(priv
->micdet
[1].jack
, report
,
3141 priv
->micdet
[1].det
| priv
->micdet
[1].shrt
);
3146 /* Default microphone detection handler for WM8958 - the user can
3147 * override this if they wish.
3149 static void wm8958_default_micdet(u16 status
, void *data
)
3151 struct snd_soc_codec
*codec
= data
;
3152 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3155 dev_dbg(codec
->dev
, "MICDET %x\n", status
);
3157 /* Either nothing present or just starting detection */
3158 if (!(status
& WM8958_MICD_STS
)) {
3159 if (!wm8994
->jackdet
) {
3160 /* If nothing present then clear our statuses */
3161 dev_dbg(codec
->dev
, "Detected open circuit\n");
3162 wm8994
->jack_mic
= false;
3163 wm8994
->mic_detecting
= true;
3165 wm8958_micd_set_rate(codec
);
3167 snd_soc_jack_report(wm8994
->micdet
[0].jack
, 0,
3174 /* If the measurement is showing a high impedence we've got a
3177 if (wm8994
->mic_detecting
&& (status
& 0x600)) {
3178 dev_dbg(codec
->dev
, "Detected microphone\n");
3180 wm8994
->mic_detecting
= false;
3181 wm8994
->jack_mic
= true;
3183 wm8958_micd_set_rate(codec
);
3185 snd_soc_jack_report(wm8994
->micdet
[0].jack
, SND_JACK_HEADSET
,
3190 if (wm8994
->mic_detecting
&& status
& 0x4) {
3191 dev_dbg(codec
->dev
, "Detected headphone\n");
3192 wm8994
->mic_detecting
= false;
3194 wm8958_micd_set_rate(codec
);
3196 snd_soc_jack_report(wm8994
->micdet
[0].jack
, SND_JACK_HEADPHONE
,
3199 /* If we have jackdet that will detect removal */
3200 if (wm8994
->jackdet
) {
3201 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3202 WM8958_MICD_ENA
, 0);
3204 wm1811_jackdet_set_mode(codec
,
3205 WM1811_JACKDET_MODE_JACK
);
3209 /* Report short circuit as a button */
3210 if (wm8994
->jack_mic
) {
3213 report
|= SND_JACK_BTN_0
;
3216 report
|= SND_JACK_BTN_1
;
3219 report
|= SND_JACK_BTN_2
;
3222 report
|= SND_JACK_BTN_3
;
3225 report
|= SND_JACK_BTN_4
;
3228 report
|= SND_JACK_BTN_5
;
3230 snd_soc_jack_report(wm8994
->micdet
[0].jack
, report
,
3235 static irqreturn_t
wm1811_jackdet_irq(int irq
, void *data
)
3237 struct wm8994_priv
*wm8994
= data
;
3238 struct snd_soc_codec
*codec
= wm8994
->codec
;
3241 mutex_lock(&wm8994
->accdet_lock
);
3243 reg
= snd_soc_read(codec
, WM1811_JACKDET_CTRL
);
3245 dev_err(codec
->dev
, "Failed to read jack status: %d\n", reg
);
3246 mutex_unlock(&wm8994
->accdet_lock
);
3250 dev_dbg(codec
->dev
, "JACKDET %x\n", reg
);
3252 if (reg
& WM1811_JACKDET_LVL
) {
3253 dev_dbg(codec
->dev
, "Jack detected\n");
3255 snd_soc_jack_report(wm8994
->micdet
[0].jack
,
3256 SND_JACK_MECHANICAL
, SND_JACK_MECHANICAL
);
3259 * Start off measument of microphone impedence to find
3260 * out what's actually there.
3262 wm8994
->mic_detecting
= true;
3263 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_MIC
);
3264 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3265 WM8958_MICD_ENA
, WM8958_MICD_ENA
);
3267 dev_dbg(codec
->dev
, "Jack not detected\n");
3269 snd_soc_jack_report(wm8994
->micdet
[0].jack
, 0,
3270 SND_JACK_MECHANICAL
| SND_JACK_HEADSET
|
3273 wm8994
->mic_detecting
= false;
3274 wm8994
->jack_mic
= false;
3275 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3276 WM8958_MICD_ENA
, 0);
3277 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_JACK
);
3280 mutex_unlock(&wm8994
->accdet_lock
);
3286 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3288 * @codec: WM8958 codec
3289 * @jack: jack to report detection events on
3291 * Enable microphone detection functionality for the WM8958. By
3292 * default simple detection which supports the detection of up to 6
3293 * buttons plus video and microphone functionality is supported.
3295 * The WM8958 has an advanced jack detection facility which is able to
3296 * support complex accessory detection, especially when used in
3297 * conjunction with external circuitry. In order to provide maximum
3298 * flexiblity a callback is provided which allows a completely custom
3299 * detection algorithm.
3301 int wm8958_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
3302 wm8958_micdet_cb cb
, void *cb_data
)
3304 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3305 struct wm8994
*control
= wm8994
->wm8994
;
3308 switch (control
->type
) {
3318 dev_dbg(codec
->dev
, "Using default micdet callback\n");
3319 cb
= wm8958_default_micdet
;
3323 snd_soc_dapm_force_enable_pin(&codec
->dapm
, "CLK_SYS");
3325 wm8994
->micdet
[0].jack
= jack
;
3326 wm8994
->jack_cb
= cb
;
3327 wm8994
->jack_cb_data
= cb_data
;
3329 wm8994
->mic_detecting
= true;
3330 wm8994
->jack_mic
= false;
3332 wm8958_micd_set_rate(codec
);
3334 /* Detect microphones and short circuits by default */
3335 if (wm8994
->pdata
->micd_lvl_sel
)
3336 micd_lvl_sel
= wm8994
->pdata
->micd_lvl_sel
;
3338 micd_lvl_sel
= 0x41;
3340 wm8994
->btn_mask
= SND_JACK_BTN_0
| SND_JACK_BTN_1
|
3341 SND_JACK_BTN_2
| SND_JACK_BTN_3
|
3342 SND_JACK_BTN_4
| SND_JACK_BTN_5
;
3344 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_2
,
3345 WM8958_MICD_LVL_SEL_MASK
, micd_lvl_sel
);
3347 WARN_ON(codec
->dapm
.bias_level
> SND_SOC_BIAS_STANDBY
);
3350 * If we can use jack detection start off with that,
3351 * otherwise jump straight to microphone detection.
3353 if (wm8994
->jackdet
) {
3354 snd_soc_update_bits(codec
, WM8994_LDO_1
,
3355 WM8994_LDO1_DISCH
, 0);
3356 wm1811_jackdet_set_mode(codec
,
3357 WM1811_JACKDET_MODE_JACK
);
3359 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3360 WM8958_MICD_ENA
, WM8958_MICD_ENA
);
3364 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3365 WM8958_MICD_ENA
, 0);
3366 snd_soc_dapm_disable_pin(&codec
->dapm
, "CLK_SYS");
3371 EXPORT_SYMBOL_GPL(wm8958_mic_detect
);
3373 static irqreturn_t
wm8958_mic_irq(int irq
, void *data
)
3375 struct wm8994_priv
*wm8994
= data
;
3376 struct snd_soc_codec
*codec
= wm8994
->codec
;
3379 mutex_lock(&wm8994
->accdet_lock
);
3382 * Jack detection may have detected a removal simulataneously
3383 * with an update of the MICDET status; if so it will have
3384 * stopped detection and we can ignore this interrupt.
3386 if (!(snd_soc_read(codec
, WM8958_MIC_DETECT_1
) & WM8958_MICD_ENA
)) {
3387 mutex_unlock(&wm8994
->accdet_lock
);
3391 /* We may occasionally read a detection without an impedence
3392 * range being provided - if that happens loop again.
3396 reg
= snd_soc_read(codec
, WM8958_MIC_DETECT_3
);
3398 mutex_unlock(&wm8994
->accdet_lock
);
3400 "Failed to read mic detect status: %d\n",
3405 if (!(reg
& WM8958_MICD_VALID
)) {
3406 dev_dbg(codec
->dev
, "Mic detect data not valid\n");
3410 if (!(reg
& WM8958_MICD_STS
) || (reg
& WM8958_MICD_LVL_MASK
))
3417 dev_warn(codec
->dev
, "No impedence range reported for jack\n");
3419 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3420 trace_snd_soc_jack_irq(dev_name(codec
->dev
));
3423 if (wm8994
->jack_cb
)
3424 wm8994
->jack_cb(reg
, wm8994
->jack_cb_data
);
3426 dev_warn(codec
->dev
, "Accessory detection with no callback\n");
3429 mutex_unlock(&wm8994
->accdet_lock
);
3434 static irqreturn_t
wm8994_fifo_error(int irq
, void *data
)
3436 struct snd_soc_codec
*codec
= data
;
3438 dev_err(codec
->dev
, "FIFO error\n");
3443 static irqreturn_t
wm8994_temp_warn(int irq
, void *data
)
3445 struct snd_soc_codec
*codec
= data
;
3447 dev_err(codec
->dev
, "Thermal warning\n");
3452 static irqreturn_t
wm8994_temp_shut(int irq
, void *data
)
3454 struct snd_soc_codec
*codec
= data
;
3456 dev_crit(codec
->dev
, "Thermal shutdown\n");
3461 static int wm8994_codec_probe(struct snd_soc_codec
*codec
)
3463 struct wm8994
*control
;
3464 struct wm8994_priv
*wm8994
;
3465 struct snd_soc_dapm_context
*dapm
= &codec
->dapm
;
3468 codec
->control_data
= dev_get_drvdata(codec
->dev
->parent
);
3469 control
= codec
->control_data
;
3471 wm8994
= devm_kzalloc(codec
->dev
, sizeof(struct wm8994_priv
),
3475 snd_soc_codec_set_drvdata(codec
, wm8994
);
3478 wm8994
->wm8994
= dev_get_drvdata(codec
->dev
->parent
);
3479 wm8994
->pdata
= dev_get_platdata(codec
->dev
->parent
);
3480 wm8994
->codec
= codec
;
3482 mutex_init(&wm8994
->accdet_lock
);
3484 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++)
3485 init_completion(&wm8994
->fll_locked
[i
]);
3487 if (wm8994
->pdata
&& wm8994
->pdata
->micdet_irq
)
3488 wm8994
->micdet_irq
= wm8994
->pdata
->micdet_irq
;
3489 else if (wm8994
->pdata
&& wm8994
->pdata
->irq_base
)
3490 wm8994
->micdet_irq
= wm8994
->pdata
->irq_base
+
3491 WM8994_IRQ_MIC1_DET
;
3493 pm_runtime_enable(codec
->dev
);
3494 pm_runtime_resume(codec
->dev
);
3496 /* Read our current status back from the chip - we don't want to
3497 * reset as this may interfere with the GPIO or LDO operation. */
3498 for (i
= 0; i
< WM8994_CACHE_SIZE
; i
++) {
3499 if (!wm8994_readable(codec
, i
) || wm8994_volatile(codec
, i
))
3502 ret
= wm8994_reg_read(codec
->control_data
, i
);
3506 ret
= snd_soc_cache_write(codec
, i
, ret
);
3509 "Failed to initialise cache for 0x%x: %d\n",
3515 /* Set revision-specific configuration */
3516 wm8994
->revision
= snd_soc_read(codec
, WM8994_CHIP_REVISION
);
3517 switch (control
->type
) {
3519 switch (wm8994
->revision
) {
3522 wm8994
->hubs
.dcs_codes_l
= -5;
3523 wm8994
->hubs
.dcs_codes_r
= -5;
3524 wm8994
->hubs
.hp_startup_mode
= 1;
3525 wm8994
->hubs
.dcs_readback_mode
= 1;
3526 wm8994
->hubs
.series_startup
= 1;
3529 wm8994
->hubs
.dcs_readback_mode
= 2;
3535 wm8994
->hubs
.dcs_readback_mode
= 1;
3539 wm8994
->hubs
.dcs_readback_mode
= 2;
3540 wm8994
->hubs
.no_series_update
= 1;
3542 switch (wm8994
->revision
) {
3547 wm8994
->hubs
.dcs_codes_l
= -9;
3548 wm8994
->hubs
.dcs_codes_r
= -5;
3554 snd_soc_update_bits(codec
, WM8994_ANALOGUE_HP_1
,
3555 WM1811_HPOUT1_ATTN
, WM1811_HPOUT1_ATTN
);
3562 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_FIFOS_ERR
,
3563 wm8994_fifo_error
, "FIFO error", codec
);
3564 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_WARN
,
3565 wm8994_temp_warn
, "Thermal warning", codec
);
3566 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_SHUT
,
3567 wm8994_temp_shut
, "Thermal shutdown", codec
);
3569 ret
= wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_DCS_DONE
,
3570 wm_hubs_dcs_done
, "DC servo done",
3573 wm8994
->hubs
.dcs_done_irq
= true;
3575 switch (control
->type
) {
3577 if (wm8994
->micdet_irq
) {
3578 ret
= request_threaded_irq(wm8994
->micdet_irq
, NULL
,
3580 IRQF_TRIGGER_RISING
,
3584 dev_warn(codec
->dev
,
3585 "Failed to request Mic1 detect IRQ: %d\n",
3589 ret
= wm8994_request_irq(wm8994
->wm8994
,
3590 WM8994_IRQ_MIC1_SHRT
,
3591 wm8994_mic_irq
, "Mic 1 short",
3594 dev_warn(codec
->dev
,
3595 "Failed to request Mic1 short IRQ: %d\n",
3598 ret
= wm8994_request_irq(wm8994
->wm8994
,
3599 WM8994_IRQ_MIC2_DET
,
3600 wm8994_mic_irq
, "Mic 2 detect",
3603 dev_warn(codec
->dev
,
3604 "Failed to request Mic2 detect IRQ: %d\n",
3607 ret
= wm8994_request_irq(wm8994
->wm8994
,
3608 WM8994_IRQ_MIC2_SHRT
,
3609 wm8994_mic_irq
, "Mic 2 short",
3612 dev_warn(codec
->dev
,
3613 "Failed to request Mic2 short IRQ: %d\n",
3619 if (wm8994
->micdet_irq
) {
3620 ret
= request_threaded_irq(wm8994
->micdet_irq
, NULL
,
3622 IRQF_TRIGGER_RISING
,
3626 dev_warn(codec
->dev
,
3627 "Failed to request Mic detect IRQ: %d\n",
3632 switch (control
->type
) {
3634 if (wm8994
->revision
> 1) {
3635 ret
= wm8994_request_irq(wm8994
->wm8994
,
3637 wm1811_jackdet_irq
, "JACKDET",
3640 wm8994
->jackdet
= true;
3647 wm8994
->fll_locked_irq
= true;
3648 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++) {
3649 ret
= wm8994_request_irq(wm8994
->wm8994
,
3650 WM8994_IRQ_FLL1_LOCK
+ i
,
3651 wm8994_fll_locked_irq
, "FLL lock",
3652 &wm8994
->fll_locked
[i
]);
3654 wm8994
->fll_locked_irq
= false;
3657 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3658 * configured on init - if a system wants to do this dynamically
3659 * at runtime we can deal with that then.
3661 ret
= wm8994_reg_read(codec
->control_data
, WM8994_GPIO_1
);
3663 dev_err(codec
->dev
, "Failed to read GPIO1 state: %d\n", ret
);
3666 if ((ret
& WM8994_GPN_FN_MASK
) != WM8994_GP_FN_PIN_SPECIFIC
) {
3667 wm8994
->lrclk_shared
[0] = 1;
3668 wm8994_dai
[0].symmetric_rates
= 1;
3670 wm8994
->lrclk_shared
[0] = 0;
3673 ret
= wm8994_reg_read(codec
->control_data
, WM8994_GPIO_6
);
3675 dev_err(codec
->dev
, "Failed to read GPIO6 state: %d\n", ret
);
3678 if ((ret
& WM8994_GPN_FN_MASK
) != WM8994_GP_FN_PIN_SPECIFIC
) {
3679 wm8994
->lrclk_shared
[1] = 1;
3680 wm8994_dai
[1].symmetric_rates
= 1;
3682 wm8994
->lrclk_shared
[1] = 0;
3685 wm8994_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
3687 /* Latch volume updates (right only; we always do left then right). */
3688 snd_soc_update_bits(codec
, WM8994_AIF1_DAC1_LEFT_VOLUME
,
3689 WM8994_AIF1DAC1_VU
, WM8994_AIF1DAC1_VU
);
3690 snd_soc_update_bits(codec
, WM8994_AIF1_DAC1_RIGHT_VOLUME
,
3691 WM8994_AIF1DAC1_VU
, WM8994_AIF1DAC1_VU
);
3692 snd_soc_update_bits(codec
, WM8994_AIF1_DAC2_LEFT_VOLUME
,
3693 WM8994_AIF1DAC2_VU
, WM8994_AIF1DAC2_VU
);
3694 snd_soc_update_bits(codec
, WM8994_AIF1_DAC2_RIGHT_VOLUME
,
3695 WM8994_AIF1DAC2_VU
, WM8994_AIF1DAC2_VU
);
3696 snd_soc_update_bits(codec
, WM8994_AIF2_DAC_LEFT_VOLUME
,
3697 WM8994_AIF2DAC_VU
, WM8994_AIF2DAC_VU
);
3698 snd_soc_update_bits(codec
, WM8994_AIF2_DAC_RIGHT_VOLUME
,
3699 WM8994_AIF2DAC_VU
, WM8994_AIF2DAC_VU
);
3700 snd_soc_update_bits(codec
, WM8994_AIF1_ADC1_LEFT_VOLUME
,
3701 WM8994_AIF1ADC1_VU
, WM8994_AIF1ADC1_VU
);
3702 snd_soc_update_bits(codec
, WM8994_AIF1_ADC1_RIGHT_VOLUME
,
3703 WM8994_AIF1ADC1_VU
, WM8994_AIF1ADC1_VU
);
3704 snd_soc_update_bits(codec
, WM8994_AIF1_ADC2_LEFT_VOLUME
,
3705 WM8994_AIF1ADC2_VU
, WM8994_AIF1ADC2_VU
);
3706 snd_soc_update_bits(codec
, WM8994_AIF1_ADC2_RIGHT_VOLUME
,
3707 WM8994_AIF1ADC2_VU
, WM8994_AIF1ADC2_VU
);
3708 snd_soc_update_bits(codec
, WM8994_AIF2_ADC_LEFT_VOLUME
,
3709 WM8994_AIF2ADC_VU
, WM8994_AIF1ADC2_VU
);
3710 snd_soc_update_bits(codec
, WM8994_AIF2_ADC_RIGHT_VOLUME
,
3711 WM8994_AIF2ADC_VU
, WM8994_AIF1ADC2_VU
);
3712 snd_soc_update_bits(codec
, WM8994_DAC1_LEFT_VOLUME
,
3713 WM8994_DAC1_VU
, WM8994_DAC1_VU
);
3714 snd_soc_update_bits(codec
, WM8994_DAC1_RIGHT_VOLUME
,
3715 WM8994_DAC1_VU
, WM8994_DAC1_VU
);
3716 snd_soc_update_bits(codec
, WM8994_DAC2_LEFT_VOLUME
,
3717 WM8994_DAC2_VU
, WM8994_DAC2_VU
);
3718 snd_soc_update_bits(codec
, WM8994_DAC2_RIGHT_VOLUME
,
3719 WM8994_DAC2_VU
, WM8994_DAC2_VU
);
3721 /* Set the low bit of the 3D stereo depth so TLV matches */
3722 snd_soc_update_bits(codec
, WM8994_AIF1_DAC1_FILTERS_2
,
3723 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT
,
3724 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT
);
3725 snd_soc_update_bits(codec
, WM8994_AIF1_DAC2_FILTERS_2
,
3726 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT
,
3727 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT
);
3728 snd_soc_update_bits(codec
, WM8994_AIF2_DAC_FILTERS_2
,
3729 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT
,
3730 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT
);
3732 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3733 * use this; it only affects behaviour on idle TDM clock
3735 switch (control
->type
) {
3738 snd_soc_update_bits(codec
, WM8994_AIF1_CONTROL_1
,
3739 WM8994_AIF1ADC_TDM
, WM8994_AIF1ADC_TDM
);
3745 /* Put MICBIAS into bypass mode by default on newer devices */
3746 switch (control
->type
) {
3749 snd_soc_update_bits(codec
, WM8958_MICBIAS1
,
3750 WM8958_MICB1_MODE
, WM8958_MICB1_MODE
);
3751 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
3752 WM8958_MICB2_MODE
, WM8958_MICB2_MODE
);
3758 wm8994_update_class_w(codec
);
3760 wm8994_handle_pdata(wm8994
);
3762 wm_hubs_add_analogue_controls(codec
);
3763 snd_soc_add_controls(codec
, wm8994_snd_controls
,
3764 ARRAY_SIZE(wm8994_snd_controls
));
3765 snd_soc_dapm_new_controls(dapm
, wm8994_dapm_widgets
,
3766 ARRAY_SIZE(wm8994_dapm_widgets
));
3768 switch (control
->type
) {
3770 snd_soc_dapm_new_controls(dapm
, wm8994_specific_dapm_widgets
,
3771 ARRAY_SIZE(wm8994_specific_dapm_widgets
));
3772 if (wm8994
->revision
< 4) {
3773 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_revd_widgets
,
3774 ARRAY_SIZE(wm8994_lateclk_revd_widgets
));
3775 snd_soc_dapm_new_controls(dapm
, wm8994_adc_revd_widgets
,
3776 ARRAY_SIZE(wm8994_adc_revd_widgets
));
3777 snd_soc_dapm_new_controls(dapm
, wm8994_dac_revd_widgets
,
3778 ARRAY_SIZE(wm8994_dac_revd_widgets
));
3780 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_widgets
,
3781 ARRAY_SIZE(wm8994_lateclk_widgets
));
3782 snd_soc_dapm_new_controls(dapm
, wm8994_adc_widgets
,
3783 ARRAY_SIZE(wm8994_adc_widgets
));
3784 snd_soc_dapm_new_controls(dapm
, wm8994_dac_widgets
,
3785 ARRAY_SIZE(wm8994_dac_widgets
));
3789 snd_soc_add_controls(codec
, wm8958_snd_controls
,
3790 ARRAY_SIZE(wm8958_snd_controls
));
3791 snd_soc_dapm_new_controls(dapm
, wm8958_dapm_widgets
,
3792 ARRAY_SIZE(wm8958_dapm_widgets
));
3793 if (wm8994
->revision
< 1) {
3794 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_revd_widgets
,
3795 ARRAY_SIZE(wm8994_lateclk_revd_widgets
));
3796 snd_soc_dapm_new_controls(dapm
, wm8994_adc_revd_widgets
,
3797 ARRAY_SIZE(wm8994_adc_revd_widgets
));
3798 snd_soc_dapm_new_controls(dapm
, wm8994_dac_revd_widgets
,
3799 ARRAY_SIZE(wm8994_dac_revd_widgets
));
3801 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_widgets
,
3802 ARRAY_SIZE(wm8994_lateclk_widgets
));
3803 snd_soc_dapm_new_controls(dapm
, wm8994_adc_widgets
,
3804 ARRAY_SIZE(wm8994_adc_widgets
));
3805 snd_soc_dapm_new_controls(dapm
, wm8994_dac_widgets
,
3806 ARRAY_SIZE(wm8994_dac_widgets
));
3811 snd_soc_add_controls(codec
, wm8958_snd_controls
,
3812 ARRAY_SIZE(wm8958_snd_controls
));
3813 snd_soc_dapm_new_controls(dapm
, wm8958_dapm_widgets
,
3814 ARRAY_SIZE(wm8958_dapm_widgets
));
3815 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_widgets
,
3816 ARRAY_SIZE(wm8994_lateclk_widgets
));
3817 snd_soc_dapm_new_controls(dapm
, wm8994_adc_widgets
,
3818 ARRAY_SIZE(wm8994_adc_widgets
));
3819 snd_soc_dapm_new_controls(dapm
, wm8994_dac_widgets
,
3820 ARRAY_SIZE(wm8994_dac_widgets
));
3825 wm_hubs_add_analogue_routes(codec
, 0, 0);
3826 snd_soc_dapm_add_routes(dapm
, intercon
, ARRAY_SIZE(intercon
));
3828 switch (control
->type
) {
3830 snd_soc_dapm_add_routes(dapm
, wm8994_intercon
,
3831 ARRAY_SIZE(wm8994_intercon
));
3833 if (wm8994
->revision
< 4) {
3834 snd_soc_dapm_add_routes(dapm
, wm8994_revd_intercon
,
3835 ARRAY_SIZE(wm8994_revd_intercon
));
3836 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_revd_intercon
,
3837 ARRAY_SIZE(wm8994_lateclk_revd_intercon
));
3839 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_intercon
,
3840 ARRAY_SIZE(wm8994_lateclk_intercon
));
3844 if (wm8994
->revision
< 1) {
3845 snd_soc_dapm_add_routes(dapm
, wm8994_revd_intercon
,
3846 ARRAY_SIZE(wm8994_revd_intercon
));
3847 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_revd_intercon
,
3848 ARRAY_SIZE(wm8994_lateclk_revd_intercon
));
3850 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_intercon
,
3851 ARRAY_SIZE(wm8994_lateclk_intercon
));
3852 snd_soc_dapm_add_routes(dapm
, wm8958_intercon
,
3853 ARRAY_SIZE(wm8958_intercon
));
3856 wm8958_dsp2_init(codec
);
3859 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_intercon
,
3860 ARRAY_SIZE(wm8994_lateclk_intercon
));
3861 snd_soc_dapm_add_routes(dapm
, wm8958_intercon
,
3862 ARRAY_SIZE(wm8958_intercon
));
3869 if (wm8994
->jackdet
)
3870 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_GPIO(6), wm8994
);
3871 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC2_SHRT
, wm8994
);
3872 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC2_DET
, wm8994
);
3873 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_SHRT
, wm8994
);
3874 if (wm8994
->micdet_irq
)
3875 free_irq(wm8994
->micdet_irq
, wm8994
);
3876 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++)
3877 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FLL1_LOCK
+ i
,
3878 &wm8994
->fll_locked
[i
]);
3879 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_DCS_DONE
,
3881 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FIFOS_ERR
, codec
);
3882 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_SHUT
, codec
);
3883 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_WARN
, codec
);
3888 static int wm8994_codec_remove(struct snd_soc_codec
*codec
)
3890 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3891 struct wm8994
*control
= wm8994
->wm8994
;
3894 wm8994_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
3896 pm_runtime_disable(codec
->dev
);
3898 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++)
3899 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FLL1_LOCK
+ i
,
3900 &wm8994
->fll_locked
[i
]);
3902 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_DCS_DONE
,
3904 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FIFOS_ERR
, codec
);
3905 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_SHUT
, codec
);
3906 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_WARN
, codec
);
3908 if (wm8994
->jackdet
)
3909 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_GPIO(6), wm8994
);
3911 switch (control
->type
) {
3913 if (wm8994
->micdet_irq
)
3914 free_irq(wm8994
->micdet_irq
, wm8994
);
3915 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC2_DET
,
3917 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_SHRT
,
3919 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_DET
,
3925 if (wm8994
->micdet_irq
)
3926 free_irq(wm8994
->micdet_irq
, wm8994
);
3930 release_firmware(wm8994
->mbc
);
3931 if (wm8994
->mbc_vss
)
3932 release_firmware(wm8994
->mbc_vss
);
3934 release_firmware(wm8994
->enh_eq
);
3935 kfree(wm8994
->retune_mobile_texts
);
3940 static struct snd_soc_codec_driver soc_codec_dev_wm8994
= {
3941 .probe
= wm8994_codec_probe
,
3942 .remove
= wm8994_codec_remove
,
3943 .suspend
= wm8994_suspend
,
3944 .resume
= wm8994_resume
,
3945 .read
= wm8994_read
,
3946 .write
= wm8994_write
,
3947 .readable_register
= wm8994_readable
,
3948 .volatile_register
= wm8994_volatile
,
3949 .set_bias_level
= wm8994_set_bias_level
,
3951 .reg_cache_size
= WM8994_CACHE_SIZE
,
3952 .reg_cache_default
= wm8994_reg_defaults
,
3954 .compress_type
= SND_SOC_RBTREE_COMPRESSION
,
3957 static int __devinit
wm8994_probe(struct platform_device
*pdev
)
3959 return snd_soc_register_codec(&pdev
->dev
, &soc_codec_dev_wm8994
,
3960 wm8994_dai
, ARRAY_SIZE(wm8994_dai
));
3963 static int __devexit
wm8994_remove(struct platform_device
*pdev
)
3965 snd_soc_unregister_codec(&pdev
->dev
);
3969 static struct platform_driver wm8994_codec_driver
= {
3971 .name
= "wm8994-codec",
3972 .owner
= THIS_MODULE
,
3974 .probe
= wm8994_probe
,
3975 .remove
= __devexit_p(wm8994_remove
),
3978 module_platform_driver(wm8994_codec_driver
);
3980 MODULE_DESCRIPTION("ASoC WM8994 driver");
3981 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3982 MODULE_LICENSE("GPL");
3983 MODULE_ALIAS("platform:wm8994-codec");