2 * wm8994.c -- WM8994 ALSA SoC Audio driver
4 * Copyright 2009-12 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
19 #include <linux/gcd.h>
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/slab.h>
25 #include <sound/core.h>
26 #include <sound/jack.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
32 #include <trace/events/asoc.h>
34 #include <linux/mfd/wm8994/core.h>
35 #include <linux/mfd/wm8994/registers.h>
36 #include <linux/mfd/wm8994/pdata.h>
37 #include <linux/mfd/wm8994/gpio.h>
42 #define WM1811_JACKDET_MODE_NONE 0x0000
43 #define WM1811_JACKDET_MODE_JACK 0x0100
44 #define WM1811_JACKDET_MODE_MIC 0x0080
45 #define WM1811_JACKDET_MODE_AUDIO 0x0180
47 #define WM8994_NUM_DRC 3
48 #define WM8994_NUM_EQ 3
53 } wm8994_vu_bits
[] = {
54 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME
, WM8994_IN1_VU
},
55 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME
, WM8994_IN1_VU
},
56 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME
, WM8994_IN2_VU
},
57 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME
, WM8994_IN2_VU
},
58 { WM8994_SPEAKER_VOLUME_LEFT
, WM8994_SPKOUT_VU
},
59 { WM8994_SPEAKER_VOLUME_RIGHT
, WM8994_SPKOUT_VU
},
60 { WM8994_LEFT_OUTPUT_VOLUME
, WM8994_HPOUT1_VU
},
61 { WM8994_RIGHT_OUTPUT_VOLUME
, WM8994_HPOUT1_VU
},
62 { WM8994_LEFT_OPGA_VOLUME
, WM8994_MIXOUT_VU
},
63 { WM8994_RIGHT_OPGA_VOLUME
, WM8994_MIXOUT_VU
},
65 { WM8994_AIF1_DAC1_LEFT_VOLUME
, WM8994_AIF1DAC1_VU
},
66 { WM8994_AIF1_DAC1_RIGHT_VOLUME
, WM8994_AIF1DAC1_VU
},
67 { WM8994_AIF1_DAC2_LEFT_VOLUME
, WM8994_AIF1DAC2_VU
},
68 { WM8994_AIF1_DAC2_RIGHT_VOLUME
, WM8994_AIF1DAC2_VU
},
69 { WM8994_AIF2_DAC_LEFT_VOLUME
, WM8994_AIF2DAC_VU
},
70 { WM8994_AIF2_DAC_RIGHT_VOLUME
, WM8994_AIF2DAC_VU
},
71 { WM8994_AIF1_ADC1_LEFT_VOLUME
, WM8994_AIF1ADC1_VU
},
72 { WM8994_AIF1_ADC1_RIGHT_VOLUME
, WM8994_AIF1ADC1_VU
},
73 { WM8994_AIF1_ADC2_LEFT_VOLUME
, WM8994_AIF1ADC2_VU
},
74 { WM8994_AIF1_ADC2_RIGHT_VOLUME
, WM8994_AIF1ADC2_VU
},
75 { WM8994_AIF2_ADC_LEFT_VOLUME
, WM8994_AIF2ADC_VU
},
76 { WM8994_AIF2_ADC_RIGHT_VOLUME
, WM8994_AIF1ADC2_VU
},
77 { WM8994_DAC1_LEFT_VOLUME
, WM8994_DAC1_VU
},
78 { WM8994_DAC1_RIGHT_VOLUME
, WM8994_DAC1_VU
},
79 { WM8994_DAC2_LEFT_VOLUME
, WM8994_DAC2_VU
},
80 { WM8994_DAC2_RIGHT_VOLUME
, WM8994_DAC2_VU
},
83 static int wm8994_drc_base
[] = {
89 static int wm8994_retune_mobile_base
[] = {
90 WM8994_AIF1_DAC1_EQ_GAINS_1
,
91 WM8994_AIF1_DAC2_EQ_GAINS_1
,
92 WM8994_AIF2_EQ_GAINS_1
,
95 static const struct wm8958_micd_rate micdet_rates
[] = {
96 { 32768, true, 1, 4 },
97 { 32768, false, 1, 1 },
98 { 44100 * 256, true, 7, 10 },
99 { 44100 * 256, false, 7, 10 },
102 static const struct wm8958_micd_rate jackdet_rates
[] = {
103 { 32768, true, 0, 1 },
104 { 32768, false, 0, 1 },
105 { 44100 * 256, true, 10, 10 },
106 { 44100 * 256, false, 7, 8 },
109 static void wm8958_micd_set_rate(struct snd_soc_codec
*codec
)
111 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
112 struct wm8994
*control
= wm8994
->wm8994
;
113 int best
, i
, sysclk
, val
;
115 const struct wm8958_micd_rate
*rates
;
118 idle
= !wm8994
->jack_mic
;
120 sysclk
= snd_soc_read(codec
, WM8994_CLOCKING_1
);
121 if (sysclk
& WM8994_SYSCLK_SRC
)
122 sysclk
= wm8994
->aifclk
[1];
124 sysclk
= wm8994
->aifclk
[0];
126 if (control
->pdata
.micd_rates
) {
127 rates
= control
->pdata
.micd_rates
;
128 num_rates
= control
->pdata
.num_micd_rates
;
129 } else if (wm8994
->jackdet
) {
130 rates
= jackdet_rates
;
131 num_rates
= ARRAY_SIZE(jackdet_rates
);
133 rates
= micdet_rates
;
134 num_rates
= ARRAY_SIZE(micdet_rates
);
138 for (i
= 0; i
< num_rates
; i
++) {
139 if (rates
[i
].idle
!= idle
)
141 if (abs(rates
[i
].sysclk
- sysclk
) <
142 abs(rates
[best
].sysclk
- sysclk
))
144 else if (rates
[best
].idle
!= idle
)
148 val
= rates
[best
].start
<< WM8958_MICD_BIAS_STARTTIME_SHIFT
149 | rates
[best
].rate
<< WM8958_MICD_RATE_SHIFT
;
151 dev_dbg(codec
->dev
, "MICD rate %d,%d for %dHz %s\n",
152 rates
[best
].start
, rates
[best
].rate
, sysclk
,
153 idle
? "idle" : "active");
155 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
156 WM8958_MICD_BIAS_STARTTIME_MASK
|
157 WM8958_MICD_RATE_MASK
, val
);
160 static int configure_aif_clock(struct snd_soc_codec
*codec
, int aif
)
162 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
172 switch (wm8994
->sysclk
[aif
]) {
173 case WM8994_SYSCLK_MCLK1
:
174 rate
= wm8994
->mclk
[0];
177 case WM8994_SYSCLK_MCLK2
:
179 rate
= wm8994
->mclk
[1];
182 case WM8994_SYSCLK_FLL1
:
184 rate
= wm8994
->fll
[0].out
;
187 case WM8994_SYSCLK_FLL2
:
189 rate
= wm8994
->fll
[1].out
;
196 if (rate
>= 13500000) {
198 reg1
|= WM8994_AIF1CLK_DIV
;
200 dev_dbg(codec
->dev
, "Dividing AIF%d clock to %dHz\n",
204 wm8994
->aifclk
[aif
] = rate
;
206 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
+ offset
,
207 WM8994_AIF1CLK_SRC_MASK
| WM8994_AIF1CLK_DIV
,
213 static int configure_clock(struct snd_soc_codec
*codec
)
215 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
218 /* Bring up the AIF clocks first */
219 configure_aif_clock(codec
, 0);
220 configure_aif_clock(codec
, 1);
222 /* Then switch CLK_SYS over to the higher of them; a change
223 * can only happen as a result of a clocking change which can
224 * only be made outside of DAPM so we can safely redo the
228 /* If they're equal it doesn't matter which is used */
229 if (wm8994
->aifclk
[0] == wm8994
->aifclk
[1]) {
230 wm8958_micd_set_rate(codec
);
234 if (wm8994
->aifclk
[0] < wm8994
->aifclk
[1])
235 new = WM8994_SYSCLK_SRC
;
239 change
= snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
240 WM8994_SYSCLK_SRC
, new);
242 snd_soc_dapm_sync(&codec
->dapm
);
244 wm8958_micd_set_rate(codec
);
249 static int check_clk_sys(struct snd_soc_dapm_widget
*source
,
250 struct snd_soc_dapm_widget
*sink
)
252 int reg
= snd_soc_read(source
->codec
, WM8994_CLOCKING_1
);
255 /* Check what we're currently using for CLK_SYS */
256 if (reg
& WM8994_SYSCLK_SRC
)
261 return strcmp(source
->name
, clk
) == 0;
264 static const char *sidetone_hpf_text
[] = {
265 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
268 static const struct soc_enum sidetone_hpf
=
269 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 7, 7, sidetone_hpf_text
);
271 static const char *adc_hpf_text
[] = {
272 "HiFi", "Voice 1", "Voice 2", "Voice 3"
275 static const struct soc_enum aif1adc1_hpf
=
276 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS
, 13, 4, adc_hpf_text
);
278 static const struct soc_enum aif1adc2_hpf
=
279 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS
, 13, 4, adc_hpf_text
);
281 static const struct soc_enum aif2adc_hpf
=
282 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS
, 13, 4, adc_hpf_text
);
284 static const DECLARE_TLV_DB_SCALE(aif_tlv
, 0, 600, 0);
285 static const DECLARE_TLV_DB_SCALE(digital_tlv
, -7200, 75, 1);
286 static const DECLARE_TLV_DB_SCALE(st_tlv
, -3600, 300, 0);
287 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv
, -1600, 183, 0);
288 static const DECLARE_TLV_DB_SCALE(eq_tlv
, -1200, 100, 0);
289 static const DECLARE_TLV_DB_SCALE(ng_tlv
, -10200, 600, 0);
290 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv
, 0, 900, 0);
292 #define WM8994_DRC_SWITCH(xname, reg, shift) \
293 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
294 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
295 .put = wm8994_put_drc_sw, \
296 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
298 static int wm8994_put_drc_sw(struct snd_kcontrol
*kcontrol
,
299 struct snd_ctl_elem_value
*ucontrol
)
301 struct soc_mixer_control
*mc
=
302 (struct soc_mixer_control
*)kcontrol
->private_value
;
303 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
306 /* Can't enable both ADC and DAC paths simultaneously */
307 if (mc
->shift
== WM8994_AIF1DAC1_DRC_ENA_SHIFT
)
308 mask
= WM8994_AIF1ADC1L_DRC_ENA_MASK
|
309 WM8994_AIF1ADC1R_DRC_ENA_MASK
;
311 mask
= WM8994_AIF1DAC1_DRC_ENA_MASK
;
313 ret
= snd_soc_read(codec
, mc
->reg
);
319 return snd_soc_put_volsw(kcontrol
, ucontrol
);
322 static void wm8994_set_drc(struct snd_soc_codec
*codec
, int drc
)
324 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
325 struct wm8994
*control
= wm8994
->wm8994
;
326 struct wm8994_pdata
*pdata
= &control
->pdata
;
327 int base
= wm8994_drc_base
[drc
];
328 int cfg
= wm8994
->drc_cfg
[drc
];
331 /* Save any enables; the configuration should clear them. */
332 save
= snd_soc_read(codec
, base
);
333 save
&= WM8994_AIF1DAC1_DRC_ENA
| WM8994_AIF1ADC1L_DRC_ENA
|
334 WM8994_AIF1ADC1R_DRC_ENA
;
336 for (i
= 0; i
< WM8994_DRC_REGS
; i
++)
337 snd_soc_update_bits(codec
, base
+ i
, 0xffff,
338 pdata
->drc_cfgs
[cfg
].regs
[i
]);
340 snd_soc_update_bits(codec
, base
, WM8994_AIF1DAC1_DRC_ENA
|
341 WM8994_AIF1ADC1L_DRC_ENA
|
342 WM8994_AIF1ADC1R_DRC_ENA
, save
);
345 /* Icky as hell but saves code duplication */
346 static int wm8994_get_drc(const char *name
)
348 if (strcmp(name
, "AIF1DRC1 Mode") == 0)
350 if (strcmp(name
, "AIF1DRC2 Mode") == 0)
352 if (strcmp(name
, "AIF2DRC Mode") == 0)
357 static int wm8994_put_drc_enum(struct snd_kcontrol
*kcontrol
,
358 struct snd_ctl_elem_value
*ucontrol
)
360 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
361 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
362 struct wm8994
*control
= wm8994
->wm8994
;
363 struct wm8994_pdata
*pdata
= &control
->pdata
;
364 int drc
= wm8994_get_drc(kcontrol
->id
.name
);
365 int value
= ucontrol
->value
.integer
.value
[0];
370 if (value
>= pdata
->num_drc_cfgs
)
373 wm8994
->drc_cfg
[drc
] = value
;
375 wm8994_set_drc(codec
, drc
);
380 static int wm8994_get_drc_enum(struct snd_kcontrol
*kcontrol
,
381 struct snd_ctl_elem_value
*ucontrol
)
383 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
384 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
385 int drc
= wm8994_get_drc(kcontrol
->id
.name
);
387 ucontrol
->value
.enumerated
.item
[0] = wm8994
->drc_cfg
[drc
];
392 static void wm8994_set_retune_mobile(struct snd_soc_codec
*codec
, int block
)
394 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
395 struct wm8994
*control
= wm8994
->wm8994
;
396 struct wm8994_pdata
*pdata
= &control
->pdata
;
397 int base
= wm8994_retune_mobile_base
[block
];
398 int iface
, best
, best_val
, save
, i
, cfg
;
400 if (!pdata
|| !wm8994
->num_retune_mobile_texts
)
415 /* Find the version of the currently selected configuration
416 * with the nearest sample rate. */
417 cfg
= wm8994
->retune_mobile_cfg
[block
];
420 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
421 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
422 wm8994
->retune_mobile_texts
[cfg
]) == 0 &&
423 abs(pdata
->retune_mobile_cfgs
[i
].rate
424 - wm8994
->dac_rates
[iface
]) < best_val
) {
426 best_val
= abs(pdata
->retune_mobile_cfgs
[i
].rate
427 - wm8994
->dac_rates
[iface
]);
431 dev_dbg(codec
->dev
, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
433 pdata
->retune_mobile_cfgs
[best
].name
,
434 pdata
->retune_mobile_cfgs
[best
].rate
,
435 wm8994
->dac_rates
[iface
]);
437 /* The EQ will be disabled while reconfiguring it, remember the
438 * current configuration.
440 save
= snd_soc_read(codec
, base
);
441 save
&= WM8994_AIF1DAC1_EQ_ENA
;
443 for (i
= 0; i
< WM8994_EQ_REGS
; i
++)
444 snd_soc_update_bits(codec
, base
+ i
, 0xffff,
445 pdata
->retune_mobile_cfgs
[best
].regs
[i
]);
447 snd_soc_update_bits(codec
, base
, WM8994_AIF1DAC1_EQ_ENA
, save
);
450 /* Icky as hell but saves code duplication */
451 static int wm8994_get_retune_mobile_block(const char *name
)
453 if (strcmp(name
, "AIF1.1 EQ Mode") == 0)
455 if (strcmp(name
, "AIF1.2 EQ Mode") == 0)
457 if (strcmp(name
, "AIF2 EQ Mode") == 0)
462 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
463 struct snd_ctl_elem_value
*ucontrol
)
465 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
466 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
467 struct wm8994
*control
= wm8994
->wm8994
;
468 struct wm8994_pdata
*pdata
= &control
->pdata
;
469 int block
= wm8994_get_retune_mobile_block(kcontrol
->id
.name
);
470 int value
= ucontrol
->value
.integer
.value
[0];
475 if (value
>= pdata
->num_retune_mobile_cfgs
)
478 wm8994
->retune_mobile_cfg
[block
] = value
;
480 wm8994_set_retune_mobile(codec
, block
);
485 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
486 struct snd_ctl_elem_value
*ucontrol
)
488 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
489 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
490 int block
= wm8994_get_retune_mobile_block(kcontrol
->id
.name
);
492 ucontrol
->value
.enumerated
.item
[0] = wm8994
->retune_mobile_cfg
[block
];
497 static const char *aif_chan_src_text
[] = {
501 static const struct soc_enum aif1adcl_src
=
502 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1
, 15, 2, aif_chan_src_text
);
504 static const struct soc_enum aif1adcr_src
=
505 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1
, 14, 2, aif_chan_src_text
);
507 static const struct soc_enum aif2adcl_src
=
508 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1
, 15, 2, aif_chan_src_text
);
510 static const struct soc_enum aif2adcr_src
=
511 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1
, 14, 2, aif_chan_src_text
);
513 static const struct soc_enum aif1dacl_src
=
514 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2
, 15, 2, aif_chan_src_text
);
516 static const struct soc_enum aif1dacr_src
=
517 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2
, 14, 2, aif_chan_src_text
);
519 static const struct soc_enum aif2dacl_src
=
520 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2
, 15, 2, aif_chan_src_text
);
522 static const struct soc_enum aif2dacr_src
=
523 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2
, 14, 2, aif_chan_src_text
);
525 static const char *osr_text
[] = {
526 "Low Power", "High Performance",
529 static const struct soc_enum dac_osr
=
530 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING
, 0, 2, osr_text
);
532 static const struct soc_enum adc_osr
=
533 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING
, 1, 2, osr_text
);
535 static const struct snd_kcontrol_new wm8994_snd_controls
[] = {
536 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME
,
537 WM8994_AIF1_ADC1_RIGHT_VOLUME
,
538 1, 119, 0, digital_tlv
),
539 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME
,
540 WM8994_AIF1_ADC2_RIGHT_VOLUME
,
541 1, 119, 0, digital_tlv
),
542 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME
,
543 WM8994_AIF2_ADC_RIGHT_VOLUME
,
544 1, 119, 0, digital_tlv
),
546 SOC_ENUM("AIF1ADCL Source", aif1adcl_src
),
547 SOC_ENUM("AIF1ADCR Source", aif1adcr_src
),
548 SOC_ENUM("AIF2ADCL Source", aif2adcl_src
),
549 SOC_ENUM("AIF2ADCR Source", aif2adcr_src
),
551 SOC_ENUM("AIF1DACL Source", aif1dacl_src
),
552 SOC_ENUM("AIF1DACR Source", aif1dacr_src
),
553 SOC_ENUM("AIF2DACL Source", aif2dacl_src
),
554 SOC_ENUM("AIF2DACR Source", aif2dacr_src
),
556 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME
,
557 WM8994_AIF1_DAC1_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
558 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME
,
559 WM8994_AIF1_DAC2_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
560 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME
,
561 WM8994_AIF2_DAC_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
563 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2
, 10, 3, 0, aif_tlv
),
564 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2
, 10, 3, 0, aif_tlv
),
566 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1
, 0, 1, 0),
567 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1
, 0, 1, 0),
568 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1
, 0, 1, 0),
570 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1
, 2),
571 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1
, 1),
572 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1
, 0),
574 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1
, 2),
575 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1
, 1),
576 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1
, 0),
578 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1
, 2),
579 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1
, 1),
580 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1
, 0),
582 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES
,
584 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES
,
586 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES
,
588 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES
,
590 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf
),
591 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE
, 6, 1, 0),
593 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf
),
594 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS
, 12, 11, 1, 0),
596 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf
),
597 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS
, 12, 11, 1, 0),
599 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf
),
600 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS
, 12, 11, 1, 0),
602 SOC_ENUM("ADC OSR", adc_osr
),
603 SOC_ENUM("DAC OSR", dac_osr
),
605 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME
,
606 WM8994_DAC1_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
607 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME
,
608 WM8994_DAC1_RIGHT_VOLUME
, 9, 1, 1),
610 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME
,
611 WM8994_DAC2_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
612 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME
,
613 WM8994_DAC2_RIGHT_VOLUME
, 9, 1, 1),
615 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION
,
616 6, 1, 1, wm_hubs_spkmix_tlv
),
617 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION
,
618 2, 1, 1, wm_hubs_spkmix_tlv
),
620 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION
,
621 6, 1, 1, wm_hubs_spkmix_tlv
),
622 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION
,
623 2, 1, 1, wm_hubs_spkmix_tlv
),
625 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2
,
626 10, 15, 0, wm8994_3d_tlv
),
627 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2
,
629 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2
,
630 10, 15, 0, wm8994_3d_tlv
),
631 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2
,
633 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2
,
634 10, 15, 0, wm8994_3d_tlv
),
635 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2
,
639 static const struct snd_kcontrol_new wm8994_eq_controls
[] = {
640 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 11, 31, 0,
642 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 6, 31, 0,
644 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 1, 31, 0,
646 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2
, 11, 31, 0,
648 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2
, 6, 31, 0,
651 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 11, 31, 0,
653 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 6, 31, 0,
655 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 1, 31, 0,
657 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2
, 11, 31, 0,
659 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2
, 6, 31, 0,
662 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1
, 11, 31, 0,
664 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1
, 6, 31, 0,
666 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1
, 1, 31, 0,
668 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2
, 11, 31, 0,
670 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2
, 6, 31, 0,
674 static const struct snd_kcontrol_new wm8994_drc_controls
[] = {
675 SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1
, 5,
676 WM8994_AIF1DAC1_DRC_ENA
| WM8994_AIF1ADC1L_DRC_ENA
|
677 WM8994_AIF1ADC1R_DRC_ENA
),
678 SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1
, 5,
679 WM8994_AIF1DAC2_DRC_ENA
| WM8994_AIF1ADC2L_DRC_ENA
|
680 WM8994_AIF1ADC2R_DRC_ENA
),
681 SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1
, 5,
682 WM8994_AIF2DAC_DRC_ENA
| WM8994_AIF2ADCL_DRC_ENA
|
683 WM8994_AIF2ADCR_DRC_ENA
),
686 static const char *wm8958_ng_text
[] = {
687 "30ms", "125ms", "250ms", "500ms",
690 static const struct soc_enum wm8958_aif1dac1_ng_hold
=
691 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE
,
692 WM8958_AIF1DAC1_NG_THR_SHIFT
, 4, wm8958_ng_text
);
694 static const struct soc_enum wm8958_aif1dac2_ng_hold
=
695 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE
,
696 WM8958_AIF1DAC2_NG_THR_SHIFT
, 4, wm8958_ng_text
);
698 static const struct soc_enum wm8958_aif2dac_ng_hold
=
699 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE
,
700 WM8958_AIF2DAC_NG_THR_SHIFT
, 4, wm8958_ng_text
);
702 static const struct snd_kcontrol_new wm8958_snd_controls
[] = {
703 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2
, 10, 3, 0, aif_tlv
),
705 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE
,
706 WM8958_AIF1DAC1_NG_ENA_SHIFT
, 1, 0),
707 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold
),
708 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
709 WM8958_AIF1_DAC1_NOISE_GATE
, WM8958_AIF1DAC1_NG_THR_SHIFT
,
712 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE
,
713 WM8958_AIF1DAC2_NG_ENA_SHIFT
, 1, 0),
714 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold
),
715 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
716 WM8958_AIF1_DAC2_NOISE_GATE
, WM8958_AIF1DAC2_NG_THR_SHIFT
,
719 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE
,
720 WM8958_AIF2DAC_NG_ENA_SHIFT
, 1, 0),
721 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold
),
722 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
723 WM8958_AIF2_DAC_NOISE_GATE
, WM8958_AIF2DAC_NG_THR_SHIFT
,
727 static const struct snd_kcontrol_new wm1811_snd_controls
[] = {
728 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1
, 7, 1, 0,
730 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1
, 8, 1, 0,
734 /* We run all mode setting through a function to enforce audio mode */
735 static void wm1811_jackdet_set_mode(struct snd_soc_codec
*codec
, u16 mode
)
737 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
739 if (!wm8994
->jackdet
|| !wm8994
->micdet
[0].jack
)
742 if (wm8994
->active_refcount
)
743 mode
= WM1811_JACKDET_MODE_AUDIO
;
745 if (mode
== wm8994
->jackdet_mode
)
748 wm8994
->jackdet_mode
= mode
;
750 /* Always use audio mode to detect while the system is active */
751 if (mode
!= WM1811_JACKDET_MODE_NONE
)
752 mode
= WM1811_JACKDET_MODE_AUDIO
;
754 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
755 WM1811_JACKDET_MODE_MASK
, mode
);
758 static void active_reference(struct snd_soc_codec
*codec
)
760 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
762 mutex_lock(&wm8994
->accdet_lock
);
764 wm8994
->active_refcount
++;
766 dev_dbg(codec
->dev
, "Active refcount incremented, now %d\n",
767 wm8994
->active_refcount
);
769 /* If we're using jack detection go into audio mode */
770 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_AUDIO
);
772 mutex_unlock(&wm8994
->accdet_lock
);
775 static void active_dereference(struct snd_soc_codec
*codec
)
777 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
780 mutex_lock(&wm8994
->accdet_lock
);
782 wm8994
->active_refcount
--;
784 dev_dbg(codec
->dev
, "Active refcount decremented, now %d\n",
785 wm8994
->active_refcount
);
787 if (wm8994
->active_refcount
== 0) {
788 /* Go into appropriate detection only mode */
789 if (wm8994
->jack_mic
|| wm8994
->mic_detecting
)
790 mode
= WM1811_JACKDET_MODE_MIC
;
792 mode
= WM1811_JACKDET_MODE_JACK
;
794 wm1811_jackdet_set_mode(codec
, mode
);
797 mutex_unlock(&wm8994
->accdet_lock
);
800 static int clk_sys_event(struct snd_soc_dapm_widget
*w
,
801 struct snd_kcontrol
*kcontrol
, int event
)
803 struct snd_soc_codec
*codec
= w
->codec
;
804 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
807 case SND_SOC_DAPM_PRE_PMU
:
808 return configure_clock(codec
);
810 case SND_SOC_DAPM_POST_PMU
:
812 * JACKDET won't run until we start the clock and it
813 * only reports deltas, make sure we notify the state
814 * up the stack on startup. Use a *very* generous
815 * timeout for paranoia, there's no urgency and we
816 * don't want false reports.
818 if (wm8994
->jackdet
&& !wm8994
->clk_has_run
) {
819 schedule_delayed_work(&wm8994
->jackdet_bootstrap
,
820 msecs_to_jiffies(1000));
821 wm8994
->clk_has_run
= true;
825 case SND_SOC_DAPM_POST_PMD
:
826 configure_clock(codec
);
833 static void vmid_reference(struct snd_soc_codec
*codec
)
835 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
837 pm_runtime_get_sync(codec
->dev
);
839 wm8994
->vmid_refcount
++;
841 dev_dbg(codec
->dev
, "Referencing VMID, refcount is now %d\n",
842 wm8994
->vmid_refcount
);
844 if (wm8994
->vmid_refcount
== 1) {
845 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
846 WM8994_LINEOUT1_DISCH
|
847 WM8994_LINEOUT2_DISCH
, 0);
849 wm_hubs_vmid_ena(codec
);
851 switch (wm8994
->vmid_mode
) {
853 WARN_ON(NULL
== "Invalid VMID mode");
854 case WM8994_VMID_NORMAL
:
855 /* Startup bias, VMID ramp & buffer */
856 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
859 WM8994_STARTUP_BIAS_ENA
|
860 WM8994_VMID_BUF_ENA
|
861 WM8994_VMID_RAMP_MASK
,
863 WM8994_STARTUP_BIAS_ENA
|
864 WM8994_VMID_BUF_ENA
|
865 (0x2 << WM8994_VMID_RAMP_SHIFT
));
867 /* Main bias enable, VMID=2x40k */
868 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
870 WM8994_VMID_SEL_MASK
,
871 WM8994_BIAS_ENA
| 0x2);
875 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
876 WM8994_VMID_RAMP_MASK
|
881 case WM8994_VMID_FORCE
:
882 /* Startup bias, slow VMID ramp & buffer */
883 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
886 WM8994_STARTUP_BIAS_ENA
|
887 WM8994_VMID_BUF_ENA
|
888 WM8994_VMID_RAMP_MASK
,
890 WM8994_STARTUP_BIAS_ENA
|
891 WM8994_VMID_BUF_ENA
|
892 (0x2 << WM8994_VMID_RAMP_SHIFT
));
894 /* Main bias enable, VMID=2x40k */
895 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
897 WM8994_VMID_SEL_MASK
,
898 WM8994_BIAS_ENA
| 0x2);
902 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
903 WM8994_VMID_RAMP_MASK
|
911 static void vmid_dereference(struct snd_soc_codec
*codec
)
913 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
915 wm8994
->vmid_refcount
--;
917 dev_dbg(codec
->dev
, "Dereferencing VMID, refcount is now %d\n",
918 wm8994
->vmid_refcount
);
920 if (wm8994
->vmid_refcount
== 0) {
921 if (wm8994
->hubs
.lineout1_se
)
922 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_3
,
923 WM8994_LINEOUT1N_ENA
|
924 WM8994_LINEOUT1P_ENA
,
925 WM8994_LINEOUT1N_ENA
|
926 WM8994_LINEOUT1P_ENA
);
928 if (wm8994
->hubs
.lineout2_se
)
929 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_3
,
930 WM8994_LINEOUT2N_ENA
|
931 WM8994_LINEOUT2P_ENA
,
932 WM8994_LINEOUT2N_ENA
|
933 WM8994_LINEOUT2P_ENA
);
935 /* Start discharging VMID */
936 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
942 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
943 WM8994_VMID_SEL_MASK
, 0);
947 /* Active discharge */
948 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
949 WM8994_LINEOUT1_DISCH
|
950 WM8994_LINEOUT2_DISCH
,
951 WM8994_LINEOUT1_DISCH
|
952 WM8994_LINEOUT2_DISCH
);
954 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_3
,
955 WM8994_LINEOUT1N_ENA
|
956 WM8994_LINEOUT1P_ENA
|
957 WM8994_LINEOUT2N_ENA
|
958 WM8994_LINEOUT2P_ENA
, 0);
960 /* Switch off startup biases */
961 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
963 WM8994_STARTUP_BIAS_ENA
|
964 WM8994_VMID_BUF_ENA
|
965 WM8994_VMID_RAMP_MASK
, 0);
967 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
968 WM8994_VMID_SEL_MASK
, 0);
971 pm_runtime_put(codec
->dev
);
974 static int vmid_event(struct snd_soc_dapm_widget
*w
,
975 struct snd_kcontrol
*kcontrol
, int event
)
977 struct snd_soc_codec
*codec
= w
->codec
;
980 case SND_SOC_DAPM_PRE_PMU
:
981 vmid_reference(codec
);
984 case SND_SOC_DAPM_POST_PMD
:
985 vmid_dereference(codec
);
992 static bool wm8994_check_class_w_digital(struct snd_soc_codec
*codec
)
994 int source
= 0; /* GCC flow analysis can't track enable */
997 /* We also need the same AIF source for L/R and only one path */
998 reg
= snd_soc_read(codec
, WM8994_DAC1_LEFT_MIXER_ROUTING
);
1000 case WM8994_AIF2DACL_TO_DAC1L
:
1001 dev_vdbg(codec
->dev
, "Class W source AIF2DAC\n");
1002 source
= 2 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
1004 case WM8994_AIF1DAC2L_TO_DAC1L
:
1005 dev_vdbg(codec
->dev
, "Class W source AIF1DAC2\n");
1006 source
= 1 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
1008 case WM8994_AIF1DAC1L_TO_DAC1L
:
1009 dev_vdbg(codec
->dev
, "Class W source AIF1DAC1\n");
1010 source
= 0 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
1013 dev_vdbg(codec
->dev
, "DAC mixer setting: %x\n", reg
);
1017 reg_r
= snd_soc_read(codec
, WM8994_DAC1_RIGHT_MIXER_ROUTING
);
1019 dev_vdbg(codec
->dev
, "Left and right DAC mixers different\n");
1023 /* Set the source up */
1024 snd_soc_update_bits(codec
, WM8994_CLASS_W_1
,
1025 WM8994_CP_DYN_SRC_SEL_MASK
, source
);
1030 static int aif1clk_ev(struct snd_soc_dapm_widget
*w
,
1031 struct snd_kcontrol
*kcontrol
, int event
)
1033 struct snd_soc_codec
*codec
= w
->codec
;
1034 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1035 struct wm8994
*control
= codec
->control_data
;
1036 int mask
= WM8994_AIF1DAC1L_ENA
| WM8994_AIF1DAC1R_ENA
;
1042 switch (control
->type
) {
1045 mask
|= WM8994_AIF1DAC2L_ENA
| WM8994_AIF1DAC2R_ENA
;
1052 case SND_SOC_DAPM_PRE_PMU
:
1053 /* Don't enable timeslot 2 if not in use */
1054 if (wm8994
->channels
[0] <= 2)
1055 mask
&= ~(WM8994_AIF1DAC2L_ENA
| WM8994_AIF1DAC2R_ENA
);
1057 val
= snd_soc_read(codec
, WM8994_AIF1_CONTROL_1
);
1058 if ((val
& WM8994_AIF1ADCL_SRC
) &&
1059 (val
& WM8994_AIF1ADCR_SRC
))
1060 adc
= WM8994_AIF1ADC1R_ENA
| WM8994_AIF1ADC2R_ENA
;
1061 else if (!(val
& WM8994_AIF1ADCL_SRC
) &&
1062 !(val
& WM8994_AIF1ADCR_SRC
))
1063 adc
= WM8994_AIF1ADC1L_ENA
| WM8994_AIF1ADC2L_ENA
;
1065 adc
= WM8994_AIF1ADC1R_ENA
| WM8994_AIF1ADC2R_ENA
|
1066 WM8994_AIF1ADC1L_ENA
| WM8994_AIF1ADC2L_ENA
;
1068 val
= snd_soc_read(codec
, WM8994_AIF1_CONTROL_2
);
1069 if ((val
& WM8994_AIF1DACL_SRC
) &&
1070 (val
& WM8994_AIF1DACR_SRC
))
1071 dac
= WM8994_AIF1DAC1R_ENA
| WM8994_AIF1DAC2R_ENA
;
1072 else if (!(val
& WM8994_AIF1DACL_SRC
) &&
1073 !(val
& WM8994_AIF1DACR_SRC
))
1074 dac
= WM8994_AIF1DAC1L_ENA
| WM8994_AIF1DAC2L_ENA
;
1076 dac
= WM8994_AIF1DAC1R_ENA
| WM8994_AIF1DAC2R_ENA
|
1077 WM8994_AIF1DAC1L_ENA
| WM8994_AIF1DAC2L_ENA
;
1079 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
,
1081 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1083 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
1084 WM8994_AIF1DSPCLK_ENA
|
1085 WM8994_SYSDSPCLK_ENA
,
1086 WM8994_AIF1DSPCLK_ENA
|
1087 WM8994_SYSDSPCLK_ENA
);
1088 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
, mask
,
1089 WM8994_AIF1ADC1R_ENA
|
1090 WM8994_AIF1ADC1L_ENA
|
1091 WM8994_AIF1ADC2R_ENA
|
1092 WM8994_AIF1ADC2L_ENA
);
1093 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
, mask
,
1094 WM8994_AIF1DAC1R_ENA
|
1095 WM8994_AIF1DAC1L_ENA
|
1096 WM8994_AIF1DAC2R_ENA
|
1097 WM8994_AIF1DAC2L_ENA
);
1100 case SND_SOC_DAPM_POST_PMU
:
1101 for (i
= 0; i
< ARRAY_SIZE(wm8994_vu_bits
); i
++)
1102 snd_soc_write(codec
, wm8994_vu_bits
[i
].reg
,
1104 wm8994_vu_bits
[i
].reg
));
1107 case SND_SOC_DAPM_PRE_PMD
:
1108 case SND_SOC_DAPM_POST_PMD
:
1109 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1111 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
,
1114 val
= snd_soc_read(codec
, WM8994_CLOCKING_1
);
1115 if (val
& WM8994_AIF2DSPCLK_ENA
)
1116 val
= WM8994_SYSDSPCLK_ENA
;
1119 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
1120 WM8994_SYSDSPCLK_ENA
|
1121 WM8994_AIF1DSPCLK_ENA
, val
);
1128 static int aif2clk_ev(struct snd_soc_dapm_widget
*w
,
1129 struct snd_kcontrol
*kcontrol
, int event
)
1131 struct snd_soc_codec
*codec
= w
->codec
;
1138 case SND_SOC_DAPM_PRE_PMU
:
1139 val
= snd_soc_read(codec
, WM8994_AIF2_CONTROL_1
);
1140 if ((val
& WM8994_AIF2ADCL_SRC
) &&
1141 (val
& WM8994_AIF2ADCR_SRC
))
1142 adc
= WM8994_AIF2ADCR_ENA
;
1143 else if (!(val
& WM8994_AIF2ADCL_SRC
) &&
1144 !(val
& WM8994_AIF2ADCR_SRC
))
1145 adc
= WM8994_AIF2ADCL_ENA
;
1147 adc
= WM8994_AIF2ADCL_ENA
| WM8994_AIF2ADCR_ENA
;
1150 val
= snd_soc_read(codec
, WM8994_AIF2_CONTROL_2
);
1151 if ((val
& WM8994_AIF2DACL_SRC
) &&
1152 (val
& WM8994_AIF2DACR_SRC
))
1153 dac
= WM8994_AIF2DACR_ENA
;
1154 else if (!(val
& WM8994_AIF2DACL_SRC
) &&
1155 !(val
& WM8994_AIF2DACR_SRC
))
1156 dac
= WM8994_AIF2DACL_ENA
;
1158 dac
= WM8994_AIF2DACL_ENA
| WM8994_AIF2DACR_ENA
;
1160 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
,
1161 WM8994_AIF2ADCL_ENA
|
1162 WM8994_AIF2ADCR_ENA
, adc
);
1163 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1164 WM8994_AIF2DACL_ENA
|
1165 WM8994_AIF2DACR_ENA
, dac
);
1166 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
1167 WM8994_AIF2DSPCLK_ENA
|
1168 WM8994_SYSDSPCLK_ENA
,
1169 WM8994_AIF2DSPCLK_ENA
|
1170 WM8994_SYSDSPCLK_ENA
);
1171 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
,
1172 WM8994_AIF2ADCL_ENA
|
1173 WM8994_AIF2ADCR_ENA
,
1174 WM8994_AIF2ADCL_ENA
|
1175 WM8994_AIF2ADCR_ENA
);
1176 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1177 WM8994_AIF2DACL_ENA
|
1178 WM8994_AIF2DACR_ENA
,
1179 WM8994_AIF2DACL_ENA
|
1180 WM8994_AIF2DACR_ENA
);
1183 case SND_SOC_DAPM_POST_PMU
:
1184 for (i
= 0; i
< ARRAY_SIZE(wm8994_vu_bits
); i
++)
1185 snd_soc_write(codec
, wm8994_vu_bits
[i
].reg
,
1187 wm8994_vu_bits
[i
].reg
));
1190 case SND_SOC_DAPM_PRE_PMD
:
1191 case SND_SOC_DAPM_POST_PMD
:
1192 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1193 WM8994_AIF2DACL_ENA
|
1194 WM8994_AIF2DACR_ENA
, 0);
1195 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
,
1196 WM8994_AIF2ADCL_ENA
|
1197 WM8994_AIF2ADCR_ENA
, 0);
1199 val
= snd_soc_read(codec
, WM8994_CLOCKING_1
);
1200 if (val
& WM8994_AIF1DSPCLK_ENA
)
1201 val
= WM8994_SYSDSPCLK_ENA
;
1204 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
1205 WM8994_SYSDSPCLK_ENA
|
1206 WM8994_AIF2DSPCLK_ENA
, val
);
1213 static int aif1clk_late_ev(struct snd_soc_dapm_widget
*w
,
1214 struct snd_kcontrol
*kcontrol
, int event
)
1216 struct snd_soc_codec
*codec
= w
->codec
;
1217 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1220 case SND_SOC_DAPM_PRE_PMU
:
1221 wm8994
->aif1clk_enable
= 1;
1223 case SND_SOC_DAPM_POST_PMD
:
1224 wm8994
->aif1clk_disable
= 1;
1231 static int aif2clk_late_ev(struct snd_soc_dapm_widget
*w
,
1232 struct snd_kcontrol
*kcontrol
, int event
)
1234 struct snd_soc_codec
*codec
= w
->codec
;
1235 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1238 case SND_SOC_DAPM_PRE_PMU
:
1239 wm8994
->aif2clk_enable
= 1;
1241 case SND_SOC_DAPM_POST_PMD
:
1242 wm8994
->aif2clk_disable
= 1;
1249 static int late_enable_ev(struct snd_soc_dapm_widget
*w
,
1250 struct snd_kcontrol
*kcontrol
, int event
)
1252 struct snd_soc_codec
*codec
= w
->codec
;
1253 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1256 case SND_SOC_DAPM_PRE_PMU
:
1257 if (wm8994
->aif1clk_enable
) {
1258 aif1clk_ev(w
, kcontrol
, SND_SOC_DAPM_PRE_PMU
);
1259 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
1260 WM8994_AIF1CLK_ENA_MASK
,
1261 WM8994_AIF1CLK_ENA
);
1262 aif1clk_ev(w
, kcontrol
, SND_SOC_DAPM_POST_PMU
);
1263 wm8994
->aif1clk_enable
= 0;
1265 if (wm8994
->aif2clk_enable
) {
1266 aif2clk_ev(w
, kcontrol
, SND_SOC_DAPM_PRE_PMU
);
1267 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
1268 WM8994_AIF2CLK_ENA_MASK
,
1269 WM8994_AIF2CLK_ENA
);
1270 aif2clk_ev(w
, kcontrol
, SND_SOC_DAPM_POST_PMU
);
1271 wm8994
->aif2clk_enable
= 0;
1276 /* We may also have postponed startup of DSP, handle that. */
1277 wm8958_aif_ev(w
, kcontrol
, event
);
1282 static int late_disable_ev(struct snd_soc_dapm_widget
*w
,
1283 struct snd_kcontrol
*kcontrol
, int event
)
1285 struct snd_soc_codec
*codec
= w
->codec
;
1286 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1289 case SND_SOC_DAPM_POST_PMD
:
1290 if (wm8994
->aif1clk_disable
) {
1291 aif1clk_ev(w
, kcontrol
, SND_SOC_DAPM_PRE_PMD
);
1292 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
1293 WM8994_AIF1CLK_ENA_MASK
, 0);
1294 aif1clk_ev(w
, kcontrol
, SND_SOC_DAPM_POST_PMD
);
1295 wm8994
->aif1clk_disable
= 0;
1297 if (wm8994
->aif2clk_disable
) {
1298 aif2clk_ev(w
, kcontrol
, SND_SOC_DAPM_PRE_PMD
);
1299 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
1300 WM8994_AIF2CLK_ENA_MASK
, 0);
1301 aif2clk_ev(w
, kcontrol
, SND_SOC_DAPM_POST_PMD
);
1302 wm8994
->aif2clk_disable
= 0;
1310 static int adc_mux_ev(struct snd_soc_dapm_widget
*w
,
1311 struct snd_kcontrol
*kcontrol
, int event
)
1313 late_enable_ev(w
, kcontrol
, event
);
1317 static int micbias_ev(struct snd_soc_dapm_widget
*w
,
1318 struct snd_kcontrol
*kcontrol
, int event
)
1320 late_enable_ev(w
, kcontrol
, event
);
1324 static int dac_ev(struct snd_soc_dapm_widget
*w
,
1325 struct snd_kcontrol
*kcontrol
, int event
)
1327 struct snd_soc_codec
*codec
= w
->codec
;
1328 unsigned int mask
= 1 << w
->shift
;
1330 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1335 static const char *adc_mux_text
[] = {
1340 static const struct soc_enum adc_enum
=
1341 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text
);
1343 static const struct snd_kcontrol_new adcl_mux
=
1344 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum
);
1346 static const struct snd_kcontrol_new adcr_mux
=
1347 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum
);
1349 static const struct snd_kcontrol_new left_speaker_mixer
[] = {
1350 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER
, 9, 1, 0),
1351 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER
, 7, 1, 0),
1352 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER
, 5, 1, 0),
1353 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER
, 3, 1, 0),
1354 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER
, 1, 1, 0),
1357 static const struct snd_kcontrol_new right_speaker_mixer
[] = {
1358 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER
, 8, 1, 0),
1359 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER
, 6, 1, 0),
1360 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER
, 4, 1, 0),
1361 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER
, 2, 1, 0),
1362 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER
, 0, 1, 0),
1365 /* Debugging; dump chip status after DAPM transitions */
1366 static int post_ev(struct snd_soc_dapm_widget
*w
,
1367 struct snd_kcontrol
*kcontrol
, int event
)
1369 struct snd_soc_codec
*codec
= w
->codec
;
1370 dev_dbg(codec
->dev
, "SRC status: %x\n",
1372 WM8994_RATE_STATUS
));
1376 static const struct snd_kcontrol_new aif1adc1l_mix
[] = {
1377 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING
,
1379 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING
,
1383 static const struct snd_kcontrol_new aif1adc1r_mix
[] = {
1384 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING
,
1386 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING
,
1390 static const struct snd_kcontrol_new aif1adc2l_mix
[] = {
1391 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING
,
1393 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING
,
1397 static const struct snd_kcontrol_new aif1adc2r_mix
[] = {
1398 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING
,
1400 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING
,
1404 static const struct snd_kcontrol_new aif2dac2l_mix
[] = {
1405 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1407 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1409 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1411 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1413 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1417 static const struct snd_kcontrol_new aif2dac2r_mix
[] = {
1418 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1420 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1422 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1424 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1426 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1430 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1431 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1432 .info = snd_soc_info_volsw, \
1433 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1434 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1436 static int wm8994_put_class_w(struct snd_kcontrol
*kcontrol
,
1437 struct snd_ctl_elem_value
*ucontrol
)
1439 struct snd_soc_dapm_widget_list
*wlist
= snd_kcontrol_chip(kcontrol
);
1440 struct snd_soc_dapm_widget
*w
= wlist
->widgets
[0];
1441 struct snd_soc_codec
*codec
= w
->codec
;
1444 ret
= snd_soc_dapm_put_volsw(kcontrol
, ucontrol
);
1446 wm_hubs_update_class_w(codec
);
1451 static const struct snd_kcontrol_new dac1l_mix
[] = {
1452 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1454 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1456 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1458 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1460 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1464 static const struct snd_kcontrol_new dac1r_mix
[] = {
1465 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1467 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1469 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1471 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1473 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1477 static const char *sidetone_text
[] = {
1478 "ADC/DMIC1", "DMIC2",
1481 static const struct soc_enum sidetone1_enum
=
1482 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 0, 2, sidetone_text
);
1484 static const struct snd_kcontrol_new sidetone1_mux
=
1485 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum
);
1487 static const struct soc_enum sidetone2_enum
=
1488 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 1, 2, sidetone_text
);
1490 static const struct snd_kcontrol_new sidetone2_mux
=
1491 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum
);
1493 static const char *aif1dac_text
[] = {
1494 "AIF1DACDAT", "AIF3DACDAT",
1497 static const struct soc_enum aif1dac_enum
=
1498 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 0, 2, aif1dac_text
);
1500 static const struct snd_kcontrol_new aif1dac_mux
=
1501 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum
);
1503 static const char *aif2dac_text
[] = {
1504 "AIF2DACDAT", "AIF3DACDAT",
1507 static const struct soc_enum aif2dac_enum
=
1508 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 1, 2, aif2dac_text
);
1510 static const struct snd_kcontrol_new aif2dac_mux
=
1511 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum
);
1513 static const char *aif2adc_text
[] = {
1514 "AIF2ADCDAT", "AIF3DACDAT",
1517 static const struct soc_enum aif2adc_enum
=
1518 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 2, 2, aif2adc_text
);
1520 static const struct snd_kcontrol_new aif2adc_mux
=
1521 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum
);
1523 static const char *aif3adc_text
[] = {
1524 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1527 static const struct soc_enum wm8994_aif3adc_enum
=
1528 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 3, 3, aif3adc_text
);
1530 static const struct snd_kcontrol_new wm8994_aif3adc_mux
=
1531 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum
);
1533 static const struct soc_enum wm8958_aif3adc_enum
=
1534 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 3, 4, aif3adc_text
);
1536 static const struct snd_kcontrol_new wm8958_aif3adc_mux
=
1537 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum
);
1539 static const char *mono_pcm_out_text
[] = {
1540 "None", "AIF2ADCL", "AIF2ADCR",
1543 static const struct soc_enum mono_pcm_out_enum
=
1544 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 9, 3, mono_pcm_out_text
);
1546 static const struct snd_kcontrol_new mono_pcm_out_mux
=
1547 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum
);
1549 static const char *aif2dac_src_text
[] = {
1553 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1554 static const struct soc_enum aif2dacl_src_enum
=
1555 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 7, 2, aif2dac_src_text
);
1557 static const struct snd_kcontrol_new aif2dacl_src_mux
=
1558 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum
);
1560 static const struct soc_enum aif2dacr_src_enum
=
1561 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 8, 2, aif2dac_src_text
);
1563 static const struct snd_kcontrol_new aif2dacr_src_mux
=
1564 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum
);
1566 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets
[] = {
1567 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM
, 0, 0, aif1clk_late_ev
,
1568 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1569 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM
, 0, 0, aif2clk_late_ev
,
1570 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1572 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1573 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1574 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1575 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1576 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1577 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1578 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1579 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1580 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1581 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1583 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3
, 8, 0,
1584 left_speaker_mixer
, ARRAY_SIZE(left_speaker_mixer
),
1585 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1586 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3
, 9, 0,
1587 right_speaker_mixer
, ARRAY_SIZE(right_speaker_mixer
),
1588 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1589 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM
, 0, 0, &wm_hubs_hpl_mux
,
1590 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1591 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM
, 0, 0, &wm_hubs_hpr_mux
,
1592 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1594 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev
)
1597 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets
[] = {
1598 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1
, 0, 0, aif1clk_ev
,
1599 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMU
|
1600 SND_SOC_DAPM_PRE_PMD
),
1601 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1
, 0, 0, aif2clk_ev
,
1602 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMU
|
1603 SND_SOC_DAPM_PRE_PMD
),
1604 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM
, 0, 0, NULL
, 0),
1605 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3
, 8, 0,
1606 left_speaker_mixer
, ARRAY_SIZE(left_speaker_mixer
)),
1607 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3
, 9, 0,
1608 right_speaker_mixer
, ARRAY_SIZE(right_speaker_mixer
)),
1609 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM
, 0, 0, &wm_hubs_hpl_mux
),
1610 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM
, 0, 0, &wm_hubs_hpr_mux
),
1613 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets
[] = {
1614 SND_SOC_DAPM_DAC_E("DAC2L", NULL
, SND_SOC_NOPM
, 3, 0,
1615 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1616 SND_SOC_DAPM_DAC_E("DAC2R", NULL
, SND_SOC_NOPM
, 2, 0,
1617 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1618 SND_SOC_DAPM_DAC_E("DAC1L", NULL
, SND_SOC_NOPM
, 1, 0,
1619 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1620 SND_SOC_DAPM_DAC_E("DAC1R", NULL
, SND_SOC_NOPM
, 0, 0,
1621 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1624 static const struct snd_soc_dapm_widget wm8994_dac_widgets
[] = {
1625 SND_SOC_DAPM_DAC("DAC2L", NULL
, WM8994_POWER_MANAGEMENT_5
, 3, 0),
1626 SND_SOC_DAPM_DAC("DAC2R", NULL
, WM8994_POWER_MANAGEMENT_5
, 2, 0),
1627 SND_SOC_DAPM_DAC("DAC1L", NULL
, WM8994_POWER_MANAGEMENT_5
, 1, 0),
1628 SND_SOC_DAPM_DAC("DAC1R", NULL
, WM8994_POWER_MANAGEMENT_5
, 0, 0),
1631 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets
[] = {
1632 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4
, 1, 0, &adcl_mux
,
1633 adc_mux_ev
, SND_SOC_DAPM_PRE_PMU
),
1634 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4
, 0, 0, &adcr_mux
,
1635 adc_mux_ev
, SND_SOC_DAPM_PRE_PMU
),
1638 static const struct snd_soc_dapm_widget wm8994_adc_widgets
[] = {
1639 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4
, 1, 0, &adcl_mux
),
1640 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4
, 0, 0, &adcr_mux
),
1643 static const struct snd_soc_dapm_widget wm8994_dapm_widgets
[] = {
1644 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1645 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1646 SND_SOC_DAPM_INPUT("Clock"),
1648 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM
, 0, 0, micbias_ev
,
1649 SND_SOC_DAPM_PRE_PMU
),
1650 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM
, 0, 0, vmid_event
,
1651 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1653 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM
, 0, 0, clk_sys_event
,
1654 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMU
|
1655 SND_SOC_DAPM_PRE_PMD
),
1657 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM
, 3, 0, NULL
, 0),
1658 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM
, 2, 0, NULL
, 0),
1659 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM
, 1, 0, NULL
, 0),
1661 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL
,
1662 0, SND_SOC_NOPM
, 9, 0),
1663 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL
,
1664 0, SND_SOC_NOPM
, 8, 0),
1665 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL
, 0,
1666 SND_SOC_NOPM
, 9, 0, wm8958_aif_ev
,
1667 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1668 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL
, 0,
1669 SND_SOC_NOPM
, 8, 0, wm8958_aif_ev
,
1670 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1672 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL
,
1673 0, SND_SOC_NOPM
, 11, 0),
1674 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL
,
1675 0, SND_SOC_NOPM
, 10, 0),
1676 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL
, 0,
1677 SND_SOC_NOPM
, 11, 0, wm8958_aif_ev
,
1678 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1679 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL
, 0,
1680 SND_SOC_NOPM
, 10, 0, wm8958_aif_ev
,
1681 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1683 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM
, 0, 0,
1684 aif1adc1l_mix
, ARRAY_SIZE(aif1adc1l_mix
)),
1685 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM
, 0, 0,
1686 aif1adc1r_mix
, ARRAY_SIZE(aif1adc1r_mix
)),
1688 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM
, 0, 0,
1689 aif1adc2l_mix
, ARRAY_SIZE(aif1adc2l_mix
)),
1690 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM
, 0, 0,
1691 aif1adc2r_mix
, ARRAY_SIZE(aif1adc2r_mix
)),
1693 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM
, 0, 0,
1694 aif2dac2l_mix
, ARRAY_SIZE(aif2dac2l_mix
)),
1695 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM
, 0, 0,
1696 aif2dac2r_mix
, ARRAY_SIZE(aif2dac2r_mix
)),
1698 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM
, 0, 0, &sidetone1_mux
),
1699 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM
, 0, 0, &sidetone2_mux
),
1701 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM
, 0, 0,
1702 dac1l_mix
, ARRAY_SIZE(dac1l_mix
)),
1703 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM
, 0, 0,
1704 dac1r_mix
, ARRAY_SIZE(dac1r_mix
)),
1706 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL
, 0,
1707 SND_SOC_NOPM
, 13, 0),
1708 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL
, 0,
1709 SND_SOC_NOPM
, 12, 0),
1710 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL
, 0,
1711 SND_SOC_NOPM
, 13, 0, wm8958_aif_ev
,
1712 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1713 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL
, 0,
1714 SND_SOC_NOPM
, 12, 0, wm8958_aif_ev
,
1715 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1717 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1718 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1719 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1720 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1722 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM
, 0, 0, &aif1dac_mux
),
1723 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM
, 0, 0, &aif2dac_mux
),
1724 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM
, 0, 0, &aif2adc_mux
),
1726 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1727 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1729 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1
, 4, 0, NULL
, 0),
1731 SND_SOC_DAPM_ADC("DMIC2L", NULL
, WM8994_POWER_MANAGEMENT_4
, 5, 0),
1732 SND_SOC_DAPM_ADC("DMIC2R", NULL
, WM8994_POWER_MANAGEMENT_4
, 4, 0),
1733 SND_SOC_DAPM_ADC("DMIC1L", NULL
, WM8994_POWER_MANAGEMENT_4
, 3, 0),
1734 SND_SOC_DAPM_ADC("DMIC1R", NULL
, WM8994_POWER_MANAGEMENT_4
, 2, 0),
1736 /* Power is done with the muxes since the ADC power also controls the
1737 * downsampling chain, the chip will automatically manage the analogue
1738 * specific portions.
1740 SND_SOC_DAPM_ADC("ADCL", NULL
, SND_SOC_NOPM
, 1, 0),
1741 SND_SOC_DAPM_ADC("ADCR", NULL
, SND_SOC_NOPM
, 0, 0),
1743 SND_SOC_DAPM_POST("Debug log", post_ev
),
1746 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets
[] = {
1747 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM
, 0, 0, &wm8994_aif3adc_mux
),
1750 static const struct snd_soc_dapm_widget wm8958_dapm_widgets
[] = {
1751 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6
, 5, 1, NULL
, 0),
1752 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM
, 0, 0, &mono_pcm_out_mux
),
1753 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM
, 0, 0, &aif2dacl_src_mux
),
1754 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM
, 0, 0, &aif2dacr_src_mux
),
1755 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM
, 0, 0, &wm8958_aif3adc_mux
),
1758 static const struct snd_soc_dapm_route intercon
[] = {
1759 { "CLK_SYS", NULL
, "AIF1CLK", check_clk_sys
},
1760 { "CLK_SYS", NULL
, "AIF2CLK", check_clk_sys
},
1762 { "DSP1CLK", NULL
, "CLK_SYS" },
1763 { "DSP2CLK", NULL
, "CLK_SYS" },
1764 { "DSPINTCLK", NULL
, "CLK_SYS" },
1766 { "AIF1ADC1L", NULL
, "AIF1CLK" },
1767 { "AIF1ADC1L", NULL
, "DSP1CLK" },
1768 { "AIF1ADC1R", NULL
, "AIF1CLK" },
1769 { "AIF1ADC1R", NULL
, "DSP1CLK" },
1770 { "AIF1ADC1R", NULL
, "DSPINTCLK" },
1772 { "AIF1DAC1L", NULL
, "AIF1CLK" },
1773 { "AIF1DAC1L", NULL
, "DSP1CLK" },
1774 { "AIF1DAC1R", NULL
, "AIF1CLK" },
1775 { "AIF1DAC1R", NULL
, "DSP1CLK" },
1776 { "AIF1DAC1R", NULL
, "DSPINTCLK" },
1778 { "AIF1ADC2L", NULL
, "AIF1CLK" },
1779 { "AIF1ADC2L", NULL
, "DSP1CLK" },
1780 { "AIF1ADC2R", NULL
, "AIF1CLK" },
1781 { "AIF1ADC2R", NULL
, "DSP1CLK" },
1782 { "AIF1ADC2R", NULL
, "DSPINTCLK" },
1784 { "AIF1DAC2L", NULL
, "AIF1CLK" },
1785 { "AIF1DAC2L", NULL
, "DSP1CLK" },
1786 { "AIF1DAC2R", NULL
, "AIF1CLK" },
1787 { "AIF1DAC2R", NULL
, "DSP1CLK" },
1788 { "AIF1DAC2R", NULL
, "DSPINTCLK" },
1790 { "AIF2ADCL", NULL
, "AIF2CLK" },
1791 { "AIF2ADCL", NULL
, "DSP2CLK" },
1792 { "AIF2ADCR", NULL
, "AIF2CLK" },
1793 { "AIF2ADCR", NULL
, "DSP2CLK" },
1794 { "AIF2ADCR", NULL
, "DSPINTCLK" },
1796 { "AIF2DACL", NULL
, "AIF2CLK" },
1797 { "AIF2DACL", NULL
, "DSP2CLK" },
1798 { "AIF2DACR", NULL
, "AIF2CLK" },
1799 { "AIF2DACR", NULL
, "DSP2CLK" },
1800 { "AIF2DACR", NULL
, "DSPINTCLK" },
1802 { "DMIC1L", NULL
, "DMIC1DAT" },
1803 { "DMIC1L", NULL
, "CLK_SYS" },
1804 { "DMIC1R", NULL
, "DMIC1DAT" },
1805 { "DMIC1R", NULL
, "CLK_SYS" },
1806 { "DMIC2L", NULL
, "DMIC2DAT" },
1807 { "DMIC2L", NULL
, "CLK_SYS" },
1808 { "DMIC2R", NULL
, "DMIC2DAT" },
1809 { "DMIC2R", NULL
, "CLK_SYS" },
1811 { "ADCL", NULL
, "AIF1CLK" },
1812 { "ADCL", NULL
, "DSP1CLK" },
1813 { "ADCL", NULL
, "DSPINTCLK" },
1815 { "ADCR", NULL
, "AIF1CLK" },
1816 { "ADCR", NULL
, "DSP1CLK" },
1817 { "ADCR", NULL
, "DSPINTCLK" },
1819 { "ADCL Mux", "ADC", "ADCL" },
1820 { "ADCL Mux", "DMIC", "DMIC1L" },
1821 { "ADCR Mux", "ADC", "ADCR" },
1822 { "ADCR Mux", "DMIC", "DMIC1R" },
1824 { "DAC1L", NULL
, "AIF1CLK" },
1825 { "DAC1L", NULL
, "DSP1CLK" },
1826 { "DAC1L", NULL
, "DSPINTCLK" },
1828 { "DAC1R", NULL
, "AIF1CLK" },
1829 { "DAC1R", NULL
, "DSP1CLK" },
1830 { "DAC1R", NULL
, "DSPINTCLK" },
1832 { "DAC2L", NULL
, "AIF2CLK" },
1833 { "DAC2L", NULL
, "DSP2CLK" },
1834 { "DAC2L", NULL
, "DSPINTCLK" },
1836 { "DAC2R", NULL
, "AIF2DACR" },
1837 { "DAC2R", NULL
, "AIF2CLK" },
1838 { "DAC2R", NULL
, "DSP2CLK" },
1839 { "DAC2R", NULL
, "DSPINTCLK" },
1841 { "TOCLK", NULL
, "CLK_SYS" },
1843 { "AIF1DACDAT", NULL
, "AIF1 Playback" },
1844 { "AIF2DACDAT", NULL
, "AIF2 Playback" },
1845 { "AIF3DACDAT", NULL
, "AIF3 Playback" },
1847 { "AIF1 Capture", NULL
, "AIF1ADCDAT" },
1848 { "AIF2 Capture", NULL
, "AIF2ADCDAT" },
1849 { "AIF3 Capture", NULL
, "AIF3ADCDAT" },
1852 { "AIF1ADC1L", NULL
, "AIF1ADC1L Mixer" },
1853 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1854 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1856 { "AIF1ADC1R", NULL
, "AIF1ADC1R Mixer" },
1857 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1858 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1860 { "AIF1ADC2L", NULL
, "AIF1ADC2L Mixer" },
1861 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1862 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1864 { "AIF1ADC2R", NULL
, "AIF1ADC2R Mixer" },
1865 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1866 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1868 /* Pin level routing for AIF3 */
1869 { "AIF1DAC1L", NULL
, "AIF1DAC Mux" },
1870 { "AIF1DAC1R", NULL
, "AIF1DAC Mux" },
1871 { "AIF1DAC2L", NULL
, "AIF1DAC Mux" },
1872 { "AIF1DAC2R", NULL
, "AIF1DAC Mux" },
1874 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1875 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1876 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1877 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1878 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1879 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1880 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1883 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1884 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1885 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1886 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1887 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1889 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1890 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1891 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1892 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1893 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1895 /* DAC2/AIF2 outputs */
1896 { "AIF2ADCL", NULL
, "AIF2DAC2L Mixer" },
1897 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1898 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1899 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1900 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1901 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1903 { "AIF2ADCR", NULL
, "AIF2DAC2R Mixer" },
1904 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1905 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1906 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1907 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1908 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1910 { "AIF1ADCDAT", NULL
, "AIF1ADC1L" },
1911 { "AIF1ADCDAT", NULL
, "AIF1ADC1R" },
1912 { "AIF1ADCDAT", NULL
, "AIF1ADC2L" },
1913 { "AIF1ADCDAT", NULL
, "AIF1ADC2R" },
1915 { "AIF2ADCDAT", NULL
, "AIF2ADC Mux" },
1918 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1919 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1920 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1921 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1922 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1923 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1924 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1925 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1928 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1929 { "Left Sidetone", "DMIC2", "DMIC2L" },
1930 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1931 { "Right Sidetone", "DMIC2", "DMIC2R" },
1934 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1935 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1937 { "SPKL", "DAC1 Switch", "DAC1L" },
1938 { "SPKL", "DAC2 Switch", "DAC2L" },
1940 { "SPKR", "DAC1 Switch", "DAC1R" },
1941 { "SPKR", "DAC2 Switch", "DAC2R" },
1943 { "Left Headphone Mux", "DAC", "DAC1L" },
1944 { "Right Headphone Mux", "DAC", "DAC1R" },
1947 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon
[] = {
1948 { "DAC1L", NULL
, "Late DAC1L Enable PGA" },
1949 { "Late DAC1L Enable PGA", NULL
, "DAC1L Mixer" },
1950 { "DAC1R", NULL
, "Late DAC1R Enable PGA" },
1951 { "Late DAC1R Enable PGA", NULL
, "DAC1R Mixer" },
1952 { "DAC2L", NULL
, "Late DAC2L Enable PGA" },
1953 { "Late DAC2L Enable PGA", NULL
, "AIF2DAC2L Mixer" },
1954 { "DAC2R", NULL
, "Late DAC2R Enable PGA" },
1955 { "Late DAC2R Enable PGA", NULL
, "AIF2DAC2R Mixer" }
1958 static const struct snd_soc_dapm_route wm8994_lateclk_intercon
[] = {
1959 { "DAC1L", NULL
, "DAC1L Mixer" },
1960 { "DAC1R", NULL
, "DAC1R Mixer" },
1961 { "DAC2L", NULL
, "AIF2DAC2L Mixer" },
1962 { "DAC2R", NULL
, "AIF2DAC2R Mixer" },
1965 static const struct snd_soc_dapm_route wm8994_revd_intercon
[] = {
1966 { "AIF1DACDAT", NULL
, "AIF2DACDAT" },
1967 { "AIF2DACDAT", NULL
, "AIF1DACDAT" },
1968 { "AIF1ADCDAT", NULL
, "AIF2ADCDAT" },
1969 { "AIF2ADCDAT", NULL
, "AIF1ADCDAT" },
1970 { "MICBIAS1", NULL
, "CLK_SYS" },
1971 { "MICBIAS1", NULL
, "MICBIAS Supply" },
1972 { "MICBIAS2", NULL
, "CLK_SYS" },
1973 { "MICBIAS2", NULL
, "MICBIAS Supply" },
1976 static const struct snd_soc_dapm_route wm8994_intercon
[] = {
1977 { "AIF2DACL", NULL
, "AIF2DAC Mux" },
1978 { "AIF2DACR", NULL
, "AIF2DAC Mux" },
1979 { "MICBIAS1", NULL
, "VMID" },
1980 { "MICBIAS2", NULL
, "VMID" },
1983 static const struct snd_soc_dapm_route wm8958_intercon
[] = {
1984 { "AIF2DACL", NULL
, "AIF2DACL Mux" },
1985 { "AIF2DACR", NULL
, "AIF2DACR Mux" },
1987 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1988 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1989 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1990 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1992 { "AIF3DACDAT", NULL
, "AIF3" },
1993 { "AIF3ADCDAT", NULL
, "AIF3" },
1995 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1996 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1998 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
2001 /* The size in bits of the FLL divide multiplied by 10
2002 * to allow rounding later */
2003 #define FIXED_FLL_SIZE ((1 << 16) * 10)
2014 static int wm8994_get_fll_config(struct wm8994
*control
, struct fll_div
*fll
,
2015 int freq_in
, int freq_out
)
2018 unsigned int K
, Ndiv
, Nmod
, gcd_fll
;
2020 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in
, freq_out
);
2022 /* Scale the input frequency down to <= 13.5MHz */
2023 fll
->clk_ref_div
= 0;
2024 while (freq_in
> 13500000) {
2028 if (fll
->clk_ref_div
> 3)
2031 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll
->clk_ref_div
, freq_in
);
2033 /* Scale the output to give 90MHz<=Fvco<=100MHz */
2035 while (freq_out
* (fll
->outdiv
+ 1) < 90000000) {
2037 if (fll
->outdiv
> 63)
2040 freq_out
*= fll
->outdiv
+ 1;
2041 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll
->outdiv
, freq_out
);
2043 if (freq_in
> 1000000) {
2044 fll
->fll_fratio
= 0;
2045 } else if (freq_in
> 256000) {
2046 fll
->fll_fratio
= 1;
2048 } else if (freq_in
> 128000) {
2049 fll
->fll_fratio
= 2;
2051 } else if (freq_in
> 64000) {
2052 fll
->fll_fratio
= 3;
2055 fll
->fll_fratio
= 4;
2058 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll
->fll_fratio
, freq_in
);
2060 /* Now, calculate N.K */
2061 Ndiv
= freq_out
/ freq_in
;
2064 Nmod
= freq_out
% freq_in
;
2065 pr_debug("Nmod=%d\n", Nmod
);
2067 switch (control
->type
) {
2069 /* Calculate fractional part - scale up so we can round. */
2070 Kpart
= FIXED_FLL_SIZE
* (long long)Nmod
;
2072 do_div(Kpart
, freq_in
);
2074 K
= Kpart
& 0xFFFFFFFF;
2079 /* Move down to proper range now rounding is done */
2083 pr_debug("N=%x K=%x\n", fll
->n
, fll
->k
);
2087 gcd_fll
= gcd(freq_out
, freq_in
);
2089 fll
->k
= (freq_out
- (freq_in
* fll
->n
)) / gcd_fll
;
2090 fll
->lambda
= freq_in
/ gcd_fll
;
2097 static int _wm8994_set_fll(struct snd_soc_codec
*codec
, int id
, int src
,
2098 unsigned int freq_in
, unsigned int freq_out
)
2100 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2101 struct wm8994
*control
= wm8994
->wm8994
;
2102 int reg_offset
, ret
;
2104 u16 reg
, clk1
, aif_reg
, aif_src
;
2105 unsigned long timeout
;
2123 reg
= snd_soc_read(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
);
2124 was_enabled
= reg
& WM8994_FLL1_ENA
;
2128 /* Allow no source specification when stopping */
2131 src
= wm8994
->fll
[id
].src
;
2133 case WM8994_FLL_SRC_MCLK1
:
2134 case WM8994_FLL_SRC_MCLK2
:
2135 case WM8994_FLL_SRC_LRCLK
:
2136 case WM8994_FLL_SRC_BCLK
:
2138 case WM8994_FLL_SRC_INTERNAL
:
2140 freq_out
= 12000000;
2146 /* Are we changing anything? */
2147 if (wm8994
->fll
[id
].src
== src
&&
2148 wm8994
->fll
[id
].in
== freq_in
&& wm8994
->fll
[id
].out
== freq_out
)
2151 /* If we're stopping the FLL redo the old config - no
2152 * registers will actually be written but we avoid GCC flow
2153 * analysis bugs spewing warnings.
2156 ret
= wm8994_get_fll_config(control
, &fll
, freq_in
, freq_out
);
2158 ret
= wm8994_get_fll_config(control
, &fll
, wm8994
->fll
[id
].in
,
2159 wm8994
->fll
[id
].out
);
2163 /* Make sure that we're not providing SYSCLK right now */
2164 clk1
= snd_soc_read(codec
, WM8994_CLOCKING_1
);
2165 if (clk1
& WM8994_SYSCLK_SRC
)
2166 aif_reg
= WM8994_AIF2_CLOCKING_1
;
2168 aif_reg
= WM8994_AIF1_CLOCKING_1
;
2169 reg
= snd_soc_read(codec
, aif_reg
);
2171 if ((reg
& WM8994_AIF1CLK_ENA
) &&
2172 (reg
& WM8994_AIF1CLK_SRC_MASK
) == aif_src
) {
2173 dev_err(codec
->dev
, "FLL%d is currently providing SYSCLK\n",
2178 /* We always need to disable the FLL while reconfiguring */
2179 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
,
2180 WM8994_FLL1_ENA
, 0);
2182 if (wm8994
->fll_byp
&& src
== WM8994_FLL_SRC_BCLK
&&
2183 freq_in
== freq_out
&& freq_out
) {
2184 dev_dbg(codec
->dev
, "Bypassing FLL%d\n", id
+ 1);
2185 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_5
+ reg_offset
,
2186 WM8958_FLL1_BYP
, WM8958_FLL1_BYP
);
2190 reg
= (fll
.outdiv
<< WM8994_FLL1_OUTDIV_SHIFT
) |
2191 (fll
.fll_fratio
<< WM8994_FLL1_FRATIO_SHIFT
);
2192 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_2
+ reg_offset
,
2193 WM8994_FLL1_OUTDIV_MASK
|
2194 WM8994_FLL1_FRATIO_MASK
, reg
);
2196 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_3
+ reg_offset
,
2197 WM8994_FLL1_K_MASK
, fll
.k
);
2199 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_4
+ reg_offset
,
2201 fll
.n
<< WM8994_FLL1_N_SHIFT
);
2204 snd_soc_update_bits(codec
, WM8958_FLL1_EFS_1
+ reg_offset
,
2205 WM8958_FLL1_LAMBDA_MASK
,
2207 snd_soc_update_bits(codec
, WM8958_FLL1_EFS_2
+ reg_offset
,
2208 WM8958_FLL1_EFS_ENA
, WM8958_FLL1_EFS_ENA
);
2210 snd_soc_update_bits(codec
, WM8958_FLL1_EFS_2
+ reg_offset
,
2211 WM8958_FLL1_EFS_ENA
, 0);
2214 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_5
+ reg_offset
,
2215 WM8994_FLL1_FRC_NCO
| WM8958_FLL1_BYP
|
2216 WM8994_FLL1_REFCLK_DIV_MASK
|
2217 WM8994_FLL1_REFCLK_SRC_MASK
,
2218 ((src
== WM8994_FLL_SRC_INTERNAL
)
2219 << WM8994_FLL1_FRC_NCO_SHIFT
) |
2220 (fll
.clk_ref_div
<< WM8994_FLL1_REFCLK_DIV_SHIFT
) |
2223 /* Clear any pending completion from a previous failure */
2224 try_wait_for_completion(&wm8994
->fll_locked
[id
]);
2226 /* Enable (with fractional mode if required) */
2228 /* Enable VMID if we need it */
2230 active_reference(codec
);
2232 switch (control
->type
) {
2234 vmid_reference(codec
);
2237 if (control
->revision
< 1)
2238 vmid_reference(codec
);
2245 reg
= WM8994_FLL1_ENA
;
2248 reg
|= WM8994_FLL1_FRAC
;
2249 if (src
== WM8994_FLL_SRC_INTERNAL
)
2250 reg
|= WM8994_FLL1_OSC_ENA
;
2252 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
,
2253 WM8994_FLL1_ENA
| WM8994_FLL1_OSC_ENA
|
2254 WM8994_FLL1_FRAC
, reg
);
2256 if (wm8994
->fll_locked_irq
) {
2257 timeout
= wait_for_completion_timeout(&wm8994
->fll_locked
[id
],
2258 msecs_to_jiffies(10));
2260 dev_warn(codec
->dev
,
2261 "Timed out waiting for FLL lock\n");
2267 switch (control
->type
) {
2269 vmid_dereference(codec
);
2272 if (control
->revision
< 1)
2273 vmid_dereference(codec
);
2279 active_dereference(codec
);
2284 wm8994
->fll
[id
].in
= freq_in
;
2285 wm8994
->fll
[id
].out
= freq_out
;
2286 wm8994
->fll
[id
].src
= src
;
2288 configure_clock(codec
);
2291 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2294 if (max(wm8994
->aifclk
[0], wm8994
->aifclk
[1]) < 50000) {
2295 dev_dbg(codec
->dev
, "Configuring AIFs for 128fs\n");
2297 wm8994
->aifdiv
[0] = snd_soc_read(codec
, WM8994_AIF1_RATE
)
2298 & WM8994_AIF1CLK_RATE_MASK
;
2299 wm8994
->aifdiv
[1] = snd_soc_read(codec
, WM8994_AIF2_RATE
)
2300 & WM8994_AIF1CLK_RATE_MASK
;
2302 snd_soc_update_bits(codec
, WM8994_AIF1_RATE
,
2303 WM8994_AIF1CLK_RATE_MASK
, 0x1);
2304 snd_soc_update_bits(codec
, WM8994_AIF2_RATE
,
2305 WM8994_AIF2CLK_RATE_MASK
, 0x1);
2306 } else if (wm8994
->aifdiv
[0]) {
2307 snd_soc_update_bits(codec
, WM8994_AIF1_RATE
,
2308 WM8994_AIF1CLK_RATE_MASK
,
2310 snd_soc_update_bits(codec
, WM8994_AIF2_RATE
,
2311 WM8994_AIF2CLK_RATE_MASK
,
2314 wm8994
->aifdiv
[0] = 0;
2315 wm8994
->aifdiv
[1] = 0;
2321 static irqreturn_t
wm8994_fll_locked_irq(int irq
, void *data
)
2323 struct completion
*completion
= data
;
2325 complete(completion
);
2330 static int opclk_divs
[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2332 static int wm8994_set_fll(struct snd_soc_dai
*dai
, int id
, int src
,
2333 unsigned int freq_in
, unsigned int freq_out
)
2335 return _wm8994_set_fll(dai
->codec
, id
, src
, freq_in
, freq_out
);
2338 static int wm8994_set_dai_sysclk(struct snd_soc_dai
*dai
,
2339 int clk_id
, unsigned int freq
, int dir
)
2341 struct snd_soc_codec
*codec
= dai
->codec
;
2342 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2351 /* AIF3 shares clocking with AIF1/2 */
2356 case WM8994_SYSCLK_MCLK1
:
2357 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_MCLK1
;
2358 wm8994
->mclk
[0] = freq
;
2359 dev_dbg(dai
->dev
, "AIF%d using MCLK1 at %uHz\n",
2363 case WM8994_SYSCLK_MCLK2
:
2364 /* TODO: Set GPIO AF */
2365 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_MCLK2
;
2366 wm8994
->mclk
[1] = freq
;
2367 dev_dbg(dai
->dev
, "AIF%d using MCLK2 at %uHz\n",
2371 case WM8994_SYSCLK_FLL1
:
2372 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_FLL1
;
2373 dev_dbg(dai
->dev
, "AIF%d using FLL1\n", dai
->id
);
2376 case WM8994_SYSCLK_FLL2
:
2377 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_FLL2
;
2378 dev_dbg(dai
->dev
, "AIF%d using FLL2\n", dai
->id
);
2381 case WM8994_SYSCLK_OPCLK
:
2382 /* Special case - a division (times 10) is given and
2383 * no effect on main clocking.
2386 for (i
= 0; i
< ARRAY_SIZE(opclk_divs
); i
++)
2387 if (opclk_divs
[i
] == freq
)
2389 if (i
== ARRAY_SIZE(opclk_divs
))
2391 snd_soc_update_bits(codec
, WM8994_CLOCKING_2
,
2392 WM8994_OPCLK_DIV_MASK
, i
);
2393 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_2
,
2394 WM8994_OPCLK_ENA
, WM8994_OPCLK_ENA
);
2396 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_2
,
2397 WM8994_OPCLK_ENA
, 0);
2404 configure_clock(codec
);
2407 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2410 if (max(wm8994
->aifclk
[0], wm8994
->aifclk
[1]) < 50000) {
2411 dev_dbg(codec
->dev
, "Configuring AIFs for 128fs\n");
2413 wm8994
->aifdiv
[0] = snd_soc_read(codec
, WM8994_AIF1_RATE
)
2414 & WM8994_AIF1CLK_RATE_MASK
;
2415 wm8994
->aifdiv
[1] = snd_soc_read(codec
, WM8994_AIF2_RATE
)
2416 & WM8994_AIF1CLK_RATE_MASK
;
2418 snd_soc_update_bits(codec
, WM8994_AIF1_RATE
,
2419 WM8994_AIF1CLK_RATE_MASK
, 0x1);
2420 snd_soc_update_bits(codec
, WM8994_AIF2_RATE
,
2421 WM8994_AIF2CLK_RATE_MASK
, 0x1);
2422 } else if (wm8994
->aifdiv
[0]) {
2423 snd_soc_update_bits(codec
, WM8994_AIF1_RATE
,
2424 WM8994_AIF1CLK_RATE_MASK
,
2426 snd_soc_update_bits(codec
, WM8994_AIF2_RATE
,
2427 WM8994_AIF2CLK_RATE_MASK
,
2430 wm8994
->aifdiv
[0] = 0;
2431 wm8994
->aifdiv
[1] = 0;
2437 static int wm8994_set_bias_level(struct snd_soc_codec
*codec
,
2438 enum snd_soc_bias_level level
)
2440 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2441 struct wm8994
*control
= wm8994
->wm8994
;
2443 wm_hubs_set_bias_level(codec
, level
);
2446 case SND_SOC_BIAS_ON
:
2449 case SND_SOC_BIAS_PREPARE
:
2450 /* MICBIAS into regulating mode */
2451 switch (control
->type
) {
2454 snd_soc_update_bits(codec
, WM8958_MICBIAS1
,
2455 WM8958_MICB1_MODE
, 0);
2456 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
2457 WM8958_MICB2_MODE
, 0);
2463 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_STANDBY
)
2464 active_reference(codec
);
2467 case SND_SOC_BIAS_STANDBY
:
2468 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
2469 switch (control
->type
) {
2471 if (control
->revision
== 0) {
2472 /* Optimise performance for rev A */
2473 snd_soc_update_bits(codec
,
2474 WM8958_CHARGE_PUMP_2
,
2484 /* Discharge LINEOUT1 & 2 */
2485 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
2486 WM8994_LINEOUT1_DISCH
|
2487 WM8994_LINEOUT2_DISCH
,
2488 WM8994_LINEOUT1_DISCH
|
2489 WM8994_LINEOUT2_DISCH
);
2492 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_PREPARE
)
2493 active_dereference(codec
);
2495 /* MICBIAS into bypass mode on newer devices */
2496 switch (control
->type
) {
2499 snd_soc_update_bits(codec
, WM8958_MICBIAS1
,
2502 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
2511 case SND_SOC_BIAS_OFF
:
2512 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_STANDBY
)
2513 wm8994
->cur_fw
= NULL
;
2517 codec
->dapm
.bias_level
= level
;
2522 int wm8994_vmid_mode(struct snd_soc_codec
*codec
, enum wm8994_vmid_mode mode
)
2524 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2527 case WM8994_VMID_NORMAL
:
2528 if (wm8994
->hubs
.lineout1_se
) {
2529 snd_soc_dapm_disable_pin(&codec
->dapm
,
2530 "LINEOUT1N Driver");
2531 snd_soc_dapm_disable_pin(&codec
->dapm
,
2532 "LINEOUT1P Driver");
2534 if (wm8994
->hubs
.lineout2_se
) {
2535 snd_soc_dapm_disable_pin(&codec
->dapm
,
2536 "LINEOUT2N Driver");
2537 snd_soc_dapm_disable_pin(&codec
->dapm
,
2538 "LINEOUT2P Driver");
2541 /* Do the sync with the old mode to allow it to clean up */
2542 snd_soc_dapm_sync(&codec
->dapm
);
2543 wm8994
->vmid_mode
= mode
;
2546 case WM8994_VMID_FORCE
:
2547 if (wm8994
->hubs
.lineout1_se
) {
2548 snd_soc_dapm_force_enable_pin(&codec
->dapm
,
2549 "LINEOUT1N Driver");
2550 snd_soc_dapm_force_enable_pin(&codec
->dapm
,
2551 "LINEOUT1P Driver");
2553 if (wm8994
->hubs
.lineout2_se
) {
2554 snd_soc_dapm_force_enable_pin(&codec
->dapm
,
2555 "LINEOUT2N Driver");
2556 snd_soc_dapm_force_enable_pin(&codec
->dapm
,
2557 "LINEOUT2P Driver");
2560 wm8994
->vmid_mode
= mode
;
2561 snd_soc_dapm_sync(&codec
->dapm
);
2571 static int wm8994_set_dai_fmt(struct snd_soc_dai
*dai
, unsigned int fmt
)
2573 struct snd_soc_codec
*codec
= dai
->codec
;
2574 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2575 struct wm8994
*control
= wm8994
->wm8994
;
2586 ms_reg
= WM8994_AIF1_MASTER_SLAVE
;
2587 aif1_reg
= WM8994_AIF1_CONTROL_1
;
2588 dac_reg
= WM8994_AIF1DAC_LRCLK
;
2589 adc_reg
= WM8994_AIF1ADC_LRCLK
;
2592 ms_reg
= WM8994_AIF2_MASTER_SLAVE
;
2593 aif1_reg
= WM8994_AIF2_CONTROL_1
;
2594 dac_reg
= WM8994_AIF1DAC_LRCLK
;
2595 adc_reg
= WM8994_AIF1ADC_LRCLK
;
2601 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
2602 case SND_SOC_DAIFMT_CBS_CFS
:
2604 case SND_SOC_DAIFMT_CBM_CFM
:
2605 ms
= WM8994_AIF1_MSTR
;
2611 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
2612 case SND_SOC_DAIFMT_DSP_B
:
2613 aif1
|= WM8994_AIF1_LRCLK_INV
;
2614 lrclk
|= WM8958_AIF1_LRCLK_INV
;
2615 case SND_SOC_DAIFMT_DSP_A
:
2618 case SND_SOC_DAIFMT_I2S
:
2621 case SND_SOC_DAIFMT_RIGHT_J
:
2623 case SND_SOC_DAIFMT_LEFT_J
:
2630 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
2631 case SND_SOC_DAIFMT_DSP_A
:
2632 case SND_SOC_DAIFMT_DSP_B
:
2633 /* frame inversion not valid for DSP modes */
2634 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
2635 case SND_SOC_DAIFMT_NB_NF
:
2637 case SND_SOC_DAIFMT_IB_NF
:
2638 aif1
|= WM8994_AIF1_BCLK_INV
;
2645 case SND_SOC_DAIFMT_I2S
:
2646 case SND_SOC_DAIFMT_RIGHT_J
:
2647 case SND_SOC_DAIFMT_LEFT_J
:
2648 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
2649 case SND_SOC_DAIFMT_NB_NF
:
2651 case SND_SOC_DAIFMT_IB_IF
:
2652 aif1
|= WM8994_AIF1_BCLK_INV
| WM8994_AIF1_LRCLK_INV
;
2653 lrclk
|= WM8958_AIF1_LRCLK_INV
;
2655 case SND_SOC_DAIFMT_IB_NF
:
2656 aif1
|= WM8994_AIF1_BCLK_INV
;
2658 case SND_SOC_DAIFMT_NB_IF
:
2659 aif1
|= WM8994_AIF1_LRCLK_INV
;
2660 lrclk
|= WM8958_AIF1_LRCLK_INV
;
2670 /* The AIF2 format configuration needs to be mirrored to AIF3
2671 * on WM8958 if it's in use so just do it all the time. */
2672 switch (control
->type
) {
2676 snd_soc_update_bits(codec
, WM8958_AIF3_CONTROL_1
,
2677 WM8994_AIF1_LRCLK_INV
|
2678 WM8958_AIF3_FMT_MASK
, aif1
);
2685 snd_soc_update_bits(codec
, aif1_reg
,
2686 WM8994_AIF1_BCLK_INV
| WM8994_AIF1_LRCLK_INV
|
2687 WM8994_AIF1_FMT_MASK
,
2689 snd_soc_update_bits(codec
, ms_reg
, WM8994_AIF1_MSTR
,
2691 snd_soc_update_bits(codec
, dac_reg
,
2692 WM8958_AIF1_LRCLK_INV
, lrclk
);
2693 snd_soc_update_bits(codec
, adc_reg
,
2694 WM8958_AIF1_LRCLK_INV
, lrclk
);
2715 static int fs_ratios
[] = {
2716 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2719 static int bclk_divs
[] = {
2720 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2721 640, 880, 960, 1280, 1760, 1920
2724 static int wm8994_hw_params(struct snd_pcm_substream
*substream
,
2725 struct snd_pcm_hw_params
*params
,
2726 struct snd_soc_dai
*dai
)
2728 struct snd_soc_codec
*codec
= dai
->codec
;
2729 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2730 struct wm8994
*control
= wm8994
->wm8994
;
2731 struct wm8994_pdata
*pdata
= &control
->pdata
;
2742 int id
= dai
->id
- 1;
2744 int i
, cur_val
, best_val
, bclk_rate
, best
;
2748 aif1_reg
= WM8994_AIF1_CONTROL_1
;
2749 aif2_reg
= WM8994_AIF1_CONTROL_2
;
2750 bclk_reg
= WM8994_AIF1_BCLK
;
2751 rate_reg
= WM8994_AIF1_RATE
;
2752 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
||
2753 wm8994
->lrclk_shared
[0]) {
2754 lrclk_reg
= WM8994_AIF1DAC_LRCLK
;
2756 lrclk_reg
= WM8994_AIF1ADC_LRCLK
;
2757 dev_dbg(codec
->dev
, "AIF1 using split LRCLK\n");
2761 aif1_reg
= WM8994_AIF2_CONTROL_1
;
2762 aif2_reg
= WM8994_AIF2_CONTROL_2
;
2763 bclk_reg
= WM8994_AIF2_BCLK
;
2764 rate_reg
= WM8994_AIF2_RATE
;
2765 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
||
2766 wm8994
->lrclk_shared
[1]) {
2767 lrclk_reg
= WM8994_AIF2DAC_LRCLK
;
2769 lrclk_reg
= WM8994_AIF2ADC_LRCLK
;
2770 dev_dbg(codec
->dev
, "AIF2 using split LRCLK\n");
2777 bclk_rate
= params_rate(params
);
2778 switch (params_format(params
)) {
2779 case SNDRV_PCM_FORMAT_S16_LE
:
2782 case SNDRV_PCM_FORMAT_S20_3LE
:
2786 case SNDRV_PCM_FORMAT_S24_LE
:
2790 case SNDRV_PCM_FORMAT_S32_LE
:
2798 wm8994
->channels
[id
] = params_channels(params
);
2799 if (pdata
->max_channels_clocked
[id
] &&
2800 wm8994
->channels
[id
] > pdata
->max_channels_clocked
[id
]) {
2801 dev_dbg(dai
->dev
, "Constraining channels to %d from %d\n",
2802 pdata
->max_channels_clocked
[id
], wm8994
->channels
[id
]);
2803 wm8994
->channels
[id
] = pdata
->max_channels_clocked
[id
];
2806 switch (wm8994
->channels
[id
]) {
2816 /* Try to find an appropriate sample rate; look for an exact match. */
2817 for (i
= 0; i
< ARRAY_SIZE(srs
); i
++)
2818 if (srs
[i
].rate
== params_rate(params
))
2820 if (i
== ARRAY_SIZE(srs
))
2822 rate_val
|= srs
[i
].val
<< WM8994_AIF1_SR_SHIFT
;
2824 dev_dbg(dai
->dev
, "Sample rate is %dHz\n", srs
[i
].rate
);
2825 dev_dbg(dai
->dev
, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2826 dai
->id
, wm8994
->aifclk
[id
], bclk_rate
);
2828 if (wm8994
->channels
[id
] == 1 &&
2829 (snd_soc_read(codec
, aif1_reg
) & 0x18) == 0x18)
2830 aif2
|= WM8994_AIF1_MONO
;
2832 if (wm8994
->aifclk
[id
] == 0) {
2833 dev_err(dai
->dev
, "AIF%dCLK not configured\n", dai
->id
);
2837 /* AIFCLK/fs ratio; look for a close match in either direction */
2839 best_val
= abs((fs_ratios
[0] * params_rate(params
))
2840 - wm8994
->aifclk
[id
]);
2841 for (i
= 1; i
< ARRAY_SIZE(fs_ratios
); i
++) {
2842 cur_val
= abs((fs_ratios
[i
] * params_rate(params
))
2843 - wm8994
->aifclk
[id
]);
2844 if (cur_val
>= best_val
)
2849 dev_dbg(dai
->dev
, "Selected AIF%dCLK/fs = %d\n",
2850 dai
->id
, fs_ratios
[best
]);
2853 /* We may not get quite the right frequency if using
2854 * approximate clocks so look for the closest match that is
2855 * higher than the target (we need to ensure that there enough
2856 * BCLKs to clock out the samples).
2859 for (i
= 0; i
< ARRAY_SIZE(bclk_divs
); i
++) {
2860 cur_val
= (wm8994
->aifclk
[id
] * 10 / bclk_divs
[i
]) - bclk_rate
;
2861 if (cur_val
< 0) /* BCLK table is sorted */
2865 bclk_rate
= wm8994
->aifclk
[id
] * 10 / bclk_divs
[best
];
2866 dev_dbg(dai
->dev
, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2867 bclk_divs
[best
], bclk_rate
);
2868 bclk
|= best
<< WM8994_AIF1_BCLK_DIV_SHIFT
;
2870 lrclk
= bclk_rate
/ params_rate(params
);
2872 dev_err(dai
->dev
, "Unable to generate LRCLK from %dHz BCLK\n",
2876 dev_dbg(dai
->dev
, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2877 lrclk
, bclk_rate
/ lrclk
);
2879 snd_soc_update_bits(codec
, aif1_reg
, WM8994_AIF1_WL_MASK
, aif1
);
2880 snd_soc_update_bits(codec
, aif2_reg
, WM8994_AIF1_MONO
, aif2
);
2881 snd_soc_update_bits(codec
, bclk_reg
, WM8994_AIF1_BCLK_DIV_MASK
, bclk
);
2882 snd_soc_update_bits(codec
, lrclk_reg
, WM8994_AIF1DAC_RATE_MASK
,
2884 snd_soc_update_bits(codec
, rate_reg
, WM8994_AIF1_SR_MASK
|
2885 WM8994_AIF1CLK_RATE_MASK
, rate_val
);
2887 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
2890 wm8994
->dac_rates
[0] = params_rate(params
);
2891 wm8994_set_retune_mobile(codec
, 0);
2892 wm8994_set_retune_mobile(codec
, 1);
2895 wm8994
->dac_rates
[1] = params_rate(params
);
2896 wm8994_set_retune_mobile(codec
, 2);
2904 static int wm8994_aif3_hw_params(struct snd_pcm_substream
*substream
,
2905 struct snd_pcm_hw_params
*params
,
2906 struct snd_soc_dai
*dai
)
2908 struct snd_soc_codec
*codec
= dai
->codec
;
2909 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2910 struct wm8994
*control
= wm8994
->wm8994
;
2916 switch (control
->type
) {
2919 aif1_reg
= WM8958_AIF3_CONTROL_1
;
2929 switch (params_format(params
)) {
2930 case SNDRV_PCM_FORMAT_S16_LE
:
2932 case SNDRV_PCM_FORMAT_S20_3LE
:
2935 case SNDRV_PCM_FORMAT_S24_LE
:
2938 case SNDRV_PCM_FORMAT_S32_LE
:
2945 return snd_soc_update_bits(codec
, aif1_reg
, WM8994_AIF1_WL_MASK
, aif1
);
2948 static int wm8994_aif_mute(struct snd_soc_dai
*codec_dai
, int mute
)
2950 struct snd_soc_codec
*codec
= codec_dai
->codec
;
2954 switch (codec_dai
->id
) {
2956 mute_reg
= WM8994_AIF1_DAC1_FILTERS_1
;
2959 mute_reg
= WM8994_AIF2_DAC_FILTERS_1
;
2966 reg
= WM8994_AIF1DAC1_MUTE
;
2970 snd_soc_update_bits(codec
, mute_reg
, WM8994_AIF1DAC1_MUTE
, reg
);
2975 static int wm8994_set_tristate(struct snd_soc_dai
*codec_dai
, int tristate
)
2977 struct snd_soc_codec
*codec
= codec_dai
->codec
;
2980 switch (codec_dai
->id
) {
2982 reg
= WM8994_AIF1_MASTER_SLAVE
;
2983 mask
= WM8994_AIF1_TRI
;
2986 reg
= WM8994_AIF2_MASTER_SLAVE
;
2987 mask
= WM8994_AIF2_TRI
;
2998 return snd_soc_update_bits(codec
, reg
, mask
, val
);
3001 static int wm8994_aif2_probe(struct snd_soc_dai
*dai
)
3003 struct snd_soc_codec
*codec
= dai
->codec
;
3005 /* Disable the pulls on the AIF if we're using it to save power. */
3006 snd_soc_update_bits(codec
, WM8994_GPIO_3
,
3007 WM8994_GPN_PU
| WM8994_GPN_PD
, 0);
3008 snd_soc_update_bits(codec
, WM8994_GPIO_4
,
3009 WM8994_GPN_PU
| WM8994_GPN_PD
, 0);
3010 snd_soc_update_bits(codec
, WM8994_GPIO_5
,
3011 WM8994_GPN_PU
| WM8994_GPN_PD
, 0);
3016 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
3018 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3019 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
3021 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops
= {
3022 .set_sysclk
= wm8994_set_dai_sysclk
,
3023 .set_fmt
= wm8994_set_dai_fmt
,
3024 .hw_params
= wm8994_hw_params
,
3025 .digital_mute
= wm8994_aif_mute
,
3026 .set_pll
= wm8994_set_fll
,
3027 .set_tristate
= wm8994_set_tristate
,
3030 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops
= {
3031 .set_sysclk
= wm8994_set_dai_sysclk
,
3032 .set_fmt
= wm8994_set_dai_fmt
,
3033 .hw_params
= wm8994_hw_params
,
3034 .digital_mute
= wm8994_aif_mute
,
3035 .set_pll
= wm8994_set_fll
,
3036 .set_tristate
= wm8994_set_tristate
,
3039 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops
= {
3040 .hw_params
= wm8994_aif3_hw_params
,
3043 static struct snd_soc_dai_driver wm8994_dai
[] = {
3045 .name
= "wm8994-aif1",
3048 .stream_name
= "AIF1 Playback",
3051 .rates
= WM8994_RATES
,
3052 .formats
= WM8994_FORMATS
,
3056 .stream_name
= "AIF1 Capture",
3059 .rates
= WM8994_RATES
,
3060 .formats
= WM8994_FORMATS
,
3063 .ops
= &wm8994_aif1_dai_ops
,
3066 .name
= "wm8994-aif2",
3069 .stream_name
= "AIF2 Playback",
3072 .rates
= WM8994_RATES
,
3073 .formats
= WM8994_FORMATS
,
3077 .stream_name
= "AIF2 Capture",
3080 .rates
= WM8994_RATES
,
3081 .formats
= WM8994_FORMATS
,
3084 .probe
= wm8994_aif2_probe
,
3085 .ops
= &wm8994_aif2_dai_ops
,
3088 .name
= "wm8994-aif3",
3091 .stream_name
= "AIF3 Playback",
3094 .rates
= WM8994_RATES
,
3095 .formats
= WM8994_FORMATS
,
3099 .stream_name
= "AIF3 Capture",
3102 .rates
= WM8994_RATES
,
3103 .formats
= WM8994_FORMATS
,
3106 .ops
= &wm8994_aif3_dai_ops
,
3111 static int wm8994_codec_suspend(struct snd_soc_codec
*codec
)
3113 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3116 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll
); i
++) {
3117 memcpy(&wm8994
->fll_suspend
[i
], &wm8994
->fll
[i
],
3118 sizeof(struct wm8994_fll_config
));
3119 ret
= _wm8994_set_fll(codec
, i
+ 1, 0, 0, 0);
3121 dev_warn(codec
->dev
, "Failed to stop FLL%d: %d\n",
3125 wm8994_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
3130 static int wm8994_codec_resume(struct snd_soc_codec
*codec
)
3132 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3133 struct wm8994
*control
= wm8994
->wm8994
;
3136 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll
); i
++) {
3137 if (!wm8994
->fll_suspend
[i
].out
)
3140 ret
= _wm8994_set_fll(codec
, i
+ 1,
3141 wm8994
->fll_suspend
[i
].src
,
3142 wm8994
->fll_suspend
[i
].in
,
3143 wm8994
->fll_suspend
[i
].out
);
3145 dev_warn(codec
->dev
, "Failed to restore FLL%d: %d\n",
3152 #define wm8994_codec_suspend NULL
3153 #define wm8994_codec_resume NULL
3156 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv
*wm8994
)
3158 struct snd_soc_codec
*codec
= wm8994
->hubs
.codec
;
3159 struct wm8994
*control
= wm8994
->wm8994
;
3160 struct wm8994_pdata
*pdata
= &control
->pdata
;
3161 struct snd_kcontrol_new controls
[] = {
3162 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3163 wm8994
->retune_mobile_enum
,
3164 wm8994_get_retune_mobile_enum
,
3165 wm8994_put_retune_mobile_enum
),
3166 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3167 wm8994
->retune_mobile_enum
,
3168 wm8994_get_retune_mobile_enum
,
3169 wm8994_put_retune_mobile_enum
),
3170 SOC_ENUM_EXT("AIF2 EQ Mode",
3171 wm8994
->retune_mobile_enum
,
3172 wm8994_get_retune_mobile_enum
,
3173 wm8994_put_retune_mobile_enum
),
3178 /* We need an array of texts for the enum API but the number
3179 * of texts is likely to be less than the number of
3180 * configurations due to the sample rate dependency of the
3181 * configurations. */
3182 wm8994
->num_retune_mobile_texts
= 0;
3183 wm8994
->retune_mobile_texts
= NULL
;
3184 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
3185 for (j
= 0; j
< wm8994
->num_retune_mobile_texts
; j
++) {
3186 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
3187 wm8994
->retune_mobile_texts
[j
]) == 0)
3191 if (j
!= wm8994
->num_retune_mobile_texts
)
3194 /* Expand the array... */
3195 t
= krealloc(wm8994
->retune_mobile_texts
,
3197 (wm8994
->num_retune_mobile_texts
+ 1),
3202 /* ...store the new entry... */
3203 t
[wm8994
->num_retune_mobile_texts
] =
3204 pdata
->retune_mobile_cfgs
[i
].name
;
3206 /* ...and remember the new version. */
3207 wm8994
->num_retune_mobile_texts
++;
3208 wm8994
->retune_mobile_texts
= t
;
3211 dev_dbg(codec
->dev
, "Allocated %d unique ReTune Mobile names\n",
3212 wm8994
->num_retune_mobile_texts
);
3214 wm8994
->retune_mobile_enum
.max
= wm8994
->num_retune_mobile_texts
;
3215 wm8994
->retune_mobile_enum
.texts
= wm8994
->retune_mobile_texts
;
3217 ret
= snd_soc_add_codec_controls(wm8994
->hubs
.codec
, controls
,
3218 ARRAY_SIZE(controls
));
3220 dev_err(wm8994
->hubs
.codec
->dev
,
3221 "Failed to add ReTune Mobile controls: %d\n", ret
);
3224 static void wm8994_handle_pdata(struct wm8994_priv
*wm8994
)
3226 struct snd_soc_codec
*codec
= wm8994
->hubs
.codec
;
3227 struct wm8994
*control
= wm8994
->wm8994
;
3228 struct wm8994_pdata
*pdata
= &control
->pdata
;
3234 wm_hubs_handle_analogue_pdata(codec
, pdata
->lineout1_diff
,
3235 pdata
->lineout2_diff
,
3242 pdata
->micbias1_lvl
,
3243 pdata
->micbias2_lvl
);
3245 dev_dbg(codec
->dev
, "%d DRC configurations\n", pdata
->num_drc_cfgs
);
3247 if (pdata
->num_drc_cfgs
) {
3248 struct snd_kcontrol_new controls
[] = {
3249 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994
->drc_enum
,
3250 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
3251 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994
->drc_enum
,
3252 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
3253 SOC_ENUM_EXT("AIF2DRC Mode", wm8994
->drc_enum
,
3254 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
3257 /* We need an array of texts for the enum API */
3258 wm8994
->drc_texts
= devm_kzalloc(wm8994
->hubs
.codec
->dev
,
3259 sizeof(char *) * pdata
->num_drc_cfgs
, GFP_KERNEL
);
3260 if (!wm8994
->drc_texts
) {
3261 dev_err(wm8994
->hubs
.codec
->dev
,
3262 "Failed to allocate %d DRC config texts\n",
3263 pdata
->num_drc_cfgs
);
3267 for (i
= 0; i
< pdata
->num_drc_cfgs
; i
++)
3268 wm8994
->drc_texts
[i
] = pdata
->drc_cfgs
[i
].name
;
3270 wm8994
->drc_enum
.max
= pdata
->num_drc_cfgs
;
3271 wm8994
->drc_enum
.texts
= wm8994
->drc_texts
;
3273 ret
= snd_soc_add_codec_controls(wm8994
->hubs
.codec
, controls
,
3274 ARRAY_SIZE(controls
));
3275 for (i
= 0; i
< WM8994_NUM_DRC
; i
++)
3276 wm8994_set_drc(codec
, i
);
3278 ret
= snd_soc_add_codec_controls(wm8994
->hubs
.codec
,
3279 wm8994_drc_controls
,
3280 ARRAY_SIZE(wm8994_drc_controls
));
3284 dev_err(wm8994
->hubs
.codec
->dev
,
3285 "Failed to add DRC mode controls: %d\n", ret
);
3288 dev_dbg(codec
->dev
, "%d ReTune Mobile configurations\n",
3289 pdata
->num_retune_mobile_cfgs
);
3291 if (pdata
->num_retune_mobile_cfgs
)
3292 wm8994_handle_retune_mobile_pdata(wm8994
);
3294 snd_soc_add_codec_controls(wm8994
->hubs
.codec
, wm8994_eq_controls
,
3295 ARRAY_SIZE(wm8994_eq_controls
));
3297 for (i
= 0; i
< ARRAY_SIZE(pdata
->micbias
); i
++) {
3298 if (pdata
->micbias
[i
]) {
3299 snd_soc_write(codec
, WM8958_MICBIAS1
+ i
,
3300 pdata
->micbias
[i
] & 0xffff);
3306 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3308 * @codec: WM8994 codec
3309 * @jack: jack to report detection events on
3310 * @micbias: microphone bias to detect on
3312 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3313 * being used to bring out signals to the processor then only platform
3314 * data configuration is needed for WM8994 and processor GPIOs should
3315 * be configured using snd_soc_jack_add_gpios() instead.
3317 * Configuration of detection levels is available via the micbias1_lvl
3318 * and micbias2_lvl platform data members.
3320 int wm8994_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
3323 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3324 struct wm8994_micdet
*micdet
;
3325 struct wm8994
*control
= wm8994
->wm8994
;
3328 if (control
->type
!= WM8994
) {
3329 dev_warn(codec
->dev
, "Not a WM8994\n");
3335 micdet
= &wm8994
->micdet
[0];
3337 ret
= snd_soc_dapm_force_enable_pin(&codec
->dapm
,
3340 ret
= snd_soc_dapm_disable_pin(&codec
->dapm
,
3344 micdet
= &wm8994
->micdet
[1];
3346 ret
= snd_soc_dapm_force_enable_pin(&codec
->dapm
,
3349 ret
= snd_soc_dapm_disable_pin(&codec
->dapm
,
3353 dev_warn(codec
->dev
, "Invalid MICBIAS %d\n", micbias
);
3358 dev_warn(codec
->dev
, "Failed to configure MICBIAS%d: %d\n",
3361 dev_dbg(codec
->dev
, "Configuring microphone detection on %d %p\n",
3364 /* Store the configuration */
3365 micdet
->jack
= jack
;
3366 micdet
->detecting
= true;
3368 /* If either of the jacks is set up then enable detection */
3369 if (wm8994
->micdet
[0].jack
|| wm8994
->micdet
[1].jack
)
3370 reg
= WM8994_MICD_ENA
;
3374 snd_soc_update_bits(codec
, WM8994_MICBIAS
, WM8994_MICD_ENA
, reg
);
3376 /* enable MICDET and MICSHRT deboune */
3377 snd_soc_update_bits(codec
, WM8994_IRQ_DEBOUNCE
,
3378 WM8994_MIC1_DET_DB_MASK
| WM8994_MIC1_SHRT_DB_MASK
|
3379 WM8994_MIC2_DET_DB_MASK
| WM8994_MIC2_SHRT_DB_MASK
,
3380 WM8994_MIC1_DET_DB
| WM8994_MIC1_SHRT_DB
);
3382 snd_soc_dapm_sync(&codec
->dapm
);
3386 EXPORT_SYMBOL_GPL(wm8994_mic_detect
);
3388 static void wm8994_mic_work(struct work_struct
*work
)
3390 struct wm8994_priv
*priv
= container_of(work
,
3393 struct regmap
*regmap
= priv
->wm8994
->regmap
;
3394 struct device
*dev
= priv
->wm8994
->dev
;
3399 pm_runtime_get_sync(dev
);
3401 ret
= regmap_read(regmap
, WM8994_INTERRUPT_RAW_STATUS_2
, ®
);
3403 dev_err(dev
, "Failed to read microphone status: %d\n",
3405 pm_runtime_put(dev
);
3409 dev_dbg(dev
, "Microphone status: %x\n", reg
);
3412 if (reg
& WM8994_MIC1_DET_STS
) {
3413 if (priv
->micdet
[0].detecting
)
3414 report
= SND_JACK_HEADSET
;
3416 if (reg
& WM8994_MIC1_SHRT_STS
) {
3417 if (priv
->micdet
[0].detecting
)
3418 report
= SND_JACK_HEADPHONE
;
3420 report
|= SND_JACK_BTN_0
;
3423 priv
->micdet
[0].detecting
= false;
3425 priv
->micdet
[0].detecting
= true;
3427 snd_soc_jack_report(priv
->micdet
[0].jack
, report
,
3428 SND_JACK_HEADSET
| SND_JACK_BTN_0
);
3431 if (reg
& WM8994_MIC2_DET_STS
) {
3432 if (priv
->micdet
[1].detecting
)
3433 report
= SND_JACK_HEADSET
;
3435 if (reg
& WM8994_MIC2_SHRT_STS
) {
3436 if (priv
->micdet
[1].detecting
)
3437 report
= SND_JACK_HEADPHONE
;
3439 report
|= SND_JACK_BTN_0
;
3442 priv
->micdet
[1].detecting
= false;
3444 priv
->micdet
[1].detecting
= true;
3446 snd_soc_jack_report(priv
->micdet
[1].jack
, report
,
3447 SND_JACK_HEADSET
| SND_JACK_BTN_0
);
3449 pm_runtime_put(dev
);
3452 static irqreturn_t
wm8994_mic_irq(int irq
, void *data
)
3454 struct wm8994_priv
*priv
= data
;
3455 struct snd_soc_codec
*codec
= priv
->hubs
.codec
;
3457 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3458 trace_snd_soc_jack_irq(dev_name(codec
->dev
));
3461 pm_wakeup_event(codec
->dev
, 300);
3463 schedule_delayed_work(&priv
->mic_work
, msecs_to_jiffies(250));
3468 static void wm1811_micd_stop(struct snd_soc_codec
*codec
)
3470 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3472 if (!wm8994
->jackdet
)
3475 mutex_lock(&wm8994
->accdet_lock
);
3477 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
, WM8958_MICD_ENA
, 0);
3479 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_JACK
);
3481 mutex_unlock(&wm8994
->accdet_lock
);
3483 if (wm8994
->wm8994
->pdata
.jd_ext_cap
)
3484 snd_soc_dapm_disable_pin(&codec
->dapm
,
3488 static void wm8958_button_det(struct snd_soc_codec
*codec
, u16 status
)
3490 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3495 report
|= SND_JACK_BTN_0
;
3498 report
|= SND_JACK_BTN_1
;
3501 report
|= SND_JACK_BTN_2
;
3504 report
|= SND_JACK_BTN_3
;
3507 report
|= SND_JACK_BTN_4
;
3510 report
|= SND_JACK_BTN_5
;
3512 snd_soc_jack_report(wm8994
->micdet
[0].jack
, report
,
3516 static void wm8958_mic_id(void *data
, u16 status
)
3518 struct snd_soc_codec
*codec
= data
;
3519 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3521 /* Either nothing present or just starting detection */
3522 if (!(status
& WM8958_MICD_STS
)) {
3523 /* If nothing present then clear our statuses */
3524 dev_dbg(codec
->dev
, "Detected open circuit\n");
3525 wm8994
->jack_mic
= false;
3526 wm8994
->mic_detecting
= true;
3528 wm1811_micd_stop(codec
);
3530 wm8958_micd_set_rate(codec
);
3532 snd_soc_jack_report(wm8994
->micdet
[0].jack
, 0,
3538 /* If the measurement is showing a high impedence we've got a
3541 if (status
& 0x600) {
3542 dev_dbg(codec
->dev
, "Detected microphone\n");
3544 wm8994
->mic_detecting
= false;
3545 wm8994
->jack_mic
= true;
3547 wm8958_micd_set_rate(codec
);
3549 snd_soc_jack_report(wm8994
->micdet
[0].jack
, SND_JACK_HEADSET
,
3554 if (status
& 0xfc) {
3555 dev_dbg(codec
->dev
, "Detected headphone\n");
3556 wm8994
->mic_detecting
= false;
3558 wm8958_micd_set_rate(codec
);
3560 /* If we have jackdet that will detect removal */
3561 wm1811_micd_stop(codec
);
3563 snd_soc_jack_report(wm8994
->micdet
[0].jack
, SND_JACK_HEADPHONE
,
3568 /* Deferred mic detection to allow for extra settling time */
3569 static void wm1811_mic_work(struct work_struct
*work
)
3571 struct wm8994_priv
*wm8994
= container_of(work
, struct wm8994_priv
,
3573 struct wm8994
*control
= wm8994
->wm8994
;
3574 struct snd_soc_codec
*codec
= wm8994
->hubs
.codec
;
3576 pm_runtime_get_sync(codec
->dev
);
3578 /* If required for an external cap force MICBIAS on */
3579 if (control
->pdata
.jd_ext_cap
) {
3580 snd_soc_dapm_force_enable_pin(&codec
->dapm
,
3582 snd_soc_dapm_sync(&codec
->dapm
);
3585 mutex_lock(&wm8994
->accdet_lock
);
3587 dev_dbg(codec
->dev
, "Starting mic detection\n");
3589 /* Use a user-supplied callback if we have one */
3590 if (wm8994
->micd_cb
) {
3591 wm8994
->micd_cb(wm8994
->micd_cb_data
);
3594 * Start off measument of microphone impedence to find out
3595 * what's actually there.
3597 wm8994
->mic_detecting
= true;
3598 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_MIC
);
3600 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3601 WM8958_MICD_ENA
, WM8958_MICD_ENA
);
3604 mutex_unlock(&wm8994
->accdet_lock
);
3606 pm_runtime_put(codec
->dev
);
3609 static irqreturn_t
wm1811_jackdet_irq(int irq
, void *data
)
3611 struct wm8994_priv
*wm8994
= data
;
3612 struct wm8994
*control
= wm8994
->wm8994
;
3613 struct snd_soc_codec
*codec
= wm8994
->hubs
.codec
;
3617 pm_runtime_get_sync(codec
->dev
);
3619 mutex_lock(&wm8994
->accdet_lock
);
3621 reg
= snd_soc_read(codec
, WM1811_JACKDET_CTRL
);
3623 dev_err(codec
->dev
, "Failed to read jack status: %d\n", reg
);
3624 mutex_unlock(&wm8994
->accdet_lock
);
3625 pm_runtime_put(codec
->dev
);
3629 dev_dbg(codec
->dev
, "JACKDET %x\n", reg
);
3631 present
= reg
& WM1811_JACKDET_LVL
;
3634 dev_dbg(codec
->dev
, "Jack detected\n");
3636 wm8958_micd_set_rate(codec
);
3638 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
3639 WM8958_MICB2_DISCH
, 0);
3641 /* Disable debounce while inserted */
3642 snd_soc_update_bits(codec
, WM1811_JACKDET_CTRL
,
3643 WM1811_JACKDET_DB
, 0);
3645 delay
= control
->pdata
.micdet_delay
;
3646 schedule_delayed_work(&wm8994
->mic_work
,
3647 msecs_to_jiffies(delay
));
3649 dev_dbg(codec
->dev
, "Jack not detected\n");
3651 cancel_delayed_work_sync(&wm8994
->mic_work
);
3653 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
3654 WM8958_MICB2_DISCH
, WM8958_MICB2_DISCH
);
3656 /* Enable debounce while removed */
3657 snd_soc_update_bits(codec
, WM1811_JACKDET_CTRL
,
3658 WM1811_JACKDET_DB
, WM1811_JACKDET_DB
);
3660 wm8994
->mic_detecting
= false;
3661 wm8994
->jack_mic
= false;
3662 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3663 WM8958_MICD_ENA
, 0);
3664 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_JACK
);
3667 mutex_unlock(&wm8994
->accdet_lock
);
3669 /* Turn off MICBIAS if it was on for an external cap */
3670 if (control
->pdata
.jd_ext_cap
&& !present
)
3671 snd_soc_dapm_disable_pin(&codec
->dapm
, "MICBIAS2");
3674 snd_soc_jack_report(wm8994
->micdet
[0].jack
,
3675 SND_JACK_MECHANICAL
, SND_JACK_MECHANICAL
);
3677 snd_soc_jack_report(wm8994
->micdet
[0].jack
, 0,
3678 SND_JACK_MECHANICAL
| SND_JACK_HEADSET
|
3681 /* Since we only report deltas force an update, ensures we
3682 * avoid bootstrapping issues with the core. */
3683 snd_soc_jack_report(wm8994
->micdet
[0].jack
, 0, 0);
3685 pm_runtime_put(codec
->dev
);
3689 static void wm1811_jackdet_bootstrap(struct work_struct
*work
)
3691 struct wm8994_priv
*wm8994
= container_of(work
,
3693 jackdet_bootstrap
.work
);
3694 wm1811_jackdet_irq(0, wm8994
);
3698 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3700 * @codec: WM8958 codec
3701 * @jack: jack to report detection events on
3703 * Enable microphone detection functionality for the WM8958. By
3704 * default simple detection which supports the detection of up to 6
3705 * buttons plus video and microphone functionality is supported.
3707 * The WM8958 has an advanced jack detection facility which is able to
3708 * support complex accessory detection, especially when used in
3709 * conjunction with external circuitry. In order to provide maximum
3710 * flexiblity a callback is provided which allows a completely custom
3711 * detection algorithm.
3713 int wm8958_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
3714 wm1811_micdet_cb det_cb
, void *det_cb_data
,
3715 wm1811_mic_id_cb id_cb
, void *id_cb_data
)
3717 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3718 struct wm8994
*control
= wm8994
->wm8994
;
3721 switch (control
->type
) {
3730 snd_soc_dapm_force_enable_pin(&codec
->dapm
, "CLK_SYS");
3731 snd_soc_dapm_sync(&codec
->dapm
);
3733 wm8994
->micdet
[0].jack
= jack
;
3736 wm8994
->micd_cb
= det_cb
;
3737 wm8994
->micd_cb_data
= det_cb_data
;
3739 wm8994
->mic_detecting
= true;
3740 wm8994
->jack_mic
= false;
3744 wm8994
->mic_id_cb
= id_cb
;
3745 wm8994
->mic_id_cb_data
= id_cb_data
;
3747 wm8994
->mic_id_cb
= wm8958_mic_id
;
3748 wm8994
->mic_id_cb_data
= codec
;
3751 wm8958_micd_set_rate(codec
);
3753 /* Detect microphones and short circuits by default */
3754 if (control
->pdata
.micd_lvl_sel
)
3755 micd_lvl_sel
= control
->pdata
.micd_lvl_sel
;
3757 micd_lvl_sel
= 0x41;
3759 wm8994
->btn_mask
= SND_JACK_BTN_0
| SND_JACK_BTN_1
|
3760 SND_JACK_BTN_2
| SND_JACK_BTN_3
|
3761 SND_JACK_BTN_4
| SND_JACK_BTN_5
;
3763 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_2
,
3764 WM8958_MICD_LVL_SEL_MASK
, micd_lvl_sel
);
3766 WARN_ON(codec
->dapm
.bias_level
> SND_SOC_BIAS_STANDBY
);
3769 * If we can use jack detection start off with that,
3770 * otherwise jump straight to microphone detection.
3772 if (wm8994
->jackdet
) {
3773 /* Disable debounce for the initial detect */
3774 snd_soc_update_bits(codec
, WM1811_JACKDET_CTRL
,
3775 WM1811_JACKDET_DB
, 0);
3777 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
3779 WM8958_MICB2_DISCH
);
3780 snd_soc_update_bits(codec
, WM8994_LDO_1
,
3781 WM8994_LDO1_DISCH
, 0);
3782 wm1811_jackdet_set_mode(codec
,
3783 WM1811_JACKDET_MODE_JACK
);
3785 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3786 WM8958_MICD_ENA
, WM8958_MICD_ENA
);
3790 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3791 WM8958_MICD_ENA
, 0);
3792 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_NONE
);
3793 snd_soc_dapm_disable_pin(&codec
->dapm
, "CLK_SYS");
3794 snd_soc_dapm_sync(&codec
->dapm
);
3799 EXPORT_SYMBOL_GPL(wm8958_mic_detect
);
3801 static irqreturn_t
wm8958_mic_irq(int irq
, void *data
)
3803 struct wm8994_priv
*wm8994
= data
;
3804 struct snd_soc_codec
*codec
= wm8994
->hubs
.codec
;
3805 int reg
, count
, ret
;
3808 * Jack detection may have detected a removal simulataneously
3809 * with an update of the MICDET status; if so it will have
3810 * stopped detection and we can ignore this interrupt.
3812 if (!(snd_soc_read(codec
, WM8958_MIC_DETECT_1
) & WM8958_MICD_ENA
))
3815 pm_runtime_get_sync(codec
->dev
);
3817 /* We may occasionally read a detection without an impedence
3818 * range being provided - if that happens loop again.
3822 reg
= snd_soc_read(codec
, WM8958_MIC_DETECT_3
);
3825 "Failed to read mic detect status: %d\n",
3827 pm_runtime_put(codec
->dev
);
3831 if (!(reg
& WM8958_MICD_VALID
)) {
3832 dev_dbg(codec
->dev
, "Mic detect data not valid\n");
3836 if (!(reg
& WM8958_MICD_STS
) || (reg
& WM8958_MICD_LVL_MASK
))
3843 dev_warn(codec
->dev
, "No impedance range reported for jack\n");
3845 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3846 trace_snd_soc_jack_irq(dev_name(codec
->dev
));
3849 /* Avoid a transient report when the accessory is being removed */
3850 if (wm8994
->jackdet
) {
3851 ret
= snd_soc_read(codec
, WM1811_JACKDET_CTRL
);
3853 dev_err(codec
->dev
, "Failed to read jack status: %d\n",
3855 } else if (!(ret
& WM1811_JACKDET_LVL
)) {
3856 dev_dbg(codec
->dev
, "Ignoring removed jack\n");
3861 if (wm8994
->mic_detecting
)
3862 wm8994
->mic_id_cb(wm8994
->mic_id_cb_data
, reg
);
3864 wm8958_button_det(codec
, reg
);
3867 pm_runtime_put(codec
->dev
);
3871 static irqreturn_t
wm8994_fifo_error(int irq
, void *data
)
3873 struct snd_soc_codec
*codec
= data
;
3875 dev_err(codec
->dev
, "FIFO error\n");
3880 static irqreturn_t
wm8994_temp_warn(int irq
, void *data
)
3882 struct snd_soc_codec
*codec
= data
;
3884 dev_err(codec
->dev
, "Thermal warning\n");
3889 static irqreturn_t
wm8994_temp_shut(int irq
, void *data
)
3891 struct snd_soc_codec
*codec
= data
;
3893 dev_crit(codec
->dev
, "Thermal shutdown\n");
3898 static int wm8994_codec_probe(struct snd_soc_codec
*codec
)
3900 struct wm8994
*control
= dev_get_drvdata(codec
->dev
->parent
);
3901 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3902 struct snd_soc_dapm_context
*dapm
= &codec
->dapm
;
3906 wm8994
->hubs
.codec
= codec
;
3907 codec
->control_data
= control
->regmap
;
3909 snd_soc_codec_set_cache_io(codec
, 16, 16, SND_SOC_REGMAP
);
3911 mutex_init(&wm8994
->accdet_lock
);
3912 INIT_DELAYED_WORK(&wm8994
->jackdet_bootstrap
,
3913 wm1811_jackdet_bootstrap
);
3915 switch (control
->type
) {
3917 INIT_DELAYED_WORK(&wm8994
->mic_work
, wm8994_mic_work
);
3920 INIT_DELAYED_WORK(&wm8994
->mic_work
, wm1811_mic_work
);
3926 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++)
3927 init_completion(&wm8994
->fll_locked
[i
]);
3929 wm8994
->micdet_irq
= control
->pdata
.micdet_irq
;
3931 pm_runtime_enable(codec
->dev
);
3932 pm_runtime_idle(codec
->dev
);
3934 /* By default use idle_bias_off, will override for WM8994 */
3935 codec
->dapm
.idle_bias_off
= 1;
3937 /* Set revision-specific configuration */
3938 switch (control
->type
) {
3940 /* Single ended line outputs should have VMID on. */
3941 if (!control
->pdata
.lineout1_diff
||
3942 !control
->pdata
.lineout2_diff
)
3943 codec
->dapm
.idle_bias_off
= 0;
3945 switch (control
->revision
) {
3948 wm8994
->hubs
.dcs_codes_l
= -5;
3949 wm8994
->hubs
.dcs_codes_r
= -5;
3950 wm8994
->hubs
.hp_startup_mode
= 1;
3951 wm8994
->hubs
.dcs_readback_mode
= 1;
3952 wm8994
->hubs
.series_startup
= 1;
3955 wm8994
->hubs
.dcs_readback_mode
= 2;
3961 wm8994
->hubs
.dcs_readback_mode
= 1;
3962 wm8994
->hubs
.hp_startup_mode
= 1;
3964 switch (control
->revision
) {
3968 wm8994
->fll_byp
= true;
3974 wm8994
->hubs
.dcs_readback_mode
= 2;
3975 wm8994
->hubs
.no_series_update
= 1;
3976 wm8994
->hubs
.hp_startup_mode
= 1;
3977 wm8994
->hubs
.no_cache_dac_hp_direct
= true;
3978 wm8994
->fll_byp
= true;
3980 wm8994
->hubs
.dcs_codes_l
= -9;
3981 wm8994
->hubs
.dcs_codes_r
= -7;
3983 snd_soc_update_bits(codec
, WM8994_ANALOGUE_HP_1
,
3984 WM1811_HPOUT1_ATTN
, WM1811_HPOUT1_ATTN
);
3991 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_FIFOS_ERR
,
3992 wm8994_fifo_error
, "FIFO error", codec
);
3993 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_WARN
,
3994 wm8994_temp_warn
, "Thermal warning", codec
);
3995 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_SHUT
,
3996 wm8994_temp_shut
, "Thermal shutdown", codec
);
3998 ret
= wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_DCS_DONE
,
3999 wm_hubs_dcs_done
, "DC servo done",
4002 wm8994
->hubs
.dcs_done_irq
= true;
4004 switch (control
->type
) {
4006 if (wm8994
->micdet_irq
) {
4007 ret
= request_threaded_irq(wm8994
->micdet_irq
, NULL
,
4009 IRQF_TRIGGER_RISING
,
4013 dev_warn(codec
->dev
,
4014 "Failed to request Mic1 detect IRQ: %d\n",
4018 ret
= wm8994_request_irq(wm8994
->wm8994
,
4019 WM8994_IRQ_MIC1_SHRT
,
4020 wm8994_mic_irq
, "Mic 1 short",
4023 dev_warn(codec
->dev
,
4024 "Failed to request Mic1 short IRQ: %d\n",
4027 ret
= wm8994_request_irq(wm8994
->wm8994
,
4028 WM8994_IRQ_MIC2_DET
,
4029 wm8994_mic_irq
, "Mic 2 detect",
4032 dev_warn(codec
->dev
,
4033 "Failed to request Mic2 detect IRQ: %d\n",
4036 ret
= wm8994_request_irq(wm8994
->wm8994
,
4037 WM8994_IRQ_MIC2_SHRT
,
4038 wm8994_mic_irq
, "Mic 2 short",
4041 dev_warn(codec
->dev
,
4042 "Failed to request Mic2 short IRQ: %d\n",
4048 if (wm8994
->micdet_irq
) {
4049 ret
= request_threaded_irq(wm8994
->micdet_irq
, NULL
,
4051 IRQF_TRIGGER_RISING
,
4055 dev_warn(codec
->dev
,
4056 "Failed to request Mic detect IRQ: %d\n",
4059 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_DET
,
4060 wm8958_mic_irq
, "Mic detect",
4065 switch (control
->type
) {
4067 if (control
->cust_id
> 1 || control
->revision
> 1) {
4068 ret
= wm8994_request_irq(wm8994
->wm8994
,
4070 wm1811_jackdet_irq
, "JACKDET",
4073 wm8994
->jackdet
= true;
4080 wm8994
->fll_locked_irq
= true;
4081 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++) {
4082 ret
= wm8994_request_irq(wm8994
->wm8994
,
4083 WM8994_IRQ_FLL1_LOCK
+ i
,
4084 wm8994_fll_locked_irq
, "FLL lock",
4085 &wm8994
->fll_locked
[i
]);
4087 wm8994
->fll_locked_irq
= false;
4090 /* Make sure we can read from the GPIOs if they're inputs */
4091 pm_runtime_get_sync(codec
->dev
);
4093 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
4094 * configured on init - if a system wants to do this dynamically
4095 * at runtime we can deal with that then.
4097 ret
= regmap_read(control
->regmap
, WM8994_GPIO_1
, ®
);
4099 dev_err(codec
->dev
, "Failed to read GPIO1 state: %d\n", ret
);
4102 if ((reg
& WM8994_GPN_FN_MASK
) != WM8994_GP_FN_PIN_SPECIFIC
) {
4103 wm8994
->lrclk_shared
[0] = 1;
4104 wm8994_dai
[0].symmetric_rates
= 1;
4106 wm8994
->lrclk_shared
[0] = 0;
4109 ret
= regmap_read(control
->regmap
, WM8994_GPIO_6
, ®
);
4111 dev_err(codec
->dev
, "Failed to read GPIO6 state: %d\n", ret
);
4114 if ((reg
& WM8994_GPN_FN_MASK
) != WM8994_GP_FN_PIN_SPECIFIC
) {
4115 wm8994
->lrclk_shared
[1] = 1;
4116 wm8994_dai
[1].symmetric_rates
= 1;
4118 wm8994
->lrclk_shared
[1] = 0;
4121 pm_runtime_put(codec
->dev
);
4123 /* Latch volume update bits */
4124 for (i
= 0; i
< ARRAY_SIZE(wm8994_vu_bits
); i
++)
4125 snd_soc_update_bits(codec
, wm8994_vu_bits
[i
].reg
,
4126 wm8994_vu_bits
[i
].mask
,
4127 wm8994_vu_bits
[i
].mask
);
4129 /* Set the low bit of the 3D stereo depth so TLV matches */
4130 snd_soc_update_bits(codec
, WM8994_AIF1_DAC1_FILTERS_2
,
4131 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT
,
4132 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT
);
4133 snd_soc_update_bits(codec
, WM8994_AIF1_DAC2_FILTERS_2
,
4134 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT
,
4135 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT
);
4136 snd_soc_update_bits(codec
, WM8994_AIF2_DAC_FILTERS_2
,
4137 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT
,
4138 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT
);
4140 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
4141 * use this; it only affects behaviour on idle TDM clock
4143 switch (control
->type
) {
4146 snd_soc_update_bits(codec
, WM8994_AIF1_CONTROL_1
,
4147 WM8994_AIF1ADC_TDM
, WM8994_AIF1ADC_TDM
);
4153 /* Put MICBIAS into bypass mode by default on newer devices */
4154 switch (control
->type
) {
4157 snd_soc_update_bits(codec
, WM8958_MICBIAS1
,
4158 WM8958_MICB1_MODE
, WM8958_MICB1_MODE
);
4159 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
4160 WM8958_MICB2_MODE
, WM8958_MICB2_MODE
);
4166 wm8994
->hubs
.check_class_w_digital
= wm8994_check_class_w_digital
;
4167 wm_hubs_update_class_w(codec
);
4169 wm8994_handle_pdata(wm8994
);
4171 wm_hubs_add_analogue_controls(codec
);
4172 snd_soc_add_codec_controls(codec
, wm8994_snd_controls
,
4173 ARRAY_SIZE(wm8994_snd_controls
));
4174 snd_soc_dapm_new_controls(dapm
, wm8994_dapm_widgets
,
4175 ARRAY_SIZE(wm8994_dapm_widgets
));
4177 switch (control
->type
) {
4179 snd_soc_dapm_new_controls(dapm
, wm8994_specific_dapm_widgets
,
4180 ARRAY_SIZE(wm8994_specific_dapm_widgets
));
4181 if (control
->revision
< 4) {
4182 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_revd_widgets
,
4183 ARRAY_SIZE(wm8994_lateclk_revd_widgets
));
4184 snd_soc_dapm_new_controls(dapm
, wm8994_adc_revd_widgets
,
4185 ARRAY_SIZE(wm8994_adc_revd_widgets
));
4186 snd_soc_dapm_new_controls(dapm
, wm8994_dac_revd_widgets
,
4187 ARRAY_SIZE(wm8994_dac_revd_widgets
));
4189 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_widgets
,
4190 ARRAY_SIZE(wm8994_lateclk_widgets
));
4191 snd_soc_dapm_new_controls(dapm
, wm8994_adc_widgets
,
4192 ARRAY_SIZE(wm8994_adc_widgets
));
4193 snd_soc_dapm_new_controls(dapm
, wm8994_dac_widgets
,
4194 ARRAY_SIZE(wm8994_dac_widgets
));
4198 snd_soc_add_codec_controls(codec
, wm8958_snd_controls
,
4199 ARRAY_SIZE(wm8958_snd_controls
));
4200 snd_soc_dapm_new_controls(dapm
, wm8958_dapm_widgets
,
4201 ARRAY_SIZE(wm8958_dapm_widgets
));
4202 if (control
->revision
< 1) {
4203 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_revd_widgets
,
4204 ARRAY_SIZE(wm8994_lateclk_revd_widgets
));
4205 snd_soc_dapm_new_controls(dapm
, wm8994_adc_revd_widgets
,
4206 ARRAY_SIZE(wm8994_adc_revd_widgets
));
4207 snd_soc_dapm_new_controls(dapm
, wm8994_dac_revd_widgets
,
4208 ARRAY_SIZE(wm8994_dac_revd_widgets
));
4210 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_widgets
,
4211 ARRAY_SIZE(wm8994_lateclk_widgets
));
4212 snd_soc_dapm_new_controls(dapm
, wm8994_adc_widgets
,
4213 ARRAY_SIZE(wm8994_adc_widgets
));
4214 snd_soc_dapm_new_controls(dapm
, wm8994_dac_widgets
,
4215 ARRAY_SIZE(wm8994_dac_widgets
));
4220 snd_soc_add_codec_controls(codec
, wm8958_snd_controls
,
4221 ARRAY_SIZE(wm8958_snd_controls
));
4222 snd_soc_dapm_new_controls(dapm
, wm8958_dapm_widgets
,
4223 ARRAY_SIZE(wm8958_dapm_widgets
));
4224 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_widgets
,
4225 ARRAY_SIZE(wm8994_lateclk_widgets
));
4226 snd_soc_dapm_new_controls(dapm
, wm8994_adc_widgets
,
4227 ARRAY_SIZE(wm8994_adc_widgets
));
4228 snd_soc_dapm_new_controls(dapm
, wm8994_dac_widgets
,
4229 ARRAY_SIZE(wm8994_dac_widgets
));
4233 wm_hubs_add_analogue_routes(codec
, 0, 0);
4234 snd_soc_dapm_add_routes(dapm
, intercon
, ARRAY_SIZE(intercon
));
4236 switch (control
->type
) {
4238 snd_soc_dapm_add_routes(dapm
, wm8994_intercon
,
4239 ARRAY_SIZE(wm8994_intercon
));
4241 if (control
->revision
< 4) {
4242 snd_soc_dapm_add_routes(dapm
, wm8994_revd_intercon
,
4243 ARRAY_SIZE(wm8994_revd_intercon
));
4244 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_revd_intercon
,
4245 ARRAY_SIZE(wm8994_lateclk_revd_intercon
));
4247 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_intercon
,
4248 ARRAY_SIZE(wm8994_lateclk_intercon
));
4252 if (control
->revision
< 1) {
4253 snd_soc_dapm_add_routes(dapm
, wm8994_intercon
,
4254 ARRAY_SIZE(wm8994_intercon
));
4255 snd_soc_dapm_add_routes(dapm
, wm8994_revd_intercon
,
4256 ARRAY_SIZE(wm8994_revd_intercon
));
4257 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_revd_intercon
,
4258 ARRAY_SIZE(wm8994_lateclk_revd_intercon
));
4260 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_intercon
,
4261 ARRAY_SIZE(wm8994_lateclk_intercon
));
4262 snd_soc_dapm_add_routes(dapm
, wm8958_intercon
,
4263 ARRAY_SIZE(wm8958_intercon
));
4266 wm8958_dsp2_init(codec
);
4269 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_intercon
,
4270 ARRAY_SIZE(wm8994_lateclk_intercon
));
4271 snd_soc_dapm_add_routes(dapm
, wm8958_intercon
,
4272 ARRAY_SIZE(wm8958_intercon
));
4279 if (wm8994
->jackdet
)
4280 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_GPIO(6), wm8994
);
4281 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC2_SHRT
, wm8994
);
4282 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC2_DET
, wm8994
);
4283 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_SHRT
, wm8994
);
4284 if (wm8994
->micdet_irq
)
4285 free_irq(wm8994
->micdet_irq
, wm8994
);
4286 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++)
4287 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FLL1_LOCK
+ i
,
4288 &wm8994
->fll_locked
[i
]);
4289 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_DCS_DONE
,
4291 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FIFOS_ERR
, codec
);
4292 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_SHUT
, codec
);
4293 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_WARN
, codec
);
4298 static int wm8994_codec_remove(struct snd_soc_codec
*codec
)
4300 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
4301 struct wm8994
*control
= wm8994
->wm8994
;
4304 wm8994_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
4306 pm_runtime_disable(codec
->dev
);
4308 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++)
4309 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FLL1_LOCK
+ i
,
4310 &wm8994
->fll_locked
[i
]);
4312 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_DCS_DONE
,
4314 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FIFOS_ERR
, codec
);
4315 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_SHUT
, codec
);
4316 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_WARN
, codec
);
4318 if (wm8994
->jackdet
)
4319 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_GPIO(6), wm8994
);
4321 switch (control
->type
) {
4323 if (wm8994
->micdet_irq
)
4324 free_irq(wm8994
->micdet_irq
, wm8994
);
4325 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC2_DET
,
4327 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_SHRT
,
4329 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_DET
,
4335 if (wm8994
->micdet_irq
)
4336 free_irq(wm8994
->micdet_irq
, wm8994
);
4339 release_firmware(wm8994
->mbc
);
4340 release_firmware(wm8994
->mbc_vss
);
4341 release_firmware(wm8994
->enh_eq
);
4342 kfree(wm8994
->retune_mobile_texts
);
4346 static struct snd_soc_codec_driver soc_codec_dev_wm8994
= {
4347 .probe
= wm8994_codec_probe
,
4348 .remove
= wm8994_codec_remove
,
4349 .suspend
= wm8994_codec_suspend
,
4350 .resume
= wm8994_codec_resume
,
4351 .set_bias_level
= wm8994_set_bias_level
,
4354 static int wm8994_probe(struct platform_device
*pdev
)
4356 struct wm8994_priv
*wm8994
;
4358 wm8994
= devm_kzalloc(&pdev
->dev
, sizeof(struct wm8994_priv
),
4362 platform_set_drvdata(pdev
, wm8994
);
4364 wm8994
->wm8994
= dev_get_drvdata(pdev
->dev
.parent
);
4366 return snd_soc_register_codec(&pdev
->dev
, &soc_codec_dev_wm8994
,
4367 wm8994_dai
, ARRAY_SIZE(wm8994_dai
));
4370 static int wm8994_remove(struct platform_device
*pdev
)
4372 snd_soc_unregister_codec(&pdev
->dev
);
4376 #ifdef CONFIG_PM_SLEEP
4377 static int wm8994_suspend(struct device
*dev
)
4379 struct wm8994_priv
*wm8994
= dev_get_drvdata(dev
);
4381 /* Drop down to power saving mode when system is suspended */
4382 if (wm8994
->jackdet
&& !wm8994
->active_refcount
)
4383 regmap_update_bits(wm8994
->wm8994
->regmap
, WM8994_ANTIPOP_2
,
4384 WM1811_JACKDET_MODE_MASK
,
4385 wm8994
->jackdet_mode
);
4390 static int wm8994_resume(struct device
*dev
)
4392 struct wm8994_priv
*wm8994
= dev_get_drvdata(dev
);
4394 if (wm8994
->jackdet
&& wm8994
->jackdet_mode
)
4395 regmap_update_bits(wm8994
->wm8994
->regmap
, WM8994_ANTIPOP_2
,
4396 WM1811_JACKDET_MODE_MASK
,
4397 WM1811_JACKDET_MODE_AUDIO
);
4403 static const struct dev_pm_ops wm8994_pm_ops
= {
4404 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend
, wm8994_resume
)
4407 static struct platform_driver wm8994_codec_driver
= {
4409 .name
= "wm8994-codec",
4410 .owner
= THIS_MODULE
,
4411 .pm
= &wm8994_pm_ops
,
4413 .probe
= wm8994_probe
,
4414 .remove
= wm8994_remove
,
4417 module_platform_driver(wm8994_codec_driver
);
4419 MODULE_DESCRIPTION("ASoC WM8994 driver");
4420 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4421 MODULE_LICENSE("GPL");
4422 MODULE_ALIAS("platform:wm8994-codec");