2 * wm8994.c -- WM8994 ALSA SoC Audio driver
4 * Copyright 2009-12 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/jack.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <trace/events/asoc.h>
33 #include <linux/mfd/wm8994/core.h>
34 #include <linux/mfd/wm8994/registers.h>
35 #include <linux/mfd/wm8994/pdata.h>
36 #include <linux/mfd/wm8994/gpio.h>
41 #define WM1811_JACKDET_MODE_NONE 0x0000
42 #define WM1811_JACKDET_MODE_JACK 0x0100
43 #define WM1811_JACKDET_MODE_MIC 0x0080
44 #define WM1811_JACKDET_MODE_AUDIO 0x0180
46 #define WM8994_NUM_DRC 3
47 #define WM8994_NUM_EQ 3
52 } wm8994_vu_bits
[] = {
53 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME
, WM8994_IN1_VU
},
54 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME
, WM8994_IN1_VU
},
55 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME
, WM8994_IN2_VU
},
56 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME
, WM8994_IN2_VU
},
57 { WM8994_SPEAKER_VOLUME_LEFT
, WM8994_SPKOUT_VU
},
58 { WM8994_SPEAKER_VOLUME_RIGHT
, WM8994_SPKOUT_VU
},
59 { WM8994_LEFT_OUTPUT_VOLUME
, WM8994_HPOUT1_VU
},
60 { WM8994_RIGHT_OUTPUT_VOLUME
, WM8994_HPOUT1_VU
},
61 { WM8994_LEFT_OPGA_VOLUME
, WM8994_MIXOUT_VU
},
62 { WM8994_RIGHT_OPGA_VOLUME
, WM8994_MIXOUT_VU
},
64 { WM8994_AIF1_DAC1_LEFT_VOLUME
, WM8994_AIF1DAC1_VU
},
65 { WM8994_AIF1_DAC1_RIGHT_VOLUME
, WM8994_AIF1DAC1_VU
},
66 { WM8994_AIF1_DAC2_LEFT_VOLUME
, WM8994_AIF1DAC2_VU
},
67 { WM8994_AIF1_DAC2_RIGHT_VOLUME
, WM8994_AIF1DAC2_VU
},
68 { WM8994_AIF2_DAC_LEFT_VOLUME
, WM8994_AIF2DAC_VU
},
69 { WM8994_AIF2_DAC_RIGHT_VOLUME
, WM8994_AIF2DAC_VU
},
70 { WM8994_AIF1_ADC1_LEFT_VOLUME
, WM8994_AIF1ADC1_VU
},
71 { WM8994_AIF1_ADC1_RIGHT_VOLUME
, WM8994_AIF1ADC1_VU
},
72 { WM8994_AIF1_ADC2_LEFT_VOLUME
, WM8994_AIF1ADC2_VU
},
73 { WM8994_AIF1_ADC2_RIGHT_VOLUME
, WM8994_AIF1ADC2_VU
},
74 { WM8994_AIF2_ADC_LEFT_VOLUME
, WM8994_AIF2ADC_VU
},
75 { WM8994_AIF2_ADC_RIGHT_VOLUME
, WM8994_AIF1ADC2_VU
},
76 { WM8994_DAC1_LEFT_VOLUME
, WM8994_DAC1_VU
},
77 { WM8994_DAC1_RIGHT_VOLUME
, WM8994_DAC1_VU
},
78 { WM8994_DAC2_LEFT_VOLUME
, WM8994_DAC2_VU
},
79 { WM8994_DAC2_RIGHT_VOLUME
, WM8994_DAC2_VU
},
82 static int wm8994_drc_base
[] = {
88 static int wm8994_retune_mobile_base
[] = {
89 WM8994_AIF1_DAC1_EQ_GAINS_1
,
90 WM8994_AIF1_DAC2_EQ_GAINS_1
,
91 WM8994_AIF2_EQ_GAINS_1
,
94 static void wm8958_default_micdet(u16 status
, void *data
);
96 static const struct wm8958_micd_rate micdet_rates
[] = {
97 { 32768, true, 1, 4 },
98 { 32768, false, 1, 1 },
99 { 44100 * 256, true, 7, 10 },
100 { 44100 * 256, false, 7, 10 },
103 static const struct wm8958_micd_rate jackdet_rates
[] = {
104 { 32768, true, 0, 1 },
105 { 32768, false, 0, 1 },
106 { 44100 * 256, true, 10, 10 },
107 { 44100 * 256, false, 7, 8 },
110 static void wm8958_micd_set_rate(struct snd_soc_codec
*codec
)
112 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
113 int best
, i
, sysclk
, val
;
115 const struct wm8958_micd_rate
*rates
;
118 if (!(wm8994
->pdata
&& wm8994
->pdata
->micd_rates
) &&
119 wm8994
->jack_cb
!= wm8958_default_micdet
)
122 idle
= !wm8994
->jack_mic
;
124 sysclk
= snd_soc_read(codec
, WM8994_CLOCKING_1
);
125 if (sysclk
& WM8994_SYSCLK_SRC
)
126 sysclk
= wm8994
->aifclk
[1];
128 sysclk
= wm8994
->aifclk
[0];
130 if (wm8994
->pdata
&& wm8994
->pdata
->micd_rates
) {
131 rates
= wm8994
->pdata
->micd_rates
;
132 num_rates
= wm8994
->pdata
->num_micd_rates
;
133 } else if (wm8994
->jackdet
) {
134 rates
= jackdet_rates
;
135 num_rates
= ARRAY_SIZE(jackdet_rates
);
137 rates
= micdet_rates
;
138 num_rates
= ARRAY_SIZE(micdet_rates
);
142 for (i
= 0; i
< num_rates
; i
++) {
143 if (rates
[i
].idle
!= idle
)
145 if (abs(rates
[i
].sysclk
- sysclk
) <
146 abs(rates
[best
].sysclk
- sysclk
))
148 else if (rates
[best
].idle
!= idle
)
152 val
= rates
[best
].start
<< WM8958_MICD_BIAS_STARTTIME_SHIFT
153 | rates
[best
].rate
<< WM8958_MICD_RATE_SHIFT
;
155 dev_dbg(codec
->dev
, "MICD rate %d,%d for %dHz %s\n",
156 rates
[best
].start
, rates
[best
].rate
, sysclk
,
157 idle
? "idle" : "active");
159 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
160 WM8958_MICD_BIAS_STARTTIME_MASK
|
161 WM8958_MICD_RATE_MASK
, val
);
164 static int configure_aif_clock(struct snd_soc_codec
*codec
, int aif
)
166 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
176 switch (wm8994
->sysclk
[aif
]) {
177 case WM8994_SYSCLK_MCLK1
:
178 rate
= wm8994
->mclk
[0];
181 case WM8994_SYSCLK_MCLK2
:
183 rate
= wm8994
->mclk
[1];
186 case WM8994_SYSCLK_FLL1
:
188 rate
= wm8994
->fll
[0].out
;
191 case WM8994_SYSCLK_FLL2
:
193 rate
= wm8994
->fll
[1].out
;
200 if (rate
>= 13500000) {
202 reg1
|= WM8994_AIF1CLK_DIV
;
204 dev_dbg(codec
->dev
, "Dividing AIF%d clock to %dHz\n",
208 wm8994
->aifclk
[aif
] = rate
;
210 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
+ offset
,
211 WM8994_AIF1CLK_SRC_MASK
| WM8994_AIF1CLK_DIV
,
217 static int configure_clock(struct snd_soc_codec
*codec
)
219 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
222 /* Bring up the AIF clocks first */
223 configure_aif_clock(codec
, 0);
224 configure_aif_clock(codec
, 1);
226 /* Then switch CLK_SYS over to the higher of them; a change
227 * can only happen as a result of a clocking change which can
228 * only be made outside of DAPM so we can safely redo the
232 /* If they're equal it doesn't matter which is used */
233 if (wm8994
->aifclk
[0] == wm8994
->aifclk
[1]) {
234 wm8958_micd_set_rate(codec
);
238 if (wm8994
->aifclk
[0] < wm8994
->aifclk
[1])
239 new = WM8994_SYSCLK_SRC
;
243 change
= snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
244 WM8994_SYSCLK_SRC
, new);
246 snd_soc_dapm_sync(&codec
->dapm
);
248 wm8958_micd_set_rate(codec
);
253 static int check_clk_sys(struct snd_soc_dapm_widget
*source
,
254 struct snd_soc_dapm_widget
*sink
)
256 int reg
= snd_soc_read(source
->codec
, WM8994_CLOCKING_1
);
259 /* Check what we're currently using for CLK_SYS */
260 if (reg
& WM8994_SYSCLK_SRC
)
265 return strcmp(source
->name
, clk
) == 0;
268 static const char *sidetone_hpf_text
[] = {
269 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
272 static const struct soc_enum sidetone_hpf
=
273 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 7, 7, sidetone_hpf_text
);
275 static const char *adc_hpf_text
[] = {
276 "HiFi", "Voice 1", "Voice 2", "Voice 3"
279 static const struct soc_enum aif1adc1_hpf
=
280 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS
, 13, 4, adc_hpf_text
);
282 static const struct soc_enum aif1adc2_hpf
=
283 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS
, 13, 4, adc_hpf_text
);
285 static const struct soc_enum aif2adc_hpf
=
286 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS
, 13, 4, adc_hpf_text
);
288 static const DECLARE_TLV_DB_SCALE(aif_tlv
, 0, 600, 0);
289 static const DECLARE_TLV_DB_SCALE(digital_tlv
, -7200, 75, 1);
290 static const DECLARE_TLV_DB_SCALE(st_tlv
, -3600, 300, 0);
291 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv
, -1600, 183, 0);
292 static const DECLARE_TLV_DB_SCALE(eq_tlv
, -1200, 100, 0);
293 static const DECLARE_TLV_DB_SCALE(ng_tlv
, -10200, 600, 0);
294 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv
, 0, 900, 0);
296 #define WM8994_DRC_SWITCH(xname, reg, shift) \
297 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
298 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
299 .put = wm8994_put_drc_sw, \
300 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
302 static int wm8994_put_drc_sw(struct snd_kcontrol
*kcontrol
,
303 struct snd_ctl_elem_value
*ucontrol
)
305 struct soc_mixer_control
*mc
=
306 (struct soc_mixer_control
*)kcontrol
->private_value
;
307 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
310 /* Can't enable both ADC and DAC paths simultaneously */
311 if (mc
->shift
== WM8994_AIF1DAC1_DRC_ENA_SHIFT
)
312 mask
= WM8994_AIF1ADC1L_DRC_ENA_MASK
|
313 WM8994_AIF1ADC1R_DRC_ENA_MASK
;
315 mask
= WM8994_AIF1DAC1_DRC_ENA_MASK
;
317 ret
= snd_soc_read(codec
, mc
->reg
);
323 return snd_soc_put_volsw(kcontrol
, ucontrol
);
326 static void wm8994_set_drc(struct snd_soc_codec
*codec
, int drc
)
328 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
329 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
330 int base
= wm8994_drc_base
[drc
];
331 int cfg
= wm8994
->drc_cfg
[drc
];
334 /* Save any enables; the configuration should clear them. */
335 save
= snd_soc_read(codec
, base
);
336 save
&= WM8994_AIF1DAC1_DRC_ENA
| WM8994_AIF1ADC1L_DRC_ENA
|
337 WM8994_AIF1ADC1R_DRC_ENA
;
339 for (i
= 0; i
< WM8994_DRC_REGS
; i
++)
340 snd_soc_update_bits(codec
, base
+ i
, 0xffff,
341 pdata
->drc_cfgs
[cfg
].regs
[i
]);
343 snd_soc_update_bits(codec
, base
, WM8994_AIF1DAC1_DRC_ENA
|
344 WM8994_AIF1ADC1L_DRC_ENA
|
345 WM8994_AIF1ADC1R_DRC_ENA
, save
);
348 /* Icky as hell but saves code duplication */
349 static int wm8994_get_drc(const char *name
)
351 if (strcmp(name
, "AIF1DRC1 Mode") == 0)
353 if (strcmp(name
, "AIF1DRC2 Mode") == 0)
355 if (strcmp(name
, "AIF2DRC Mode") == 0)
360 static int wm8994_put_drc_enum(struct snd_kcontrol
*kcontrol
,
361 struct snd_ctl_elem_value
*ucontrol
)
363 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
364 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
365 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
366 int drc
= wm8994_get_drc(kcontrol
->id
.name
);
367 int value
= ucontrol
->value
.integer
.value
[0];
372 if (value
>= pdata
->num_drc_cfgs
)
375 wm8994
->drc_cfg
[drc
] = value
;
377 wm8994_set_drc(codec
, drc
);
382 static int wm8994_get_drc_enum(struct snd_kcontrol
*kcontrol
,
383 struct snd_ctl_elem_value
*ucontrol
)
385 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
386 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
387 int drc
= wm8994_get_drc(kcontrol
->id
.name
);
389 ucontrol
->value
.enumerated
.item
[0] = wm8994
->drc_cfg
[drc
];
394 static void wm8994_set_retune_mobile(struct snd_soc_codec
*codec
, int block
)
396 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
397 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
398 int base
= wm8994_retune_mobile_base
[block
];
399 int iface
, best
, best_val
, save
, i
, cfg
;
401 if (!pdata
|| !wm8994
->num_retune_mobile_texts
)
416 /* Find the version of the currently selected configuration
417 * with the nearest sample rate. */
418 cfg
= wm8994
->retune_mobile_cfg
[block
];
421 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
422 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
423 wm8994
->retune_mobile_texts
[cfg
]) == 0 &&
424 abs(pdata
->retune_mobile_cfgs
[i
].rate
425 - wm8994
->dac_rates
[iface
]) < best_val
) {
427 best_val
= abs(pdata
->retune_mobile_cfgs
[i
].rate
428 - wm8994
->dac_rates
[iface
]);
432 dev_dbg(codec
->dev
, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
434 pdata
->retune_mobile_cfgs
[best
].name
,
435 pdata
->retune_mobile_cfgs
[best
].rate
,
436 wm8994
->dac_rates
[iface
]);
438 /* The EQ will be disabled while reconfiguring it, remember the
439 * current configuration.
441 save
= snd_soc_read(codec
, base
);
442 save
&= WM8994_AIF1DAC1_EQ_ENA
;
444 for (i
= 0; i
< WM8994_EQ_REGS
; i
++)
445 snd_soc_update_bits(codec
, base
+ i
, 0xffff,
446 pdata
->retune_mobile_cfgs
[best
].regs
[i
]);
448 snd_soc_update_bits(codec
, base
, WM8994_AIF1DAC1_EQ_ENA
, save
);
451 /* Icky as hell but saves code duplication */
452 static int wm8994_get_retune_mobile_block(const char *name
)
454 if (strcmp(name
, "AIF1.1 EQ Mode") == 0)
456 if (strcmp(name
, "AIF1.2 EQ Mode") == 0)
458 if (strcmp(name
, "AIF2 EQ Mode") == 0)
463 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
464 struct snd_ctl_elem_value
*ucontrol
)
466 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
467 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
468 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
469 int block
= wm8994_get_retune_mobile_block(kcontrol
->id
.name
);
470 int value
= ucontrol
->value
.integer
.value
[0];
475 if (value
>= pdata
->num_retune_mobile_cfgs
)
478 wm8994
->retune_mobile_cfg
[block
] = value
;
480 wm8994_set_retune_mobile(codec
, block
);
485 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
486 struct snd_ctl_elem_value
*ucontrol
)
488 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
489 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
490 int block
= wm8994_get_retune_mobile_block(kcontrol
->id
.name
);
492 ucontrol
->value
.enumerated
.item
[0] = wm8994
->retune_mobile_cfg
[block
];
497 static const char *aif_chan_src_text
[] = {
501 static const struct soc_enum aif1adcl_src
=
502 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1
, 15, 2, aif_chan_src_text
);
504 static const struct soc_enum aif1adcr_src
=
505 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1
, 14, 2, aif_chan_src_text
);
507 static const struct soc_enum aif2adcl_src
=
508 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1
, 15, 2, aif_chan_src_text
);
510 static const struct soc_enum aif2adcr_src
=
511 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1
, 14, 2, aif_chan_src_text
);
513 static const struct soc_enum aif1dacl_src
=
514 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2
, 15, 2, aif_chan_src_text
);
516 static const struct soc_enum aif1dacr_src
=
517 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2
, 14, 2, aif_chan_src_text
);
519 static const struct soc_enum aif2dacl_src
=
520 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2
, 15, 2, aif_chan_src_text
);
522 static const struct soc_enum aif2dacr_src
=
523 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2
, 14, 2, aif_chan_src_text
);
525 static const char *osr_text
[] = {
526 "Low Power", "High Performance",
529 static const struct soc_enum dac_osr
=
530 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING
, 0, 2, osr_text
);
532 static const struct soc_enum adc_osr
=
533 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING
, 1, 2, osr_text
);
535 static const struct snd_kcontrol_new wm8994_snd_controls
[] = {
536 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME
,
537 WM8994_AIF1_ADC1_RIGHT_VOLUME
,
538 1, 119, 0, digital_tlv
),
539 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME
,
540 WM8994_AIF1_ADC2_RIGHT_VOLUME
,
541 1, 119, 0, digital_tlv
),
542 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME
,
543 WM8994_AIF2_ADC_RIGHT_VOLUME
,
544 1, 119, 0, digital_tlv
),
546 SOC_ENUM("AIF1ADCL Source", aif1adcl_src
),
547 SOC_ENUM("AIF1ADCR Source", aif1adcr_src
),
548 SOC_ENUM("AIF2ADCL Source", aif2adcl_src
),
549 SOC_ENUM("AIF2ADCR Source", aif2adcr_src
),
551 SOC_ENUM("AIF1DACL Source", aif1dacl_src
),
552 SOC_ENUM("AIF1DACR Source", aif1dacr_src
),
553 SOC_ENUM("AIF2DACL Source", aif2dacl_src
),
554 SOC_ENUM("AIF2DACR Source", aif2dacr_src
),
556 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME
,
557 WM8994_AIF1_DAC1_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
558 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME
,
559 WM8994_AIF1_DAC2_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
560 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME
,
561 WM8994_AIF2_DAC_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
563 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2
, 10, 3, 0, aif_tlv
),
564 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2
, 10, 3, 0, aif_tlv
),
566 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1
, 0, 1, 0),
567 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1
, 0, 1, 0),
568 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1
, 0, 1, 0),
570 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1
, 2),
571 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1
, 1),
572 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1
, 0),
574 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1
, 2),
575 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1
, 1),
576 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1
, 0),
578 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1
, 2),
579 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1
, 1),
580 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1
, 0),
582 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES
,
584 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES
,
586 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES
,
588 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES
,
590 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf
),
591 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE
, 6, 1, 0),
593 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf
),
594 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS
, 12, 11, 1, 0),
596 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf
),
597 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS
, 12, 11, 1, 0),
599 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf
),
600 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS
, 12, 11, 1, 0),
602 SOC_ENUM("ADC OSR", adc_osr
),
603 SOC_ENUM("DAC OSR", dac_osr
),
605 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME
,
606 WM8994_DAC1_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
607 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME
,
608 WM8994_DAC1_RIGHT_VOLUME
, 9, 1, 1),
610 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME
,
611 WM8994_DAC2_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
612 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME
,
613 WM8994_DAC2_RIGHT_VOLUME
, 9, 1, 1),
615 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION
,
616 6, 1, 1, wm_hubs_spkmix_tlv
),
617 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION
,
618 2, 1, 1, wm_hubs_spkmix_tlv
),
620 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION
,
621 6, 1, 1, wm_hubs_spkmix_tlv
),
622 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION
,
623 2, 1, 1, wm_hubs_spkmix_tlv
),
625 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2
,
626 10, 15, 0, wm8994_3d_tlv
),
627 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2
,
629 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2
,
630 10, 15, 0, wm8994_3d_tlv
),
631 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2
,
633 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2
,
634 10, 15, 0, wm8994_3d_tlv
),
635 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2
,
639 static const struct snd_kcontrol_new wm8994_eq_controls
[] = {
640 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 11, 31, 0,
642 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 6, 31, 0,
644 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 1, 31, 0,
646 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2
, 11, 31, 0,
648 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2
, 6, 31, 0,
651 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 11, 31, 0,
653 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 6, 31, 0,
655 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 1, 31, 0,
657 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2
, 11, 31, 0,
659 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2
, 6, 31, 0,
662 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1
, 11, 31, 0,
664 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1
, 6, 31, 0,
666 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1
, 1, 31, 0,
668 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2
, 11, 31, 0,
670 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2
, 6, 31, 0,
674 static const char *wm8958_ng_text
[] = {
675 "30ms", "125ms", "250ms", "500ms",
678 static const struct soc_enum wm8958_aif1dac1_ng_hold
=
679 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE
,
680 WM8958_AIF1DAC1_NG_THR_SHIFT
, 4, wm8958_ng_text
);
682 static const struct soc_enum wm8958_aif1dac2_ng_hold
=
683 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE
,
684 WM8958_AIF1DAC2_NG_THR_SHIFT
, 4, wm8958_ng_text
);
686 static const struct soc_enum wm8958_aif2dac_ng_hold
=
687 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE
,
688 WM8958_AIF2DAC_NG_THR_SHIFT
, 4, wm8958_ng_text
);
690 static const struct snd_kcontrol_new wm8958_snd_controls
[] = {
691 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2
, 10, 3, 0, aif_tlv
),
693 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE
,
694 WM8958_AIF1DAC1_NG_ENA_SHIFT
, 1, 0),
695 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold
),
696 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
697 WM8958_AIF1_DAC1_NOISE_GATE
, WM8958_AIF1DAC1_NG_THR_SHIFT
,
700 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE
,
701 WM8958_AIF1DAC2_NG_ENA_SHIFT
, 1, 0),
702 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold
),
703 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
704 WM8958_AIF1_DAC2_NOISE_GATE
, WM8958_AIF1DAC2_NG_THR_SHIFT
,
707 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE
,
708 WM8958_AIF2DAC_NG_ENA_SHIFT
, 1, 0),
709 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold
),
710 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
711 WM8958_AIF2_DAC_NOISE_GATE
, WM8958_AIF2DAC_NG_THR_SHIFT
,
715 static const struct snd_kcontrol_new wm1811_snd_controls
[] = {
716 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1
, 7, 1, 0,
718 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1
, 8, 1, 0,
722 /* We run all mode setting through a function to enforce audio mode */
723 static void wm1811_jackdet_set_mode(struct snd_soc_codec
*codec
, u16 mode
)
725 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
727 if (!wm8994
->jackdet
|| !wm8994
->jack_cb
)
730 if (wm8994
->active_refcount
)
731 mode
= WM1811_JACKDET_MODE_AUDIO
;
733 if (mode
== wm8994
->jackdet_mode
)
736 wm8994
->jackdet_mode
= mode
;
738 /* Always use audio mode to detect while the system is active */
739 if (mode
!= WM1811_JACKDET_MODE_NONE
)
740 mode
= WM1811_JACKDET_MODE_AUDIO
;
742 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
743 WM1811_JACKDET_MODE_MASK
, mode
);
746 static void active_reference(struct snd_soc_codec
*codec
)
748 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
750 mutex_lock(&wm8994
->accdet_lock
);
752 wm8994
->active_refcount
++;
754 dev_dbg(codec
->dev
, "Active refcount incremented, now %d\n",
755 wm8994
->active_refcount
);
757 /* If we're using jack detection go into audio mode */
758 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_AUDIO
);
760 mutex_unlock(&wm8994
->accdet_lock
);
763 static void active_dereference(struct snd_soc_codec
*codec
)
765 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
768 mutex_lock(&wm8994
->accdet_lock
);
770 wm8994
->active_refcount
--;
772 dev_dbg(codec
->dev
, "Active refcount decremented, now %d\n",
773 wm8994
->active_refcount
);
775 if (wm8994
->active_refcount
== 0) {
776 /* Go into appropriate detection only mode */
777 if (wm8994
->jack_mic
|| wm8994
->mic_detecting
)
778 mode
= WM1811_JACKDET_MODE_MIC
;
780 mode
= WM1811_JACKDET_MODE_JACK
;
782 wm1811_jackdet_set_mode(codec
, mode
);
785 mutex_unlock(&wm8994
->accdet_lock
);
788 static int clk_sys_event(struct snd_soc_dapm_widget
*w
,
789 struct snd_kcontrol
*kcontrol
, int event
)
791 struct snd_soc_codec
*codec
= w
->codec
;
794 case SND_SOC_DAPM_PRE_PMU
:
795 return configure_clock(codec
);
797 case SND_SOC_DAPM_POST_PMD
:
798 configure_clock(codec
);
805 static void vmid_reference(struct snd_soc_codec
*codec
)
807 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
809 pm_runtime_get_sync(codec
->dev
);
811 wm8994
->vmid_refcount
++;
813 dev_dbg(codec
->dev
, "Referencing VMID, refcount is now %d\n",
814 wm8994
->vmid_refcount
);
816 if (wm8994
->vmid_refcount
== 1) {
817 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
818 WM8994_LINEOUT1_DISCH
|
819 WM8994_LINEOUT2_DISCH
, 0);
821 wm_hubs_vmid_ena(codec
);
823 switch (wm8994
->vmid_mode
) {
825 WARN_ON(NULL
== "Invalid VMID mode");
826 case WM8994_VMID_NORMAL
:
827 /* Startup bias, VMID ramp & buffer */
828 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
831 WM8994_STARTUP_BIAS_ENA
|
832 WM8994_VMID_BUF_ENA
|
833 WM8994_VMID_RAMP_MASK
,
835 WM8994_STARTUP_BIAS_ENA
|
836 WM8994_VMID_BUF_ENA
|
837 (0x3 << WM8994_VMID_RAMP_SHIFT
));
839 /* Main bias enable, VMID=2x40k */
840 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
842 WM8994_VMID_SEL_MASK
,
843 WM8994_BIAS_ENA
| 0x2);
847 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
848 WM8994_VMID_RAMP_MASK
|
853 case WM8994_VMID_FORCE
:
854 /* Startup bias, slow VMID ramp & buffer */
855 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
858 WM8994_STARTUP_BIAS_ENA
|
859 WM8994_VMID_BUF_ENA
|
860 WM8994_VMID_RAMP_MASK
,
862 WM8994_STARTUP_BIAS_ENA
|
863 WM8994_VMID_BUF_ENA
|
864 (0x2 << WM8994_VMID_RAMP_SHIFT
));
866 /* Main bias enable, VMID=2x40k */
867 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
869 WM8994_VMID_SEL_MASK
,
870 WM8994_BIAS_ENA
| 0x2);
874 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
875 WM8994_VMID_RAMP_MASK
|
883 static void vmid_dereference(struct snd_soc_codec
*codec
)
885 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
887 wm8994
->vmid_refcount
--;
889 dev_dbg(codec
->dev
, "Dereferencing VMID, refcount is now %d\n",
890 wm8994
->vmid_refcount
);
892 if (wm8994
->vmid_refcount
== 0) {
893 if (wm8994
->hubs
.lineout1_se
)
894 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_3
,
895 WM8994_LINEOUT1N_ENA
|
896 WM8994_LINEOUT1P_ENA
,
897 WM8994_LINEOUT1N_ENA
|
898 WM8994_LINEOUT1P_ENA
);
900 if (wm8994
->hubs
.lineout2_se
)
901 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_3
,
902 WM8994_LINEOUT2N_ENA
|
903 WM8994_LINEOUT2P_ENA
,
904 WM8994_LINEOUT2N_ENA
|
905 WM8994_LINEOUT2P_ENA
);
907 /* Start discharging VMID */
908 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
914 switch (wm8994
->vmid_mode
) {
915 case WM8994_VMID_FORCE
:
922 snd_soc_update_bits(codec
, WM8994_ADDITIONAL_CONTROL
,
923 WM8994_VROI
, WM8994_VROI
);
925 /* Active discharge */
926 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
927 WM8994_LINEOUT1_DISCH
|
928 WM8994_LINEOUT2_DISCH
,
929 WM8994_LINEOUT1_DISCH
|
930 WM8994_LINEOUT2_DISCH
);
934 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_3
,
935 WM8994_LINEOUT1N_ENA
|
936 WM8994_LINEOUT1P_ENA
|
937 WM8994_LINEOUT2N_ENA
|
938 WM8994_LINEOUT2P_ENA
, 0);
940 snd_soc_update_bits(codec
, WM8994_ADDITIONAL_CONTROL
,
943 /* Switch off startup biases */
944 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
946 WM8994_STARTUP_BIAS_ENA
|
947 WM8994_VMID_BUF_ENA
|
948 WM8994_VMID_RAMP_MASK
, 0);
950 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
951 WM8994_BIAS_ENA
| WM8994_VMID_SEL_MASK
, 0);
953 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
954 WM8994_VMID_RAMP_MASK
, 0);
957 pm_runtime_put(codec
->dev
);
960 static int vmid_event(struct snd_soc_dapm_widget
*w
,
961 struct snd_kcontrol
*kcontrol
, int event
)
963 struct snd_soc_codec
*codec
= w
->codec
;
966 case SND_SOC_DAPM_PRE_PMU
:
967 vmid_reference(codec
);
970 case SND_SOC_DAPM_POST_PMD
:
971 vmid_dereference(codec
);
978 static bool wm8994_check_class_w_digital(struct snd_soc_codec
*codec
)
980 int source
= 0; /* GCC flow analysis can't track enable */
983 /* We also need the same AIF source for L/R and only one path */
984 reg
= snd_soc_read(codec
, WM8994_DAC1_LEFT_MIXER_ROUTING
);
986 case WM8994_AIF2DACL_TO_DAC1L
:
987 dev_vdbg(codec
->dev
, "Class W source AIF2DAC\n");
988 source
= 2 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
990 case WM8994_AIF1DAC2L_TO_DAC1L
:
991 dev_vdbg(codec
->dev
, "Class W source AIF1DAC2\n");
992 source
= 1 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
994 case WM8994_AIF1DAC1L_TO_DAC1L
:
995 dev_vdbg(codec
->dev
, "Class W source AIF1DAC1\n");
996 source
= 0 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
999 dev_vdbg(codec
->dev
, "DAC mixer setting: %x\n", reg
);
1003 reg_r
= snd_soc_read(codec
, WM8994_DAC1_RIGHT_MIXER_ROUTING
);
1005 dev_vdbg(codec
->dev
, "Left and right DAC mixers different\n");
1009 /* Set the source up */
1010 snd_soc_update_bits(codec
, WM8994_CLASS_W_1
,
1011 WM8994_CP_DYN_SRC_SEL_MASK
, source
);
1016 static int aif1clk_ev(struct snd_soc_dapm_widget
*w
,
1017 struct snd_kcontrol
*kcontrol
, int event
)
1019 struct snd_soc_codec
*codec
= w
->codec
;
1020 struct wm8994
*control
= codec
->control_data
;
1021 int mask
= WM8994_AIF1DAC1L_ENA
| WM8994_AIF1DAC1R_ENA
;
1027 switch (control
->type
) {
1030 mask
|= WM8994_AIF1DAC2L_ENA
| WM8994_AIF1DAC2R_ENA
;
1037 case SND_SOC_DAPM_PRE_PMU
:
1038 val
= snd_soc_read(codec
, WM8994_AIF1_CONTROL_1
);
1039 if ((val
& WM8994_AIF1ADCL_SRC
) &&
1040 (val
& WM8994_AIF1ADCR_SRC
))
1041 adc
= WM8994_AIF1ADC1R_ENA
| WM8994_AIF1ADC2R_ENA
;
1042 else if (!(val
& WM8994_AIF1ADCL_SRC
) &&
1043 !(val
& WM8994_AIF1ADCR_SRC
))
1044 adc
= WM8994_AIF1ADC1L_ENA
| WM8994_AIF1ADC2L_ENA
;
1046 adc
= WM8994_AIF1ADC1R_ENA
| WM8994_AIF1ADC2R_ENA
|
1047 WM8994_AIF1ADC1L_ENA
| WM8994_AIF1ADC2L_ENA
;
1049 val
= snd_soc_read(codec
, WM8994_AIF1_CONTROL_2
);
1050 if ((val
& WM8994_AIF1DACL_SRC
) &&
1051 (val
& WM8994_AIF1DACR_SRC
))
1052 dac
= WM8994_AIF1DAC1R_ENA
| WM8994_AIF1DAC2R_ENA
;
1053 else if (!(val
& WM8994_AIF1DACL_SRC
) &&
1054 !(val
& WM8994_AIF1DACR_SRC
))
1055 dac
= WM8994_AIF1DAC1L_ENA
| WM8994_AIF1DAC2L_ENA
;
1057 dac
= WM8994_AIF1DAC1R_ENA
| WM8994_AIF1DAC2R_ENA
|
1058 WM8994_AIF1DAC1L_ENA
| WM8994_AIF1DAC2L_ENA
;
1060 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
,
1062 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1064 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
1065 WM8994_AIF1DSPCLK_ENA
|
1066 WM8994_SYSDSPCLK_ENA
,
1067 WM8994_AIF1DSPCLK_ENA
|
1068 WM8994_SYSDSPCLK_ENA
);
1069 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
, mask
,
1070 WM8994_AIF1ADC1R_ENA
|
1071 WM8994_AIF1ADC1L_ENA
|
1072 WM8994_AIF1ADC2R_ENA
|
1073 WM8994_AIF1ADC2L_ENA
);
1074 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
, mask
,
1075 WM8994_AIF1DAC1R_ENA
|
1076 WM8994_AIF1DAC1L_ENA
|
1077 WM8994_AIF1DAC2R_ENA
|
1078 WM8994_AIF1DAC2L_ENA
);
1081 case SND_SOC_DAPM_POST_PMU
:
1082 for (i
= 0; i
< ARRAY_SIZE(wm8994_vu_bits
); i
++)
1083 snd_soc_write(codec
, wm8994_vu_bits
[i
].reg
,
1085 wm8994_vu_bits
[i
].reg
));
1088 case SND_SOC_DAPM_PRE_PMD
:
1089 case SND_SOC_DAPM_POST_PMD
:
1090 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1092 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
,
1095 val
= snd_soc_read(codec
, WM8994_CLOCKING_1
);
1096 if (val
& WM8994_AIF2DSPCLK_ENA
)
1097 val
= WM8994_SYSDSPCLK_ENA
;
1100 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
1101 WM8994_SYSDSPCLK_ENA
|
1102 WM8994_AIF1DSPCLK_ENA
, val
);
1109 static int aif2clk_ev(struct snd_soc_dapm_widget
*w
,
1110 struct snd_kcontrol
*kcontrol
, int event
)
1112 struct snd_soc_codec
*codec
= w
->codec
;
1119 case SND_SOC_DAPM_PRE_PMU
:
1120 val
= snd_soc_read(codec
, WM8994_AIF2_CONTROL_1
);
1121 if ((val
& WM8994_AIF2ADCL_SRC
) &&
1122 (val
& WM8994_AIF2ADCR_SRC
))
1123 adc
= WM8994_AIF2ADCR_ENA
;
1124 else if (!(val
& WM8994_AIF2ADCL_SRC
) &&
1125 !(val
& WM8994_AIF2ADCR_SRC
))
1126 adc
= WM8994_AIF2ADCL_ENA
;
1128 adc
= WM8994_AIF2ADCL_ENA
| WM8994_AIF2ADCR_ENA
;
1131 val
= snd_soc_read(codec
, WM8994_AIF2_CONTROL_2
);
1132 if ((val
& WM8994_AIF2DACL_SRC
) &&
1133 (val
& WM8994_AIF2DACR_SRC
))
1134 dac
= WM8994_AIF2DACR_ENA
;
1135 else if (!(val
& WM8994_AIF2DACL_SRC
) &&
1136 !(val
& WM8994_AIF2DACR_SRC
))
1137 dac
= WM8994_AIF2DACL_ENA
;
1139 dac
= WM8994_AIF2DACL_ENA
| WM8994_AIF2DACR_ENA
;
1141 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
,
1142 WM8994_AIF2ADCL_ENA
|
1143 WM8994_AIF2ADCR_ENA
, adc
);
1144 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1145 WM8994_AIF2DACL_ENA
|
1146 WM8994_AIF2DACR_ENA
, dac
);
1147 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
1148 WM8994_AIF2DSPCLK_ENA
|
1149 WM8994_SYSDSPCLK_ENA
,
1150 WM8994_AIF2DSPCLK_ENA
|
1151 WM8994_SYSDSPCLK_ENA
);
1152 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
,
1153 WM8994_AIF2ADCL_ENA
|
1154 WM8994_AIF2ADCR_ENA
,
1155 WM8994_AIF2ADCL_ENA
|
1156 WM8994_AIF2ADCR_ENA
);
1157 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1158 WM8994_AIF2DACL_ENA
|
1159 WM8994_AIF2DACR_ENA
,
1160 WM8994_AIF2DACL_ENA
|
1161 WM8994_AIF2DACR_ENA
);
1164 case SND_SOC_DAPM_POST_PMU
:
1165 for (i
= 0; i
< ARRAY_SIZE(wm8994_vu_bits
); i
++)
1166 snd_soc_write(codec
, wm8994_vu_bits
[i
].reg
,
1168 wm8994_vu_bits
[i
].reg
));
1171 case SND_SOC_DAPM_PRE_PMD
:
1172 case SND_SOC_DAPM_POST_PMD
:
1173 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1174 WM8994_AIF2DACL_ENA
|
1175 WM8994_AIF2DACR_ENA
, 0);
1176 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
,
1177 WM8994_AIF2ADCL_ENA
|
1178 WM8994_AIF2ADCR_ENA
, 0);
1180 val
= snd_soc_read(codec
, WM8994_CLOCKING_1
);
1181 if (val
& WM8994_AIF1DSPCLK_ENA
)
1182 val
= WM8994_SYSDSPCLK_ENA
;
1185 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
1186 WM8994_SYSDSPCLK_ENA
|
1187 WM8994_AIF2DSPCLK_ENA
, val
);
1194 static int aif1clk_late_ev(struct snd_soc_dapm_widget
*w
,
1195 struct snd_kcontrol
*kcontrol
, int event
)
1197 struct snd_soc_codec
*codec
= w
->codec
;
1198 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1201 case SND_SOC_DAPM_PRE_PMU
:
1202 wm8994
->aif1clk_enable
= 1;
1204 case SND_SOC_DAPM_POST_PMD
:
1205 wm8994
->aif1clk_disable
= 1;
1212 static int aif2clk_late_ev(struct snd_soc_dapm_widget
*w
,
1213 struct snd_kcontrol
*kcontrol
, int event
)
1215 struct snd_soc_codec
*codec
= w
->codec
;
1216 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1219 case SND_SOC_DAPM_PRE_PMU
:
1220 wm8994
->aif2clk_enable
= 1;
1222 case SND_SOC_DAPM_POST_PMD
:
1223 wm8994
->aif2clk_disable
= 1;
1230 static int late_enable_ev(struct snd_soc_dapm_widget
*w
,
1231 struct snd_kcontrol
*kcontrol
, int event
)
1233 struct snd_soc_codec
*codec
= w
->codec
;
1234 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1237 case SND_SOC_DAPM_PRE_PMU
:
1238 if (wm8994
->aif1clk_enable
) {
1239 aif1clk_ev(w
, kcontrol
, SND_SOC_DAPM_PRE_PMU
);
1240 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
1241 WM8994_AIF1CLK_ENA_MASK
,
1242 WM8994_AIF1CLK_ENA
);
1243 aif1clk_ev(w
, kcontrol
, SND_SOC_DAPM_POST_PMU
);
1244 wm8994
->aif1clk_enable
= 0;
1246 if (wm8994
->aif2clk_enable
) {
1247 aif2clk_ev(w
, kcontrol
, SND_SOC_DAPM_PRE_PMU
);
1248 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
1249 WM8994_AIF2CLK_ENA_MASK
,
1250 WM8994_AIF2CLK_ENA
);
1251 aif2clk_ev(w
, kcontrol
, SND_SOC_DAPM_POST_PMU
);
1252 wm8994
->aif2clk_enable
= 0;
1257 /* We may also have postponed startup of DSP, handle that. */
1258 wm8958_aif_ev(w
, kcontrol
, event
);
1263 static int late_disable_ev(struct snd_soc_dapm_widget
*w
,
1264 struct snd_kcontrol
*kcontrol
, int event
)
1266 struct snd_soc_codec
*codec
= w
->codec
;
1267 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1270 case SND_SOC_DAPM_POST_PMD
:
1271 if (wm8994
->aif1clk_disable
) {
1272 aif1clk_ev(w
, kcontrol
, SND_SOC_DAPM_PRE_PMD
);
1273 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
1274 WM8994_AIF1CLK_ENA_MASK
, 0);
1275 aif1clk_ev(w
, kcontrol
, SND_SOC_DAPM_POST_PMD
);
1276 wm8994
->aif1clk_disable
= 0;
1278 if (wm8994
->aif2clk_disable
) {
1279 aif2clk_ev(w
, kcontrol
, SND_SOC_DAPM_PRE_PMD
);
1280 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
1281 WM8994_AIF2CLK_ENA_MASK
, 0);
1282 aif2clk_ev(w
, kcontrol
, SND_SOC_DAPM_POST_PMD
);
1283 wm8994
->aif2clk_disable
= 0;
1291 static int adc_mux_ev(struct snd_soc_dapm_widget
*w
,
1292 struct snd_kcontrol
*kcontrol
, int event
)
1294 late_enable_ev(w
, kcontrol
, event
);
1298 static int micbias_ev(struct snd_soc_dapm_widget
*w
,
1299 struct snd_kcontrol
*kcontrol
, int event
)
1301 late_enable_ev(w
, kcontrol
, event
);
1305 static int dac_ev(struct snd_soc_dapm_widget
*w
,
1306 struct snd_kcontrol
*kcontrol
, int event
)
1308 struct snd_soc_codec
*codec
= w
->codec
;
1309 unsigned int mask
= 1 << w
->shift
;
1311 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1316 static const char *adc_mux_text
[] = {
1321 static const struct soc_enum adc_enum
=
1322 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text
);
1324 static const struct snd_kcontrol_new adcl_mux
=
1325 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum
);
1327 static const struct snd_kcontrol_new adcr_mux
=
1328 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum
);
1330 static const struct snd_kcontrol_new left_speaker_mixer
[] = {
1331 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER
, 9, 1, 0),
1332 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER
, 7, 1, 0),
1333 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER
, 5, 1, 0),
1334 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER
, 3, 1, 0),
1335 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER
, 1, 1, 0),
1338 static const struct snd_kcontrol_new right_speaker_mixer
[] = {
1339 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER
, 8, 1, 0),
1340 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER
, 6, 1, 0),
1341 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER
, 4, 1, 0),
1342 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER
, 2, 1, 0),
1343 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER
, 0, 1, 0),
1346 /* Debugging; dump chip status after DAPM transitions */
1347 static int post_ev(struct snd_soc_dapm_widget
*w
,
1348 struct snd_kcontrol
*kcontrol
, int event
)
1350 struct snd_soc_codec
*codec
= w
->codec
;
1351 dev_dbg(codec
->dev
, "SRC status: %x\n",
1353 WM8994_RATE_STATUS
));
1357 static const struct snd_kcontrol_new aif1adc1l_mix
[] = {
1358 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING
,
1360 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING
,
1364 static const struct snd_kcontrol_new aif1adc1r_mix
[] = {
1365 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING
,
1367 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING
,
1371 static const struct snd_kcontrol_new aif1adc2l_mix
[] = {
1372 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING
,
1374 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING
,
1378 static const struct snd_kcontrol_new aif1adc2r_mix
[] = {
1379 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING
,
1381 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING
,
1385 static const struct snd_kcontrol_new aif2dac2l_mix
[] = {
1386 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1388 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1390 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1392 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1394 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1398 static const struct snd_kcontrol_new aif2dac2r_mix
[] = {
1399 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1401 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1403 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1405 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1407 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1411 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1412 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1413 .info = snd_soc_info_volsw, \
1414 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1415 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1417 static int wm8994_put_class_w(struct snd_kcontrol
*kcontrol
,
1418 struct snd_ctl_elem_value
*ucontrol
)
1420 struct snd_soc_dapm_widget_list
*wlist
= snd_kcontrol_chip(kcontrol
);
1421 struct snd_soc_dapm_widget
*w
= wlist
->widgets
[0];
1422 struct snd_soc_codec
*codec
= w
->codec
;
1425 ret
= snd_soc_dapm_put_volsw(kcontrol
, ucontrol
);
1427 wm_hubs_update_class_w(codec
);
1432 static const struct snd_kcontrol_new dac1l_mix
[] = {
1433 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1435 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1437 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1439 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1441 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1445 static const struct snd_kcontrol_new dac1r_mix
[] = {
1446 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1448 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1450 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1452 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1454 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1458 static const char *sidetone_text
[] = {
1459 "ADC/DMIC1", "DMIC2",
1462 static const struct soc_enum sidetone1_enum
=
1463 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 0, 2, sidetone_text
);
1465 static const struct snd_kcontrol_new sidetone1_mux
=
1466 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum
);
1468 static const struct soc_enum sidetone2_enum
=
1469 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 1, 2, sidetone_text
);
1471 static const struct snd_kcontrol_new sidetone2_mux
=
1472 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum
);
1474 static const char *aif1dac_text
[] = {
1475 "AIF1DACDAT", "AIF3DACDAT",
1478 static const struct soc_enum aif1dac_enum
=
1479 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 0, 2, aif1dac_text
);
1481 static const struct snd_kcontrol_new aif1dac_mux
=
1482 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum
);
1484 static const char *aif2dac_text
[] = {
1485 "AIF2DACDAT", "AIF3DACDAT",
1488 static const struct soc_enum aif2dac_enum
=
1489 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 1, 2, aif2dac_text
);
1491 static const struct snd_kcontrol_new aif2dac_mux
=
1492 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum
);
1494 static const char *aif2adc_text
[] = {
1495 "AIF2ADCDAT", "AIF3DACDAT",
1498 static const struct soc_enum aif2adc_enum
=
1499 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 2, 2, aif2adc_text
);
1501 static const struct snd_kcontrol_new aif2adc_mux
=
1502 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum
);
1504 static const char *aif3adc_text
[] = {
1505 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1508 static const struct soc_enum wm8994_aif3adc_enum
=
1509 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 3, 3, aif3adc_text
);
1511 static const struct snd_kcontrol_new wm8994_aif3adc_mux
=
1512 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum
);
1514 static const struct soc_enum wm8958_aif3adc_enum
=
1515 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 3, 4, aif3adc_text
);
1517 static const struct snd_kcontrol_new wm8958_aif3adc_mux
=
1518 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum
);
1520 static const char *mono_pcm_out_text
[] = {
1521 "None", "AIF2ADCL", "AIF2ADCR",
1524 static const struct soc_enum mono_pcm_out_enum
=
1525 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 9, 3, mono_pcm_out_text
);
1527 static const struct snd_kcontrol_new mono_pcm_out_mux
=
1528 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum
);
1530 static const char *aif2dac_src_text
[] = {
1534 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1535 static const struct soc_enum aif2dacl_src_enum
=
1536 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 7, 2, aif2dac_src_text
);
1538 static const struct snd_kcontrol_new aif2dacl_src_mux
=
1539 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum
);
1541 static const struct soc_enum aif2dacr_src_enum
=
1542 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 8, 2, aif2dac_src_text
);
1544 static const struct snd_kcontrol_new aif2dacr_src_mux
=
1545 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum
);
1547 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets
[] = {
1548 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM
, 0, 0, aif1clk_late_ev
,
1549 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1550 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM
, 0, 0, aif2clk_late_ev
,
1551 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1553 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1554 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1555 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1556 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1557 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1558 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1559 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1560 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1561 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1562 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1564 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3
, 8, 0,
1565 left_speaker_mixer
, ARRAY_SIZE(left_speaker_mixer
),
1566 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1567 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3
, 9, 0,
1568 right_speaker_mixer
, ARRAY_SIZE(right_speaker_mixer
),
1569 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1570 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM
, 0, 0, &wm_hubs_hpl_mux
,
1571 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1572 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM
, 0, 0, &wm_hubs_hpr_mux
,
1573 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1575 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev
)
1578 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets
[] = {
1579 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1
, 0, 0, aif1clk_ev
,
1580 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMU
|
1581 SND_SOC_DAPM_PRE_PMD
),
1582 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1
, 0, 0, aif2clk_ev
,
1583 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMU
|
1584 SND_SOC_DAPM_PRE_PMD
),
1585 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM
, 0, 0, NULL
, 0),
1586 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3
, 8, 0,
1587 left_speaker_mixer
, ARRAY_SIZE(left_speaker_mixer
)),
1588 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3
, 9, 0,
1589 right_speaker_mixer
, ARRAY_SIZE(right_speaker_mixer
)),
1590 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM
, 0, 0, &wm_hubs_hpl_mux
),
1591 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM
, 0, 0, &wm_hubs_hpr_mux
),
1594 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets
[] = {
1595 SND_SOC_DAPM_DAC_E("DAC2L", NULL
, SND_SOC_NOPM
, 3, 0,
1596 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1597 SND_SOC_DAPM_DAC_E("DAC2R", NULL
, SND_SOC_NOPM
, 2, 0,
1598 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1599 SND_SOC_DAPM_DAC_E("DAC1L", NULL
, SND_SOC_NOPM
, 1, 0,
1600 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1601 SND_SOC_DAPM_DAC_E("DAC1R", NULL
, SND_SOC_NOPM
, 0, 0,
1602 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1605 static const struct snd_soc_dapm_widget wm8994_dac_widgets
[] = {
1606 SND_SOC_DAPM_DAC("DAC2L", NULL
, WM8994_POWER_MANAGEMENT_5
, 3, 0),
1607 SND_SOC_DAPM_DAC("DAC2R", NULL
, WM8994_POWER_MANAGEMENT_5
, 2, 0),
1608 SND_SOC_DAPM_DAC("DAC1L", NULL
, WM8994_POWER_MANAGEMENT_5
, 1, 0),
1609 SND_SOC_DAPM_DAC("DAC1R", NULL
, WM8994_POWER_MANAGEMENT_5
, 0, 0),
1612 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets
[] = {
1613 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4
, 1, 0, &adcl_mux
,
1614 adc_mux_ev
, SND_SOC_DAPM_PRE_PMU
),
1615 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4
, 0, 0, &adcr_mux
,
1616 adc_mux_ev
, SND_SOC_DAPM_PRE_PMU
),
1619 static const struct snd_soc_dapm_widget wm8994_adc_widgets
[] = {
1620 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4
, 1, 0, &adcl_mux
),
1621 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4
, 0, 0, &adcr_mux
),
1624 static const struct snd_soc_dapm_widget wm8994_dapm_widgets
[] = {
1625 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1626 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1627 SND_SOC_DAPM_INPUT("Clock"),
1629 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM
, 0, 0, micbias_ev
,
1630 SND_SOC_DAPM_PRE_PMU
),
1631 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM
, 0, 0, vmid_event
,
1632 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1634 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM
, 0, 0, clk_sys_event
,
1635 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1637 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM
, 3, 0, NULL
, 0),
1638 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM
, 2, 0, NULL
, 0),
1639 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM
, 1, 0, NULL
, 0),
1641 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL
,
1642 0, SND_SOC_NOPM
, 9, 0),
1643 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL
,
1644 0, SND_SOC_NOPM
, 8, 0),
1645 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL
, 0,
1646 SND_SOC_NOPM
, 9, 0, wm8958_aif_ev
,
1647 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1648 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL
, 0,
1649 SND_SOC_NOPM
, 8, 0, wm8958_aif_ev
,
1650 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1652 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL
,
1653 0, SND_SOC_NOPM
, 11, 0),
1654 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL
,
1655 0, SND_SOC_NOPM
, 10, 0),
1656 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL
, 0,
1657 SND_SOC_NOPM
, 11, 0, wm8958_aif_ev
,
1658 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1659 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL
, 0,
1660 SND_SOC_NOPM
, 10, 0, wm8958_aif_ev
,
1661 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1663 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM
, 0, 0,
1664 aif1adc1l_mix
, ARRAY_SIZE(aif1adc1l_mix
)),
1665 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM
, 0, 0,
1666 aif1adc1r_mix
, ARRAY_SIZE(aif1adc1r_mix
)),
1668 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM
, 0, 0,
1669 aif1adc2l_mix
, ARRAY_SIZE(aif1adc2l_mix
)),
1670 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM
, 0, 0,
1671 aif1adc2r_mix
, ARRAY_SIZE(aif1adc2r_mix
)),
1673 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM
, 0, 0,
1674 aif2dac2l_mix
, ARRAY_SIZE(aif2dac2l_mix
)),
1675 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM
, 0, 0,
1676 aif2dac2r_mix
, ARRAY_SIZE(aif2dac2r_mix
)),
1678 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM
, 0, 0, &sidetone1_mux
),
1679 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM
, 0, 0, &sidetone2_mux
),
1681 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM
, 0, 0,
1682 dac1l_mix
, ARRAY_SIZE(dac1l_mix
)),
1683 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM
, 0, 0,
1684 dac1r_mix
, ARRAY_SIZE(dac1r_mix
)),
1686 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL
, 0,
1687 SND_SOC_NOPM
, 13, 0),
1688 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL
, 0,
1689 SND_SOC_NOPM
, 12, 0),
1690 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL
, 0,
1691 SND_SOC_NOPM
, 13, 0, wm8958_aif_ev
,
1692 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1693 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL
, 0,
1694 SND_SOC_NOPM
, 12, 0, wm8958_aif_ev
,
1695 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1697 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1698 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1699 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1700 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1702 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM
, 0, 0, &aif1dac_mux
),
1703 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM
, 0, 0, &aif2dac_mux
),
1704 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM
, 0, 0, &aif2adc_mux
),
1706 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1707 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1709 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1
, 4, 0, NULL
, 0),
1711 SND_SOC_DAPM_ADC("DMIC2L", NULL
, WM8994_POWER_MANAGEMENT_4
, 5, 0),
1712 SND_SOC_DAPM_ADC("DMIC2R", NULL
, WM8994_POWER_MANAGEMENT_4
, 4, 0),
1713 SND_SOC_DAPM_ADC("DMIC1L", NULL
, WM8994_POWER_MANAGEMENT_4
, 3, 0),
1714 SND_SOC_DAPM_ADC("DMIC1R", NULL
, WM8994_POWER_MANAGEMENT_4
, 2, 0),
1716 /* Power is done with the muxes since the ADC power also controls the
1717 * downsampling chain, the chip will automatically manage the analogue
1718 * specific portions.
1720 SND_SOC_DAPM_ADC("ADCL", NULL
, SND_SOC_NOPM
, 1, 0),
1721 SND_SOC_DAPM_ADC("ADCR", NULL
, SND_SOC_NOPM
, 0, 0),
1723 SND_SOC_DAPM_POST("Debug log", post_ev
),
1726 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets
[] = {
1727 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM
, 0, 0, &wm8994_aif3adc_mux
),
1730 static const struct snd_soc_dapm_widget wm8958_dapm_widgets
[] = {
1731 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6
, 5, 1, NULL
, 0),
1732 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM
, 0, 0, &mono_pcm_out_mux
),
1733 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM
, 0, 0, &aif2dacl_src_mux
),
1734 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM
, 0, 0, &aif2dacr_src_mux
),
1735 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM
, 0, 0, &wm8958_aif3adc_mux
),
1738 static const struct snd_soc_dapm_route intercon
[] = {
1739 { "CLK_SYS", NULL
, "AIF1CLK", check_clk_sys
},
1740 { "CLK_SYS", NULL
, "AIF2CLK", check_clk_sys
},
1742 { "DSP1CLK", NULL
, "CLK_SYS" },
1743 { "DSP2CLK", NULL
, "CLK_SYS" },
1744 { "DSPINTCLK", NULL
, "CLK_SYS" },
1746 { "AIF1ADC1L", NULL
, "AIF1CLK" },
1747 { "AIF1ADC1L", NULL
, "DSP1CLK" },
1748 { "AIF1ADC1R", NULL
, "AIF1CLK" },
1749 { "AIF1ADC1R", NULL
, "DSP1CLK" },
1750 { "AIF1ADC1R", NULL
, "DSPINTCLK" },
1752 { "AIF1DAC1L", NULL
, "AIF1CLK" },
1753 { "AIF1DAC1L", NULL
, "DSP1CLK" },
1754 { "AIF1DAC1R", NULL
, "AIF1CLK" },
1755 { "AIF1DAC1R", NULL
, "DSP1CLK" },
1756 { "AIF1DAC1R", NULL
, "DSPINTCLK" },
1758 { "AIF1ADC2L", NULL
, "AIF1CLK" },
1759 { "AIF1ADC2L", NULL
, "DSP1CLK" },
1760 { "AIF1ADC2R", NULL
, "AIF1CLK" },
1761 { "AIF1ADC2R", NULL
, "DSP1CLK" },
1762 { "AIF1ADC2R", NULL
, "DSPINTCLK" },
1764 { "AIF1DAC2L", NULL
, "AIF1CLK" },
1765 { "AIF1DAC2L", NULL
, "DSP1CLK" },
1766 { "AIF1DAC2R", NULL
, "AIF1CLK" },
1767 { "AIF1DAC2R", NULL
, "DSP1CLK" },
1768 { "AIF1DAC2R", NULL
, "DSPINTCLK" },
1770 { "AIF2ADCL", NULL
, "AIF2CLK" },
1771 { "AIF2ADCL", NULL
, "DSP2CLK" },
1772 { "AIF2ADCR", NULL
, "AIF2CLK" },
1773 { "AIF2ADCR", NULL
, "DSP2CLK" },
1774 { "AIF2ADCR", NULL
, "DSPINTCLK" },
1776 { "AIF2DACL", NULL
, "AIF2CLK" },
1777 { "AIF2DACL", NULL
, "DSP2CLK" },
1778 { "AIF2DACR", NULL
, "AIF2CLK" },
1779 { "AIF2DACR", NULL
, "DSP2CLK" },
1780 { "AIF2DACR", NULL
, "DSPINTCLK" },
1782 { "DMIC1L", NULL
, "DMIC1DAT" },
1783 { "DMIC1L", NULL
, "CLK_SYS" },
1784 { "DMIC1R", NULL
, "DMIC1DAT" },
1785 { "DMIC1R", NULL
, "CLK_SYS" },
1786 { "DMIC2L", NULL
, "DMIC2DAT" },
1787 { "DMIC2L", NULL
, "CLK_SYS" },
1788 { "DMIC2R", NULL
, "DMIC2DAT" },
1789 { "DMIC2R", NULL
, "CLK_SYS" },
1791 { "ADCL", NULL
, "AIF1CLK" },
1792 { "ADCL", NULL
, "DSP1CLK" },
1793 { "ADCL", NULL
, "DSPINTCLK" },
1795 { "ADCR", NULL
, "AIF1CLK" },
1796 { "ADCR", NULL
, "DSP1CLK" },
1797 { "ADCR", NULL
, "DSPINTCLK" },
1799 { "ADCL Mux", "ADC", "ADCL" },
1800 { "ADCL Mux", "DMIC", "DMIC1L" },
1801 { "ADCR Mux", "ADC", "ADCR" },
1802 { "ADCR Mux", "DMIC", "DMIC1R" },
1804 { "DAC1L", NULL
, "AIF1CLK" },
1805 { "DAC1L", NULL
, "DSP1CLK" },
1806 { "DAC1L", NULL
, "DSPINTCLK" },
1808 { "DAC1R", NULL
, "AIF1CLK" },
1809 { "DAC1R", NULL
, "DSP1CLK" },
1810 { "DAC1R", NULL
, "DSPINTCLK" },
1812 { "DAC2L", NULL
, "AIF2CLK" },
1813 { "DAC2L", NULL
, "DSP2CLK" },
1814 { "DAC2L", NULL
, "DSPINTCLK" },
1816 { "DAC2R", NULL
, "AIF2DACR" },
1817 { "DAC2R", NULL
, "AIF2CLK" },
1818 { "DAC2R", NULL
, "DSP2CLK" },
1819 { "DAC2R", NULL
, "DSPINTCLK" },
1821 { "TOCLK", NULL
, "CLK_SYS" },
1823 { "AIF1DACDAT", NULL
, "AIF1 Playback" },
1824 { "AIF2DACDAT", NULL
, "AIF2 Playback" },
1825 { "AIF3DACDAT", NULL
, "AIF3 Playback" },
1827 { "AIF1 Capture", NULL
, "AIF1ADCDAT" },
1828 { "AIF2 Capture", NULL
, "AIF2ADCDAT" },
1829 { "AIF3 Capture", NULL
, "AIF3ADCDAT" },
1832 { "AIF1ADC1L", NULL
, "AIF1ADC1L Mixer" },
1833 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1834 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1836 { "AIF1ADC1R", NULL
, "AIF1ADC1R Mixer" },
1837 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1838 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1840 { "AIF1ADC2L", NULL
, "AIF1ADC2L Mixer" },
1841 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1842 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1844 { "AIF1ADC2R", NULL
, "AIF1ADC2R Mixer" },
1845 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1846 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1848 /* Pin level routing for AIF3 */
1849 { "AIF1DAC1L", NULL
, "AIF1DAC Mux" },
1850 { "AIF1DAC1R", NULL
, "AIF1DAC Mux" },
1851 { "AIF1DAC2L", NULL
, "AIF1DAC Mux" },
1852 { "AIF1DAC2R", NULL
, "AIF1DAC Mux" },
1854 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1855 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1856 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1857 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1858 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1859 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1860 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1863 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1864 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1865 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1866 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1867 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1869 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1870 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1871 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1872 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1873 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1875 /* DAC2/AIF2 outputs */
1876 { "AIF2ADCL", NULL
, "AIF2DAC2L Mixer" },
1877 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1878 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1879 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1880 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1881 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1883 { "AIF2ADCR", NULL
, "AIF2DAC2R Mixer" },
1884 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1885 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1886 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1887 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1888 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1890 { "AIF1ADCDAT", NULL
, "AIF1ADC1L" },
1891 { "AIF1ADCDAT", NULL
, "AIF1ADC1R" },
1892 { "AIF1ADCDAT", NULL
, "AIF1ADC2L" },
1893 { "AIF1ADCDAT", NULL
, "AIF1ADC2R" },
1895 { "AIF2ADCDAT", NULL
, "AIF2ADC Mux" },
1898 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1899 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1900 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1901 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1902 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1903 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1904 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1905 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1908 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1909 { "Left Sidetone", "DMIC2", "DMIC2L" },
1910 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1911 { "Right Sidetone", "DMIC2", "DMIC2R" },
1914 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1915 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1917 { "SPKL", "DAC1 Switch", "DAC1L" },
1918 { "SPKL", "DAC2 Switch", "DAC2L" },
1920 { "SPKR", "DAC1 Switch", "DAC1R" },
1921 { "SPKR", "DAC2 Switch", "DAC2R" },
1923 { "Left Headphone Mux", "DAC", "DAC1L" },
1924 { "Right Headphone Mux", "DAC", "DAC1R" },
1927 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon
[] = {
1928 { "DAC1L", NULL
, "Late DAC1L Enable PGA" },
1929 { "Late DAC1L Enable PGA", NULL
, "DAC1L Mixer" },
1930 { "DAC1R", NULL
, "Late DAC1R Enable PGA" },
1931 { "Late DAC1R Enable PGA", NULL
, "DAC1R Mixer" },
1932 { "DAC2L", NULL
, "Late DAC2L Enable PGA" },
1933 { "Late DAC2L Enable PGA", NULL
, "AIF2DAC2L Mixer" },
1934 { "DAC2R", NULL
, "Late DAC2R Enable PGA" },
1935 { "Late DAC2R Enable PGA", NULL
, "AIF2DAC2R Mixer" }
1938 static const struct snd_soc_dapm_route wm8994_lateclk_intercon
[] = {
1939 { "DAC1L", NULL
, "DAC1L Mixer" },
1940 { "DAC1R", NULL
, "DAC1R Mixer" },
1941 { "DAC2L", NULL
, "AIF2DAC2L Mixer" },
1942 { "DAC2R", NULL
, "AIF2DAC2R Mixer" },
1945 static const struct snd_soc_dapm_route wm8994_revd_intercon
[] = {
1946 { "AIF1DACDAT", NULL
, "AIF2DACDAT" },
1947 { "AIF2DACDAT", NULL
, "AIF1DACDAT" },
1948 { "AIF1ADCDAT", NULL
, "AIF2ADCDAT" },
1949 { "AIF2ADCDAT", NULL
, "AIF1ADCDAT" },
1950 { "MICBIAS1", NULL
, "CLK_SYS" },
1951 { "MICBIAS1", NULL
, "MICBIAS Supply" },
1952 { "MICBIAS2", NULL
, "CLK_SYS" },
1953 { "MICBIAS2", NULL
, "MICBIAS Supply" },
1956 static const struct snd_soc_dapm_route wm8994_intercon
[] = {
1957 { "AIF2DACL", NULL
, "AIF2DAC Mux" },
1958 { "AIF2DACR", NULL
, "AIF2DAC Mux" },
1959 { "MICBIAS1", NULL
, "VMID" },
1960 { "MICBIAS2", NULL
, "VMID" },
1963 static const struct snd_soc_dapm_route wm8958_intercon
[] = {
1964 { "AIF2DACL", NULL
, "AIF2DACL Mux" },
1965 { "AIF2DACR", NULL
, "AIF2DACR Mux" },
1967 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1968 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1969 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1970 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1972 { "AIF3DACDAT", NULL
, "AIF3" },
1973 { "AIF3ADCDAT", NULL
, "AIF3" },
1975 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1976 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1978 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1981 /* The size in bits of the FLL divide multiplied by 10
1982 * to allow rounding later */
1983 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1993 static int wm8994_get_fll_config(struct fll_div
*fll
,
1994 int freq_in
, int freq_out
)
1997 unsigned int K
, Ndiv
, Nmod
;
1999 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in
, freq_out
);
2001 /* Scale the input frequency down to <= 13.5MHz */
2002 fll
->clk_ref_div
= 0;
2003 while (freq_in
> 13500000) {
2007 if (fll
->clk_ref_div
> 3)
2010 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll
->clk_ref_div
, freq_in
);
2012 /* Scale the output to give 90MHz<=Fvco<=100MHz */
2014 while (freq_out
* (fll
->outdiv
+ 1) < 90000000) {
2016 if (fll
->outdiv
> 63)
2019 freq_out
*= fll
->outdiv
+ 1;
2020 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll
->outdiv
, freq_out
);
2022 if (freq_in
> 1000000) {
2023 fll
->fll_fratio
= 0;
2024 } else if (freq_in
> 256000) {
2025 fll
->fll_fratio
= 1;
2027 } else if (freq_in
> 128000) {
2028 fll
->fll_fratio
= 2;
2030 } else if (freq_in
> 64000) {
2031 fll
->fll_fratio
= 3;
2034 fll
->fll_fratio
= 4;
2037 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll
->fll_fratio
, freq_in
);
2039 /* Now, calculate N.K */
2040 Ndiv
= freq_out
/ freq_in
;
2043 Nmod
= freq_out
% freq_in
;
2044 pr_debug("Nmod=%d\n", Nmod
);
2046 /* Calculate fractional part - scale up so we can round. */
2047 Kpart
= FIXED_FLL_SIZE
* (long long)Nmod
;
2049 do_div(Kpart
, freq_in
);
2051 K
= Kpart
& 0xFFFFFFFF;
2056 /* Move down to proper range now rounding is done */
2059 pr_debug("N=%x K=%x\n", fll
->n
, fll
->k
);
2064 static int _wm8994_set_fll(struct snd_soc_codec
*codec
, int id
, int src
,
2065 unsigned int freq_in
, unsigned int freq_out
)
2067 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2068 struct wm8994
*control
= wm8994
->wm8994
;
2069 int reg_offset
, ret
;
2071 u16 reg
, clk1
, aif_reg
, aif_src
;
2072 unsigned long timeout
;
2090 reg
= snd_soc_read(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
);
2091 was_enabled
= reg
& WM8994_FLL1_ENA
;
2095 /* Allow no source specification when stopping */
2098 src
= wm8994
->fll
[id
].src
;
2100 case WM8994_FLL_SRC_MCLK1
:
2101 case WM8994_FLL_SRC_MCLK2
:
2102 case WM8994_FLL_SRC_LRCLK
:
2103 case WM8994_FLL_SRC_BCLK
:
2105 case WM8994_FLL_SRC_INTERNAL
:
2107 freq_out
= 12000000;
2113 /* Are we changing anything? */
2114 if (wm8994
->fll
[id
].src
== src
&&
2115 wm8994
->fll
[id
].in
== freq_in
&& wm8994
->fll
[id
].out
== freq_out
)
2118 /* If we're stopping the FLL redo the old config - no
2119 * registers will actually be written but we avoid GCC flow
2120 * analysis bugs spewing warnings.
2123 ret
= wm8994_get_fll_config(&fll
, freq_in
, freq_out
);
2125 ret
= wm8994_get_fll_config(&fll
, wm8994
->fll
[id
].in
,
2126 wm8994
->fll
[id
].out
);
2130 /* Make sure that we're not providing SYSCLK right now */
2131 clk1
= snd_soc_read(codec
, WM8994_CLOCKING_1
);
2132 if (clk1
& WM8994_SYSCLK_SRC
)
2133 aif_reg
= WM8994_AIF2_CLOCKING_1
;
2135 aif_reg
= WM8994_AIF1_CLOCKING_1
;
2136 reg
= snd_soc_read(codec
, aif_reg
);
2138 if ((reg
& WM8994_AIF1CLK_ENA
) &&
2139 (reg
& WM8994_AIF1CLK_SRC_MASK
) == aif_src
) {
2140 dev_err(codec
->dev
, "FLL%d is currently providing SYSCLK\n",
2145 /* We always need to disable the FLL while reconfiguring */
2146 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
,
2147 WM8994_FLL1_ENA
, 0);
2149 if (wm8994
->fll_byp
&& src
== WM8994_FLL_SRC_BCLK
&&
2150 freq_in
== freq_out
&& freq_out
) {
2151 dev_dbg(codec
->dev
, "Bypassing FLL%d\n", id
+ 1);
2152 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_5
+ reg_offset
,
2153 WM8958_FLL1_BYP
, WM8958_FLL1_BYP
);
2157 reg
= (fll
.outdiv
<< WM8994_FLL1_OUTDIV_SHIFT
) |
2158 (fll
.fll_fratio
<< WM8994_FLL1_FRATIO_SHIFT
);
2159 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_2
+ reg_offset
,
2160 WM8994_FLL1_OUTDIV_MASK
|
2161 WM8994_FLL1_FRATIO_MASK
, reg
);
2163 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_3
+ reg_offset
,
2164 WM8994_FLL1_K_MASK
, fll
.k
);
2166 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_4
+ reg_offset
,
2168 fll
.n
<< WM8994_FLL1_N_SHIFT
);
2170 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_5
+ reg_offset
,
2171 WM8994_FLL1_FRC_NCO
| WM8958_FLL1_BYP
|
2172 WM8994_FLL1_REFCLK_DIV_MASK
|
2173 WM8994_FLL1_REFCLK_SRC_MASK
,
2174 ((src
== WM8994_FLL_SRC_INTERNAL
)
2175 << WM8994_FLL1_FRC_NCO_SHIFT
) |
2176 (fll
.clk_ref_div
<< WM8994_FLL1_REFCLK_DIV_SHIFT
) |
2179 /* Clear any pending completion from a previous failure */
2180 try_wait_for_completion(&wm8994
->fll_locked
[id
]);
2182 /* Enable (with fractional mode if required) */
2184 /* Enable VMID if we need it */
2186 active_reference(codec
);
2188 switch (control
->type
) {
2190 vmid_reference(codec
);
2193 if (wm8994
->revision
< 1)
2194 vmid_reference(codec
);
2201 reg
= WM8994_FLL1_ENA
;
2204 reg
|= WM8994_FLL1_FRAC
;
2205 if (src
== WM8994_FLL_SRC_INTERNAL
)
2206 reg
|= WM8994_FLL1_OSC_ENA
;
2208 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
,
2209 WM8994_FLL1_ENA
| WM8994_FLL1_OSC_ENA
|
2210 WM8994_FLL1_FRAC
, reg
);
2212 if (wm8994
->fll_locked_irq
) {
2213 timeout
= wait_for_completion_timeout(&wm8994
->fll_locked
[id
],
2214 msecs_to_jiffies(10));
2216 dev_warn(codec
->dev
,
2217 "Timed out waiting for FLL lock\n");
2223 switch (control
->type
) {
2225 vmid_dereference(codec
);
2228 if (wm8994
->revision
< 1)
2229 vmid_dereference(codec
);
2235 active_dereference(codec
);
2240 wm8994
->fll
[id
].in
= freq_in
;
2241 wm8994
->fll
[id
].out
= freq_out
;
2242 wm8994
->fll
[id
].src
= src
;
2244 configure_clock(codec
);
2249 static irqreturn_t
wm8994_fll_locked_irq(int irq
, void *data
)
2251 struct completion
*completion
= data
;
2253 complete(completion
);
2258 static int opclk_divs
[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2260 static int wm8994_set_fll(struct snd_soc_dai
*dai
, int id
, int src
,
2261 unsigned int freq_in
, unsigned int freq_out
)
2263 return _wm8994_set_fll(dai
->codec
, id
, src
, freq_in
, freq_out
);
2266 static int wm8994_set_dai_sysclk(struct snd_soc_dai
*dai
,
2267 int clk_id
, unsigned int freq
, int dir
)
2269 struct snd_soc_codec
*codec
= dai
->codec
;
2270 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2279 /* AIF3 shares clocking with AIF1/2 */
2284 case WM8994_SYSCLK_MCLK1
:
2285 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_MCLK1
;
2286 wm8994
->mclk
[0] = freq
;
2287 dev_dbg(dai
->dev
, "AIF%d using MCLK1 at %uHz\n",
2291 case WM8994_SYSCLK_MCLK2
:
2292 /* TODO: Set GPIO AF */
2293 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_MCLK2
;
2294 wm8994
->mclk
[1] = freq
;
2295 dev_dbg(dai
->dev
, "AIF%d using MCLK2 at %uHz\n",
2299 case WM8994_SYSCLK_FLL1
:
2300 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_FLL1
;
2301 dev_dbg(dai
->dev
, "AIF%d using FLL1\n", dai
->id
);
2304 case WM8994_SYSCLK_FLL2
:
2305 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_FLL2
;
2306 dev_dbg(dai
->dev
, "AIF%d using FLL2\n", dai
->id
);
2309 case WM8994_SYSCLK_OPCLK
:
2310 /* Special case - a division (times 10) is given and
2311 * no effect on main clocking.
2314 for (i
= 0; i
< ARRAY_SIZE(opclk_divs
); i
++)
2315 if (opclk_divs
[i
] == freq
)
2317 if (i
== ARRAY_SIZE(opclk_divs
))
2319 snd_soc_update_bits(codec
, WM8994_CLOCKING_2
,
2320 WM8994_OPCLK_DIV_MASK
, i
);
2321 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_2
,
2322 WM8994_OPCLK_ENA
, WM8994_OPCLK_ENA
);
2324 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_2
,
2325 WM8994_OPCLK_ENA
, 0);
2332 configure_clock(codec
);
2337 static int wm8994_set_bias_level(struct snd_soc_codec
*codec
,
2338 enum snd_soc_bias_level level
)
2340 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2341 struct wm8994
*control
= wm8994
->wm8994
;
2343 wm_hubs_set_bias_level(codec
, level
);
2346 case SND_SOC_BIAS_ON
:
2349 case SND_SOC_BIAS_PREPARE
:
2350 /* MICBIAS into regulating mode */
2351 switch (control
->type
) {
2354 snd_soc_update_bits(codec
, WM8958_MICBIAS1
,
2355 WM8958_MICB1_MODE
, 0);
2356 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
2357 WM8958_MICB2_MODE
, 0);
2363 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_STANDBY
)
2364 active_reference(codec
);
2367 case SND_SOC_BIAS_STANDBY
:
2368 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
2369 switch (control
->type
) {
2371 if (wm8994
->revision
== 0) {
2372 /* Optimise performance for rev A */
2373 snd_soc_update_bits(codec
,
2374 WM8958_CHARGE_PUMP_2
,
2384 /* Discharge LINEOUT1 & 2 */
2385 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
2386 WM8994_LINEOUT1_DISCH
|
2387 WM8994_LINEOUT2_DISCH
,
2388 WM8994_LINEOUT1_DISCH
|
2389 WM8994_LINEOUT2_DISCH
);
2392 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_PREPARE
)
2393 active_dereference(codec
);
2395 /* MICBIAS into bypass mode on newer devices */
2396 switch (control
->type
) {
2399 snd_soc_update_bits(codec
, WM8958_MICBIAS1
,
2402 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
2411 case SND_SOC_BIAS_OFF
:
2412 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_STANDBY
)
2413 wm8994
->cur_fw
= NULL
;
2417 codec
->dapm
.bias_level
= level
;
2422 int wm8994_vmid_mode(struct snd_soc_codec
*codec
, enum wm8994_vmid_mode mode
)
2424 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2427 case WM8994_VMID_NORMAL
:
2428 if (wm8994
->hubs
.lineout1_se
) {
2429 snd_soc_dapm_disable_pin(&codec
->dapm
,
2430 "LINEOUT1N Driver");
2431 snd_soc_dapm_disable_pin(&codec
->dapm
,
2432 "LINEOUT1P Driver");
2434 if (wm8994
->hubs
.lineout2_se
) {
2435 snd_soc_dapm_disable_pin(&codec
->dapm
,
2436 "LINEOUT2N Driver");
2437 snd_soc_dapm_disable_pin(&codec
->dapm
,
2438 "LINEOUT2P Driver");
2441 /* Do the sync with the old mode to allow it to clean up */
2442 snd_soc_dapm_sync(&codec
->dapm
);
2443 wm8994
->vmid_mode
= mode
;
2446 case WM8994_VMID_FORCE
:
2447 if (wm8994
->hubs
.lineout1_se
) {
2448 snd_soc_dapm_force_enable_pin(&codec
->dapm
,
2449 "LINEOUT1N Driver");
2450 snd_soc_dapm_force_enable_pin(&codec
->dapm
,
2451 "LINEOUT1P Driver");
2453 if (wm8994
->hubs
.lineout2_se
) {
2454 snd_soc_dapm_force_enable_pin(&codec
->dapm
,
2455 "LINEOUT2N Driver");
2456 snd_soc_dapm_force_enable_pin(&codec
->dapm
,
2457 "LINEOUT2P Driver");
2460 wm8994
->vmid_mode
= mode
;
2461 snd_soc_dapm_sync(&codec
->dapm
);
2471 static int wm8994_set_dai_fmt(struct snd_soc_dai
*dai
, unsigned int fmt
)
2473 struct snd_soc_codec
*codec
= dai
->codec
;
2474 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2475 struct wm8994
*control
= wm8994
->wm8994
;
2483 ms_reg
= WM8994_AIF1_MASTER_SLAVE
;
2484 aif1_reg
= WM8994_AIF1_CONTROL_1
;
2487 ms_reg
= WM8994_AIF2_MASTER_SLAVE
;
2488 aif1_reg
= WM8994_AIF2_CONTROL_1
;
2494 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
2495 case SND_SOC_DAIFMT_CBS_CFS
:
2497 case SND_SOC_DAIFMT_CBM_CFM
:
2498 ms
= WM8994_AIF1_MSTR
;
2504 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
2505 case SND_SOC_DAIFMT_DSP_B
:
2506 aif1
|= WM8994_AIF1_LRCLK_INV
;
2507 case SND_SOC_DAIFMT_DSP_A
:
2510 case SND_SOC_DAIFMT_I2S
:
2513 case SND_SOC_DAIFMT_RIGHT_J
:
2515 case SND_SOC_DAIFMT_LEFT_J
:
2522 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
2523 case SND_SOC_DAIFMT_DSP_A
:
2524 case SND_SOC_DAIFMT_DSP_B
:
2525 /* frame inversion not valid for DSP modes */
2526 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
2527 case SND_SOC_DAIFMT_NB_NF
:
2529 case SND_SOC_DAIFMT_IB_NF
:
2530 aif1
|= WM8994_AIF1_BCLK_INV
;
2537 case SND_SOC_DAIFMT_I2S
:
2538 case SND_SOC_DAIFMT_RIGHT_J
:
2539 case SND_SOC_DAIFMT_LEFT_J
:
2540 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
2541 case SND_SOC_DAIFMT_NB_NF
:
2543 case SND_SOC_DAIFMT_IB_IF
:
2544 aif1
|= WM8994_AIF1_BCLK_INV
| WM8994_AIF1_LRCLK_INV
;
2546 case SND_SOC_DAIFMT_IB_NF
:
2547 aif1
|= WM8994_AIF1_BCLK_INV
;
2549 case SND_SOC_DAIFMT_NB_IF
:
2550 aif1
|= WM8994_AIF1_LRCLK_INV
;
2560 /* The AIF2 format configuration needs to be mirrored to AIF3
2561 * on WM8958 if it's in use so just do it all the time. */
2562 switch (control
->type
) {
2566 snd_soc_update_bits(codec
, WM8958_AIF3_CONTROL_1
,
2567 WM8994_AIF1_LRCLK_INV
|
2568 WM8958_AIF3_FMT_MASK
, aif1
);
2575 snd_soc_update_bits(codec
, aif1_reg
,
2576 WM8994_AIF1_BCLK_INV
| WM8994_AIF1_LRCLK_INV
|
2577 WM8994_AIF1_FMT_MASK
,
2579 snd_soc_update_bits(codec
, ms_reg
, WM8994_AIF1_MSTR
,
2601 static int fs_ratios
[] = {
2602 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2605 static int bclk_divs
[] = {
2606 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2607 640, 880, 960, 1280, 1760, 1920
2610 static int wm8994_hw_params(struct snd_pcm_substream
*substream
,
2611 struct snd_pcm_hw_params
*params
,
2612 struct snd_soc_dai
*dai
)
2614 struct snd_soc_codec
*codec
= dai
->codec
;
2615 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2626 int id
= dai
->id
- 1;
2628 int i
, cur_val
, best_val
, bclk_rate
, best
;
2632 aif1_reg
= WM8994_AIF1_CONTROL_1
;
2633 aif2_reg
= WM8994_AIF1_CONTROL_2
;
2634 bclk_reg
= WM8994_AIF1_BCLK
;
2635 rate_reg
= WM8994_AIF1_RATE
;
2636 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
||
2637 wm8994
->lrclk_shared
[0]) {
2638 lrclk_reg
= WM8994_AIF1DAC_LRCLK
;
2640 lrclk_reg
= WM8994_AIF1ADC_LRCLK
;
2641 dev_dbg(codec
->dev
, "AIF1 using split LRCLK\n");
2645 aif1_reg
= WM8994_AIF2_CONTROL_1
;
2646 aif2_reg
= WM8994_AIF2_CONTROL_2
;
2647 bclk_reg
= WM8994_AIF2_BCLK
;
2648 rate_reg
= WM8994_AIF2_RATE
;
2649 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
||
2650 wm8994
->lrclk_shared
[1]) {
2651 lrclk_reg
= WM8994_AIF2DAC_LRCLK
;
2653 lrclk_reg
= WM8994_AIF2ADC_LRCLK
;
2654 dev_dbg(codec
->dev
, "AIF2 using split LRCLK\n");
2661 bclk_rate
= params_rate(params
) * 4;
2662 switch (params_format(params
)) {
2663 case SNDRV_PCM_FORMAT_S16_LE
:
2666 case SNDRV_PCM_FORMAT_S20_3LE
:
2670 case SNDRV_PCM_FORMAT_S24_LE
:
2674 case SNDRV_PCM_FORMAT_S32_LE
:
2682 /* Try to find an appropriate sample rate; look for an exact match. */
2683 for (i
= 0; i
< ARRAY_SIZE(srs
); i
++)
2684 if (srs
[i
].rate
== params_rate(params
))
2686 if (i
== ARRAY_SIZE(srs
))
2688 rate_val
|= srs
[i
].val
<< WM8994_AIF1_SR_SHIFT
;
2690 dev_dbg(dai
->dev
, "Sample rate is %dHz\n", srs
[i
].rate
);
2691 dev_dbg(dai
->dev
, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2692 dai
->id
, wm8994
->aifclk
[id
], bclk_rate
);
2694 if (params_channels(params
) == 1 &&
2695 (snd_soc_read(codec
, aif1_reg
) & 0x18) == 0x18)
2696 aif2
|= WM8994_AIF1_MONO
;
2698 if (wm8994
->aifclk
[id
] == 0) {
2699 dev_err(dai
->dev
, "AIF%dCLK not configured\n", dai
->id
);
2703 /* AIFCLK/fs ratio; look for a close match in either direction */
2705 best_val
= abs((fs_ratios
[0] * params_rate(params
))
2706 - wm8994
->aifclk
[id
]);
2707 for (i
= 1; i
< ARRAY_SIZE(fs_ratios
); i
++) {
2708 cur_val
= abs((fs_ratios
[i
] * params_rate(params
))
2709 - wm8994
->aifclk
[id
]);
2710 if (cur_val
>= best_val
)
2715 dev_dbg(dai
->dev
, "Selected AIF%dCLK/fs = %d\n",
2716 dai
->id
, fs_ratios
[best
]);
2719 /* We may not get quite the right frequency if using
2720 * approximate clocks so look for the closest match that is
2721 * higher than the target (we need to ensure that there enough
2722 * BCLKs to clock out the samples).
2725 for (i
= 0; i
< ARRAY_SIZE(bclk_divs
); i
++) {
2726 cur_val
= (wm8994
->aifclk
[id
] * 10 / bclk_divs
[i
]) - bclk_rate
;
2727 if (cur_val
< 0) /* BCLK table is sorted */
2731 bclk_rate
= wm8994
->aifclk
[id
] * 10 / bclk_divs
[best
];
2732 dev_dbg(dai
->dev
, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2733 bclk_divs
[best
], bclk_rate
);
2734 bclk
|= best
<< WM8994_AIF1_BCLK_DIV_SHIFT
;
2736 lrclk
= bclk_rate
/ params_rate(params
);
2738 dev_err(dai
->dev
, "Unable to generate LRCLK from %dHz BCLK\n",
2742 dev_dbg(dai
->dev
, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2743 lrclk
, bclk_rate
/ lrclk
);
2745 snd_soc_update_bits(codec
, aif1_reg
, WM8994_AIF1_WL_MASK
, aif1
);
2746 snd_soc_update_bits(codec
, aif2_reg
, WM8994_AIF1_MONO
, aif2
);
2747 snd_soc_update_bits(codec
, bclk_reg
, WM8994_AIF1_BCLK_DIV_MASK
, bclk
);
2748 snd_soc_update_bits(codec
, lrclk_reg
, WM8994_AIF1DAC_RATE_MASK
,
2750 snd_soc_update_bits(codec
, rate_reg
, WM8994_AIF1_SR_MASK
|
2751 WM8994_AIF1CLK_RATE_MASK
, rate_val
);
2753 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
2756 wm8994
->dac_rates
[0] = params_rate(params
);
2757 wm8994_set_retune_mobile(codec
, 0);
2758 wm8994_set_retune_mobile(codec
, 1);
2761 wm8994
->dac_rates
[1] = params_rate(params
);
2762 wm8994_set_retune_mobile(codec
, 2);
2770 static int wm8994_aif3_hw_params(struct snd_pcm_substream
*substream
,
2771 struct snd_pcm_hw_params
*params
,
2772 struct snd_soc_dai
*dai
)
2774 struct snd_soc_codec
*codec
= dai
->codec
;
2775 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2776 struct wm8994
*control
= wm8994
->wm8994
;
2782 switch (control
->type
) {
2785 aif1_reg
= WM8958_AIF3_CONTROL_1
;
2794 switch (params_format(params
)) {
2795 case SNDRV_PCM_FORMAT_S16_LE
:
2797 case SNDRV_PCM_FORMAT_S20_3LE
:
2800 case SNDRV_PCM_FORMAT_S24_LE
:
2803 case SNDRV_PCM_FORMAT_S32_LE
:
2810 return snd_soc_update_bits(codec
, aif1_reg
, WM8994_AIF1_WL_MASK
, aif1
);
2813 static int wm8994_aif_mute(struct snd_soc_dai
*codec_dai
, int mute
)
2815 struct snd_soc_codec
*codec
= codec_dai
->codec
;
2819 switch (codec_dai
->id
) {
2821 mute_reg
= WM8994_AIF1_DAC1_FILTERS_1
;
2824 mute_reg
= WM8994_AIF2_DAC_FILTERS_1
;
2831 reg
= WM8994_AIF1DAC1_MUTE
;
2835 snd_soc_update_bits(codec
, mute_reg
, WM8994_AIF1DAC1_MUTE
, reg
);
2840 static int wm8994_set_tristate(struct snd_soc_dai
*codec_dai
, int tristate
)
2842 struct snd_soc_codec
*codec
= codec_dai
->codec
;
2845 switch (codec_dai
->id
) {
2847 reg
= WM8994_AIF1_MASTER_SLAVE
;
2848 mask
= WM8994_AIF1_TRI
;
2851 reg
= WM8994_AIF2_MASTER_SLAVE
;
2852 mask
= WM8994_AIF2_TRI
;
2863 return snd_soc_update_bits(codec
, reg
, mask
, val
);
2866 static int wm8994_aif2_probe(struct snd_soc_dai
*dai
)
2868 struct snd_soc_codec
*codec
= dai
->codec
;
2870 /* Disable the pulls on the AIF if we're using it to save power. */
2871 snd_soc_update_bits(codec
, WM8994_GPIO_3
,
2872 WM8994_GPN_PU
| WM8994_GPN_PD
, 0);
2873 snd_soc_update_bits(codec
, WM8994_GPIO_4
,
2874 WM8994_GPN_PU
| WM8994_GPN_PD
, 0);
2875 snd_soc_update_bits(codec
, WM8994_GPIO_5
,
2876 WM8994_GPN_PU
| WM8994_GPN_PD
, 0);
2881 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2883 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2884 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2886 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops
= {
2887 .set_sysclk
= wm8994_set_dai_sysclk
,
2888 .set_fmt
= wm8994_set_dai_fmt
,
2889 .hw_params
= wm8994_hw_params
,
2890 .digital_mute
= wm8994_aif_mute
,
2891 .set_pll
= wm8994_set_fll
,
2892 .set_tristate
= wm8994_set_tristate
,
2895 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops
= {
2896 .set_sysclk
= wm8994_set_dai_sysclk
,
2897 .set_fmt
= wm8994_set_dai_fmt
,
2898 .hw_params
= wm8994_hw_params
,
2899 .digital_mute
= wm8994_aif_mute
,
2900 .set_pll
= wm8994_set_fll
,
2901 .set_tristate
= wm8994_set_tristate
,
2904 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops
= {
2905 .hw_params
= wm8994_aif3_hw_params
,
2908 static struct snd_soc_dai_driver wm8994_dai
[] = {
2910 .name
= "wm8994-aif1",
2913 .stream_name
= "AIF1 Playback",
2916 .rates
= WM8994_RATES
,
2917 .formats
= WM8994_FORMATS
,
2921 .stream_name
= "AIF1 Capture",
2924 .rates
= WM8994_RATES
,
2925 .formats
= WM8994_FORMATS
,
2928 .ops
= &wm8994_aif1_dai_ops
,
2931 .name
= "wm8994-aif2",
2934 .stream_name
= "AIF2 Playback",
2937 .rates
= WM8994_RATES
,
2938 .formats
= WM8994_FORMATS
,
2942 .stream_name
= "AIF2 Capture",
2945 .rates
= WM8994_RATES
,
2946 .formats
= WM8994_FORMATS
,
2949 .probe
= wm8994_aif2_probe
,
2950 .ops
= &wm8994_aif2_dai_ops
,
2953 .name
= "wm8994-aif3",
2956 .stream_name
= "AIF3 Playback",
2959 .rates
= WM8994_RATES
,
2960 .formats
= WM8994_FORMATS
,
2964 .stream_name
= "AIF3 Capture",
2967 .rates
= WM8994_RATES
,
2968 .formats
= WM8994_FORMATS
,
2971 .ops
= &wm8994_aif3_dai_ops
,
2976 static int wm8994_codec_suspend(struct snd_soc_codec
*codec
)
2978 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2981 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll
); i
++) {
2982 memcpy(&wm8994
->fll_suspend
[i
], &wm8994
->fll
[i
],
2983 sizeof(struct wm8994_fll_config
));
2984 ret
= _wm8994_set_fll(codec
, i
+ 1, 0, 0, 0);
2986 dev_warn(codec
->dev
, "Failed to stop FLL%d: %d\n",
2990 wm8994_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
2995 static int wm8994_codec_resume(struct snd_soc_codec
*codec
)
2997 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2998 struct wm8994
*control
= wm8994
->wm8994
;
3000 unsigned int val
, mask
;
3002 if (wm8994
->revision
< 4) {
3003 /* force a HW read */
3004 ret
= regmap_read(control
->regmap
,
3005 WM8994_POWER_MANAGEMENT_5
, &val
);
3007 /* modify the cache only */
3008 codec
->cache_only
= 1;
3009 mask
= WM8994_DAC1R_ENA
| WM8994_DAC1L_ENA
|
3010 WM8994_DAC2R_ENA
| WM8994_DAC2L_ENA
;
3012 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
3014 codec
->cache_only
= 0;
3017 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll
); i
++) {
3018 if (!wm8994
->fll_suspend
[i
].out
)
3021 ret
= _wm8994_set_fll(codec
, i
+ 1,
3022 wm8994
->fll_suspend
[i
].src
,
3023 wm8994
->fll_suspend
[i
].in
,
3024 wm8994
->fll_suspend
[i
].out
);
3026 dev_warn(codec
->dev
, "Failed to restore FLL%d: %d\n",
3033 #define wm8994_codec_suspend NULL
3034 #define wm8994_codec_resume NULL
3037 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv
*wm8994
)
3039 struct snd_soc_codec
*codec
= wm8994
->hubs
.codec
;
3040 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
3041 struct snd_kcontrol_new controls
[] = {
3042 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3043 wm8994
->retune_mobile_enum
,
3044 wm8994_get_retune_mobile_enum
,
3045 wm8994_put_retune_mobile_enum
),
3046 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3047 wm8994
->retune_mobile_enum
,
3048 wm8994_get_retune_mobile_enum
,
3049 wm8994_put_retune_mobile_enum
),
3050 SOC_ENUM_EXT("AIF2 EQ Mode",
3051 wm8994
->retune_mobile_enum
,
3052 wm8994_get_retune_mobile_enum
,
3053 wm8994_put_retune_mobile_enum
),
3058 /* We need an array of texts for the enum API but the number
3059 * of texts is likely to be less than the number of
3060 * configurations due to the sample rate dependency of the
3061 * configurations. */
3062 wm8994
->num_retune_mobile_texts
= 0;
3063 wm8994
->retune_mobile_texts
= NULL
;
3064 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
3065 for (j
= 0; j
< wm8994
->num_retune_mobile_texts
; j
++) {
3066 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
3067 wm8994
->retune_mobile_texts
[j
]) == 0)
3071 if (j
!= wm8994
->num_retune_mobile_texts
)
3074 /* Expand the array... */
3075 t
= krealloc(wm8994
->retune_mobile_texts
,
3077 (wm8994
->num_retune_mobile_texts
+ 1),
3082 /* ...store the new entry... */
3083 t
[wm8994
->num_retune_mobile_texts
] =
3084 pdata
->retune_mobile_cfgs
[i
].name
;
3086 /* ...and remember the new version. */
3087 wm8994
->num_retune_mobile_texts
++;
3088 wm8994
->retune_mobile_texts
= t
;
3091 dev_dbg(codec
->dev
, "Allocated %d unique ReTune Mobile names\n",
3092 wm8994
->num_retune_mobile_texts
);
3094 wm8994
->retune_mobile_enum
.max
= wm8994
->num_retune_mobile_texts
;
3095 wm8994
->retune_mobile_enum
.texts
= wm8994
->retune_mobile_texts
;
3097 ret
= snd_soc_add_codec_controls(wm8994
->hubs
.codec
, controls
,
3098 ARRAY_SIZE(controls
));
3100 dev_err(wm8994
->hubs
.codec
->dev
,
3101 "Failed to add ReTune Mobile controls: %d\n", ret
);
3104 static void wm8994_handle_pdata(struct wm8994_priv
*wm8994
)
3106 struct snd_soc_codec
*codec
= wm8994
->hubs
.codec
;
3107 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
3113 wm_hubs_handle_analogue_pdata(codec
, pdata
->lineout1_diff
,
3114 pdata
->lineout2_diff
,
3119 pdata
->micbias1_lvl
,
3120 pdata
->micbias2_lvl
);
3122 dev_dbg(codec
->dev
, "%d DRC configurations\n", pdata
->num_drc_cfgs
);
3124 if (pdata
->num_drc_cfgs
) {
3125 struct snd_kcontrol_new controls
[] = {
3126 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994
->drc_enum
,
3127 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
3128 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994
->drc_enum
,
3129 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
3130 SOC_ENUM_EXT("AIF2DRC Mode", wm8994
->drc_enum
,
3131 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
3134 /* We need an array of texts for the enum API */
3135 wm8994
->drc_texts
= devm_kzalloc(wm8994
->hubs
.codec
->dev
,
3136 sizeof(char *) * pdata
->num_drc_cfgs
, GFP_KERNEL
);
3137 if (!wm8994
->drc_texts
) {
3138 dev_err(wm8994
->hubs
.codec
->dev
,
3139 "Failed to allocate %d DRC config texts\n",
3140 pdata
->num_drc_cfgs
);
3144 for (i
= 0; i
< pdata
->num_drc_cfgs
; i
++)
3145 wm8994
->drc_texts
[i
] = pdata
->drc_cfgs
[i
].name
;
3147 wm8994
->drc_enum
.max
= pdata
->num_drc_cfgs
;
3148 wm8994
->drc_enum
.texts
= wm8994
->drc_texts
;
3150 ret
= snd_soc_add_codec_controls(wm8994
->hubs
.codec
, controls
,
3151 ARRAY_SIZE(controls
));
3153 dev_err(wm8994
->hubs
.codec
->dev
,
3154 "Failed to add DRC mode controls: %d\n", ret
);
3156 for (i
= 0; i
< WM8994_NUM_DRC
; i
++)
3157 wm8994_set_drc(codec
, i
);
3160 dev_dbg(codec
->dev
, "%d ReTune Mobile configurations\n",
3161 pdata
->num_retune_mobile_cfgs
);
3163 if (pdata
->num_retune_mobile_cfgs
)
3164 wm8994_handle_retune_mobile_pdata(wm8994
);
3166 snd_soc_add_codec_controls(wm8994
->hubs
.codec
, wm8994_eq_controls
,
3167 ARRAY_SIZE(wm8994_eq_controls
));
3169 for (i
= 0; i
< ARRAY_SIZE(pdata
->micbias
); i
++) {
3170 if (pdata
->micbias
[i
]) {
3171 snd_soc_write(codec
, WM8958_MICBIAS1
+ i
,
3172 pdata
->micbias
[i
] & 0xffff);
3178 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3180 * @codec: WM8994 codec
3181 * @jack: jack to report detection events on
3182 * @micbias: microphone bias to detect on
3184 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3185 * being used to bring out signals to the processor then only platform
3186 * data configuration is needed for WM8994 and processor GPIOs should
3187 * be configured using snd_soc_jack_add_gpios() instead.
3189 * Configuration of detection levels is available via the micbias1_lvl
3190 * and micbias2_lvl platform data members.
3192 int wm8994_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
3195 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3196 struct wm8994_micdet
*micdet
;
3197 struct wm8994
*control
= wm8994
->wm8994
;
3200 if (control
->type
!= WM8994
) {
3201 dev_warn(codec
->dev
, "Not a WM8994\n");
3207 micdet
= &wm8994
->micdet
[0];
3209 ret
= snd_soc_dapm_force_enable_pin(&codec
->dapm
,
3212 ret
= snd_soc_dapm_disable_pin(&codec
->dapm
,
3216 micdet
= &wm8994
->micdet
[1];
3218 ret
= snd_soc_dapm_force_enable_pin(&codec
->dapm
,
3221 ret
= snd_soc_dapm_disable_pin(&codec
->dapm
,
3225 dev_warn(codec
->dev
, "Invalid MICBIAS %d\n", micbias
);
3230 dev_warn(codec
->dev
, "Failed to configure MICBIAS%d: %d\n",
3233 dev_dbg(codec
->dev
, "Configuring microphone detection on %d %p\n",
3236 /* Store the configuration */
3237 micdet
->jack
= jack
;
3238 micdet
->detecting
= true;
3240 /* If either of the jacks is set up then enable detection */
3241 if (wm8994
->micdet
[0].jack
|| wm8994
->micdet
[1].jack
)
3242 reg
= WM8994_MICD_ENA
;
3246 snd_soc_update_bits(codec
, WM8994_MICBIAS
, WM8994_MICD_ENA
, reg
);
3248 snd_soc_dapm_sync(&codec
->dapm
);
3252 EXPORT_SYMBOL_GPL(wm8994_mic_detect
);
3254 static void wm8994_mic_work(struct work_struct
*work
)
3256 struct wm8994_priv
*priv
= container_of(work
,
3259 struct regmap
*regmap
= priv
->wm8994
->regmap
;
3260 struct device
*dev
= priv
->wm8994
->dev
;
3265 pm_runtime_get_sync(dev
);
3267 ret
= regmap_read(regmap
, WM8994_INTERRUPT_RAW_STATUS_2
, ®
);
3269 dev_err(dev
, "Failed to read microphone status: %d\n",
3271 pm_runtime_put(dev
);
3275 dev_dbg(dev
, "Microphone status: %x\n", reg
);
3278 if (reg
& WM8994_MIC1_DET_STS
) {
3279 if (priv
->micdet
[0].detecting
)
3280 report
= SND_JACK_HEADSET
;
3282 if (reg
& WM8994_MIC1_SHRT_STS
) {
3283 if (priv
->micdet
[0].detecting
)
3284 report
= SND_JACK_HEADPHONE
;
3286 report
|= SND_JACK_BTN_0
;
3289 priv
->micdet
[0].detecting
= false;
3291 priv
->micdet
[0].detecting
= true;
3293 snd_soc_jack_report(priv
->micdet
[0].jack
, report
,
3294 SND_JACK_HEADSET
| SND_JACK_BTN_0
);
3297 if (reg
& WM8994_MIC2_DET_STS
) {
3298 if (priv
->micdet
[1].detecting
)
3299 report
= SND_JACK_HEADSET
;
3301 if (reg
& WM8994_MIC2_SHRT_STS
) {
3302 if (priv
->micdet
[1].detecting
)
3303 report
= SND_JACK_HEADPHONE
;
3305 report
|= SND_JACK_BTN_0
;
3308 priv
->micdet
[1].detecting
= false;
3310 priv
->micdet
[1].detecting
= true;
3312 snd_soc_jack_report(priv
->micdet
[1].jack
, report
,
3313 SND_JACK_HEADSET
| SND_JACK_BTN_0
);
3315 pm_runtime_put(dev
);
3318 static irqreturn_t
wm8994_mic_irq(int irq
, void *data
)
3320 struct wm8994_priv
*priv
= data
;
3321 struct snd_soc_codec
*codec
= priv
->hubs
.codec
;
3323 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3324 trace_snd_soc_jack_irq(dev_name(codec
->dev
));
3327 pm_wakeup_event(codec
->dev
, 300);
3329 schedule_delayed_work(&priv
->mic_work
, msecs_to_jiffies(250));
3334 /* Default microphone detection handler for WM8958 - the user can
3335 * override this if they wish.
3337 static void wm8958_default_micdet(u16 status
, void *data
)
3339 struct snd_soc_codec
*codec
= data
;
3340 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3343 dev_dbg(codec
->dev
, "MICDET %x\n", status
);
3345 /* Either nothing present or just starting detection */
3346 if (!(status
& WM8958_MICD_STS
)) {
3347 if (!wm8994
->jackdet
) {
3348 /* If nothing present then clear our statuses */
3349 dev_dbg(codec
->dev
, "Detected open circuit\n");
3350 wm8994
->jack_mic
= false;
3351 wm8994
->mic_detecting
= true;
3353 wm8958_micd_set_rate(codec
);
3355 snd_soc_jack_report(wm8994
->micdet
[0].jack
, 0,
3362 /* If the measurement is showing a high impedence we've got a
3365 if (wm8994
->mic_detecting
&& (status
& 0x600)) {
3366 dev_dbg(codec
->dev
, "Detected microphone\n");
3368 wm8994
->mic_detecting
= false;
3369 wm8994
->jack_mic
= true;
3371 wm8958_micd_set_rate(codec
);
3373 snd_soc_jack_report(wm8994
->micdet
[0].jack
, SND_JACK_HEADSET
,
3378 if (wm8994
->mic_detecting
&& status
& 0xfc) {
3379 dev_dbg(codec
->dev
, "Detected headphone\n");
3380 wm8994
->mic_detecting
= false;
3382 wm8958_micd_set_rate(codec
);
3384 /* If we have jackdet that will detect removal */
3385 if (wm8994
->jackdet
) {
3386 mutex_lock(&wm8994
->accdet_lock
);
3388 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3389 WM8958_MICD_ENA
, 0);
3391 wm1811_jackdet_set_mode(codec
,
3392 WM1811_JACKDET_MODE_JACK
);
3394 mutex_unlock(&wm8994
->accdet_lock
);
3396 if (wm8994
->pdata
->jd_ext_cap
)
3397 snd_soc_dapm_disable_pin(&codec
->dapm
,
3401 snd_soc_jack_report(wm8994
->micdet
[0].jack
, SND_JACK_HEADPHONE
,
3405 /* Report short circuit as a button */
3406 if (wm8994
->jack_mic
) {
3409 report
|= SND_JACK_BTN_0
;
3412 report
|= SND_JACK_BTN_1
;
3415 report
|= SND_JACK_BTN_2
;
3418 report
|= SND_JACK_BTN_3
;
3421 report
|= SND_JACK_BTN_4
;
3424 report
|= SND_JACK_BTN_5
;
3426 snd_soc_jack_report(wm8994
->micdet
[0].jack
, report
,
3431 static irqreturn_t
wm1811_jackdet_irq(int irq
, void *data
)
3433 struct wm8994_priv
*wm8994
= data
;
3434 struct snd_soc_codec
*codec
= wm8994
->hubs
.codec
;
3438 pm_runtime_get_sync(codec
->dev
);
3440 mutex_lock(&wm8994
->accdet_lock
);
3442 reg
= snd_soc_read(codec
, WM1811_JACKDET_CTRL
);
3444 dev_err(codec
->dev
, "Failed to read jack status: %d\n", reg
);
3445 mutex_unlock(&wm8994
->accdet_lock
);
3446 pm_runtime_put(codec
->dev
);
3450 dev_dbg(codec
->dev
, "JACKDET %x\n", reg
);
3452 present
= reg
& WM1811_JACKDET_LVL
;
3455 dev_dbg(codec
->dev
, "Jack detected\n");
3457 wm8958_micd_set_rate(codec
);
3459 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
3460 WM8958_MICB2_DISCH
, 0);
3462 /* Disable debounce while inserted */
3463 snd_soc_update_bits(codec
, WM1811_JACKDET_CTRL
,
3464 WM1811_JACKDET_DB
, 0);
3467 * Start off measument of microphone impedence to find
3468 * out what's actually there.
3470 wm8994
->mic_detecting
= true;
3471 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_MIC
);
3473 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3474 WM8958_MICD_ENA
, WM8958_MICD_ENA
);
3476 dev_dbg(codec
->dev
, "Jack not detected\n");
3478 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
3479 WM8958_MICB2_DISCH
, WM8958_MICB2_DISCH
);
3481 /* Enable debounce while removed */
3482 snd_soc_update_bits(codec
, WM1811_JACKDET_CTRL
,
3483 WM1811_JACKDET_DB
, WM1811_JACKDET_DB
);
3485 wm8994
->mic_detecting
= false;
3486 wm8994
->jack_mic
= false;
3487 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3488 WM8958_MICD_ENA
, 0);
3489 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_JACK
);
3492 mutex_unlock(&wm8994
->accdet_lock
);
3494 /* If required for an external cap force MICBIAS on */
3495 if (wm8994
->pdata
->jd_ext_cap
) {
3497 snd_soc_dapm_force_enable_pin(&codec
->dapm
,
3500 snd_soc_dapm_disable_pin(&codec
->dapm
, "MICBIAS2");
3504 snd_soc_jack_report(wm8994
->micdet
[0].jack
,
3505 SND_JACK_MECHANICAL
, SND_JACK_MECHANICAL
);
3507 snd_soc_jack_report(wm8994
->micdet
[0].jack
, 0,
3508 SND_JACK_MECHANICAL
| SND_JACK_HEADSET
|
3511 pm_runtime_put(codec
->dev
);
3516 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3518 * @codec: WM8958 codec
3519 * @jack: jack to report detection events on
3521 * Enable microphone detection functionality for the WM8958. By
3522 * default simple detection which supports the detection of up to 6
3523 * buttons plus video and microphone functionality is supported.
3525 * The WM8958 has an advanced jack detection facility which is able to
3526 * support complex accessory detection, especially when used in
3527 * conjunction with external circuitry. In order to provide maximum
3528 * flexiblity a callback is provided which allows a completely custom
3529 * detection algorithm.
3531 int wm8958_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
3532 wm8958_micdet_cb cb
, void *cb_data
)
3534 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3535 struct wm8994
*control
= wm8994
->wm8994
;
3538 switch (control
->type
) {
3548 dev_dbg(codec
->dev
, "Using default micdet callback\n");
3549 cb
= wm8958_default_micdet
;
3553 snd_soc_dapm_force_enable_pin(&codec
->dapm
, "CLK_SYS");
3554 snd_soc_dapm_sync(&codec
->dapm
);
3556 wm8994
->micdet
[0].jack
= jack
;
3557 wm8994
->jack_cb
= cb
;
3558 wm8994
->jack_cb_data
= cb_data
;
3560 wm8994
->mic_detecting
= true;
3561 wm8994
->jack_mic
= false;
3563 wm8958_micd_set_rate(codec
);
3565 /* Detect microphones and short circuits by default */
3566 if (wm8994
->pdata
->micd_lvl_sel
)
3567 micd_lvl_sel
= wm8994
->pdata
->micd_lvl_sel
;
3569 micd_lvl_sel
= 0x41;
3571 wm8994
->btn_mask
= SND_JACK_BTN_0
| SND_JACK_BTN_1
|
3572 SND_JACK_BTN_2
| SND_JACK_BTN_3
|
3573 SND_JACK_BTN_4
| SND_JACK_BTN_5
;
3575 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_2
,
3576 WM8958_MICD_LVL_SEL_MASK
, micd_lvl_sel
);
3578 WARN_ON(codec
->dapm
.bias_level
> SND_SOC_BIAS_STANDBY
);
3581 * If we can use jack detection start off with that,
3582 * otherwise jump straight to microphone detection.
3584 if (wm8994
->jackdet
) {
3585 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
3587 WM8958_MICB2_DISCH
);
3588 snd_soc_update_bits(codec
, WM8994_LDO_1
,
3589 WM8994_LDO1_DISCH
, 0);
3590 wm1811_jackdet_set_mode(codec
,
3591 WM1811_JACKDET_MODE_JACK
);
3593 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3594 WM8958_MICD_ENA
, WM8958_MICD_ENA
);
3598 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3599 WM8958_MICD_ENA
, 0);
3600 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_NONE
);
3601 snd_soc_dapm_disable_pin(&codec
->dapm
, "CLK_SYS");
3602 snd_soc_dapm_sync(&codec
->dapm
);
3607 EXPORT_SYMBOL_GPL(wm8958_mic_detect
);
3609 static irqreturn_t
wm8958_mic_irq(int irq
, void *data
)
3611 struct wm8994_priv
*wm8994
= data
;
3612 struct snd_soc_codec
*codec
= wm8994
->hubs
.codec
;
3616 * Jack detection may have detected a removal simulataneously
3617 * with an update of the MICDET status; if so it will have
3618 * stopped detection and we can ignore this interrupt.
3620 if (!(snd_soc_read(codec
, WM8958_MIC_DETECT_1
) & WM8958_MICD_ENA
))
3623 pm_runtime_get_sync(codec
->dev
);
3625 /* We may occasionally read a detection without an impedence
3626 * range being provided - if that happens loop again.
3630 reg
= snd_soc_read(codec
, WM8958_MIC_DETECT_3
);
3633 "Failed to read mic detect status: %d\n",
3635 pm_runtime_put(codec
->dev
);
3639 if (!(reg
& WM8958_MICD_VALID
)) {
3640 dev_dbg(codec
->dev
, "Mic detect data not valid\n");
3644 if (!(reg
& WM8958_MICD_STS
) || (reg
& WM8958_MICD_LVL_MASK
))
3651 dev_warn(codec
->dev
, "No impedence range reported for jack\n");
3653 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3654 trace_snd_soc_jack_irq(dev_name(codec
->dev
));
3657 if (wm8994
->jack_cb
)
3658 wm8994
->jack_cb(reg
, wm8994
->jack_cb_data
);
3660 dev_warn(codec
->dev
, "Accessory detection with no callback\n");
3663 pm_runtime_put(codec
->dev
);
3667 static irqreturn_t
wm8994_fifo_error(int irq
, void *data
)
3669 struct snd_soc_codec
*codec
= data
;
3671 dev_err(codec
->dev
, "FIFO error\n");
3676 static irqreturn_t
wm8994_temp_warn(int irq
, void *data
)
3678 struct snd_soc_codec
*codec
= data
;
3680 dev_err(codec
->dev
, "Thermal warning\n");
3685 static irqreturn_t
wm8994_temp_shut(int irq
, void *data
)
3687 struct snd_soc_codec
*codec
= data
;
3689 dev_crit(codec
->dev
, "Thermal shutdown\n");
3694 static int wm8994_codec_probe(struct snd_soc_codec
*codec
)
3696 struct wm8994
*control
= dev_get_drvdata(codec
->dev
->parent
);
3697 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3698 struct snd_soc_dapm_context
*dapm
= &codec
->dapm
;
3702 wm8994
->hubs
.codec
= codec
;
3703 codec
->control_data
= control
->regmap
;
3705 snd_soc_codec_set_cache_io(codec
, 16, 16, SND_SOC_REGMAP
);
3707 mutex_init(&wm8994
->accdet_lock
);
3708 INIT_DELAYED_WORK(&wm8994
->mic_work
, wm8994_mic_work
);
3710 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++)
3711 init_completion(&wm8994
->fll_locked
[i
]);
3713 if (wm8994
->pdata
&& wm8994
->pdata
->micdet_irq
)
3714 wm8994
->micdet_irq
= wm8994
->pdata
->micdet_irq
;
3716 pm_runtime_enable(codec
->dev
);
3717 pm_runtime_idle(codec
->dev
);
3719 /* By default use idle_bias_off, will override for WM8994 */
3720 codec
->dapm
.idle_bias_off
= 1;
3722 /* Set revision-specific configuration */
3723 wm8994
->revision
= snd_soc_read(codec
, WM8994_CHIP_REVISION
);
3724 switch (control
->type
) {
3726 /* Single ended line outputs should have VMID on. */
3727 if (!wm8994
->pdata
->lineout1_diff
||
3728 !wm8994
->pdata
->lineout2_diff
)
3729 codec
->dapm
.idle_bias_off
= 0;
3731 switch (wm8994
->revision
) {
3734 wm8994
->hubs
.dcs_codes_l
= -5;
3735 wm8994
->hubs
.dcs_codes_r
= -5;
3736 wm8994
->hubs
.hp_startup_mode
= 1;
3737 wm8994
->hubs
.dcs_readback_mode
= 1;
3738 wm8994
->hubs
.series_startup
= 1;
3741 wm8994
->hubs
.dcs_readback_mode
= 2;
3747 wm8994
->hubs
.dcs_readback_mode
= 1;
3748 wm8994
->hubs
.hp_startup_mode
= 1;
3750 switch (wm8994
->revision
) {
3754 wm8994
->fll_byp
= true;
3760 wm8994
->hubs
.dcs_readback_mode
= 2;
3761 wm8994
->hubs
.no_series_update
= 1;
3762 wm8994
->hubs
.hp_startup_mode
= 1;
3763 wm8994
->hubs
.no_cache_dac_hp_direct
= true;
3764 wm8994
->fll_byp
= true;
3766 switch (wm8994
->revision
) {
3771 wm8994
->hubs
.dcs_codes_l
= -9;
3772 wm8994
->hubs
.dcs_codes_r
= -7;
3778 snd_soc_update_bits(codec
, WM8994_ANALOGUE_HP_1
,
3779 WM1811_HPOUT1_ATTN
, WM1811_HPOUT1_ATTN
);
3786 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_FIFOS_ERR
,
3787 wm8994_fifo_error
, "FIFO error", codec
);
3788 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_WARN
,
3789 wm8994_temp_warn
, "Thermal warning", codec
);
3790 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_SHUT
,
3791 wm8994_temp_shut
, "Thermal shutdown", codec
);
3793 ret
= wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_DCS_DONE
,
3794 wm_hubs_dcs_done
, "DC servo done",
3797 wm8994
->hubs
.dcs_done_irq
= true;
3799 switch (control
->type
) {
3801 if (wm8994
->micdet_irq
) {
3802 ret
= request_threaded_irq(wm8994
->micdet_irq
, NULL
,
3804 IRQF_TRIGGER_RISING
,
3808 dev_warn(codec
->dev
,
3809 "Failed to request Mic1 detect IRQ: %d\n",
3813 ret
= wm8994_request_irq(wm8994
->wm8994
,
3814 WM8994_IRQ_MIC1_SHRT
,
3815 wm8994_mic_irq
, "Mic 1 short",
3818 dev_warn(codec
->dev
,
3819 "Failed to request Mic1 short IRQ: %d\n",
3822 ret
= wm8994_request_irq(wm8994
->wm8994
,
3823 WM8994_IRQ_MIC2_DET
,
3824 wm8994_mic_irq
, "Mic 2 detect",
3827 dev_warn(codec
->dev
,
3828 "Failed to request Mic2 detect IRQ: %d\n",
3831 ret
= wm8994_request_irq(wm8994
->wm8994
,
3832 WM8994_IRQ_MIC2_SHRT
,
3833 wm8994_mic_irq
, "Mic 2 short",
3836 dev_warn(codec
->dev
,
3837 "Failed to request Mic2 short IRQ: %d\n",
3843 if (wm8994
->micdet_irq
) {
3844 ret
= request_threaded_irq(wm8994
->micdet_irq
, NULL
,
3846 IRQF_TRIGGER_RISING
,
3850 dev_warn(codec
->dev
,
3851 "Failed to request Mic detect IRQ: %d\n",
3854 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_DET
,
3855 wm8958_mic_irq
, "Mic detect",
3860 switch (control
->type
) {
3862 if (wm8994
->revision
> 1) {
3863 ret
= wm8994_request_irq(wm8994
->wm8994
,
3865 wm1811_jackdet_irq
, "JACKDET",
3868 wm8994
->jackdet
= true;
3875 wm8994
->fll_locked_irq
= true;
3876 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++) {
3877 ret
= wm8994_request_irq(wm8994
->wm8994
,
3878 WM8994_IRQ_FLL1_LOCK
+ i
,
3879 wm8994_fll_locked_irq
, "FLL lock",
3880 &wm8994
->fll_locked
[i
]);
3882 wm8994
->fll_locked_irq
= false;
3885 /* Make sure we can read from the GPIOs if they're inputs */
3886 pm_runtime_get_sync(codec
->dev
);
3888 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3889 * configured on init - if a system wants to do this dynamically
3890 * at runtime we can deal with that then.
3892 ret
= regmap_read(control
->regmap
, WM8994_GPIO_1
, ®
);
3894 dev_err(codec
->dev
, "Failed to read GPIO1 state: %d\n", ret
);
3897 if ((reg
& WM8994_GPN_FN_MASK
) != WM8994_GP_FN_PIN_SPECIFIC
) {
3898 wm8994
->lrclk_shared
[0] = 1;
3899 wm8994_dai
[0].symmetric_rates
= 1;
3901 wm8994
->lrclk_shared
[0] = 0;
3904 ret
= regmap_read(control
->regmap
, WM8994_GPIO_6
, ®
);
3906 dev_err(codec
->dev
, "Failed to read GPIO6 state: %d\n", ret
);
3909 if ((reg
& WM8994_GPN_FN_MASK
) != WM8994_GP_FN_PIN_SPECIFIC
) {
3910 wm8994
->lrclk_shared
[1] = 1;
3911 wm8994_dai
[1].symmetric_rates
= 1;
3913 wm8994
->lrclk_shared
[1] = 0;
3916 pm_runtime_put(codec
->dev
);
3918 /* Latch volume update bits */
3919 for (i
= 0; i
< ARRAY_SIZE(wm8994_vu_bits
); i
++)
3920 snd_soc_update_bits(codec
, wm8994_vu_bits
[i
].reg
,
3921 wm8994_vu_bits
[i
].mask
,
3922 wm8994_vu_bits
[i
].mask
);
3924 /* Set the low bit of the 3D stereo depth so TLV matches */
3925 snd_soc_update_bits(codec
, WM8994_AIF1_DAC1_FILTERS_2
,
3926 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT
,
3927 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT
);
3928 snd_soc_update_bits(codec
, WM8994_AIF1_DAC2_FILTERS_2
,
3929 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT
,
3930 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT
);
3931 snd_soc_update_bits(codec
, WM8994_AIF2_DAC_FILTERS_2
,
3932 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT
,
3933 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT
);
3935 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3936 * use this; it only affects behaviour on idle TDM clock
3938 switch (control
->type
) {
3941 snd_soc_update_bits(codec
, WM8994_AIF1_CONTROL_1
,
3942 WM8994_AIF1ADC_TDM
, WM8994_AIF1ADC_TDM
);
3948 /* Put MICBIAS into bypass mode by default on newer devices */
3949 switch (control
->type
) {
3952 snd_soc_update_bits(codec
, WM8958_MICBIAS1
,
3953 WM8958_MICB1_MODE
, WM8958_MICB1_MODE
);
3954 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
3955 WM8958_MICB2_MODE
, WM8958_MICB2_MODE
);
3961 wm8994
->hubs
.check_class_w_digital
= wm8994_check_class_w_digital
;
3962 wm_hubs_update_class_w(codec
);
3964 wm8994_handle_pdata(wm8994
);
3966 wm_hubs_add_analogue_controls(codec
);
3967 snd_soc_add_codec_controls(codec
, wm8994_snd_controls
,
3968 ARRAY_SIZE(wm8994_snd_controls
));
3969 snd_soc_dapm_new_controls(dapm
, wm8994_dapm_widgets
,
3970 ARRAY_SIZE(wm8994_dapm_widgets
));
3972 switch (control
->type
) {
3974 snd_soc_dapm_new_controls(dapm
, wm8994_specific_dapm_widgets
,
3975 ARRAY_SIZE(wm8994_specific_dapm_widgets
));
3976 if (wm8994
->revision
< 4) {
3977 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_revd_widgets
,
3978 ARRAY_SIZE(wm8994_lateclk_revd_widgets
));
3979 snd_soc_dapm_new_controls(dapm
, wm8994_adc_revd_widgets
,
3980 ARRAY_SIZE(wm8994_adc_revd_widgets
));
3981 snd_soc_dapm_new_controls(dapm
, wm8994_dac_revd_widgets
,
3982 ARRAY_SIZE(wm8994_dac_revd_widgets
));
3984 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_widgets
,
3985 ARRAY_SIZE(wm8994_lateclk_widgets
));
3986 snd_soc_dapm_new_controls(dapm
, wm8994_adc_widgets
,
3987 ARRAY_SIZE(wm8994_adc_widgets
));
3988 snd_soc_dapm_new_controls(dapm
, wm8994_dac_widgets
,
3989 ARRAY_SIZE(wm8994_dac_widgets
));
3993 snd_soc_add_codec_controls(codec
, wm8958_snd_controls
,
3994 ARRAY_SIZE(wm8958_snd_controls
));
3995 snd_soc_dapm_new_controls(dapm
, wm8958_dapm_widgets
,
3996 ARRAY_SIZE(wm8958_dapm_widgets
));
3997 if (wm8994
->revision
< 1) {
3998 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_revd_widgets
,
3999 ARRAY_SIZE(wm8994_lateclk_revd_widgets
));
4000 snd_soc_dapm_new_controls(dapm
, wm8994_adc_revd_widgets
,
4001 ARRAY_SIZE(wm8994_adc_revd_widgets
));
4002 snd_soc_dapm_new_controls(dapm
, wm8994_dac_revd_widgets
,
4003 ARRAY_SIZE(wm8994_dac_revd_widgets
));
4005 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_widgets
,
4006 ARRAY_SIZE(wm8994_lateclk_widgets
));
4007 snd_soc_dapm_new_controls(dapm
, wm8994_adc_widgets
,
4008 ARRAY_SIZE(wm8994_adc_widgets
));
4009 snd_soc_dapm_new_controls(dapm
, wm8994_dac_widgets
,
4010 ARRAY_SIZE(wm8994_dac_widgets
));
4015 snd_soc_add_codec_controls(codec
, wm8958_snd_controls
,
4016 ARRAY_SIZE(wm8958_snd_controls
));
4017 snd_soc_dapm_new_controls(dapm
, wm8958_dapm_widgets
,
4018 ARRAY_SIZE(wm8958_dapm_widgets
));
4019 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_widgets
,
4020 ARRAY_SIZE(wm8994_lateclk_widgets
));
4021 snd_soc_dapm_new_controls(dapm
, wm8994_adc_widgets
,
4022 ARRAY_SIZE(wm8994_adc_widgets
));
4023 snd_soc_dapm_new_controls(dapm
, wm8994_dac_widgets
,
4024 ARRAY_SIZE(wm8994_dac_widgets
));
4028 wm_hubs_add_analogue_routes(codec
, 0, 0);
4029 snd_soc_dapm_add_routes(dapm
, intercon
, ARRAY_SIZE(intercon
));
4031 switch (control
->type
) {
4033 snd_soc_dapm_add_routes(dapm
, wm8994_intercon
,
4034 ARRAY_SIZE(wm8994_intercon
));
4036 if (wm8994
->revision
< 4) {
4037 snd_soc_dapm_add_routes(dapm
, wm8994_revd_intercon
,
4038 ARRAY_SIZE(wm8994_revd_intercon
));
4039 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_revd_intercon
,
4040 ARRAY_SIZE(wm8994_lateclk_revd_intercon
));
4042 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_intercon
,
4043 ARRAY_SIZE(wm8994_lateclk_intercon
));
4047 if (wm8994
->revision
< 1) {
4048 snd_soc_dapm_add_routes(dapm
, wm8994_revd_intercon
,
4049 ARRAY_SIZE(wm8994_revd_intercon
));
4050 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_revd_intercon
,
4051 ARRAY_SIZE(wm8994_lateclk_revd_intercon
));
4053 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_intercon
,
4054 ARRAY_SIZE(wm8994_lateclk_intercon
));
4055 snd_soc_dapm_add_routes(dapm
, wm8958_intercon
,
4056 ARRAY_SIZE(wm8958_intercon
));
4059 wm8958_dsp2_init(codec
);
4062 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_intercon
,
4063 ARRAY_SIZE(wm8994_lateclk_intercon
));
4064 snd_soc_dapm_add_routes(dapm
, wm8958_intercon
,
4065 ARRAY_SIZE(wm8958_intercon
));
4072 if (wm8994
->jackdet
)
4073 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_GPIO(6), wm8994
);
4074 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC2_SHRT
, wm8994
);
4075 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC2_DET
, wm8994
);
4076 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_SHRT
, wm8994
);
4077 if (wm8994
->micdet_irq
)
4078 free_irq(wm8994
->micdet_irq
, wm8994
);
4079 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++)
4080 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FLL1_LOCK
+ i
,
4081 &wm8994
->fll_locked
[i
]);
4082 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_DCS_DONE
,
4084 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FIFOS_ERR
, codec
);
4085 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_SHUT
, codec
);
4086 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_WARN
, codec
);
4091 static int wm8994_codec_remove(struct snd_soc_codec
*codec
)
4093 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
4094 struct wm8994
*control
= wm8994
->wm8994
;
4097 wm8994_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
4099 pm_runtime_disable(codec
->dev
);
4101 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++)
4102 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FLL1_LOCK
+ i
,
4103 &wm8994
->fll_locked
[i
]);
4105 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_DCS_DONE
,
4107 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FIFOS_ERR
, codec
);
4108 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_SHUT
, codec
);
4109 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_WARN
, codec
);
4111 if (wm8994
->jackdet
)
4112 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_GPIO(6), wm8994
);
4114 switch (control
->type
) {
4116 if (wm8994
->micdet_irq
)
4117 free_irq(wm8994
->micdet_irq
, wm8994
);
4118 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC2_DET
,
4120 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_SHRT
,
4122 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_DET
,
4128 if (wm8994
->micdet_irq
)
4129 free_irq(wm8994
->micdet_irq
, wm8994
);
4132 release_firmware(wm8994
->mbc
);
4133 release_firmware(wm8994
->mbc_vss
);
4134 release_firmware(wm8994
->enh_eq
);
4135 kfree(wm8994
->retune_mobile_texts
);
4139 static struct snd_soc_codec_driver soc_codec_dev_wm8994
= {
4140 .probe
= wm8994_codec_probe
,
4141 .remove
= wm8994_codec_remove
,
4142 .suspend
= wm8994_codec_suspend
,
4143 .resume
= wm8994_codec_resume
,
4144 .set_bias_level
= wm8994_set_bias_level
,
4147 static int __devinit
wm8994_probe(struct platform_device
*pdev
)
4149 struct wm8994_priv
*wm8994
;
4151 wm8994
= devm_kzalloc(&pdev
->dev
, sizeof(struct wm8994_priv
),
4155 platform_set_drvdata(pdev
, wm8994
);
4157 wm8994
->wm8994
= dev_get_drvdata(pdev
->dev
.parent
);
4158 wm8994
->pdata
= dev_get_platdata(pdev
->dev
.parent
);
4160 return snd_soc_register_codec(&pdev
->dev
, &soc_codec_dev_wm8994
,
4161 wm8994_dai
, ARRAY_SIZE(wm8994_dai
));
4164 static int __devexit
wm8994_remove(struct platform_device
*pdev
)
4166 snd_soc_unregister_codec(&pdev
->dev
);
4170 #ifdef CONFIG_PM_SLEEP
4171 static int wm8994_suspend(struct device
*dev
)
4173 struct wm8994_priv
*wm8994
= dev_get_drvdata(dev
);
4175 /* Drop down to power saving mode when system is suspended */
4176 if (wm8994
->jackdet
&& !wm8994
->active_refcount
)
4177 regmap_update_bits(wm8994
->wm8994
->regmap
, WM8994_ANTIPOP_2
,
4178 WM1811_JACKDET_MODE_MASK
,
4179 wm8994
->jackdet_mode
);
4184 static int wm8994_resume(struct device
*dev
)
4186 struct wm8994_priv
*wm8994
= dev_get_drvdata(dev
);
4188 if (wm8994
->jackdet
&& wm8994
->jack_cb
)
4189 regmap_update_bits(wm8994
->wm8994
->regmap
, WM8994_ANTIPOP_2
,
4190 WM1811_JACKDET_MODE_MASK
,
4191 WM1811_JACKDET_MODE_AUDIO
);
4197 static const struct dev_pm_ops wm8994_pm_ops
= {
4198 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend
, wm8994_resume
)
4201 static struct platform_driver wm8994_codec_driver
= {
4203 .name
= "wm8994-codec",
4204 .owner
= THIS_MODULE
,
4205 .pm
= &wm8994_pm_ops
,
4207 .probe
= wm8994_probe
,
4208 .remove
= __devexit_p(wm8994_remove
),
4211 module_platform_driver(wm8994_codec_driver
);
4213 MODULE_DESCRIPTION("ASoC WM8994 driver");
4214 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4215 MODULE_LICENSE("GPL");
4216 MODULE_ALIAS("platform:wm8994-codec");