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ASoC: wm8962: Replace direct snd_soc_codec dapm field access
[deliverable/linux.git] / sound / soc / codecs / wm8994.c
1 /*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009-12 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/gcd.h>
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/slab.h>
25 #include <sound/core.h>
26 #include <sound/jack.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
32 #include <trace/events/asoc.h>
33
34 #include <linux/mfd/wm8994/core.h>
35 #include <linux/mfd/wm8994/registers.h>
36 #include <linux/mfd/wm8994/pdata.h>
37 #include <linux/mfd/wm8994/gpio.h>
38
39 #include "wm8994.h"
40 #include "wm_hubs.h"
41
42 #define WM1811_JACKDET_MODE_NONE 0x0000
43 #define WM1811_JACKDET_MODE_JACK 0x0100
44 #define WM1811_JACKDET_MODE_MIC 0x0080
45 #define WM1811_JACKDET_MODE_AUDIO 0x0180
46
47 #define WM8994_NUM_DRC 3
48 #define WM8994_NUM_EQ 3
49
50 static struct {
51 unsigned int reg;
52 unsigned int mask;
53 } wm8994_vu_bits[] = {
54 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
55 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
56 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
57 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
58 { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
59 { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
60 { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
61 { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
62 { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
63 { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
64
65 { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
66 { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
67 { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
68 { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
69 { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
70 { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
71 { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
72 { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
73 { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
74 { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
75 { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
76 { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
77 { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
78 { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
79 { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
80 { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
81 };
82
83 static int wm8994_drc_base[] = {
84 WM8994_AIF1_DRC1_1,
85 WM8994_AIF1_DRC2_1,
86 WM8994_AIF2_DRC_1,
87 };
88
89 static int wm8994_retune_mobile_base[] = {
90 WM8994_AIF1_DAC1_EQ_GAINS_1,
91 WM8994_AIF1_DAC2_EQ_GAINS_1,
92 WM8994_AIF2_EQ_GAINS_1,
93 };
94
95 static const struct wm8958_micd_rate micdet_rates[] = {
96 { 32768, true, 1, 4 },
97 { 32768, false, 1, 1 },
98 { 44100 * 256, true, 7, 10 },
99 { 44100 * 256, false, 7, 10 },
100 };
101
102 static const struct wm8958_micd_rate jackdet_rates[] = {
103 { 32768, true, 0, 1 },
104 { 32768, false, 0, 1 },
105 { 44100 * 256, true, 10, 10 },
106 { 44100 * 256, false, 7, 8 },
107 };
108
109 static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
110 {
111 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
112 struct wm8994 *control = wm8994->wm8994;
113 int best, i, sysclk, val;
114 bool idle;
115 const struct wm8958_micd_rate *rates;
116 int num_rates;
117
118 idle = !wm8994->jack_mic;
119
120 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
121 if (sysclk & WM8994_SYSCLK_SRC)
122 sysclk = wm8994->aifclk[1];
123 else
124 sysclk = wm8994->aifclk[0];
125
126 if (control->pdata.micd_rates) {
127 rates = control->pdata.micd_rates;
128 num_rates = control->pdata.num_micd_rates;
129 } else if (wm8994->jackdet) {
130 rates = jackdet_rates;
131 num_rates = ARRAY_SIZE(jackdet_rates);
132 } else {
133 rates = micdet_rates;
134 num_rates = ARRAY_SIZE(micdet_rates);
135 }
136
137 best = 0;
138 for (i = 0; i < num_rates; i++) {
139 if (rates[i].idle != idle)
140 continue;
141 if (abs(rates[i].sysclk - sysclk) <
142 abs(rates[best].sysclk - sysclk))
143 best = i;
144 else if (rates[best].idle != idle)
145 best = i;
146 }
147
148 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
149 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
150
151 dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n",
152 rates[best].start, rates[best].rate, sysclk,
153 idle ? "idle" : "active");
154
155 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
156 WM8958_MICD_BIAS_STARTTIME_MASK |
157 WM8958_MICD_RATE_MASK, val);
158 }
159
160 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
161 {
162 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
163 int rate;
164 int reg1 = 0;
165 int offset;
166
167 if (aif)
168 offset = 4;
169 else
170 offset = 0;
171
172 switch (wm8994->sysclk[aif]) {
173 case WM8994_SYSCLK_MCLK1:
174 rate = wm8994->mclk[0];
175 break;
176
177 case WM8994_SYSCLK_MCLK2:
178 reg1 |= 0x8;
179 rate = wm8994->mclk[1];
180 break;
181
182 case WM8994_SYSCLK_FLL1:
183 reg1 |= 0x10;
184 rate = wm8994->fll[0].out;
185 break;
186
187 case WM8994_SYSCLK_FLL2:
188 reg1 |= 0x18;
189 rate = wm8994->fll[1].out;
190 break;
191
192 default:
193 return -EINVAL;
194 }
195
196 if (rate >= 13500000) {
197 rate /= 2;
198 reg1 |= WM8994_AIF1CLK_DIV;
199
200 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
201 aif + 1, rate);
202 }
203
204 wm8994->aifclk[aif] = rate;
205
206 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
207 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
208 reg1);
209
210 return 0;
211 }
212
213 static int configure_clock(struct snd_soc_codec *codec)
214 {
215 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
216 int change, new;
217
218 /* Bring up the AIF clocks first */
219 configure_aif_clock(codec, 0);
220 configure_aif_clock(codec, 1);
221
222 /* Then switch CLK_SYS over to the higher of them; a change
223 * can only happen as a result of a clocking change which can
224 * only be made outside of DAPM so we can safely redo the
225 * clocking.
226 */
227
228 /* If they're equal it doesn't matter which is used */
229 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
230 wm8958_micd_set_rate(codec);
231 return 0;
232 }
233
234 if (wm8994->aifclk[0] < wm8994->aifclk[1])
235 new = WM8994_SYSCLK_SRC;
236 else
237 new = 0;
238
239 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
240 WM8994_SYSCLK_SRC, new);
241 if (change)
242 snd_soc_dapm_sync(&codec->dapm);
243
244 wm8958_micd_set_rate(codec);
245
246 return 0;
247 }
248
249 static int check_clk_sys(struct snd_soc_dapm_widget *source,
250 struct snd_soc_dapm_widget *sink)
251 {
252 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
253 int reg = snd_soc_read(codec, WM8994_CLOCKING_1);
254 const char *clk;
255
256 /* Check what we're currently using for CLK_SYS */
257 if (reg & WM8994_SYSCLK_SRC)
258 clk = "AIF2CLK";
259 else
260 clk = "AIF1CLK";
261
262 return strcmp(source->name, clk) == 0;
263 }
264
265 static const char *sidetone_hpf_text[] = {
266 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
267 };
268
269 static SOC_ENUM_SINGLE_DECL(sidetone_hpf,
270 WM8994_SIDETONE, 7, sidetone_hpf_text);
271
272 static const char *adc_hpf_text[] = {
273 "HiFi", "Voice 1", "Voice 2", "Voice 3"
274 };
275
276 static SOC_ENUM_SINGLE_DECL(aif1adc1_hpf,
277 WM8994_AIF1_ADC1_FILTERS, 13, adc_hpf_text);
278
279 static SOC_ENUM_SINGLE_DECL(aif1adc2_hpf,
280 WM8994_AIF1_ADC2_FILTERS, 13, adc_hpf_text);
281
282 static SOC_ENUM_SINGLE_DECL(aif2adc_hpf,
283 WM8994_AIF2_ADC_FILTERS, 13, adc_hpf_text);
284
285 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
286 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
287 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
288 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
289 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
290 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
291 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
292
293 #define WM8994_DRC_SWITCH(xname, reg, shift) \
294 SOC_SINGLE_EXT(xname, reg, shift, 1, 0, \
295 snd_soc_get_volsw, wm8994_put_drc_sw)
296
297 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
298 struct snd_ctl_elem_value *ucontrol)
299 {
300 struct soc_mixer_control *mc =
301 (struct soc_mixer_control *)kcontrol->private_value;
302 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
303 int mask, ret;
304
305 /* Can't enable both ADC and DAC paths simultaneously */
306 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
307 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
308 WM8994_AIF1ADC1R_DRC_ENA_MASK;
309 else
310 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
311
312 ret = snd_soc_read(codec, mc->reg);
313 if (ret < 0)
314 return ret;
315 if (ret & mask)
316 return -EINVAL;
317
318 return snd_soc_put_volsw(kcontrol, ucontrol);
319 }
320
321 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
322 {
323 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
324 struct wm8994 *control = wm8994->wm8994;
325 struct wm8994_pdata *pdata = &control->pdata;
326 int base = wm8994_drc_base[drc];
327 int cfg = wm8994->drc_cfg[drc];
328 int save, i;
329
330 /* Save any enables; the configuration should clear them. */
331 save = snd_soc_read(codec, base);
332 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
333 WM8994_AIF1ADC1R_DRC_ENA;
334
335 for (i = 0; i < WM8994_DRC_REGS; i++)
336 snd_soc_update_bits(codec, base + i, 0xffff,
337 pdata->drc_cfgs[cfg].regs[i]);
338
339 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
340 WM8994_AIF1ADC1L_DRC_ENA |
341 WM8994_AIF1ADC1R_DRC_ENA, save);
342 }
343
344 /* Icky as hell but saves code duplication */
345 static int wm8994_get_drc(const char *name)
346 {
347 if (strcmp(name, "AIF1DRC1 Mode") == 0)
348 return 0;
349 if (strcmp(name, "AIF1DRC2 Mode") == 0)
350 return 1;
351 if (strcmp(name, "AIF2DRC Mode") == 0)
352 return 2;
353 return -EINVAL;
354 }
355
356 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
357 struct snd_ctl_elem_value *ucontrol)
358 {
359 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
360 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
361 struct wm8994 *control = wm8994->wm8994;
362 struct wm8994_pdata *pdata = &control->pdata;
363 int drc = wm8994_get_drc(kcontrol->id.name);
364 int value = ucontrol->value.integer.value[0];
365
366 if (drc < 0)
367 return drc;
368
369 if (value >= pdata->num_drc_cfgs)
370 return -EINVAL;
371
372 wm8994->drc_cfg[drc] = value;
373
374 wm8994_set_drc(codec, drc);
375
376 return 0;
377 }
378
379 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
380 struct snd_ctl_elem_value *ucontrol)
381 {
382 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
383 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
384 int drc = wm8994_get_drc(kcontrol->id.name);
385
386 if (drc < 0)
387 return drc;
388 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
389
390 return 0;
391 }
392
393 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
394 {
395 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
396 struct wm8994 *control = wm8994->wm8994;
397 struct wm8994_pdata *pdata = &control->pdata;
398 int base = wm8994_retune_mobile_base[block];
399 int iface, best, best_val, save, i, cfg;
400
401 if (!pdata || !wm8994->num_retune_mobile_texts)
402 return;
403
404 switch (block) {
405 case 0:
406 case 1:
407 iface = 0;
408 break;
409 case 2:
410 iface = 1;
411 break;
412 default:
413 return;
414 }
415
416 /* Find the version of the currently selected configuration
417 * with the nearest sample rate. */
418 cfg = wm8994->retune_mobile_cfg[block];
419 best = 0;
420 best_val = INT_MAX;
421 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
422 if (strcmp(pdata->retune_mobile_cfgs[i].name,
423 wm8994->retune_mobile_texts[cfg]) == 0 &&
424 abs(pdata->retune_mobile_cfgs[i].rate
425 - wm8994->dac_rates[iface]) < best_val) {
426 best = i;
427 best_val = abs(pdata->retune_mobile_cfgs[i].rate
428 - wm8994->dac_rates[iface]);
429 }
430 }
431
432 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
433 block,
434 pdata->retune_mobile_cfgs[best].name,
435 pdata->retune_mobile_cfgs[best].rate,
436 wm8994->dac_rates[iface]);
437
438 /* The EQ will be disabled while reconfiguring it, remember the
439 * current configuration.
440 */
441 save = snd_soc_read(codec, base);
442 save &= WM8994_AIF1DAC1_EQ_ENA;
443
444 for (i = 0; i < WM8994_EQ_REGS; i++)
445 snd_soc_update_bits(codec, base + i, 0xffff,
446 pdata->retune_mobile_cfgs[best].regs[i]);
447
448 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
449 }
450
451 /* Icky as hell but saves code duplication */
452 static int wm8994_get_retune_mobile_block(const char *name)
453 {
454 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
455 return 0;
456 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
457 return 1;
458 if (strcmp(name, "AIF2 EQ Mode") == 0)
459 return 2;
460 return -EINVAL;
461 }
462
463 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
464 struct snd_ctl_elem_value *ucontrol)
465 {
466 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
467 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
468 struct wm8994 *control = wm8994->wm8994;
469 struct wm8994_pdata *pdata = &control->pdata;
470 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
471 int value = ucontrol->value.integer.value[0];
472
473 if (block < 0)
474 return block;
475
476 if (value >= pdata->num_retune_mobile_cfgs)
477 return -EINVAL;
478
479 wm8994->retune_mobile_cfg[block] = value;
480
481 wm8994_set_retune_mobile(codec, block);
482
483 return 0;
484 }
485
486 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
487 struct snd_ctl_elem_value *ucontrol)
488 {
489 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
490 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
491 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
492
493 if (block < 0)
494 return block;
495
496 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
497
498 return 0;
499 }
500
501 static const char *aif_chan_src_text[] = {
502 "Left", "Right"
503 };
504
505 static SOC_ENUM_SINGLE_DECL(aif1adcl_src,
506 WM8994_AIF1_CONTROL_1, 15, aif_chan_src_text);
507
508 static SOC_ENUM_SINGLE_DECL(aif1adcr_src,
509 WM8994_AIF1_CONTROL_1, 14, aif_chan_src_text);
510
511 static SOC_ENUM_SINGLE_DECL(aif2adcl_src,
512 WM8994_AIF2_CONTROL_1, 15, aif_chan_src_text);
513
514 static SOC_ENUM_SINGLE_DECL(aif2adcr_src,
515 WM8994_AIF2_CONTROL_1, 14, aif_chan_src_text);
516
517 static SOC_ENUM_SINGLE_DECL(aif1dacl_src,
518 WM8994_AIF1_CONTROL_2, 15, aif_chan_src_text);
519
520 static SOC_ENUM_SINGLE_DECL(aif1dacr_src,
521 WM8994_AIF1_CONTROL_2, 14, aif_chan_src_text);
522
523 static SOC_ENUM_SINGLE_DECL(aif2dacl_src,
524 WM8994_AIF2_CONTROL_2, 15, aif_chan_src_text);
525
526 static SOC_ENUM_SINGLE_DECL(aif2dacr_src,
527 WM8994_AIF2_CONTROL_2, 14, aif_chan_src_text);
528
529 static const char *osr_text[] = {
530 "Low Power", "High Performance",
531 };
532
533 static SOC_ENUM_SINGLE_DECL(dac_osr,
534 WM8994_OVERSAMPLING, 0, osr_text);
535
536 static SOC_ENUM_SINGLE_DECL(adc_osr,
537 WM8994_OVERSAMPLING, 1, osr_text);
538
539 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
540 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
541 WM8994_AIF1_ADC1_RIGHT_VOLUME,
542 1, 119, 0, digital_tlv),
543 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
544 WM8994_AIF1_ADC2_RIGHT_VOLUME,
545 1, 119, 0, digital_tlv),
546 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
547 WM8994_AIF2_ADC_RIGHT_VOLUME,
548 1, 119, 0, digital_tlv),
549
550 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
551 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
552 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
553 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
554
555 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
556 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
557 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
558 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
559
560 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
561 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
562 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
563 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
564 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
565 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
566
567 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
568 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
569
570 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
571 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
572 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
573
574 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
575 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
576 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
577
578 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
579 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
580 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
581
582 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
583 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
584 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
585
586 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
587 5, 12, 0, st_tlv),
588 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
589 0, 12, 0, st_tlv),
590 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
591 5, 12, 0, st_tlv),
592 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
593 0, 12, 0, st_tlv),
594 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
595 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
596
597 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
598 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
599
600 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
601 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
602
603 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
604 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
605
606 SOC_ENUM("ADC OSR", adc_osr),
607 SOC_ENUM("DAC OSR", dac_osr),
608
609 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
610 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
611 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
612 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
613
614 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
615 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
616 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
617 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
618
619 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
620 6, 1, 1, wm_hubs_spkmix_tlv),
621 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
622 2, 1, 1, wm_hubs_spkmix_tlv),
623
624 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
625 6, 1, 1, wm_hubs_spkmix_tlv),
626 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
627 2, 1, 1, wm_hubs_spkmix_tlv),
628
629 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
630 10, 15, 0, wm8994_3d_tlv),
631 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
632 8, 1, 0),
633 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
634 10, 15, 0, wm8994_3d_tlv),
635 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
636 8, 1, 0),
637 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
638 10, 15, 0, wm8994_3d_tlv),
639 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
640 8, 1, 0),
641 };
642
643 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
644 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
645 eq_tlv),
646 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
647 eq_tlv),
648 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
649 eq_tlv),
650 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
651 eq_tlv),
652 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
653 eq_tlv),
654
655 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
656 eq_tlv),
657 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
658 eq_tlv),
659 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
660 eq_tlv),
661 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
662 eq_tlv),
663 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
664 eq_tlv),
665
666 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
667 eq_tlv),
668 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
669 eq_tlv),
670 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
671 eq_tlv),
672 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
673 eq_tlv),
674 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
675 eq_tlv),
676 };
677
678 static const struct snd_kcontrol_new wm8994_drc_controls[] = {
679 SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5,
680 WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
681 WM8994_AIF1ADC1R_DRC_ENA),
682 SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5,
683 WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA |
684 WM8994_AIF1ADC2R_DRC_ENA),
685 SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5,
686 WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA |
687 WM8994_AIF2ADCR_DRC_ENA),
688 };
689
690 static const char *wm8958_ng_text[] = {
691 "30ms", "125ms", "250ms", "500ms",
692 };
693
694 static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac1_ng_hold,
695 WM8958_AIF1_DAC1_NOISE_GATE,
696 WM8958_AIF1DAC1_NG_THR_SHIFT,
697 wm8958_ng_text);
698
699 static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac2_ng_hold,
700 WM8958_AIF1_DAC2_NOISE_GATE,
701 WM8958_AIF1DAC2_NG_THR_SHIFT,
702 wm8958_ng_text);
703
704 static SOC_ENUM_SINGLE_DECL(wm8958_aif2dac_ng_hold,
705 WM8958_AIF2_DAC_NOISE_GATE,
706 WM8958_AIF2DAC_NG_THR_SHIFT,
707 wm8958_ng_text);
708
709 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
710 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
711
712 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
713 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
714 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
715 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
716 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
717 7, 1, ng_tlv),
718
719 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
720 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
721 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
722 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
723 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
724 7, 1, ng_tlv),
725
726 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
727 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
728 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
729 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
730 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
731 7, 1, ng_tlv),
732 };
733
734 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
735 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
736 mixin_boost_tlv),
737 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
738 mixin_boost_tlv),
739 };
740
741 /* We run all mode setting through a function to enforce audio mode */
742 static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
743 {
744 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
745
746 if (!wm8994->jackdet || !wm8994->micdet[0].jack)
747 return;
748
749 if (wm8994->active_refcount)
750 mode = WM1811_JACKDET_MODE_AUDIO;
751
752 if (mode == wm8994->jackdet_mode)
753 return;
754
755 wm8994->jackdet_mode = mode;
756
757 /* Always use audio mode to detect while the system is active */
758 if (mode != WM1811_JACKDET_MODE_NONE)
759 mode = WM1811_JACKDET_MODE_AUDIO;
760
761 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
762 WM1811_JACKDET_MODE_MASK, mode);
763 }
764
765 static void active_reference(struct snd_soc_codec *codec)
766 {
767 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
768
769 mutex_lock(&wm8994->accdet_lock);
770
771 wm8994->active_refcount++;
772
773 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
774 wm8994->active_refcount);
775
776 /* If we're using jack detection go into audio mode */
777 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
778
779 mutex_unlock(&wm8994->accdet_lock);
780 }
781
782 static void active_dereference(struct snd_soc_codec *codec)
783 {
784 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
785 u16 mode;
786
787 mutex_lock(&wm8994->accdet_lock);
788
789 wm8994->active_refcount--;
790
791 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
792 wm8994->active_refcount);
793
794 if (wm8994->active_refcount == 0) {
795 /* Go into appropriate detection only mode */
796 if (wm8994->jack_mic || wm8994->mic_detecting)
797 mode = WM1811_JACKDET_MODE_MIC;
798 else
799 mode = WM1811_JACKDET_MODE_JACK;
800
801 wm1811_jackdet_set_mode(codec, mode);
802 }
803
804 mutex_unlock(&wm8994->accdet_lock);
805 }
806
807 static int clk_sys_event(struct snd_soc_dapm_widget *w,
808 struct snd_kcontrol *kcontrol, int event)
809 {
810 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
811 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
812
813 switch (event) {
814 case SND_SOC_DAPM_PRE_PMU:
815 return configure_clock(codec);
816
817 case SND_SOC_DAPM_POST_PMU:
818 /*
819 * JACKDET won't run until we start the clock and it
820 * only reports deltas, make sure we notify the state
821 * up the stack on startup. Use a *very* generous
822 * timeout for paranoia, there's no urgency and we
823 * don't want false reports.
824 */
825 if (wm8994->jackdet && !wm8994->clk_has_run) {
826 queue_delayed_work(system_power_efficient_wq,
827 &wm8994->jackdet_bootstrap,
828 msecs_to_jiffies(1000));
829 wm8994->clk_has_run = true;
830 }
831 break;
832
833 case SND_SOC_DAPM_POST_PMD:
834 configure_clock(codec);
835 break;
836 }
837
838 return 0;
839 }
840
841 static void vmid_reference(struct snd_soc_codec *codec)
842 {
843 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
844
845 pm_runtime_get_sync(codec->dev);
846
847 wm8994->vmid_refcount++;
848
849 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
850 wm8994->vmid_refcount);
851
852 if (wm8994->vmid_refcount == 1) {
853 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
854 WM8994_LINEOUT1_DISCH |
855 WM8994_LINEOUT2_DISCH, 0);
856
857 wm_hubs_vmid_ena(codec);
858
859 switch (wm8994->vmid_mode) {
860 default:
861 WARN_ON(NULL == "Invalid VMID mode");
862 case WM8994_VMID_NORMAL:
863 /* Startup bias, VMID ramp & buffer */
864 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
865 WM8994_BIAS_SRC |
866 WM8994_VMID_DISCH |
867 WM8994_STARTUP_BIAS_ENA |
868 WM8994_VMID_BUF_ENA |
869 WM8994_VMID_RAMP_MASK,
870 WM8994_BIAS_SRC |
871 WM8994_STARTUP_BIAS_ENA |
872 WM8994_VMID_BUF_ENA |
873 (0x2 << WM8994_VMID_RAMP_SHIFT));
874
875 /* Main bias enable, VMID=2x40k */
876 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
877 WM8994_BIAS_ENA |
878 WM8994_VMID_SEL_MASK,
879 WM8994_BIAS_ENA | 0x2);
880
881 msleep(300);
882
883 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
884 WM8994_VMID_RAMP_MASK |
885 WM8994_BIAS_SRC,
886 0);
887 break;
888
889 case WM8994_VMID_FORCE:
890 /* Startup bias, slow VMID ramp & buffer */
891 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
892 WM8994_BIAS_SRC |
893 WM8994_VMID_DISCH |
894 WM8994_STARTUP_BIAS_ENA |
895 WM8994_VMID_BUF_ENA |
896 WM8994_VMID_RAMP_MASK,
897 WM8994_BIAS_SRC |
898 WM8994_STARTUP_BIAS_ENA |
899 WM8994_VMID_BUF_ENA |
900 (0x2 << WM8994_VMID_RAMP_SHIFT));
901
902 /* Main bias enable, VMID=2x40k */
903 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
904 WM8994_BIAS_ENA |
905 WM8994_VMID_SEL_MASK,
906 WM8994_BIAS_ENA | 0x2);
907
908 msleep(400);
909
910 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
911 WM8994_VMID_RAMP_MASK |
912 WM8994_BIAS_SRC,
913 0);
914 break;
915 }
916 }
917 }
918
919 static void vmid_dereference(struct snd_soc_codec *codec)
920 {
921 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
922
923 wm8994->vmid_refcount--;
924
925 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
926 wm8994->vmid_refcount);
927
928 if (wm8994->vmid_refcount == 0) {
929 if (wm8994->hubs.lineout1_se)
930 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
931 WM8994_LINEOUT1N_ENA |
932 WM8994_LINEOUT1P_ENA,
933 WM8994_LINEOUT1N_ENA |
934 WM8994_LINEOUT1P_ENA);
935
936 if (wm8994->hubs.lineout2_se)
937 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
938 WM8994_LINEOUT2N_ENA |
939 WM8994_LINEOUT2P_ENA,
940 WM8994_LINEOUT2N_ENA |
941 WM8994_LINEOUT2P_ENA);
942
943 /* Start discharging VMID */
944 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
945 WM8994_BIAS_SRC |
946 WM8994_VMID_DISCH,
947 WM8994_BIAS_SRC |
948 WM8994_VMID_DISCH);
949
950 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
951 WM8994_VMID_SEL_MASK, 0);
952
953 msleep(400);
954
955 /* Active discharge */
956 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
957 WM8994_LINEOUT1_DISCH |
958 WM8994_LINEOUT2_DISCH,
959 WM8994_LINEOUT1_DISCH |
960 WM8994_LINEOUT2_DISCH);
961
962 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
963 WM8994_LINEOUT1N_ENA |
964 WM8994_LINEOUT1P_ENA |
965 WM8994_LINEOUT2N_ENA |
966 WM8994_LINEOUT2P_ENA, 0);
967
968 /* Switch off startup biases */
969 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
970 WM8994_BIAS_SRC |
971 WM8994_STARTUP_BIAS_ENA |
972 WM8994_VMID_BUF_ENA |
973 WM8994_VMID_RAMP_MASK, 0);
974
975 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
976 WM8994_VMID_SEL_MASK, 0);
977 }
978
979 pm_runtime_put(codec->dev);
980 }
981
982 static int vmid_event(struct snd_soc_dapm_widget *w,
983 struct snd_kcontrol *kcontrol, int event)
984 {
985 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
986
987 switch (event) {
988 case SND_SOC_DAPM_PRE_PMU:
989 vmid_reference(codec);
990 break;
991
992 case SND_SOC_DAPM_POST_PMD:
993 vmid_dereference(codec);
994 break;
995 }
996
997 return 0;
998 }
999
1000 static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec)
1001 {
1002 int source = 0; /* GCC flow analysis can't track enable */
1003 int reg, reg_r;
1004
1005 /* We also need the same AIF source for L/R and only one path */
1006 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
1007 switch (reg) {
1008 case WM8994_AIF2DACL_TO_DAC1L:
1009 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
1010 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1011 break;
1012 case WM8994_AIF1DAC2L_TO_DAC1L:
1013 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
1014 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1015 break;
1016 case WM8994_AIF1DAC1L_TO_DAC1L:
1017 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
1018 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1019 break;
1020 default:
1021 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
1022 return false;
1023 }
1024
1025 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1026 if (reg_r != reg) {
1027 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
1028 return false;
1029 }
1030
1031 /* Set the source up */
1032 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1033 WM8994_CP_DYN_SRC_SEL_MASK, source);
1034
1035 return true;
1036 }
1037
1038 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1039 struct snd_kcontrol *kcontrol, int event)
1040 {
1041 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1042 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1043 struct wm8994 *control = wm8994->wm8994;
1044 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
1045 int i;
1046 int dac;
1047 int adc;
1048 int val;
1049
1050 switch (control->type) {
1051 case WM8994:
1052 case WM8958:
1053 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1054 break;
1055 default:
1056 break;
1057 }
1058
1059 switch (event) {
1060 case SND_SOC_DAPM_PRE_PMU:
1061 /* Don't enable timeslot 2 if not in use */
1062 if (wm8994->channels[0] <= 2)
1063 mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
1064
1065 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
1066 if ((val & WM8994_AIF1ADCL_SRC) &&
1067 (val & WM8994_AIF1ADCR_SRC))
1068 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1069 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1070 !(val & WM8994_AIF1ADCR_SRC))
1071 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1072 else
1073 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1074 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1075
1076 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
1077 if ((val & WM8994_AIF1DACL_SRC) &&
1078 (val & WM8994_AIF1DACR_SRC))
1079 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1080 else if (!(val & WM8994_AIF1DACL_SRC) &&
1081 !(val & WM8994_AIF1DACR_SRC))
1082 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1083 else
1084 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1085 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1086
1087 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1088 mask, adc);
1089 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1090 mask, dac);
1091 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1092 WM8994_AIF1DSPCLK_ENA |
1093 WM8994_SYSDSPCLK_ENA,
1094 WM8994_AIF1DSPCLK_ENA |
1095 WM8994_SYSDSPCLK_ENA);
1096 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
1097 WM8994_AIF1ADC1R_ENA |
1098 WM8994_AIF1ADC1L_ENA |
1099 WM8994_AIF1ADC2R_ENA |
1100 WM8994_AIF1ADC2L_ENA);
1101 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
1102 WM8994_AIF1DAC1R_ENA |
1103 WM8994_AIF1DAC1L_ENA |
1104 WM8994_AIF1DAC2R_ENA |
1105 WM8994_AIF1DAC2L_ENA);
1106 break;
1107
1108 case SND_SOC_DAPM_POST_PMU:
1109 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1110 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1111 snd_soc_read(codec,
1112 wm8994_vu_bits[i].reg));
1113 break;
1114
1115 case SND_SOC_DAPM_PRE_PMD:
1116 case SND_SOC_DAPM_POST_PMD:
1117 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1118 mask, 0);
1119 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1120 mask, 0);
1121
1122 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1123 if (val & WM8994_AIF2DSPCLK_ENA)
1124 val = WM8994_SYSDSPCLK_ENA;
1125 else
1126 val = 0;
1127 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1128 WM8994_SYSDSPCLK_ENA |
1129 WM8994_AIF1DSPCLK_ENA, val);
1130 break;
1131 }
1132
1133 return 0;
1134 }
1135
1136 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1137 struct snd_kcontrol *kcontrol, int event)
1138 {
1139 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1140 int i;
1141 int dac;
1142 int adc;
1143 int val;
1144
1145 switch (event) {
1146 case SND_SOC_DAPM_PRE_PMU:
1147 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1148 if ((val & WM8994_AIF2ADCL_SRC) &&
1149 (val & WM8994_AIF2ADCR_SRC))
1150 adc = WM8994_AIF2ADCR_ENA;
1151 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1152 !(val & WM8994_AIF2ADCR_SRC))
1153 adc = WM8994_AIF2ADCL_ENA;
1154 else
1155 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1156
1157
1158 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1159 if ((val & WM8994_AIF2DACL_SRC) &&
1160 (val & WM8994_AIF2DACR_SRC))
1161 dac = WM8994_AIF2DACR_ENA;
1162 else if (!(val & WM8994_AIF2DACL_SRC) &&
1163 !(val & WM8994_AIF2DACR_SRC))
1164 dac = WM8994_AIF2DACL_ENA;
1165 else
1166 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1167
1168 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1169 WM8994_AIF2ADCL_ENA |
1170 WM8994_AIF2ADCR_ENA, adc);
1171 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1172 WM8994_AIF2DACL_ENA |
1173 WM8994_AIF2DACR_ENA, dac);
1174 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1175 WM8994_AIF2DSPCLK_ENA |
1176 WM8994_SYSDSPCLK_ENA,
1177 WM8994_AIF2DSPCLK_ENA |
1178 WM8994_SYSDSPCLK_ENA);
1179 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1180 WM8994_AIF2ADCL_ENA |
1181 WM8994_AIF2ADCR_ENA,
1182 WM8994_AIF2ADCL_ENA |
1183 WM8994_AIF2ADCR_ENA);
1184 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1185 WM8994_AIF2DACL_ENA |
1186 WM8994_AIF2DACR_ENA,
1187 WM8994_AIF2DACL_ENA |
1188 WM8994_AIF2DACR_ENA);
1189 break;
1190
1191 case SND_SOC_DAPM_POST_PMU:
1192 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1193 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1194 snd_soc_read(codec,
1195 wm8994_vu_bits[i].reg));
1196 break;
1197
1198 case SND_SOC_DAPM_PRE_PMD:
1199 case SND_SOC_DAPM_POST_PMD:
1200 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1201 WM8994_AIF2DACL_ENA |
1202 WM8994_AIF2DACR_ENA, 0);
1203 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1204 WM8994_AIF2ADCL_ENA |
1205 WM8994_AIF2ADCR_ENA, 0);
1206
1207 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1208 if (val & WM8994_AIF1DSPCLK_ENA)
1209 val = WM8994_SYSDSPCLK_ENA;
1210 else
1211 val = 0;
1212 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1213 WM8994_SYSDSPCLK_ENA |
1214 WM8994_AIF2DSPCLK_ENA, val);
1215 break;
1216 }
1217
1218 return 0;
1219 }
1220
1221 static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1222 struct snd_kcontrol *kcontrol, int event)
1223 {
1224 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1225 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1226
1227 switch (event) {
1228 case SND_SOC_DAPM_PRE_PMU:
1229 wm8994->aif1clk_enable = 1;
1230 break;
1231 case SND_SOC_DAPM_POST_PMD:
1232 wm8994->aif1clk_disable = 1;
1233 break;
1234 }
1235
1236 return 0;
1237 }
1238
1239 static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1240 struct snd_kcontrol *kcontrol, int event)
1241 {
1242 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1243 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1244
1245 switch (event) {
1246 case SND_SOC_DAPM_PRE_PMU:
1247 wm8994->aif2clk_enable = 1;
1248 break;
1249 case SND_SOC_DAPM_POST_PMD:
1250 wm8994->aif2clk_disable = 1;
1251 break;
1252 }
1253
1254 return 0;
1255 }
1256
1257 static int late_enable_ev(struct snd_soc_dapm_widget *w,
1258 struct snd_kcontrol *kcontrol, int event)
1259 {
1260 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1261 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1262
1263 switch (event) {
1264 case SND_SOC_DAPM_PRE_PMU:
1265 if (wm8994->aif1clk_enable) {
1266 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1267 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1268 WM8994_AIF1CLK_ENA_MASK,
1269 WM8994_AIF1CLK_ENA);
1270 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1271 wm8994->aif1clk_enable = 0;
1272 }
1273 if (wm8994->aif2clk_enable) {
1274 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1275 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1276 WM8994_AIF2CLK_ENA_MASK,
1277 WM8994_AIF2CLK_ENA);
1278 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1279 wm8994->aif2clk_enable = 0;
1280 }
1281 break;
1282 }
1283
1284 /* We may also have postponed startup of DSP, handle that. */
1285 wm8958_aif_ev(w, kcontrol, event);
1286
1287 return 0;
1288 }
1289
1290 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1291 struct snd_kcontrol *kcontrol, int event)
1292 {
1293 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1294 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1295
1296 switch (event) {
1297 case SND_SOC_DAPM_POST_PMD:
1298 if (wm8994->aif1clk_disable) {
1299 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1300 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1301 WM8994_AIF1CLK_ENA_MASK, 0);
1302 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1303 wm8994->aif1clk_disable = 0;
1304 }
1305 if (wm8994->aif2clk_disable) {
1306 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1307 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1308 WM8994_AIF2CLK_ENA_MASK, 0);
1309 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1310 wm8994->aif2clk_disable = 0;
1311 }
1312 break;
1313 }
1314
1315 return 0;
1316 }
1317
1318 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1319 struct snd_kcontrol *kcontrol, int event)
1320 {
1321 late_enable_ev(w, kcontrol, event);
1322 return 0;
1323 }
1324
1325 static int micbias_ev(struct snd_soc_dapm_widget *w,
1326 struct snd_kcontrol *kcontrol, int event)
1327 {
1328 late_enable_ev(w, kcontrol, event);
1329 return 0;
1330 }
1331
1332 static int dac_ev(struct snd_soc_dapm_widget *w,
1333 struct snd_kcontrol *kcontrol, int event)
1334 {
1335 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1336 unsigned int mask = 1 << w->shift;
1337
1338 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1339 mask, mask);
1340 return 0;
1341 }
1342
1343 static const char *adc_mux_text[] = {
1344 "ADC",
1345 "DMIC",
1346 };
1347
1348 static SOC_ENUM_SINGLE_VIRT_DECL(adc_enum, adc_mux_text);
1349
1350 static const struct snd_kcontrol_new adcl_mux =
1351 SOC_DAPM_ENUM("ADCL Mux", adc_enum);
1352
1353 static const struct snd_kcontrol_new adcr_mux =
1354 SOC_DAPM_ENUM("ADCR Mux", adc_enum);
1355
1356 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1357 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1358 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1359 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1360 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1361 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1362 };
1363
1364 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1365 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1366 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1367 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1368 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1369 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1370 };
1371
1372 /* Debugging; dump chip status after DAPM transitions */
1373 static int post_ev(struct snd_soc_dapm_widget *w,
1374 struct snd_kcontrol *kcontrol, int event)
1375 {
1376 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1377 dev_dbg(codec->dev, "SRC status: %x\n",
1378 snd_soc_read(codec,
1379 WM8994_RATE_STATUS));
1380 return 0;
1381 }
1382
1383 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1384 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1385 1, 1, 0),
1386 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1387 0, 1, 0),
1388 };
1389
1390 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1391 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1392 1, 1, 0),
1393 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1394 0, 1, 0),
1395 };
1396
1397 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1398 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1399 1, 1, 0),
1400 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1401 0, 1, 0),
1402 };
1403
1404 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1405 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1406 1, 1, 0),
1407 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1408 0, 1, 0),
1409 };
1410
1411 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1412 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1413 5, 1, 0),
1414 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1415 4, 1, 0),
1416 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1417 2, 1, 0),
1418 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1419 1, 1, 0),
1420 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1421 0, 1, 0),
1422 };
1423
1424 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1425 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1426 5, 1, 0),
1427 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1428 4, 1, 0),
1429 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1430 2, 1, 0),
1431 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1432 1, 1, 0),
1433 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1434 0, 1, 0),
1435 };
1436
1437 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1438 SOC_SINGLE_EXT(xname, reg, shift, max, invert, \
1439 snd_soc_dapm_get_volsw, wm8994_put_class_w)
1440
1441 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1442 struct snd_ctl_elem_value *ucontrol)
1443 {
1444 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
1445 int ret;
1446
1447 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1448
1449 wm_hubs_update_class_w(codec);
1450
1451 return ret;
1452 }
1453
1454 static const struct snd_kcontrol_new dac1l_mix[] = {
1455 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1456 5, 1, 0),
1457 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1458 4, 1, 0),
1459 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1460 2, 1, 0),
1461 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1462 1, 1, 0),
1463 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1464 0, 1, 0),
1465 };
1466
1467 static const struct snd_kcontrol_new dac1r_mix[] = {
1468 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1469 5, 1, 0),
1470 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1471 4, 1, 0),
1472 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1473 2, 1, 0),
1474 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1475 1, 1, 0),
1476 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1477 0, 1, 0),
1478 };
1479
1480 static const char *sidetone_text[] = {
1481 "ADC/DMIC1", "DMIC2",
1482 };
1483
1484 static SOC_ENUM_SINGLE_DECL(sidetone1_enum,
1485 WM8994_SIDETONE, 0, sidetone_text);
1486
1487 static const struct snd_kcontrol_new sidetone1_mux =
1488 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1489
1490 static SOC_ENUM_SINGLE_DECL(sidetone2_enum,
1491 WM8994_SIDETONE, 1, sidetone_text);
1492
1493 static const struct snd_kcontrol_new sidetone2_mux =
1494 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1495
1496 static const char *aif1dac_text[] = {
1497 "AIF1DACDAT", "AIF3DACDAT",
1498 };
1499
1500 static const char *loopback_text[] = {
1501 "None", "ADCDAT",
1502 };
1503
1504 static SOC_ENUM_SINGLE_DECL(aif1_loopback_enum,
1505 WM8994_AIF1_CONTROL_2,
1506 WM8994_AIF1_LOOPBACK_SHIFT,
1507 loopback_text);
1508
1509 static const struct snd_kcontrol_new aif1_loopback =
1510 SOC_DAPM_ENUM("AIF1 Loopback", aif1_loopback_enum);
1511
1512 static SOC_ENUM_SINGLE_DECL(aif2_loopback_enum,
1513 WM8994_AIF2_CONTROL_2,
1514 WM8994_AIF2_LOOPBACK_SHIFT,
1515 loopback_text);
1516
1517 static const struct snd_kcontrol_new aif2_loopback =
1518 SOC_DAPM_ENUM("AIF2 Loopback", aif2_loopback_enum);
1519
1520 static SOC_ENUM_SINGLE_DECL(aif1dac_enum,
1521 WM8994_POWER_MANAGEMENT_6, 0, aif1dac_text);
1522
1523 static const struct snd_kcontrol_new aif1dac_mux =
1524 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1525
1526 static const char *aif2dac_text[] = {
1527 "AIF2DACDAT", "AIF3DACDAT",
1528 };
1529
1530 static SOC_ENUM_SINGLE_DECL(aif2dac_enum,
1531 WM8994_POWER_MANAGEMENT_6, 1, aif2dac_text);
1532
1533 static const struct snd_kcontrol_new aif2dac_mux =
1534 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1535
1536 static const char *aif2adc_text[] = {
1537 "AIF2ADCDAT", "AIF3DACDAT",
1538 };
1539
1540 static SOC_ENUM_SINGLE_DECL(aif2adc_enum,
1541 WM8994_POWER_MANAGEMENT_6, 2, aif2adc_text);
1542
1543 static const struct snd_kcontrol_new aif2adc_mux =
1544 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1545
1546 static const char *aif3adc_text[] = {
1547 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1548 };
1549
1550 static SOC_ENUM_SINGLE_DECL(wm8994_aif3adc_enum,
1551 WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text);
1552
1553 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1554 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1555
1556 static SOC_ENUM_SINGLE_DECL(wm8958_aif3adc_enum,
1557 WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text);
1558
1559 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1560 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1561
1562 static const char *mono_pcm_out_text[] = {
1563 "None", "AIF2ADCL", "AIF2ADCR",
1564 };
1565
1566 static SOC_ENUM_SINGLE_DECL(mono_pcm_out_enum,
1567 WM8994_POWER_MANAGEMENT_6, 9, mono_pcm_out_text);
1568
1569 static const struct snd_kcontrol_new mono_pcm_out_mux =
1570 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1571
1572 static const char *aif2dac_src_text[] = {
1573 "AIF2", "AIF3",
1574 };
1575
1576 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1577 static SOC_ENUM_SINGLE_DECL(aif2dacl_src_enum,
1578 WM8994_POWER_MANAGEMENT_6, 7, aif2dac_src_text);
1579
1580 static const struct snd_kcontrol_new aif2dacl_src_mux =
1581 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1582
1583 static SOC_ENUM_SINGLE_DECL(aif2dacr_src_enum,
1584 WM8994_POWER_MANAGEMENT_6, 8, aif2dac_src_text);
1585
1586 static const struct snd_kcontrol_new aif2dacr_src_mux =
1587 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1588
1589 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1590 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
1591 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1592 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
1593 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1594
1595 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1596 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1597 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1598 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1599 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1600 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1601 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1602 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1603 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1604 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1605
1606 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1607 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1608 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1609 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1610 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1611 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1612 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
1613 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1614 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
1615 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1616
1617 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1618 };
1619
1620 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1621 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
1622 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1623 SND_SOC_DAPM_PRE_PMD),
1624 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
1625 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1626 SND_SOC_DAPM_PRE_PMD),
1627 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1628 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1629 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1630 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1631 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1632 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1633 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
1634 };
1635
1636 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1637 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1638 dac_ev, SND_SOC_DAPM_PRE_PMU),
1639 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1640 dac_ev, SND_SOC_DAPM_PRE_PMU),
1641 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1642 dac_ev, SND_SOC_DAPM_PRE_PMU),
1643 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1644 dac_ev, SND_SOC_DAPM_PRE_PMU),
1645 };
1646
1647 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1648 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1649 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1650 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1651 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1652 };
1653
1654 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1655 SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1656 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1657 SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1658 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1659 };
1660
1661 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1662 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1663 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1664 };
1665
1666 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1667 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1668 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1669 SND_SOC_DAPM_INPUT("Clock"),
1670
1671 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1672 SND_SOC_DAPM_PRE_PMU),
1673 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1674 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1675
1676 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1677 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1678 SND_SOC_DAPM_PRE_PMD),
1679
1680 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1681 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1682 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
1683
1684 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1685 0, SND_SOC_NOPM, 9, 0),
1686 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1687 0, SND_SOC_NOPM, 8, 0),
1688 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1689 SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
1690 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1691 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1692 SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
1693 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1694
1695 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1696 0, SND_SOC_NOPM, 11, 0),
1697 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1698 0, SND_SOC_NOPM, 10, 0),
1699 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1700 SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
1701 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1702 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1703 SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
1704 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1705
1706 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1707 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1708 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1709 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1710
1711 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1712 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1713 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1714 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1715
1716 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1717 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1718 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1719 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1720
1721 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1722 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1723
1724 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1725 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1726 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1727 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1728
1729 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1730 SND_SOC_NOPM, 13, 0),
1731 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1732 SND_SOC_NOPM, 12, 0),
1733 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1734 SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
1735 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1736 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1737 SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
1738 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1739
1740 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1741 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1742 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1743 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1744
1745 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1746 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1747 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1748
1749 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1750 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1751
1752 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1753
1754 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1755 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1756 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1757 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1758
1759 /* Power is done with the muxes since the ADC power also controls the
1760 * downsampling chain, the chip will automatically manage the analogue
1761 * specific portions.
1762 */
1763 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1764 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1765
1766 SND_SOC_DAPM_MUX("AIF1 Loopback", SND_SOC_NOPM, 0, 0, &aif1_loopback),
1767 SND_SOC_DAPM_MUX("AIF2 Loopback", SND_SOC_NOPM, 0, 0, &aif2_loopback),
1768
1769 SND_SOC_DAPM_POST("Debug log", post_ev),
1770 };
1771
1772 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1773 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1774 };
1775
1776 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1777 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
1778 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1779 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1780 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1781 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1782 };
1783
1784 static const struct snd_soc_dapm_route intercon[] = {
1785 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1786 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1787
1788 { "DSP1CLK", NULL, "CLK_SYS" },
1789 { "DSP2CLK", NULL, "CLK_SYS" },
1790 { "DSPINTCLK", NULL, "CLK_SYS" },
1791
1792 { "AIF1ADC1L", NULL, "AIF1CLK" },
1793 { "AIF1ADC1L", NULL, "DSP1CLK" },
1794 { "AIF1ADC1R", NULL, "AIF1CLK" },
1795 { "AIF1ADC1R", NULL, "DSP1CLK" },
1796 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1797
1798 { "AIF1DAC1L", NULL, "AIF1CLK" },
1799 { "AIF1DAC1L", NULL, "DSP1CLK" },
1800 { "AIF1DAC1R", NULL, "AIF1CLK" },
1801 { "AIF1DAC1R", NULL, "DSP1CLK" },
1802 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1803
1804 { "AIF1ADC2L", NULL, "AIF1CLK" },
1805 { "AIF1ADC2L", NULL, "DSP1CLK" },
1806 { "AIF1ADC2R", NULL, "AIF1CLK" },
1807 { "AIF1ADC2R", NULL, "DSP1CLK" },
1808 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1809
1810 { "AIF1DAC2L", NULL, "AIF1CLK" },
1811 { "AIF1DAC2L", NULL, "DSP1CLK" },
1812 { "AIF1DAC2R", NULL, "AIF1CLK" },
1813 { "AIF1DAC2R", NULL, "DSP1CLK" },
1814 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1815
1816 { "AIF2ADCL", NULL, "AIF2CLK" },
1817 { "AIF2ADCL", NULL, "DSP2CLK" },
1818 { "AIF2ADCR", NULL, "AIF2CLK" },
1819 { "AIF2ADCR", NULL, "DSP2CLK" },
1820 { "AIF2ADCR", NULL, "DSPINTCLK" },
1821
1822 { "AIF2DACL", NULL, "AIF2CLK" },
1823 { "AIF2DACL", NULL, "DSP2CLK" },
1824 { "AIF2DACR", NULL, "AIF2CLK" },
1825 { "AIF2DACR", NULL, "DSP2CLK" },
1826 { "AIF2DACR", NULL, "DSPINTCLK" },
1827
1828 { "DMIC1L", NULL, "DMIC1DAT" },
1829 { "DMIC1L", NULL, "CLK_SYS" },
1830 { "DMIC1R", NULL, "DMIC1DAT" },
1831 { "DMIC1R", NULL, "CLK_SYS" },
1832 { "DMIC2L", NULL, "DMIC2DAT" },
1833 { "DMIC2L", NULL, "CLK_SYS" },
1834 { "DMIC2R", NULL, "DMIC2DAT" },
1835 { "DMIC2R", NULL, "CLK_SYS" },
1836
1837 { "ADCL", NULL, "AIF1CLK" },
1838 { "ADCL", NULL, "DSP1CLK" },
1839 { "ADCL", NULL, "DSPINTCLK" },
1840
1841 { "ADCR", NULL, "AIF1CLK" },
1842 { "ADCR", NULL, "DSP1CLK" },
1843 { "ADCR", NULL, "DSPINTCLK" },
1844
1845 { "ADCL Mux", "ADC", "ADCL" },
1846 { "ADCL Mux", "DMIC", "DMIC1L" },
1847 { "ADCR Mux", "ADC", "ADCR" },
1848 { "ADCR Mux", "DMIC", "DMIC1R" },
1849
1850 { "DAC1L", NULL, "AIF1CLK" },
1851 { "DAC1L", NULL, "DSP1CLK" },
1852 { "DAC1L", NULL, "DSPINTCLK" },
1853
1854 { "DAC1R", NULL, "AIF1CLK" },
1855 { "DAC1R", NULL, "DSP1CLK" },
1856 { "DAC1R", NULL, "DSPINTCLK" },
1857
1858 { "DAC2L", NULL, "AIF2CLK" },
1859 { "DAC2L", NULL, "DSP2CLK" },
1860 { "DAC2L", NULL, "DSPINTCLK" },
1861
1862 { "DAC2R", NULL, "AIF2DACR" },
1863 { "DAC2R", NULL, "AIF2CLK" },
1864 { "DAC2R", NULL, "DSP2CLK" },
1865 { "DAC2R", NULL, "DSPINTCLK" },
1866
1867 { "TOCLK", NULL, "CLK_SYS" },
1868
1869 { "AIF1DACDAT", NULL, "AIF1 Playback" },
1870 { "AIF2DACDAT", NULL, "AIF2 Playback" },
1871 { "AIF3DACDAT", NULL, "AIF3 Playback" },
1872
1873 { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1874 { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1875 { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1876
1877 /* AIF1 outputs */
1878 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1879 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1880 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1881
1882 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1883 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1884 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1885
1886 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1887 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1888 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1889
1890 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1891 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1892 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1893
1894 /* Pin level routing for AIF3 */
1895 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1896 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1897 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1898 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1899
1900 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1 Loopback" },
1901 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1902 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2 Loopback" },
1903 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1904 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1905 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1906 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1907
1908 /* DAC1 inputs */
1909 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1910 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1911 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1912 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1913 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1914
1915 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1916 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1917 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1918 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1919 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1920
1921 /* DAC2/AIF2 outputs */
1922 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1923 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1924 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1925 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1926 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1927 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1928
1929 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1930 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1931 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1932 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1933 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1934 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1935
1936 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1937 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1938 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1939 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1940
1941 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1942
1943 /* AIF3 output */
1944 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1945 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1946 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1947 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1948 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1949 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1950 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1951 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1952
1953 /* Loopback */
1954 { "AIF1 Loopback", "ADCDAT", "AIF1ADCDAT" },
1955 { "AIF1 Loopback", "None", "AIF1DACDAT" },
1956 { "AIF2 Loopback", "ADCDAT", "AIF2ADCDAT" },
1957 { "AIF2 Loopback", "None", "AIF2DACDAT" },
1958
1959 /* Sidetone */
1960 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1961 { "Left Sidetone", "DMIC2", "DMIC2L" },
1962 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1963 { "Right Sidetone", "DMIC2", "DMIC2R" },
1964
1965 /* Output stages */
1966 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1967 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1968
1969 { "SPKL", "DAC1 Switch", "DAC1L" },
1970 { "SPKL", "DAC2 Switch", "DAC2L" },
1971
1972 { "SPKR", "DAC1 Switch", "DAC1R" },
1973 { "SPKR", "DAC2 Switch", "DAC2R" },
1974
1975 { "Left Headphone Mux", "DAC", "DAC1L" },
1976 { "Right Headphone Mux", "DAC", "DAC1R" },
1977 };
1978
1979 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1980 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1981 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1982 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1983 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1984 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1985 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1986 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1987 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1988 };
1989
1990 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1991 { "DAC1L", NULL, "DAC1L Mixer" },
1992 { "DAC1R", NULL, "DAC1R Mixer" },
1993 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1994 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1995 };
1996
1997 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1998 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1999 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
2000 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
2001 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
2002 { "MICBIAS1", NULL, "CLK_SYS" },
2003 { "MICBIAS1", NULL, "MICBIAS Supply" },
2004 { "MICBIAS2", NULL, "CLK_SYS" },
2005 { "MICBIAS2", NULL, "MICBIAS Supply" },
2006 };
2007
2008 static const struct snd_soc_dapm_route wm8994_intercon[] = {
2009 { "AIF2DACL", NULL, "AIF2DAC Mux" },
2010 { "AIF2DACR", NULL, "AIF2DAC Mux" },
2011 { "MICBIAS1", NULL, "VMID" },
2012 { "MICBIAS2", NULL, "VMID" },
2013 };
2014
2015 static const struct snd_soc_dapm_route wm8958_intercon[] = {
2016 { "AIF2DACL", NULL, "AIF2DACL Mux" },
2017 { "AIF2DACR", NULL, "AIF2DACR Mux" },
2018
2019 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
2020 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
2021 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
2022 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
2023
2024 { "AIF3DACDAT", NULL, "AIF3" },
2025 { "AIF3ADCDAT", NULL, "AIF3" },
2026
2027 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
2028 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
2029
2030 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
2031 };
2032
2033 /* The size in bits of the FLL divide multiplied by 10
2034 * to allow rounding later */
2035 #define FIXED_FLL_SIZE ((1 << 16) * 10)
2036
2037 struct fll_div {
2038 u16 outdiv;
2039 u16 n;
2040 u16 k;
2041 u16 lambda;
2042 u16 clk_ref_div;
2043 u16 fll_fratio;
2044 };
2045
2046 static int wm8994_get_fll_config(struct wm8994 *control, struct fll_div *fll,
2047 int freq_in, int freq_out)
2048 {
2049 u64 Kpart;
2050 unsigned int K, Ndiv, Nmod, gcd_fll;
2051
2052 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2053
2054 /* Scale the input frequency down to <= 13.5MHz */
2055 fll->clk_ref_div = 0;
2056 while (freq_in > 13500000) {
2057 fll->clk_ref_div++;
2058 freq_in /= 2;
2059
2060 if (fll->clk_ref_div > 3)
2061 return -EINVAL;
2062 }
2063 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2064
2065 /* Scale the output to give 90MHz<=Fvco<=100MHz */
2066 fll->outdiv = 3;
2067 while (freq_out * (fll->outdiv + 1) < 90000000) {
2068 fll->outdiv++;
2069 if (fll->outdiv > 63)
2070 return -EINVAL;
2071 }
2072 freq_out *= fll->outdiv + 1;
2073 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2074
2075 if (freq_in > 1000000) {
2076 fll->fll_fratio = 0;
2077 } else if (freq_in > 256000) {
2078 fll->fll_fratio = 1;
2079 freq_in *= 2;
2080 } else if (freq_in > 128000) {
2081 fll->fll_fratio = 2;
2082 freq_in *= 4;
2083 } else if (freq_in > 64000) {
2084 fll->fll_fratio = 3;
2085 freq_in *= 8;
2086 } else {
2087 fll->fll_fratio = 4;
2088 freq_in *= 16;
2089 }
2090 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2091
2092 /* Now, calculate N.K */
2093 Ndiv = freq_out / freq_in;
2094
2095 fll->n = Ndiv;
2096 Nmod = freq_out % freq_in;
2097 pr_debug("Nmod=%d\n", Nmod);
2098
2099 switch (control->type) {
2100 case WM8994:
2101 /* Calculate fractional part - scale up so we can round. */
2102 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
2103
2104 do_div(Kpart, freq_in);
2105
2106 K = Kpart & 0xFFFFFFFF;
2107
2108 if ((K % 10) >= 5)
2109 K += 5;
2110
2111 /* Move down to proper range now rounding is done */
2112 fll->k = K / 10;
2113 fll->lambda = 0;
2114
2115 pr_debug("N=%x K=%x\n", fll->n, fll->k);
2116 break;
2117
2118 default:
2119 gcd_fll = gcd(freq_out, freq_in);
2120
2121 fll->k = (freq_out - (freq_in * fll->n)) / gcd_fll;
2122 fll->lambda = freq_in / gcd_fll;
2123
2124 }
2125
2126 return 0;
2127 }
2128
2129 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
2130 unsigned int freq_in, unsigned int freq_out)
2131 {
2132 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2133 struct wm8994 *control = wm8994->wm8994;
2134 int reg_offset, ret;
2135 struct fll_div fll;
2136 u16 reg, clk1, aif_reg, aif_src;
2137 unsigned long timeout;
2138 bool was_enabled;
2139
2140 switch (id) {
2141 case WM8994_FLL1:
2142 reg_offset = 0;
2143 id = 0;
2144 aif_src = 0x10;
2145 break;
2146 case WM8994_FLL2:
2147 reg_offset = 0x20;
2148 id = 1;
2149 aif_src = 0x18;
2150 break;
2151 default:
2152 return -EINVAL;
2153 }
2154
2155 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2156 was_enabled = reg & WM8994_FLL1_ENA;
2157
2158 switch (src) {
2159 case 0:
2160 /* Allow no source specification when stopping */
2161 if (freq_out)
2162 return -EINVAL;
2163 src = wm8994->fll[id].src;
2164 break;
2165 case WM8994_FLL_SRC_MCLK1:
2166 case WM8994_FLL_SRC_MCLK2:
2167 case WM8994_FLL_SRC_LRCLK:
2168 case WM8994_FLL_SRC_BCLK:
2169 break;
2170 case WM8994_FLL_SRC_INTERNAL:
2171 freq_in = 12000000;
2172 freq_out = 12000000;
2173 break;
2174 default:
2175 return -EINVAL;
2176 }
2177
2178 /* Are we changing anything? */
2179 if (wm8994->fll[id].src == src &&
2180 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2181 return 0;
2182
2183 /* If we're stopping the FLL redo the old config - no
2184 * registers will actually be written but we avoid GCC flow
2185 * analysis bugs spewing warnings.
2186 */
2187 if (freq_out)
2188 ret = wm8994_get_fll_config(control, &fll, freq_in, freq_out);
2189 else
2190 ret = wm8994_get_fll_config(control, &fll, wm8994->fll[id].in,
2191 wm8994->fll[id].out);
2192 if (ret < 0)
2193 return ret;
2194
2195 /* Make sure that we're not providing SYSCLK right now */
2196 clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
2197 if (clk1 & WM8994_SYSCLK_SRC)
2198 aif_reg = WM8994_AIF2_CLOCKING_1;
2199 else
2200 aif_reg = WM8994_AIF1_CLOCKING_1;
2201 reg = snd_soc_read(codec, aif_reg);
2202
2203 if ((reg & WM8994_AIF1CLK_ENA) &&
2204 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2205 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
2206 id + 1);
2207 return -EBUSY;
2208 }
2209
2210 /* We always need to disable the FLL while reconfiguring */
2211 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2212 WM8994_FLL1_ENA, 0);
2213
2214 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
2215 freq_in == freq_out && freq_out) {
2216 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
2217 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2218 WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2219 goto out;
2220 }
2221
2222 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2223 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2224 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2225 WM8994_FLL1_OUTDIV_MASK |
2226 WM8994_FLL1_FRATIO_MASK, reg);
2227
2228 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
2229 WM8994_FLL1_K_MASK, fll.k);
2230
2231 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2232 WM8994_FLL1_N_MASK,
2233 fll.n << WM8994_FLL1_N_SHIFT);
2234
2235 if (fll.lambda) {
2236 snd_soc_update_bits(codec, WM8958_FLL1_EFS_1 + reg_offset,
2237 WM8958_FLL1_LAMBDA_MASK,
2238 fll.lambda);
2239 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset,
2240 WM8958_FLL1_EFS_ENA, WM8958_FLL1_EFS_ENA);
2241 } else {
2242 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset,
2243 WM8958_FLL1_EFS_ENA, 0);
2244 }
2245
2246 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2247 WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
2248 WM8994_FLL1_REFCLK_DIV_MASK |
2249 WM8994_FLL1_REFCLK_SRC_MASK,
2250 ((src == WM8994_FLL_SRC_INTERNAL)
2251 << WM8994_FLL1_FRC_NCO_SHIFT) |
2252 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2253 (src - 1));
2254
2255 /* Clear any pending completion from a previous failure */
2256 try_wait_for_completion(&wm8994->fll_locked[id]);
2257
2258 /* Enable (with fractional mode if required) */
2259 if (freq_out) {
2260 /* Enable VMID if we need it */
2261 if (!was_enabled) {
2262 active_reference(codec);
2263
2264 switch (control->type) {
2265 case WM8994:
2266 vmid_reference(codec);
2267 break;
2268 case WM8958:
2269 if (control->revision < 1)
2270 vmid_reference(codec);
2271 break;
2272 default:
2273 break;
2274 }
2275 }
2276
2277 reg = WM8994_FLL1_ENA;
2278
2279 if (fll.k)
2280 reg |= WM8994_FLL1_FRAC;
2281 if (src == WM8994_FLL_SRC_INTERNAL)
2282 reg |= WM8994_FLL1_OSC_ENA;
2283
2284 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2285 WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
2286 WM8994_FLL1_FRAC, reg);
2287
2288 if (wm8994->fll_locked_irq) {
2289 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2290 msecs_to_jiffies(10));
2291 if (timeout == 0)
2292 dev_warn(codec->dev,
2293 "Timed out waiting for FLL lock\n");
2294 } else {
2295 msleep(5);
2296 }
2297 } else {
2298 if (was_enabled) {
2299 switch (control->type) {
2300 case WM8994:
2301 vmid_dereference(codec);
2302 break;
2303 case WM8958:
2304 if (control->revision < 1)
2305 vmid_dereference(codec);
2306 break;
2307 default:
2308 break;
2309 }
2310
2311 active_dereference(codec);
2312 }
2313 }
2314
2315 out:
2316 wm8994->fll[id].in = freq_in;
2317 wm8994->fll[id].out = freq_out;
2318 wm8994->fll[id].src = src;
2319
2320 configure_clock(codec);
2321
2322 /*
2323 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2324 * for detection.
2325 */
2326 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2327 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2328
2329 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2330 & WM8994_AIF1CLK_RATE_MASK;
2331 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2332 & WM8994_AIF1CLK_RATE_MASK;
2333
2334 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2335 WM8994_AIF1CLK_RATE_MASK, 0x1);
2336 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2337 WM8994_AIF2CLK_RATE_MASK, 0x1);
2338 } else if (wm8994->aifdiv[0]) {
2339 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2340 WM8994_AIF1CLK_RATE_MASK,
2341 wm8994->aifdiv[0]);
2342 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2343 WM8994_AIF2CLK_RATE_MASK,
2344 wm8994->aifdiv[1]);
2345
2346 wm8994->aifdiv[0] = 0;
2347 wm8994->aifdiv[1] = 0;
2348 }
2349
2350 return 0;
2351 }
2352
2353 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2354 {
2355 struct completion *completion = data;
2356
2357 complete(completion);
2358
2359 return IRQ_HANDLED;
2360 }
2361
2362 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2363
2364 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2365 unsigned int freq_in, unsigned int freq_out)
2366 {
2367 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2368 }
2369
2370 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2371 int clk_id, unsigned int freq, int dir)
2372 {
2373 struct snd_soc_codec *codec = dai->codec;
2374 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2375 int i;
2376
2377 switch (dai->id) {
2378 case 1:
2379 case 2:
2380 break;
2381
2382 default:
2383 /* AIF3 shares clocking with AIF1/2 */
2384 return -EINVAL;
2385 }
2386
2387 switch (clk_id) {
2388 case WM8994_SYSCLK_MCLK1:
2389 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2390 wm8994->mclk[0] = freq;
2391 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2392 dai->id, freq);
2393 break;
2394
2395 case WM8994_SYSCLK_MCLK2:
2396 /* TODO: Set GPIO AF */
2397 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2398 wm8994->mclk[1] = freq;
2399 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2400 dai->id, freq);
2401 break;
2402
2403 case WM8994_SYSCLK_FLL1:
2404 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2405 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2406 break;
2407
2408 case WM8994_SYSCLK_FLL2:
2409 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2410 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2411 break;
2412
2413 case WM8994_SYSCLK_OPCLK:
2414 /* Special case - a division (times 10) is given and
2415 * no effect on main clocking.
2416 */
2417 if (freq) {
2418 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2419 if (opclk_divs[i] == freq)
2420 break;
2421 if (i == ARRAY_SIZE(opclk_divs))
2422 return -EINVAL;
2423 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2424 WM8994_OPCLK_DIV_MASK, i);
2425 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2426 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2427 } else {
2428 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2429 WM8994_OPCLK_ENA, 0);
2430 }
2431
2432 default:
2433 return -EINVAL;
2434 }
2435
2436 configure_clock(codec);
2437
2438 /*
2439 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2440 * for detection.
2441 */
2442 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2443 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2444
2445 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2446 & WM8994_AIF1CLK_RATE_MASK;
2447 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2448 & WM8994_AIF1CLK_RATE_MASK;
2449
2450 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2451 WM8994_AIF1CLK_RATE_MASK, 0x1);
2452 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2453 WM8994_AIF2CLK_RATE_MASK, 0x1);
2454 } else if (wm8994->aifdiv[0]) {
2455 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2456 WM8994_AIF1CLK_RATE_MASK,
2457 wm8994->aifdiv[0]);
2458 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2459 WM8994_AIF2CLK_RATE_MASK,
2460 wm8994->aifdiv[1]);
2461
2462 wm8994->aifdiv[0] = 0;
2463 wm8994->aifdiv[1] = 0;
2464 }
2465
2466 return 0;
2467 }
2468
2469 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2470 enum snd_soc_bias_level level)
2471 {
2472 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2473 struct wm8994 *control = wm8994->wm8994;
2474
2475 wm_hubs_set_bias_level(codec, level);
2476
2477 switch (level) {
2478 case SND_SOC_BIAS_ON:
2479 break;
2480
2481 case SND_SOC_BIAS_PREPARE:
2482 /* MICBIAS into regulating mode */
2483 switch (control->type) {
2484 case WM8958:
2485 case WM1811:
2486 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2487 WM8958_MICB1_MODE, 0);
2488 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2489 WM8958_MICB2_MODE, 0);
2490 break;
2491 default:
2492 break;
2493 }
2494
2495 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2496 active_reference(codec);
2497 break;
2498
2499 case SND_SOC_BIAS_STANDBY:
2500 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2501 switch (control->type) {
2502 case WM8958:
2503 if (control->revision == 0) {
2504 /* Optimise performance for rev A */
2505 snd_soc_update_bits(codec,
2506 WM8958_CHARGE_PUMP_2,
2507 WM8958_CP_DISCH,
2508 WM8958_CP_DISCH);
2509 }
2510 break;
2511
2512 default:
2513 break;
2514 }
2515
2516 /* Discharge LINEOUT1 & 2 */
2517 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2518 WM8994_LINEOUT1_DISCH |
2519 WM8994_LINEOUT2_DISCH,
2520 WM8994_LINEOUT1_DISCH |
2521 WM8994_LINEOUT2_DISCH);
2522 }
2523
2524 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2525 active_dereference(codec);
2526
2527 /* MICBIAS into bypass mode on newer devices */
2528 switch (control->type) {
2529 case WM8958:
2530 case WM1811:
2531 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2532 WM8958_MICB1_MODE,
2533 WM8958_MICB1_MODE);
2534 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2535 WM8958_MICB2_MODE,
2536 WM8958_MICB2_MODE);
2537 break;
2538 default:
2539 break;
2540 }
2541 break;
2542
2543 case SND_SOC_BIAS_OFF:
2544 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2545 wm8994->cur_fw = NULL;
2546 break;
2547 }
2548
2549 return 0;
2550 }
2551
2552 int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2553 {
2554 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2555 struct snd_soc_dapm_context *dapm = &codec->dapm;
2556
2557 switch (mode) {
2558 case WM8994_VMID_NORMAL:
2559 snd_soc_dapm_mutex_lock(dapm);
2560
2561 if (wm8994->hubs.lineout1_se) {
2562 snd_soc_dapm_disable_pin_unlocked(dapm,
2563 "LINEOUT1N Driver");
2564 snd_soc_dapm_disable_pin_unlocked(dapm,
2565 "LINEOUT1P Driver");
2566 }
2567 if (wm8994->hubs.lineout2_se) {
2568 snd_soc_dapm_disable_pin_unlocked(dapm,
2569 "LINEOUT2N Driver");
2570 snd_soc_dapm_disable_pin_unlocked(dapm,
2571 "LINEOUT2P Driver");
2572 }
2573
2574 /* Do the sync with the old mode to allow it to clean up */
2575 snd_soc_dapm_sync_unlocked(dapm);
2576 wm8994->vmid_mode = mode;
2577
2578 snd_soc_dapm_mutex_unlock(dapm);
2579 break;
2580
2581 case WM8994_VMID_FORCE:
2582 snd_soc_dapm_mutex_lock(dapm);
2583
2584 if (wm8994->hubs.lineout1_se) {
2585 snd_soc_dapm_force_enable_pin_unlocked(dapm,
2586 "LINEOUT1N Driver");
2587 snd_soc_dapm_force_enable_pin_unlocked(dapm,
2588 "LINEOUT1P Driver");
2589 }
2590 if (wm8994->hubs.lineout2_se) {
2591 snd_soc_dapm_force_enable_pin_unlocked(dapm,
2592 "LINEOUT2N Driver");
2593 snd_soc_dapm_force_enable_pin_unlocked(dapm,
2594 "LINEOUT2P Driver");
2595 }
2596
2597 wm8994->vmid_mode = mode;
2598 snd_soc_dapm_sync_unlocked(dapm);
2599
2600 snd_soc_dapm_mutex_unlock(dapm);
2601 break;
2602
2603 default:
2604 return -EINVAL;
2605 }
2606
2607 return 0;
2608 }
2609
2610 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2611 {
2612 struct snd_soc_codec *codec = dai->codec;
2613 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2614 struct wm8994 *control = wm8994->wm8994;
2615 int ms_reg;
2616 int aif1_reg;
2617 int dac_reg;
2618 int adc_reg;
2619 int ms = 0;
2620 int aif1 = 0;
2621 int lrclk = 0;
2622
2623 switch (dai->id) {
2624 case 1:
2625 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2626 aif1_reg = WM8994_AIF1_CONTROL_1;
2627 dac_reg = WM8994_AIF1DAC_LRCLK;
2628 adc_reg = WM8994_AIF1ADC_LRCLK;
2629 break;
2630 case 2:
2631 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2632 aif1_reg = WM8994_AIF2_CONTROL_1;
2633 dac_reg = WM8994_AIF1DAC_LRCLK;
2634 adc_reg = WM8994_AIF1ADC_LRCLK;
2635 break;
2636 default:
2637 return -EINVAL;
2638 }
2639
2640 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2641 case SND_SOC_DAIFMT_CBS_CFS:
2642 break;
2643 case SND_SOC_DAIFMT_CBM_CFM:
2644 ms = WM8994_AIF1_MSTR;
2645 break;
2646 default:
2647 return -EINVAL;
2648 }
2649
2650 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2651 case SND_SOC_DAIFMT_DSP_B:
2652 aif1 |= WM8994_AIF1_LRCLK_INV;
2653 lrclk |= WM8958_AIF1_LRCLK_INV;
2654 case SND_SOC_DAIFMT_DSP_A:
2655 aif1 |= 0x18;
2656 break;
2657 case SND_SOC_DAIFMT_I2S:
2658 aif1 |= 0x10;
2659 break;
2660 case SND_SOC_DAIFMT_RIGHT_J:
2661 break;
2662 case SND_SOC_DAIFMT_LEFT_J:
2663 aif1 |= 0x8;
2664 break;
2665 default:
2666 return -EINVAL;
2667 }
2668
2669 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2670 case SND_SOC_DAIFMT_DSP_A:
2671 case SND_SOC_DAIFMT_DSP_B:
2672 /* frame inversion not valid for DSP modes */
2673 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2674 case SND_SOC_DAIFMT_NB_NF:
2675 break;
2676 case SND_SOC_DAIFMT_IB_NF:
2677 aif1 |= WM8994_AIF1_BCLK_INV;
2678 break;
2679 default:
2680 return -EINVAL;
2681 }
2682 break;
2683
2684 case SND_SOC_DAIFMT_I2S:
2685 case SND_SOC_DAIFMT_RIGHT_J:
2686 case SND_SOC_DAIFMT_LEFT_J:
2687 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2688 case SND_SOC_DAIFMT_NB_NF:
2689 break;
2690 case SND_SOC_DAIFMT_IB_IF:
2691 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2692 lrclk |= WM8958_AIF1_LRCLK_INV;
2693 break;
2694 case SND_SOC_DAIFMT_IB_NF:
2695 aif1 |= WM8994_AIF1_BCLK_INV;
2696 break;
2697 case SND_SOC_DAIFMT_NB_IF:
2698 aif1 |= WM8994_AIF1_LRCLK_INV;
2699 lrclk |= WM8958_AIF1_LRCLK_INV;
2700 break;
2701 default:
2702 return -EINVAL;
2703 }
2704 break;
2705 default:
2706 return -EINVAL;
2707 }
2708
2709 /* The AIF2 format configuration needs to be mirrored to AIF3
2710 * on WM8958 if it's in use so just do it all the time. */
2711 switch (control->type) {
2712 case WM1811:
2713 case WM8958:
2714 if (dai->id == 2)
2715 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2716 WM8994_AIF1_LRCLK_INV |
2717 WM8958_AIF3_FMT_MASK, aif1);
2718 break;
2719
2720 default:
2721 break;
2722 }
2723
2724 snd_soc_update_bits(codec, aif1_reg,
2725 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2726 WM8994_AIF1_FMT_MASK,
2727 aif1);
2728 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2729 ms);
2730 snd_soc_update_bits(codec, dac_reg,
2731 WM8958_AIF1_LRCLK_INV, lrclk);
2732 snd_soc_update_bits(codec, adc_reg,
2733 WM8958_AIF1_LRCLK_INV, lrclk);
2734
2735 return 0;
2736 }
2737
2738 static struct {
2739 int val, rate;
2740 } srs[] = {
2741 { 0, 8000 },
2742 { 1, 11025 },
2743 { 2, 12000 },
2744 { 3, 16000 },
2745 { 4, 22050 },
2746 { 5, 24000 },
2747 { 6, 32000 },
2748 { 7, 44100 },
2749 { 8, 48000 },
2750 { 9, 88200 },
2751 { 10, 96000 },
2752 };
2753
2754 static int fs_ratios[] = {
2755 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2756 };
2757
2758 static int bclk_divs[] = {
2759 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2760 640, 880, 960, 1280, 1760, 1920
2761 };
2762
2763 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2764 struct snd_pcm_hw_params *params,
2765 struct snd_soc_dai *dai)
2766 {
2767 struct snd_soc_codec *codec = dai->codec;
2768 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2769 struct wm8994 *control = wm8994->wm8994;
2770 struct wm8994_pdata *pdata = &control->pdata;
2771 int aif1_reg;
2772 int aif2_reg;
2773 int bclk_reg;
2774 int lrclk_reg;
2775 int rate_reg;
2776 int aif1 = 0;
2777 int aif2 = 0;
2778 int bclk = 0;
2779 int lrclk = 0;
2780 int rate_val = 0;
2781 int id = dai->id - 1;
2782
2783 int i, cur_val, best_val, bclk_rate, best;
2784
2785 switch (dai->id) {
2786 case 1:
2787 aif1_reg = WM8994_AIF1_CONTROL_1;
2788 aif2_reg = WM8994_AIF1_CONTROL_2;
2789 bclk_reg = WM8994_AIF1_BCLK;
2790 rate_reg = WM8994_AIF1_RATE;
2791 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2792 wm8994->lrclk_shared[0]) {
2793 lrclk_reg = WM8994_AIF1DAC_LRCLK;
2794 } else {
2795 lrclk_reg = WM8994_AIF1ADC_LRCLK;
2796 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2797 }
2798 break;
2799 case 2:
2800 aif1_reg = WM8994_AIF2_CONTROL_1;
2801 aif2_reg = WM8994_AIF2_CONTROL_2;
2802 bclk_reg = WM8994_AIF2_BCLK;
2803 rate_reg = WM8994_AIF2_RATE;
2804 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2805 wm8994->lrclk_shared[1]) {
2806 lrclk_reg = WM8994_AIF2DAC_LRCLK;
2807 } else {
2808 lrclk_reg = WM8994_AIF2ADC_LRCLK;
2809 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2810 }
2811 break;
2812 default:
2813 return -EINVAL;
2814 }
2815
2816 bclk_rate = params_rate(params);
2817 switch (params_width(params)) {
2818 case 16:
2819 bclk_rate *= 16;
2820 break;
2821 case 20:
2822 bclk_rate *= 20;
2823 aif1 |= 0x20;
2824 break;
2825 case 24:
2826 bclk_rate *= 24;
2827 aif1 |= 0x40;
2828 break;
2829 case 32:
2830 bclk_rate *= 32;
2831 aif1 |= 0x60;
2832 break;
2833 default:
2834 return -EINVAL;
2835 }
2836
2837 wm8994->channels[id] = params_channels(params);
2838 if (pdata->max_channels_clocked[id] &&
2839 wm8994->channels[id] > pdata->max_channels_clocked[id]) {
2840 dev_dbg(dai->dev, "Constraining channels to %d from %d\n",
2841 pdata->max_channels_clocked[id], wm8994->channels[id]);
2842 wm8994->channels[id] = pdata->max_channels_clocked[id];
2843 }
2844
2845 switch (wm8994->channels[id]) {
2846 case 1:
2847 case 2:
2848 bclk_rate *= 2;
2849 break;
2850 default:
2851 bclk_rate *= 4;
2852 break;
2853 }
2854
2855 /* Try to find an appropriate sample rate; look for an exact match. */
2856 for (i = 0; i < ARRAY_SIZE(srs); i++)
2857 if (srs[i].rate == params_rate(params))
2858 break;
2859 if (i == ARRAY_SIZE(srs))
2860 return -EINVAL;
2861 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2862
2863 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2864 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2865 dai->id, wm8994->aifclk[id], bclk_rate);
2866
2867 if (wm8994->channels[id] == 1 &&
2868 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2869 aif2 |= WM8994_AIF1_MONO;
2870
2871 if (wm8994->aifclk[id] == 0) {
2872 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2873 return -EINVAL;
2874 }
2875
2876 /* AIFCLK/fs ratio; look for a close match in either direction */
2877 best = 0;
2878 best_val = abs((fs_ratios[0] * params_rate(params))
2879 - wm8994->aifclk[id]);
2880 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2881 cur_val = abs((fs_ratios[i] * params_rate(params))
2882 - wm8994->aifclk[id]);
2883 if (cur_val >= best_val)
2884 continue;
2885 best = i;
2886 best_val = cur_val;
2887 }
2888 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2889 dai->id, fs_ratios[best]);
2890 rate_val |= best;
2891
2892 /* We may not get quite the right frequency if using
2893 * approximate clocks so look for the closest match that is
2894 * higher than the target (we need to ensure that there enough
2895 * BCLKs to clock out the samples).
2896 */
2897 best = 0;
2898 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2899 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2900 if (cur_val < 0) /* BCLK table is sorted */
2901 break;
2902 best = i;
2903 }
2904 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2905 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2906 bclk_divs[best], bclk_rate);
2907 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2908
2909 lrclk = bclk_rate / params_rate(params);
2910 if (!lrclk) {
2911 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2912 bclk_rate);
2913 return -EINVAL;
2914 }
2915 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2916 lrclk, bclk_rate / lrclk);
2917
2918 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2919 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2920 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2921 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2922 lrclk);
2923 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2924 WM8994_AIF1CLK_RATE_MASK, rate_val);
2925
2926 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2927 switch (dai->id) {
2928 case 1:
2929 wm8994->dac_rates[0] = params_rate(params);
2930 wm8994_set_retune_mobile(codec, 0);
2931 wm8994_set_retune_mobile(codec, 1);
2932 break;
2933 case 2:
2934 wm8994->dac_rates[1] = params_rate(params);
2935 wm8994_set_retune_mobile(codec, 2);
2936 break;
2937 }
2938 }
2939
2940 return 0;
2941 }
2942
2943 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2944 struct snd_pcm_hw_params *params,
2945 struct snd_soc_dai *dai)
2946 {
2947 struct snd_soc_codec *codec = dai->codec;
2948 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2949 struct wm8994 *control = wm8994->wm8994;
2950 int aif1_reg;
2951 int aif1 = 0;
2952
2953 switch (dai->id) {
2954 case 3:
2955 switch (control->type) {
2956 case WM1811:
2957 case WM8958:
2958 aif1_reg = WM8958_AIF3_CONTROL_1;
2959 break;
2960 default:
2961 return 0;
2962 }
2963 break;
2964 default:
2965 return 0;
2966 }
2967
2968 switch (params_width(params)) {
2969 case 16:
2970 break;
2971 case 20:
2972 aif1 |= 0x20;
2973 break;
2974 case 24:
2975 aif1 |= 0x40;
2976 break;
2977 case 32:
2978 aif1 |= 0x60;
2979 break;
2980 default:
2981 return -EINVAL;
2982 }
2983
2984 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2985 }
2986
2987 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2988 {
2989 struct snd_soc_codec *codec = codec_dai->codec;
2990 int mute_reg;
2991 int reg;
2992
2993 switch (codec_dai->id) {
2994 case 1:
2995 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2996 break;
2997 case 2:
2998 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2999 break;
3000 default:
3001 return -EINVAL;
3002 }
3003
3004 if (mute)
3005 reg = WM8994_AIF1DAC1_MUTE;
3006 else
3007 reg = 0;
3008
3009 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
3010
3011 return 0;
3012 }
3013
3014 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
3015 {
3016 struct snd_soc_codec *codec = codec_dai->codec;
3017 int reg, val, mask;
3018
3019 switch (codec_dai->id) {
3020 case 1:
3021 reg = WM8994_AIF1_MASTER_SLAVE;
3022 mask = WM8994_AIF1_TRI;
3023 break;
3024 case 2:
3025 reg = WM8994_AIF2_MASTER_SLAVE;
3026 mask = WM8994_AIF2_TRI;
3027 break;
3028 default:
3029 return -EINVAL;
3030 }
3031
3032 if (tristate)
3033 val = mask;
3034 else
3035 val = 0;
3036
3037 return snd_soc_update_bits(codec, reg, mask, val);
3038 }
3039
3040 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
3041 {
3042 struct snd_soc_codec *codec = dai->codec;
3043
3044 /* Disable the pulls on the AIF if we're using it to save power. */
3045 snd_soc_update_bits(codec, WM8994_GPIO_3,
3046 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3047 snd_soc_update_bits(codec, WM8994_GPIO_4,
3048 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3049 snd_soc_update_bits(codec, WM8994_GPIO_5,
3050 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3051
3052 return 0;
3053 }
3054
3055 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
3056
3057 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3058 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
3059
3060 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
3061 .set_sysclk = wm8994_set_dai_sysclk,
3062 .set_fmt = wm8994_set_dai_fmt,
3063 .hw_params = wm8994_hw_params,
3064 .digital_mute = wm8994_aif_mute,
3065 .set_pll = wm8994_set_fll,
3066 .set_tristate = wm8994_set_tristate,
3067 };
3068
3069 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
3070 .set_sysclk = wm8994_set_dai_sysclk,
3071 .set_fmt = wm8994_set_dai_fmt,
3072 .hw_params = wm8994_hw_params,
3073 .digital_mute = wm8994_aif_mute,
3074 .set_pll = wm8994_set_fll,
3075 .set_tristate = wm8994_set_tristate,
3076 };
3077
3078 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
3079 .hw_params = wm8994_aif3_hw_params,
3080 };
3081
3082 static struct snd_soc_dai_driver wm8994_dai[] = {
3083 {
3084 .name = "wm8994-aif1",
3085 .id = 1,
3086 .playback = {
3087 .stream_name = "AIF1 Playback",
3088 .channels_min = 1,
3089 .channels_max = 2,
3090 .rates = WM8994_RATES,
3091 .formats = WM8994_FORMATS,
3092 .sig_bits = 24,
3093 },
3094 .capture = {
3095 .stream_name = "AIF1 Capture",
3096 .channels_min = 1,
3097 .channels_max = 2,
3098 .rates = WM8994_RATES,
3099 .formats = WM8994_FORMATS,
3100 .sig_bits = 24,
3101 },
3102 .ops = &wm8994_aif1_dai_ops,
3103 },
3104 {
3105 .name = "wm8994-aif2",
3106 .id = 2,
3107 .playback = {
3108 .stream_name = "AIF2 Playback",
3109 .channels_min = 1,
3110 .channels_max = 2,
3111 .rates = WM8994_RATES,
3112 .formats = WM8994_FORMATS,
3113 .sig_bits = 24,
3114 },
3115 .capture = {
3116 .stream_name = "AIF2 Capture",
3117 .channels_min = 1,
3118 .channels_max = 2,
3119 .rates = WM8994_RATES,
3120 .formats = WM8994_FORMATS,
3121 .sig_bits = 24,
3122 },
3123 .probe = wm8994_aif2_probe,
3124 .ops = &wm8994_aif2_dai_ops,
3125 },
3126 {
3127 .name = "wm8994-aif3",
3128 .id = 3,
3129 .playback = {
3130 .stream_name = "AIF3 Playback",
3131 .channels_min = 1,
3132 .channels_max = 2,
3133 .rates = WM8994_RATES,
3134 .formats = WM8994_FORMATS,
3135 .sig_bits = 24,
3136 },
3137 .capture = {
3138 .stream_name = "AIF3 Capture",
3139 .channels_min = 1,
3140 .channels_max = 2,
3141 .rates = WM8994_RATES,
3142 .formats = WM8994_FORMATS,
3143 .sig_bits = 24,
3144 },
3145 .ops = &wm8994_aif3_dai_ops,
3146 }
3147 };
3148
3149 #ifdef CONFIG_PM
3150 static int wm8994_codec_suspend(struct snd_soc_codec *codec)
3151 {
3152 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3153 int i, ret;
3154
3155 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3156 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
3157 sizeof(struct wm8994_fll_config));
3158 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
3159 if (ret < 0)
3160 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
3161 i + 1, ret);
3162 }
3163
3164 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
3165
3166 return 0;
3167 }
3168
3169 static int wm8994_codec_resume(struct snd_soc_codec *codec)
3170 {
3171 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3172 int i, ret;
3173
3174 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3175 if (!wm8994->fll_suspend[i].out)
3176 continue;
3177
3178 ret = _wm8994_set_fll(codec, i + 1,
3179 wm8994->fll_suspend[i].src,
3180 wm8994->fll_suspend[i].in,
3181 wm8994->fll_suspend[i].out);
3182 if (ret < 0)
3183 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
3184 i + 1, ret);
3185 }
3186
3187 return 0;
3188 }
3189 #else
3190 #define wm8994_codec_suspend NULL
3191 #define wm8994_codec_resume NULL
3192 #endif
3193
3194 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3195 {
3196 struct snd_soc_codec *codec = wm8994->hubs.codec;
3197 struct wm8994 *control = wm8994->wm8994;
3198 struct wm8994_pdata *pdata = &control->pdata;
3199 struct snd_kcontrol_new controls[] = {
3200 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3201 wm8994->retune_mobile_enum,
3202 wm8994_get_retune_mobile_enum,
3203 wm8994_put_retune_mobile_enum),
3204 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3205 wm8994->retune_mobile_enum,
3206 wm8994_get_retune_mobile_enum,
3207 wm8994_put_retune_mobile_enum),
3208 SOC_ENUM_EXT("AIF2 EQ Mode",
3209 wm8994->retune_mobile_enum,
3210 wm8994_get_retune_mobile_enum,
3211 wm8994_put_retune_mobile_enum),
3212 };
3213 int ret, i, j;
3214 const char **t;
3215
3216 /* We need an array of texts for the enum API but the number
3217 * of texts is likely to be less than the number of
3218 * configurations due to the sample rate dependency of the
3219 * configurations. */
3220 wm8994->num_retune_mobile_texts = 0;
3221 wm8994->retune_mobile_texts = NULL;
3222 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3223 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3224 if (strcmp(pdata->retune_mobile_cfgs[i].name,
3225 wm8994->retune_mobile_texts[j]) == 0)
3226 break;
3227 }
3228
3229 if (j != wm8994->num_retune_mobile_texts)
3230 continue;
3231
3232 /* Expand the array... */
3233 t = krealloc(wm8994->retune_mobile_texts,
3234 sizeof(char *) *
3235 (wm8994->num_retune_mobile_texts + 1),
3236 GFP_KERNEL);
3237 if (t == NULL)
3238 continue;
3239
3240 /* ...store the new entry... */
3241 t[wm8994->num_retune_mobile_texts] =
3242 pdata->retune_mobile_cfgs[i].name;
3243
3244 /* ...and remember the new version. */
3245 wm8994->num_retune_mobile_texts++;
3246 wm8994->retune_mobile_texts = t;
3247 }
3248
3249 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3250 wm8994->num_retune_mobile_texts);
3251
3252 wm8994->retune_mobile_enum.items = wm8994->num_retune_mobile_texts;
3253 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3254
3255 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3256 ARRAY_SIZE(controls));
3257 if (ret != 0)
3258 dev_err(wm8994->hubs.codec->dev,
3259 "Failed to add ReTune Mobile controls: %d\n", ret);
3260 }
3261
3262 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3263 {
3264 struct snd_soc_codec *codec = wm8994->hubs.codec;
3265 struct wm8994 *control = wm8994->wm8994;
3266 struct wm8994_pdata *pdata = &control->pdata;
3267 int ret, i;
3268
3269 if (!pdata)
3270 return;
3271
3272 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3273 pdata->lineout2_diff,
3274 pdata->lineout1fb,
3275 pdata->lineout2fb,
3276 pdata->jd_scthr,
3277 pdata->jd_thr,
3278 pdata->micb1_delay,
3279 pdata->micb2_delay,
3280 pdata->micbias1_lvl,
3281 pdata->micbias2_lvl);
3282
3283 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3284
3285 if (pdata->num_drc_cfgs) {
3286 struct snd_kcontrol_new controls[] = {
3287 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3288 wm8994_get_drc_enum, wm8994_put_drc_enum),
3289 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3290 wm8994_get_drc_enum, wm8994_put_drc_enum),
3291 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3292 wm8994_get_drc_enum, wm8994_put_drc_enum),
3293 };
3294
3295 /* We need an array of texts for the enum API */
3296 wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev,
3297 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
3298 if (!wm8994->drc_texts)
3299 return;
3300
3301 for (i = 0; i < pdata->num_drc_cfgs; i++)
3302 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3303
3304 wm8994->drc_enum.items = pdata->num_drc_cfgs;
3305 wm8994->drc_enum.texts = wm8994->drc_texts;
3306
3307 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3308 ARRAY_SIZE(controls));
3309 for (i = 0; i < WM8994_NUM_DRC; i++)
3310 wm8994_set_drc(codec, i);
3311 } else {
3312 ret = snd_soc_add_codec_controls(wm8994->hubs.codec,
3313 wm8994_drc_controls,
3314 ARRAY_SIZE(wm8994_drc_controls));
3315 }
3316
3317 if (ret != 0)
3318 dev_err(wm8994->hubs.codec->dev,
3319 "Failed to add DRC mode controls: %d\n", ret);
3320
3321
3322 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3323 pdata->num_retune_mobile_cfgs);
3324
3325 if (pdata->num_retune_mobile_cfgs)
3326 wm8994_handle_retune_mobile_pdata(wm8994);
3327 else
3328 snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls,
3329 ARRAY_SIZE(wm8994_eq_controls));
3330
3331 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3332 if (pdata->micbias[i]) {
3333 snd_soc_write(codec, WM8958_MICBIAS1 + i,
3334 pdata->micbias[i] & 0xffff);
3335 }
3336 }
3337 }
3338
3339 /**
3340 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3341 *
3342 * @codec: WM8994 codec
3343 * @jack: jack to report detection events on
3344 * @micbias: microphone bias to detect on
3345 *
3346 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3347 * being used to bring out signals to the processor then only platform
3348 * data configuration is needed for WM8994 and processor GPIOs should
3349 * be configured using snd_soc_jack_add_gpios() instead.
3350 *
3351 * Configuration of detection levels is available via the micbias1_lvl
3352 * and micbias2_lvl platform data members.
3353 */
3354 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3355 int micbias)
3356 {
3357 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3358 struct wm8994_micdet *micdet;
3359 struct wm8994 *control = wm8994->wm8994;
3360 int reg, ret;
3361
3362 if (control->type != WM8994) {
3363 dev_warn(codec->dev, "Not a WM8994\n");
3364 return -EINVAL;
3365 }
3366
3367 switch (micbias) {
3368 case 1:
3369 micdet = &wm8994->micdet[0];
3370 if (jack)
3371 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3372 "MICBIAS1");
3373 else
3374 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3375 "MICBIAS1");
3376 break;
3377 case 2:
3378 micdet = &wm8994->micdet[1];
3379 if (jack)
3380 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3381 "MICBIAS1");
3382 else
3383 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3384 "MICBIAS1");
3385 break;
3386 default:
3387 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
3388 return -EINVAL;
3389 }
3390
3391 if (ret != 0)
3392 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3393 micbias, ret);
3394
3395 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3396 micbias, jack);
3397
3398 /* Store the configuration */
3399 micdet->jack = jack;
3400 micdet->detecting = true;
3401
3402 /* If either of the jacks is set up then enable detection */
3403 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3404 reg = WM8994_MICD_ENA;
3405 else
3406 reg = 0;
3407
3408 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3409
3410 /* enable MICDET and MICSHRT deboune */
3411 snd_soc_update_bits(codec, WM8994_IRQ_DEBOUNCE,
3412 WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK |
3413 WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK,
3414 WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB);
3415
3416 snd_soc_dapm_sync(&codec->dapm);
3417
3418 return 0;
3419 }
3420 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3421
3422 static void wm8994_mic_work(struct work_struct *work)
3423 {
3424 struct wm8994_priv *priv = container_of(work,
3425 struct wm8994_priv,
3426 mic_work.work);
3427 struct regmap *regmap = priv->wm8994->regmap;
3428 struct device *dev = priv->wm8994->dev;
3429 unsigned int reg;
3430 int ret;
3431 int report;
3432
3433 pm_runtime_get_sync(dev);
3434
3435 ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, &reg);
3436 if (ret < 0) {
3437 dev_err(dev, "Failed to read microphone status: %d\n",
3438 ret);
3439 pm_runtime_put(dev);
3440 return;
3441 }
3442
3443 dev_dbg(dev, "Microphone status: %x\n", reg);
3444
3445 report = 0;
3446 if (reg & WM8994_MIC1_DET_STS) {
3447 if (priv->micdet[0].detecting)
3448 report = SND_JACK_HEADSET;
3449 }
3450 if (reg & WM8994_MIC1_SHRT_STS) {
3451 if (priv->micdet[0].detecting)
3452 report = SND_JACK_HEADPHONE;
3453 else
3454 report |= SND_JACK_BTN_0;
3455 }
3456 if (report)
3457 priv->micdet[0].detecting = false;
3458 else
3459 priv->micdet[0].detecting = true;
3460
3461 snd_soc_jack_report(priv->micdet[0].jack, report,
3462 SND_JACK_HEADSET | SND_JACK_BTN_0);
3463
3464 report = 0;
3465 if (reg & WM8994_MIC2_DET_STS) {
3466 if (priv->micdet[1].detecting)
3467 report = SND_JACK_HEADSET;
3468 }
3469 if (reg & WM8994_MIC2_SHRT_STS) {
3470 if (priv->micdet[1].detecting)
3471 report = SND_JACK_HEADPHONE;
3472 else
3473 report |= SND_JACK_BTN_0;
3474 }
3475 if (report)
3476 priv->micdet[1].detecting = false;
3477 else
3478 priv->micdet[1].detecting = true;
3479
3480 snd_soc_jack_report(priv->micdet[1].jack, report,
3481 SND_JACK_HEADSET | SND_JACK_BTN_0);
3482
3483 pm_runtime_put(dev);
3484 }
3485
3486 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3487 {
3488 struct wm8994_priv *priv = data;
3489 struct snd_soc_codec *codec = priv->hubs.codec;
3490
3491 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3492 trace_snd_soc_jack_irq(dev_name(codec->dev));
3493 #endif
3494
3495 pm_wakeup_event(codec->dev, 300);
3496
3497 queue_delayed_work(system_power_efficient_wq,
3498 &priv->mic_work, msecs_to_jiffies(250));
3499
3500 return IRQ_HANDLED;
3501 }
3502
3503 /* Should be called with accdet_lock held */
3504 static void wm1811_micd_stop(struct snd_soc_codec *codec)
3505 {
3506 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3507
3508 if (!wm8994->jackdet)
3509 return;
3510
3511 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0);
3512
3513 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3514
3515 if (wm8994->wm8994->pdata.jd_ext_cap)
3516 snd_soc_dapm_disable_pin(&codec->dapm,
3517 "MICBIAS2");
3518 }
3519
3520 static void wm8958_button_det(struct snd_soc_codec *codec, u16 status)
3521 {
3522 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3523 int report;
3524
3525 report = 0;
3526 if (status & 0x4)
3527 report |= SND_JACK_BTN_0;
3528
3529 if (status & 0x8)
3530 report |= SND_JACK_BTN_1;
3531
3532 if (status & 0x10)
3533 report |= SND_JACK_BTN_2;
3534
3535 if (status & 0x20)
3536 report |= SND_JACK_BTN_3;
3537
3538 if (status & 0x40)
3539 report |= SND_JACK_BTN_4;
3540
3541 if (status & 0x80)
3542 report |= SND_JACK_BTN_5;
3543
3544 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3545 wm8994->btn_mask);
3546 }
3547
3548 static void wm8958_open_circuit_work(struct work_struct *work)
3549 {
3550 struct wm8994_priv *wm8994 = container_of(work,
3551 struct wm8994_priv,
3552 open_circuit_work.work);
3553 struct device *dev = wm8994->wm8994->dev;
3554
3555 mutex_lock(&wm8994->accdet_lock);
3556
3557 wm1811_micd_stop(wm8994->hubs.codec);
3558
3559 dev_dbg(dev, "Reporting open circuit\n");
3560
3561 wm8994->jack_mic = false;
3562 wm8994->mic_detecting = true;
3563
3564 wm8958_micd_set_rate(wm8994->hubs.codec);
3565
3566 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3567 wm8994->btn_mask |
3568 SND_JACK_HEADSET);
3569
3570 mutex_unlock(&wm8994->accdet_lock);
3571 }
3572
3573 static void wm8958_mic_id(void *data, u16 status)
3574 {
3575 struct snd_soc_codec *codec = data;
3576 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3577
3578 /* Either nothing present or just starting detection */
3579 if (!(status & WM8958_MICD_STS)) {
3580 /* If nothing present then clear our statuses */
3581 dev_dbg(codec->dev, "Detected open circuit\n");
3582
3583 queue_delayed_work(system_power_efficient_wq,
3584 &wm8994->open_circuit_work,
3585 msecs_to_jiffies(2500));
3586 return;
3587 }
3588
3589 /* If the measurement is showing a high impedence we've got a
3590 * microphone.
3591 */
3592 if (status & 0x600) {
3593 dev_dbg(codec->dev, "Detected microphone\n");
3594
3595 wm8994->mic_detecting = false;
3596 wm8994->jack_mic = true;
3597
3598 wm8958_micd_set_rate(codec);
3599
3600 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3601 SND_JACK_HEADSET);
3602 }
3603
3604
3605 if (status & 0xfc) {
3606 dev_dbg(codec->dev, "Detected headphone\n");
3607 wm8994->mic_detecting = false;
3608
3609 wm8958_micd_set_rate(codec);
3610
3611 /* If we have jackdet that will detect removal */
3612 wm1811_micd_stop(codec);
3613
3614 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3615 SND_JACK_HEADSET);
3616 }
3617 }
3618
3619 /* Deferred mic detection to allow for extra settling time */
3620 static void wm1811_mic_work(struct work_struct *work)
3621 {
3622 struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv,
3623 mic_work.work);
3624 struct wm8994 *control = wm8994->wm8994;
3625 struct snd_soc_codec *codec = wm8994->hubs.codec;
3626
3627 pm_runtime_get_sync(codec->dev);
3628
3629 /* If required for an external cap force MICBIAS on */
3630 if (control->pdata.jd_ext_cap) {
3631 snd_soc_dapm_force_enable_pin(&codec->dapm,
3632 "MICBIAS2");
3633 snd_soc_dapm_sync(&codec->dapm);
3634 }
3635
3636 mutex_lock(&wm8994->accdet_lock);
3637
3638 dev_dbg(codec->dev, "Starting mic detection\n");
3639
3640 /* Use a user-supplied callback if we have one */
3641 if (wm8994->micd_cb) {
3642 wm8994->micd_cb(wm8994->micd_cb_data);
3643 } else {
3644 /*
3645 * Start off measument of microphone impedence to find out
3646 * what's actually there.
3647 */
3648 wm8994->mic_detecting = true;
3649 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3650
3651 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3652 WM8958_MICD_ENA, WM8958_MICD_ENA);
3653 }
3654
3655 mutex_unlock(&wm8994->accdet_lock);
3656
3657 pm_runtime_put(codec->dev);
3658 }
3659
3660 static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3661 {
3662 struct wm8994_priv *wm8994 = data;
3663 struct wm8994 *control = wm8994->wm8994;
3664 struct snd_soc_codec *codec = wm8994->hubs.codec;
3665 int reg, delay;
3666 bool present;
3667
3668 pm_runtime_get_sync(codec->dev);
3669
3670 cancel_delayed_work_sync(&wm8994->mic_complete_work);
3671
3672 mutex_lock(&wm8994->accdet_lock);
3673
3674 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3675 if (reg < 0) {
3676 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3677 mutex_unlock(&wm8994->accdet_lock);
3678 pm_runtime_put(codec->dev);
3679 return IRQ_NONE;
3680 }
3681
3682 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3683
3684 present = reg & WM1811_JACKDET_LVL;
3685
3686 if (present) {
3687 dev_dbg(codec->dev, "Jack detected\n");
3688
3689 wm8958_micd_set_rate(codec);
3690
3691 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3692 WM8958_MICB2_DISCH, 0);
3693
3694 /* Disable debounce while inserted */
3695 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3696 WM1811_JACKDET_DB, 0);
3697
3698 delay = control->pdata.micdet_delay;
3699 queue_delayed_work(system_power_efficient_wq,
3700 &wm8994->mic_work,
3701 msecs_to_jiffies(delay));
3702 } else {
3703 dev_dbg(codec->dev, "Jack not detected\n");
3704
3705 cancel_delayed_work_sync(&wm8994->mic_work);
3706
3707 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3708 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3709
3710 /* Enable debounce while removed */
3711 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3712 WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3713
3714 wm8994->mic_detecting = false;
3715 wm8994->jack_mic = false;
3716 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3717 WM8958_MICD_ENA, 0);
3718 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3719 }
3720
3721 mutex_unlock(&wm8994->accdet_lock);
3722
3723 /* Turn off MICBIAS if it was on for an external cap */
3724 if (control->pdata.jd_ext_cap && !present)
3725 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
3726
3727 if (present)
3728 snd_soc_jack_report(wm8994->micdet[0].jack,
3729 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3730 else
3731 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3732 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3733 wm8994->btn_mask);
3734
3735 /* Since we only report deltas force an update, ensures we
3736 * avoid bootstrapping issues with the core. */
3737 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0);
3738
3739 pm_runtime_put(codec->dev);
3740 return IRQ_HANDLED;
3741 }
3742
3743 static void wm1811_jackdet_bootstrap(struct work_struct *work)
3744 {
3745 struct wm8994_priv *wm8994 = container_of(work,
3746 struct wm8994_priv,
3747 jackdet_bootstrap.work);
3748 wm1811_jackdet_irq(0, wm8994);
3749 }
3750
3751 /**
3752 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3753 *
3754 * @codec: WM8958 codec
3755 * @jack: jack to report detection events on
3756 *
3757 * Enable microphone detection functionality for the WM8958. By
3758 * default simple detection which supports the detection of up to 6
3759 * buttons plus video and microphone functionality is supported.
3760 *
3761 * The WM8958 has an advanced jack detection facility which is able to
3762 * support complex accessory detection, especially when used in
3763 * conjunction with external circuitry. In order to provide maximum
3764 * flexiblity a callback is provided which allows a completely custom
3765 * detection algorithm.
3766 */
3767 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3768 wm1811_micdet_cb det_cb, void *det_cb_data,
3769 wm1811_mic_id_cb id_cb, void *id_cb_data)
3770 {
3771 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3772 struct wm8994 *control = wm8994->wm8994;
3773 u16 micd_lvl_sel;
3774
3775 switch (control->type) {
3776 case WM1811:
3777 case WM8958:
3778 break;
3779 default:
3780 return -EINVAL;
3781 }
3782
3783 if (jack) {
3784 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3785 snd_soc_dapm_sync(&codec->dapm);
3786
3787 wm8994->micdet[0].jack = jack;
3788
3789 if (det_cb) {
3790 wm8994->micd_cb = det_cb;
3791 wm8994->micd_cb_data = det_cb_data;
3792 } else {
3793 wm8994->mic_detecting = true;
3794 wm8994->jack_mic = false;
3795 }
3796
3797 if (id_cb) {
3798 wm8994->mic_id_cb = id_cb;
3799 wm8994->mic_id_cb_data = id_cb_data;
3800 } else {
3801 wm8994->mic_id_cb = wm8958_mic_id;
3802 wm8994->mic_id_cb_data = codec;
3803 }
3804
3805 wm8958_micd_set_rate(codec);
3806
3807 /* Detect microphones and short circuits by default */
3808 if (control->pdata.micd_lvl_sel)
3809 micd_lvl_sel = control->pdata.micd_lvl_sel;
3810 else
3811 micd_lvl_sel = 0x41;
3812
3813 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3814 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3815 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3816
3817 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
3818 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3819
3820 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3821
3822 /*
3823 * If we can use jack detection start off with that,
3824 * otherwise jump straight to microphone detection.
3825 */
3826 if (wm8994->jackdet) {
3827 /* Disable debounce for the initial detect */
3828 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3829 WM1811_JACKDET_DB, 0);
3830
3831 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3832 WM8958_MICB2_DISCH,
3833 WM8958_MICB2_DISCH);
3834 snd_soc_update_bits(codec, WM8994_LDO_1,
3835 WM8994_LDO1_DISCH, 0);
3836 wm1811_jackdet_set_mode(codec,
3837 WM1811_JACKDET_MODE_JACK);
3838 } else {
3839 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3840 WM8958_MICD_ENA, WM8958_MICD_ENA);
3841 }
3842
3843 } else {
3844 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3845 WM8958_MICD_ENA, 0);
3846 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
3847 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
3848 snd_soc_dapm_sync(&codec->dapm);
3849 }
3850
3851 return 0;
3852 }
3853 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3854
3855 static void wm8958_mic_work(struct work_struct *work)
3856 {
3857 struct wm8994_priv *wm8994 = container_of(work,
3858 struct wm8994_priv,
3859 mic_complete_work.work);
3860 struct snd_soc_codec *codec = wm8994->hubs.codec;
3861
3862 pm_runtime_get_sync(codec->dev);
3863
3864 mutex_lock(&wm8994->accdet_lock);
3865
3866 wm8994->mic_id_cb(wm8994->mic_id_cb_data, wm8994->mic_status);
3867
3868 mutex_unlock(&wm8994->accdet_lock);
3869
3870 pm_runtime_put(codec->dev);
3871 }
3872
3873 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3874 {
3875 struct wm8994_priv *wm8994 = data;
3876 struct snd_soc_codec *codec = wm8994->hubs.codec;
3877 int reg, count, ret, id_delay;
3878
3879 /*
3880 * Jack detection may have detected a removal simulataneously
3881 * with an update of the MICDET status; if so it will have
3882 * stopped detection and we can ignore this interrupt.
3883 */
3884 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
3885 return IRQ_HANDLED;
3886
3887 cancel_delayed_work_sync(&wm8994->mic_complete_work);
3888 cancel_delayed_work_sync(&wm8994->open_circuit_work);
3889
3890 pm_runtime_get_sync(codec->dev);
3891
3892 /* We may occasionally read a detection without an impedence
3893 * range being provided - if that happens loop again.
3894 */
3895 count = 10;
3896 do {
3897 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3898 if (reg < 0) {
3899 dev_err(codec->dev,
3900 "Failed to read mic detect status: %d\n",
3901 reg);
3902 pm_runtime_put(codec->dev);
3903 return IRQ_NONE;
3904 }
3905
3906 if (!(reg & WM8958_MICD_VALID)) {
3907 dev_dbg(codec->dev, "Mic detect data not valid\n");
3908 goto out;
3909 }
3910
3911 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3912 break;
3913
3914 msleep(1);
3915 } while (count--);
3916
3917 if (count == 0)
3918 dev_warn(codec->dev, "No impedance range reported for jack\n");
3919
3920 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3921 trace_snd_soc_jack_irq(dev_name(codec->dev));
3922 #endif
3923
3924 /* Avoid a transient report when the accessory is being removed */
3925 if (wm8994->jackdet) {
3926 ret = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3927 if (ret < 0) {
3928 dev_err(codec->dev, "Failed to read jack status: %d\n",
3929 ret);
3930 } else if (!(ret & WM1811_JACKDET_LVL)) {
3931 dev_dbg(codec->dev, "Ignoring removed jack\n");
3932 goto out;
3933 }
3934 } else if (!(reg & WM8958_MICD_STS)) {
3935 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3936 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3937 wm8994->btn_mask);
3938 wm8994->mic_detecting = true;
3939 goto out;
3940 }
3941
3942 wm8994->mic_status = reg;
3943 id_delay = wm8994->wm8994->pdata.mic_id_delay;
3944
3945 if (wm8994->mic_detecting)
3946 queue_delayed_work(system_power_efficient_wq,
3947 &wm8994->mic_complete_work,
3948 msecs_to_jiffies(id_delay));
3949 else
3950 wm8958_button_det(codec, reg);
3951
3952 out:
3953 pm_runtime_put(codec->dev);
3954 return IRQ_HANDLED;
3955 }
3956
3957 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3958 {
3959 struct snd_soc_codec *codec = data;
3960
3961 dev_err(codec->dev, "FIFO error\n");
3962
3963 return IRQ_HANDLED;
3964 }
3965
3966 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3967 {
3968 struct snd_soc_codec *codec = data;
3969
3970 dev_err(codec->dev, "Thermal warning\n");
3971
3972 return IRQ_HANDLED;
3973 }
3974
3975 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3976 {
3977 struct snd_soc_codec *codec = data;
3978
3979 dev_crit(codec->dev, "Thermal shutdown\n");
3980
3981 return IRQ_HANDLED;
3982 }
3983
3984 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3985 {
3986 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
3987 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3988 struct snd_soc_dapm_context *dapm = &codec->dapm;
3989 unsigned int reg;
3990 int ret, i;
3991
3992 wm8994->hubs.codec = codec;
3993
3994 mutex_init(&wm8994->accdet_lock);
3995 INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
3996 wm1811_jackdet_bootstrap);
3997 INIT_DELAYED_WORK(&wm8994->open_circuit_work,
3998 wm8958_open_circuit_work);
3999
4000 switch (control->type) {
4001 case WM8994:
4002 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
4003 break;
4004 case WM1811:
4005 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work);
4006 break;
4007 default:
4008 break;
4009 }
4010
4011 INIT_DELAYED_WORK(&wm8994->mic_complete_work, wm8958_mic_work);
4012
4013 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4014 init_completion(&wm8994->fll_locked[i]);
4015
4016 wm8994->micdet_irq = control->pdata.micdet_irq;
4017
4018 /* By default use idle_bias_off, will override for WM8994 */
4019 codec->dapm.idle_bias_off = 1;
4020
4021 /* Set revision-specific configuration */
4022 switch (control->type) {
4023 case WM8994:
4024 /* Single ended line outputs should have VMID on. */
4025 if (!control->pdata.lineout1_diff ||
4026 !control->pdata.lineout2_diff)
4027 codec->dapm.idle_bias_off = 0;
4028
4029 switch (control->revision) {
4030 case 2:
4031 case 3:
4032 wm8994->hubs.dcs_codes_l = -5;
4033 wm8994->hubs.dcs_codes_r = -5;
4034 wm8994->hubs.hp_startup_mode = 1;
4035 wm8994->hubs.dcs_readback_mode = 1;
4036 wm8994->hubs.series_startup = 1;
4037 break;
4038 default:
4039 wm8994->hubs.dcs_readback_mode = 2;
4040 break;
4041 }
4042 break;
4043
4044 case WM8958:
4045 wm8994->hubs.dcs_readback_mode = 1;
4046 wm8994->hubs.hp_startup_mode = 1;
4047
4048 switch (control->revision) {
4049 case 0:
4050 break;
4051 default:
4052 wm8994->fll_byp = true;
4053 break;
4054 }
4055 break;
4056
4057 case WM1811:
4058 wm8994->hubs.dcs_readback_mode = 2;
4059 wm8994->hubs.no_series_update = 1;
4060 wm8994->hubs.hp_startup_mode = 1;
4061 wm8994->hubs.no_cache_dac_hp_direct = true;
4062 wm8994->fll_byp = true;
4063
4064 wm8994->hubs.dcs_codes_l = -9;
4065 wm8994->hubs.dcs_codes_r = -7;
4066
4067 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
4068 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
4069 break;
4070
4071 default:
4072 break;
4073 }
4074
4075 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
4076 wm8994_fifo_error, "FIFO error", codec);
4077 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
4078 wm8994_temp_warn, "Thermal warning", codec);
4079 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
4080 wm8994_temp_shut, "Thermal shutdown", codec);
4081
4082 switch (control->type) {
4083 case WM8994:
4084 if (wm8994->micdet_irq)
4085 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4086 wm8994_mic_irq,
4087 IRQF_TRIGGER_RISING,
4088 "Mic1 detect",
4089 wm8994);
4090 else
4091 ret = wm8994_request_irq(wm8994->wm8994,
4092 WM8994_IRQ_MIC1_DET,
4093 wm8994_mic_irq, "Mic 1 detect",
4094 wm8994);
4095
4096 if (ret != 0)
4097 dev_warn(codec->dev,
4098 "Failed to request Mic1 detect IRQ: %d\n",
4099 ret);
4100
4101
4102 ret = wm8994_request_irq(wm8994->wm8994,
4103 WM8994_IRQ_MIC1_SHRT,
4104 wm8994_mic_irq, "Mic 1 short",
4105 wm8994);
4106 if (ret != 0)
4107 dev_warn(codec->dev,
4108 "Failed to request Mic1 short IRQ: %d\n",
4109 ret);
4110
4111 ret = wm8994_request_irq(wm8994->wm8994,
4112 WM8994_IRQ_MIC2_DET,
4113 wm8994_mic_irq, "Mic 2 detect",
4114 wm8994);
4115 if (ret != 0)
4116 dev_warn(codec->dev,
4117 "Failed to request Mic2 detect IRQ: %d\n",
4118 ret);
4119
4120 ret = wm8994_request_irq(wm8994->wm8994,
4121 WM8994_IRQ_MIC2_SHRT,
4122 wm8994_mic_irq, "Mic 2 short",
4123 wm8994);
4124 if (ret != 0)
4125 dev_warn(codec->dev,
4126 "Failed to request Mic2 short IRQ: %d\n",
4127 ret);
4128 break;
4129
4130 case WM8958:
4131 case WM1811:
4132 if (wm8994->micdet_irq) {
4133 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4134 wm8958_mic_irq,
4135 IRQF_TRIGGER_RISING,
4136 "Mic detect",
4137 wm8994);
4138 if (ret != 0)
4139 dev_warn(codec->dev,
4140 "Failed to request Mic detect IRQ: %d\n",
4141 ret);
4142 } else {
4143 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4144 wm8958_mic_irq, "Mic detect",
4145 wm8994);
4146 }
4147 }
4148
4149 switch (control->type) {
4150 case WM1811:
4151 if (control->cust_id > 1 || control->revision > 1) {
4152 ret = wm8994_request_irq(wm8994->wm8994,
4153 WM8994_IRQ_GPIO(6),
4154 wm1811_jackdet_irq, "JACKDET",
4155 wm8994);
4156 if (ret == 0)
4157 wm8994->jackdet = true;
4158 }
4159 break;
4160 default:
4161 break;
4162 }
4163
4164 wm8994->fll_locked_irq = true;
4165 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
4166 ret = wm8994_request_irq(wm8994->wm8994,
4167 WM8994_IRQ_FLL1_LOCK + i,
4168 wm8994_fll_locked_irq, "FLL lock",
4169 &wm8994->fll_locked[i]);
4170 if (ret != 0)
4171 wm8994->fll_locked_irq = false;
4172 }
4173
4174 /* Make sure we can read from the GPIOs if they're inputs */
4175 pm_runtime_get_sync(codec->dev);
4176
4177 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
4178 * configured on init - if a system wants to do this dynamically
4179 * at runtime we can deal with that then.
4180 */
4181 ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
4182 if (ret < 0) {
4183 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
4184 goto err_irq;
4185 }
4186 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4187 wm8994->lrclk_shared[0] = 1;
4188 wm8994_dai[0].symmetric_rates = 1;
4189 } else {
4190 wm8994->lrclk_shared[0] = 0;
4191 }
4192
4193 ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
4194 if (ret < 0) {
4195 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
4196 goto err_irq;
4197 }
4198 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4199 wm8994->lrclk_shared[1] = 1;
4200 wm8994_dai[1].symmetric_rates = 1;
4201 } else {
4202 wm8994->lrclk_shared[1] = 0;
4203 }
4204
4205 pm_runtime_put(codec->dev);
4206
4207 /* Latch volume update bits */
4208 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
4209 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg,
4210 wm8994_vu_bits[i].mask,
4211 wm8994_vu_bits[i].mask);
4212
4213 /* Set the low bit of the 3D stereo depth so TLV matches */
4214 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
4215 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
4216 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
4217 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
4218 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
4219 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
4220 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
4221 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
4222 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
4223
4224 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
4225 * use this; it only affects behaviour on idle TDM clock
4226 * cycles. */
4227 switch (control->type) {
4228 case WM8994:
4229 case WM8958:
4230 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
4231 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
4232 break;
4233 default:
4234 break;
4235 }
4236
4237 /* Put MICBIAS into bypass mode by default on newer devices */
4238 switch (control->type) {
4239 case WM8958:
4240 case WM1811:
4241 snd_soc_update_bits(codec, WM8958_MICBIAS1,
4242 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
4243 snd_soc_update_bits(codec, WM8958_MICBIAS2,
4244 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
4245 break;
4246 default:
4247 break;
4248 }
4249
4250 wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
4251 wm_hubs_update_class_w(codec);
4252
4253 wm8994_handle_pdata(wm8994);
4254
4255 wm_hubs_add_analogue_controls(codec);
4256 snd_soc_add_codec_controls(codec, wm8994_snd_controls,
4257 ARRAY_SIZE(wm8994_snd_controls));
4258 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
4259 ARRAY_SIZE(wm8994_dapm_widgets));
4260
4261 switch (control->type) {
4262 case WM8994:
4263 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
4264 ARRAY_SIZE(wm8994_specific_dapm_widgets));
4265 if (control->revision < 4) {
4266 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4267 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4268 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4269 ARRAY_SIZE(wm8994_adc_revd_widgets));
4270 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4271 ARRAY_SIZE(wm8994_dac_revd_widgets));
4272 } else {
4273 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4274 ARRAY_SIZE(wm8994_lateclk_widgets));
4275 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4276 ARRAY_SIZE(wm8994_adc_widgets));
4277 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4278 ARRAY_SIZE(wm8994_dac_widgets));
4279 }
4280 break;
4281 case WM8958:
4282 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4283 ARRAY_SIZE(wm8958_snd_controls));
4284 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4285 ARRAY_SIZE(wm8958_dapm_widgets));
4286 if (control->revision < 1) {
4287 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4288 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4289 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4290 ARRAY_SIZE(wm8994_adc_revd_widgets));
4291 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4292 ARRAY_SIZE(wm8994_dac_revd_widgets));
4293 } else {
4294 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4295 ARRAY_SIZE(wm8994_lateclk_widgets));
4296 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4297 ARRAY_SIZE(wm8994_adc_widgets));
4298 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4299 ARRAY_SIZE(wm8994_dac_widgets));
4300 }
4301 break;
4302
4303 case WM1811:
4304 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4305 ARRAY_SIZE(wm8958_snd_controls));
4306 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4307 ARRAY_SIZE(wm8958_dapm_widgets));
4308 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4309 ARRAY_SIZE(wm8994_lateclk_widgets));
4310 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4311 ARRAY_SIZE(wm8994_adc_widgets));
4312 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4313 ARRAY_SIZE(wm8994_dac_widgets));
4314 break;
4315 }
4316
4317 wm_hubs_add_analogue_routes(codec, 0, 0);
4318 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4319 wm_hubs_dcs_done, "DC servo done",
4320 &wm8994->hubs);
4321 if (ret == 0)
4322 wm8994->hubs.dcs_done_irq = true;
4323 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
4324
4325 switch (control->type) {
4326 case WM8994:
4327 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4328 ARRAY_SIZE(wm8994_intercon));
4329
4330 if (control->revision < 4) {
4331 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4332 ARRAY_SIZE(wm8994_revd_intercon));
4333 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4334 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4335 } else {
4336 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4337 ARRAY_SIZE(wm8994_lateclk_intercon));
4338 }
4339 break;
4340 case WM8958:
4341 if (control->revision < 1) {
4342 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4343 ARRAY_SIZE(wm8994_intercon));
4344 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4345 ARRAY_SIZE(wm8994_revd_intercon));
4346 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4347 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4348 } else {
4349 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4350 ARRAY_SIZE(wm8994_lateclk_intercon));
4351 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4352 ARRAY_SIZE(wm8958_intercon));
4353 }
4354
4355 wm8958_dsp2_init(codec);
4356 break;
4357 case WM1811:
4358 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4359 ARRAY_SIZE(wm8994_lateclk_intercon));
4360 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4361 ARRAY_SIZE(wm8958_intercon));
4362 break;
4363 }
4364
4365 return 0;
4366
4367 err_irq:
4368 if (wm8994->jackdet)
4369 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4370 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4371 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4372 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
4373 if (wm8994->micdet_irq)
4374 free_irq(wm8994->micdet_irq, wm8994);
4375 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4376 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4377 &wm8994->fll_locked[i]);
4378 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4379 &wm8994->hubs);
4380 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4381 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4382 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4383
4384 return ret;
4385 }
4386
4387 static int wm8994_codec_remove(struct snd_soc_codec *codec)
4388 {
4389 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4390 struct wm8994 *control = wm8994->wm8994;
4391 int i;
4392
4393 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4394 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4395 &wm8994->fll_locked[i]);
4396
4397 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4398 &wm8994->hubs);
4399 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4400 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4401 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4402
4403 if (wm8994->jackdet)
4404 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4405
4406 switch (control->type) {
4407 case WM8994:
4408 if (wm8994->micdet_irq)
4409 free_irq(wm8994->micdet_irq, wm8994);
4410 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
4411 wm8994);
4412 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
4413 wm8994);
4414 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4415 wm8994);
4416 break;
4417
4418 case WM1811:
4419 case WM8958:
4420 if (wm8994->micdet_irq)
4421 free_irq(wm8994->micdet_irq, wm8994);
4422 break;
4423 }
4424 release_firmware(wm8994->mbc);
4425 release_firmware(wm8994->mbc_vss);
4426 release_firmware(wm8994->enh_eq);
4427 kfree(wm8994->retune_mobile_texts);
4428 return 0;
4429 }
4430
4431 static struct regmap *wm8994_get_regmap(struct device *dev)
4432 {
4433 struct wm8994 *control = dev_get_drvdata(dev->parent);
4434
4435 return control->regmap;
4436 }
4437
4438 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4439 .probe = wm8994_codec_probe,
4440 .remove = wm8994_codec_remove,
4441 .suspend = wm8994_codec_suspend,
4442 .resume = wm8994_codec_resume,
4443 .get_regmap = wm8994_get_regmap,
4444 .set_bias_level = wm8994_set_bias_level,
4445 };
4446
4447 static int wm8994_probe(struct platform_device *pdev)
4448 {
4449 struct wm8994_priv *wm8994;
4450
4451 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4452 GFP_KERNEL);
4453 if (wm8994 == NULL)
4454 return -ENOMEM;
4455 platform_set_drvdata(pdev, wm8994);
4456
4457 mutex_init(&wm8994->fw_lock);
4458
4459 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
4460
4461 pm_runtime_enable(&pdev->dev);
4462 pm_runtime_idle(&pdev->dev);
4463
4464 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4465 wm8994_dai, ARRAY_SIZE(wm8994_dai));
4466 }
4467
4468 static int wm8994_remove(struct platform_device *pdev)
4469 {
4470 snd_soc_unregister_codec(&pdev->dev);
4471 pm_runtime_disable(&pdev->dev);
4472
4473 return 0;
4474 }
4475
4476 #ifdef CONFIG_PM_SLEEP
4477 static int wm8994_suspend(struct device *dev)
4478 {
4479 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4480
4481 /* Drop down to power saving mode when system is suspended */
4482 if (wm8994->jackdet && !wm8994->active_refcount)
4483 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4484 WM1811_JACKDET_MODE_MASK,
4485 wm8994->jackdet_mode);
4486
4487 return 0;
4488 }
4489
4490 static int wm8994_resume(struct device *dev)
4491 {
4492 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4493
4494 if (wm8994->jackdet && wm8994->jackdet_mode)
4495 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4496 WM1811_JACKDET_MODE_MASK,
4497 WM1811_JACKDET_MODE_AUDIO);
4498
4499 return 0;
4500 }
4501 #endif
4502
4503 static const struct dev_pm_ops wm8994_pm_ops = {
4504 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4505 };
4506
4507 static struct platform_driver wm8994_codec_driver = {
4508 .driver = {
4509 .name = "wm8994-codec",
4510 .pm = &wm8994_pm_ops,
4511 },
4512 .probe = wm8994_probe,
4513 .remove = wm8994_remove,
4514 };
4515
4516 module_platform_driver(wm8994_codec_driver);
4517
4518 MODULE_DESCRIPTION("ASoC WM8994 driver");
4519 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4520 MODULE_LICENSE("GPL");
4521 MODULE_ALIAS("platform:wm8994-codec");
Linux kernel - Deliverables
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