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ASoC: wm8994: Delete trailing whitespace from sound/soc/codecs/wm8994.c
[deliverable/linux.git] / sound / soc / codecs / wm8994.c
1 /*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/jack.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <trace/events/asoc.h>
32
33 #include <linux/mfd/wm8994/core.h>
34 #include <linux/mfd/wm8994/registers.h>
35 #include <linux/mfd/wm8994/pdata.h>
36 #include <linux/mfd/wm8994/gpio.h>
37
38 #include "wm8994.h"
39 #include "wm_hubs.h"
40
41 #define WM1811_JACKDET_MODE_NONE 0x0000
42 #define WM1811_JACKDET_MODE_JACK 0x0100
43 #define WM1811_JACKDET_MODE_MIC 0x0080
44 #define WM1811_JACKDET_MODE_AUDIO 0x0180
45
46 #define WM8994_NUM_DRC 3
47 #define WM8994_NUM_EQ 3
48
49 static int wm8994_drc_base[] = {
50 WM8994_AIF1_DRC1_1,
51 WM8994_AIF1_DRC2_1,
52 WM8994_AIF2_DRC_1,
53 };
54
55 static int wm8994_retune_mobile_base[] = {
56 WM8994_AIF1_DAC1_EQ_GAINS_1,
57 WM8994_AIF1_DAC2_EQ_GAINS_1,
58 WM8994_AIF2_EQ_GAINS_1,
59 };
60
61 static void wm8958_default_micdet(u16 status, void *data);
62
63 static const struct wm8958_micd_rate micdet_rates[] = {
64 { 32768, true, 1, 4 },
65 { 32768, false, 1, 1 },
66 { 44100 * 256, true, 7, 10 },
67 { 44100 * 256, false, 7, 10 },
68 };
69
70 static const struct wm8958_micd_rate jackdet_rates[] = {
71 { 32768, true, 0, 1 },
72 { 32768, false, 0, 1 },
73 { 44100 * 256, true, 7, 10 },
74 { 44100 * 256, false, 7, 10 },
75 };
76
77 static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
78 {
79 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
80 int best, i, sysclk, val;
81 bool idle;
82 const struct wm8958_micd_rate *rates;
83 int num_rates;
84
85 if (wm8994->jack_cb != wm8958_default_micdet)
86 return;
87
88 idle = !wm8994->jack_mic;
89
90 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
91 if (sysclk & WM8994_SYSCLK_SRC)
92 sysclk = wm8994->aifclk[1];
93 else
94 sysclk = wm8994->aifclk[0];
95
96 if (wm8994->pdata && wm8994->pdata->micd_rates) {
97 rates = wm8994->pdata->micd_rates;
98 num_rates = wm8994->pdata->num_micd_rates;
99 } else if (wm8994->jackdet) {
100 rates = jackdet_rates;
101 num_rates = ARRAY_SIZE(jackdet_rates);
102 } else {
103 rates = micdet_rates;
104 num_rates = ARRAY_SIZE(micdet_rates);
105 }
106
107 best = 0;
108 for (i = 0; i < num_rates; i++) {
109 if (rates[i].idle != idle)
110 continue;
111 if (abs(rates[i].sysclk - sysclk) <
112 abs(rates[best].sysclk - sysclk))
113 best = i;
114 else if (rates[best].idle != idle)
115 best = i;
116 }
117
118 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
119 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
120
121 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
122 WM8958_MICD_BIAS_STARTTIME_MASK |
123 WM8958_MICD_RATE_MASK, val);
124 }
125
126 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
127 {
128 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
129 int rate;
130 int reg1 = 0;
131 int offset;
132
133 if (aif)
134 offset = 4;
135 else
136 offset = 0;
137
138 switch (wm8994->sysclk[aif]) {
139 case WM8994_SYSCLK_MCLK1:
140 rate = wm8994->mclk[0];
141 break;
142
143 case WM8994_SYSCLK_MCLK2:
144 reg1 |= 0x8;
145 rate = wm8994->mclk[1];
146 break;
147
148 case WM8994_SYSCLK_FLL1:
149 reg1 |= 0x10;
150 rate = wm8994->fll[0].out;
151 break;
152
153 case WM8994_SYSCLK_FLL2:
154 reg1 |= 0x18;
155 rate = wm8994->fll[1].out;
156 break;
157
158 default:
159 return -EINVAL;
160 }
161
162 if (rate >= 13500000) {
163 rate /= 2;
164 reg1 |= WM8994_AIF1CLK_DIV;
165
166 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
167 aif + 1, rate);
168 }
169
170 wm8994->aifclk[aif] = rate;
171
172 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
173 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
174 reg1);
175
176 return 0;
177 }
178
179 static int configure_clock(struct snd_soc_codec *codec)
180 {
181 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
182 int change, new;
183
184 /* Bring up the AIF clocks first */
185 configure_aif_clock(codec, 0);
186 configure_aif_clock(codec, 1);
187
188 /* Then switch CLK_SYS over to the higher of them; a change
189 * can only happen as a result of a clocking change which can
190 * only be made outside of DAPM so we can safely redo the
191 * clocking.
192 */
193
194 /* If they're equal it doesn't matter which is used */
195 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
196 wm8958_micd_set_rate(codec);
197 return 0;
198 }
199
200 if (wm8994->aifclk[0] < wm8994->aifclk[1])
201 new = WM8994_SYSCLK_SRC;
202 else
203 new = 0;
204
205 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
206 WM8994_SYSCLK_SRC, new);
207 if (change)
208 snd_soc_dapm_sync(&codec->dapm);
209
210 wm8958_micd_set_rate(codec);
211
212 return 0;
213 }
214
215 static int check_clk_sys(struct snd_soc_dapm_widget *source,
216 struct snd_soc_dapm_widget *sink)
217 {
218 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
219 const char *clk;
220
221 /* Check what we're currently using for CLK_SYS */
222 if (reg & WM8994_SYSCLK_SRC)
223 clk = "AIF2CLK";
224 else
225 clk = "AIF1CLK";
226
227 return strcmp(source->name, clk) == 0;
228 }
229
230 static const char *sidetone_hpf_text[] = {
231 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
232 };
233
234 static const struct soc_enum sidetone_hpf =
235 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
236
237 static const char *adc_hpf_text[] = {
238 "HiFi", "Voice 1", "Voice 2", "Voice 3"
239 };
240
241 static const struct soc_enum aif1adc1_hpf =
242 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
243
244 static const struct soc_enum aif1adc2_hpf =
245 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
246
247 static const struct soc_enum aif2adc_hpf =
248 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
249
250 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
251 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
252 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
253 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
254 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
255 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
256 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
257
258 #define WM8994_DRC_SWITCH(xname, reg, shift) \
259 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
260 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
261 .put = wm8994_put_drc_sw, \
262 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
263
264 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
265 struct snd_ctl_elem_value *ucontrol)
266 {
267 struct soc_mixer_control *mc =
268 (struct soc_mixer_control *)kcontrol->private_value;
269 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
270 int mask, ret;
271
272 /* Can't enable both ADC and DAC paths simultaneously */
273 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
274 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
275 WM8994_AIF1ADC1R_DRC_ENA_MASK;
276 else
277 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
278
279 ret = snd_soc_read(codec, mc->reg);
280 if (ret < 0)
281 return ret;
282 if (ret & mask)
283 return -EINVAL;
284
285 return snd_soc_put_volsw(kcontrol, ucontrol);
286 }
287
288 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
289 {
290 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
291 struct wm8994_pdata *pdata = wm8994->pdata;
292 int base = wm8994_drc_base[drc];
293 int cfg = wm8994->drc_cfg[drc];
294 int save, i;
295
296 /* Save any enables; the configuration should clear them. */
297 save = snd_soc_read(codec, base);
298 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
299 WM8994_AIF1ADC1R_DRC_ENA;
300
301 for (i = 0; i < WM8994_DRC_REGS; i++)
302 snd_soc_update_bits(codec, base + i, 0xffff,
303 pdata->drc_cfgs[cfg].regs[i]);
304
305 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
306 WM8994_AIF1ADC1L_DRC_ENA |
307 WM8994_AIF1ADC1R_DRC_ENA, save);
308 }
309
310 /* Icky as hell but saves code duplication */
311 static int wm8994_get_drc(const char *name)
312 {
313 if (strcmp(name, "AIF1DRC1 Mode") == 0)
314 return 0;
315 if (strcmp(name, "AIF1DRC2 Mode") == 0)
316 return 1;
317 if (strcmp(name, "AIF2DRC Mode") == 0)
318 return 2;
319 return -EINVAL;
320 }
321
322 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
323 struct snd_ctl_elem_value *ucontrol)
324 {
325 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
326 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
327 struct wm8994_pdata *pdata = wm8994->pdata;
328 int drc = wm8994_get_drc(kcontrol->id.name);
329 int value = ucontrol->value.integer.value[0];
330
331 if (drc < 0)
332 return drc;
333
334 if (value >= pdata->num_drc_cfgs)
335 return -EINVAL;
336
337 wm8994->drc_cfg[drc] = value;
338
339 wm8994_set_drc(codec, drc);
340
341 return 0;
342 }
343
344 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
345 struct snd_ctl_elem_value *ucontrol)
346 {
347 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
348 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
349 int drc = wm8994_get_drc(kcontrol->id.name);
350
351 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
352
353 return 0;
354 }
355
356 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
357 {
358 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
359 struct wm8994_pdata *pdata = wm8994->pdata;
360 int base = wm8994_retune_mobile_base[block];
361 int iface, best, best_val, save, i, cfg;
362
363 if (!pdata || !wm8994->num_retune_mobile_texts)
364 return;
365
366 switch (block) {
367 case 0:
368 case 1:
369 iface = 0;
370 break;
371 case 2:
372 iface = 1;
373 break;
374 default:
375 return;
376 }
377
378 /* Find the version of the currently selected configuration
379 * with the nearest sample rate. */
380 cfg = wm8994->retune_mobile_cfg[block];
381 best = 0;
382 best_val = INT_MAX;
383 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
384 if (strcmp(pdata->retune_mobile_cfgs[i].name,
385 wm8994->retune_mobile_texts[cfg]) == 0 &&
386 abs(pdata->retune_mobile_cfgs[i].rate
387 - wm8994->dac_rates[iface]) < best_val) {
388 best = i;
389 best_val = abs(pdata->retune_mobile_cfgs[i].rate
390 - wm8994->dac_rates[iface]);
391 }
392 }
393
394 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
395 block,
396 pdata->retune_mobile_cfgs[best].name,
397 pdata->retune_mobile_cfgs[best].rate,
398 wm8994->dac_rates[iface]);
399
400 /* The EQ will be disabled while reconfiguring it, remember the
401 * current configuration.
402 */
403 save = snd_soc_read(codec, base);
404 save &= WM8994_AIF1DAC1_EQ_ENA;
405
406 for (i = 0; i < WM8994_EQ_REGS; i++)
407 snd_soc_update_bits(codec, base + i, 0xffff,
408 pdata->retune_mobile_cfgs[best].regs[i]);
409
410 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
411 }
412
413 /* Icky as hell but saves code duplication */
414 static int wm8994_get_retune_mobile_block(const char *name)
415 {
416 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
417 return 0;
418 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
419 return 1;
420 if (strcmp(name, "AIF2 EQ Mode") == 0)
421 return 2;
422 return -EINVAL;
423 }
424
425 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
426 struct snd_ctl_elem_value *ucontrol)
427 {
428 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
429 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
430 struct wm8994_pdata *pdata = wm8994->pdata;
431 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
432 int value = ucontrol->value.integer.value[0];
433
434 if (block < 0)
435 return block;
436
437 if (value >= pdata->num_retune_mobile_cfgs)
438 return -EINVAL;
439
440 wm8994->retune_mobile_cfg[block] = value;
441
442 wm8994_set_retune_mobile(codec, block);
443
444 return 0;
445 }
446
447 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
448 struct snd_ctl_elem_value *ucontrol)
449 {
450 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
451 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
452 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
453
454 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
455
456 return 0;
457 }
458
459 static const char *aif_chan_src_text[] = {
460 "Left", "Right"
461 };
462
463 static const struct soc_enum aif1adcl_src =
464 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
465
466 static const struct soc_enum aif1adcr_src =
467 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
468
469 static const struct soc_enum aif2adcl_src =
470 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
471
472 static const struct soc_enum aif2adcr_src =
473 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
474
475 static const struct soc_enum aif1dacl_src =
476 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
477
478 static const struct soc_enum aif1dacr_src =
479 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
480
481 static const struct soc_enum aif2dacl_src =
482 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
483
484 static const struct soc_enum aif2dacr_src =
485 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
486
487 static const char *osr_text[] = {
488 "Low Power", "High Performance",
489 };
490
491 static const struct soc_enum dac_osr =
492 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
493
494 static const struct soc_enum adc_osr =
495 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
496
497 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
498 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
499 WM8994_AIF1_ADC1_RIGHT_VOLUME,
500 1, 119, 0, digital_tlv),
501 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
502 WM8994_AIF1_ADC2_RIGHT_VOLUME,
503 1, 119, 0, digital_tlv),
504 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
505 WM8994_AIF2_ADC_RIGHT_VOLUME,
506 1, 119, 0, digital_tlv),
507
508 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
509 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
510 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
511 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
512
513 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
514 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
515 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
516 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
517
518 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
519 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
520 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
521 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
522 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
523 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
524
525 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
526 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
527
528 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
529 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
530 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
531
532 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
533 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
534 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
535
536 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
537 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
538 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
539
540 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
541 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
542 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
543
544 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
545 5, 12, 0, st_tlv),
546 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
547 0, 12, 0, st_tlv),
548 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
549 5, 12, 0, st_tlv),
550 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
551 0, 12, 0, st_tlv),
552 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
553 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
554
555 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
556 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
557
558 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
559 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
560
561 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
562 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
563
564 SOC_ENUM("ADC OSR", adc_osr),
565 SOC_ENUM("DAC OSR", dac_osr),
566
567 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
568 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
569 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
570 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
571
572 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
573 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
574 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
575 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
576
577 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
578 6, 1, 1, wm_hubs_spkmix_tlv),
579 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
580 2, 1, 1, wm_hubs_spkmix_tlv),
581
582 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
583 6, 1, 1, wm_hubs_spkmix_tlv),
584 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
585 2, 1, 1, wm_hubs_spkmix_tlv),
586
587 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
588 10, 15, 0, wm8994_3d_tlv),
589 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
590 8, 1, 0),
591 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
592 10, 15, 0, wm8994_3d_tlv),
593 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
594 8, 1, 0),
595 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
596 10, 15, 0, wm8994_3d_tlv),
597 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
598 8, 1, 0),
599 };
600
601 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
602 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
603 eq_tlv),
604 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
605 eq_tlv),
606 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
607 eq_tlv),
608 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
609 eq_tlv),
610 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
611 eq_tlv),
612
613 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
614 eq_tlv),
615 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
616 eq_tlv),
617 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
618 eq_tlv),
619 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
620 eq_tlv),
621 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
622 eq_tlv),
623
624 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
625 eq_tlv),
626 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
627 eq_tlv),
628 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
629 eq_tlv),
630 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
631 eq_tlv),
632 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
633 eq_tlv),
634 };
635
636 static const char *wm8958_ng_text[] = {
637 "30ms", "125ms", "250ms", "500ms",
638 };
639
640 static const struct soc_enum wm8958_aif1dac1_ng_hold =
641 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
642 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
643
644 static const struct soc_enum wm8958_aif1dac2_ng_hold =
645 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
646 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
647
648 static const struct soc_enum wm8958_aif2dac_ng_hold =
649 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
650 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
651
652 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
653 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
654
655 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
656 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
657 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
658 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
659 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
660 7, 1, ng_tlv),
661
662 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
663 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
664 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
665 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
666 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
667 7, 1, ng_tlv),
668
669 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
670 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
671 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
672 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
673 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
674 7, 1, ng_tlv),
675 };
676
677 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
678 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
679 mixin_boost_tlv),
680 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
681 mixin_boost_tlv),
682 };
683
684 /* We run all mode setting through a function to enforce audio mode */
685 static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
686 {
687 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
688
689 if (!wm8994->jackdet || !wm8994->jack_cb)
690 return;
691
692 if (!wm8994->jackdet || !wm8994->jack_cb)
693 return;
694
695 if (wm8994->active_refcount)
696 mode = WM1811_JACKDET_MODE_AUDIO;
697
698 if (mode == wm8994->jackdet_mode)
699 return;
700
701 wm8994->jackdet_mode = mode;
702
703 /* Always use audio mode to detect while the system is active */
704 if (mode != WM1811_JACKDET_MODE_NONE)
705 mode = WM1811_JACKDET_MODE_AUDIO;
706
707 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
708 WM1811_JACKDET_MODE_MASK, mode);
709 }
710
711 static void active_reference(struct snd_soc_codec *codec)
712 {
713 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
714
715 mutex_lock(&wm8994->accdet_lock);
716
717 wm8994->active_refcount++;
718
719 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
720 wm8994->active_refcount);
721
722 /* If we're using jack detection go into audio mode */
723 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
724
725 mutex_unlock(&wm8994->accdet_lock);
726 }
727
728 static void active_dereference(struct snd_soc_codec *codec)
729 {
730 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
731 u16 mode;
732
733 mutex_lock(&wm8994->accdet_lock);
734
735 wm8994->active_refcount--;
736
737 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
738 wm8994->active_refcount);
739
740 if (wm8994->active_refcount == 0) {
741 /* Go into appropriate detection only mode */
742 if (wm8994->jack_mic || wm8994->mic_detecting)
743 mode = WM1811_JACKDET_MODE_MIC;
744 else
745 mode = WM1811_JACKDET_MODE_JACK;
746
747 wm1811_jackdet_set_mode(codec, mode);
748 }
749
750 mutex_unlock(&wm8994->accdet_lock);
751 }
752
753 static int clk_sys_event(struct snd_soc_dapm_widget *w,
754 struct snd_kcontrol *kcontrol, int event)
755 {
756 struct snd_soc_codec *codec = w->codec;
757
758 switch (event) {
759 case SND_SOC_DAPM_PRE_PMU:
760 return configure_clock(codec);
761
762 case SND_SOC_DAPM_POST_PMD:
763 configure_clock(codec);
764 break;
765 }
766
767 return 0;
768 }
769
770 static void vmid_reference(struct snd_soc_codec *codec)
771 {
772 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
773
774 pm_runtime_get_sync(codec->dev);
775
776 wm8994->vmid_refcount++;
777
778 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
779 wm8994->vmid_refcount);
780
781 if (wm8994->vmid_refcount == 1) {
782 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
783 WM8994_LINEOUT1_DISCH |
784 WM8994_LINEOUT2_DISCH, 0);
785
786 wm_hubs_vmid_ena(codec);
787
788 switch (wm8994->vmid_mode) {
789 default:
790 WARN_ON(0 == "Invalid VMID mode");
791 case WM8994_VMID_NORMAL:
792 /* Startup bias, VMID ramp & buffer */
793 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
794 WM8994_BIAS_SRC |
795 WM8994_VMID_DISCH |
796 WM8994_STARTUP_BIAS_ENA |
797 WM8994_VMID_BUF_ENA |
798 WM8994_VMID_RAMP_MASK,
799 WM8994_BIAS_SRC |
800 WM8994_STARTUP_BIAS_ENA |
801 WM8994_VMID_BUF_ENA |
802 (0x3 << WM8994_VMID_RAMP_SHIFT));
803
804 /* Main bias enable, VMID=2x40k */
805 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
806 WM8994_BIAS_ENA |
807 WM8994_VMID_SEL_MASK,
808 WM8994_BIAS_ENA | 0x2);
809
810 msleep(50);
811
812 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
813 WM8994_VMID_RAMP_MASK |
814 WM8994_BIAS_SRC,
815 0);
816 break;
817
818 case WM8994_VMID_FORCE:
819 /* Startup bias, slow VMID ramp & buffer */
820 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
821 WM8994_BIAS_SRC |
822 WM8994_VMID_DISCH |
823 WM8994_STARTUP_BIAS_ENA |
824 WM8994_VMID_BUF_ENA |
825 WM8994_VMID_RAMP_MASK,
826 WM8994_BIAS_SRC |
827 WM8994_STARTUP_BIAS_ENA |
828 WM8994_VMID_BUF_ENA |
829 (0x2 << WM8994_VMID_RAMP_SHIFT));
830
831 /* Main bias enable, VMID=2x40k */
832 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
833 WM8994_BIAS_ENA |
834 WM8994_VMID_SEL_MASK,
835 WM8994_BIAS_ENA | 0x2);
836
837 msleep(400);
838
839 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
840 WM8994_VMID_RAMP_MASK |
841 WM8994_BIAS_SRC,
842 0);
843 break;
844 }
845 }
846 }
847
848 static void vmid_dereference(struct snd_soc_codec *codec)
849 {
850 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
851
852 wm8994->vmid_refcount--;
853
854 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
855 wm8994->vmid_refcount);
856
857 if (wm8994->vmid_refcount == 0) {
858 if (wm8994->hubs.lineout1_se)
859 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
860 WM8994_LINEOUT1N_ENA |
861 WM8994_LINEOUT1P_ENA,
862 WM8994_LINEOUT1N_ENA |
863 WM8994_LINEOUT1P_ENA);
864
865 if (wm8994->hubs.lineout2_se)
866 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
867 WM8994_LINEOUT2N_ENA |
868 WM8994_LINEOUT2P_ENA,
869 WM8994_LINEOUT2N_ENA |
870 WM8994_LINEOUT2P_ENA);
871
872 /* Start discharging VMID */
873 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
874 WM8994_BIAS_SRC |
875 WM8994_VMID_DISCH,
876 WM8994_BIAS_SRC |
877 WM8994_VMID_DISCH);
878
879 switch (wm8994->vmid_mode) {
880 case WM8994_VMID_FORCE:
881 msleep(350);
882 break;
883 default:
884 break;
885 }
886
887 snd_soc_update_bits(codec, WM8994_ADDITIONAL_CONTROL,
888 WM8994_VROI, WM8994_VROI);
889
890 /* Active discharge */
891 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
892 WM8994_LINEOUT1_DISCH |
893 WM8994_LINEOUT2_DISCH,
894 WM8994_LINEOUT1_DISCH |
895 WM8994_LINEOUT2_DISCH);
896
897 msleep(150);
898
899 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
900 WM8994_LINEOUT1N_ENA |
901 WM8994_LINEOUT1P_ENA |
902 WM8994_LINEOUT2N_ENA |
903 WM8994_LINEOUT2P_ENA, 0);
904
905 snd_soc_update_bits(codec, WM8994_ADDITIONAL_CONTROL,
906 WM8994_VROI, 0);
907
908 /* Switch off startup biases */
909 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
910 WM8994_BIAS_SRC |
911 WM8994_STARTUP_BIAS_ENA |
912 WM8994_VMID_BUF_ENA |
913 WM8994_VMID_RAMP_MASK, 0);
914
915 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
916 WM8994_BIAS_ENA | WM8994_VMID_SEL_MASK, 0);
917
918 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
919 WM8994_VMID_RAMP_MASK, 0);
920 }
921
922 pm_runtime_put(codec->dev);
923 }
924
925 static int vmid_event(struct snd_soc_dapm_widget *w,
926 struct snd_kcontrol *kcontrol, int event)
927 {
928 struct snd_soc_codec *codec = w->codec;
929
930 switch (event) {
931 case SND_SOC_DAPM_PRE_PMU:
932 vmid_reference(codec);
933 break;
934
935 case SND_SOC_DAPM_POST_PMD:
936 vmid_dereference(codec);
937 break;
938 }
939
940 return 0;
941 }
942
943 static void wm8994_update_class_w(struct snd_soc_codec *codec)
944 {
945 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
946 int enable = 1;
947 int source = 0; /* GCC flow analysis can't track enable */
948 int reg, reg_r;
949
950 /* Only support direct DAC->headphone paths */
951 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
952 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
953 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
954 enable = 0;
955 }
956
957 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
958 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
959 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
960 enable = 0;
961 }
962
963 /* We also need the same setting for L/R and only one path */
964 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
965 switch (reg) {
966 case WM8994_AIF2DACL_TO_DAC1L:
967 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
968 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
969 break;
970 case WM8994_AIF1DAC2L_TO_DAC1L:
971 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
972 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
973 break;
974 case WM8994_AIF1DAC1L_TO_DAC1L:
975 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
976 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
977 break;
978 default:
979 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
980 enable = 0;
981 break;
982 }
983
984 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
985 if (reg_r != reg) {
986 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
987 enable = 0;
988 }
989
990 if (enable) {
991 dev_dbg(codec->dev, "Class W enabled\n");
992 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
993 WM8994_CP_DYN_PWR |
994 WM8994_CP_DYN_SRC_SEL_MASK,
995 source | WM8994_CP_DYN_PWR);
996 wm8994->hubs.class_w = true;
997
998 } else {
999 dev_dbg(codec->dev, "Class W disabled\n");
1000 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1001 WM8994_CP_DYN_PWR, 0);
1002 wm8994->hubs.class_w = false;
1003 }
1004 }
1005
1006 static int late_enable_ev(struct snd_soc_dapm_widget *w,
1007 struct snd_kcontrol *kcontrol, int event)
1008 {
1009 struct snd_soc_codec *codec = w->codec;
1010 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1011
1012 switch (event) {
1013 case SND_SOC_DAPM_PRE_PMU:
1014 if (wm8994->aif1clk_enable) {
1015 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1016 WM8994_AIF1CLK_ENA_MASK,
1017 WM8994_AIF1CLK_ENA);
1018 wm8994->aif1clk_enable = 0;
1019 }
1020 if (wm8994->aif2clk_enable) {
1021 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1022 WM8994_AIF2CLK_ENA_MASK,
1023 WM8994_AIF2CLK_ENA);
1024 wm8994->aif2clk_enable = 0;
1025 }
1026 break;
1027 }
1028
1029 /* We may also have postponed startup of DSP, handle that. */
1030 wm8958_aif_ev(w, kcontrol, event);
1031
1032 return 0;
1033 }
1034
1035 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1036 struct snd_kcontrol *kcontrol, int event)
1037 {
1038 struct snd_soc_codec *codec = w->codec;
1039 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1040
1041 switch (event) {
1042 case SND_SOC_DAPM_POST_PMD:
1043 if (wm8994->aif1clk_disable) {
1044 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1045 WM8994_AIF1CLK_ENA_MASK, 0);
1046 wm8994->aif1clk_disable = 0;
1047 }
1048 if (wm8994->aif2clk_disable) {
1049 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1050 WM8994_AIF2CLK_ENA_MASK, 0);
1051 wm8994->aif2clk_disable = 0;
1052 }
1053 break;
1054 }
1055
1056 return 0;
1057 }
1058
1059 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1060 struct snd_kcontrol *kcontrol, int event)
1061 {
1062 struct snd_soc_codec *codec = w->codec;
1063 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1064
1065 switch (event) {
1066 case SND_SOC_DAPM_PRE_PMU:
1067 wm8994->aif1clk_enable = 1;
1068 break;
1069 case SND_SOC_DAPM_POST_PMD:
1070 wm8994->aif1clk_disable = 1;
1071 break;
1072 }
1073
1074 return 0;
1075 }
1076
1077 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1078 struct snd_kcontrol *kcontrol, int event)
1079 {
1080 struct snd_soc_codec *codec = w->codec;
1081 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1082
1083 switch (event) {
1084 case SND_SOC_DAPM_PRE_PMU:
1085 wm8994->aif2clk_enable = 1;
1086 break;
1087 case SND_SOC_DAPM_POST_PMD:
1088 wm8994->aif2clk_disable = 1;
1089 break;
1090 }
1091
1092 return 0;
1093 }
1094
1095 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1096 struct snd_kcontrol *kcontrol, int event)
1097 {
1098 late_enable_ev(w, kcontrol, event);
1099 return 0;
1100 }
1101
1102 static int micbias_ev(struct snd_soc_dapm_widget *w,
1103 struct snd_kcontrol *kcontrol, int event)
1104 {
1105 late_enable_ev(w, kcontrol, event);
1106 return 0;
1107 }
1108
1109 static int dac_ev(struct snd_soc_dapm_widget *w,
1110 struct snd_kcontrol *kcontrol, int event)
1111 {
1112 struct snd_soc_codec *codec = w->codec;
1113 unsigned int mask = 1 << w->shift;
1114
1115 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1116 mask, mask);
1117 return 0;
1118 }
1119
1120 static const char *hp_mux_text[] = {
1121 "Mixer",
1122 "DAC",
1123 };
1124
1125 #define WM8994_HP_ENUM(xname, xenum) \
1126 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1127 .info = snd_soc_info_enum_double, \
1128 .get = snd_soc_dapm_get_enum_double, \
1129 .put = wm8994_put_hp_enum, \
1130 .private_value = (unsigned long)&xenum }
1131
1132 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1133 struct snd_ctl_elem_value *ucontrol)
1134 {
1135 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1136 struct snd_soc_dapm_widget *w = wlist->widgets[0];
1137 struct snd_soc_codec *codec = w->codec;
1138 int ret;
1139
1140 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1141
1142 wm8994_update_class_w(codec);
1143
1144 return ret;
1145 }
1146
1147 static const struct soc_enum hpl_enum =
1148 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1149
1150 static const struct snd_kcontrol_new hpl_mux =
1151 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1152
1153 static const struct soc_enum hpr_enum =
1154 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1155
1156 static const struct snd_kcontrol_new hpr_mux =
1157 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1158
1159 static const char *adc_mux_text[] = {
1160 "ADC",
1161 "DMIC",
1162 };
1163
1164 static const struct soc_enum adc_enum =
1165 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1166
1167 static const struct snd_kcontrol_new adcl_mux =
1168 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1169
1170 static const struct snd_kcontrol_new adcr_mux =
1171 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1172
1173 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1174 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1175 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1176 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1177 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1178 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1179 };
1180
1181 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1182 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1183 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1184 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1185 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1186 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1187 };
1188
1189 /* Debugging; dump chip status after DAPM transitions */
1190 static int post_ev(struct snd_soc_dapm_widget *w,
1191 struct snd_kcontrol *kcontrol, int event)
1192 {
1193 struct snd_soc_codec *codec = w->codec;
1194 dev_dbg(codec->dev, "SRC status: %x\n",
1195 snd_soc_read(codec,
1196 WM8994_RATE_STATUS));
1197 return 0;
1198 }
1199
1200 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1201 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1202 1, 1, 0),
1203 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1204 0, 1, 0),
1205 };
1206
1207 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1208 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1209 1, 1, 0),
1210 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1211 0, 1, 0),
1212 };
1213
1214 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1215 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1216 1, 1, 0),
1217 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1218 0, 1, 0),
1219 };
1220
1221 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1222 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1223 1, 1, 0),
1224 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1225 0, 1, 0),
1226 };
1227
1228 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1229 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1230 5, 1, 0),
1231 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1232 4, 1, 0),
1233 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1234 2, 1, 0),
1235 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1236 1, 1, 0),
1237 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1238 0, 1, 0),
1239 };
1240
1241 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1242 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1243 5, 1, 0),
1244 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1245 4, 1, 0),
1246 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1247 2, 1, 0),
1248 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1249 1, 1, 0),
1250 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1251 0, 1, 0),
1252 };
1253
1254 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1255 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1256 .info = snd_soc_info_volsw, \
1257 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1258 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1259
1260 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1261 struct snd_ctl_elem_value *ucontrol)
1262 {
1263 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1264 struct snd_soc_dapm_widget *w = wlist->widgets[0];
1265 struct snd_soc_codec *codec = w->codec;
1266 int ret;
1267
1268 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1269
1270 wm8994_update_class_w(codec);
1271
1272 return ret;
1273 }
1274
1275 static const struct snd_kcontrol_new dac1l_mix[] = {
1276 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1277 5, 1, 0),
1278 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1279 4, 1, 0),
1280 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1281 2, 1, 0),
1282 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1283 1, 1, 0),
1284 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1285 0, 1, 0),
1286 };
1287
1288 static const struct snd_kcontrol_new dac1r_mix[] = {
1289 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1290 5, 1, 0),
1291 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1292 4, 1, 0),
1293 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1294 2, 1, 0),
1295 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1296 1, 1, 0),
1297 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1298 0, 1, 0),
1299 };
1300
1301 static const char *sidetone_text[] = {
1302 "ADC/DMIC1", "DMIC2",
1303 };
1304
1305 static const struct soc_enum sidetone1_enum =
1306 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1307
1308 static const struct snd_kcontrol_new sidetone1_mux =
1309 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1310
1311 static const struct soc_enum sidetone2_enum =
1312 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1313
1314 static const struct snd_kcontrol_new sidetone2_mux =
1315 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1316
1317 static const char *aif1dac_text[] = {
1318 "AIF1DACDAT", "AIF3DACDAT",
1319 };
1320
1321 static const struct soc_enum aif1dac_enum =
1322 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1323
1324 static const struct snd_kcontrol_new aif1dac_mux =
1325 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1326
1327 static const char *aif2dac_text[] = {
1328 "AIF2DACDAT", "AIF3DACDAT",
1329 };
1330
1331 static const struct soc_enum aif2dac_enum =
1332 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1333
1334 static const struct snd_kcontrol_new aif2dac_mux =
1335 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1336
1337 static const char *aif2adc_text[] = {
1338 "AIF2ADCDAT", "AIF3DACDAT",
1339 };
1340
1341 static const struct soc_enum aif2adc_enum =
1342 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1343
1344 static const struct snd_kcontrol_new aif2adc_mux =
1345 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1346
1347 static const char *aif3adc_text[] = {
1348 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1349 };
1350
1351 static const struct soc_enum wm8994_aif3adc_enum =
1352 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1353
1354 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1355 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1356
1357 static const struct soc_enum wm8958_aif3adc_enum =
1358 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1359
1360 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1361 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1362
1363 static const char *mono_pcm_out_text[] = {
1364 "None", "AIF2ADCL", "AIF2ADCR",
1365 };
1366
1367 static const struct soc_enum mono_pcm_out_enum =
1368 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1369
1370 static const struct snd_kcontrol_new mono_pcm_out_mux =
1371 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1372
1373 static const char *aif2dac_src_text[] = {
1374 "AIF2", "AIF3",
1375 };
1376
1377 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1378 static const struct soc_enum aif2dacl_src_enum =
1379 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1380
1381 static const struct snd_kcontrol_new aif2dacl_src_mux =
1382 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1383
1384 static const struct soc_enum aif2dacr_src_enum =
1385 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1386
1387 static const struct snd_kcontrol_new aif2dacr_src_mux =
1388 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1389
1390 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1391 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1392 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1393 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1394 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1395
1396 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1397 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1398 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1399 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1400 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1401 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1402 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1403 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1404 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1405 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1406
1407 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1408 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1409 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1410 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1411 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1412 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1413 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1414 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1415 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1416 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1417
1418 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1419 };
1420
1421 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1422 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1423 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1424 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1425 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1426 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1427 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1428 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1429 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1430 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1431 };
1432
1433 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1434 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1435 dac_ev, SND_SOC_DAPM_PRE_PMU),
1436 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1437 dac_ev, SND_SOC_DAPM_PRE_PMU),
1438 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1439 dac_ev, SND_SOC_DAPM_PRE_PMU),
1440 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1441 dac_ev, SND_SOC_DAPM_PRE_PMU),
1442 };
1443
1444 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1445 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1446 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1447 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1448 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1449 };
1450
1451 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1452 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1453 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1454 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1455 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1456 };
1457
1458 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1459 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1460 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1461 };
1462
1463 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1464 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1465 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1466 SND_SOC_DAPM_INPUT("Clock"),
1467
1468 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1469 SND_SOC_DAPM_PRE_PMU),
1470 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1471 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1472
1473 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1474 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1475
1476 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1477 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1478 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1479
1480 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1481 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1482 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1483 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
1484 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1485 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1486 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1487 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1488 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1489 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1490
1491 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1492 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1493 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1494 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
1495 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1496 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
1497 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1498 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1499 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1500 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1501
1502 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1503 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1504 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1505 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1506
1507 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1508 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1509 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1510 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1511
1512 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1513 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1514 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1515 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1516
1517 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1518 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1519
1520 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1521 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1522 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1523 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1524
1525 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1526 WM8994_POWER_MANAGEMENT_4, 13, 0),
1527 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1528 WM8994_POWER_MANAGEMENT_4, 12, 0),
1529 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1530 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1531 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1532 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1533 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1534 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1535
1536 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1537 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1538 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1539 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1540
1541 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1542 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1543 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1544
1545 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1546 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1547
1548 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1549
1550 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1551 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1552 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1553 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1554
1555 /* Power is done with the muxes since the ADC power also controls the
1556 * downsampling chain, the chip will automatically manage the analogue
1557 * specific portions.
1558 */
1559 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1560 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1561
1562 SND_SOC_DAPM_POST("Debug log", post_ev),
1563 };
1564
1565 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1566 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1567 };
1568
1569 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1570 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
1571 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1572 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1573 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1574 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1575 };
1576
1577 static const struct snd_soc_dapm_route intercon[] = {
1578 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1579 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1580
1581 { "DSP1CLK", NULL, "CLK_SYS" },
1582 { "DSP2CLK", NULL, "CLK_SYS" },
1583 { "DSPINTCLK", NULL, "CLK_SYS" },
1584
1585 { "AIF1ADC1L", NULL, "AIF1CLK" },
1586 { "AIF1ADC1L", NULL, "DSP1CLK" },
1587 { "AIF1ADC1R", NULL, "AIF1CLK" },
1588 { "AIF1ADC1R", NULL, "DSP1CLK" },
1589 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1590
1591 { "AIF1DAC1L", NULL, "AIF1CLK" },
1592 { "AIF1DAC1L", NULL, "DSP1CLK" },
1593 { "AIF1DAC1R", NULL, "AIF1CLK" },
1594 { "AIF1DAC1R", NULL, "DSP1CLK" },
1595 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1596
1597 { "AIF1ADC2L", NULL, "AIF1CLK" },
1598 { "AIF1ADC2L", NULL, "DSP1CLK" },
1599 { "AIF1ADC2R", NULL, "AIF1CLK" },
1600 { "AIF1ADC2R", NULL, "DSP1CLK" },
1601 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1602
1603 { "AIF1DAC2L", NULL, "AIF1CLK" },
1604 { "AIF1DAC2L", NULL, "DSP1CLK" },
1605 { "AIF1DAC2R", NULL, "AIF1CLK" },
1606 { "AIF1DAC2R", NULL, "DSP1CLK" },
1607 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1608
1609 { "AIF2ADCL", NULL, "AIF2CLK" },
1610 { "AIF2ADCL", NULL, "DSP2CLK" },
1611 { "AIF2ADCR", NULL, "AIF2CLK" },
1612 { "AIF2ADCR", NULL, "DSP2CLK" },
1613 { "AIF2ADCR", NULL, "DSPINTCLK" },
1614
1615 { "AIF2DACL", NULL, "AIF2CLK" },
1616 { "AIF2DACL", NULL, "DSP2CLK" },
1617 { "AIF2DACR", NULL, "AIF2CLK" },
1618 { "AIF2DACR", NULL, "DSP2CLK" },
1619 { "AIF2DACR", NULL, "DSPINTCLK" },
1620
1621 { "DMIC1L", NULL, "DMIC1DAT" },
1622 { "DMIC1L", NULL, "CLK_SYS" },
1623 { "DMIC1R", NULL, "DMIC1DAT" },
1624 { "DMIC1R", NULL, "CLK_SYS" },
1625 { "DMIC2L", NULL, "DMIC2DAT" },
1626 { "DMIC2L", NULL, "CLK_SYS" },
1627 { "DMIC2R", NULL, "DMIC2DAT" },
1628 { "DMIC2R", NULL, "CLK_SYS" },
1629
1630 { "ADCL", NULL, "AIF1CLK" },
1631 { "ADCL", NULL, "DSP1CLK" },
1632 { "ADCL", NULL, "DSPINTCLK" },
1633
1634 { "ADCR", NULL, "AIF1CLK" },
1635 { "ADCR", NULL, "DSP1CLK" },
1636 { "ADCR", NULL, "DSPINTCLK" },
1637
1638 { "ADCL Mux", "ADC", "ADCL" },
1639 { "ADCL Mux", "DMIC", "DMIC1L" },
1640 { "ADCR Mux", "ADC", "ADCR" },
1641 { "ADCR Mux", "DMIC", "DMIC1R" },
1642
1643 { "DAC1L", NULL, "AIF1CLK" },
1644 { "DAC1L", NULL, "DSP1CLK" },
1645 { "DAC1L", NULL, "DSPINTCLK" },
1646
1647 { "DAC1R", NULL, "AIF1CLK" },
1648 { "DAC1R", NULL, "DSP1CLK" },
1649 { "DAC1R", NULL, "DSPINTCLK" },
1650
1651 { "DAC2L", NULL, "AIF2CLK" },
1652 { "DAC2L", NULL, "DSP2CLK" },
1653 { "DAC2L", NULL, "DSPINTCLK" },
1654
1655 { "DAC2R", NULL, "AIF2DACR" },
1656 { "DAC2R", NULL, "AIF2CLK" },
1657 { "DAC2R", NULL, "DSP2CLK" },
1658 { "DAC2R", NULL, "DSPINTCLK" },
1659
1660 { "TOCLK", NULL, "CLK_SYS" },
1661
1662 { "AIF1DACDAT", NULL, "AIF1 Playback" },
1663 { "AIF2DACDAT", NULL, "AIF2 Playback" },
1664 { "AIF3DACDAT", NULL, "AIF3 Playback" },
1665
1666 { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1667 { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1668 { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1669
1670 /* AIF1 outputs */
1671 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1672 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1673 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1674
1675 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1676 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1677 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1678
1679 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1680 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1681 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1682
1683 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1684 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1685 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1686
1687 /* Pin level routing for AIF3 */
1688 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1689 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1690 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1691 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1692
1693 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1694 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1695 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1696 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1697 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1698 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1699 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1700
1701 /* DAC1 inputs */
1702 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1703 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1704 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1705 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1706 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1707
1708 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1709 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1710 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1711 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1712 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1713
1714 /* DAC2/AIF2 outputs */
1715 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1716 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1717 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1718 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1719 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1720 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1721
1722 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1723 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1724 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1725 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1726 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1727 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1728
1729 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1730 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1731 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1732 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1733
1734 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1735
1736 /* AIF3 output */
1737 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1738 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1739 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1740 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1741 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1742 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1743 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1744 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1745
1746 /* Sidetone */
1747 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1748 { "Left Sidetone", "DMIC2", "DMIC2L" },
1749 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1750 { "Right Sidetone", "DMIC2", "DMIC2R" },
1751
1752 /* Output stages */
1753 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1754 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1755
1756 { "SPKL", "DAC1 Switch", "DAC1L" },
1757 { "SPKL", "DAC2 Switch", "DAC2L" },
1758
1759 { "SPKR", "DAC1 Switch", "DAC1R" },
1760 { "SPKR", "DAC2 Switch", "DAC2R" },
1761
1762 { "Left Headphone Mux", "DAC", "DAC1L" },
1763 { "Right Headphone Mux", "DAC", "DAC1R" },
1764 };
1765
1766 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1767 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1768 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1769 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1770 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1771 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1772 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1773 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1774 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1775 };
1776
1777 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1778 { "DAC1L", NULL, "DAC1L Mixer" },
1779 { "DAC1R", NULL, "DAC1R Mixer" },
1780 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1781 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1782 };
1783
1784 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1785 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1786 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1787 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1788 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1789 { "MICBIAS1", NULL, "CLK_SYS" },
1790 { "MICBIAS1", NULL, "MICBIAS Supply" },
1791 { "MICBIAS2", NULL, "CLK_SYS" },
1792 { "MICBIAS2", NULL, "MICBIAS Supply" },
1793 };
1794
1795 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1796 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1797 { "AIF2DACR", NULL, "AIF2DAC Mux" },
1798 { "MICBIAS1", NULL, "VMID" },
1799 { "MICBIAS2", NULL, "VMID" },
1800 };
1801
1802 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1803 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1804 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1805
1806 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1807 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1808 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1809 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1810
1811 { "AIF3DACDAT", NULL, "AIF3" },
1812 { "AIF3ADCDAT", NULL, "AIF3" },
1813
1814 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1815 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1816
1817 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1818 };
1819
1820 /* The size in bits of the FLL divide multiplied by 10
1821 * to allow rounding later */
1822 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1823
1824 struct fll_div {
1825 u16 outdiv;
1826 u16 n;
1827 u16 k;
1828 u16 clk_ref_div;
1829 u16 fll_fratio;
1830 };
1831
1832 static int wm8994_get_fll_config(struct fll_div *fll,
1833 int freq_in, int freq_out)
1834 {
1835 u64 Kpart;
1836 unsigned int K, Ndiv, Nmod;
1837
1838 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1839
1840 /* Scale the input frequency down to <= 13.5MHz */
1841 fll->clk_ref_div = 0;
1842 while (freq_in > 13500000) {
1843 fll->clk_ref_div++;
1844 freq_in /= 2;
1845
1846 if (fll->clk_ref_div > 3)
1847 return -EINVAL;
1848 }
1849 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1850
1851 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1852 fll->outdiv = 3;
1853 while (freq_out * (fll->outdiv + 1) < 90000000) {
1854 fll->outdiv++;
1855 if (fll->outdiv > 63)
1856 return -EINVAL;
1857 }
1858 freq_out *= fll->outdiv + 1;
1859 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1860
1861 if (freq_in > 1000000) {
1862 fll->fll_fratio = 0;
1863 } else if (freq_in > 256000) {
1864 fll->fll_fratio = 1;
1865 freq_in *= 2;
1866 } else if (freq_in > 128000) {
1867 fll->fll_fratio = 2;
1868 freq_in *= 4;
1869 } else if (freq_in > 64000) {
1870 fll->fll_fratio = 3;
1871 freq_in *= 8;
1872 } else {
1873 fll->fll_fratio = 4;
1874 freq_in *= 16;
1875 }
1876 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1877
1878 /* Now, calculate N.K */
1879 Ndiv = freq_out / freq_in;
1880
1881 fll->n = Ndiv;
1882 Nmod = freq_out % freq_in;
1883 pr_debug("Nmod=%d\n", Nmod);
1884
1885 /* Calculate fractional part - scale up so we can round. */
1886 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1887
1888 do_div(Kpart, freq_in);
1889
1890 K = Kpart & 0xFFFFFFFF;
1891
1892 if ((K % 10) >= 5)
1893 K += 5;
1894
1895 /* Move down to proper range now rounding is done */
1896 fll->k = K / 10;
1897
1898 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1899
1900 return 0;
1901 }
1902
1903 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1904 unsigned int freq_in, unsigned int freq_out)
1905 {
1906 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1907 struct wm8994 *control = wm8994->wm8994;
1908 int reg_offset, ret;
1909 struct fll_div fll;
1910 u16 reg, clk1, aif_reg, aif_src;
1911 unsigned long timeout;
1912 bool was_enabled;
1913
1914 switch (id) {
1915 case WM8994_FLL1:
1916 reg_offset = 0;
1917 id = 0;
1918 aif_src = 0x10;
1919 break;
1920 case WM8994_FLL2:
1921 reg_offset = 0x20;
1922 id = 1;
1923 aif_src = 0x18;
1924 break;
1925 default:
1926 return -EINVAL;
1927 }
1928
1929 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
1930 was_enabled = reg & WM8994_FLL1_ENA;
1931
1932 switch (src) {
1933 case 0:
1934 /* Allow no source specification when stopping */
1935 if (freq_out)
1936 return -EINVAL;
1937 src = wm8994->fll[id].src;
1938 break;
1939 case WM8994_FLL_SRC_MCLK1:
1940 case WM8994_FLL_SRC_MCLK2:
1941 case WM8994_FLL_SRC_LRCLK:
1942 case WM8994_FLL_SRC_BCLK:
1943 break;
1944 default:
1945 return -EINVAL;
1946 }
1947
1948 /* Are we changing anything? */
1949 if (wm8994->fll[id].src == src &&
1950 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1951 return 0;
1952
1953 /* If we're stopping the FLL redo the old config - no
1954 * registers will actually be written but we avoid GCC flow
1955 * analysis bugs spewing warnings.
1956 */
1957 if (freq_out)
1958 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1959 else
1960 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1961 wm8994->fll[id].out);
1962 if (ret < 0)
1963 return ret;
1964
1965 /* Make sure that we're not providing SYSCLK right now */
1966 clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
1967 if (clk1 & WM8994_SYSCLK_SRC)
1968 aif_reg = WM8994_AIF2_CLOCKING_1;
1969 else
1970 aif_reg = WM8994_AIF1_CLOCKING_1;
1971 reg = snd_soc_read(codec, aif_reg);
1972
1973 if ((reg & WM8994_AIF1CLK_ENA) &&
1974 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
1975 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
1976 id + 1);
1977 return -EBUSY;
1978 }
1979
1980 /* We always need to disable the FLL while reconfiguring */
1981 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1982 WM8994_FLL1_ENA, 0);
1983
1984 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
1985 freq_in == freq_out) {
1986 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
1987 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1988 WM8958_FLL1_BYP, WM8958_FLL1_BYP);
1989 goto out;
1990 }
1991
1992 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1993 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1994 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1995 WM8994_FLL1_OUTDIV_MASK |
1996 WM8994_FLL1_FRATIO_MASK, reg);
1997
1998 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
1999 WM8994_FLL1_K_MASK, fll.k);
2000
2001 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2002 WM8994_FLL1_N_MASK,
2003 fll.n << WM8994_FLL1_N_SHIFT);
2004
2005 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2006 WM8958_FLL1_BYP |
2007 WM8994_FLL1_REFCLK_DIV_MASK |
2008 WM8994_FLL1_REFCLK_SRC_MASK,
2009 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2010 (src - 1));
2011
2012 /* Clear any pending completion from a previous failure */
2013 try_wait_for_completion(&wm8994->fll_locked[id]);
2014
2015 /* Enable (with fractional mode if required) */
2016 if (freq_out) {
2017 /* Enable VMID if we need it */
2018 if (!was_enabled) {
2019 active_reference(codec);
2020
2021 switch (control->type) {
2022 case WM8994:
2023 vmid_reference(codec);
2024 break;
2025 case WM8958:
2026 if (wm8994->revision < 1)
2027 vmid_reference(codec);
2028 break;
2029 default:
2030 break;
2031 }
2032 }
2033
2034 if (fll.k)
2035 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
2036 else
2037 reg = WM8994_FLL1_ENA;
2038 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2039 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
2040 reg);
2041
2042 if (wm8994->fll_locked_irq) {
2043 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2044 msecs_to_jiffies(10));
2045 if (timeout == 0)
2046 dev_warn(codec->dev,
2047 "Timed out waiting for FLL lock\n");
2048 } else {
2049 msleep(5);
2050 }
2051 } else {
2052 if (was_enabled) {
2053 switch (control->type) {
2054 case WM8994:
2055 vmid_dereference(codec);
2056 break;
2057 case WM8958:
2058 if (wm8994->revision < 1)
2059 vmid_dereference(codec);
2060 break;
2061 default:
2062 break;
2063 }
2064
2065 active_dereference(codec);
2066 }
2067 }
2068
2069 out:
2070 wm8994->fll[id].in = freq_in;
2071 wm8994->fll[id].out = freq_out;
2072 wm8994->fll[id].src = src;
2073
2074 configure_clock(codec);
2075
2076 return 0;
2077 }
2078
2079 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2080 {
2081 struct completion *completion = data;
2082
2083 complete(completion);
2084
2085 return IRQ_HANDLED;
2086 }
2087
2088 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2089
2090 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2091 unsigned int freq_in, unsigned int freq_out)
2092 {
2093 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2094 }
2095
2096 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2097 int clk_id, unsigned int freq, int dir)
2098 {
2099 struct snd_soc_codec *codec = dai->codec;
2100 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2101 int i;
2102
2103 switch (dai->id) {
2104 case 1:
2105 case 2:
2106 break;
2107
2108 default:
2109 /* AIF3 shares clocking with AIF1/2 */
2110 return -EINVAL;
2111 }
2112
2113 switch (clk_id) {
2114 case WM8994_SYSCLK_MCLK1:
2115 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2116 wm8994->mclk[0] = freq;
2117 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2118 dai->id, freq);
2119 break;
2120
2121 case WM8994_SYSCLK_MCLK2:
2122 /* TODO: Set GPIO AF */
2123 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2124 wm8994->mclk[1] = freq;
2125 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2126 dai->id, freq);
2127 break;
2128
2129 case WM8994_SYSCLK_FLL1:
2130 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2131 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2132 break;
2133
2134 case WM8994_SYSCLK_FLL2:
2135 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2136 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2137 break;
2138
2139 case WM8994_SYSCLK_OPCLK:
2140 /* Special case - a division (times 10) is given and
2141 * no effect on main clocking.
2142 */
2143 if (freq) {
2144 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2145 if (opclk_divs[i] == freq)
2146 break;
2147 if (i == ARRAY_SIZE(opclk_divs))
2148 return -EINVAL;
2149 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2150 WM8994_OPCLK_DIV_MASK, i);
2151 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2152 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2153 } else {
2154 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2155 WM8994_OPCLK_ENA, 0);
2156 }
2157
2158 default:
2159 return -EINVAL;
2160 }
2161
2162 configure_clock(codec);
2163
2164 return 0;
2165 }
2166
2167 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2168 enum snd_soc_bias_level level)
2169 {
2170 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2171 struct wm8994 *control = wm8994->wm8994;
2172
2173 wm_hubs_set_bias_level(codec, level);
2174
2175 switch (level) {
2176 case SND_SOC_BIAS_ON:
2177 break;
2178
2179 case SND_SOC_BIAS_PREPARE:
2180 /* MICBIAS into regulating mode */
2181 switch (control->type) {
2182 case WM8958:
2183 case WM1811:
2184 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2185 WM8958_MICB1_MODE, 0);
2186 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2187 WM8958_MICB2_MODE, 0);
2188 break;
2189 default:
2190 break;
2191 }
2192
2193 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2194 active_reference(codec);
2195 break;
2196
2197 case SND_SOC_BIAS_STANDBY:
2198 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2199 switch (control->type) {
2200 case WM8958:
2201 if (wm8994->revision == 0) {
2202 /* Optimise performance for rev A */
2203 snd_soc_update_bits(codec,
2204 WM8958_CHARGE_PUMP_2,
2205 WM8958_CP_DISCH,
2206 WM8958_CP_DISCH);
2207 }
2208 break;
2209
2210 default:
2211 break;
2212 }
2213
2214 /* Discharge LINEOUT1 & 2 */
2215 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2216 WM8994_LINEOUT1_DISCH |
2217 WM8994_LINEOUT2_DISCH,
2218 WM8994_LINEOUT1_DISCH |
2219 WM8994_LINEOUT2_DISCH);
2220 }
2221
2222 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2223 active_dereference(codec);
2224
2225 /* MICBIAS into bypass mode on newer devices */
2226 switch (control->type) {
2227 case WM8958:
2228 case WM1811:
2229 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2230 WM8958_MICB1_MODE,
2231 WM8958_MICB1_MODE);
2232 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2233 WM8958_MICB2_MODE,
2234 WM8958_MICB2_MODE);
2235 break;
2236 default:
2237 break;
2238 }
2239 break;
2240
2241 case SND_SOC_BIAS_OFF:
2242 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2243 wm8994->cur_fw = NULL;
2244 break;
2245 }
2246
2247 codec->dapm.bias_level = level;
2248
2249 return 0;
2250 }
2251
2252 int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2253 {
2254 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2255
2256 switch (mode) {
2257 case WM8994_VMID_NORMAL:
2258 if (wm8994->hubs.lineout1_se) {
2259 snd_soc_dapm_disable_pin(&codec->dapm,
2260 "LINEOUT1N Driver");
2261 snd_soc_dapm_disable_pin(&codec->dapm,
2262 "LINEOUT1P Driver");
2263 }
2264 if (wm8994->hubs.lineout2_se) {
2265 snd_soc_dapm_disable_pin(&codec->dapm,
2266 "LINEOUT2N Driver");
2267 snd_soc_dapm_disable_pin(&codec->dapm,
2268 "LINEOUT2P Driver");
2269 }
2270
2271 /* Do the sync with the old mode to allow it to clean up */
2272 snd_soc_dapm_sync(&codec->dapm);
2273 wm8994->vmid_mode = mode;
2274 break;
2275
2276 case WM8994_VMID_FORCE:
2277 if (wm8994->hubs.lineout1_se) {
2278 snd_soc_dapm_force_enable_pin(&codec->dapm,
2279 "LINEOUT1N Driver");
2280 snd_soc_dapm_force_enable_pin(&codec->dapm,
2281 "LINEOUT1P Driver");
2282 }
2283 if (wm8994->hubs.lineout2_se) {
2284 snd_soc_dapm_force_enable_pin(&codec->dapm,
2285 "LINEOUT2N Driver");
2286 snd_soc_dapm_force_enable_pin(&codec->dapm,
2287 "LINEOUT2P Driver");
2288 }
2289
2290 wm8994->vmid_mode = mode;
2291 snd_soc_dapm_sync(&codec->dapm);
2292 break;
2293
2294 default:
2295 return -EINVAL;
2296 }
2297
2298 return 0;
2299 }
2300
2301 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2302 {
2303 struct snd_soc_codec *codec = dai->codec;
2304 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2305 struct wm8994 *control = wm8994->wm8994;
2306 int ms_reg;
2307 int aif1_reg;
2308 int ms = 0;
2309 int aif1 = 0;
2310
2311 switch (dai->id) {
2312 case 1:
2313 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2314 aif1_reg = WM8994_AIF1_CONTROL_1;
2315 break;
2316 case 2:
2317 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2318 aif1_reg = WM8994_AIF2_CONTROL_1;
2319 break;
2320 default:
2321 return -EINVAL;
2322 }
2323
2324 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2325 case SND_SOC_DAIFMT_CBS_CFS:
2326 break;
2327 case SND_SOC_DAIFMT_CBM_CFM:
2328 ms = WM8994_AIF1_MSTR;
2329 break;
2330 default:
2331 return -EINVAL;
2332 }
2333
2334 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2335 case SND_SOC_DAIFMT_DSP_B:
2336 aif1 |= WM8994_AIF1_LRCLK_INV;
2337 case SND_SOC_DAIFMT_DSP_A:
2338 aif1 |= 0x18;
2339 break;
2340 case SND_SOC_DAIFMT_I2S:
2341 aif1 |= 0x10;
2342 break;
2343 case SND_SOC_DAIFMT_RIGHT_J:
2344 break;
2345 case SND_SOC_DAIFMT_LEFT_J:
2346 aif1 |= 0x8;
2347 break;
2348 default:
2349 return -EINVAL;
2350 }
2351
2352 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2353 case SND_SOC_DAIFMT_DSP_A:
2354 case SND_SOC_DAIFMT_DSP_B:
2355 /* frame inversion not valid for DSP modes */
2356 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2357 case SND_SOC_DAIFMT_NB_NF:
2358 break;
2359 case SND_SOC_DAIFMT_IB_NF:
2360 aif1 |= WM8994_AIF1_BCLK_INV;
2361 break;
2362 default:
2363 return -EINVAL;
2364 }
2365 break;
2366
2367 case SND_SOC_DAIFMT_I2S:
2368 case SND_SOC_DAIFMT_RIGHT_J:
2369 case SND_SOC_DAIFMT_LEFT_J:
2370 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2371 case SND_SOC_DAIFMT_NB_NF:
2372 break;
2373 case SND_SOC_DAIFMT_IB_IF:
2374 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2375 break;
2376 case SND_SOC_DAIFMT_IB_NF:
2377 aif1 |= WM8994_AIF1_BCLK_INV;
2378 break;
2379 case SND_SOC_DAIFMT_NB_IF:
2380 aif1 |= WM8994_AIF1_LRCLK_INV;
2381 break;
2382 default:
2383 return -EINVAL;
2384 }
2385 break;
2386 default:
2387 return -EINVAL;
2388 }
2389
2390 /* The AIF2 format configuration needs to be mirrored to AIF3
2391 * on WM8958 if it's in use so just do it all the time. */
2392 switch (control->type) {
2393 case WM1811:
2394 case WM8958:
2395 if (dai->id == 2)
2396 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2397 WM8994_AIF1_LRCLK_INV |
2398 WM8958_AIF3_FMT_MASK, aif1);
2399 break;
2400
2401 default:
2402 break;
2403 }
2404
2405 snd_soc_update_bits(codec, aif1_reg,
2406 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2407 WM8994_AIF1_FMT_MASK,
2408 aif1);
2409 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2410 ms);
2411
2412 return 0;
2413 }
2414
2415 static struct {
2416 int val, rate;
2417 } srs[] = {
2418 { 0, 8000 },
2419 { 1, 11025 },
2420 { 2, 12000 },
2421 { 3, 16000 },
2422 { 4, 22050 },
2423 { 5, 24000 },
2424 { 6, 32000 },
2425 { 7, 44100 },
2426 { 8, 48000 },
2427 { 9, 88200 },
2428 { 10, 96000 },
2429 };
2430
2431 static int fs_ratios[] = {
2432 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2433 };
2434
2435 static int bclk_divs[] = {
2436 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2437 640, 880, 960, 1280, 1760, 1920
2438 };
2439
2440 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2441 struct snd_pcm_hw_params *params,
2442 struct snd_soc_dai *dai)
2443 {
2444 struct snd_soc_codec *codec = dai->codec;
2445 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2446 int aif1_reg;
2447 int aif2_reg;
2448 int bclk_reg;
2449 int lrclk_reg;
2450 int rate_reg;
2451 int aif1 = 0;
2452 int aif2 = 0;
2453 int bclk = 0;
2454 int lrclk = 0;
2455 int rate_val = 0;
2456 int id = dai->id - 1;
2457
2458 int i, cur_val, best_val, bclk_rate, best;
2459
2460 switch (dai->id) {
2461 case 1:
2462 aif1_reg = WM8994_AIF1_CONTROL_1;
2463 aif2_reg = WM8994_AIF1_CONTROL_2;
2464 bclk_reg = WM8994_AIF1_BCLK;
2465 rate_reg = WM8994_AIF1_RATE;
2466 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2467 wm8994->lrclk_shared[0]) {
2468 lrclk_reg = WM8994_AIF1DAC_LRCLK;
2469 } else {
2470 lrclk_reg = WM8994_AIF1ADC_LRCLK;
2471 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2472 }
2473 break;
2474 case 2:
2475 aif1_reg = WM8994_AIF2_CONTROL_1;
2476 aif2_reg = WM8994_AIF2_CONTROL_2;
2477 bclk_reg = WM8994_AIF2_BCLK;
2478 rate_reg = WM8994_AIF2_RATE;
2479 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2480 wm8994->lrclk_shared[1]) {
2481 lrclk_reg = WM8994_AIF2DAC_LRCLK;
2482 } else {
2483 lrclk_reg = WM8994_AIF2ADC_LRCLK;
2484 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2485 }
2486 break;
2487 default:
2488 return -EINVAL;
2489 }
2490
2491 bclk_rate = params_rate(params) * 2;
2492 switch (params_format(params)) {
2493 case SNDRV_PCM_FORMAT_S16_LE:
2494 bclk_rate *= 16;
2495 break;
2496 case SNDRV_PCM_FORMAT_S20_3LE:
2497 bclk_rate *= 20;
2498 aif1 |= 0x20;
2499 break;
2500 case SNDRV_PCM_FORMAT_S24_LE:
2501 bclk_rate *= 24;
2502 aif1 |= 0x40;
2503 break;
2504 case SNDRV_PCM_FORMAT_S32_LE:
2505 bclk_rate *= 32;
2506 aif1 |= 0x60;
2507 break;
2508 default:
2509 return -EINVAL;
2510 }
2511
2512 /* Try to find an appropriate sample rate; look for an exact match. */
2513 for (i = 0; i < ARRAY_SIZE(srs); i++)
2514 if (srs[i].rate == params_rate(params))
2515 break;
2516 if (i == ARRAY_SIZE(srs))
2517 return -EINVAL;
2518 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2519
2520 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2521 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2522 dai->id, wm8994->aifclk[id], bclk_rate);
2523
2524 if (params_channels(params) == 1 &&
2525 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2526 aif2 |= WM8994_AIF1_MONO;
2527
2528 if (wm8994->aifclk[id] == 0) {
2529 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2530 return -EINVAL;
2531 }
2532
2533 /* AIFCLK/fs ratio; look for a close match in either direction */
2534 best = 0;
2535 best_val = abs((fs_ratios[0] * params_rate(params))
2536 - wm8994->aifclk[id]);
2537 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2538 cur_val = abs((fs_ratios[i] * params_rate(params))
2539 - wm8994->aifclk[id]);
2540 if (cur_val >= best_val)
2541 continue;
2542 best = i;
2543 best_val = cur_val;
2544 }
2545 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2546 dai->id, fs_ratios[best]);
2547 rate_val |= best;
2548
2549 /* We may not get quite the right frequency if using
2550 * approximate clocks so look for the closest match that is
2551 * higher than the target (we need to ensure that there enough
2552 * BCLKs to clock out the samples).
2553 */
2554 best = 0;
2555 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2556 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2557 if (cur_val < 0) /* BCLK table is sorted */
2558 break;
2559 best = i;
2560 }
2561 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2562 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2563 bclk_divs[best], bclk_rate);
2564 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2565
2566 lrclk = bclk_rate / params_rate(params);
2567 if (!lrclk) {
2568 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2569 bclk_rate);
2570 return -EINVAL;
2571 }
2572 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2573 lrclk, bclk_rate / lrclk);
2574
2575 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2576 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2577 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2578 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2579 lrclk);
2580 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2581 WM8994_AIF1CLK_RATE_MASK, rate_val);
2582
2583 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2584 switch (dai->id) {
2585 case 1:
2586 wm8994->dac_rates[0] = params_rate(params);
2587 wm8994_set_retune_mobile(codec, 0);
2588 wm8994_set_retune_mobile(codec, 1);
2589 break;
2590 case 2:
2591 wm8994->dac_rates[1] = params_rate(params);
2592 wm8994_set_retune_mobile(codec, 2);
2593 break;
2594 }
2595 }
2596
2597 return 0;
2598 }
2599
2600 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2601 struct snd_pcm_hw_params *params,
2602 struct snd_soc_dai *dai)
2603 {
2604 struct snd_soc_codec *codec = dai->codec;
2605 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2606 struct wm8994 *control = wm8994->wm8994;
2607 int aif1_reg;
2608 int aif1 = 0;
2609
2610 switch (dai->id) {
2611 case 3:
2612 switch (control->type) {
2613 case WM1811:
2614 case WM8958:
2615 aif1_reg = WM8958_AIF3_CONTROL_1;
2616 break;
2617 default:
2618 return 0;
2619 }
2620 default:
2621 return 0;
2622 }
2623
2624 switch (params_format(params)) {
2625 case SNDRV_PCM_FORMAT_S16_LE:
2626 break;
2627 case SNDRV_PCM_FORMAT_S20_3LE:
2628 aif1 |= 0x20;
2629 break;
2630 case SNDRV_PCM_FORMAT_S24_LE:
2631 aif1 |= 0x40;
2632 break;
2633 case SNDRV_PCM_FORMAT_S32_LE:
2634 aif1 |= 0x60;
2635 break;
2636 default:
2637 return -EINVAL;
2638 }
2639
2640 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2641 }
2642
2643 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2644 {
2645 struct snd_soc_codec *codec = codec_dai->codec;
2646 int mute_reg;
2647 int reg;
2648
2649 switch (codec_dai->id) {
2650 case 1:
2651 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2652 break;
2653 case 2:
2654 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2655 break;
2656 default:
2657 return -EINVAL;
2658 }
2659
2660 if (mute)
2661 reg = WM8994_AIF1DAC1_MUTE;
2662 else
2663 reg = 0;
2664
2665 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2666
2667 return 0;
2668 }
2669
2670 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2671 {
2672 struct snd_soc_codec *codec = codec_dai->codec;
2673 int reg, val, mask;
2674
2675 switch (codec_dai->id) {
2676 case 1:
2677 reg = WM8994_AIF1_MASTER_SLAVE;
2678 mask = WM8994_AIF1_TRI;
2679 break;
2680 case 2:
2681 reg = WM8994_AIF2_MASTER_SLAVE;
2682 mask = WM8994_AIF2_TRI;
2683 break;
2684 default:
2685 return -EINVAL;
2686 }
2687
2688 if (tristate)
2689 val = mask;
2690 else
2691 val = 0;
2692
2693 return snd_soc_update_bits(codec, reg, mask, val);
2694 }
2695
2696 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2697 {
2698 struct snd_soc_codec *codec = dai->codec;
2699
2700 /* Disable the pulls on the AIF if we're using it to save power. */
2701 snd_soc_update_bits(codec, WM8994_GPIO_3,
2702 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2703 snd_soc_update_bits(codec, WM8994_GPIO_4,
2704 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2705 snd_soc_update_bits(codec, WM8994_GPIO_5,
2706 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2707
2708 return 0;
2709 }
2710
2711 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2712
2713 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2714 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2715
2716 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2717 .set_sysclk = wm8994_set_dai_sysclk,
2718 .set_fmt = wm8994_set_dai_fmt,
2719 .hw_params = wm8994_hw_params,
2720 .digital_mute = wm8994_aif_mute,
2721 .set_pll = wm8994_set_fll,
2722 .set_tristate = wm8994_set_tristate,
2723 };
2724
2725 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2726 .set_sysclk = wm8994_set_dai_sysclk,
2727 .set_fmt = wm8994_set_dai_fmt,
2728 .hw_params = wm8994_hw_params,
2729 .digital_mute = wm8994_aif_mute,
2730 .set_pll = wm8994_set_fll,
2731 .set_tristate = wm8994_set_tristate,
2732 };
2733
2734 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2735 .hw_params = wm8994_aif3_hw_params,
2736 };
2737
2738 static struct snd_soc_dai_driver wm8994_dai[] = {
2739 {
2740 .name = "wm8994-aif1",
2741 .id = 1,
2742 .playback = {
2743 .stream_name = "AIF1 Playback",
2744 .channels_min = 1,
2745 .channels_max = 2,
2746 .rates = WM8994_RATES,
2747 .formats = WM8994_FORMATS,
2748 .sig_bits = 24,
2749 },
2750 .capture = {
2751 .stream_name = "AIF1 Capture",
2752 .channels_min = 1,
2753 .channels_max = 2,
2754 .rates = WM8994_RATES,
2755 .formats = WM8994_FORMATS,
2756 .sig_bits = 24,
2757 },
2758 .ops = &wm8994_aif1_dai_ops,
2759 },
2760 {
2761 .name = "wm8994-aif2",
2762 .id = 2,
2763 .playback = {
2764 .stream_name = "AIF2 Playback",
2765 .channels_min = 1,
2766 .channels_max = 2,
2767 .rates = WM8994_RATES,
2768 .formats = WM8994_FORMATS,
2769 .sig_bits = 24,
2770 },
2771 .capture = {
2772 .stream_name = "AIF2 Capture",
2773 .channels_min = 1,
2774 .channels_max = 2,
2775 .rates = WM8994_RATES,
2776 .formats = WM8994_FORMATS,
2777 .sig_bits = 24,
2778 },
2779 .probe = wm8994_aif2_probe,
2780 .ops = &wm8994_aif2_dai_ops,
2781 },
2782 {
2783 .name = "wm8994-aif3",
2784 .id = 3,
2785 .playback = {
2786 .stream_name = "AIF3 Playback",
2787 .channels_min = 1,
2788 .channels_max = 2,
2789 .rates = WM8994_RATES,
2790 .formats = WM8994_FORMATS,
2791 .sig_bits = 24,
2792 },
2793 .capture = {
2794 .stream_name = "AIF3 Capture",
2795 .channels_min = 1,
2796 .channels_max = 2,
2797 .rates = WM8994_RATES,
2798 .formats = WM8994_FORMATS,
2799 .sig_bits = 24,
2800 },
2801 .ops = &wm8994_aif3_dai_ops,
2802 }
2803 };
2804
2805 #ifdef CONFIG_PM
2806 static int wm8994_codec_suspend(struct snd_soc_codec *codec)
2807 {
2808 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2809 struct wm8994 *control = wm8994->wm8994;
2810 int i, ret;
2811
2812 switch (control->type) {
2813 case WM8994:
2814 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2815 break;
2816 case WM1811:
2817 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2818 WM1811_JACKDET_MODE_MASK, 0);
2819 /* Fall through */
2820 case WM8958:
2821 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2822 WM8958_MICD_ENA, 0);
2823 break;
2824 }
2825
2826 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2827 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2828 sizeof(struct wm8994_fll_config));
2829 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2830 if (ret < 0)
2831 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2832 i + 1, ret);
2833 }
2834
2835 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2836
2837 return 0;
2838 }
2839
2840 static int wm8994_codec_resume(struct snd_soc_codec *codec)
2841 {
2842 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2843 struct wm8994 *control = wm8994->wm8994;
2844 int i, ret;
2845 unsigned int val, mask;
2846
2847 if (wm8994->revision < 4) {
2848 /* force a HW read */
2849 ret = regmap_read(control->regmap,
2850 WM8994_POWER_MANAGEMENT_5, &val);
2851
2852 /* modify the cache only */
2853 codec->cache_only = 1;
2854 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2855 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2856 val &= mask;
2857 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2858 mask, val);
2859 codec->cache_only = 0;
2860 }
2861
2862 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2863 if (!wm8994->fll_suspend[i].out)
2864 continue;
2865
2866 ret = _wm8994_set_fll(codec, i + 1,
2867 wm8994->fll_suspend[i].src,
2868 wm8994->fll_suspend[i].in,
2869 wm8994->fll_suspend[i].out);
2870 if (ret < 0)
2871 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2872 i + 1, ret);
2873 }
2874
2875 switch (control->type) {
2876 case WM8994:
2877 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2878 snd_soc_update_bits(codec, WM8994_MICBIAS,
2879 WM8994_MICD_ENA, WM8994_MICD_ENA);
2880 break;
2881 case WM1811:
2882 if (wm8994->jackdet && wm8994->jack_cb) {
2883 /* Restart from idle */
2884 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2885 WM1811_JACKDET_MODE_MASK,
2886 WM1811_JACKDET_MODE_JACK);
2887 break;
2888 }
2889 break;
2890 case WM8958:
2891 if (wm8994->jack_cb)
2892 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2893 WM8958_MICD_ENA, WM8958_MICD_ENA);
2894 break;
2895 }
2896
2897 return 0;
2898 }
2899 #else
2900 #define wm8994_codec_suspend NULL
2901 #define wm8994_codec_resume NULL
2902 #endif
2903
2904 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2905 {
2906 struct snd_soc_codec *codec = wm8994->codec;
2907 struct wm8994_pdata *pdata = wm8994->pdata;
2908 struct snd_kcontrol_new controls[] = {
2909 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2910 wm8994->retune_mobile_enum,
2911 wm8994_get_retune_mobile_enum,
2912 wm8994_put_retune_mobile_enum),
2913 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2914 wm8994->retune_mobile_enum,
2915 wm8994_get_retune_mobile_enum,
2916 wm8994_put_retune_mobile_enum),
2917 SOC_ENUM_EXT("AIF2 EQ Mode",
2918 wm8994->retune_mobile_enum,
2919 wm8994_get_retune_mobile_enum,
2920 wm8994_put_retune_mobile_enum),
2921 };
2922 int ret, i, j;
2923 const char **t;
2924
2925 /* We need an array of texts for the enum API but the number
2926 * of texts is likely to be less than the number of
2927 * configurations due to the sample rate dependency of the
2928 * configurations. */
2929 wm8994->num_retune_mobile_texts = 0;
2930 wm8994->retune_mobile_texts = NULL;
2931 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2932 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2933 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2934 wm8994->retune_mobile_texts[j]) == 0)
2935 break;
2936 }
2937
2938 if (j != wm8994->num_retune_mobile_texts)
2939 continue;
2940
2941 /* Expand the array... */
2942 t = krealloc(wm8994->retune_mobile_texts,
2943 sizeof(char *) *
2944 (wm8994->num_retune_mobile_texts + 1),
2945 GFP_KERNEL);
2946 if (t == NULL)
2947 continue;
2948
2949 /* ...store the new entry... */
2950 t[wm8994->num_retune_mobile_texts] =
2951 pdata->retune_mobile_cfgs[i].name;
2952
2953 /* ...and remember the new version. */
2954 wm8994->num_retune_mobile_texts++;
2955 wm8994->retune_mobile_texts = t;
2956 }
2957
2958 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2959 wm8994->num_retune_mobile_texts);
2960
2961 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2962 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2963
2964 ret = snd_soc_add_codec_controls(wm8994->codec, controls,
2965 ARRAY_SIZE(controls));
2966 if (ret != 0)
2967 dev_err(wm8994->codec->dev,
2968 "Failed to add ReTune Mobile controls: %d\n", ret);
2969 }
2970
2971 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2972 {
2973 struct snd_soc_codec *codec = wm8994->codec;
2974 struct wm8994_pdata *pdata = wm8994->pdata;
2975 int ret, i;
2976
2977 if (!pdata)
2978 return;
2979
2980 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2981 pdata->lineout2_diff,
2982 pdata->lineout1fb,
2983 pdata->lineout2fb,
2984 pdata->jd_scthr,
2985 pdata->jd_thr,
2986 pdata->micbias1_lvl,
2987 pdata->micbias2_lvl);
2988
2989 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2990
2991 if (pdata->num_drc_cfgs) {
2992 struct snd_kcontrol_new controls[] = {
2993 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2994 wm8994_get_drc_enum, wm8994_put_drc_enum),
2995 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2996 wm8994_get_drc_enum, wm8994_put_drc_enum),
2997 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2998 wm8994_get_drc_enum, wm8994_put_drc_enum),
2999 };
3000
3001 /* We need an array of texts for the enum API */
3002 wm8994->drc_texts = devm_kzalloc(wm8994->codec->dev,
3003 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
3004 if (!wm8994->drc_texts) {
3005 dev_err(wm8994->codec->dev,
3006 "Failed to allocate %d DRC config texts\n",
3007 pdata->num_drc_cfgs);
3008 return;
3009 }
3010
3011 for (i = 0; i < pdata->num_drc_cfgs; i++)
3012 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3013
3014 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3015 wm8994->drc_enum.texts = wm8994->drc_texts;
3016
3017 ret = snd_soc_add_codec_controls(wm8994->codec, controls,
3018 ARRAY_SIZE(controls));
3019 if (ret != 0)
3020 dev_err(wm8994->codec->dev,
3021 "Failed to add DRC mode controls: %d\n", ret);
3022
3023 for (i = 0; i < WM8994_NUM_DRC; i++)
3024 wm8994_set_drc(codec, i);
3025 }
3026
3027 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3028 pdata->num_retune_mobile_cfgs);
3029
3030 if (pdata->num_retune_mobile_cfgs)
3031 wm8994_handle_retune_mobile_pdata(wm8994);
3032 else
3033 snd_soc_add_codec_controls(wm8994->codec, wm8994_eq_controls,
3034 ARRAY_SIZE(wm8994_eq_controls));
3035
3036 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3037 if (pdata->micbias[i]) {
3038 snd_soc_write(codec, WM8958_MICBIAS1 + i,
3039 pdata->micbias[i] & 0xffff);
3040 }
3041 }
3042 }
3043
3044 /**
3045 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3046 *
3047 * @codec: WM8994 codec
3048 * @jack: jack to report detection events on
3049 * @micbias: microphone bias to detect on
3050 *
3051 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3052 * being used to bring out signals to the processor then only platform
3053 * data configuration is needed for WM8994 and processor GPIOs should
3054 * be configured using snd_soc_jack_add_gpios() instead.
3055 *
3056 * Configuration of detection levels is available via the micbias1_lvl
3057 * and micbias2_lvl platform data members.
3058 */
3059 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3060 int micbias)
3061 {
3062 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3063 struct wm8994_micdet *micdet;
3064 struct wm8994 *control = wm8994->wm8994;
3065 int reg, ret;
3066
3067 if (control->type != WM8994) {
3068 dev_warn(codec->dev, "Not a WM8994\n");
3069 return -EINVAL;
3070 }
3071
3072 switch (micbias) {
3073 case 1:
3074 micdet = &wm8994->micdet[0];
3075 if (jack)
3076 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3077 "MICBIAS1");
3078 else
3079 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3080 "MICBIAS1");
3081 break;
3082 case 2:
3083 micdet = &wm8994->micdet[1];
3084 if (jack)
3085 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3086 "MICBIAS1");
3087 else
3088 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3089 "MICBIAS1");
3090 break;
3091 default:
3092 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
3093 return -EINVAL;
3094 }
3095
3096 if (ret != 0)
3097 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3098 micbias, ret);
3099
3100 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3101 micbias, jack);
3102
3103 /* Store the configuration */
3104 micdet->jack = jack;
3105 micdet->detecting = true;
3106
3107 /* If either of the jacks is set up then enable detection */
3108 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3109 reg = WM8994_MICD_ENA;
3110 else
3111 reg = 0;
3112
3113 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3114
3115 snd_soc_dapm_sync(&codec->dapm);
3116
3117 return 0;
3118 }
3119 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3120
3121 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3122 {
3123 struct wm8994_priv *priv = data;
3124 struct snd_soc_codec *codec = priv->codec;
3125 int reg;
3126 int report;
3127
3128 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3129 trace_snd_soc_jack_irq(dev_name(codec->dev));
3130 #endif
3131
3132 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
3133 if (reg < 0) {
3134 dev_err(codec->dev, "Failed to read microphone status: %d\n",
3135 reg);
3136 return IRQ_HANDLED;
3137 }
3138
3139 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
3140
3141 report = 0;
3142 if (reg & WM8994_MIC1_DET_STS) {
3143 if (priv->micdet[0].detecting)
3144 report = SND_JACK_HEADSET;
3145 }
3146 if (reg & WM8994_MIC1_SHRT_STS) {
3147 if (priv->micdet[0].detecting)
3148 report = SND_JACK_HEADPHONE;
3149 else
3150 report |= SND_JACK_BTN_0;
3151 }
3152 if (report)
3153 priv->micdet[0].detecting = false;
3154 else
3155 priv->micdet[0].detecting = true;
3156
3157 snd_soc_jack_report(priv->micdet[0].jack, report,
3158 SND_JACK_HEADSET | SND_JACK_BTN_0);
3159
3160 report = 0;
3161 if (reg & WM8994_MIC2_DET_STS) {
3162 if (priv->micdet[1].detecting)
3163 report = SND_JACK_HEADSET;
3164 }
3165 if (reg & WM8994_MIC2_SHRT_STS) {
3166 if (priv->micdet[1].detecting)
3167 report = SND_JACK_HEADPHONE;
3168 else
3169 report |= SND_JACK_BTN_0;
3170 }
3171 if (report)
3172 priv->micdet[1].detecting = false;
3173 else
3174 priv->micdet[1].detecting = true;
3175
3176 snd_soc_jack_report(priv->micdet[1].jack, report,
3177 SND_JACK_HEADSET | SND_JACK_BTN_0);
3178
3179 return IRQ_HANDLED;
3180 }
3181
3182 /* Default microphone detection handler for WM8958 - the user can
3183 * override this if they wish.
3184 */
3185 static void wm8958_default_micdet(u16 status, void *data)
3186 {
3187 struct snd_soc_codec *codec = data;
3188 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3189 int report;
3190
3191 dev_dbg(codec->dev, "MICDET %x\n", status);
3192
3193 /* Either nothing present or just starting detection */
3194 if (!(status & WM8958_MICD_STS)) {
3195 if (!wm8994->jackdet) {
3196 /* If nothing present then clear our statuses */
3197 dev_dbg(codec->dev, "Detected open circuit\n");
3198 wm8994->jack_mic = false;
3199 wm8994->mic_detecting = true;
3200
3201 wm8958_micd_set_rate(codec);
3202
3203 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3204 wm8994->btn_mask |
3205 SND_JACK_HEADSET);
3206 }
3207 return;
3208 }
3209
3210 /* If the measurement is showing a high impedence we've got a
3211 * microphone.
3212 */
3213 if (wm8994->mic_detecting && (status & 0x600)) {
3214 dev_dbg(codec->dev, "Detected microphone\n");
3215
3216 wm8994->mic_detecting = false;
3217 wm8994->jack_mic = true;
3218
3219 wm8958_micd_set_rate(codec);
3220
3221 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3222 SND_JACK_HEADSET);
3223 }
3224
3225
3226 if (wm8994->mic_detecting && status & 0xfc) {
3227 dev_dbg(codec->dev, "Detected headphone\n");
3228 wm8994->mic_detecting = false;
3229
3230 wm8958_micd_set_rate(codec);
3231
3232 /* If we have jackdet that will detect removal */
3233 if (wm8994->jackdet) {
3234 mutex_lock(&wm8994->accdet_lock);
3235
3236 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3237 WM8958_MICD_ENA, 0);
3238
3239 wm1811_jackdet_set_mode(codec,
3240 WM1811_JACKDET_MODE_JACK);
3241
3242 mutex_unlock(&wm8994->accdet_lock);
3243
3244 if (wm8994->pdata->jd_ext_cap)
3245 snd_soc_dapm_disable_pin(&codec->dapm,
3246 "MICBIAS2");
3247 }
3248
3249 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3250 SND_JACK_HEADSET);
3251 }
3252
3253 /* Report short circuit as a button */
3254 if (wm8994->jack_mic) {
3255 report = 0;
3256 if (status & 0x4)
3257 report |= SND_JACK_BTN_0;
3258
3259 if (status & 0x8)
3260 report |= SND_JACK_BTN_1;
3261
3262 if (status & 0x10)
3263 report |= SND_JACK_BTN_2;
3264
3265 if (status & 0x20)
3266 report |= SND_JACK_BTN_3;
3267
3268 if (status & 0x40)
3269 report |= SND_JACK_BTN_4;
3270
3271 if (status & 0x80)
3272 report |= SND_JACK_BTN_5;
3273
3274 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3275 wm8994->btn_mask);
3276 }
3277 }
3278
3279 static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3280 {
3281 struct wm8994_priv *wm8994 = data;
3282 struct snd_soc_codec *codec = wm8994->codec;
3283 int reg;
3284 bool present;
3285
3286 mutex_lock(&wm8994->accdet_lock);
3287
3288 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3289 if (reg < 0) {
3290 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3291 mutex_unlock(&wm8994->accdet_lock);
3292 return IRQ_NONE;
3293 }
3294
3295 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3296
3297 present = reg & WM1811_JACKDET_LVL;
3298
3299 if (present) {
3300 dev_dbg(codec->dev, "Jack detected\n");
3301
3302 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3303 WM8958_MICB2_DISCH, 0);
3304
3305 /* Disable debounce while inserted */
3306 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3307 WM1811_JACKDET_DB, 0);
3308
3309 /*
3310 * Start off measument of microphone impedence to find
3311 * out what's actually there.
3312 */
3313 wm8994->mic_detecting = true;
3314 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3315
3316 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3317 WM8958_MICD_ENA, WM8958_MICD_ENA);
3318 } else {
3319 dev_dbg(codec->dev, "Jack not detected\n");
3320
3321 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3322 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3323
3324 /* Enable debounce while removed */
3325 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3326 WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3327
3328 wm8994->mic_detecting = false;
3329 wm8994->jack_mic = false;
3330 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3331 WM8958_MICD_ENA, 0);
3332 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3333 }
3334
3335 mutex_unlock(&wm8994->accdet_lock);
3336
3337 /* If required for an external cap force MICBIAS on */
3338 if (wm8994->pdata->jd_ext_cap) {
3339 if (present)
3340 snd_soc_dapm_force_enable_pin(&codec->dapm,
3341 "MICBIAS2");
3342 else
3343 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
3344 }
3345
3346 if (present)
3347 snd_soc_jack_report(wm8994->micdet[0].jack,
3348 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3349 else
3350 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3351 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3352 wm8994->btn_mask);
3353
3354 return IRQ_HANDLED;
3355 }
3356
3357 /**
3358 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3359 *
3360 * @codec: WM8958 codec
3361 * @jack: jack to report detection events on
3362 *
3363 * Enable microphone detection functionality for the WM8958. By
3364 * default simple detection which supports the detection of up to 6
3365 * buttons plus video and microphone functionality is supported.
3366 *
3367 * The WM8958 has an advanced jack detection facility which is able to
3368 * support complex accessory detection, especially when used in
3369 * conjunction with external circuitry. In order to provide maximum
3370 * flexiblity a callback is provided which allows a completely custom
3371 * detection algorithm.
3372 */
3373 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3374 wm8958_micdet_cb cb, void *cb_data)
3375 {
3376 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3377 struct wm8994 *control = wm8994->wm8994;
3378 u16 micd_lvl_sel;
3379
3380 switch (control->type) {
3381 case WM1811:
3382 case WM8958:
3383 break;
3384 default:
3385 return -EINVAL;
3386 }
3387
3388 if (jack) {
3389 if (!cb) {
3390 dev_dbg(codec->dev, "Using default micdet callback\n");
3391 cb = wm8958_default_micdet;
3392 cb_data = codec;
3393 }
3394
3395 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3396 snd_soc_dapm_sync(&codec->dapm);
3397
3398 wm8994->micdet[0].jack = jack;
3399 wm8994->jack_cb = cb;
3400 wm8994->jack_cb_data = cb_data;
3401
3402 wm8994->mic_detecting = true;
3403 wm8994->jack_mic = false;
3404
3405 wm8958_micd_set_rate(codec);
3406
3407 /* Detect microphones and short circuits by default */
3408 if (wm8994->pdata->micd_lvl_sel)
3409 micd_lvl_sel = wm8994->pdata->micd_lvl_sel;
3410 else
3411 micd_lvl_sel = 0x41;
3412
3413 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3414 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3415 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3416
3417 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
3418 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3419
3420 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3421
3422 /*
3423 * If we can use jack detection start off with that,
3424 * otherwise jump straight to microphone detection.
3425 */
3426 if (wm8994->jackdet) {
3427 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3428 WM8958_MICB2_DISCH,
3429 WM8958_MICB2_DISCH);
3430 snd_soc_update_bits(codec, WM8994_LDO_1,
3431 WM8994_LDO1_DISCH, 0);
3432 wm1811_jackdet_set_mode(codec,
3433 WM1811_JACKDET_MODE_JACK);
3434 } else {
3435 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3436 WM8958_MICD_ENA, WM8958_MICD_ENA);
3437 }
3438
3439 } else {
3440 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3441 WM8958_MICD_ENA, 0);
3442 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
3443 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
3444 snd_soc_dapm_sync(&codec->dapm);
3445 }
3446
3447 return 0;
3448 }
3449 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3450
3451 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3452 {
3453 struct wm8994_priv *wm8994 = data;
3454 struct snd_soc_codec *codec = wm8994->codec;
3455 int reg, count;
3456
3457 /*
3458 * Jack detection may have detected a removal simulataneously
3459 * with an update of the MICDET status; if so it will have
3460 * stopped detection and we can ignore this interrupt.
3461 */
3462 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
3463 return IRQ_HANDLED;
3464
3465 /* We may occasionally read a detection without an impedence
3466 * range being provided - if that happens loop again.
3467 */
3468 count = 10;
3469 do {
3470 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3471 if (reg < 0) {
3472 dev_err(codec->dev,
3473 "Failed to read mic detect status: %d\n",
3474 reg);
3475 return IRQ_NONE;
3476 }
3477
3478 if (!(reg & WM8958_MICD_VALID)) {
3479 dev_dbg(codec->dev, "Mic detect data not valid\n");
3480 goto out;
3481 }
3482
3483 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3484 break;
3485
3486 msleep(1);
3487 } while (count--);
3488
3489 if (count == 0)
3490 dev_warn(codec->dev, "No impedence range reported for jack\n");
3491
3492 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3493 trace_snd_soc_jack_irq(dev_name(codec->dev));
3494 #endif
3495
3496 if (wm8994->jack_cb)
3497 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3498 else
3499 dev_warn(codec->dev, "Accessory detection with no callback\n");
3500
3501 out:
3502 return IRQ_HANDLED;
3503 }
3504
3505 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3506 {
3507 struct snd_soc_codec *codec = data;
3508
3509 dev_err(codec->dev, "FIFO error\n");
3510
3511 return IRQ_HANDLED;
3512 }
3513
3514 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3515 {
3516 struct snd_soc_codec *codec = data;
3517
3518 dev_err(codec->dev, "Thermal warning\n");
3519
3520 return IRQ_HANDLED;
3521 }
3522
3523 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3524 {
3525 struct snd_soc_codec *codec = data;
3526
3527 dev_crit(codec->dev, "Thermal shutdown\n");
3528
3529 return IRQ_HANDLED;
3530 }
3531
3532 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3533 {
3534 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
3535 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3536 struct snd_soc_dapm_context *dapm = &codec->dapm;
3537 unsigned int reg;
3538 int ret, i;
3539
3540 wm8994->codec = codec;
3541 codec->control_data = control->regmap;
3542
3543 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
3544
3545 wm8994->codec = codec;
3546
3547 mutex_init(&wm8994->accdet_lock);
3548
3549 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3550 init_completion(&wm8994->fll_locked[i]);
3551
3552 if (wm8994->pdata && wm8994->pdata->micdet_irq)
3553 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3554 else if (wm8994->pdata && wm8994->pdata->irq_base)
3555 wm8994->micdet_irq = wm8994->pdata->irq_base +
3556 WM8994_IRQ_MIC1_DET;
3557
3558 pm_runtime_enable(codec->dev);
3559 pm_runtime_idle(codec->dev);
3560
3561 /* By default use idle_bias_off, will override for WM8994 */
3562 codec->dapm.idle_bias_off = 1;
3563
3564 /* Set revision-specific configuration */
3565 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3566 switch (control->type) {
3567 case WM8994:
3568 /* Single ended line outputs should have VMID on. */
3569 if (!wm8994->pdata->lineout1_diff ||
3570 !wm8994->pdata->lineout2_diff)
3571 codec->dapm.idle_bias_off = 0;
3572
3573 switch (wm8994->revision) {
3574 case 2:
3575 case 3:
3576 wm8994->hubs.dcs_codes_l = -5;
3577 wm8994->hubs.dcs_codes_r = -5;
3578 wm8994->hubs.hp_startup_mode = 1;
3579 wm8994->hubs.dcs_readback_mode = 1;
3580 wm8994->hubs.series_startup = 1;
3581 break;
3582 default:
3583 wm8994->hubs.dcs_readback_mode = 2;
3584 break;
3585 }
3586 break;
3587
3588 case WM8958:
3589 wm8994->hubs.dcs_readback_mode = 1;
3590 wm8994->hubs.hp_startup_mode = 1;
3591
3592 switch (wm8994->revision) {
3593 case 0:
3594 break;
3595 default:
3596 wm8994->fll_byp = true;
3597 break;
3598 }
3599 break;
3600
3601 case WM1811:
3602 wm8994->hubs.dcs_readback_mode = 2;
3603 wm8994->hubs.no_series_update = 1;
3604 wm8994->hubs.hp_startup_mode = 1;
3605 wm8994->hubs.no_cache_class_w = true;
3606 wm8994->fll_byp = true;
3607
3608 switch (wm8994->revision) {
3609 case 0:
3610 case 1:
3611 case 2:
3612 case 3:
3613 wm8994->hubs.dcs_codes_l = -9;
3614 wm8994->hubs.dcs_codes_r = -7;
3615 break;
3616 default:
3617 break;
3618 }
3619
3620 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3621 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3622 break;
3623
3624 default:
3625 break;
3626 }
3627
3628 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3629 wm8994_fifo_error, "FIFO error", codec);
3630 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
3631 wm8994_temp_warn, "Thermal warning", codec);
3632 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
3633 wm8994_temp_shut, "Thermal shutdown", codec);
3634
3635 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3636 wm_hubs_dcs_done, "DC servo done",
3637 &wm8994->hubs);
3638 if (ret == 0)
3639 wm8994->hubs.dcs_done_irq = true;
3640
3641 switch (control->type) {
3642 case WM8994:
3643 if (wm8994->micdet_irq) {
3644 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3645 wm8994_mic_irq,
3646 IRQF_TRIGGER_RISING,
3647 "Mic1 detect",
3648 wm8994);
3649 if (ret != 0)
3650 dev_warn(codec->dev,
3651 "Failed to request Mic1 detect IRQ: %d\n",
3652 ret);
3653 }
3654
3655 ret = wm8994_request_irq(wm8994->wm8994,
3656 WM8994_IRQ_MIC1_SHRT,
3657 wm8994_mic_irq, "Mic 1 short",
3658 wm8994);
3659 if (ret != 0)
3660 dev_warn(codec->dev,
3661 "Failed to request Mic1 short IRQ: %d\n",
3662 ret);
3663
3664 ret = wm8994_request_irq(wm8994->wm8994,
3665 WM8994_IRQ_MIC2_DET,
3666 wm8994_mic_irq, "Mic 2 detect",
3667 wm8994);
3668 if (ret != 0)
3669 dev_warn(codec->dev,
3670 "Failed to request Mic2 detect IRQ: %d\n",
3671 ret);
3672
3673 ret = wm8994_request_irq(wm8994->wm8994,
3674 WM8994_IRQ_MIC2_SHRT,
3675 wm8994_mic_irq, "Mic 2 short",
3676 wm8994);
3677 if (ret != 0)
3678 dev_warn(codec->dev,
3679 "Failed to request Mic2 short IRQ: %d\n",
3680 ret);
3681 break;
3682
3683 case WM8958:
3684 case WM1811:
3685 if (wm8994->micdet_irq) {
3686 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3687 wm8958_mic_irq,
3688 IRQF_TRIGGER_RISING,
3689 "Mic detect",
3690 wm8994);
3691 if (ret != 0)
3692 dev_warn(codec->dev,
3693 "Failed to request Mic detect IRQ: %d\n",
3694 ret);
3695 }
3696 }
3697
3698 switch (control->type) {
3699 case WM1811:
3700 if (wm8994->revision > 1) {
3701 ret = wm8994_request_irq(wm8994->wm8994,
3702 WM8994_IRQ_GPIO(6),
3703 wm1811_jackdet_irq, "JACKDET",
3704 wm8994);
3705 if (ret == 0)
3706 wm8994->jackdet = true;
3707 }
3708 break;
3709 default:
3710 break;
3711 }
3712
3713 wm8994->fll_locked_irq = true;
3714 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
3715 ret = wm8994_request_irq(wm8994->wm8994,
3716 WM8994_IRQ_FLL1_LOCK + i,
3717 wm8994_fll_locked_irq, "FLL lock",
3718 &wm8994->fll_locked[i]);
3719 if (ret != 0)
3720 wm8994->fll_locked_irq = false;
3721 }
3722
3723 /* Make sure we can read from the GPIOs if they're inputs */
3724 pm_runtime_get_sync(codec->dev);
3725
3726 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3727 * configured on init - if a system wants to do this dynamically
3728 * at runtime we can deal with that then.
3729 */
3730 ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
3731 if (ret < 0) {
3732 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3733 goto err_irq;
3734 }
3735 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3736 wm8994->lrclk_shared[0] = 1;
3737 wm8994_dai[0].symmetric_rates = 1;
3738 } else {
3739 wm8994->lrclk_shared[0] = 0;
3740 }
3741
3742 ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
3743 if (ret < 0) {
3744 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3745 goto err_irq;
3746 }
3747 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3748 wm8994->lrclk_shared[1] = 1;
3749 wm8994_dai[1].symmetric_rates = 1;
3750 } else {
3751 wm8994->lrclk_shared[1] = 0;
3752 }
3753
3754 pm_runtime_put(codec->dev);
3755
3756 /* Latch volume updates (right only; we always do left then right). */
3757 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3758 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3759 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3760 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3761 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3762 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3763 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3764 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3765 snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3766 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3767 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3768 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3769 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3770 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3771 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3772 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3773 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3774 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3775 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3776 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3777 snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3778 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3779 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3780 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3781 snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3782 WM8994_DAC1_VU, WM8994_DAC1_VU);
3783 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3784 WM8994_DAC1_VU, WM8994_DAC1_VU);
3785 snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3786 WM8994_DAC2_VU, WM8994_DAC2_VU);
3787 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3788 WM8994_DAC2_VU, WM8994_DAC2_VU);
3789
3790 /* Set the low bit of the 3D stereo depth so TLV matches */
3791 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3792 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3793 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3794 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3795 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3796 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3797 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3798 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3799 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3800
3801 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3802 * use this; it only affects behaviour on idle TDM clock
3803 * cycles. */
3804 switch (control->type) {
3805 case WM8994:
3806 case WM8958:
3807 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3808 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3809 break;
3810 default:
3811 break;
3812 }
3813
3814 /* Put MICBIAS into bypass mode by default on newer devices */
3815 switch (control->type) {
3816 case WM8958:
3817 case WM1811:
3818 snd_soc_update_bits(codec, WM8958_MICBIAS1,
3819 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
3820 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3821 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
3822 break;
3823 default:
3824 break;
3825 }
3826
3827 wm8994_update_class_w(codec);
3828
3829 wm8994_handle_pdata(wm8994);
3830
3831 wm_hubs_add_analogue_controls(codec);
3832 snd_soc_add_codec_controls(codec, wm8994_snd_controls,
3833 ARRAY_SIZE(wm8994_snd_controls));
3834 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3835 ARRAY_SIZE(wm8994_dapm_widgets));
3836
3837 switch (control->type) {
3838 case WM8994:
3839 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3840 ARRAY_SIZE(wm8994_specific_dapm_widgets));
3841 if (wm8994->revision < 4) {
3842 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3843 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3844 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3845 ARRAY_SIZE(wm8994_adc_revd_widgets));
3846 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3847 ARRAY_SIZE(wm8994_dac_revd_widgets));
3848 } else {
3849 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3850 ARRAY_SIZE(wm8994_lateclk_widgets));
3851 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3852 ARRAY_SIZE(wm8994_adc_widgets));
3853 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3854 ARRAY_SIZE(wm8994_dac_widgets));
3855 }
3856 break;
3857 case WM8958:
3858 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
3859 ARRAY_SIZE(wm8958_snd_controls));
3860 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3861 ARRAY_SIZE(wm8958_dapm_widgets));
3862 if (wm8994->revision < 1) {
3863 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3864 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3865 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3866 ARRAY_SIZE(wm8994_adc_revd_widgets));
3867 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3868 ARRAY_SIZE(wm8994_dac_revd_widgets));
3869 } else {
3870 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3871 ARRAY_SIZE(wm8994_lateclk_widgets));
3872 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3873 ARRAY_SIZE(wm8994_adc_widgets));
3874 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3875 ARRAY_SIZE(wm8994_dac_widgets));
3876 }
3877 break;
3878
3879 case WM1811:
3880 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
3881 ARRAY_SIZE(wm8958_snd_controls));
3882 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3883 ARRAY_SIZE(wm8958_dapm_widgets));
3884 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3885 ARRAY_SIZE(wm8994_lateclk_widgets));
3886 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3887 ARRAY_SIZE(wm8994_adc_widgets));
3888 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3889 ARRAY_SIZE(wm8994_dac_widgets));
3890 break;
3891 }
3892
3893 wm_hubs_add_analogue_routes(codec, 0, 0);
3894 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3895
3896 switch (control->type) {
3897 case WM8994:
3898 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3899 ARRAY_SIZE(wm8994_intercon));
3900
3901 if (wm8994->revision < 4) {
3902 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3903 ARRAY_SIZE(wm8994_revd_intercon));
3904 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3905 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3906 } else {
3907 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3908 ARRAY_SIZE(wm8994_lateclk_intercon));
3909 }
3910 break;
3911 case WM8958:
3912 if (wm8994->revision < 1) {
3913 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3914 ARRAY_SIZE(wm8994_revd_intercon));
3915 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3916 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3917 } else {
3918 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3919 ARRAY_SIZE(wm8994_lateclk_intercon));
3920 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3921 ARRAY_SIZE(wm8958_intercon));
3922 }
3923
3924 wm8958_dsp2_init(codec);
3925 break;
3926 case WM1811:
3927 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3928 ARRAY_SIZE(wm8994_lateclk_intercon));
3929 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3930 ARRAY_SIZE(wm8958_intercon));
3931 break;
3932 }
3933
3934 return 0;
3935
3936 err_irq:
3937 if (wm8994->jackdet)
3938 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
3939 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
3940 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
3941 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
3942 if (wm8994->micdet_irq)
3943 free_irq(wm8994->micdet_irq, wm8994);
3944 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3945 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
3946 &wm8994->fll_locked[i]);
3947 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3948 &wm8994->hubs);
3949 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3950 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3951 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
3952
3953 return ret;
3954 }
3955
3956 static int wm8994_codec_remove(struct snd_soc_codec *codec)
3957 {
3958 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3959 struct wm8994 *control = wm8994->wm8994;
3960 int i;
3961
3962 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3963
3964 pm_runtime_disable(codec->dev);
3965
3966 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3967 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
3968 &wm8994->fll_locked[i]);
3969
3970 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3971 &wm8994->hubs);
3972 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3973 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3974 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
3975
3976 if (wm8994->jackdet)
3977 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
3978
3979 switch (control->type) {
3980 case WM8994:
3981 if (wm8994->micdet_irq)
3982 free_irq(wm8994->micdet_irq, wm8994);
3983 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
3984 wm8994);
3985 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
3986 wm8994);
3987 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3988 wm8994);
3989 break;
3990
3991 case WM1811:
3992 case WM8958:
3993 if (wm8994->micdet_irq)
3994 free_irq(wm8994->micdet_irq, wm8994);
3995 break;
3996 }
3997 release_firmware(wm8994->mbc);
3998 release_firmware(wm8994->mbc_vss);
3999 release_firmware(wm8994->enh_eq);
4000 kfree(wm8994->retune_mobile_texts);
4001 return 0;
4002 }
4003
4004 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4005 .probe = wm8994_codec_probe,
4006 .remove = wm8994_codec_remove,
4007 .suspend = wm8994_codec_suspend,
4008 .resume = wm8994_codec_resume,
4009 .set_bias_level = wm8994_set_bias_level,
4010 };
4011
4012 static int __devinit wm8994_probe(struct platform_device *pdev)
4013 {
4014 struct wm8994_priv *wm8994;
4015
4016 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4017 GFP_KERNEL);
4018 if (wm8994 == NULL)
4019 return -ENOMEM;
4020 platform_set_drvdata(pdev, wm8994);
4021
4022 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
4023 wm8994->pdata = dev_get_platdata(pdev->dev.parent);
4024
4025 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4026 wm8994_dai, ARRAY_SIZE(wm8994_dai));
4027 }
4028
4029 static int __devexit wm8994_remove(struct platform_device *pdev)
4030 {
4031 snd_soc_unregister_codec(&pdev->dev);
4032 return 0;
4033 }
4034
4035 #ifdef CONFIG_PM_SLEEP
4036 static int wm8994_suspend(struct device *dev)
4037 {
4038 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4039
4040 /* Drop down to power saving mode when system is suspended */
4041 if (wm8994->jackdet && !wm8994->active_refcount)
4042 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4043 WM1811_JACKDET_MODE_MASK,
4044 wm8994->jackdet_mode);
4045
4046 return 0;
4047 }
4048
4049 static int wm8994_resume(struct device *dev)
4050 {
4051 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4052
4053 if (wm8994->jackdet && wm8994->jack_cb)
4054 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4055 WM1811_JACKDET_MODE_MASK,
4056 WM1811_JACKDET_MODE_AUDIO);
4057
4058 return 0;
4059 }
4060 #endif
4061
4062 static const struct dev_pm_ops wm8994_pm_ops = {
4063 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4064 };
4065
4066 static struct platform_driver wm8994_codec_driver = {
4067 .driver = {
4068 .name = "wm8994-codec",
4069 .owner = THIS_MODULE,
4070 .pm = &wm8994_pm_ops,
4071 },
4072 .probe = wm8994_probe,
4073 .remove = __devexit_p(wm8994_remove),
4074 };
4075
4076 module_platform_driver(wm8994_codec_driver);
4077
4078 MODULE_DESCRIPTION("ASoC WM8994 driver");
4079 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4080 MODULE_LICENSE("GPL");
4081 MODULE_ALIAS("platform:wm8994-codec");
Linux kernel - Deliverables
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