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irq_domain: correct a minor wrong comment for linear revmap
[deliverable/linux.git] / sound / soc / codecs / wm8994.c
1 /*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/jack.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <trace/events/asoc.h>
32
33 #include <linux/mfd/wm8994/core.h>
34 #include <linux/mfd/wm8994/registers.h>
35 #include <linux/mfd/wm8994/pdata.h>
36 #include <linux/mfd/wm8994/gpio.h>
37
38 #include "wm8994.h"
39 #include "wm_hubs.h"
40
41 #define WM1811_JACKDET_MODE_NONE 0x0000
42 #define WM1811_JACKDET_MODE_JACK 0x0100
43 #define WM1811_JACKDET_MODE_MIC 0x0080
44 #define WM1811_JACKDET_MODE_AUDIO 0x0180
45
46 #define WM8994_NUM_DRC 3
47 #define WM8994_NUM_EQ 3
48
49 static int wm8994_drc_base[] = {
50 WM8994_AIF1_DRC1_1,
51 WM8994_AIF1_DRC2_1,
52 WM8994_AIF2_DRC_1,
53 };
54
55 static int wm8994_retune_mobile_base[] = {
56 WM8994_AIF1_DAC1_EQ_GAINS_1,
57 WM8994_AIF1_DAC2_EQ_GAINS_1,
58 WM8994_AIF2_EQ_GAINS_1,
59 };
60
61 static void wm8958_default_micdet(u16 status, void *data);
62
63 static const struct wm8958_micd_rate micdet_rates[] = {
64 { 32768, true, 1, 4 },
65 { 32768, false, 1, 1 },
66 { 44100 * 256, true, 7, 10 },
67 { 44100 * 256, false, 7, 10 },
68 };
69
70 static const struct wm8958_micd_rate jackdet_rates[] = {
71 { 32768, true, 0, 1 },
72 { 32768, false, 0, 1 },
73 { 44100 * 256, true, 10, 10 },
74 { 44100 * 256, false, 7, 8 },
75 };
76
77 static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
78 {
79 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
80 int best, i, sysclk, val;
81 bool idle;
82 const struct wm8958_micd_rate *rates;
83 int num_rates;
84
85 if (!(wm8994->pdata && wm8994->pdata->micd_rates) &&
86 wm8994->jack_cb != wm8958_default_micdet)
87 return;
88
89 idle = !wm8994->jack_mic;
90
91 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
92 if (sysclk & WM8994_SYSCLK_SRC)
93 sysclk = wm8994->aifclk[1];
94 else
95 sysclk = wm8994->aifclk[0];
96
97 if (wm8994->pdata && wm8994->pdata->micd_rates) {
98 rates = wm8994->pdata->micd_rates;
99 num_rates = wm8994->pdata->num_micd_rates;
100 } else if (wm8994->jackdet) {
101 rates = jackdet_rates;
102 num_rates = ARRAY_SIZE(jackdet_rates);
103 } else {
104 rates = micdet_rates;
105 num_rates = ARRAY_SIZE(micdet_rates);
106 }
107
108 best = 0;
109 for (i = 0; i < num_rates; i++) {
110 if (rates[i].idle != idle)
111 continue;
112 if (abs(rates[i].sysclk - sysclk) <
113 abs(rates[best].sysclk - sysclk))
114 best = i;
115 else if (rates[best].idle != idle)
116 best = i;
117 }
118
119 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
120 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
121
122 dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n",
123 rates[best].start, rates[best].rate, sysclk,
124 idle ? "idle" : "active");
125
126 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
127 WM8958_MICD_BIAS_STARTTIME_MASK |
128 WM8958_MICD_RATE_MASK, val);
129 }
130
131 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
132 {
133 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
134 int rate;
135 int reg1 = 0;
136 int offset;
137
138 if (aif)
139 offset = 4;
140 else
141 offset = 0;
142
143 switch (wm8994->sysclk[aif]) {
144 case WM8994_SYSCLK_MCLK1:
145 rate = wm8994->mclk[0];
146 break;
147
148 case WM8994_SYSCLK_MCLK2:
149 reg1 |= 0x8;
150 rate = wm8994->mclk[1];
151 break;
152
153 case WM8994_SYSCLK_FLL1:
154 reg1 |= 0x10;
155 rate = wm8994->fll[0].out;
156 break;
157
158 case WM8994_SYSCLK_FLL2:
159 reg1 |= 0x18;
160 rate = wm8994->fll[1].out;
161 break;
162
163 default:
164 return -EINVAL;
165 }
166
167 if (rate >= 13500000) {
168 rate /= 2;
169 reg1 |= WM8994_AIF1CLK_DIV;
170
171 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
172 aif + 1, rate);
173 }
174
175 wm8994->aifclk[aif] = rate;
176
177 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
178 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
179 reg1);
180
181 return 0;
182 }
183
184 static int configure_clock(struct snd_soc_codec *codec)
185 {
186 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
187 int change, new;
188
189 /* Bring up the AIF clocks first */
190 configure_aif_clock(codec, 0);
191 configure_aif_clock(codec, 1);
192
193 /* Then switch CLK_SYS over to the higher of them; a change
194 * can only happen as a result of a clocking change which can
195 * only be made outside of DAPM so we can safely redo the
196 * clocking.
197 */
198
199 /* If they're equal it doesn't matter which is used */
200 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
201 wm8958_micd_set_rate(codec);
202 return 0;
203 }
204
205 if (wm8994->aifclk[0] < wm8994->aifclk[1])
206 new = WM8994_SYSCLK_SRC;
207 else
208 new = 0;
209
210 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
211 WM8994_SYSCLK_SRC, new);
212 if (change)
213 snd_soc_dapm_sync(&codec->dapm);
214
215 wm8958_micd_set_rate(codec);
216
217 return 0;
218 }
219
220 static int check_clk_sys(struct snd_soc_dapm_widget *source,
221 struct snd_soc_dapm_widget *sink)
222 {
223 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
224 const char *clk;
225
226 /* Check what we're currently using for CLK_SYS */
227 if (reg & WM8994_SYSCLK_SRC)
228 clk = "AIF2CLK";
229 else
230 clk = "AIF1CLK";
231
232 return strcmp(source->name, clk) == 0;
233 }
234
235 static const char *sidetone_hpf_text[] = {
236 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
237 };
238
239 static const struct soc_enum sidetone_hpf =
240 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
241
242 static const char *adc_hpf_text[] = {
243 "HiFi", "Voice 1", "Voice 2", "Voice 3"
244 };
245
246 static const struct soc_enum aif1adc1_hpf =
247 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
248
249 static const struct soc_enum aif1adc2_hpf =
250 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
251
252 static const struct soc_enum aif2adc_hpf =
253 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
254
255 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
256 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
257 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
258 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
259 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
260 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
261 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
262
263 #define WM8994_DRC_SWITCH(xname, reg, shift) \
264 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
265 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
266 .put = wm8994_put_drc_sw, \
267 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
268
269 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
270 struct snd_ctl_elem_value *ucontrol)
271 {
272 struct soc_mixer_control *mc =
273 (struct soc_mixer_control *)kcontrol->private_value;
274 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
275 int mask, ret;
276
277 /* Can't enable both ADC and DAC paths simultaneously */
278 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
279 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
280 WM8994_AIF1ADC1R_DRC_ENA_MASK;
281 else
282 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
283
284 ret = snd_soc_read(codec, mc->reg);
285 if (ret < 0)
286 return ret;
287 if (ret & mask)
288 return -EINVAL;
289
290 return snd_soc_put_volsw(kcontrol, ucontrol);
291 }
292
293 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
294 {
295 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
296 struct wm8994_pdata *pdata = wm8994->pdata;
297 int base = wm8994_drc_base[drc];
298 int cfg = wm8994->drc_cfg[drc];
299 int save, i;
300
301 /* Save any enables; the configuration should clear them. */
302 save = snd_soc_read(codec, base);
303 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
304 WM8994_AIF1ADC1R_DRC_ENA;
305
306 for (i = 0; i < WM8994_DRC_REGS; i++)
307 snd_soc_update_bits(codec, base + i, 0xffff,
308 pdata->drc_cfgs[cfg].regs[i]);
309
310 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
311 WM8994_AIF1ADC1L_DRC_ENA |
312 WM8994_AIF1ADC1R_DRC_ENA, save);
313 }
314
315 /* Icky as hell but saves code duplication */
316 static int wm8994_get_drc(const char *name)
317 {
318 if (strcmp(name, "AIF1DRC1 Mode") == 0)
319 return 0;
320 if (strcmp(name, "AIF1DRC2 Mode") == 0)
321 return 1;
322 if (strcmp(name, "AIF2DRC Mode") == 0)
323 return 2;
324 return -EINVAL;
325 }
326
327 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
328 struct snd_ctl_elem_value *ucontrol)
329 {
330 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
331 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
332 struct wm8994_pdata *pdata = wm8994->pdata;
333 int drc = wm8994_get_drc(kcontrol->id.name);
334 int value = ucontrol->value.integer.value[0];
335
336 if (drc < 0)
337 return drc;
338
339 if (value >= pdata->num_drc_cfgs)
340 return -EINVAL;
341
342 wm8994->drc_cfg[drc] = value;
343
344 wm8994_set_drc(codec, drc);
345
346 return 0;
347 }
348
349 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
350 struct snd_ctl_elem_value *ucontrol)
351 {
352 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
353 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
354 int drc = wm8994_get_drc(kcontrol->id.name);
355
356 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
357
358 return 0;
359 }
360
361 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
362 {
363 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
364 struct wm8994_pdata *pdata = wm8994->pdata;
365 int base = wm8994_retune_mobile_base[block];
366 int iface, best, best_val, save, i, cfg;
367
368 if (!pdata || !wm8994->num_retune_mobile_texts)
369 return;
370
371 switch (block) {
372 case 0:
373 case 1:
374 iface = 0;
375 break;
376 case 2:
377 iface = 1;
378 break;
379 default:
380 return;
381 }
382
383 /* Find the version of the currently selected configuration
384 * with the nearest sample rate. */
385 cfg = wm8994->retune_mobile_cfg[block];
386 best = 0;
387 best_val = INT_MAX;
388 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
389 if (strcmp(pdata->retune_mobile_cfgs[i].name,
390 wm8994->retune_mobile_texts[cfg]) == 0 &&
391 abs(pdata->retune_mobile_cfgs[i].rate
392 - wm8994->dac_rates[iface]) < best_val) {
393 best = i;
394 best_val = abs(pdata->retune_mobile_cfgs[i].rate
395 - wm8994->dac_rates[iface]);
396 }
397 }
398
399 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
400 block,
401 pdata->retune_mobile_cfgs[best].name,
402 pdata->retune_mobile_cfgs[best].rate,
403 wm8994->dac_rates[iface]);
404
405 /* The EQ will be disabled while reconfiguring it, remember the
406 * current configuration.
407 */
408 save = snd_soc_read(codec, base);
409 save &= WM8994_AIF1DAC1_EQ_ENA;
410
411 for (i = 0; i < WM8994_EQ_REGS; i++)
412 snd_soc_update_bits(codec, base + i, 0xffff,
413 pdata->retune_mobile_cfgs[best].regs[i]);
414
415 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
416 }
417
418 /* Icky as hell but saves code duplication */
419 static int wm8994_get_retune_mobile_block(const char *name)
420 {
421 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
422 return 0;
423 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
424 return 1;
425 if (strcmp(name, "AIF2 EQ Mode") == 0)
426 return 2;
427 return -EINVAL;
428 }
429
430 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
431 struct snd_ctl_elem_value *ucontrol)
432 {
433 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
434 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
435 struct wm8994_pdata *pdata = wm8994->pdata;
436 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
437 int value = ucontrol->value.integer.value[0];
438
439 if (block < 0)
440 return block;
441
442 if (value >= pdata->num_retune_mobile_cfgs)
443 return -EINVAL;
444
445 wm8994->retune_mobile_cfg[block] = value;
446
447 wm8994_set_retune_mobile(codec, block);
448
449 return 0;
450 }
451
452 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
453 struct snd_ctl_elem_value *ucontrol)
454 {
455 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
456 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
457 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
458
459 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
460
461 return 0;
462 }
463
464 static const char *aif_chan_src_text[] = {
465 "Left", "Right"
466 };
467
468 static const struct soc_enum aif1adcl_src =
469 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
470
471 static const struct soc_enum aif1adcr_src =
472 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
473
474 static const struct soc_enum aif2adcl_src =
475 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
476
477 static const struct soc_enum aif2adcr_src =
478 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
479
480 static const struct soc_enum aif1dacl_src =
481 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
482
483 static const struct soc_enum aif1dacr_src =
484 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
485
486 static const struct soc_enum aif2dacl_src =
487 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
488
489 static const struct soc_enum aif2dacr_src =
490 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
491
492 static const char *osr_text[] = {
493 "Low Power", "High Performance",
494 };
495
496 static const struct soc_enum dac_osr =
497 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
498
499 static const struct soc_enum adc_osr =
500 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
501
502 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
503 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
504 WM8994_AIF1_ADC1_RIGHT_VOLUME,
505 1, 119, 0, digital_tlv),
506 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
507 WM8994_AIF1_ADC2_RIGHT_VOLUME,
508 1, 119, 0, digital_tlv),
509 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
510 WM8994_AIF2_ADC_RIGHT_VOLUME,
511 1, 119, 0, digital_tlv),
512
513 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
514 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
515 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
516 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
517
518 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
519 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
520 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
521 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
522
523 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
524 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
525 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
526 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
527 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
528 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
529
530 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
531 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
532
533 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
534 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
535 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
536
537 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
538 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
539 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
540
541 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
542 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
543 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
544
545 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
546 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
547 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
548
549 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
550 5, 12, 0, st_tlv),
551 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
552 0, 12, 0, st_tlv),
553 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
554 5, 12, 0, st_tlv),
555 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
556 0, 12, 0, st_tlv),
557 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
558 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
559
560 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
561 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
562
563 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
564 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
565
566 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
567 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
568
569 SOC_ENUM("ADC OSR", adc_osr),
570 SOC_ENUM("DAC OSR", dac_osr),
571
572 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
573 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
574 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
575 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
576
577 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
578 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
579 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
580 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
581
582 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
583 6, 1, 1, wm_hubs_spkmix_tlv),
584 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
585 2, 1, 1, wm_hubs_spkmix_tlv),
586
587 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
588 6, 1, 1, wm_hubs_spkmix_tlv),
589 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
590 2, 1, 1, wm_hubs_spkmix_tlv),
591
592 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
593 10, 15, 0, wm8994_3d_tlv),
594 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
595 8, 1, 0),
596 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
597 10, 15, 0, wm8994_3d_tlv),
598 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
599 8, 1, 0),
600 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
601 10, 15, 0, wm8994_3d_tlv),
602 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
603 8, 1, 0),
604 };
605
606 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
607 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
608 eq_tlv),
609 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
610 eq_tlv),
611 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
612 eq_tlv),
613 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
614 eq_tlv),
615 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
616 eq_tlv),
617
618 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
619 eq_tlv),
620 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
621 eq_tlv),
622 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
623 eq_tlv),
624 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
625 eq_tlv),
626 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
627 eq_tlv),
628
629 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
630 eq_tlv),
631 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
632 eq_tlv),
633 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
634 eq_tlv),
635 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
636 eq_tlv),
637 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
638 eq_tlv),
639 };
640
641 static const char *wm8958_ng_text[] = {
642 "30ms", "125ms", "250ms", "500ms",
643 };
644
645 static const struct soc_enum wm8958_aif1dac1_ng_hold =
646 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
647 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
648
649 static const struct soc_enum wm8958_aif1dac2_ng_hold =
650 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
651 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
652
653 static const struct soc_enum wm8958_aif2dac_ng_hold =
654 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
655 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
656
657 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
658 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
659
660 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
661 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
662 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
663 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
664 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
665 7, 1, ng_tlv),
666
667 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
668 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
669 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
670 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
671 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
672 7, 1, ng_tlv),
673
674 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
675 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
676 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
677 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
678 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
679 7, 1, ng_tlv),
680 };
681
682 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
683 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
684 mixin_boost_tlv),
685 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
686 mixin_boost_tlv),
687 };
688
689 /* We run all mode setting through a function to enforce audio mode */
690 static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
691 {
692 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
693
694 if (!wm8994->jackdet || !wm8994->jack_cb)
695 return;
696
697 if (!wm8994->jackdet || !wm8994->jack_cb)
698 return;
699
700 if (wm8994->active_refcount)
701 mode = WM1811_JACKDET_MODE_AUDIO;
702
703 if (mode == wm8994->jackdet_mode)
704 return;
705
706 wm8994->jackdet_mode = mode;
707
708 /* Always use audio mode to detect while the system is active */
709 if (mode != WM1811_JACKDET_MODE_NONE)
710 mode = WM1811_JACKDET_MODE_AUDIO;
711
712 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
713 WM1811_JACKDET_MODE_MASK, mode);
714 }
715
716 static void active_reference(struct snd_soc_codec *codec)
717 {
718 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
719
720 mutex_lock(&wm8994->accdet_lock);
721
722 wm8994->active_refcount++;
723
724 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
725 wm8994->active_refcount);
726
727 /* If we're using jack detection go into audio mode */
728 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
729
730 mutex_unlock(&wm8994->accdet_lock);
731 }
732
733 static void active_dereference(struct snd_soc_codec *codec)
734 {
735 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
736 u16 mode;
737
738 mutex_lock(&wm8994->accdet_lock);
739
740 wm8994->active_refcount--;
741
742 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
743 wm8994->active_refcount);
744
745 if (wm8994->active_refcount == 0) {
746 /* Go into appropriate detection only mode */
747 if (wm8994->jack_mic || wm8994->mic_detecting)
748 mode = WM1811_JACKDET_MODE_MIC;
749 else
750 mode = WM1811_JACKDET_MODE_JACK;
751
752 wm1811_jackdet_set_mode(codec, mode);
753 }
754
755 mutex_unlock(&wm8994->accdet_lock);
756 }
757
758 static int clk_sys_event(struct snd_soc_dapm_widget *w,
759 struct snd_kcontrol *kcontrol, int event)
760 {
761 struct snd_soc_codec *codec = w->codec;
762
763 switch (event) {
764 case SND_SOC_DAPM_PRE_PMU:
765 return configure_clock(codec);
766
767 case SND_SOC_DAPM_POST_PMD:
768 configure_clock(codec);
769 break;
770 }
771
772 return 0;
773 }
774
775 static void vmid_reference(struct snd_soc_codec *codec)
776 {
777 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
778
779 pm_runtime_get_sync(codec->dev);
780
781 wm8994->vmid_refcount++;
782
783 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
784 wm8994->vmid_refcount);
785
786 if (wm8994->vmid_refcount == 1) {
787 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
788 WM8994_LINEOUT1_DISCH |
789 WM8994_LINEOUT2_DISCH, 0);
790
791 wm_hubs_vmid_ena(codec);
792
793 switch (wm8994->vmid_mode) {
794 default:
795 WARN_ON(NULL == "Invalid VMID mode");
796 case WM8994_VMID_NORMAL:
797 /* Startup bias, VMID ramp & buffer */
798 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
799 WM8994_BIAS_SRC |
800 WM8994_VMID_DISCH |
801 WM8994_STARTUP_BIAS_ENA |
802 WM8994_VMID_BUF_ENA |
803 WM8994_VMID_RAMP_MASK,
804 WM8994_BIAS_SRC |
805 WM8994_STARTUP_BIAS_ENA |
806 WM8994_VMID_BUF_ENA |
807 (0x3 << WM8994_VMID_RAMP_SHIFT));
808
809 /* Main bias enable, VMID=2x40k */
810 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
811 WM8994_BIAS_ENA |
812 WM8994_VMID_SEL_MASK,
813 WM8994_BIAS_ENA | 0x2);
814
815 msleep(50);
816
817 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
818 WM8994_VMID_RAMP_MASK |
819 WM8994_BIAS_SRC,
820 0);
821 break;
822
823 case WM8994_VMID_FORCE:
824 /* Startup bias, slow VMID ramp & buffer */
825 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
826 WM8994_BIAS_SRC |
827 WM8994_VMID_DISCH |
828 WM8994_STARTUP_BIAS_ENA |
829 WM8994_VMID_BUF_ENA |
830 WM8994_VMID_RAMP_MASK,
831 WM8994_BIAS_SRC |
832 WM8994_STARTUP_BIAS_ENA |
833 WM8994_VMID_BUF_ENA |
834 (0x2 << WM8994_VMID_RAMP_SHIFT));
835
836 /* Main bias enable, VMID=2x40k */
837 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
838 WM8994_BIAS_ENA |
839 WM8994_VMID_SEL_MASK,
840 WM8994_BIAS_ENA | 0x2);
841
842 msleep(400);
843
844 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
845 WM8994_VMID_RAMP_MASK |
846 WM8994_BIAS_SRC,
847 0);
848 break;
849 }
850 }
851 }
852
853 static void vmid_dereference(struct snd_soc_codec *codec)
854 {
855 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
856
857 wm8994->vmid_refcount--;
858
859 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
860 wm8994->vmid_refcount);
861
862 if (wm8994->vmid_refcount == 0) {
863 if (wm8994->hubs.lineout1_se)
864 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
865 WM8994_LINEOUT1N_ENA |
866 WM8994_LINEOUT1P_ENA,
867 WM8994_LINEOUT1N_ENA |
868 WM8994_LINEOUT1P_ENA);
869
870 if (wm8994->hubs.lineout2_se)
871 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
872 WM8994_LINEOUT2N_ENA |
873 WM8994_LINEOUT2P_ENA,
874 WM8994_LINEOUT2N_ENA |
875 WM8994_LINEOUT2P_ENA);
876
877 /* Start discharging VMID */
878 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
879 WM8994_BIAS_SRC |
880 WM8994_VMID_DISCH,
881 WM8994_BIAS_SRC |
882 WM8994_VMID_DISCH);
883
884 switch (wm8994->vmid_mode) {
885 case WM8994_VMID_FORCE:
886 msleep(350);
887 break;
888 default:
889 break;
890 }
891
892 snd_soc_update_bits(codec, WM8994_ADDITIONAL_CONTROL,
893 WM8994_VROI, WM8994_VROI);
894
895 /* Active discharge */
896 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
897 WM8994_LINEOUT1_DISCH |
898 WM8994_LINEOUT2_DISCH,
899 WM8994_LINEOUT1_DISCH |
900 WM8994_LINEOUT2_DISCH);
901
902 msleep(150);
903
904 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
905 WM8994_LINEOUT1N_ENA |
906 WM8994_LINEOUT1P_ENA |
907 WM8994_LINEOUT2N_ENA |
908 WM8994_LINEOUT2P_ENA, 0);
909
910 snd_soc_update_bits(codec, WM8994_ADDITIONAL_CONTROL,
911 WM8994_VROI, 0);
912
913 /* Switch off startup biases */
914 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
915 WM8994_BIAS_SRC |
916 WM8994_STARTUP_BIAS_ENA |
917 WM8994_VMID_BUF_ENA |
918 WM8994_VMID_RAMP_MASK, 0);
919
920 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
921 WM8994_BIAS_ENA | WM8994_VMID_SEL_MASK, 0);
922
923 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
924 WM8994_VMID_RAMP_MASK, 0);
925 }
926
927 pm_runtime_put(codec->dev);
928 }
929
930 static int vmid_event(struct snd_soc_dapm_widget *w,
931 struct snd_kcontrol *kcontrol, int event)
932 {
933 struct snd_soc_codec *codec = w->codec;
934
935 switch (event) {
936 case SND_SOC_DAPM_PRE_PMU:
937 vmid_reference(codec);
938 break;
939
940 case SND_SOC_DAPM_POST_PMD:
941 vmid_dereference(codec);
942 break;
943 }
944
945 return 0;
946 }
947
948 static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec)
949 {
950 int source = 0; /* GCC flow analysis can't track enable */
951 int reg, reg_r;
952
953 /* We also need the same AIF source for L/R and only one path */
954 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
955 switch (reg) {
956 case WM8994_AIF2DACL_TO_DAC1L:
957 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
958 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
959 break;
960 case WM8994_AIF1DAC2L_TO_DAC1L:
961 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
962 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
963 break;
964 case WM8994_AIF1DAC1L_TO_DAC1L:
965 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
966 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
967 break;
968 default:
969 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
970 return false;
971 }
972
973 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
974 if (reg_r != reg) {
975 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
976 return false;
977 }
978
979 /* Set the source up */
980 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
981 WM8994_CP_DYN_SRC_SEL_MASK, source);
982
983 return true;
984 }
985
986 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
987 struct snd_kcontrol *kcontrol, int event)
988 {
989 struct snd_soc_codec *codec = w->codec;
990 struct wm8994 *control = codec->control_data;
991 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
992 int dac;
993 int adc;
994 int val;
995
996 switch (control->type) {
997 case WM8994:
998 case WM8958:
999 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1000 break;
1001 default:
1002 break;
1003 }
1004
1005 switch (event) {
1006 case SND_SOC_DAPM_PRE_PMU:
1007 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
1008 if ((val & WM8994_AIF1ADCL_SRC) &&
1009 (val & WM8994_AIF1ADCR_SRC))
1010 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1011 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1012 !(val & WM8994_AIF1ADCR_SRC))
1013 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1014 else
1015 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1016 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1017
1018 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
1019 if ((val & WM8994_AIF1DACL_SRC) &&
1020 (val & WM8994_AIF1DACR_SRC))
1021 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1022 else if (!(val & WM8994_AIF1DACL_SRC) &&
1023 !(val & WM8994_AIF1DACR_SRC))
1024 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1025 else
1026 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1027 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1028
1029 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1030 mask, adc);
1031 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1032 mask, dac);
1033 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1034 WM8994_AIF1DSPCLK_ENA |
1035 WM8994_SYSDSPCLK_ENA,
1036 WM8994_AIF1DSPCLK_ENA |
1037 WM8994_SYSDSPCLK_ENA);
1038 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
1039 WM8994_AIF1ADC1R_ENA |
1040 WM8994_AIF1ADC1L_ENA |
1041 WM8994_AIF1ADC2R_ENA |
1042 WM8994_AIF1ADC2L_ENA);
1043 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
1044 WM8994_AIF1DAC1R_ENA |
1045 WM8994_AIF1DAC1L_ENA |
1046 WM8994_AIF1DAC2R_ENA |
1047 WM8994_AIF1DAC2L_ENA);
1048 break;
1049
1050 case SND_SOC_DAPM_PRE_PMD:
1051 case SND_SOC_DAPM_POST_PMD:
1052 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1053 mask, 0);
1054 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1055 mask, 0);
1056
1057 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1058 if (val & WM8994_AIF2DSPCLK_ENA)
1059 val = WM8994_SYSDSPCLK_ENA;
1060 else
1061 val = 0;
1062 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1063 WM8994_SYSDSPCLK_ENA |
1064 WM8994_AIF1DSPCLK_ENA, val);
1065 break;
1066 }
1067
1068 return 0;
1069 }
1070
1071 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1072 struct snd_kcontrol *kcontrol, int event)
1073 {
1074 struct snd_soc_codec *codec = w->codec;
1075 int dac;
1076 int adc;
1077 int val;
1078
1079 switch (event) {
1080 case SND_SOC_DAPM_PRE_PMU:
1081 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1082 if ((val & WM8994_AIF2ADCL_SRC) &&
1083 (val & WM8994_AIF2ADCR_SRC))
1084 adc = WM8994_AIF2ADCR_ENA;
1085 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1086 !(val & WM8994_AIF2ADCR_SRC))
1087 adc = WM8994_AIF2ADCL_ENA;
1088 else
1089 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1090
1091
1092 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1093 if ((val & WM8994_AIF2DACL_SRC) &&
1094 (val & WM8994_AIF2DACR_SRC))
1095 dac = WM8994_AIF2DACR_ENA;
1096 else if (!(val & WM8994_AIF2DACL_SRC) &&
1097 !(val & WM8994_AIF2DACR_SRC))
1098 dac = WM8994_AIF2DACL_ENA;
1099 else
1100 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1101
1102 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1103 WM8994_AIF2ADCL_ENA |
1104 WM8994_AIF2ADCR_ENA, adc);
1105 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1106 WM8994_AIF2DACL_ENA |
1107 WM8994_AIF2DACR_ENA, dac);
1108 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1109 WM8994_AIF2DSPCLK_ENA |
1110 WM8994_SYSDSPCLK_ENA,
1111 WM8994_AIF2DSPCLK_ENA |
1112 WM8994_SYSDSPCLK_ENA);
1113 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1114 WM8994_AIF2ADCL_ENA |
1115 WM8994_AIF2ADCR_ENA,
1116 WM8994_AIF2ADCL_ENA |
1117 WM8994_AIF2ADCR_ENA);
1118 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1119 WM8994_AIF2DACL_ENA |
1120 WM8994_AIF2DACR_ENA,
1121 WM8994_AIF2DACL_ENA |
1122 WM8994_AIF2DACR_ENA);
1123 break;
1124
1125 case SND_SOC_DAPM_PRE_PMD:
1126 case SND_SOC_DAPM_POST_PMD:
1127 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1128 WM8994_AIF2DACL_ENA |
1129 WM8994_AIF2DACR_ENA, 0);
1130 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1131 WM8994_AIF2ADCL_ENA |
1132 WM8994_AIF2ADCR_ENA, 0);
1133
1134 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1135 if (val & WM8994_AIF1DSPCLK_ENA)
1136 val = WM8994_SYSDSPCLK_ENA;
1137 else
1138 val = 0;
1139 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1140 WM8994_SYSDSPCLK_ENA |
1141 WM8994_AIF2DSPCLK_ENA, val);
1142 break;
1143 }
1144
1145 return 0;
1146 }
1147
1148 static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1149 struct snd_kcontrol *kcontrol, int event)
1150 {
1151 struct snd_soc_codec *codec = w->codec;
1152 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1153
1154 switch (event) {
1155 case SND_SOC_DAPM_PRE_PMU:
1156 wm8994->aif1clk_enable = 1;
1157 break;
1158 case SND_SOC_DAPM_POST_PMD:
1159 wm8994->aif1clk_disable = 1;
1160 break;
1161 }
1162
1163 return 0;
1164 }
1165
1166 static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1167 struct snd_kcontrol *kcontrol, int event)
1168 {
1169 struct snd_soc_codec *codec = w->codec;
1170 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1171
1172 switch (event) {
1173 case SND_SOC_DAPM_PRE_PMU:
1174 wm8994->aif2clk_enable = 1;
1175 break;
1176 case SND_SOC_DAPM_POST_PMD:
1177 wm8994->aif2clk_disable = 1;
1178 break;
1179 }
1180
1181 return 0;
1182 }
1183
1184 static int late_enable_ev(struct snd_soc_dapm_widget *w,
1185 struct snd_kcontrol *kcontrol, int event)
1186 {
1187 struct snd_soc_codec *codec = w->codec;
1188 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1189
1190 switch (event) {
1191 case SND_SOC_DAPM_PRE_PMU:
1192 if (wm8994->aif1clk_enable) {
1193 aif1clk_ev(w, kcontrol, event);
1194 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1195 WM8994_AIF1CLK_ENA_MASK,
1196 WM8994_AIF1CLK_ENA);
1197 wm8994->aif1clk_enable = 0;
1198 }
1199 if (wm8994->aif2clk_enable) {
1200 aif2clk_ev(w, kcontrol, event);
1201 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1202 WM8994_AIF2CLK_ENA_MASK,
1203 WM8994_AIF2CLK_ENA);
1204 wm8994->aif2clk_enable = 0;
1205 }
1206 break;
1207 }
1208
1209 /* We may also have postponed startup of DSP, handle that. */
1210 wm8958_aif_ev(w, kcontrol, event);
1211
1212 return 0;
1213 }
1214
1215 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1216 struct snd_kcontrol *kcontrol, int event)
1217 {
1218 struct snd_soc_codec *codec = w->codec;
1219 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1220
1221 switch (event) {
1222 case SND_SOC_DAPM_POST_PMD:
1223 if (wm8994->aif1clk_disable) {
1224 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1225 WM8994_AIF1CLK_ENA_MASK, 0);
1226 aif1clk_ev(w, kcontrol, event);
1227 wm8994->aif1clk_disable = 0;
1228 }
1229 if (wm8994->aif2clk_disable) {
1230 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1231 WM8994_AIF2CLK_ENA_MASK, 0);
1232 aif2clk_ev(w, kcontrol, event);
1233 wm8994->aif2clk_disable = 0;
1234 }
1235 break;
1236 }
1237
1238 return 0;
1239 }
1240
1241 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1242 struct snd_kcontrol *kcontrol, int event)
1243 {
1244 late_enable_ev(w, kcontrol, event);
1245 return 0;
1246 }
1247
1248 static int micbias_ev(struct snd_soc_dapm_widget *w,
1249 struct snd_kcontrol *kcontrol, int event)
1250 {
1251 late_enable_ev(w, kcontrol, event);
1252 return 0;
1253 }
1254
1255 static int dac_ev(struct snd_soc_dapm_widget *w,
1256 struct snd_kcontrol *kcontrol, int event)
1257 {
1258 struct snd_soc_codec *codec = w->codec;
1259 unsigned int mask = 1 << w->shift;
1260
1261 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1262 mask, mask);
1263 return 0;
1264 }
1265
1266 static const char *adc_mux_text[] = {
1267 "ADC",
1268 "DMIC",
1269 };
1270
1271 static const struct soc_enum adc_enum =
1272 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1273
1274 static const struct snd_kcontrol_new adcl_mux =
1275 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1276
1277 static const struct snd_kcontrol_new adcr_mux =
1278 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1279
1280 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1281 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1282 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1283 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1284 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1285 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1286 };
1287
1288 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1289 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1290 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1291 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1292 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1293 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1294 };
1295
1296 /* Debugging; dump chip status after DAPM transitions */
1297 static int post_ev(struct snd_soc_dapm_widget *w,
1298 struct snd_kcontrol *kcontrol, int event)
1299 {
1300 struct snd_soc_codec *codec = w->codec;
1301 dev_dbg(codec->dev, "SRC status: %x\n",
1302 snd_soc_read(codec,
1303 WM8994_RATE_STATUS));
1304 return 0;
1305 }
1306
1307 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1308 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1309 1, 1, 0),
1310 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1311 0, 1, 0),
1312 };
1313
1314 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1315 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1316 1, 1, 0),
1317 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1318 0, 1, 0),
1319 };
1320
1321 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1322 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1323 1, 1, 0),
1324 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1325 0, 1, 0),
1326 };
1327
1328 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1329 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1330 1, 1, 0),
1331 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1332 0, 1, 0),
1333 };
1334
1335 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1336 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1337 5, 1, 0),
1338 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1339 4, 1, 0),
1340 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1341 2, 1, 0),
1342 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1343 1, 1, 0),
1344 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1345 0, 1, 0),
1346 };
1347
1348 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1349 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1350 5, 1, 0),
1351 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1352 4, 1, 0),
1353 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1354 2, 1, 0),
1355 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1356 1, 1, 0),
1357 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1358 0, 1, 0),
1359 };
1360
1361 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1362 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1363 .info = snd_soc_info_volsw, \
1364 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1365 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1366
1367 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1368 struct snd_ctl_elem_value *ucontrol)
1369 {
1370 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1371 struct snd_soc_dapm_widget *w = wlist->widgets[0];
1372 struct snd_soc_codec *codec = w->codec;
1373 int ret;
1374
1375 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1376
1377 wm_hubs_update_class_w(codec);
1378
1379 return ret;
1380 }
1381
1382 static const struct snd_kcontrol_new dac1l_mix[] = {
1383 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1384 5, 1, 0),
1385 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1386 4, 1, 0),
1387 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1388 2, 1, 0),
1389 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1390 1, 1, 0),
1391 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1392 0, 1, 0),
1393 };
1394
1395 static const struct snd_kcontrol_new dac1r_mix[] = {
1396 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1397 5, 1, 0),
1398 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1399 4, 1, 0),
1400 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1401 2, 1, 0),
1402 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1403 1, 1, 0),
1404 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1405 0, 1, 0),
1406 };
1407
1408 static const char *sidetone_text[] = {
1409 "ADC/DMIC1", "DMIC2",
1410 };
1411
1412 static const struct soc_enum sidetone1_enum =
1413 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1414
1415 static const struct snd_kcontrol_new sidetone1_mux =
1416 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1417
1418 static const struct soc_enum sidetone2_enum =
1419 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1420
1421 static const struct snd_kcontrol_new sidetone2_mux =
1422 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1423
1424 static const char *aif1dac_text[] = {
1425 "AIF1DACDAT", "AIF3DACDAT",
1426 };
1427
1428 static const struct soc_enum aif1dac_enum =
1429 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1430
1431 static const struct snd_kcontrol_new aif1dac_mux =
1432 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1433
1434 static const char *aif2dac_text[] = {
1435 "AIF2DACDAT", "AIF3DACDAT",
1436 };
1437
1438 static const struct soc_enum aif2dac_enum =
1439 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1440
1441 static const struct snd_kcontrol_new aif2dac_mux =
1442 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1443
1444 static const char *aif2adc_text[] = {
1445 "AIF2ADCDAT", "AIF3DACDAT",
1446 };
1447
1448 static const struct soc_enum aif2adc_enum =
1449 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1450
1451 static const struct snd_kcontrol_new aif2adc_mux =
1452 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1453
1454 static const char *aif3adc_text[] = {
1455 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1456 };
1457
1458 static const struct soc_enum wm8994_aif3adc_enum =
1459 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1460
1461 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1462 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1463
1464 static const struct soc_enum wm8958_aif3adc_enum =
1465 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1466
1467 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1468 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1469
1470 static const char *mono_pcm_out_text[] = {
1471 "None", "AIF2ADCL", "AIF2ADCR",
1472 };
1473
1474 static const struct soc_enum mono_pcm_out_enum =
1475 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1476
1477 static const struct snd_kcontrol_new mono_pcm_out_mux =
1478 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1479
1480 static const char *aif2dac_src_text[] = {
1481 "AIF2", "AIF3",
1482 };
1483
1484 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1485 static const struct soc_enum aif2dacl_src_enum =
1486 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1487
1488 static const struct snd_kcontrol_new aif2dacl_src_mux =
1489 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1490
1491 static const struct soc_enum aif2dacr_src_enum =
1492 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1493
1494 static const struct snd_kcontrol_new aif2dacr_src_mux =
1495 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1496
1497 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1498 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
1499 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1500 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
1501 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1502
1503 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1504 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1505 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1506 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1507 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1508 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1509 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1510 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1511 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1512 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1513
1514 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1515 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1516 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1517 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1518 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1519 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1520 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
1521 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1522 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
1523 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1524
1525 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1526 };
1527
1528 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1529 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
1530 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1531 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
1532 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1533 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1534 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1535 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1536 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1537 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1538 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1539 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
1540 };
1541
1542 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1543 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1544 dac_ev, SND_SOC_DAPM_PRE_PMU),
1545 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1546 dac_ev, SND_SOC_DAPM_PRE_PMU),
1547 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1548 dac_ev, SND_SOC_DAPM_PRE_PMU),
1549 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1550 dac_ev, SND_SOC_DAPM_PRE_PMU),
1551 };
1552
1553 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1554 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1555 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1556 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1557 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1558 };
1559
1560 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1561 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1562 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1563 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1564 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1565 };
1566
1567 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1568 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1569 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1570 };
1571
1572 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1573 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1574 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1575 SND_SOC_DAPM_INPUT("Clock"),
1576
1577 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1578 SND_SOC_DAPM_PRE_PMU),
1579 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1580 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1581
1582 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1583 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1584
1585 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1586 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1587 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
1588
1589 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1590 0, SND_SOC_NOPM, 9, 0),
1591 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1592 0, SND_SOC_NOPM, 8, 0),
1593 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1594 SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
1595 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1596 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1597 SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
1598 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1599
1600 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1601 0, SND_SOC_NOPM, 11, 0),
1602 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1603 0, SND_SOC_NOPM, 10, 0),
1604 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1605 SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
1606 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1607 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1608 SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
1609 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1610
1611 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1612 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1613 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1614 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1615
1616 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1617 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1618 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1619 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1620
1621 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1622 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1623 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1624 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1625
1626 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1627 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1628
1629 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1630 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1631 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1632 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1633
1634 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1635 SND_SOC_NOPM, 13, 0),
1636 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1637 SND_SOC_NOPM, 12, 0),
1638 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1639 SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
1640 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1641 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1642 SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
1643 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1644
1645 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1646 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1647 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1648 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1649
1650 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1651 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1652 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1653
1654 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1655 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1656
1657 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1658
1659 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1660 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1661 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1662 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1663
1664 /* Power is done with the muxes since the ADC power also controls the
1665 * downsampling chain, the chip will automatically manage the analogue
1666 * specific portions.
1667 */
1668 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1669 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1670
1671 SND_SOC_DAPM_POST("Debug log", post_ev),
1672 };
1673
1674 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1675 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1676 };
1677
1678 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1679 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
1680 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1681 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1682 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1683 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1684 };
1685
1686 static const struct snd_soc_dapm_route intercon[] = {
1687 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1688 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1689
1690 { "DSP1CLK", NULL, "CLK_SYS" },
1691 { "DSP2CLK", NULL, "CLK_SYS" },
1692 { "DSPINTCLK", NULL, "CLK_SYS" },
1693
1694 { "AIF1ADC1L", NULL, "AIF1CLK" },
1695 { "AIF1ADC1L", NULL, "DSP1CLK" },
1696 { "AIF1ADC1R", NULL, "AIF1CLK" },
1697 { "AIF1ADC1R", NULL, "DSP1CLK" },
1698 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1699
1700 { "AIF1DAC1L", NULL, "AIF1CLK" },
1701 { "AIF1DAC1L", NULL, "DSP1CLK" },
1702 { "AIF1DAC1R", NULL, "AIF1CLK" },
1703 { "AIF1DAC1R", NULL, "DSP1CLK" },
1704 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1705
1706 { "AIF1ADC2L", NULL, "AIF1CLK" },
1707 { "AIF1ADC2L", NULL, "DSP1CLK" },
1708 { "AIF1ADC2R", NULL, "AIF1CLK" },
1709 { "AIF1ADC2R", NULL, "DSP1CLK" },
1710 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1711
1712 { "AIF1DAC2L", NULL, "AIF1CLK" },
1713 { "AIF1DAC2L", NULL, "DSP1CLK" },
1714 { "AIF1DAC2R", NULL, "AIF1CLK" },
1715 { "AIF1DAC2R", NULL, "DSP1CLK" },
1716 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1717
1718 { "AIF2ADCL", NULL, "AIF2CLK" },
1719 { "AIF2ADCL", NULL, "DSP2CLK" },
1720 { "AIF2ADCR", NULL, "AIF2CLK" },
1721 { "AIF2ADCR", NULL, "DSP2CLK" },
1722 { "AIF2ADCR", NULL, "DSPINTCLK" },
1723
1724 { "AIF2DACL", NULL, "AIF2CLK" },
1725 { "AIF2DACL", NULL, "DSP2CLK" },
1726 { "AIF2DACR", NULL, "AIF2CLK" },
1727 { "AIF2DACR", NULL, "DSP2CLK" },
1728 { "AIF2DACR", NULL, "DSPINTCLK" },
1729
1730 { "DMIC1L", NULL, "DMIC1DAT" },
1731 { "DMIC1L", NULL, "CLK_SYS" },
1732 { "DMIC1R", NULL, "DMIC1DAT" },
1733 { "DMIC1R", NULL, "CLK_SYS" },
1734 { "DMIC2L", NULL, "DMIC2DAT" },
1735 { "DMIC2L", NULL, "CLK_SYS" },
1736 { "DMIC2R", NULL, "DMIC2DAT" },
1737 { "DMIC2R", NULL, "CLK_SYS" },
1738
1739 { "ADCL", NULL, "AIF1CLK" },
1740 { "ADCL", NULL, "DSP1CLK" },
1741 { "ADCL", NULL, "DSPINTCLK" },
1742
1743 { "ADCR", NULL, "AIF1CLK" },
1744 { "ADCR", NULL, "DSP1CLK" },
1745 { "ADCR", NULL, "DSPINTCLK" },
1746
1747 { "ADCL Mux", "ADC", "ADCL" },
1748 { "ADCL Mux", "DMIC", "DMIC1L" },
1749 { "ADCR Mux", "ADC", "ADCR" },
1750 { "ADCR Mux", "DMIC", "DMIC1R" },
1751
1752 { "DAC1L", NULL, "AIF1CLK" },
1753 { "DAC1L", NULL, "DSP1CLK" },
1754 { "DAC1L", NULL, "DSPINTCLK" },
1755
1756 { "DAC1R", NULL, "AIF1CLK" },
1757 { "DAC1R", NULL, "DSP1CLK" },
1758 { "DAC1R", NULL, "DSPINTCLK" },
1759
1760 { "DAC2L", NULL, "AIF2CLK" },
1761 { "DAC2L", NULL, "DSP2CLK" },
1762 { "DAC2L", NULL, "DSPINTCLK" },
1763
1764 { "DAC2R", NULL, "AIF2DACR" },
1765 { "DAC2R", NULL, "AIF2CLK" },
1766 { "DAC2R", NULL, "DSP2CLK" },
1767 { "DAC2R", NULL, "DSPINTCLK" },
1768
1769 { "TOCLK", NULL, "CLK_SYS" },
1770
1771 { "AIF1DACDAT", NULL, "AIF1 Playback" },
1772 { "AIF2DACDAT", NULL, "AIF2 Playback" },
1773 { "AIF3DACDAT", NULL, "AIF3 Playback" },
1774
1775 { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1776 { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1777 { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1778
1779 /* AIF1 outputs */
1780 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1781 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1782 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1783
1784 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1785 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1786 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1787
1788 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1789 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1790 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1791
1792 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1793 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1794 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1795
1796 /* Pin level routing for AIF3 */
1797 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1798 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1799 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1800 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1801
1802 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1803 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1804 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1805 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1806 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1807 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1808 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1809
1810 /* DAC1 inputs */
1811 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1812 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1813 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1814 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1815 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1816
1817 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1818 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1819 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1820 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1821 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1822
1823 /* DAC2/AIF2 outputs */
1824 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1825 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1826 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1827 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1828 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1829 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1830
1831 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1832 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1833 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1834 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1835 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1836 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1837
1838 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1839 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1840 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1841 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1842
1843 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1844
1845 /* AIF3 output */
1846 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1847 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1848 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1849 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1850 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1851 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1852 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1853 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1854
1855 /* Sidetone */
1856 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1857 { "Left Sidetone", "DMIC2", "DMIC2L" },
1858 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1859 { "Right Sidetone", "DMIC2", "DMIC2R" },
1860
1861 /* Output stages */
1862 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1863 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1864
1865 { "SPKL", "DAC1 Switch", "DAC1L" },
1866 { "SPKL", "DAC2 Switch", "DAC2L" },
1867
1868 { "SPKR", "DAC1 Switch", "DAC1R" },
1869 { "SPKR", "DAC2 Switch", "DAC2R" },
1870
1871 { "Left Headphone Mux", "DAC", "DAC1L" },
1872 { "Right Headphone Mux", "DAC", "DAC1R" },
1873 };
1874
1875 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1876 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1877 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1878 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1879 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1880 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1881 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1882 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1883 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1884 };
1885
1886 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1887 { "DAC1L", NULL, "DAC1L Mixer" },
1888 { "DAC1R", NULL, "DAC1R Mixer" },
1889 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1890 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1891 };
1892
1893 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1894 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1895 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1896 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1897 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1898 { "MICBIAS1", NULL, "CLK_SYS" },
1899 { "MICBIAS1", NULL, "MICBIAS Supply" },
1900 { "MICBIAS2", NULL, "CLK_SYS" },
1901 { "MICBIAS2", NULL, "MICBIAS Supply" },
1902 };
1903
1904 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1905 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1906 { "AIF2DACR", NULL, "AIF2DAC Mux" },
1907 { "MICBIAS1", NULL, "VMID" },
1908 { "MICBIAS2", NULL, "VMID" },
1909 };
1910
1911 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1912 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1913 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1914
1915 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1916 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1917 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1918 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1919
1920 { "AIF3DACDAT", NULL, "AIF3" },
1921 { "AIF3ADCDAT", NULL, "AIF3" },
1922
1923 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1924 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1925
1926 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1927 };
1928
1929 /* The size in bits of the FLL divide multiplied by 10
1930 * to allow rounding later */
1931 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1932
1933 struct fll_div {
1934 u16 outdiv;
1935 u16 n;
1936 u16 k;
1937 u16 clk_ref_div;
1938 u16 fll_fratio;
1939 };
1940
1941 static int wm8994_get_fll_config(struct fll_div *fll,
1942 int freq_in, int freq_out)
1943 {
1944 u64 Kpart;
1945 unsigned int K, Ndiv, Nmod;
1946
1947 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1948
1949 /* Scale the input frequency down to <= 13.5MHz */
1950 fll->clk_ref_div = 0;
1951 while (freq_in > 13500000) {
1952 fll->clk_ref_div++;
1953 freq_in /= 2;
1954
1955 if (fll->clk_ref_div > 3)
1956 return -EINVAL;
1957 }
1958 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1959
1960 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1961 fll->outdiv = 3;
1962 while (freq_out * (fll->outdiv + 1) < 90000000) {
1963 fll->outdiv++;
1964 if (fll->outdiv > 63)
1965 return -EINVAL;
1966 }
1967 freq_out *= fll->outdiv + 1;
1968 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1969
1970 if (freq_in > 1000000) {
1971 fll->fll_fratio = 0;
1972 } else if (freq_in > 256000) {
1973 fll->fll_fratio = 1;
1974 freq_in *= 2;
1975 } else if (freq_in > 128000) {
1976 fll->fll_fratio = 2;
1977 freq_in *= 4;
1978 } else if (freq_in > 64000) {
1979 fll->fll_fratio = 3;
1980 freq_in *= 8;
1981 } else {
1982 fll->fll_fratio = 4;
1983 freq_in *= 16;
1984 }
1985 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1986
1987 /* Now, calculate N.K */
1988 Ndiv = freq_out / freq_in;
1989
1990 fll->n = Ndiv;
1991 Nmod = freq_out % freq_in;
1992 pr_debug("Nmod=%d\n", Nmod);
1993
1994 /* Calculate fractional part - scale up so we can round. */
1995 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1996
1997 do_div(Kpart, freq_in);
1998
1999 K = Kpart & 0xFFFFFFFF;
2000
2001 if ((K % 10) >= 5)
2002 K += 5;
2003
2004 /* Move down to proper range now rounding is done */
2005 fll->k = K / 10;
2006
2007 pr_debug("N=%x K=%x\n", fll->n, fll->k);
2008
2009 return 0;
2010 }
2011
2012 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
2013 unsigned int freq_in, unsigned int freq_out)
2014 {
2015 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2016 struct wm8994 *control = wm8994->wm8994;
2017 int reg_offset, ret;
2018 struct fll_div fll;
2019 u16 reg, clk1, aif_reg, aif_src;
2020 unsigned long timeout;
2021 bool was_enabled;
2022
2023 switch (id) {
2024 case WM8994_FLL1:
2025 reg_offset = 0;
2026 id = 0;
2027 aif_src = 0x10;
2028 break;
2029 case WM8994_FLL2:
2030 reg_offset = 0x20;
2031 id = 1;
2032 aif_src = 0x18;
2033 break;
2034 default:
2035 return -EINVAL;
2036 }
2037
2038 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2039 was_enabled = reg & WM8994_FLL1_ENA;
2040
2041 switch (src) {
2042 case 0:
2043 /* Allow no source specification when stopping */
2044 if (freq_out)
2045 return -EINVAL;
2046 src = wm8994->fll[id].src;
2047 break;
2048 case WM8994_FLL_SRC_MCLK1:
2049 case WM8994_FLL_SRC_MCLK2:
2050 case WM8994_FLL_SRC_LRCLK:
2051 case WM8994_FLL_SRC_BCLK:
2052 break;
2053 default:
2054 return -EINVAL;
2055 }
2056
2057 /* Are we changing anything? */
2058 if (wm8994->fll[id].src == src &&
2059 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2060 return 0;
2061
2062 /* If we're stopping the FLL redo the old config - no
2063 * registers will actually be written but we avoid GCC flow
2064 * analysis bugs spewing warnings.
2065 */
2066 if (freq_out)
2067 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
2068 else
2069 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
2070 wm8994->fll[id].out);
2071 if (ret < 0)
2072 return ret;
2073
2074 /* Make sure that we're not providing SYSCLK right now */
2075 clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
2076 if (clk1 & WM8994_SYSCLK_SRC)
2077 aif_reg = WM8994_AIF2_CLOCKING_1;
2078 else
2079 aif_reg = WM8994_AIF1_CLOCKING_1;
2080 reg = snd_soc_read(codec, aif_reg);
2081
2082 if ((reg & WM8994_AIF1CLK_ENA) &&
2083 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2084 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
2085 id + 1);
2086 return -EBUSY;
2087 }
2088
2089 /* We always need to disable the FLL while reconfiguring */
2090 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2091 WM8994_FLL1_ENA, 0);
2092
2093 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
2094 freq_in == freq_out && freq_out) {
2095 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
2096 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2097 WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2098 goto out;
2099 }
2100
2101 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2102 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2103 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2104 WM8994_FLL1_OUTDIV_MASK |
2105 WM8994_FLL1_FRATIO_MASK, reg);
2106
2107 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
2108 WM8994_FLL1_K_MASK, fll.k);
2109
2110 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2111 WM8994_FLL1_N_MASK,
2112 fll.n << WM8994_FLL1_N_SHIFT);
2113
2114 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2115 WM8958_FLL1_BYP |
2116 WM8994_FLL1_REFCLK_DIV_MASK |
2117 WM8994_FLL1_REFCLK_SRC_MASK,
2118 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2119 (src - 1));
2120
2121 /* Clear any pending completion from a previous failure */
2122 try_wait_for_completion(&wm8994->fll_locked[id]);
2123
2124 /* Enable (with fractional mode if required) */
2125 if (freq_out) {
2126 /* Enable VMID if we need it */
2127 if (!was_enabled) {
2128 active_reference(codec);
2129
2130 switch (control->type) {
2131 case WM8994:
2132 vmid_reference(codec);
2133 break;
2134 case WM8958:
2135 if (wm8994->revision < 1)
2136 vmid_reference(codec);
2137 break;
2138 default:
2139 break;
2140 }
2141 }
2142
2143 if (fll.k)
2144 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
2145 else
2146 reg = WM8994_FLL1_ENA;
2147 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2148 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
2149 reg);
2150
2151 if (wm8994->fll_locked_irq) {
2152 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2153 msecs_to_jiffies(10));
2154 if (timeout == 0)
2155 dev_warn(codec->dev,
2156 "Timed out waiting for FLL lock\n");
2157 } else {
2158 msleep(5);
2159 }
2160 } else {
2161 if (was_enabled) {
2162 switch (control->type) {
2163 case WM8994:
2164 vmid_dereference(codec);
2165 break;
2166 case WM8958:
2167 if (wm8994->revision < 1)
2168 vmid_dereference(codec);
2169 break;
2170 default:
2171 break;
2172 }
2173
2174 active_dereference(codec);
2175 }
2176 }
2177
2178 out:
2179 wm8994->fll[id].in = freq_in;
2180 wm8994->fll[id].out = freq_out;
2181 wm8994->fll[id].src = src;
2182
2183 configure_clock(codec);
2184
2185 return 0;
2186 }
2187
2188 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2189 {
2190 struct completion *completion = data;
2191
2192 complete(completion);
2193
2194 return IRQ_HANDLED;
2195 }
2196
2197 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2198
2199 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2200 unsigned int freq_in, unsigned int freq_out)
2201 {
2202 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2203 }
2204
2205 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2206 int clk_id, unsigned int freq, int dir)
2207 {
2208 struct snd_soc_codec *codec = dai->codec;
2209 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2210 int i;
2211
2212 switch (dai->id) {
2213 case 1:
2214 case 2:
2215 break;
2216
2217 default:
2218 /* AIF3 shares clocking with AIF1/2 */
2219 return -EINVAL;
2220 }
2221
2222 switch (clk_id) {
2223 case WM8994_SYSCLK_MCLK1:
2224 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2225 wm8994->mclk[0] = freq;
2226 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2227 dai->id, freq);
2228 break;
2229
2230 case WM8994_SYSCLK_MCLK2:
2231 /* TODO: Set GPIO AF */
2232 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2233 wm8994->mclk[1] = freq;
2234 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2235 dai->id, freq);
2236 break;
2237
2238 case WM8994_SYSCLK_FLL1:
2239 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2240 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2241 break;
2242
2243 case WM8994_SYSCLK_FLL2:
2244 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2245 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2246 break;
2247
2248 case WM8994_SYSCLK_OPCLK:
2249 /* Special case - a division (times 10) is given and
2250 * no effect on main clocking.
2251 */
2252 if (freq) {
2253 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2254 if (opclk_divs[i] == freq)
2255 break;
2256 if (i == ARRAY_SIZE(opclk_divs))
2257 return -EINVAL;
2258 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2259 WM8994_OPCLK_DIV_MASK, i);
2260 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2261 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2262 } else {
2263 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2264 WM8994_OPCLK_ENA, 0);
2265 }
2266
2267 default:
2268 return -EINVAL;
2269 }
2270
2271 configure_clock(codec);
2272
2273 return 0;
2274 }
2275
2276 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2277 enum snd_soc_bias_level level)
2278 {
2279 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2280 struct wm8994 *control = wm8994->wm8994;
2281
2282 wm_hubs_set_bias_level(codec, level);
2283
2284 switch (level) {
2285 case SND_SOC_BIAS_ON:
2286 break;
2287
2288 case SND_SOC_BIAS_PREPARE:
2289 /* MICBIAS into regulating mode */
2290 switch (control->type) {
2291 case WM8958:
2292 case WM1811:
2293 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2294 WM8958_MICB1_MODE, 0);
2295 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2296 WM8958_MICB2_MODE, 0);
2297 break;
2298 default:
2299 break;
2300 }
2301
2302 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2303 active_reference(codec);
2304 break;
2305
2306 case SND_SOC_BIAS_STANDBY:
2307 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2308 switch (control->type) {
2309 case WM8958:
2310 if (wm8994->revision == 0) {
2311 /* Optimise performance for rev A */
2312 snd_soc_update_bits(codec,
2313 WM8958_CHARGE_PUMP_2,
2314 WM8958_CP_DISCH,
2315 WM8958_CP_DISCH);
2316 }
2317 break;
2318
2319 default:
2320 break;
2321 }
2322
2323 /* Discharge LINEOUT1 & 2 */
2324 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2325 WM8994_LINEOUT1_DISCH |
2326 WM8994_LINEOUT2_DISCH,
2327 WM8994_LINEOUT1_DISCH |
2328 WM8994_LINEOUT2_DISCH);
2329 }
2330
2331 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2332 active_dereference(codec);
2333
2334 /* MICBIAS into bypass mode on newer devices */
2335 switch (control->type) {
2336 case WM8958:
2337 case WM1811:
2338 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2339 WM8958_MICB1_MODE,
2340 WM8958_MICB1_MODE);
2341 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2342 WM8958_MICB2_MODE,
2343 WM8958_MICB2_MODE);
2344 break;
2345 default:
2346 break;
2347 }
2348 break;
2349
2350 case SND_SOC_BIAS_OFF:
2351 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2352 wm8994->cur_fw = NULL;
2353 break;
2354 }
2355
2356 codec->dapm.bias_level = level;
2357
2358 return 0;
2359 }
2360
2361 int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2362 {
2363 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2364
2365 switch (mode) {
2366 case WM8994_VMID_NORMAL:
2367 if (wm8994->hubs.lineout1_se) {
2368 snd_soc_dapm_disable_pin(&codec->dapm,
2369 "LINEOUT1N Driver");
2370 snd_soc_dapm_disable_pin(&codec->dapm,
2371 "LINEOUT1P Driver");
2372 }
2373 if (wm8994->hubs.lineout2_se) {
2374 snd_soc_dapm_disable_pin(&codec->dapm,
2375 "LINEOUT2N Driver");
2376 snd_soc_dapm_disable_pin(&codec->dapm,
2377 "LINEOUT2P Driver");
2378 }
2379
2380 /* Do the sync with the old mode to allow it to clean up */
2381 snd_soc_dapm_sync(&codec->dapm);
2382 wm8994->vmid_mode = mode;
2383 break;
2384
2385 case WM8994_VMID_FORCE:
2386 if (wm8994->hubs.lineout1_se) {
2387 snd_soc_dapm_force_enable_pin(&codec->dapm,
2388 "LINEOUT1N Driver");
2389 snd_soc_dapm_force_enable_pin(&codec->dapm,
2390 "LINEOUT1P Driver");
2391 }
2392 if (wm8994->hubs.lineout2_se) {
2393 snd_soc_dapm_force_enable_pin(&codec->dapm,
2394 "LINEOUT2N Driver");
2395 snd_soc_dapm_force_enable_pin(&codec->dapm,
2396 "LINEOUT2P Driver");
2397 }
2398
2399 wm8994->vmid_mode = mode;
2400 snd_soc_dapm_sync(&codec->dapm);
2401 break;
2402
2403 default:
2404 return -EINVAL;
2405 }
2406
2407 return 0;
2408 }
2409
2410 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2411 {
2412 struct snd_soc_codec *codec = dai->codec;
2413 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2414 struct wm8994 *control = wm8994->wm8994;
2415 int ms_reg;
2416 int aif1_reg;
2417 int ms = 0;
2418 int aif1 = 0;
2419
2420 switch (dai->id) {
2421 case 1:
2422 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2423 aif1_reg = WM8994_AIF1_CONTROL_1;
2424 break;
2425 case 2:
2426 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2427 aif1_reg = WM8994_AIF2_CONTROL_1;
2428 break;
2429 default:
2430 return -EINVAL;
2431 }
2432
2433 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2434 case SND_SOC_DAIFMT_CBS_CFS:
2435 break;
2436 case SND_SOC_DAIFMT_CBM_CFM:
2437 ms = WM8994_AIF1_MSTR;
2438 break;
2439 default:
2440 return -EINVAL;
2441 }
2442
2443 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2444 case SND_SOC_DAIFMT_DSP_B:
2445 aif1 |= WM8994_AIF1_LRCLK_INV;
2446 case SND_SOC_DAIFMT_DSP_A:
2447 aif1 |= 0x18;
2448 break;
2449 case SND_SOC_DAIFMT_I2S:
2450 aif1 |= 0x10;
2451 break;
2452 case SND_SOC_DAIFMT_RIGHT_J:
2453 break;
2454 case SND_SOC_DAIFMT_LEFT_J:
2455 aif1 |= 0x8;
2456 break;
2457 default:
2458 return -EINVAL;
2459 }
2460
2461 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2462 case SND_SOC_DAIFMT_DSP_A:
2463 case SND_SOC_DAIFMT_DSP_B:
2464 /* frame inversion not valid for DSP modes */
2465 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2466 case SND_SOC_DAIFMT_NB_NF:
2467 break;
2468 case SND_SOC_DAIFMT_IB_NF:
2469 aif1 |= WM8994_AIF1_BCLK_INV;
2470 break;
2471 default:
2472 return -EINVAL;
2473 }
2474 break;
2475
2476 case SND_SOC_DAIFMT_I2S:
2477 case SND_SOC_DAIFMT_RIGHT_J:
2478 case SND_SOC_DAIFMT_LEFT_J:
2479 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2480 case SND_SOC_DAIFMT_NB_NF:
2481 break;
2482 case SND_SOC_DAIFMT_IB_IF:
2483 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2484 break;
2485 case SND_SOC_DAIFMT_IB_NF:
2486 aif1 |= WM8994_AIF1_BCLK_INV;
2487 break;
2488 case SND_SOC_DAIFMT_NB_IF:
2489 aif1 |= WM8994_AIF1_LRCLK_INV;
2490 break;
2491 default:
2492 return -EINVAL;
2493 }
2494 break;
2495 default:
2496 return -EINVAL;
2497 }
2498
2499 /* The AIF2 format configuration needs to be mirrored to AIF3
2500 * on WM8958 if it's in use so just do it all the time. */
2501 switch (control->type) {
2502 case WM1811:
2503 case WM8958:
2504 if (dai->id == 2)
2505 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2506 WM8994_AIF1_LRCLK_INV |
2507 WM8958_AIF3_FMT_MASK, aif1);
2508 break;
2509
2510 default:
2511 break;
2512 }
2513
2514 snd_soc_update_bits(codec, aif1_reg,
2515 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2516 WM8994_AIF1_FMT_MASK,
2517 aif1);
2518 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2519 ms);
2520
2521 return 0;
2522 }
2523
2524 static struct {
2525 int val, rate;
2526 } srs[] = {
2527 { 0, 8000 },
2528 { 1, 11025 },
2529 { 2, 12000 },
2530 { 3, 16000 },
2531 { 4, 22050 },
2532 { 5, 24000 },
2533 { 6, 32000 },
2534 { 7, 44100 },
2535 { 8, 48000 },
2536 { 9, 88200 },
2537 { 10, 96000 },
2538 };
2539
2540 static int fs_ratios[] = {
2541 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2542 };
2543
2544 static int bclk_divs[] = {
2545 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2546 640, 880, 960, 1280, 1760, 1920
2547 };
2548
2549 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2550 struct snd_pcm_hw_params *params,
2551 struct snd_soc_dai *dai)
2552 {
2553 struct snd_soc_codec *codec = dai->codec;
2554 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2555 int aif1_reg;
2556 int aif2_reg;
2557 int bclk_reg;
2558 int lrclk_reg;
2559 int rate_reg;
2560 int aif1 = 0;
2561 int aif2 = 0;
2562 int bclk = 0;
2563 int lrclk = 0;
2564 int rate_val = 0;
2565 int id = dai->id - 1;
2566
2567 int i, cur_val, best_val, bclk_rate, best;
2568
2569 switch (dai->id) {
2570 case 1:
2571 aif1_reg = WM8994_AIF1_CONTROL_1;
2572 aif2_reg = WM8994_AIF1_CONTROL_2;
2573 bclk_reg = WM8994_AIF1_BCLK;
2574 rate_reg = WM8994_AIF1_RATE;
2575 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2576 wm8994->lrclk_shared[0]) {
2577 lrclk_reg = WM8994_AIF1DAC_LRCLK;
2578 } else {
2579 lrclk_reg = WM8994_AIF1ADC_LRCLK;
2580 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2581 }
2582 break;
2583 case 2:
2584 aif1_reg = WM8994_AIF2_CONTROL_1;
2585 aif2_reg = WM8994_AIF2_CONTROL_2;
2586 bclk_reg = WM8994_AIF2_BCLK;
2587 rate_reg = WM8994_AIF2_RATE;
2588 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2589 wm8994->lrclk_shared[1]) {
2590 lrclk_reg = WM8994_AIF2DAC_LRCLK;
2591 } else {
2592 lrclk_reg = WM8994_AIF2ADC_LRCLK;
2593 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2594 }
2595 break;
2596 default:
2597 return -EINVAL;
2598 }
2599
2600 bclk_rate = params_rate(params) * 2;
2601 switch (params_format(params)) {
2602 case SNDRV_PCM_FORMAT_S16_LE:
2603 bclk_rate *= 16;
2604 break;
2605 case SNDRV_PCM_FORMAT_S20_3LE:
2606 bclk_rate *= 20;
2607 aif1 |= 0x20;
2608 break;
2609 case SNDRV_PCM_FORMAT_S24_LE:
2610 bclk_rate *= 24;
2611 aif1 |= 0x40;
2612 break;
2613 case SNDRV_PCM_FORMAT_S32_LE:
2614 bclk_rate *= 32;
2615 aif1 |= 0x60;
2616 break;
2617 default:
2618 return -EINVAL;
2619 }
2620
2621 /* Try to find an appropriate sample rate; look for an exact match. */
2622 for (i = 0; i < ARRAY_SIZE(srs); i++)
2623 if (srs[i].rate == params_rate(params))
2624 break;
2625 if (i == ARRAY_SIZE(srs))
2626 return -EINVAL;
2627 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2628
2629 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2630 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2631 dai->id, wm8994->aifclk[id], bclk_rate);
2632
2633 if (params_channels(params) == 1 &&
2634 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2635 aif2 |= WM8994_AIF1_MONO;
2636
2637 if (wm8994->aifclk[id] == 0) {
2638 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2639 return -EINVAL;
2640 }
2641
2642 /* AIFCLK/fs ratio; look for a close match in either direction */
2643 best = 0;
2644 best_val = abs((fs_ratios[0] * params_rate(params))
2645 - wm8994->aifclk[id]);
2646 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2647 cur_val = abs((fs_ratios[i] * params_rate(params))
2648 - wm8994->aifclk[id]);
2649 if (cur_val >= best_val)
2650 continue;
2651 best = i;
2652 best_val = cur_val;
2653 }
2654 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2655 dai->id, fs_ratios[best]);
2656 rate_val |= best;
2657
2658 /* We may not get quite the right frequency if using
2659 * approximate clocks so look for the closest match that is
2660 * higher than the target (we need to ensure that there enough
2661 * BCLKs to clock out the samples).
2662 */
2663 best = 0;
2664 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2665 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2666 if (cur_val < 0) /* BCLK table is sorted */
2667 break;
2668 best = i;
2669 }
2670 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2671 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2672 bclk_divs[best], bclk_rate);
2673 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2674
2675 lrclk = bclk_rate / params_rate(params);
2676 if (!lrclk) {
2677 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2678 bclk_rate);
2679 return -EINVAL;
2680 }
2681 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2682 lrclk, bclk_rate / lrclk);
2683
2684 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2685 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2686 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2687 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2688 lrclk);
2689 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2690 WM8994_AIF1CLK_RATE_MASK, rate_val);
2691
2692 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2693 switch (dai->id) {
2694 case 1:
2695 wm8994->dac_rates[0] = params_rate(params);
2696 wm8994_set_retune_mobile(codec, 0);
2697 wm8994_set_retune_mobile(codec, 1);
2698 break;
2699 case 2:
2700 wm8994->dac_rates[1] = params_rate(params);
2701 wm8994_set_retune_mobile(codec, 2);
2702 break;
2703 }
2704 }
2705
2706 return 0;
2707 }
2708
2709 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2710 struct snd_pcm_hw_params *params,
2711 struct snd_soc_dai *dai)
2712 {
2713 struct snd_soc_codec *codec = dai->codec;
2714 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2715 struct wm8994 *control = wm8994->wm8994;
2716 int aif1_reg;
2717 int aif1 = 0;
2718
2719 switch (dai->id) {
2720 case 3:
2721 switch (control->type) {
2722 case WM1811:
2723 case WM8958:
2724 aif1_reg = WM8958_AIF3_CONTROL_1;
2725 break;
2726 default:
2727 return 0;
2728 }
2729 default:
2730 return 0;
2731 }
2732
2733 switch (params_format(params)) {
2734 case SNDRV_PCM_FORMAT_S16_LE:
2735 break;
2736 case SNDRV_PCM_FORMAT_S20_3LE:
2737 aif1 |= 0x20;
2738 break;
2739 case SNDRV_PCM_FORMAT_S24_LE:
2740 aif1 |= 0x40;
2741 break;
2742 case SNDRV_PCM_FORMAT_S32_LE:
2743 aif1 |= 0x60;
2744 break;
2745 default:
2746 return -EINVAL;
2747 }
2748
2749 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2750 }
2751
2752 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2753 {
2754 struct snd_soc_codec *codec = codec_dai->codec;
2755 int mute_reg;
2756 int reg;
2757
2758 switch (codec_dai->id) {
2759 case 1:
2760 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2761 break;
2762 case 2:
2763 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2764 break;
2765 default:
2766 return -EINVAL;
2767 }
2768
2769 if (mute)
2770 reg = WM8994_AIF1DAC1_MUTE;
2771 else
2772 reg = 0;
2773
2774 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2775
2776 return 0;
2777 }
2778
2779 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2780 {
2781 struct snd_soc_codec *codec = codec_dai->codec;
2782 int reg, val, mask;
2783
2784 switch (codec_dai->id) {
2785 case 1:
2786 reg = WM8994_AIF1_MASTER_SLAVE;
2787 mask = WM8994_AIF1_TRI;
2788 break;
2789 case 2:
2790 reg = WM8994_AIF2_MASTER_SLAVE;
2791 mask = WM8994_AIF2_TRI;
2792 break;
2793 default:
2794 return -EINVAL;
2795 }
2796
2797 if (tristate)
2798 val = mask;
2799 else
2800 val = 0;
2801
2802 return snd_soc_update_bits(codec, reg, mask, val);
2803 }
2804
2805 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2806 {
2807 struct snd_soc_codec *codec = dai->codec;
2808
2809 /* Disable the pulls on the AIF if we're using it to save power. */
2810 snd_soc_update_bits(codec, WM8994_GPIO_3,
2811 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2812 snd_soc_update_bits(codec, WM8994_GPIO_4,
2813 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2814 snd_soc_update_bits(codec, WM8994_GPIO_5,
2815 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2816
2817 return 0;
2818 }
2819
2820 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2821
2822 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2823 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2824
2825 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2826 .set_sysclk = wm8994_set_dai_sysclk,
2827 .set_fmt = wm8994_set_dai_fmt,
2828 .hw_params = wm8994_hw_params,
2829 .digital_mute = wm8994_aif_mute,
2830 .set_pll = wm8994_set_fll,
2831 .set_tristate = wm8994_set_tristate,
2832 };
2833
2834 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2835 .set_sysclk = wm8994_set_dai_sysclk,
2836 .set_fmt = wm8994_set_dai_fmt,
2837 .hw_params = wm8994_hw_params,
2838 .digital_mute = wm8994_aif_mute,
2839 .set_pll = wm8994_set_fll,
2840 .set_tristate = wm8994_set_tristate,
2841 };
2842
2843 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2844 .hw_params = wm8994_aif3_hw_params,
2845 };
2846
2847 static struct snd_soc_dai_driver wm8994_dai[] = {
2848 {
2849 .name = "wm8994-aif1",
2850 .id = 1,
2851 .playback = {
2852 .stream_name = "AIF1 Playback",
2853 .channels_min = 1,
2854 .channels_max = 2,
2855 .rates = WM8994_RATES,
2856 .formats = WM8994_FORMATS,
2857 .sig_bits = 24,
2858 },
2859 .capture = {
2860 .stream_name = "AIF1 Capture",
2861 .channels_min = 1,
2862 .channels_max = 2,
2863 .rates = WM8994_RATES,
2864 .formats = WM8994_FORMATS,
2865 .sig_bits = 24,
2866 },
2867 .ops = &wm8994_aif1_dai_ops,
2868 },
2869 {
2870 .name = "wm8994-aif2",
2871 .id = 2,
2872 .playback = {
2873 .stream_name = "AIF2 Playback",
2874 .channels_min = 1,
2875 .channels_max = 2,
2876 .rates = WM8994_RATES,
2877 .formats = WM8994_FORMATS,
2878 .sig_bits = 24,
2879 },
2880 .capture = {
2881 .stream_name = "AIF2 Capture",
2882 .channels_min = 1,
2883 .channels_max = 2,
2884 .rates = WM8994_RATES,
2885 .formats = WM8994_FORMATS,
2886 .sig_bits = 24,
2887 },
2888 .probe = wm8994_aif2_probe,
2889 .ops = &wm8994_aif2_dai_ops,
2890 },
2891 {
2892 .name = "wm8994-aif3",
2893 .id = 3,
2894 .playback = {
2895 .stream_name = "AIF3 Playback",
2896 .channels_min = 1,
2897 .channels_max = 2,
2898 .rates = WM8994_RATES,
2899 .formats = WM8994_FORMATS,
2900 .sig_bits = 24,
2901 },
2902 .capture = {
2903 .stream_name = "AIF3 Capture",
2904 .channels_min = 1,
2905 .channels_max = 2,
2906 .rates = WM8994_RATES,
2907 .formats = WM8994_FORMATS,
2908 .sig_bits = 24,
2909 },
2910 .ops = &wm8994_aif3_dai_ops,
2911 }
2912 };
2913
2914 #ifdef CONFIG_PM
2915 static int wm8994_codec_suspend(struct snd_soc_codec *codec)
2916 {
2917 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2918 struct wm8994 *control = wm8994->wm8994;
2919 int i, ret;
2920
2921 switch (control->type) {
2922 case WM8994:
2923 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2924 break;
2925 case WM1811:
2926 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2927 WM1811_JACKDET_MODE_MASK, 0);
2928 /* Fall through */
2929 case WM8958:
2930 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2931 WM8958_MICD_ENA, 0);
2932 break;
2933 }
2934
2935 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2936 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2937 sizeof(struct wm8994_fll_config));
2938 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2939 if (ret < 0)
2940 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2941 i + 1, ret);
2942 }
2943
2944 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2945
2946 return 0;
2947 }
2948
2949 static int wm8994_codec_resume(struct snd_soc_codec *codec)
2950 {
2951 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2952 struct wm8994 *control = wm8994->wm8994;
2953 int i, ret;
2954 unsigned int val, mask;
2955
2956 if (wm8994->revision < 4) {
2957 /* force a HW read */
2958 ret = regmap_read(control->regmap,
2959 WM8994_POWER_MANAGEMENT_5, &val);
2960
2961 /* modify the cache only */
2962 codec->cache_only = 1;
2963 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2964 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2965 val &= mask;
2966 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2967 mask, val);
2968 codec->cache_only = 0;
2969 }
2970
2971 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2972 if (!wm8994->fll_suspend[i].out)
2973 continue;
2974
2975 ret = _wm8994_set_fll(codec, i + 1,
2976 wm8994->fll_suspend[i].src,
2977 wm8994->fll_suspend[i].in,
2978 wm8994->fll_suspend[i].out);
2979 if (ret < 0)
2980 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2981 i + 1, ret);
2982 }
2983
2984 switch (control->type) {
2985 case WM8994:
2986 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2987 snd_soc_update_bits(codec, WM8994_MICBIAS,
2988 WM8994_MICD_ENA, WM8994_MICD_ENA);
2989 break;
2990 case WM1811:
2991 if (wm8994->jackdet && wm8994->jack_cb) {
2992 /* Restart from idle */
2993 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2994 WM1811_JACKDET_MODE_MASK,
2995 WM1811_JACKDET_MODE_JACK);
2996 break;
2997 }
2998 break;
2999 case WM8958:
3000 if (wm8994->jack_cb)
3001 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3002 WM8958_MICD_ENA, WM8958_MICD_ENA);
3003 break;
3004 }
3005
3006 return 0;
3007 }
3008 #else
3009 #define wm8994_codec_suspend NULL
3010 #define wm8994_codec_resume NULL
3011 #endif
3012
3013 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3014 {
3015 struct snd_soc_codec *codec = wm8994->codec;
3016 struct wm8994_pdata *pdata = wm8994->pdata;
3017 struct snd_kcontrol_new controls[] = {
3018 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3019 wm8994->retune_mobile_enum,
3020 wm8994_get_retune_mobile_enum,
3021 wm8994_put_retune_mobile_enum),
3022 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3023 wm8994->retune_mobile_enum,
3024 wm8994_get_retune_mobile_enum,
3025 wm8994_put_retune_mobile_enum),
3026 SOC_ENUM_EXT("AIF2 EQ Mode",
3027 wm8994->retune_mobile_enum,
3028 wm8994_get_retune_mobile_enum,
3029 wm8994_put_retune_mobile_enum),
3030 };
3031 int ret, i, j;
3032 const char **t;
3033
3034 /* We need an array of texts for the enum API but the number
3035 * of texts is likely to be less than the number of
3036 * configurations due to the sample rate dependency of the
3037 * configurations. */
3038 wm8994->num_retune_mobile_texts = 0;
3039 wm8994->retune_mobile_texts = NULL;
3040 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3041 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3042 if (strcmp(pdata->retune_mobile_cfgs[i].name,
3043 wm8994->retune_mobile_texts[j]) == 0)
3044 break;
3045 }
3046
3047 if (j != wm8994->num_retune_mobile_texts)
3048 continue;
3049
3050 /* Expand the array... */
3051 t = krealloc(wm8994->retune_mobile_texts,
3052 sizeof(char *) *
3053 (wm8994->num_retune_mobile_texts + 1),
3054 GFP_KERNEL);
3055 if (t == NULL)
3056 continue;
3057
3058 /* ...store the new entry... */
3059 t[wm8994->num_retune_mobile_texts] =
3060 pdata->retune_mobile_cfgs[i].name;
3061
3062 /* ...and remember the new version. */
3063 wm8994->num_retune_mobile_texts++;
3064 wm8994->retune_mobile_texts = t;
3065 }
3066
3067 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3068 wm8994->num_retune_mobile_texts);
3069
3070 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
3071 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3072
3073 ret = snd_soc_add_codec_controls(wm8994->codec, controls,
3074 ARRAY_SIZE(controls));
3075 if (ret != 0)
3076 dev_err(wm8994->codec->dev,
3077 "Failed to add ReTune Mobile controls: %d\n", ret);
3078 }
3079
3080 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3081 {
3082 struct snd_soc_codec *codec = wm8994->codec;
3083 struct wm8994_pdata *pdata = wm8994->pdata;
3084 int ret, i;
3085
3086 if (!pdata)
3087 return;
3088
3089 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3090 pdata->lineout2_diff,
3091 pdata->lineout1fb,
3092 pdata->lineout2fb,
3093 pdata->jd_scthr,
3094 pdata->jd_thr,
3095 pdata->micbias1_lvl,
3096 pdata->micbias2_lvl);
3097
3098 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3099
3100 if (pdata->num_drc_cfgs) {
3101 struct snd_kcontrol_new controls[] = {
3102 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3103 wm8994_get_drc_enum, wm8994_put_drc_enum),
3104 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3105 wm8994_get_drc_enum, wm8994_put_drc_enum),
3106 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3107 wm8994_get_drc_enum, wm8994_put_drc_enum),
3108 };
3109
3110 /* We need an array of texts for the enum API */
3111 wm8994->drc_texts = devm_kzalloc(wm8994->codec->dev,
3112 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
3113 if (!wm8994->drc_texts) {
3114 dev_err(wm8994->codec->dev,
3115 "Failed to allocate %d DRC config texts\n",
3116 pdata->num_drc_cfgs);
3117 return;
3118 }
3119
3120 for (i = 0; i < pdata->num_drc_cfgs; i++)
3121 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3122
3123 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3124 wm8994->drc_enum.texts = wm8994->drc_texts;
3125
3126 ret = snd_soc_add_codec_controls(wm8994->codec, controls,
3127 ARRAY_SIZE(controls));
3128 if (ret != 0)
3129 dev_err(wm8994->codec->dev,
3130 "Failed to add DRC mode controls: %d\n", ret);
3131
3132 for (i = 0; i < WM8994_NUM_DRC; i++)
3133 wm8994_set_drc(codec, i);
3134 }
3135
3136 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3137 pdata->num_retune_mobile_cfgs);
3138
3139 if (pdata->num_retune_mobile_cfgs)
3140 wm8994_handle_retune_mobile_pdata(wm8994);
3141 else
3142 snd_soc_add_codec_controls(wm8994->codec, wm8994_eq_controls,
3143 ARRAY_SIZE(wm8994_eq_controls));
3144
3145 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3146 if (pdata->micbias[i]) {
3147 snd_soc_write(codec, WM8958_MICBIAS1 + i,
3148 pdata->micbias[i] & 0xffff);
3149 }
3150 }
3151 }
3152
3153 /**
3154 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3155 *
3156 * @codec: WM8994 codec
3157 * @jack: jack to report detection events on
3158 * @micbias: microphone bias to detect on
3159 *
3160 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3161 * being used to bring out signals to the processor then only platform
3162 * data configuration is needed for WM8994 and processor GPIOs should
3163 * be configured using snd_soc_jack_add_gpios() instead.
3164 *
3165 * Configuration of detection levels is available via the micbias1_lvl
3166 * and micbias2_lvl platform data members.
3167 */
3168 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3169 int micbias)
3170 {
3171 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3172 struct wm8994_micdet *micdet;
3173 struct wm8994 *control = wm8994->wm8994;
3174 int reg, ret;
3175
3176 if (control->type != WM8994) {
3177 dev_warn(codec->dev, "Not a WM8994\n");
3178 return -EINVAL;
3179 }
3180
3181 switch (micbias) {
3182 case 1:
3183 micdet = &wm8994->micdet[0];
3184 if (jack)
3185 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3186 "MICBIAS1");
3187 else
3188 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3189 "MICBIAS1");
3190 break;
3191 case 2:
3192 micdet = &wm8994->micdet[1];
3193 if (jack)
3194 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3195 "MICBIAS1");
3196 else
3197 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3198 "MICBIAS1");
3199 break;
3200 default:
3201 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
3202 return -EINVAL;
3203 }
3204
3205 if (ret != 0)
3206 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3207 micbias, ret);
3208
3209 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3210 micbias, jack);
3211
3212 /* Store the configuration */
3213 micdet->jack = jack;
3214 micdet->detecting = true;
3215
3216 /* If either of the jacks is set up then enable detection */
3217 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3218 reg = WM8994_MICD_ENA;
3219 else
3220 reg = 0;
3221
3222 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3223
3224 snd_soc_dapm_sync(&codec->dapm);
3225
3226 return 0;
3227 }
3228 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3229
3230 static void wm8994_mic_work(struct work_struct *work)
3231 {
3232 struct wm8994_priv *priv = container_of(work,
3233 struct wm8994_priv,
3234 mic_work.work);
3235 struct regmap *regmap = priv->wm8994->regmap;
3236 struct device *dev = priv->wm8994->dev;
3237 unsigned int reg;
3238 int ret;
3239 int report;
3240
3241 ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, &reg);
3242 if (ret < 0) {
3243 dev_err(dev, "Failed to read microphone status: %d\n",
3244 ret);
3245 return;
3246 }
3247
3248 dev_dbg(dev, "Microphone status: %x\n", reg);
3249
3250 report = 0;
3251 if (reg & WM8994_MIC1_DET_STS) {
3252 if (priv->micdet[0].detecting)
3253 report = SND_JACK_HEADSET;
3254 }
3255 if (reg & WM8994_MIC1_SHRT_STS) {
3256 if (priv->micdet[0].detecting)
3257 report = SND_JACK_HEADPHONE;
3258 else
3259 report |= SND_JACK_BTN_0;
3260 }
3261 if (report)
3262 priv->micdet[0].detecting = false;
3263 else
3264 priv->micdet[0].detecting = true;
3265
3266 snd_soc_jack_report(priv->micdet[0].jack, report,
3267 SND_JACK_HEADSET | SND_JACK_BTN_0);
3268
3269 report = 0;
3270 if (reg & WM8994_MIC2_DET_STS) {
3271 if (priv->micdet[1].detecting)
3272 report = SND_JACK_HEADSET;
3273 }
3274 if (reg & WM8994_MIC2_SHRT_STS) {
3275 if (priv->micdet[1].detecting)
3276 report = SND_JACK_HEADPHONE;
3277 else
3278 report |= SND_JACK_BTN_0;
3279 }
3280 if (report)
3281 priv->micdet[1].detecting = false;
3282 else
3283 priv->micdet[1].detecting = true;
3284
3285 snd_soc_jack_report(priv->micdet[1].jack, report,
3286 SND_JACK_HEADSET | SND_JACK_BTN_0);
3287 }
3288
3289 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3290 {
3291 struct wm8994_priv *priv = data;
3292 struct snd_soc_codec *codec = priv->codec;
3293
3294 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3295 trace_snd_soc_jack_irq(dev_name(codec->dev));
3296 #endif
3297
3298 pm_wakeup_event(codec->dev, 300);
3299
3300 schedule_delayed_work(&priv->mic_work, msecs_to_jiffies(250));
3301
3302 return IRQ_HANDLED;
3303 }
3304
3305 /* Default microphone detection handler for WM8958 - the user can
3306 * override this if they wish.
3307 */
3308 static void wm8958_default_micdet(u16 status, void *data)
3309 {
3310 struct snd_soc_codec *codec = data;
3311 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3312 int report;
3313
3314 dev_dbg(codec->dev, "MICDET %x\n", status);
3315
3316 /* Either nothing present or just starting detection */
3317 if (!(status & WM8958_MICD_STS)) {
3318 if (!wm8994->jackdet) {
3319 /* If nothing present then clear our statuses */
3320 dev_dbg(codec->dev, "Detected open circuit\n");
3321 wm8994->jack_mic = false;
3322 wm8994->mic_detecting = true;
3323
3324 wm8958_micd_set_rate(codec);
3325
3326 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3327 wm8994->btn_mask |
3328 SND_JACK_HEADSET);
3329 }
3330 return;
3331 }
3332
3333 /* If the measurement is showing a high impedence we've got a
3334 * microphone.
3335 */
3336 if (wm8994->mic_detecting && (status & 0x600)) {
3337 dev_dbg(codec->dev, "Detected microphone\n");
3338
3339 wm8994->mic_detecting = false;
3340 wm8994->jack_mic = true;
3341
3342 wm8958_micd_set_rate(codec);
3343
3344 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3345 SND_JACK_HEADSET);
3346 }
3347
3348
3349 if (wm8994->mic_detecting && status & 0xfc) {
3350 dev_dbg(codec->dev, "Detected headphone\n");
3351 wm8994->mic_detecting = false;
3352
3353 wm8958_micd_set_rate(codec);
3354
3355 /* If we have jackdet that will detect removal */
3356 if (wm8994->jackdet) {
3357 mutex_lock(&wm8994->accdet_lock);
3358
3359 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3360 WM8958_MICD_ENA, 0);
3361
3362 wm1811_jackdet_set_mode(codec,
3363 WM1811_JACKDET_MODE_JACK);
3364
3365 mutex_unlock(&wm8994->accdet_lock);
3366
3367 if (wm8994->pdata->jd_ext_cap)
3368 snd_soc_dapm_disable_pin(&codec->dapm,
3369 "MICBIAS2");
3370 }
3371
3372 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3373 SND_JACK_HEADSET);
3374 }
3375
3376 /* Report short circuit as a button */
3377 if (wm8994->jack_mic) {
3378 report = 0;
3379 if (status & 0x4)
3380 report |= SND_JACK_BTN_0;
3381
3382 if (status & 0x8)
3383 report |= SND_JACK_BTN_1;
3384
3385 if (status & 0x10)
3386 report |= SND_JACK_BTN_2;
3387
3388 if (status & 0x20)
3389 report |= SND_JACK_BTN_3;
3390
3391 if (status & 0x40)
3392 report |= SND_JACK_BTN_4;
3393
3394 if (status & 0x80)
3395 report |= SND_JACK_BTN_5;
3396
3397 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3398 wm8994->btn_mask);
3399 }
3400 }
3401
3402 static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3403 {
3404 struct wm8994_priv *wm8994 = data;
3405 struct snd_soc_codec *codec = wm8994->codec;
3406 int reg;
3407 bool present;
3408
3409 mutex_lock(&wm8994->accdet_lock);
3410
3411 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3412 if (reg < 0) {
3413 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3414 mutex_unlock(&wm8994->accdet_lock);
3415 return IRQ_NONE;
3416 }
3417
3418 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3419
3420 present = reg & WM1811_JACKDET_LVL;
3421
3422 if (present) {
3423 dev_dbg(codec->dev, "Jack detected\n");
3424
3425 wm8958_micd_set_rate(codec);
3426
3427 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3428 WM8958_MICB2_DISCH, 0);
3429
3430 /* Disable debounce while inserted */
3431 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3432 WM1811_JACKDET_DB, 0);
3433
3434 /*
3435 * Start off measument of microphone impedence to find
3436 * out what's actually there.
3437 */
3438 wm8994->mic_detecting = true;
3439 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3440
3441 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3442 WM8958_MICD_ENA, WM8958_MICD_ENA);
3443 } else {
3444 dev_dbg(codec->dev, "Jack not detected\n");
3445
3446 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3447 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3448
3449 /* Enable debounce while removed */
3450 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3451 WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3452
3453 wm8994->mic_detecting = false;
3454 wm8994->jack_mic = false;
3455 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3456 WM8958_MICD_ENA, 0);
3457 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3458 }
3459
3460 mutex_unlock(&wm8994->accdet_lock);
3461
3462 /* If required for an external cap force MICBIAS on */
3463 if (wm8994->pdata->jd_ext_cap) {
3464 if (present)
3465 snd_soc_dapm_force_enable_pin(&codec->dapm,
3466 "MICBIAS2");
3467 else
3468 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
3469 }
3470
3471 if (present)
3472 snd_soc_jack_report(wm8994->micdet[0].jack,
3473 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3474 else
3475 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3476 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3477 wm8994->btn_mask);
3478
3479 return IRQ_HANDLED;
3480 }
3481
3482 /**
3483 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3484 *
3485 * @codec: WM8958 codec
3486 * @jack: jack to report detection events on
3487 *
3488 * Enable microphone detection functionality for the WM8958. By
3489 * default simple detection which supports the detection of up to 6
3490 * buttons plus video and microphone functionality is supported.
3491 *
3492 * The WM8958 has an advanced jack detection facility which is able to
3493 * support complex accessory detection, especially when used in
3494 * conjunction with external circuitry. In order to provide maximum
3495 * flexiblity a callback is provided which allows a completely custom
3496 * detection algorithm.
3497 */
3498 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3499 wm8958_micdet_cb cb, void *cb_data)
3500 {
3501 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3502 struct wm8994 *control = wm8994->wm8994;
3503 u16 micd_lvl_sel;
3504
3505 switch (control->type) {
3506 case WM1811:
3507 case WM8958:
3508 break;
3509 default:
3510 return -EINVAL;
3511 }
3512
3513 if (jack) {
3514 if (!cb) {
3515 dev_dbg(codec->dev, "Using default micdet callback\n");
3516 cb = wm8958_default_micdet;
3517 cb_data = codec;
3518 }
3519
3520 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3521 snd_soc_dapm_sync(&codec->dapm);
3522
3523 wm8994->micdet[0].jack = jack;
3524 wm8994->jack_cb = cb;
3525 wm8994->jack_cb_data = cb_data;
3526
3527 wm8994->mic_detecting = true;
3528 wm8994->jack_mic = false;
3529
3530 wm8958_micd_set_rate(codec);
3531
3532 /* Detect microphones and short circuits by default */
3533 if (wm8994->pdata->micd_lvl_sel)
3534 micd_lvl_sel = wm8994->pdata->micd_lvl_sel;
3535 else
3536 micd_lvl_sel = 0x41;
3537
3538 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3539 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3540 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3541
3542 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
3543 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3544
3545 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3546
3547 /*
3548 * If we can use jack detection start off with that,
3549 * otherwise jump straight to microphone detection.
3550 */
3551 if (wm8994->jackdet) {
3552 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3553 WM8958_MICB2_DISCH,
3554 WM8958_MICB2_DISCH);
3555 snd_soc_update_bits(codec, WM8994_LDO_1,
3556 WM8994_LDO1_DISCH, 0);
3557 wm1811_jackdet_set_mode(codec,
3558 WM1811_JACKDET_MODE_JACK);
3559 } else {
3560 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3561 WM8958_MICD_ENA, WM8958_MICD_ENA);
3562 }
3563
3564 } else {
3565 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3566 WM8958_MICD_ENA, 0);
3567 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
3568 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
3569 snd_soc_dapm_sync(&codec->dapm);
3570 }
3571
3572 return 0;
3573 }
3574 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3575
3576 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3577 {
3578 struct wm8994_priv *wm8994 = data;
3579 struct snd_soc_codec *codec = wm8994->codec;
3580 int reg, count;
3581
3582 /*
3583 * Jack detection may have detected a removal simulataneously
3584 * with an update of the MICDET status; if so it will have
3585 * stopped detection and we can ignore this interrupt.
3586 */
3587 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
3588 return IRQ_HANDLED;
3589
3590 /* We may occasionally read a detection without an impedence
3591 * range being provided - if that happens loop again.
3592 */
3593 count = 10;
3594 do {
3595 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3596 if (reg < 0) {
3597 dev_err(codec->dev,
3598 "Failed to read mic detect status: %d\n",
3599 reg);
3600 return IRQ_NONE;
3601 }
3602
3603 if (!(reg & WM8958_MICD_VALID)) {
3604 dev_dbg(codec->dev, "Mic detect data not valid\n");
3605 goto out;
3606 }
3607
3608 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3609 break;
3610
3611 msleep(1);
3612 } while (count--);
3613
3614 if (count == 0)
3615 dev_warn(codec->dev, "No impedence range reported for jack\n");
3616
3617 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3618 trace_snd_soc_jack_irq(dev_name(codec->dev));
3619 #endif
3620
3621 if (wm8994->jack_cb)
3622 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3623 else
3624 dev_warn(codec->dev, "Accessory detection with no callback\n");
3625
3626 out:
3627 return IRQ_HANDLED;
3628 }
3629
3630 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3631 {
3632 struct snd_soc_codec *codec = data;
3633
3634 dev_err(codec->dev, "FIFO error\n");
3635
3636 return IRQ_HANDLED;
3637 }
3638
3639 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3640 {
3641 struct snd_soc_codec *codec = data;
3642
3643 dev_err(codec->dev, "Thermal warning\n");
3644
3645 return IRQ_HANDLED;
3646 }
3647
3648 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3649 {
3650 struct snd_soc_codec *codec = data;
3651
3652 dev_crit(codec->dev, "Thermal shutdown\n");
3653
3654 return IRQ_HANDLED;
3655 }
3656
3657 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3658 {
3659 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
3660 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3661 struct snd_soc_dapm_context *dapm = &codec->dapm;
3662 unsigned int reg;
3663 int ret, i;
3664
3665 wm8994->codec = codec;
3666 codec->control_data = control->regmap;
3667
3668 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
3669
3670 wm8994->codec = codec;
3671
3672 mutex_init(&wm8994->accdet_lock);
3673 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
3674
3675 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3676 init_completion(&wm8994->fll_locked[i]);
3677
3678 if (wm8994->pdata && wm8994->pdata->micdet_irq)
3679 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3680 else if (wm8994->pdata && wm8994->pdata->irq_base)
3681 wm8994->micdet_irq = wm8994->pdata->irq_base +
3682 WM8994_IRQ_MIC1_DET;
3683
3684 pm_runtime_enable(codec->dev);
3685 pm_runtime_idle(codec->dev);
3686
3687 /* By default use idle_bias_off, will override for WM8994 */
3688 codec->dapm.idle_bias_off = 1;
3689
3690 /* Set revision-specific configuration */
3691 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3692 switch (control->type) {
3693 case WM8994:
3694 /* Single ended line outputs should have VMID on. */
3695 if (!wm8994->pdata->lineout1_diff ||
3696 !wm8994->pdata->lineout2_diff)
3697 codec->dapm.idle_bias_off = 0;
3698
3699 switch (wm8994->revision) {
3700 case 2:
3701 case 3:
3702 wm8994->hubs.dcs_codes_l = -5;
3703 wm8994->hubs.dcs_codes_r = -5;
3704 wm8994->hubs.hp_startup_mode = 1;
3705 wm8994->hubs.dcs_readback_mode = 1;
3706 wm8994->hubs.series_startup = 1;
3707 break;
3708 default:
3709 wm8994->hubs.dcs_readback_mode = 2;
3710 break;
3711 }
3712 break;
3713
3714 case WM8958:
3715 wm8994->hubs.dcs_readback_mode = 1;
3716 wm8994->hubs.hp_startup_mode = 1;
3717
3718 switch (wm8994->revision) {
3719 case 0:
3720 break;
3721 default:
3722 wm8994->fll_byp = true;
3723 break;
3724 }
3725 break;
3726
3727 case WM1811:
3728 wm8994->hubs.dcs_readback_mode = 2;
3729 wm8994->hubs.no_series_update = 1;
3730 wm8994->hubs.hp_startup_mode = 1;
3731 wm8994->hubs.no_cache_dac_hp_direct = true;
3732 wm8994->fll_byp = true;
3733
3734 switch (wm8994->revision) {
3735 case 0:
3736 case 1:
3737 case 2:
3738 case 3:
3739 wm8994->hubs.dcs_codes_l = -9;
3740 wm8994->hubs.dcs_codes_r = -7;
3741 break;
3742 default:
3743 break;
3744 }
3745
3746 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3747 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3748 break;
3749
3750 default:
3751 break;
3752 }
3753
3754 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3755 wm8994_fifo_error, "FIFO error", codec);
3756 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
3757 wm8994_temp_warn, "Thermal warning", codec);
3758 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
3759 wm8994_temp_shut, "Thermal shutdown", codec);
3760
3761 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3762 wm_hubs_dcs_done, "DC servo done",
3763 &wm8994->hubs);
3764 if (ret == 0)
3765 wm8994->hubs.dcs_done_irq = true;
3766
3767 switch (control->type) {
3768 case WM8994:
3769 if (wm8994->micdet_irq) {
3770 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3771 wm8994_mic_irq,
3772 IRQF_TRIGGER_RISING,
3773 "Mic1 detect",
3774 wm8994);
3775 if (ret != 0)
3776 dev_warn(codec->dev,
3777 "Failed to request Mic1 detect IRQ: %d\n",
3778 ret);
3779 }
3780
3781 ret = wm8994_request_irq(wm8994->wm8994,
3782 WM8994_IRQ_MIC1_SHRT,
3783 wm8994_mic_irq, "Mic 1 short",
3784 wm8994);
3785 if (ret != 0)
3786 dev_warn(codec->dev,
3787 "Failed to request Mic1 short IRQ: %d\n",
3788 ret);
3789
3790 ret = wm8994_request_irq(wm8994->wm8994,
3791 WM8994_IRQ_MIC2_DET,
3792 wm8994_mic_irq, "Mic 2 detect",
3793 wm8994);
3794 if (ret != 0)
3795 dev_warn(codec->dev,
3796 "Failed to request Mic2 detect IRQ: %d\n",
3797 ret);
3798
3799 ret = wm8994_request_irq(wm8994->wm8994,
3800 WM8994_IRQ_MIC2_SHRT,
3801 wm8994_mic_irq, "Mic 2 short",
3802 wm8994);
3803 if (ret != 0)
3804 dev_warn(codec->dev,
3805 "Failed to request Mic2 short IRQ: %d\n",
3806 ret);
3807 break;
3808
3809 case WM8958:
3810 case WM1811:
3811 if (wm8994->micdet_irq) {
3812 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3813 wm8958_mic_irq,
3814 IRQF_TRIGGER_RISING,
3815 "Mic detect",
3816 wm8994);
3817 if (ret != 0)
3818 dev_warn(codec->dev,
3819 "Failed to request Mic detect IRQ: %d\n",
3820 ret);
3821 }
3822 }
3823
3824 switch (control->type) {
3825 case WM1811:
3826 if (wm8994->revision > 1) {
3827 ret = wm8994_request_irq(wm8994->wm8994,
3828 WM8994_IRQ_GPIO(6),
3829 wm1811_jackdet_irq, "JACKDET",
3830 wm8994);
3831 if (ret == 0)
3832 wm8994->jackdet = true;
3833 }
3834 break;
3835 default:
3836 break;
3837 }
3838
3839 wm8994->fll_locked_irq = true;
3840 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
3841 ret = wm8994_request_irq(wm8994->wm8994,
3842 WM8994_IRQ_FLL1_LOCK + i,
3843 wm8994_fll_locked_irq, "FLL lock",
3844 &wm8994->fll_locked[i]);
3845 if (ret != 0)
3846 wm8994->fll_locked_irq = false;
3847 }
3848
3849 /* Make sure we can read from the GPIOs if they're inputs */
3850 pm_runtime_get_sync(codec->dev);
3851
3852 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3853 * configured on init - if a system wants to do this dynamically
3854 * at runtime we can deal with that then.
3855 */
3856 ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
3857 if (ret < 0) {
3858 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3859 goto err_irq;
3860 }
3861 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3862 wm8994->lrclk_shared[0] = 1;
3863 wm8994_dai[0].symmetric_rates = 1;
3864 } else {
3865 wm8994->lrclk_shared[0] = 0;
3866 }
3867
3868 ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
3869 if (ret < 0) {
3870 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3871 goto err_irq;
3872 }
3873 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3874 wm8994->lrclk_shared[1] = 1;
3875 wm8994_dai[1].symmetric_rates = 1;
3876 } else {
3877 wm8994->lrclk_shared[1] = 0;
3878 }
3879
3880 pm_runtime_put(codec->dev);
3881
3882 /* Latch volume updates (right only; we always do left then right). */
3883 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3884 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3885 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3886 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3887 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3888 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3889 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3890 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3891 snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3892 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3893 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3894 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3895 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3896 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3897 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3898 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3899 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3900 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3901 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3902 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3903 snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3904 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3905 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3906 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3907 snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3908 WM8994_DAC1_VU, WM8994_DAC1_VU);
3909 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3910 WM8994_DAC1_VU, WM8994_DAC1_VU);
3911 snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3912 WM8994_DAC2_VU, WM8994_DAC2_VU);
3913 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3914 WM8994_DAC2_VU, WM8994_DAC2_VU);
3915
3916 /* Set the low bit of the 3D stereo depth so TLV matches */
3917 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3918 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3919 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3920 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3921 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3922 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3923 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3924 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3925 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3926
3927 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3928 * use this; it only affects behaviour on idle TDM clock
3929 * cycles. */
3930 switch (control->type) {
3931 case WM8994:
3932 case WM8958:
3933 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3934 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3935 break;
3936 default:
3937 break;
3938 }
3939
3940 /* Put MICBIAS into bypass mode by default on newer devices */
3941 switch (control->type) {
3942 case WM8958:
3943 case WM1811:
3944 snd_soc_update_bits(codec, WM8958_MICBIAS1,
3945 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
3946 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3947 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
3948 break;
3949 default:
3950 break;
3951 }
3952
3953 wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
3954 wm_hubs_update_class_w(codec);
3955
3956 wm8994_handle_pdata(wm8994);
3957
3958 wm_hubs_add_analogue_controls(codec);
3959 snd_soc_add_codec_controls(codec, wm8994_snd_controls,
3960 ARRAY_SIZE(wm8994_snd_controls));
3961 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3962 ARRAY_SIZE(wm8994_dapm_widgets));
3963
3964 switch (control->type) {
3965 case WM8994:
3966 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3967 ARRAY_SIZE(wm8994_specific_dapm_widgets));
3968 if (wm8994->revision < 4) {
3969 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3970 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3971 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3972 ARRAY_SIZE(wm8994_adc_revd_widgets));
3973 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3974 ARRAY_SIZE(wm8994_dac_revd_widgets));
3975 } else {
3976 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3977 ARRAY_SIZE(wm8994_lateclk_widgets));
3978 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3979 ARRAY_SIZE(wm8994_adc_widgets));
3980 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3981 ARRAY_SIZE(wm8994_dac_widgets));
3982 }
3983 break;
3984 case WM8958:
3985 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
3986 ARRAY_SIZE(wm8958_snd_controls));
3987 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3988 ARRAY_SIZE(wm8958_dapm_widgets));
3989 if (wm8994->revision < 1) {
3990 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3991 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3992 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3993 ARRAY_SIZE(wm8994_adc_revd_widgets));
3994 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3995 ARRAY_SIZE(wm8994_dac_revd_widgets));
3996 } else {
3997 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3998 ARRAY_SIZE(wm8994_lateclk_widgets));
3999 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4000 ARRAY_SIZE(wm8994_adc_widgets));
4001 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4002 ARRAY_SIZE(wm8994_dac_widgets));
4003 }
4004 break;
4005
4006 case WM1811:
4007 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4008 ARRAY_SIZE(wm8958_snd_controls));
4009 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4010 ARRAY_SIZE(wm8958_dapm_widgets));
4011 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4012 ARRAY_SIZE(wm8994_lateclk_widgets));
4013 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4014 ARRAY_SIZE(wm8994_adc_widgets));
4015 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4016 ARRAY_SIZE(wm8994_dac_widgets));
4017 break;
4018 }
4019
4020 wm_hubs_add_analogue_routes(codec, 0, 0);
4021 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
4022
4023 switch (control->type) {
4024 case WM8994:
4025 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4026 ARRAY_SIZE(wm8994_intercon));
4027
4028 if (wm8994->revision < 4) {
4029 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4030 ARRAY_SIZE(wm8994_revd_intercon));
4031 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4032 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4033 } else {
4034 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4035 ARRAY_SIZE(wm8994_lateclk_intercon));
4036 }
4037 break;
4038 case WM8958:
4039 if (wm8994->revision < 1) {
4040 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4041 ARRAY_SIZE(wm8994_revd_intercon));
4042 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4043 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4044 } else {
4045 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4046 ARRAY_SIZE(wm8994_lateclk_intercon));
4047 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4048 ARRAY_SIZE(wm8958_intercon));
4049 }
4050
4051 wm8958_dsp2_init(codec);
4052 break;
4053 case WM1811:
4054 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4055 ARRAY_SIZE(wm8994_lateclk_intercon));
4056 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4057 ARRAY_SIZE(wm8958_intercon));
4058 break;
4059 }
4060
4061 return 0;
4062
4063 err_irq:
4064 if (wm8994->jackdet)
4065 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4066 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4067 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4068 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
4069 if (wm8994->micdet_irq)
4070 free_irq(wm8994->micdet_irq, wm8994);
4071 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4072 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4073 &wm8994->fll_locked[i]);
4074 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4075 &wm8994->hubs);
4076 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4077 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4078 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4079
4080 return ret;
4081 }
4082
4083 static int wm8994_codec_remove(struct snd_soc_codec *codec)
4084 {
4085 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4086 struct wm8994 *control = wm8994->wm8994;
4087 int i;
4088
4089 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
4090
4091 pm_runtime_disable(codec->dev);
4092
4093 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4094 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4095 &wm8994->fll_locked[i]);
4096
4097 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4098 &wm8994->hubs);
4099 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4100 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4101 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4102
4103 if (wm8994->jackdet)
4104 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4105
4106 switch (control->type) {
4107 case WM8994:
4108 if (wm8994->micdet_irq)
4109 free_irq(wm8994->micdet_irq, wm8994);
4110 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
4111 wm8994);
4112 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
4113 wm8994);
4114 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4115 wm8994);
4116 break;
4117
4118 case WM1811:
4119 case WM8958:
4120 if (wm8994->micdet_irq)
4121 free_irq(wm8994->micdet_irq, wm8994);
4122 break;
4123 }
4124 release_firmware(wm8994->mbc);
4125 release_firmware(wm8994->mbc_vss);
4126 release_firmware(wm8994->enh_eq);
4127 kfree(wm8994->retune_mobile_texts);
4128 return 0;
4129 }
4130
4131 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4132 .probe = wm8994_codec_probe,
4133 .remove = wm8994_codec_remove,
4134 .suspend = wm8994_codec_suspend,
4135 .resume = wm8994_codec_resume,
4136 .set_bias_level = wm8994_set_bias_level,
4137 };
4138
4139 static int __devinit wm8994_probe(struct platform_device *pdev)
4140 {
4141 struct wm8994_priv *wm8994;
4142
4143 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4144 GFP_KERNEL);
4145 if (wm8994 == NULL)
4146 return -ENOMEM;
4147 platform_set_drvdata(pdev, wm8994);
4148
4149 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
4150 wm8994->pdata = dev_get_platdata(pdev->dev.parent);
4151
4152 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4153 wm8994_dai, ARRAY_SIZE(wm8994_dai));
4154 }
4155
4156 static int __devexit wm8994_remove(struct platform_device *pdev)
4157 {
4158 snd_soc_unregister_codec(&pdev->dev);
4159 return 0;
4160 }
4161
4162 #ifdef CONFIG_PM_SLEEP
4163 static int wm8994_suspend(struct device *dev)
4164 {
4165 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4166
4167 /* Drop down to power saving mode when system is suspended */
4168 if (wm8994->jackdet && !wm8994->active_refcount)
4169 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4170 WM1811_JACKDET_MODE_MASK,
4171 wm8994->jackdet_mode);
4172
4173 return 0;
4174 }
4175
4176 static int wm8994_resume(struct device *dev)
4177 {
4178 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4179
4180 if (wm8994->jackdet && wm8994->jack_cb)
4181 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4182 WM1811_JACKDET_MODE_MASK,
4183 WM1811_JACKDET_MODE_AUDIO);
4184
4185 return 0;
4186 }
4187 #endif
4188
4189 static const struct dev_pm_ops wm8994_pm_ops = {
4190 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4191 };
4192
4193 static struct platform_driver wm8994_codec_driver = {
4194 .driver = {
4195 .name = "wm8994-codec",
4196 .owner = THIS_MODULE,
4197 .pm = &wm8994_pm_ops,
4198 },
4199 .probe = wm8994_probe,
4200 .remove = __devexit_p(wm8994_remove),
4201 };
4202
4203 module_platform_driver(wm8994_codec_driver);
4204
4205 MODULE_DESCRIPTION("ASoC WM8994 driver");
4206 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4207 MODULE_LICENSE("GPL");
4208 MODULE_ALIAS("platform:wm8994-codec");
Linux kernel - Deliverables
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