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ASoC: WM8994: Don't disable the AIF[1|2]CLK_ENA unconditionaly
[deliverable/linux.git] / sound / soc / codecs / wm8994.c
1 /*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/jack.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <trace/events/asoc.h>
32
33 #include <linux/mfd/wm8994/core.h>
34 #include <linux/mfd/wm8994/registers.h>
35 #include <linux/mfd/wm8994/pdata.h>
36 #include <linux/mfd/wm8994/gpio.h>
37
38 #include "wm8994.h"
39 #include "wm_hubs.h"
40
41 struct fll_config {
42 int src;
43 int in;
44 int out;
45 };
46
47 #define WM8994_NUM_DRC 3
48 #define WM8994_NUM_EQ 3
49
50 static int wm8994_drc_base[] = {
51 WM8994_AIF1_DRC1_1,
52 WM8994_AIF1_DRC2_1,
53 WM8994_AIF2_DRC_1,
54 };
55
56 static int wm8994_retune_mobile_base[] = {
57 WM8994_AIF1_DAC1_EQ_GAINS_1,
58 WM8994_AIF1_DAC2_EQ_GAINS_1,
59 WM8994_AIF2_EQ_GAINS_1,
60 };
61
62 struct wm8994_micdet {
63 struct snd_soc_jack *jack;
64 int det;
65 int shrt;
66 };
67
68 /* codec private data */
69 struct wm8994_priv {
70 struct wm_hubs_data hubs;
71 enum snd_soc_control_type control_type;
72 void *control_data;
73 struct snd_soc_codec *codec;
74 int sysclk[2];
75 int sysclk_rate[2];
76 int mclk[2];
77 int aifclk[2];
78 struct fll_config fll[2], fll_suspend[2];
79
80 int dac_rates[2];
81 int lrclk_shared[2];
82
83 int mbc_ena[3];
84
85 /* Platform dependant DRC configuration */
86 const char **drc_texts;
87 int drc_cfg[WM8994_NUM_DRC];
88 struct soc_enum drc_enum;
89
90 /* Platform dependant ReTune mobile configuration */
91 int num_retune_mobile_texts;
92 const char **retune_mobile_texts;
93 int retune_mobile_cfg[WM8994_NUM_EQ];
94 struct soc_enum retune_mobile_enum;
95
96 /* Platform dependant MBC configuration */
97 int mbc_cfg;
98 const char **mbc_texts;
99 struct soc_enum mbc_enum;
100
101 struct wm8994_micdet micdet[2];
102
103 wm8958_micdet_cb jack_cb;
104 void *jack_cb_data;
105 bool jack_is_mic;
106 bool jack_is_video;
107
108 int revision;
109 struct wm8994_pdata *pdata;
110
111 unsigned int aif1clk_enable:1;
112 unsigned int aif2clk_enable:1;
113
114 unsigned int aif1clk_disable:1;
115 unsigned int aif2clk_disable:1;
116 };
117
118 static int wm8994_readable(unsigned int reg)
119 {
120 switch (reg) {
121 case WM8994_GPIO_1:
122 case WM8994_GPIO_2:
123 case WM8994_GPIO_3:
124 case WM8994_GPIO_4:
125 case WM8994_GPIO_5:
126 case WM8994_GPIO_6:
127 case WM8994_GPIO_7:
128 case WM8994_GPIO_8:
129 case WM8994_GPIO_9:
130 case WM8994_GPIO_10:
131 case WM8994_GPIO_11:
132 case WM8994_INTERRUPT_STATUS_1:
133 case WM8994_INTERRUPT_STATUS_2:
134 case WM8994_INTERRUPT_RAW_STATUS_2:
135 return 1;
136 default:
137 break;
138 }
139
140 if (reg >= WM8994_CACHE_SIZE)
141 return 0;
142 return wm8994_access_masks[reg].readable != 0;
143 }
144
145 static int wm8994_volatile(unsigned int reg)
146 {
147 if (reg >= WM8994_CACHE_SIZE)
148 return 1;
149
150 switch (reg) {
151 case WM8994_SOFTWARE_RESET:
152 case WM8994_CHIP_REVISION:
153 case WM8994_DC_SERVO_1:
154 case WM8994_DC_SERVO_READBACK:
155 case WM8994_RATE_STATUS:
156 case WM8994_LDO_1:
157 case WM8994_LDO_2:
158 case WM8958_DSP2_EXECCONTROL:
159 case WM8958_MIC_DETECT_3:
160 return 1;
161 default:
162 return 0;
163 }
164 }
165
166 static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
167 unsigned int value)
168 {
169 int ret;
170
171 BUG_ON(reg > WM8994_MAX_REGISTER);
172
173 if (!wm8994_volatile(reg)) {
174 ret = snd_soc_cache_write(codec, reg, value);
175 if (ret != 0)
176 dev_err(codec->dev, "Cache write to %x failed: %d\n",
177 reg, ret);
178 }
179
180 return wm8994_reg_write(codec->control_data, reg, value);
181 }
182
183 static unsigned int wm8994_read(struct snd_soc_codec *codec,
184 unsigned int reg)
185 {
186 unsigned int val;
187 int ret;
188
189 BUG_ON(reg > WM8994_MAX_REGISTER);
190
191 if (!wm8994_volatile(reg) && wm8994_readable(reg) &&
192 reg < codec->driver->reg_cache_size) {
193 ret = snd_soc_cache_read(codec, reg, &val);
194 if (ret >= 0)
195 return val;
196 else
197 dev_err(codec->dev, "Cache read from %x failed: %d\n",
198 reg, ret);
199 }
200
201 return wm8994_reg_read(codec->control_data, reg);
202 }
203
204 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
205 {
206 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
207 int rate;
208 int reg1 = 0;
209 int offset;
210
211 if (aif)
212 offset = 4;
213 else
214 offset = 0;
215
216 switch (wm8994->sysclk[aif]) {
217 case WM8994_SYSCLK_MCLK1:
218 rate = wm8994->mclk[0];
219 break;
220
221 case WM8994_SYSCLK_MCLK2:
222 reg1 |= 0x8;
223 rate = wm8994->mclk[1];
224 break;
225
226 case WM8994_SYSCLK_FLL1:
227 reg1 |= 0x10;
228 rate = wm8994->fll[0].out;
229 break;
230
231 case WM8994_SYSCLK_FLL2:
232 reg1 |= 0x18;
233 rate = wm8994->fll[1].out;
234 break;
235
236 default:
237 return -EINVAL;
238 }
239
240 if (rate >= 13500000) {
241 rate /= 2;
242 reg1 |= WM8994_AIF1CLK_DIV;
243
244 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
245 aif + 1, rate);
246 }
247
248 if (rate && rate < 3000000)
249 dev_warn(codec->dev, "AIF%dCLK is %dHz, should be >=3MHz for optimal performance\n",
250 aif + 1, rate);
251
252 wm8994->aifclk[aif] = rate;
253
254 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
255 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
256 reg1);
257
258 return 0;
259 }
260
261 static int configure_clock(struct snd_soc_codec *codec)
262 {
263 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
264 int old, new;
265
266 /* Bring up the AIF clocks first */
267 configure_aif_clock(codec, 0);
268 configure_aif_clock(codec, 1);
269
270 /* Then switch CLK_SYS over to the higher of them; a change
271 * can only happen as a result of a clocking change which can
272 * only be made outside of DAPM so we can safely redo the
273 * clocking.
274 */
275
276 /* If they're equal it doesn't matter which is used */
277 if (wm8994->aifclk[0] == wm8994->aifclk[1])
278 return 0;
279
280 if (wm8994->aifclk[0] < wm8994->aifclk[1])
281 new = WM8994_SYSCLK_SRC;
282 else
283 new = 0;
284
285 old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
286
287 /* If there's no change then we're done. */
288 if (old == new)
289 return 0;
290
291 snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
292
293 snd_soc_dapm_sync(&codec->dapm);
294
295 return 0;
296 }
297
298 static int check_clk_sys(struct snd_soc_dapm_widget *source,
299 struct snd_soc_dapm_widget *sink)
300 {
301 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
302 const char *clk;
303
304 /* Check what we're currently using for CLK_SYS */
305 if (reg & WM8994_SYSCLK_SRC)
306 clk = "AIF2CLK";
307 else
308 clk = "AIF1CLK";
309
310 return strcmp(source->name, clk) == 0;
311 }
312
313 static const char *sidetone_hpf_text[] = {
314 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
315 };
316
317 static const struct soc_enum sidetone_hpf =
318 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
319
320 static const char *adc_hpf_text[] = {
321 "HiFi", "Voice 1", "Voice 2", "Voice 3"
322 };
323
324 static const struct soc_enum aif1adc1_hpf =
325 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
326
327 static const struct soc_enum aif1adc2_hpf =
328 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
329
330 static const struct soc_enum aif2adc_hpf =
331 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
332
333 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
334 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
335 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
336 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
337 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
338
339 #define WM8994_DRC_SWITCH(xname, reg, shift) \
340 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
341 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
342 .put = wm8994_put_drc_sw, \
343 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
344
345 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
346 struct snd_ctl_elem_value *ucontrol)
347 {
348 struct soc_mixer_control *mc =
349 (struct soc_mixer_control *)kcontrol->private_value;
350 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
351 int mask, ret;
352
353 /* Can't enable both ADC and DAC paths simultaneously */
354 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
355 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
356 WM8994_AIF1ADC1R_DRC_ENA_MASK;
357 else
358 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
359
360 ret = snd_soc_read(codec, mc->reg);
361 if (ret < 0)
362 return ret;
363 if (ret & mask)
364 return -EINVAL;
365
366 return snd_soc_put_volsw(kcontrol, ucontrol);
367 }
368
369 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
370 {
371 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
372 struct wm8994_pdata *pdata = wm8994->pdata;
373 int base = wm8994_drc_base[drc];
374 int cfg = wm8994->drc_cfg[drc];
375 int save, i;
376
377 /* Save any enables; the configuration should clear them. */
378 save = snd_soc_read(codec, base);
379 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
380 WM8994_AIF1ADC1R_DRC_ENA;
381
382 for (i = 0; i < WM8994_DRC_REGS; i++)
383 snd_soc_update_bits(codec, base + i, 0xffff,
384 pdata->drc_cfgs[cfg].regs[i]);
385
386 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
387 WM8994_AIF1ADC1L_DRC_ENA |
388 WM8994_AIF1ADC1R_DRC_ENA, save);
389 }
390
391 /* Icky as hell but saves code duplication */
392 static int wm8994_get_drc(const char *name)
393 {
394 if (strcmp(name, "AIF1DRC1 Mode") == 0)
395 return 0;
396 if (strcmp(name, "AIF1DRC2 Mode") == 0)
397 return 1;
398 if (strcmp(name, "AIF2DRC Mode") == 0)
399 return 2;
400 return -EINVAL;
401 }
402
403 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
404 struct snd_ctl_elem_value *ucontrol)
405 {
406 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
407 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
408 struct wm8994_pdata *pdata = wm8994->pdata;
409 int drc = wm8994_get_drc(kcontrol->id.name);
410 int value = ucontrol->value.integer.value[0];
411
412 if (drc < 0)
413 return drc;
414
415 if (value >= pdata->num_drc_cfgs)
416 return -EINVAL;
417
418 wm8994->drc_cfg[drc] = value;
419
420 wm8994_set_drc(codec, drc);
421
422 return 0;
423 }
424
425 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
426 struct snd_ctl_elem_value *ucontrol)
427 {
428 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
429 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
430 int drc = wm8994_get_drc(kcontrol->id.name);
431
432 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
433
434 return 0;
435 }
436
437 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
438 {
439 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
440 struct wm8994_pdata *pdata = wm8994->pdata;
441 int base = wm8994_retune_mobile_base[block];
442 int iface, best, best_val, save, i, cfg;
443
444 if (!pdata || !wm8994->num_retune_mobile_texts)
445 return;
446
447 switch (block) {
448 case 0:
449 case 1:
450 iface = 0;
451 break;
452 case 2:
453 iface = 1;
454 break;
455 default:
456 return;
457 }
458
459 /* Find the version of the currently selected configuration
460 * with the nearest sample rate. */
461 cfg = wm8994->retune_mobile_cfg[block];
462 best = 0;
463 best_val = INT_MAX;
464 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
465 if (strcmp(pdata->retune_mobile_cfgs[i].name,
466 wm8994->retune_mobile_texts[cfg]) == 0 &&
467 abs(pdata->retune_mobile_cfgs[i].rate
468 - wm8994->dac_rates[iface]) < best_val) {
469 best = i;
470 best_val = abs(pdata->retune_mobile_cfgs[i].rate
471 - wm8994->dac_rates[iface]);
472 }
473 }
474
475 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
476 block,
477 pdata->retune_mobile_cfgs[best].name,
478 pdata->retune_mobile_cfgs[best].rate,
479 wm8994->dac_rates[iface]);
480
481 /* The EQ will be disabled while reconfiguring it, remember the
482 * current configuration.
483 */
484 save = snd_soc_read(codec, base);
485 save &= WM8994_AIF1DAC1_EQ_ENA;
486
487 for (i = 0; i < WM8994_EQ_REGS; i++)
488 snd_soc_update_bits(codec, base + i, 0xffff,
489 pdata->retune_mobile_cfgs[best].regs[i]);
490
491 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
492 }
493
494 /* Icky as hell but saves code duplication */
495 static int wm8994_get_retune_mobile_block(const char *name)
496 {
497 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
498 return 0;
499 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
500 return 1;
501 if (strcmp(name, "AIF2 EQ Mode") == 0)
502 return 2;
503 return -EINVAL;
504 }
505
506 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
507 struct snd_ctl_elem_value *ucontrol)
508 {
509 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
510 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
511 struct wm8994_pdata *pdata = wm8994->pdata;
512 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
513 int value = ucontrol->value.integer.value[0];
514
515 if (block < 0)
516 return block;
517
518 if (value >= pdata->num_retune_mobile_cfgs)
519 return -EINVAL;
520
521 wm8994->retune_mobile_cfg[block] = value;
522
523 wm8994_set_retune_mobile(codec, block);
524
525 return 0;
526 }
527
528 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
529 struct snd_ctl_elem_value *ucontrol)
530 {
531 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
532 struct wm8994_priv *wm8994 =snd_soc_codec_get_drvdata(codec);
533 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
534
535 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
536
537 return 0;
538 }
539
540 static const char *aif_chan_src_text[] = {
541 "Left", "Right"
542 };
543
544 static const struct soc_enum aif1adcl_src =
545 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
546
547 static const struct soc_enum aif1adcr_src =
548 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
549
550 static const struct soc_enum aif2adcl_src =
551 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
552
553 static const struct soc_enum aif2adcr_src =
554 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
555
556 static const struct soc_enum aif1dacl_src =
557 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
558
559 static const struct soc_enum aif1dacr_src =
560 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
561
562 static const struct soc_enum aif2dacl_src =
563 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
564
565 static const struct soc_enum aif2dacr_src =
566 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
567
568 static const char *osr_text[] = {
569 "Low Power", "High Performance",
570 };
571
572 static const struct soc_enum dac_osr =
573 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
574
575 static const struct soc_enum adc_osr =
576 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
577
578 static void wm8958_mbc_apply(struct snd_soc_codec *codec, int mbc, int start)
579 {
580 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
581 struct wm8994_pdata *pdata = wm8994->pdata;
582 int pwr_reg = snd_soc_read(codec, WM8994_POWER_MANAGEMENT_5);
583 int ena, reg, aif, i;
584
585 switch (mbc) {
586 case 0:
587 pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA);
588 aif = 0;
589 break;
590 case 1:
591 pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
592 aif = 0;
593 break;
594 case 2:
595 pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA);
596 aif = 1;
597 break;
598 default:
599 BUG();
600 return;
601 }
602
603 /* We can only enable the MBC if the AIF is enabled and we
604 * want it to be enabled. */
605 ena = pwr_reg && wm8994->mbc_ena[mbc];
606
607 reg = snd_soc_read(codec, WM8958_DSP2_PROGRAM);
608
609 dev_dbg(codec->dev, "MBC %d startup: %d, power: %x, DSP: %x\n",
610 mbc, start, pwr_reg, reg);
611
612 if (start && ena) {
613 /* If the DSP is already running then noop */
614 if (reg & WM8958_DSP2_ENA)
615 return;
616
617 /* Switch the clock over to the appropriate AIF */
618 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
619 WM8958_DSP2CLK_SRC | WM8958_DSP2CLK_ENA,
620 aif << WM8958_DSP2CLK_SRC_SHIFT |
621 WM8958_DSP2CLK_ENA);
622
623 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
624 WM8958_DSP2_ENA, WM8958_DSP2_ENA);
625
626 /* If we've got user supplied MBC settings use them */
627 if (pdata && pdata->num_mbc_cfgs) {
628 struct wm8958_mbc_cfg *cfg
629 = &pdata->mbc_cfgs[wm8994->mbc_cfg];
630
631 for (i = 0; i < ARRAY_SIZE(cfg->coeff_regs); i++)
632 snd_soc_write(codec, i + WM8958_MBC_BAND_1_K_1,
633 cfg->coeff_regs[i]);
634
635 for (i = 0; i < ARRAY_SIZE(cfg->cutoff_regs); i++)
636 snd_soc_write(codec,
637 i + WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1,
638 cfg->cutoff_regs[i]);
639 }
640
641 /* Run the DSP */
642 snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
643 WM8958_DSP2_RUNR);
644
645 /* And we're off! */
646 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
647 WM8958_MBC_ENA | WM8958_MBC_SEL_MASK,
648 mbc << WM8958_MBC_SEL_SHIFT |
649 WM8958_MBC_ENA);
650 } else {
651 /* If the DSP is already stopped then noop */
652 if (!(reg & WM8958_DSP2_ENA))
653 return;
654
655 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
656 WM8958_MBC_ENA, 0);
657 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
658 WM8958_DSP2_ENA, 0);
659 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
660 WM8958_DSP2CLK_ENA, 0);
661 }
662 }
663
664 static int wm8958_aif_ev(struct snd_soc_dapm_widget *w,
665 struct snd_kcontrol *kcontrol, int event)
666 {
667 struct snd_soc_codec *codec = w->codec;
668 int mbc;
669
670 switch (w->shift) {
671 case 13:
672 case 12:
673 mbc = 2;
674 break;
675 case 11:
676 case 10:
677 mbc = 1;
678 break;
679 case 9:
680 case 8:
681 mbc = 0;
682 break;
683 default:
684 BUG();
685 return -EINVAL;
686 }
687
688 switch (event) {
689 case SND_SOC_DAPM_POST_PMU:
690 wm8958_mbc_apply(codec, mbc, 1);
691 break;
692 case SND_SOC_DAPM_POST_PMD:
693 wm8958_mbc_apply(codec, mbc, 0);
694 break;
695 }
696
697 return 0;
698 }
699
700 static int wm8958_put_mbc_enum(struct snd_kcontrol *kcontrol,
701 struct snd_ctl_elem_value *ucontrol)
702 {
703 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
704 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
705 struct wm8994_pdata *pdata = wm8994->pdata;
706 int value = ucontrol->value.integer.value[0];
707 int reg;
708
709 /* Don't allow on the fly reconfiguration */
710 reg = snd_soc_read(codec, WM8994_CLOCKING_1);
711 if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
712 return -EBUSY;
713
714 if (value >= pdata->num_mbc_cfgs)
715 return -EINVAL;
716
717 wm8994->mbc_cfg = value;
718
719 return 0;
720 }
721
722 static int wm8958_get_mbc_enum(struct snd_kcontrol *kcontrol,
723 struct snd_ctl_elem_value *ucontrol)
724 {
725 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
726 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
727
728 ucontrol->value.enumerated.item[0] = wm8994->mbc_cfg;
729
730 return 0;
731 }
732
733 static int wm8958_mbc_info(struct snd_kcontrol *kcontrol,
734 struct snd_ctl_elem_info *uinfo)
735 {
736 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
737 uinfo->count = 1;
738 uinfo->value.integer.min = 0;
739 uinfo->value.integer.max = 1;
740 return 0;
741 }
742
743 static int wm8958_mbc_get(struct snd_kcontrol *kcontrol,
744 struct snd_ctl_elem_value *ucontrol)
745 {
746 int mbc = kcontrol->private_value;
747 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
748 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
749
750 ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc];
751
752 return 0;
753 }
754
755 static int wm8958_mbc_put(struct snd_kcontrol *kcontrol,
756 struct snd_ctl_elem_value *ucontrol)
757 {
758 int mbc = kcontrol->private_value;
759 int i;
760 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
761 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
762
763 if (ucontrol->value.integer.value[0] > 1)
764 return -EINVAL;
765
766 for (i = 0; i < ARRAY_SIZE(wm8994->mbc_ena); i++) {
767 if (mbc != i && wm8994->mbc_ena[i]) {
768 dev_dbg(codec->dev, "MBC %d active already\n", mbc);
769 return -EBUSY;
770 }
771 }
772
773 wm8994->mbc_ena[mbc] = ucontrol->value.integer.value[0];
774
775 wm8958_mbc_apply(codec, mbc, wm8994->mbc_ena[mbc]);
776
777 return 0;
778 }
779
780 #define WM8958_MBC_SWITCH(xname, xval) {\
781 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
782 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
783 .info = wm8958_mbc_info, \
784 .get = wm8958_mbc_get, .put = wm8958_mbc_put, \
785 .private_value = xval }
786
787 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
788 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
789 WM8994_AIF1_ADC1_RIGHT_VOLUME,
790 1, 119, 0, digital_tlv),
791 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
792 WM8994_AIF1_ADC2_RIGHT_VOLUME,
793 1, 119, 0, digital_tlv),
794 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
795 WM8994_AIF2_ADC_RIGHT_VOLUME,
796 1, 119, 0, digital_tlv),
797
798 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
799 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
800 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
801 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
802
803 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
804 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
805 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
806 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
807
808 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
809 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
810 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
811 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
812 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
813 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
814
815 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
816 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
817
818 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
819 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
820 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
821
822 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
823 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
824 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
825
826 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
827 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
828 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
829
830 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
831 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
832 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
833
834 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
835 5, 12, 0, st_tlv),
836 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
837 0, 12, 0, st_tlv),
838 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
839 5, 12, 0, st_tlv),
840 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
841 0, 12, 0, st_tlv),
842 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
843 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
844
845 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
846 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
847
848 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
849 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
850
851 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
852 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
853
854 SOC_ENUM("ADC OSR", adc_osr),
855 SOC_ENUM("DAC OSR", dac_osr),
856
857 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
858 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
859 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
860 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
861
862 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
863 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
864 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
865 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
866
867 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
868 6, 1, 1, wm_hubs_spkmix_tlv),
869 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
870 2, 1, 1, wm_hubs_spkmix_tlv),
871
872 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
873 6, 1, 1, wm_hubs_spkmix_tlv),
874 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
875 2, 1, 1, wm_hubs_spkmix_tlv),
876
877 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
878 10, 15, 0, wm8994_3d_tlv),
879 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
880 8, 1, 0),
881 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
882 10, 15, 0, wm8994_3d_tlv),
883 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
884 8, 1, 0),
885 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
886 10, 15, 0, wm8994_3d_tlv),
887 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
888 8, 1, 0),
889 };
890
891 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
892 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
893 eq_tlv),
894 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
895 eq_tlv),
896 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
897 eq_tlv),
898 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
899 eq_tlv),
900 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
901 eq_tlv),
902
903 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
904 eq_tlv),
905 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
906 eq_tlv),
907 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
908 eq_tlv),
909 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
910 eq_tlv),
911 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
912 eq_tlv),
913
914 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
915 eq_tlv),
916 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
917 eq_tlv),
918 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
919 eq_tlv),
920 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
921 eq_tlv),
922 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
923 eq_tlv),
924 };
925
926 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
927 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
928 WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0),
929 WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1),
930 WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2),
931 };
932
933 static int clk_sys_event(struct snd_soc_dapm_widget *w,
934 struct snd_kcontrol *kcontrol, int event)
935 {
936 struct snd_soc_codec *codec = w->codec;
937
938 switch (event) {
939 case SND_SOC_DAPM_PRE_PMU:
940 return configure_clock(codec);
941
942 case SND_SOC_DAPM_POST_PMD:
943 configure_clock(codec);
944 break;
945 }
946
947 return 0;
948 }
949
950 static void wm8994_update_class_w(struct snd_soc_codec *codec)
951 {
952 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
953 int enable = 1;
954 int source = 0; /* GCC flow analysis can't track enable */
955 int reg, reg_r;
956
957 /* Only support direct DAC->headphone paths */
958 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
959 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
960 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
961 enable = 0;
962 }
963
964 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
965 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
966 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
967 enable = 0;
968 }
969
970 /* We also need the same setting for L/R and only one path */
971 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
972 switch (reg) {
973 case WM8994_AIF2DACL_TO_DAC1L:
974 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
975 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
976 break;
977 case WM8994_AIF1DAC2L_TO_DAC1L:
978 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
979 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
980 break;
981 case WM8994_AIF1DAC1L_TO_DAC1L:
982 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
983 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
984 break;
985 default:
986 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
987 enable = 0;
988 break;
989 }
990
991 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
992 if (reg_r != reg) {
993 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
994 enable = 0;
995 }
996
997 if (enable) {
998 dev_dbg(codec->dev, "Class W enabled\n");
999 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1000 WM8994_CP_DYN_PWR |
1001 WM8994_CP_DYN_SRC_SEL_MASK,
1002 source | WM8994_CP_DYN_PWR);
1003 wm8994->hubs.class_w = true;
1004
1005 } else {
1006 dev_dbg(codec->dev, "Class W disabled\n");
1007 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1008 WM8994_CP_DYN_PWR, 0);
1009 wm8994->hubs.class_w = false;
1010 }
1011 }
1012
1013 static int late_enable_ev(struct snd_soc_dapm_widget *w,
1014 struct snd_kcontrol *kcontrol, int event)
1015 {
1016 struct snd_soc_codec *codec = w->codec;
1017 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1018
1019 switch (event) {
1020 case SND_SOC_DAPM_PRE_PMU:
1021 if (wm8994->aif1clk_enable) {
1022 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1023 WM8994_AIF1CLK_ENA_MASK,
1024 WM8994_AIF1CLK_ENA);
1025 wm8994->aif1clk_enable = 0;
1026 }
1027 if (wm8994->aif2clk_enable) {
1028 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1029 WM8994_AIF2CLK_ENA_MASK,
1030 WM8994_AIF2CLK_ENA);
1031 wm8994->aif2clk_enable = 0;
1032 }
1033 break;
1034 }
1035
1036 return 0;
1037 }
1038
1039 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1040 struct snd_kcontrol *kcontrol, int event)
1041 {
1042 struct snd_soc_codec *codec = w->codec;
1043 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1044
1045 switch (event) {
1046 case SND_SOC_DAPM_POST_PMD:
1047 if (wm8994->aif1clk_disable) {
1048 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1049 WM8994_AIF1CLK_ENA_MASK, 0);
1050 wm8994->aif1clk_disable = 0;
1051 }
1052 if (wm8994->aif2clk_disable) {
1053 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1054 WM8994_AIF2CLK_ENA_MASK, 0);
1055 wm8994->aif2clk_disable = 0;
1056 }
1057 break;
1058 }
1059
1060 return 0;
1061 }
1062
1063 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1064 struct snd_kcontrol *kcontrol, int event)
1065 {
1066 struct snd_soc_codec *codec = w->codec;
1067 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1068
1069 switch (event) {
1070 case SND_SOC_DAPM_PRE_PMU:
1071 wm8994->aif1clk_enable = 1;
1072 break;
1073 case SND_SOC_DAPM_POST_PMD:
1074 wm8994->aif1clk_disable = 1;
1075 break;
1076 }
1077
1078 return 0;
1079 }
1080
1081 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1082 struct snd_kcontrol *kcontrol, int event)
1083 {
1084 struct snd_soc_codec *codec = w->codec;
1085 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1086
1087 switch (event) {
1088 case SND_SOC_DAPM_PRE_PMU:
1089 wm8994->aif2clk_enable = 1;
1090 break;
1091 case SND_SOC_DAPM_POST_PMD:
1092 wm8994->aif2clk_disable = 1;
1093 break;
1094 }
1095
1096 return 0;
1097 }
1098
1099 static int dac_ev(struct snd_soc_dapm_widget *w,
1100 struct snd_kcontrol *kcontrol, int event)
1101 {
1102 struct snd_soc_codec *codec = w->codec;
1103 unsigned int mask = 1 << w->shift;
1104
1105 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1106 mask, mask);
1107 return 0;
1108 }
1109
1110 static const char *hp_mux_text[] = {
1111 "Mixer",
1112 "DAC",
1113 };
1114
1115 #define WM8994_HP_ENUM(xname, xenum) \
1116 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1117 .info = snd_soc_info_enum_double, \
1118 .get = snd_soc_dapm_get_enum_double, \
1119 .put = wm8994_put_hp_enum, \
1120 .private_value = (unsigned long)&xenum }
1121
1122 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1123 struct snd_ctl_elem_value *ucontrol)
1124 {
1125 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
1126 struct snd_soc_codec *codec = w->codec;
1127 int ret;
1128
1129 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1130
1131 wm8994_update_class_w(codec);
1132
1133 return ret;
1134 }
1135
1136 static const struct soc_enum hpl_enum =
1137 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1138
1139 static const struct snd_kcontrol_new hpl_mux =
1140 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1141
1142 static const struct soc_enum hpr_enum =
1143 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1144
1145 static const struct snd_kcontrol_new hpr_mux =
1146 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1147
1148 static const char *adc_mux_text[] = {
1149 "ADC",
1150 "DMIC",
1151 };
1152
1153 static const struct soc_enum adc_enum =
1154 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1155
1156 static const struct snd_kcontrol_new adcl_mux =
1157 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1158
1159 static const struct snd_kcontrol_new adcr_mux =
1160 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1161
1162 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1163 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1164 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1165 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1166 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1167 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1168 };
1169
1170 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1171 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1172 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1173 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1174 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1175 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1176 };
1177
1178 /* Debugging; dump chip status after DAPM transitions */
1179 static int post_ev(struct snd_soc_dapm_widget *w,
1180 struct snd_kcontrol *kcontrol, int event)
1181 {
1182 struct snd_soc_codec *codec = w->codec;
1183 dev_dbg(codec->dev, "SRC status: %x\n",
1184 snd_soc_read(codec,
1185 WM8994_RATE_STATUS));
1186 return 0;
1187 }
1188
1189 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1190 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1191 1, 1, 0),
1192 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1193 0, 1, 0),
1194 };
1195
1196 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1197 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1198 1, 1, 0),
1199 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1200 0, 1, 0),
1201 };
1202
1203 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1204 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1205 1, 1, 0),
1206 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1207 0, 1, 0),
1208 };
1209
1210 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1211 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1212 1, 1, 0),
1213 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1214 0, 1, 0),
1215 };
1216
1217 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1218 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1219 5, 1, 0),
1220 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1221 4, 1, 0),
1222 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1223 2, 1, 0),
1224 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1225 1, 1, 0),
1226 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1227 0, 1, 0),
1228 };
1229
1230 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1231 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1232 5, 1, 0),
1233 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1234 4, 1, 0),
1235 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1236 2, 1, 0),
1237 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1238 1, 1, 0),
1239 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1240 0, 1, 0),
1241 };
1242
1243 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1244 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1245 .info = snd_soc_info_volsw, \
1246 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1247 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1248
1249 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1250 struct snd_ctl_elem_value *ucontrol)
1251 {
1252 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
1253 struct snd_soc_codec *codec = w->codec;
1254 int ret;
1255
1256 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1257
1258 wm8994_update_class_w(codec);
1259
1260 return ret;
1261 }
1262
1263 static const struct snd_kcontrol_new dac1l_mix[] = {
1264 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1265 5, 1, 0),
1266 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1267 4, 1, 0),
1268 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1269 2, 1, 0),
1270 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1271 1, 1, 0),
1272 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1273 0, 1, 0),
1274 };
1275
1276 static const struct snd_kcontrol_new dac1r_mix[] = {
1277 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1278 5, 1, 0),
1279 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1280 4, 1, 0),
1281 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1282 2, 1, 0),
1283 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1284 1, 1, 0),
1285 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1286 0, 1, 0),
1287 };
1288
1289 static const char *sidetone_text[] = {
1290 "ADC/DMIC1", "DMIC2",
1291 };
1292
1293 static const struct soc_enum sidetone1_enum =
1294 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1295
1296 static const struct snd_kcontrol_new sidetone1_mux =
1297 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1298
1299 static const struct soc_enum sidetone2_enum =
1300 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1301
1302 static const struct snd_kcontrol_new sidetone2_mux =
1303 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1304
1305 static const char *aif1dac_text[] = {
1306 "AIF1DACDAT", "AIF3DACDAT",
1307 };
1308
1309 static const struct soc_enum aif1dac_enum =
1310 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1311
1312 static const struct snd_kcontrol_new aif1dac_mux =
1313 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1314
1315 static const char *aif2dac_text[] = {
1316 "AIF2DACDAT", "AIF3DACDAT",
1317 };
1318
1319 static const struct soc_enum aif2dac_enum =
1320 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1321
1322 static const struct snd_kcontrol_new aif2dac_mux =
1323 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1324
1325 static const char *aif2adc_text[] = {
1326 "AIF2ADCDAT", "AIF3DACDAT",
1327 };
1328
1329 static const struct soc_enum aif2adc_enum =
1330 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1331
1332 static const struct snd_kcontrol_new aif2adc_mux =
1333 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1334
1335 static const char *aif3adc_text[] = {
1336 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1337 };
1338
1339 static const struct soc_enum wm8994_aif3adc_enum =
1340 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1341
1342 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1343 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1344
1345 static const struct soc_enum wm8958_aif3adc_enum =
1346 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1347
1348 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1349 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1350
1351 static const char *mono_pcm_out_text[] = {
1352 "None", "AIF2ADCL", "AIF2ADCR",
1353 };
1354
1355 static const struct soc_enum mono_pcm_out_enum =
1356 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1357
1358 static const struct snd_kcontrol_new mono_pcm_out_mux =
1359 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1360
1361 static const char *aif2dac_src_text[] = {
1362 "AIF2", "AIF3",
1363 };
1364
1365 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1366 static const struct soc_enum aif2dacl_src_enum =
1367 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1368
1369 static const struct snd_kcontrol_new aif2dacl_src_mux =
1370 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1371
1372 static const struct soc_enum aif2dacr_src_enum =
1373 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1374
1375 static const struct snd_kcontrol_new aif2dacr_src_mux =
1376 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1377
1378 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1379 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1380 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1381 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1382 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1383
1384 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1385 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1386 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1387 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1388 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1389 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1390 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1391 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1392
1393 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1394 };
1395
1396 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1397 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1398 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0)
1399 };
1400
1401 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1402 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1403 dac_ev, SND_SOC_DAPM_PRE_PMU),
1404 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1405 dac_ev, SND_SOC_DAPM_PRE_PMU),
1406 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1407 dac_ev, SND_SOC_DAPM_PRE_PMU),
1408 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1409 dac_ev, SND_SOC_DAPM_PRE_PMU),
1410 };
1411
1412 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1413 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1414 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1415 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1416 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1417 };
1418
1419 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1420 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1421 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1422 SND_SOC_DAPM_INPUT("Clock"),
1423
1424 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1425 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1426
1427 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1428 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1429 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1430
1431 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1432 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1433 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1434 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
1435 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1436 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1437 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1438 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1439 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1440 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1441
1442 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1443 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1444 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1445 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
1446 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1447 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
1448 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1449 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1450 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1451 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1452
1453 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1454 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1455 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1456 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1457
1458 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1459 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1460 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1461 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1462
1463 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1464 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1465 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1466 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1467
1468 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1469 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1470
1471 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1472 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1473 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1474 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1475
1476 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1477 WM8994_POWER_MANAGEMENT_4, 13, 0),
1478 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1479 WM8994_POWER_MANAGEMENT_4, 12, 0),
1480 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1481 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1482 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1483 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1484 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1485 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1486
1487 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1488 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1489 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1490 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1491
1492 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1493 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1494 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1495
1496 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1497 SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1498
1499 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1500
1501 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1502 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1503 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1504 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1505
1506 /* Power is done with the muxes since the ADC power also controls the
1507 * downsampling chain, the chip will automatically manage the analogue
1508 * specific portions.
1509 */
1510 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1511 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1512
1513 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1514 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1515
1516 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1517 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1518
1519 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1520 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1521 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1522 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1523
1524 SND_SOC_DAPM_POST("Debug log", post_ev),
1525 };
1526
1527 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1528 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1529 };
1530
1531 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1532 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1533 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1534 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1535 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1536 };
1537
1538 static const struct snd_soc_dapm_route intercon[] = {
1539 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1540 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1541
1542 { "DSP1CLK", NULL, "CLK_SYS" },
1543 { "DSP2CLK", NULL, "CLK_SYS" },
1544 { "DSPINTCLK", NULL, "CLK_SYS" },
1545
1546 { "AIF1ADC1L", NULL, "AIF1CLK" },
1547 { "AIF1ADC1L", NULL, "DSP1CLK" },
1548 { "AIF1ADC1R", NULL, "AIF1CLK" },
1549 { "AIF1ADC1R", NULL, "DSP1CLK" },
1550 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1551
1552 { "AIF1DAC1L", NULL, "AIF1CLK" },
1553 { "AIF1DAC1L", NULL, "DSP1CLK" },
1554 { "AIF1DAC1R", NULL, "AIF1CLK" },
1555 { "AIF1DAC1R", NULL, "DSP1CLK" },
1556 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1557
1558 { "AIF1ADC2L", NULL, "AIF1CLK" },
1559 { "AIF1ADC2L", NULL, "DSP1CLK" },
1560 { "AIF1ADC2R", NULL, "AIF1CLK" },
1561 { "AIF1ADC2R", NULL, "DSP1CLK" },
1562 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1563
1564 { "AIF1DAC2L", NULL, "AIF1CLK" },
1565 { "AIF1DAC2L", NULL, "DSP1CLK" },
1566 { "AIF1DAC2R", NULL, "AIF1CLK" },
1567 { "AIF1DAC2R", NULL, "DSP1CLK" },
1568 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1569
1570 { "AIF2ADCL", NULL, "AIF2CLK" },
1571 { "AIF2ADCL", NULL, "DSP2CLK" },
1572 { "AIF2ADCR", NULL, "AIF2CLK" },
1573 { "AIF2ADCR", NULL, "DSP2CLK" },
1574 { "AIF2ADCR", NULL, "DSPINTCLK" },
1575
1576 { "AIF2DACL", NULL, "AIF2CLK" },
1577 { "AIF2DACL", NULL, "DSP2CLK" },
1578 { "AIF2DACR", NULL, "AIF2CLK" },
1579 { "AIF2DACR", NULL, "DSP2CLK" },
1580 { "AIF2DACR", NULL, "DSPINTCLK" },
1581
1582 { "DMIC1L", NULL, "DMIC1DAT" },
1583 { "DMIC1L", NULL, "CLK_SYS" },
1584 { "DMIC1R", NULL, "DMIC1DAT" },
1585 { "DMIC1R", NULL, "CLK_SYS" },
1586 { "DMIC2L", NULL, "DMIC2DAT" },
1587 { "DMIC2L", NULL, "CLK_SYS" },
1588 { "DMIC2R", NULL, "DMIC2DAT" },
1589 { "DMIC2R", NULL, "CLK_SYS" },
1590
1591 { "ADCL", NULL, "AIF1CLK" },
1592 { "ADCL", NULL, "DSP1CLK" },
1593 { "ADCL", NULL, "DSPINTCLK" },
1594
1595 { "ADCR", NULL, "AIF1CLK" },
1596 { "ADCR", NULL, "DSP1CLK" },
1597 { "ADCR", NULL, "DSPINTCLK" },
1598
1599 { "ADCL Mux", "ADC", "ADCL" },
1600 { "ADCL Mux", "DMIC", "DMIC1L" },
1601 { "ADCR Mux", "ADC", "ADCR" },
1602 { "ADCR Mux", "DMIC", "DMIC1R" },
1603
1604 { "DAC1L", NULL, "AIF1CLK" },
1605 { "DAC1L", NULL, "DSP1CLK" },
1606 { "DAC1L", NULL, "DSPINTCLK" },
1607
1608 { "DAC1R", NULL, "AIF1CLK" },
1609 { "DAC1R", NULL, "DSP1CLK" },
1610 { "DAC1R", NULL, "DSPINTCLK" },
1611
1612 { "DAC2L", NULL, "AIF2CLK" },
1613 { "DAC2L", NULL, "DSP2CLK" },
1614 { "DAC2L", NULL, "DSPINTCLK" },
1615
1616 { "DAC2R", NULL, "AIF2DACR" },
1617 { "DAC2R", NULL, "AIF2CLK" },
1618 { "DAC2R", NULL, "DSP2CLK" },
1619 { "DAC2R", NULL, "DSPINTCLK" },
1620
1621 { "TOCLK", NULL, "CLK_SYS" },
1622
1623 /* AIF1 outputs */
1624 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1625 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1626 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1627
1628 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1629 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1630 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1631
1632 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1633 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1634 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1635
1636 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1637 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1638 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1639
1640 /* Pin level routing for AIF3 */
1641 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1642 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1643 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1644 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1645
1646 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1647 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1648 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1649 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1650 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1651 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1652 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1653
1654 /* DAC1 inputs */
1655 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1656 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1657 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1658 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1659 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1660
1661 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1662 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1663 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1664 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1665 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1666
1667 /* DAC2/AIF2 outputs */
1668 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1669 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1670 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1671 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1672 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1673 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1674
1675 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1676 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1677 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1678 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1679 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1680 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1681
1682 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1683 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1684 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1685 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1686
1687 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1688
1689 /* AIF3 output */
1690 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1691 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1692 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1693 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1694 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1695 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1696 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1697 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1698
1699 /* Sidetone */
1700 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1701 { "Left Sidetone", "DMIC2", "DMIC2L" },
1702 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1703 { "Right Sidetone", "DMIC2", "DMIC2R" },
1704
1705 /* Output stages */
1706 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1707 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1708
1709 { "SPKL", "DAC1 Switch", "DAC1L" },
1710 { "SPKL", "DAC2 Switch", "DAC2L" },
1711
1712 { "SPKR", "DAC1 Switch", "DAC1R" },
1713 { "SPKR", "DAC2 Switch", "DAC2R" },
1714
1715 { "Left Headphone Mux", "DAC", "DAC1L" },
1716 { "Right Headphone Mux", "DAC", "DAC1R" },
1717 };
1718
1719 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1720 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1721 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1722 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1723 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1724 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1725 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1726 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1727 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1728 };
1729
1730 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1731 { "DAC1L", NULL, "DAC1L Mixer" },
1732 { "DAC1R", NULL, "DAC1R Mixer" },
1733 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1734 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1735 };
1736
1737 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1738 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1739 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1740 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1741 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1742 };
1743
1744 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1745 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1746 { "AIF2DACR", NULL, "AIF2DAC Mux" },
1747 };
1748
1749 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1750 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1751 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1752
1753 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1754 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1755 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1756 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1757
1758 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1759 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1760
1761 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1762 };
1763
1764 /* The size in bits of the FLL divide multiplied by 10
1765 * to allow rounding later */
1766 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1767
1768 struct fll_div {
1769 u16 outdiv;
1770 u16 n;
1771 u16 k;
1772 u16 clk_ref_div;
1773 u16 fll_fratio;
1774 };
1775
1776 static int wm8994_get_fll_config(struct fll_div *fll,
1777 int freq_in, int freq_out)
1778 {
1779 u64 Kpart;
1780 unsigned int K, Ndiv, Nmod;
1781
1782 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1783
1784 /* Scale the input frequency down to <= 13.5MHz */
1785 fll->clk_ref_div = 0;
1786 while (freq_in > 13500000) {
1787 fll->clk_ref_div++;
1788 freq_in /= 2;
1789
1790 if (fll->clk_ref_div > 3)
1791 return -EINVAL;
1792 }
1793 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1794
1795 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1796 fll->outdiv = 3;
1797 while (freq_out * (fll->outdiv + 1) < 90000000) {
1798 fll->outdiv++;
1799 if (fll->outdiv > 63)
1800 return -EINVAL;
1801 }
1802 freq_out *= fll->outdiv + 1;
1803 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1804
1805 if (freq_in > 1000000) {
1806 fll->fll_fratio = 0;
1807 } else if (freq_in > 256000) {
1808 fll->fll_fratio = 1;
1809 freq_in *= 2;
1810 } else if (freq_in > 128000) {
1811 fll->fll_fratio = 2;
1812 freq_in *= 4;
1813 } else if (freq_in > 64000) {
1814 fll->fll_fratio = 3;
1815 freq_in *= 8;
1816 } else {
1817 fll->fll_fratio = 4;
1818 freq_in *= 16;
1819 }
1820 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1821
1822 /* Now, calculate N.K */
1823 Ndiv = freq_out / freq_in;
1824
1825 fll->n = Ndiv;
1826 Nmod = freq_out % freq_in;
1827 pr_debug("Nmod=%d\n", Nmod);
1828
1829 /* Calculate fractional part - scale up so we can round. */
1830 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1831
1832 do_div(Kpart, freq_in);
1833
1834 K = Kpart & 0xFFFFFFFF;
1835
1836 if ((K % 10) >= 5)
1837 K += 5;
1838
1839 /* Move down to proper range now rounding is done */
1840 fll->k = K / 10;
1841
1842 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1843
1844 return 0;
1845 }
1846
1847 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1848 unsigned int freq_in, unsigned int freq_out)
1849 {
1850 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1851 int reg_offset, ret;
1852 struct fll_div fll;
1853 u16 reg, aif1, aif2;
1854
1855 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1856 & WM8994_AIF1CLK_ENA;
1857
1858 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1859 & WM8994_AIF2CLK_ENA;
1860
1861 switch (id) {
1862 case WM8994_FLL1:
1863 reg_offset = 0;
1864 id = 0;
1865 break;
1866 case WM8994_FLL2:
1867 reg_offset = 0x20;
1868 id = 1;
1869 break;
1870 default:
1871 return -EINVAL;
1872 }
1873
1874 switch (src) {
1875 case 0:
1876 /* Allow no source specification when stopping */
1877 if (freq_out)
1878 return -EINVAL;
1879 src = wm8994->fll[id].src;
1880 break;
1881 case WM8994_FLL_SRC_MCLK1:
1882 case WM8994_FLL_SRC_MCLK2:
1883 case WM8994_FLL_SRC_LRCLK:
1884 case WM8994_FLL_SRC_BCLK:
1885 break;
1886 default:
1887 return -EINVAL;
1888 }
1889
1890 /* Are we changing anything? */
1891 if (wm8994->fll[id].src == src &&
1892 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1893 return 0;
1894
1895 /* If we're stopping the FLL redo the old config - no
1896 * registers will actually be written but we avoid GCC flow
1897 * analysis bugs spewing warnings.
1898 */
1899 if (freq_out)
1900 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1901 else
1902 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1903 wm8994->fll[id].out);
1904 if (ret < 0)
1905 return ret;
1906
1907 /* Gate the AIF clocks while we reclock */
1908 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1909 WM8994_AIF1CLK_ENA, 0);
1910 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1911 WM8994_AIF2CLK_ENA, 0);
1912
1913 /* We always need to disable the FLL while reconfiguring */
1914 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1915 WM8994_FLL1_ENA, 0);
1916
1917 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1918 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1919 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1920 WM8994_FLL1_OUTDIV_MASK |
1921 WM8994_FLL1_FRATIO_MASK, reg);
1922
1923 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1924
1925 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1926 WM8994_FLL1_N_MASK,
1927 fll.n << WM8994_FLL1_N_SHIFT);
1928
1929 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1930 WM8994_FLL1_REFCLK_DIV_MASK |
1931 WM8994_FLL1_REFCLK_SRC_MASK,
1932 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1933 (src - 1));
1934
1935 /* Enable (with fractional mode if required) */
1936 if (freq_out) {
1937 if (fll.k)
1938 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1939 else
1940 reg = WM8994_FLL1_ENA;
1941 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1942 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1943 reg);
1944 }
1945
1946 wm8994->fll[id].in = freq_in;
1947 wm8994->fll[id].out = freq_out;
1948 wm8994->fll[id].src = src;
1949
1950 /* Enable any gated AIF clocks */
1951 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1952 WM8994_AIF1CLK_ENA, aif1);
1953 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1954 WM8994_AIF2CLK_ENA, aif2);
1955
1956 configure_clock(codec);
1957
1958 return 0;
1959 }
1960
1961
1962 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1963
1964 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1965 unsigned int freq_in, unsigned int freq_out)
1966 {
1967 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1968 }
1969
1970 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1971 int clk_id, unsigned int freq, int dir)
1972 {
1973 struct snd_soc_codec *codec = dai->codec;
1974 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1975 int i;
1976
1977 switch (dai->id) {
1978 case 1:
1979 case 2:
1980 break;
1981
1982 default:
1983 /* AIF3 shares clocking with AIF1/2 */
1984 return -EINVAL;
1985 }
1986
1987 switch (clk_id) {
1988 case WM8994_SYSCLK_MCLK1:
1989 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
1990 wm8994->mclk[0] = freq;
1991 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1992 dai->id, freq);
1993 break;
1994
1995 case WM8994_SYSCLK_MCLK2:
1996 /* TODO: Set GPIO AF */
1997 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
1998 wm8994->mclk[1] = freq;
1999 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2000 dai->id, freq);
2001 break;
2002
2003 case WM8994_SYSCLK_FLL1:
2004 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2005 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2006 break;
2007
2008 case WM8994_SYSCLK_FLL2:
2009 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2010 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2011 break;
2012
2013 case WM8994_SYSCLK_OPCLK:
2014 /* Special case - a division (times 10) is given and
2015 * no effect on main clocking.
2016 */
2017 if (freq) {
2018 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2019 if (opclk_divs[i] == freq)
2020 break;
2021 if (i == ARRAY_SIZE(opclk_divs))
2022 return -EINVAL;
2023 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2024 WM8994_OPCLK_DIV_MASK, i);
2025 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2026 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2027 } else {
2028 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2029 WM8994_OPCLK_ENA, 0);
2030 }
2031
2032 default:
2033 return -EINVAL;
2034 }
2035
2036 configure_clock(codec);
2037
2038 return 0;
2039 }
2040
2041 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2042 enum snd_soc_bias_level level)
2043 {
2044 struct wm8994 *control = codec->control_data;
2045 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2046
2047 switch (level) {
2048 case SND_SOC_BIAS_ON:
2049 break;
2050
2051 case SND_SOC_BIAS_PREPARE:
2052 /* VMID=2x40k */
2053 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
2054 WM8994_VMID_SEL_MASK, 0x2);
2055 break;
2056
2057 case SND_SOC_BIAS_STANDBY:
2058 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2059 pm_runtime_get_sync(codec->dev);
2060
2061 switch (control->type) {
2062 case WM8994:
2063 if (wm8994->revision < 4) {
2064 /* Tweak DC servo and DSP
2065 * configuration for improved
2066 * performance. */
2067 snd_soc_write(codec, 0x102, 0x3);
2068 snd_soc_write(codec, 0x56, 0x3);
2069 snd_soc_write(codec, 0x817, 0);
2070 snd_soc_write(codec, 0x102, 0);
2071 }
2072 break;
2073
2074 case WM8958:
2075 if (wm8994->revision == 0) {
2076 /* Optimise performance for rev A */
2077 snd_soc_write(codec, 0x102, 0x3);
2078 snd_soc_write(codec, 0xcb, 0x81);
2079 snd_soc_write(codec, 0x817, 0);
2080 snd_soc_write(codec, 0x102, 0);
2081
2082 snd_soc_update_bits(codec,
2083 WM8958_CHARGE_PUMP_2,
2084 WM8958_CP_DISCH,
2085 WM8958_CP_DISCH);
2086 }
2087 break;
2088 }
2089
2090 /* Discharge LINEOUT1 & 2 */
2091 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2092 WM8994_LINEOUT1_DISCH |
2093 WM8994_LINEOUT2_DISCH,
2094 WM8994_LINEOUT1_DISCH |
2095 WM8994_LINEOUT2_DISCH);
2096
2097 /* Startup bias, VMID ramp & buffer */
2098 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2099 WM8994_STARTUP_BIAS_ENA |
2100 WM8994_VMID_BUF_ENA |
2101 WM8994_VMID_RAMP_MASK,
2102 WM8994_STARTUP_BIAS_ENA |
2103 WM8994_VMID_BUF_ENA |
2104 (0x11 << WM8994_VMID_RAMP_SHIFT));
2105
2106 /* Main bias enable, VMID=2x40k */
2107 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
2108 WM8994_BIAS_ENA |
2109 WM8994_VMID_SEL_MASK,
2110 WM8994_BIAS_ENA | 0x2);
2111
2112 msleep(20);
2113 }
2114
2115 /* VMID=2x500k */
2116 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
2117 WM8994_VMID_SEL_MASK, 0x4);
2118
2119 break;
2120
2121 case SND_SOC_BIAS_OFF:
2122 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
2123 /* Switch over to startup biases */
2124 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2125 WM8994_BIAS_SRC |
2126 WM8994_STARTUP_BIAS_ENA |
2127 WM8994_VMID_BUF_ENA |
2128 WM8994_VMID_RAMP_MASK,
2129 WM8994_BIAS_SRC |
2130 WM8994_STARTUP_BIAS_ENA |
2131 WM8994_VMID_BUF_ENA |
2132 (1 << WM8994_VMID_RAMP_SHIFT));
2133
2134 /* Disable main biases */
2135 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
2136 WM8994_BIAS_ENA |
2137 WM8994_VMID_SEL_MASK, 0);
2138
2139 /* Discharge line */
2140 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2141 WM8994_LINEOUT1_DISCH |
2142 WM8994_LINEOUT2_DISCH,
2143 WM8994_LINEOUT1_DISCH |
2144 WM8994_LINEOUT2_DISCH);
2145
2146 msleep(5);
2147
2148 /* Switch off startup biases */
2149 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2150 WM8994_BIAS_SRC |
2151 WM8994_STARTUP_BIAS_ENA |
2152 WM8994_VMID_BUF_ENA |
2153 WM8994_VMID_RAMP_MASK, 0);
2154
2155 pm_runtime_put(codec->dev);
2156 }
2157 break;
2158 }
2159 codec->dapm.bias_level = level;
2160 return 0;
2161 }
2162
2163 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2164 {
2165 struct snd_soc_codec *codec = dai->codec;
2166 struct wm8994 *control = codec->control_data;
2167 int ms_reg;
2168 int aif1_reg;
2169 int ms = 0;
2170 int aif1 = 0;
2171
2172 switch (dai->id) {
2173 case 1:
2174 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2175 aif1_reg = WM8994_AIF1_CONTROL_1;
2176 break;
2177 case 2:
2178 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2179 aif1_reg = WM8994_AIF2_CONTROL_1;
2180 break;
2181 default:
2182 return -EINVAL;
2183 }
2184
2185 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2186 case SND_SOC_DAIFMT_CBS_CFS:
2187 break;
2188 case SND_SOC_DAIFMT_CBM_CFM:
2189 ms = WM8994_AIF1_MSTR;
2190 break;
2191 default:
2192 return -EINVAL;
2193 }
2194
2195 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2196 case SND_SOC_DAIFMT_DSP_B:
2197 aif1 |= WM8994_AIF1_LRCLK_INV;
2198 case SND_SOC_DAIFMT_DSP_A:
2199 aif1 |= 0x18;
2200 break;
2201 case SND_SOC_DAIFMT_I2S:
2202 aif1 |= 0x10;
2203 break;
2204 case SND_SOC_DAIFMT_RIGHT_J:
2205 break;
2206 case SND_SOC_DAIFMT_LEFT_J:
2207 aif1 |= 0x8;
2208 break;
2209 default:
2210 return -EINVAL;
2211 }
2212
2213 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2214 case SND_SOC_DAIFMT_DSP_A:
2215 case SND_SOC_DAIFMT_DSP_B:
2216 /* frame inversion not valid for DSP modes */
2217 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2218 case SND_SOC_DAIFMT_NB_NF:
2219 break;
2220 case SND_SOC_DAIFMT_IB_NF:
2221 aif1 |= WM8994_AIF1_BCLK_INV;
2222 break;
2223 default:
2224 return -EINVAL;
2225 }
2226 break;
2227
2228 case SND_SOC_DAIFMT_I2S:
2229 case SND_SOC_DAIFMT_RIGHT_J:
2230 case SND_SOC_DAIFMT_LEFT_J:
2231 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2232 case SND_SOC_DAIFMT_NB_NF:
2233 break;
2234 case SND_SOC_DAIFMT_IB_IF:
2235 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2236 break;
2237 case SND_SOC_DAIFMT_IB_NF:
2238 aif1 |= WM8994_AIF1_BCLK_INV;
2239 break;
2240 case SND_SOC_DAIFMT_NB_IF:
2241 aif1 |= WM8994_AIF1_LRCLK_INV;
2242 break;
2243 default:
2244 return -EINVAL;
2245 }
2246 break;
2247 default:
2248 return -EINVAL;
2249 }
2250
2251 /* The AIF2 format configuration needs to be mirrored to AIF3
2252 * on WM8958 if it's in use so just do it all the time. */
2253 if (control->type == WM8958 && dai->id == 2)
2254 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2255 WM8994_AIF1_LRCLK_INV |
2256 WM8958_AIF3_FMT_MASK, aif1);
2257
2258 snd_soc_update_bits(codec, aif1_reg,
2259 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2260 WM8994_AIF1_FMT_MASK,
2261 aif1);
2262 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2263 ms);
2264
2265 return 0;
2266 }
2267
2268 static struct {
2269 int val, rate;
2270 } srs[] = {
2271 { 0, 8000 },
2272 { 1, 11025 },
2273 { 2, 12000 },
2274 { 3, 16000 },
2275 { 4, 22050 },
2276 { 5, 24000 },
2277 { 6, 32000 },
2278 { 7, 44100 },
2279 { 8, 48000 },
2280 { 9, 88200 },
2281 { 10, 96000 },
2282 };
2283
2284 static int fs_ratios[] = {
2285 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2286 };
2287
2288 static int bclk_divs[] = {
2289 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2290 640, 880, 960, 1280, 1760, 1920
2291 };
2292
2293 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2294 struct snd_pcm_hw_params *params,
2295 struct snd_soc_dai *dai)
2296 {
2297 struct snd_soc_codec *codec = dai->codec;
2298 struct wm8994 *control = codec->control_data;
2299 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2300 int aif1_reg;
2301 int aif2_reg;
2302 int bclk_reg;
2303 int lrclk_reg;
2304 int rate_reg;
2305 int aif1 = 0;
2306 int aif2 = 0;
2307 int bclk = 0;
2308 int lrclk = 0;
2309 int rate_val = 0;
2310 int id = dai->id - 1;
2311
2312 int i, cur_val, best_val, bclk_rate, best;
2313
2314 switch (dai->id) {
2315 case 1:
2316 aif1_reg = WM8994_AIF1_CONTROL_1;
2317 aif2_reg = WM8994_AIF1_CONTROL_2;
2318 bclk_reg = WM8994_AIF1_BCLK;
2319 rate_reg = WM8994_AIF1_RATE;
2320 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2321 wm8994->lrclk_shared[0]) {
2322 lrclk_reg = WM8994_AIF1DAC_LRCLK;
2323 } else {
2324 lrclk_reg = WM8994_AIF1ADC_LRCLK;
2325 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2326 }
2327 break;
2328 case 2:
2329 aif1_reg = WM8994_AIF2_CONTROL_1;
2330 aif2_reg = WM8994_AIF2_CONTROL_2;
2331 bclk_reg = WM8994_AIF2_BCLK;
2332 rate_reg = WM8994_AIF2_RATE;
2333 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2334 wm8994->lrclk_shared[1]) {
2335 lrclk_reg = WM8994_AIF2DAC_LRCLK;
2336 } else {
2337 lrclk_reg = WM8994_AIF2ADC_LRCLK;
2338 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2339 }
2340 break;
2341 case 3:
2342 switch (control->type) {
2343 case WM8958:
2344 aif1_reg = WM8958_AIF3_CONTROL_1;
2345 break;
2346 default:
2347 return 0;
2348 }
2349 default:
2350 return -EINVAL;
2351 }
2352
2353 bclk_rate = params_rate(params) * 2;
2354 switch (params_format(params)) {
2355 case SNDRV_PCM_FORMAT_S16_LE:
2356 bclk_rate *= 16;
2357 break;
2358 case SNDRV_PCM_FORMAT_S20_3LE:
2359 bclk_rate *= 20;
2360 aif1 |= 0x20;
2361 break;
2362 case SNDRV_PCM_FORMAT_S24_LE:
2363 bclk_rate *= 24;
2364 aif1 |= 0x40;
2365 break;
2366 case SNDRV_PCM_FORMAT_S32_LE:
2367 bclk_rate *= 32;
2368 aif1 |= 0x60;
2369 break;
2370 default:
2371 return -EINVAL;
2372 }
2373
2374 /* Try to find an appropriate sample rate; look for an exact match. */
2375 for (i = 0; i < ARRAY_SIZE(srs); i++)
2376 if (srs[i].rate == params_rate(params))
2377 break;
2378 if (i == ARRAY_SIZE(srs))
2379 return -EINVAL;
2380 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2381
2382 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2383 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2384 dai->id, wm8994->aifclk[id], bclk_rate);
2385
2386 if (params_channels(params) == 1 &&
2387 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2388 aif2 |= WM8994_AIF1_MONO;
2389
2390 if (wm8994->aifclk[id] == 0) {
2391 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2392 return -EINVAL;
2393 }
2394
2395 /* AIFCLK/fs ratio; look for a close match in either direction */
2396 best = 0;
2397 best_val = abs((fs_ratios[0] * params_rate(params))
2398 - wm8994->aifclk[id]);
2399 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2400 cur_val = abs((fs_ratios[i] * params_rate(params))
2401 - wm8994->aifclk[id]);
2402 if (cur_val >= best_val)
2403 continue;
2404 best = i;
2405 best_val = cur_val;
2406 }
2407 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2408 dai->id, fs_ratios[best]);
2409 rate_val |= best;
2410
2411 /* We may not get quite the right frequency if using
2412 * approximate clocks so look for the closest match that is
2413 * higher than the target (we need to ensure that there enough
2414 * BCLKs to clock out the samples).
2415 */
2416 best = 0;
2417 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2418 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2419 if (cur_val < 0) /* BCLK table is sorted */
2420 break;
2421 best = i;
2422 }
2423 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2424 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2425 bclk_divs[best], bclk_rate);
2426 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2427
2428 lrclk = bclk_rate / params_rate(params);
2429 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2430 lrclk, bclk_rate / lrclk);
2431
2432 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2433 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2434 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2435 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2436 lrclk);
2437 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2438 WM8994_AIF1CLK_RATE_MASK, rate_val);
2439
2440 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2441 switch (dai->id) {
2442 case 1:
2443 wm8994->dac_rates[0] = params_rate(params);
2444 wm8994_set_retune_mobile(codec, 0);
2445 wm8994_set_retune_mobile(codec, 1);
2446 break;
2447 case 2:
2448 wm8994->dac_rates[1] = params_rate(params);
2449 wm8994_set_retune_mobile(codec, 2);
2450 break;
2451 }
2452 }
2453
2454 return 0;
2455 }
2456
2457 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2458 struct snd_pcm_hw_params *params,
2459 struct snd_soc_dai *dai)
2460 {
2461 struct snd_soc_codec *codec = dai->codec;
2462 struct wm8994 *control = codec->control_data;
2463 int aif1_reg;
2464 int aif1 = 0;
2465
2466 switch (dai->id) {
2467 case 3:
2468 switch (control->type) {
2469 case WM8958:
2470 aif1_reg = WM8958_AIF3_CONTROL_1;
2471 break;
2472 default:
2473 return 0;
2474 }
2475 default:
2476 return 0;
2477 }
2478
2479 switch (params_format(params)) {
2480 case SNDRV_PCM_FORMAT_S16_LE:
2481 break;
2482 case SNDRV_PCM_FORMAT_S20_3LE:
2483 aif1 |= 0x20;
2484 break;
2485 case SNDRV_PCM_FORMAT_S24_LE:
2486 aif1 |= 0x40;
2487 break;
2488 case SNDRV_PCM_FORMAT_S32_LE:
2489 aif1 |= 0x60;
2490 break;
2491 default:
2492 return -EINVAL;
2493 }
2494
2495 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2496 }
2497
2498 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2499 {
2500 struct snd_soc_codec *codec = codec_dai->codec;
2501 int mute_reg;
2502 int reg;
2503
2504 switch (codec_dai->id) {
2505 case 1:
2506 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2507 break;
2508 case 2:
2509 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2510 break;
2511 default:
2512 return -EINVAL;
2513 }
2514
2515 if (mute)
2516 reg = WM8994_AIF1DAC1_MUTE;
2517 else
2518 reg = 0;
2519
2520 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2521
2522 return 0;
2523 }
2524
2525 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2526 {
2527 struct snd_soc_codec *codec = codec_dai->codec;
2528 int reg, val, mask;
2529
2530 switch (codec_dai->id) {
2531 case 1:
2532 reg = WM8994_AIF1_MASTER_SLAVE;
2533 mask = WM8994_AIF1_TRI;
2534 break;
2535 case 2:
2536 reg = WM8994_AIF2_MASTER_SLAVE;
2537 mask = WM8994_AIF2_TRI;
2538 break;
2539 case 3:
2540 reg = WM8994_POWER_MANAGEMENT_6;
2541 mask = WM8994_AIF3_TRI;
2542 break;
2543 default:
2544 return -EINVAL;
2545 }
2546
2547 if (tristate)
2548 val = mask;
2549 else
2550 val = 0;
2551
2552 return snd_soc_update_bits(codec, reg, mask, val);
2553 }
2554
2555 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2556
2557 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2558 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2559
2560 static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2561 .set_sysclk = wm8994_set_dai_sysclk,
2562 .set_fmt = wm8994_set_dai_fmt,
2563 .hw_params = wm8994_hw_params,
2564 .digital_mute = wm8994_aif_mute,
2565 .set_pll = wm8994_set_fll,
2566 .set_tristate = wm8994_set_tristate,
2567 };
2568
2569 static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2570 .set_sysclk = wm8994_set_dai_sysclk,
2571 .set_fmt = wm8994_set_dai_fmt,
2572 .hw_params = wm8994_hw_params,
2573 .digital_mute = wm8994_aif_mute,
2574 .set_pll = wm8994_set_fll,
2575 .set_tristate = wm8994_set_tristate,
2576 };
2577
2578 static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2579 .hw_params = wm8994_aif3_hw_params,
2580 .set_tristate = wm8994_set_tristate,
2581 };
2582
2583 static struct snd_soc_dai_driver wm8994_dai[] = {
2584 {
2585 .name = "wm8994-aif1",
2586 .id = 1,
2587 .playback = {
2588 .stream_name = "AIF1 Playback",
2589 .channels_min = 1,
2590 .channels_max = 2,
2591 .rates = WM8994_RATES,
2592 .formats = WM8994_FORMATS,
2593 },
2594 .capture = {
2595 .stream_name = "AIF1 Capture",
2596 .channels_min = 1,
2597 .channels_max = 2,
2598 .rates = WM8994_RATES,
2599 .formats = WM8994_FORMATS,
2600 },
2601 .ops = &wm8994_aif1_dai_ops,
2602 },
2603 {
2604 .name = "wm8994-aif2",
2605 .id = 2,
2606 .playback = {
2607 .stream_name = "AIF2 Playback",
2608 .channels_min = 1,
2609 .channels_max = 2,
2610 .rates = WM8994_RATES,
2611 .formats = WM8994_FORMATS,
2612 },
2613 .capture = {
2614 .stream_name = "AIF2 Capture",
2615 .channels_min = 1,
2616 .channels_max = 2,
2617 .rates = WM8994_RATES,
2618 .formats = WM8994_FORMATS,
2619 },
2620 .ops = &wm8994_aif2_dai_ops,
2621 },
2622 {
2623 .name = "wm8994-aif3",
2624 .id = 3,
2625 .playback = {
2626 .stream_name = "AIF3 Playback",
2627 .channels_min = 1,
2628 .channels_max = 2,
2629 .rates = WM8994_RATES,
2630 .formats = WM8994_FORMATS,
2631 },
2632 .capture = {
2633 .stream_name = "AIF3 Capture",
2634 .channels_min = 1,
2635 .channels_max = 2,
2636 .rates = WM8994_RATES,
2637 .formats = WM8994_FORMATS,
2638 },
2639 .ops = &wm8994_aif3_dai_ops,
2640 }
2641 };
2642
2643 #ifdef CONFIG_PM
2644 static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
2645 {
2646 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2647 int i, ret;
2648
2649 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2650 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2651 sizeof(struct fll_config));
2652 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2653 if (ret < 0)
2654 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2655 i + 1, ret);
2656 }
2657
2658 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2659
2660 return 0;
2661 }
2662
2663 static int wm8994_resume(struct snd_soc_codec *codec)
2664 {
2665 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2666 int i, ret;
2667 unsigned int val, mask;
2668
2669 if (wm8994->revision < 4) {
2670 /* force a HW read */
2671 val = wm8994_reg_read(codec->control_data,
2672 WM8994_POWER_MANAGEMENT_5);
2673
2674 /* modify the cache only */
2675 codec->cache_only = 1;
2676 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2677 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2678 val &= mask;
2679 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2680 mask, val);
2681 codec->cache_only = 0;
2682 }
2683
2684 /* Restore the registers */
2685 ret = snd_soc_cache_sync(codec);
2686 if (ret != 0)
2687 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
2688
2689 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2690
2691 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2692 if (!wm8994->fll_suspend[i].out)
2693 continue;
2694
2695 ret = _wm8994_set_fll(codec, i + 1,
2696 wm8994->fll_suspend[i].src,
2697 wm8994->fll_suspend[i].in,
2698 wm8994->fll_suspend[i].out);
2699 if (ret < 0)
2700 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2701 i + 1, ret);
2702 }
2703
2704 return 0;
2705 }
2706 #else
2707 #define wm8994_suspend NULL
2708 #define wm8994_resume NULL
2709 #endif
2710
2711 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2712 {
2713 struct snd_soc_codec *codec = wm8994->codec;
2714 struct wm8994_pdata *pdata = wm8994->pdata;
2715 struct snd_kcontrol_new controls[] = {
2716 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2717 wm8994->retune_mobile_enum,
2718 wm8994_get_retune_mobile_enum,
2719 wm8994_put_retune_mobile_enum),
2720 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2721 wm8994->retune_mobile_enum,
2722 wm8994_get_retune_mobile_enum,
2723 wm8994_put_retune_mobile_enum),
2724 SOC_ENUM_EXT("AIF2 EQ Mode",
2725 wm8994->retune_mobile_enum,
2726 wm8994_get_retune_mobile_enum,
2727 wm8994_put_retune_mobile_enum),
2728 };
2729 int ret, i, j;
2730 const char **t;
2731
2732 /* We need an array of texts for the enum API but the number
2733 * of texts is likely to be less than the number of
2734 * configurations due to the sample rate dependency of the
2735 * configurations. */
2736 wm8994->num_retune_mobile_texts = 0;
2737 wm8994->retune_mobile_texts = NULL;
2738 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2739 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2740 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2741 wm8994->retune_mobile_texts[j]) == 0)
2742 break;
2743 }
2744
2745 if (j != wm8994->num_retune_mobile_texts)
2746 continue;
2747
2748 /* Expand the array... */
2749 t = krealloc(wm8994->retune_mobile_texts,
2750 sizeof(char *) *
2751 (wm8994->num_retune_mobile_texts + 1),
2752 GFP_KERNEL);
2753 if (t == NULL)
2754 continue;
2755
2756 /* ...store the new entry... */
2757 t[wm8994->num_retune_mobile_texts] =
2758 pdata->retune_mobile_cfgs[i].name;
2759
2760 /* ...and remember the new version. */
2761 wm8994->num_retune_mobile_texts++;
2762 wm8994->retune_mobile_texts = t;
2763 }
2764
2765 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2766 wm8994->num_retune_mobile_texts);
2767
2768 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2769 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2770
2771 ret = snd_soc_add_controls(wm8994->codec, controls,
2772 ARRAY_SIZE(controls));
2773 if (ret != 0)
2774 dev_err(wm8994->codec->dev,
2775 "Failed to add ReTune Mobile controls: %d\n", ret);
2776 }
2777
2778 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2779 {
2780 struct snd_soc_codec *codec = wm8994->codec;
2781 struct wm8994_pdata *pdata = wm8994->pdata;
2782 int ret, i;
2783
2784 if (!pdata)
2785 return;
2786
2787 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2788 pdata->lineout2_diff,
2789 pdata->lineout1fb,
2790 pdata->lineout2fb,
2791 pdata->jd_scthr,
2792 pdata->jd_thr,
2793 pdata->micbias1_lvl,
2794 pdata->micbias2_lvl);
2795
2796 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2797
2798 if (pdata->num_drc_cfgs) {
2799 struct snd_kcontrol_new controls[] = {
2800 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2801 wm8994_get_drc_enum, wm8994_put_drc_enum),
2802 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2803 wm8994_get_drc_enum, wm8994_put_drc_enum),
2804 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2805 wm8994_get_drc_enum, wm8994_put_drc_enum),
2806 };
2807
2808 /* We need an array of texts for the enum API */
2809 wm8994->drc_texts = kmalloc(sizeof(char *)
2810 * pdata->num_drc_cfgs, GFP_KERNEL);
2811 if (!wm8994->drc_texts) {
2812 dev_err(wm8994->codec->dev,
2813 "Failed to allocate %d DRC config texts\n",
2814 pdata->num_drc_cfgs);
2815 return;
2816 }
2817
2818 for (i = 0; i < pdata->num_drc_cfgs; i++)
2819 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2820
2821 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2822 wm8994->drc_enum.texts = wm8994->drc_texts;
2823
2824 ret = snd_soc_add_controls(wm8994->codec, controls,
2825 ARRAY_SIZE(controls));
2826 if (ret != 0)
2827 dev_err(wm8994->codec->dev,
2828 "Failed to add DRC mode controls: %d\n", ret);
2829
2830 for (i = 0; i < WM8994_NUM_DRC; i++)
2831 wm8994_set_drc(codec, i);
2832 }
2833
2834 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2835 pdata->num_retune_mobile_cfgs);
2836
2837 if (pdata->num_mbc_cfgs) {
2838 struct snd_kcontrol_new control[] = {
2839 SOC_ENUM_EXT("MBC Mode", wm8994->mbc_enum,
2840 wm8958_get_mbc_enum, wm8958_put_mbc_enum),
2841 };
2842
2843 /* We need an array of texts for the enum API */
2844 wm8994->mbc_texts = kmalloc(sizeof(char *)
2845 * pdata->num_mbc_cfgs, GFP_KERNEL);
2846 if (!wm8994->mbc_texts) {
2847 dev_err(wm8994->codec->dev,
2848 "Failed to allocate %d MBC config texts\n",
2849 pdata->num_mbc_cfgs);
2850 return;
2851 }
2852
2853 for (i = 0; i < pdata->num_mbc_cfgs; i++)
2854 wm8994->mbc_texts[i] = pdata->mbc_cfgs[i].name;
2855
2856 wm8994->mbc_enum.max = pdata->num_mbc_cfgs;
2857 wm8994->mbc_enum.texts = wm8994->mbc_texts;
2858
2859 ret = snd_soc_add_controls(wm8994->codec, control, 1);
2860 if (ret != 0)
2861 dev_err(wm8994->codec->dev,
2862 "Failed to add MBC mode controls: %d\n", ret);
2863 }
2864
2865 if (pdata->num_retune_mobile_cfgs)
2866 wm8994_handle_retune_mobile_pdata(wm8994);
2867 else
2868 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
2869 ARRAY_SIZE(wm8994_eq_controls));
2870 }
2871
2872 /**
2873 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2874 *
2875 * @codec: WM8994 codec
2876 * @jack: jack to report detection events on
2877 * @micbias: microphone bias to detect on
2878 * @det: value to report for presence detection
2879 * @shrt: value to report for short detection
2880 *
2881 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
2882 * being used to bring out signals to the processor then only platform
2883 * data configuration is needed for WM8994 and processor GPIOs should
2884 * be configured using snd_soc_jack_add_gpios() instead.
2885 *
2886 * Configuration of detection levels is available via the micbias1_lvl
2887 * and micbias2_lvl platform data members.
2888 */
2889 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2890 int micbias, int det, int shrt)
2891 {
2892 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2893 struct wm8994_micdet *micdet;
2894 struct wm8994 *control = codec->control_data;
2895 int reg;
2896
2897 if (control->type != WM8994)
2898 return -EINVAL;
2899
2900 switch (micbias) {
2901 case 1:
2902 micdet = &wm8994->micdet[0];
2903 break;
2904 case 2:
2905 micdet = &wm8994->micdet[1];
2906 break;
2907 default:
2908 return -EINVAL;
2909 }
2910
2911 dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2912 micbias, det, shrt);
2913
2914 /* Store the configuration */
2915 micdet->jack = jack;
2916 micdet->det = det;
2917 micdet->shrt = shrt;
2918
2919 /* If either of the jacks is set up then enable detection */
2920 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2921 reg = WM8994_MICD_ENA;
2922 else
2923 reg = 0;
2924
2925 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2926
2927 return 0;
2928 }
2929 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
2930
2931 static irqreturn_t wm8994_mic_irq(int irq, void *data)
2932 {
2933 struct wm8994_priv *priv = data;
2934 struct snd_soc_codec *codec = priv->codec;
2935 int reg;
2936 int report;
2937
2938 #ifndef CONFIG_SND_SOC_WM8994_MODULE
2939 trace_snd_soc_jack_irq(dev_name(codec->dev));
2940 #endif
2941
2942 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2943 if (reg < 0) {
2944 dev_err(codec->dev, "Failed to read microphone status: %d\n",
2945 reg);
2946 return IRQ_HANDLED;
2947 }
2948
2949 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
2950
2951 report = 0;
2952 if (reg & WM8994_MIC1_DET_STS)
2953 report |= priv->micdet[0].det;
2954 if (reg & WM8994_MIC1_SHRT_STS)
2955 report |= priv->micdet[0].shrt;
2956 snd_soc_jack_report(priv->micdet[0].jack, report,
2957 priv->micdet[0].det | priv->micdet[0].shrt);
2958
2959 report = 0;
2960 if (reg & WM8994_MIC2_DET_STS)
2961 report |= priv->micdet[1].det;
2962 if (reg & WM8994_MIC2_SHRT_STS)
2963 report |= priv->micdet[1].shrt;
2964 snd_soc_jack_report(priv->micdet[1].jack, report,
2965 priv->micdet[1].det | priv->micdet[1].shrt);
2966
2967 return IRQ_HANDLED;
2968 }
2969
2970 /* Default microphone detection handler for WM8958 - the user can
2971 * override this if they wish.
2972 */
2973 static void wm8958_default_micdet(u16 status, void *data)
2974 {
2975 struct snd_soc_codec *codec = data;
2976 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2977 int report = 0;
2978
2979 /* If nothing present then clear our statuses */
2980 if (!(status & WM8958_MICD_STS)) {
2981 wm8994->jack_is_video = false;
2982 wm8994->jack_is_mic = false;
2983 goto done;
2984 }
2985
2986 /* Assume anything over 475 ohms is a microphone and remember
2987 * that we've seen one (since buttons override it) */
2988 if (status & 0x600)
2989 wm8994->jack_is_mic = true;
2990 if (wm8994->jack_is_mic)
2991 report |= SND_JACK_MICROPHONE;
2992
2993 /* Video has an impedence of approximately 75 ohms; assume
2994 * this isn't used as a button and remember it since buttons
2995 * override it. */
2996 if (status & 0x40)
2997 wm8994->jack_is_video = true;
2998 if (wm8994->jack_is_video)
2999 report |= SND_JACK_VIDEOOUT;
3000
3001 /* Everything else is buttons; just assign slots */
3002 if (status & 0x4)
3003 report |= SND_JACK_BTN_0;
3004 if (status & 0x8)
3005 report |= SND_JACK_BTN_1;
3006 if (status & 0x10)
3007 report |= SND_JACK_BTN_2;
3008 if (status & 0x20)
3009 report |= SND_JACK_BTN_3;
3010 if (status & 0x80)
3011 report |= SND_JACK_BTN_4;
3012 if (status & 0x100)
3013 report |= SND_JACK_BTN_5;
3014
3015 done:
3016 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3017 SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2 |
3018 SND_JACK_BTN_3 | SND_JACK_BTN_4 | SND_JACK_BTN_5 |
3019 SND_JACK_MICROPHONE | SND_JACK_VIDEOOUT);
3020 }
3021
3022 /**
3023 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3024 *
3025 * @codec: WM8958 codec
3026 * @jack: jack to report detection events on
3027 *
3028 * Enable microphone detection functionality for the WM8958. By
3029 * default simple detection which supports the detection of up to 6
3030 * buttons plus video and microphone functionality is supported.
3031 *
3032 * The WM8958 has an advanced jack detection facility which is able to
3033 * support complex accessory detection, especially when used in
3034 * conjunction with external circuitry. In order to provide maximum
3035 * flexiblity a callback is provided which allows a completely custom
3036 * detection algorithm.
3037 */
3038 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3039 wm8958_micdet_cb cb, void *cb_data)
3040 {
3041 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3042 struct wm8994 *control = codec->control_data;
3043
3044 if (control->type != WM8958)
3045 return -EINVAL;
3046
3047 if (jack) {
3048 if (!cb) {
3049 dev_dbg(codec->dev, "Using default micdet callback\n");
3050 cb = wm8958_default_micdet;
3051 cb_data = codec;
3052 }
3053
3054 wm8994->micdet[0].jack = jack;
3055 wm8994->jack_cb = cb;
3056 wm8994->jack_cb_data = cb_data;
3057
3058 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3059 WM8958_MICD_ENA, WM8958_MICD_ENA);
3060 } else {
3061 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3062 WM8958_MICD_ENA, 0);
3063 }
3064
3065 return 0;
3066 }
3067 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3068
3069 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3070 {
3071 struct wm8994_priv *wm8994 = data;
3072 struct snd_soc_codec *codec = wm8994->codec;
3073 int reg;
3074
3075 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3076 if (reg < 0) {
3077 dev_err(codec->dev, "Failed to read mic detect status: %d\n",
3078 reg);
3079 return IRQ_NONE;
3080 }
3081
3082 if (!(reg & WM8958_MICD_VALID)) {
3083 dev_dbg(codec->dev, "Mic detect data not valid\n");
3084 goto out;
3085 }
3086
3087 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3088 trace_snd_soc_jack_irq(dev_name(codec->dev));
3089 #endif
3090
3091 if (wm8994->jack_cb)
3092 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3093 else
3094 dev_warn(codec->dev, "Accessory detection with no callback\n");
3095
3096 out:
3097 return IRQ_HANDLED;
3098 }
3099
3100 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3101 {
3102 struct wm8994 *control;
3103 struct wm8994_priv *wm8994;
3104 struct snd_soc_dapm_context *dapm = &codec->dapm;
3105 int ret, i;
3106
3107 codec->control_data = dev_get_drvdata(codec->dev->parent);
3108 control = codec->control_data;
3109
3110 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
3111 if (wm8994 == NULL)
3112 return -ENOMEM;
3113 snd_soc_codec_set_drvdata(codec, wm8994);
3114
3115 wm8994->pdata = dev_get_platdata(codec->dev->parent);
3116 wm8994->codec = codec;
3117
3118 pm_runtime_enable(codec->dev);
3119 pm_runtime_resume(codec->dev);
3120
3121 /* Read our current status back from the chip - we don't want to
3122 * reset as this may interfere with the GPIO or LDO operation. */
3123 for (i = 0; i < WM8994_CACHE_SIZE; i++) {
3124 if (!wm8994_readable(i) || wm8994_volatile(i))
3125 continue;
3126
3127 ret = wm8994_reg_read(codec->control_data, i);
3128 if (ret <= 0)
3129 continue;
3130
3131 ret = snd_soc_cache_write(codec, i, ret);
3132 if (ret != 0) {
3133 dev_err(codec->dev,
3134 "Failed to initialise cache for 0x%x: %d\n",
3135 i, ret);
3136 goto err;
3137 }
3138 }
3139
3140 /* Set revision-specific configuration */
3141 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3142 switch (control->type) {
3143 case WM8994:
3144 switch (wm8994->revision) {
3145 case 2:
3146 case 3:
3147 wm8994->hubs.dcs_codes = -5;
3148 wm8994->hubs.hp_startup_mode = 1;
3149 wm8994->hubs.dcs_readback_mode = 1;
3150 break;
3151 default:
3152 wm8994->hubs.dcs_readback_mode = 1;
3153 break;
3154 }
3155
3156 case WM8958:
3157 wm8994->hubs.dcs_readback_mode = 1;
3158 break;
3159
3160 default:
3161 break;
3162 }
3163
3164 switch (control->type) {
3165 case WM8994:
3166 ret = wm8994_request_irq(codec->control_data,
3167 WM8994_IRQ_MIC1_DET,
3168 wm8994_mic_irq, "Mic 1 detect",
3169 wm8994);
3170 if (ret != 0)
3171 dev_warn(codec->dev,
3172 "Failed to request Mic1 detect IRQ: %d\n",
3173 ret);
3174
3175 ret = wm8994_request_irq(codec->control_data,
3176 WM8994_IRQ_MIC1_SHRT,
3177 wm8994_mic_irq, "Mic 1 short",
3178 wm8994);
3179 if (ret != 0)
3180 dev_warn(codec->dev,
3181 "Failed to request Mic1 short IRQ: %d\n",
3182 ret);
3183
3184 ret = wm8994_request_irq(codec->control_data,
3185 WM8994_IRQ_MIC2_DET,
3186 wm8994_mic_irq, "Mic 2 detect",
3187 wm8994);
3188 if (ret != 0)
3189 dev_warn(codec->dev,
3190 "Failed to request Mic2 detect IRQ: %d\n",
3191 ret);
3192
3193 ret = wm8994_request_irq(codec->control_data,
3194 WM8994_IRQ_MIC2_SHRT,
3195 wm8994_mic_irq, "Mic 2 short",
3196 wm8994);
3197 if (ret != 0)
3198 dev_warn(codec->dev,
3199 "Failed to request Mic2 short IRQ: %d\n",
3200 ret);
3201 break;
3202
3203 case WM8958:
3204 ret = wm8994_request_irq(codec->control_data,
3205 WM8994_IRQ_MIC1_DET,
3206 wm8958_mic_irq, "Mic detect",
3207 wm8994);
3208 if (ret != 0)
3209 dev_warn(codec->dev,
3210 "Failed to request Mic detect IRQ: %d\n",
3211 ret);
3212 break;
3213 }
3214
3215 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3216 * configured on init - if a system wants to do this dynamically
3217 * at runtime we can deal with that then.
3218 */
3219 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
3220 if (ret < 0) {
3221 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3222 goto err_irq;
3223 }
3224 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3225 wm8994->lrclk_shared[0] = 1;
3226 wm8994_dai[0].symmetric_rates = 1;
3227 } else {
3228 wm8994->lrclk_shared[0] = 0;
3229 }
3230
3231 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
3232 if (ret < 0) {
3233 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3234 goto err_irq;
3235 }
3236 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3237 wm8994->lrclk_shared[1] = 1;
3238 wm8994_dai[1].symmetric_rates = 1;
3239 } else {
3240 wm8994->lrclk_shared[1] = 0;
3241 }
3242
3243 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3244
3245 /* Latch volume updates (right only; we always do left then right). */
3246 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3247 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3248 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3249 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3250 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3251 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3252 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3253 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3254 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3255 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3256 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3257 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3258 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3259 WM8994_DAC1_VU, WM8994_DAC1_VU);
3260 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3261 WM8994_DAC2_VU, WM8994_DAC2_VU);
3262
3263 /* Set the low bit of the 3D stereo depth so TLV matches */
3264 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3265 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3266 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3267 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3268 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3269 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3270 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3271 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3272 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3273
3274 /* Unconditionally enable AIF1 ADC TDM mode; it only affects
3275 * behaviour on idle TDM clock cycles. */
3276 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3277 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3278
3279 wm8994_update_class_w(codec);
3280
3281 wm8994_handle_pdata(wm8994);
3282
3283 wm_hubs_add_analogue_controls(codec);
3284 snd_soc_add_controls(codec, wm8994_snd_controls,
3285 ARRAY_SIZE(wm8994_snd_controls));
3286 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3287 ARRAY_SIZE(wm8994_dapm_widgets));
3288
3289 switch (control->type) {
3290 case WM8994:
3291 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3292 ARRAY_SIZE(wm8994_specific_dapm_widgets));
3293 if (wm8994->revision < 4) {
3294 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3295 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3296 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3297 ARRAY_SIZE(wm8994_dac_revd_widgets));
3298 } else {
3299 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3300 ARRAY_SIZE(wm8994_lateclk_widgets));
3301 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3302 ARRAY_SIZE(wm8994_dac_widgets));
3303 }
3304 break;
3305 case WM8958:
3306 snd_soc_add_controls(codec, wm8958_snd_controls,
3307 ARRAY_SIZE(wm8958_snd_controls));
3308 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3309 ARRAY_SIZE(wm8958_dapm_widgets));
3310 break;
3311 }
3312
3313
3314 wm_hubs_add_analogue_routes(codec, 0, 0);
3315 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3316
3317 switch (control->type) {
3318 case WM8994:
3319 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3320 ARRAY_SIZE(wm8994_intercon));
3321
3322 if (wm8994->revision < 4) {
3323 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3324 ARRAY_SIZE(wm8994_revd_intercon));
3325 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3326 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3327 } else {
3328 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3329 ARRAY_SIZE(wm8994_lateclk_intercon));
3330 }
3331 break;
3332 case WM8958:
3333 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3334 ARRAY_SIZE(wm8958_intercon));
3335 break;
3336 }
3337
3338 return 0;
3339
3340 err_irq:
3341 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
3342 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
3343 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
3344 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994);
3345 err:
3346 kfree(wm8994);
3347 return ret;
3348 }
3349
3350 static int wm8994_codec_remove(struct snd_soc_codec *codec)
3351 {
3352 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3353 struct wm8994 *control = codec->control_data;
3354
3355 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3356
3357 pm_runtime_disable(codec->dev);
3358
3359 switch (control->type) {
3360 case WM8994:
3361 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT,
3362 wm8994);
3363 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
3364 wm8994);
3365 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3366 wm8994);
3367 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3368 wm8994);
3369 break;
3370
3371 case WM8958:
3372 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3373 wm8994);
3374 break;
3375 }
3376 kfree(wm8994->retune_mobile_texts);
3377 kfree(wm8994->drc_texts);
3378 kfree(wm8994);
3379
3380 return 0;
3381 }
3382
3383 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3384 .probe = wm8994_codec_probe,
3385 .remove = wm8994_codec_remove,
3386 .suspend = wm8994_suspend,
3387 .resume = wm8994_resume,
3388 .read = wm8994_read,
3389 .write = wm8994_write,
3390 .readable_register = wm8994_readable,
3391 .volatile_register = wm8994_volatile,
3392 .set_bias_level = wm8994_set_bias_level,
3393
3394 .reg_cache_size = WM8994_CACHE_SIZE,
3395 .reg_cache_default = wm8994_reg_defaults,
3396 .reg_word_size = 2,
3397 .compress_type = SND_SOC_RBTREE_COMPRESSION,
3398 };
3399
3400 static int __devinit wm8994_probe(struct platform_device *pdev)
3401 {
3402 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3403 wm8994_dai, ARRAY_SIZE(wm8994_dai));
3404 }
3405
3406 static int __devexit wm8994_remove(struct platform_device *pdev)
3407 {
3408 snd_soc_unregister_codec(&pdev->dev);
3409 return 0;
3410 }
3411
3412 static struct platform_driver wm8994_codec_driver = {
3413 .driver = {
3414 .name = "wm8994-codec",
3415 .owner = THIS_MODULE,
3416 },
3417 .probe = wm8994_probe,
3418 .remove = __devexit_p(wm8994_remove),
3419 };
3420
3421 static __init int wm8994_init(void)
3422 {
3423 return platform_driver_register(&wm8994_codec_driver);
3424 }
3425 module_init(wm8994_init);
3426
3427 static __exit void wm8994_exit(void)
3428 {
3429 platform_driver_unregister(&wm8994_codec_driver);
3430 }
3431 module_exit(wm8994_exit);
3432
3433
3434 MODULE_DESCRIPTION("ASoC WM8994 driver");
3435 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3436 MODULE_LICENSE("GPL");
3437 MODULE_ALIAS("platform:wm8994-codec");
Linux kernel - Deliverables
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