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x86: Move call to print_modules() out of show_regs()
[deliverable/linux.git] / sound / soc / codecs / wm8994.c
1 /*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/jack.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <trace/events/asoc.h>
32
33 #include <linux/mfd/wm8994/core.h>
34 #include <linux/mfd/wm8994/registers.h>
35 #include <linux/mfd/wm8994/pdata.h>
36 #include <linux/mfd/wm8994/gpio.h>
37
38 #include "wm8994.h"
39 #include "wm_hubs.h"
40
41 #define WM1811_JACKDET_MODE_NONE 0x0000
42 #define WM1811_JACKDET_MODE_JACK 0x0100
43 #define WM1811_JACKDET_MODE_MIC 0x0080
44 #define WM1811_JACKDET_MODE_AUDIO 0x0180
45
46 #define WM8994_NUM_DRC 3
47 #define WM8994_NUM_EQ 3
48
49 static struct {
50 unsigned int reg;
51 unsigned int mask;
52 } wm8994_vu_bits[] = {
53 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
54 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
55 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
56 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
57 { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
58 { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
59 { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
60 { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
61 { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
62 { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
63
64 { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
65 { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
66 { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
67 { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
68 { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
69 { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
70 { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
71 { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
72 { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
73 { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
74 { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
75 { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
76 { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
77 { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
78 { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
79 { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
80 };
81
82 static int wm8994_drc_base[] = {
83 WM8994_AIF1_DRC1_1,
84 WM8994_AIF1_DRC2_1,
85 WM8994_AIF2_DRC_1,
86 };
87
88 static int wm8994_retune_mobile_base[] = {
89 WM8994_AIF1_DAC1_EQ_GAINS_1,
90 WM8994_AIF1_DAC2_EQ_GAINS_1,
91 WM8994_AIF2_EQ_GAINS_1,
92 };
93
94 static void wm8958_default_micdet(u16 status, void *data);
95
96 static const struct wm8958_micd_rate micdet_rates[] = {
97 { 32768, true, 1, 4 },
98 { 32768, false, 1, 1 },
99 { 44100 * 256, true, 7, 10 },
100 { 44100 * 256, false, 7, 10 },
101 };
102
103 static const struct wm8958_micd_rate jackdet_rates[] = {
104 { 32768, true, 0, 1 },
105 { 32768, false, 0, 1 },
106 { 44100 * 256, true, 10, 10 },
107 { 44100 * 256, false, 7, 8 },
108 };
109
110 static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
111 {
112 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
113 int best, i, sysclk, val;
114 bool idle;
115 const struct wm8958_micd_rate *rates;
116 int num_rates;
117
118 if (!(wm8994->pdata && wm8994->pdata->micd_rates) &&
119 wm8994->jack_cb != wm8958_default_micdet)
120 return;
121
122 idle = !wm8994->jack_mic;
123
124 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
125 if (sysclk & WM8994_SYSCLK_SRC)
126 sysclk = wm8994->aifclk[1];
127 else
128 sysclk = wm8994->aifclk[0];
129
130 if (wm8994->pdata && wm8994->pdata->micd_rates) {
131 rates = wm8994->pdata->micd_rates;
132 num_rates = wm8994->pdata->num_micd_rates;
133 } else if (wm8994->jackdet) {
134 rates = jackdet_rates;
135 num_rates = ARRAY_SIZE(jackdet_rates);
136 } else {
137 rates = micdet_rates;
138 num_rates = ARRAY_SIZE(micdet_rates);
139 }
140
141 best = 0;
142 for (i = 0; i < num_rates; i++) {
143 if (rates[i].idle != idle)
144 continue;
145 if (abs(rates[i].sysclk - sysclk) <
146 abs(rates[best].sysclk - sysclk))
147 best = i;
148 else if (rates[best].idle != idle)
149 best = i;
150 }
151
152 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
153 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
154
155 dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n",
156 rates[best].start, rates[best].rate, sysclk,
157 idle ? "idle" : "active");
158
159 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
160 WM8958_MICD_BIAS_STARTTIME_MASK |
161 WM8958_MICD_RATE_MASK, val);
162 }
163
164 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
165 {
166 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
167 int rate;
168 int reg1 = 0;
169 int offset;
170
171 if (aif)
172 offset = 4;
173 else
174 offset = 0;
175
176 switch (wm8994->sysclk[aif]) {
177 case WM8994_SYSCLK_MCLK1:
178 rate = wm8994->mclk[0];
179 break;
180
181 case WM8994_SYSCLK_MCLK2:
182 reg1 |= 0x8;
183 rate = wm8994->mclk[1];
184 break;
185
186 case WM8994_SYSCLK_FLL1:
187 reg1 |= 0x10;
188 rate = wm8994->fll[0].out;
189 break;
190
191 case WM8994_SYSCLK_FLL2:
192 reg1 |= 0x18;
193 rate = wm8994->fll[1].out;
194 break;
195
196 default:
197 return -EINVAL;
198 }
199
200 if (rate >= 13500000) {
201 rate /= 2;
202 reg1 |= WM8994_AIF1CLK_DIV;
203
204 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
205 aif + 1, rate);
206 }
207
208 wm8994->aifclk[aif] = rate;
209
210 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
211 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
212 reg1);
213
214 return 0;
215 }
216
217 static int configure_clock(struct snd_soc_codec *codec)
218 {
219 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
220 int change, new;
221
222 /* Bring up the AIF clocks first */
223 configure_aif_clock(codec, 0);
224 configure_aif_clock(codec, 1);
225
226 /* Then switch CLK_SYS over to the higher of them; a change
227 * can only happen as a result of a clocking change which can
228 * only be made outside of DAPM so we can safely redo the
229 * clocking.
230 */
231
232 /* If they're equal it doesn't matter which is used */
233 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
234 wm8958_micd_set_rate(codec);
235 return 0;
236 }
237
238 if (wm8994->aifclk[0] < wm8994->aifclk[1])
239 new = WM8994_SYSCLK_SRC;
240 else
241 new = 0;
242
243 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
244 WM8994_SYSCLK_SRC, new);
245 if (change)
246 snd_soc_dapm_sync(&codec->dapm);
247
248 wm8958_micd_set_rate(codec);
249
250 return 0;
251 }
252
253 static int check_clk_sys(struct snd_soc_dapm_widget *source,
254 struct snd_soc_dapm_widget *sink)
255 {
256 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
257 const char *clk;
258
259 /* Check what we're currently using for CLK_SYS */
260 if (reg & WM8994_SYSCLK_SRC)
261 clk = "AIF2CLK";
262 else
263 clk = "AIF1CLK";
264
265 return strcmp(source->name, clk) == 0;
266 }
267
268 static const char *sidetone_hpf_text[] = {
269 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
270 };
271
272 static const struct soc_enum sidetone_hpf =
273 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
274
275 static const char *adc_hpf_text[] = {
276 "HiFi", "Voice 1", "Voice 2", "Voice 3"
277 };
278
279 static const struct soc_enum aif1adc1_hpf =
280 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
281
282 static const struct soc_enum aif1adc2_hpf =
283 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
284
285 static const struct soc_enum aif2adc_hpf =
286 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
287
288 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
289 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
290 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
291 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
292 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
293 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
294 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
295
296 #define WM8994_DRC_SWITCH(xname, reg, shift) \
297 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
298 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
299 .put = wm8994_put_drc_sw, \
300 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
301
302 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
303 struct snd_ctl_elem_value *ucontrol)
304 {
305 struct soc_mixer_control *mc =
306 (struct soc_mixer_control *)kcontrol->private_value;
307 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
308 int mask, ret;
309
310 /* Can't enable both ADC and DAC paths simultaneously */
311 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
312 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
313 WM8994_AIF1ADC1R_DRC_ENA_MASK;
314 else
315 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
316
317 ret = snd_soc_read(codec, mc->reg);
318 if (ret < 0)
319 return ret;
320 if (ret & mask)
321 return -EINVAL;
322
323 return snd_soc_put_volsw(kcontrol, ucontrol);
324 }
325
326 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
327 {
328 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
329 struct wm8994_pdata *pdata = wm8994->pdata;
330 int base = wm8994_drc_base[drc];
331 int cfg = wm8994->drc_cfg[drc];
332 int save, i;
333
334 /* Save any enables; the configuration should clear them. */
335 save = snd_soc_read(codec, base);
336 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
337 WM8994_AIF1ADC1R_DRC_ENA;
338
339 for (i = 0; i < WM8994_DRC_REGS; i++)
340 snd_soc_update_bits(codec, base + i, 0xffff,
341 pdata->drc_cfgs[cfg].regs[i]);
342
343 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
344 WM8994_AIF1ADC1L_DRC_ENA |
345 WM8994_AIF1ADC1R_DRC_ENA, save);
346 }
347
348 /* Icky as hell but saves code duplication */
349 static int wm8994_get_drc(const char *name)
350 {
351 if (strcmp(name, "AIF1DRC1 Mode") == 0)
352 return 0;
353 if (strcmp(name, "AIF1DRC2 Mode") == 0)
354 return 1;
355 if (strcmp(name, "AIF2DRC Mode") == 0)
356 return 2;
357 return -EINVAL;
358 }
359
360 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
361 struct snd_ctl_elem_value *ucontrol)
362 {
363 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
364 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
365 struct wm8994_pdata *pdata = wm8994->pdata;
366 int drc = wm8994_get_drc(kcontrol->id.name);
367 int value = ucontrol->value.integer.value[0];
368
369 if (drc < 0)
370 return drc;
371
372 if (value >= pdata->num_drc_cfgs)
373 return -EINVAL;
374
375 wm8994->drc_cfg[drc] = value;
376
377 wm8994_set_drc(codec, drc);
378
379 return 0;
380 }
381
382 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
383 struct snd_ctl_elem_value *ucontrol)
384 {
385 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
386 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
387 int drc = wm8994_get_drc(kcontrol->id.name);
388
389 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
390
391 return 0;
392 }
393
394 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
395 {
396 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
397 struct wm8994_pdata *pdata = wm8994->pdata;
398 int base = wm8994_retune_mobile_base[block];
399 int iface, best, best_val, save, i, cfg;
400
401 if (!pdata || !wm8994->num_retune_mobile_texts)
402 return;
403
404 switch (block) {
405 case 0:
406 case 1:
407 iface = 0;
408 break;
409 case 2:
410 iface = 1;
411 break;
412 default:
413 return;
414 }
415
416 /* Find the version of the currently selected configuration
417 * with the nearest sample rate. */
418 cfg = wm8994->retune_mobile_cfg[block];
419 best = 0;
420 best_val = INT_MAX;
421 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
422 if (strcmp(pdata->retune_mobile_cfgs[i].name,
423 wm8994->retune_mobile_texts[cfg]) == 0 &&
424 abs(pdata->retune_mobile_cfgs[i].rate
425 - wm8994->dac_rates[iface]) < best_val) {
426 best = i;
427 best_val = abs(pdata->retune_mobile_cfgs[i].rate
428 - wm8994->dac_rates[iface]);
429 }
430 }
431
432 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
433 block,
434 pdata->retune_mobile_cfgs[best].name,
435 pdata->retune_mobile_cfgs[best].rate,
436 wm8994->dac_rates[iface]);
437
438 /* The EQ will be disabled while reconfiguring it, remember the
439 * current configuration.
440 */
441 save = snd_soc_read(codec, base);
442 save &= WM8994_AIF1DAC1_EQ_ENA;
443
444 for (i = 0; i < WM8994_EQ_REGS; i++)
445 snd_soc_update_bits(codec, base + i, 0xffff,
446 pdata->retune_mobile_cfgs[best].regs[i]);
447
448 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
449 }
450
451 /* Icky as hell but saves code duplication */
452 static int wm8994_get_retune_mobile_block(const char *name)
453 {
454 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
455 return 0;
456 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
457 return 1;
458 if (strcmp(name, "AIF2 EQ Mode") == 0)
459 return 2;
460 return -EINVAL;
461 }
462
463 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
464 struct snd_ctl_elem_value *ucontrol)
465 {
466 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
467 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
468 struct wm8994_pdata *pdata = wm8994->pdata;
469 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
470 int value = ucontrol->value.integer.value[0];
471
472 if (block < 0)
473 return block;
474
475 if (value >= pdata->num_retune_mobile_cfgs)
476 return -EINVAL;
477
478 wm8994->retune_mobile_cfg[block] = value;
479
480 wm8994_set_retune_mobile(codec, block);
481
482 return 0;
483 }
484
485 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
486 struct snd_ctl_elem_value *ucontrol)
487 {
488 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
489 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
490 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
491
492 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
493
494 return 0;
495 }
496
497 static const char *aif_chan_src_text[] = {
498 "Left", "Right"
499 };
500
501 static const struct soc_enum aif1adcl_src =
502 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
503
504 static const struct soc_enum aif1adcr_src =
505 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
506
507 static const struct soc_enum aif2adcl_src =
508 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
509
510 static const struct soc_enum aif2adcr_src =
511 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
512
513 static const struct soc_enum aif1dacl_src =
514 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
515
516 static const struct soc_enum aif1dacr_src =
517 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
518
519 static const struct soc_enum aif2dacl_src =
520 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
521
522 static const struct soc_enum aif2dacr_src =
523 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
524
525 static const char *osr_text[] = {
526 "Low Power", "High Performance",
527 };
528
529 static const struct soc_enum dac_osr =
530 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
531
532 static const struct soc_enum adc_osr =
533 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
534
535 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
536 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
537 WM8994_AIF1_ADC1_RIGHT_VOLUME,
538 1, 119, 0, digital_tlv),
539 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
540 WM8994_AIF1_ADC2_RIGHT_VOLUME,
541 1, 119, 0, digital_tlv),
542 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
543 WM8994_AIF2_ADC_RIGHT_VOLUME,
544 1, 119, 0, digital_tlv),
545
546 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
547 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
548 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
549 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
550
551 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
552 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
553 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
554 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
555
556 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
557 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
558 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
559 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
560 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
561 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
562
563 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
564 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
565
566 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
567 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
568 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
569
570 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
571 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
572 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
573
574 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
575 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
576 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
577
578 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
579 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
580 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
581
582 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
583 5, 12, 0, st_tlv),
584 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
585 0, 12, 0, st_tlv),
586 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
587 5, 12, 0, st_tlv),
588 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
589 0, 12, 0, st_tlv),
590 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
591 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
592
593 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
594 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
595
596 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
597 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
598
599 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
600 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
601
602 SOC_ENUM("ADC OSR", adc_osr),
603 SOC_ENUM("DAC OSR", dac_osr),
604
605 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
606 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
607 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
608 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
609
610 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
611 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
612 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
613 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
614
615 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
616 6, 1, 1, wm_hubs_spkmix_tlv),
617 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
618 2, 1, 1, wm_hubs_spkmix_tlv),
619
620 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
621 6, 1, 1, wm_hubs_spkmix_tlv),
622 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
623 2, 1, 1, wm_hubs_spkmix_tlv),
624
625 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
626 10, 15, 0, wm8994_3d_tlv),
627 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
628 8, 1, 0),
629 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
630 10, 15, 0, wm8994_3d_tlv),
631 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
632 8, 1, 0),
633 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
634 10, 15, 0, wm8994_3d_tlv),
635 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
636 8, 1, 0),
637 };
638
639 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
640 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
641 eq_tlv),
642 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
643 eq_tlv),
644 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
645 eq_tlv),
646 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
647 eq_tlv),
648 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
649 eq_tlv),
650
651 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
652 eq_tlv),
653 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
654 eq_tlv),
655 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
656 eq_tlv),
657 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
658 eq_tlv),
659 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
660 eq_tlv),
661
662 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
663 eq_tlv),
664 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
665 eq_tlv),
666 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
667 eq_tlv),
668 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
669 eq_tlv),
670 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
671 eq_tlv),
672 };
673
674 static const char *wm8958_ng_text[] = {
675 "30ms", "125ms", "250ms", "500ms",
676 };
677
678 static const struct soc_enum wm8958_aif1dac1_ng_hold =
679 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
680 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
681
682 static const struct soc_enum wm8958_aif1dac2_ng_hold =
683 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
684 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
685
686 static const struct soc_enum wm8958_aif2dac_ng_hold =
687 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
688 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
689
690 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
691 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
692
693 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
694 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
695 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
696 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
697 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
698 7, 1, ng_tlv),
699
700 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
701 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
702 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
703 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
704 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
705 7, 1, ng_tlv),
706
707 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
708 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
709 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
710 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
711 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
712 7, 1, ng_tlv),
713 };
714
715 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
716 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
717 mixin_boost_tlv),
718 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
719 mixin_boost_tlv),
720 };
721
722 /* We run all mode setting through a function to enforce audio mode */
723 static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
724 {
725 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
726
727 if (!wm8994->jackdet || !wm8994->jack_cb)
728 return;
729
730 if (!wm8994->jackdet || !wm8994->jack_cb)
731 return;
732
733 if (wm8994->active_refcount)
734 mode = WM1811_JACKDET_MODE_AUDIO;
735
736 if (mode == wm8994->jackdet_mode)
737 return;
738
739 wm8994->jackdet_mode = mode;
740
741 /* Always use audio mode to detect while the system is active */
742 if (mode != WM1811_JACKDET_MODE_NONE)
743 mode = WM1811_JACKDET_MODE_AUDIO;
744
745 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
746 WM1811_JACKDET_MODE_MASK, mode);
747 }
748
749 static void active_reference(struct snd_soc_codec *codec)
750 {
751 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
752
753 mutex_lock(&wm8994->accdet_lock);
754
755 wm8994->active_refcount++;
756
757 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
758 wm8994->active_refcount);
759
760 /* If we're using jack detection go into audio mode */
761 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
762
763 mutex_unlock(&wm8994->accdet_lock);
764 }
765
766 static void active_dereference(struct snd_soc_codec *codec)
767 {
768 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
769 u16 mode;
770
771 mutex_lock(&wm8994->accdet_lock);
772
773 wm8994->active_refcount--;
774
775 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
776 wm8994->active_refcount);
777
778 if (wm8994->active_refcount == 0) {
779 /* Go into appropriate detection only mode */
780 if (wm8994->jack_mic || wm8994->mic_detecting)
781 mode = WM1811_JACKDET_MODE_MIC;
782 else
783 mode = WM1811_JACKDET_MODE_JACK;
784
785 wm1811_jackdet_set_mode(codec, mode);
786 }
787
788 mutex_unlock(&wm8994->accdet_lock);
789 }
790
791 static int clk_sys_event(struct snd_soc_dapm_widget *w,
792 struct snd_kcontrol *kcontrol, int event)
793 {
794 struct snd_soc_codec *codec = w->codec;
795
796 switch (event) {
797 case SND_SOC_DAPM_PRE_PMU:
798 return configure_clock(codec);
799
800 case SND_SOC_DAPM_POST_PMD:
801 configure_clock(codec);
802 break;
803 }
804
805 return 0;
806 }
807
808 static void vmid_reference(struct snd_soc_codec *codec)
809 {
810 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
811
812 pm_runtime_get_sync(codec->dev);
813
814 wm8994->vmid_refcount++;
815
816 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
817 wm8994->vmid_refcount);
818
819 if (wm8994->vmid_refcount == 1) {
820 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
821 WM8994_LINEOUT1_DISCH |
822 WM8994_LINEOUT2_DISCH, 0);
823
824 wm_hubs_vmid_ena(codec);
825
826 switch (wm8994->vmid_mode) {
827 default:
828 WARN_ON(NULL == "Invalid VMID mode");
829 case WM8994_VMID_NORMAL:
830 /* Startup bias, VMID ramp & buffer */
831 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
832 WM8994_BIAS_SRC |
833 WM8994_VMID_DISCH |
834 WM8994_STARTUP_BIAS_ENA |
835 WM8994_VMID_BUF_ENA |
836 WM8994_VMID_RAMP_MASK,
837 WM8994_BIAS_SRC |
838 WM8994_STARTUP_BIAS_ENA |
839 WM8994_VMID_BUF_ENA |
840 (0x3 << WM8994_VMID_RAMP_SHIFT));
841
842 /* Main bias enable, VMID=2x40k */
843 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
844 WM8994_BIAS_ENA |
845 WM8994_VMID_SEL_MASK,
846 WM8994_BIAS_ENA | 0x2);
847
848 msleep(50);
849
850 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
851 WM8994_VMID_RAMP_MASK |
852 WM8994_BIAS_SRC,
853 0);
854 break;
855
856 case WM8994_VMID_FORCE:
857 /* Startup bias, slow VMID ramp & buffer */
858 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
859 WM8994_BIAS_SRC |
860 WM8994_VMID_DISCH |
861 WM8994_STARTUP_BIAS_ENA |
862 WM8994_VMID_BUF_ENA |
863 WM8994_VMID_RAMP_MASK,
864 WM8994_BIAS_SRC |
865 WM8994_STARTUP_BIAS_ENA |
866 WM8994_VMID_BUF_ENA |
867 (0x2 << WM8994_VMID_RAMP_SHIFT));
868
869 /* Main bias enable, VMID=2x40k */
870 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
871 WM8994_BIAS_ENA |
872 WM8994_VMID_SEL_MASK,
873 WM8994_BIAS_ENA | 0x2);
874
875 msleep(400);
876
877 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
878 WM8994_VMID_RAMP_MASK |
879 WM8994_BIAS_SRC,
880 0);
881 break;
882 }
883 }
884 }
885
886 static void vmid_dereference(struct snd_soc_codec *codec)
887 {
888 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
889
890 wm8994->vmid_refcount--;
891
892 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
893 wm8994->vmid_refcount);
894
895 if (wm8994->vmid_refcount == 0) {
896 if (wm8994->hubs.lineout1_se)
897 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
898 WM8994_LINEOUT1N_ENA |
899 WM8994_LINEOUT1P_ENA,
900 WM8994_LINEOUT1N_ENA |
901 WM8994_LINEOUT1P_ENA);
902
903 if (wm8994->hubs.lineout2_se)
904 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
905 WM8994_LINEOUT2N_ENA |
906 WM8994_LINEOUT2P_ENA,
907 WM8994_LINEOUT2N_ENA |
908 WM8994_LINEOUT2P_ENA);
909
910 /* Start discharging VMID */
911 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
912 WM8994_BIAS_SRC |
913 WM8994_VMID_DISCH,
914 WM8994_BIAS_SRC |
915 WM8994_VMID_DISCH);
916
917 switch (wm8994->vmid_mode) {
918 case WM8994_VMID_FORCE:
919 msleep(350);
920 break;
921 default:
922 break;
923 }
924
925 snd_soc_update_bits(codec, WM8994_ADDITIONAL_CONTROL,
926 WM8994_VROI, WM8994_VROI);
927
928 /* Active discharge */
929 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
930 WM8994_LINEOUT1_DISCH |
931 WM8994_LINEOUT2_DISCH,
932 WM8994_LINEOUT1_DISCH |
933 WM8994_LINEOUT2_DISCH);
934
935 msleep(150);
936
937 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
938 WM8994_LINEOUT1N_ENA |
939 WM8994_LINEOUT1P_ENA |
940 WM8994_LINEOUT2N_ENA |
941 WM8994_LINEOUT2P_ENA, 0);
942
943 snd_soc_update_bits(codec, WM8994_ADDITIONAL_CONTROL,
944 WM8994_VROI, 0);
945
946 /* Switch off startup biases */
947 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
948 WM8994_BIAS_SRC |
949 WM8994_STARTUP_BIAS_ENA |
950 WM8994_VMID_BUF_ENA |
951 WM8994_VMID_RAMP_MASK, 0);
952
953 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
954 WM8994_BIAS_ENA | WM8994_VMID_SEL_MASK, 0);
955
956 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
957 WM8994_VMID_RAMP_MASK, 0);
958 }
959
960 pm_runtime_put(codec->dev);
961 }
962
963 static int vmid_event(struct snd_soc_dapm_widget *w,
964 struct snd_kcontrol *kcontrol, int event)
965 {
966 struct snd_soc_codec *codec = w->codec;
967
968 switch (event) {
969 case SND_SOC_DAPM_PRE_PMU:
970 vmid_reference(codec);
971 break;
972
973 case SND_SOC_DAPM_POST_PMD:
974 vmid_dereference(codec);
975 break;
976 }
977
978 return 0;
979 }
980
981 static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec)
982 {
983 int source = 0; /* GCC flow analysis can't track enable */
984 int reg, reg_r;
985
986 /* We also need the same AIF source for L/R and only one path */
987 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
988 switch (reg) {
989 case WM8994_AIF2DACL_TO_DAC1L:
990 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
991 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
992 break;
993 case WM8994_AIF1DAC2L_TO_DAC1L:
994 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
995 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
996 break;
997 case WM8994_AIF1DAC1L_TO_DAC1L:
998 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
999 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1000 break;
1001 default:
1002 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
1003 return false;
1004 }
1005
1006 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1007 if (reg_r != reg) {
1008 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
1009 return false;
1010 }
1011
1012 /* Set the source up */
1013 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1014 WM8994_CP_DYN_SRC_SEL_MASK, source);
1015
1016 return true;
1017 }
1018
1019 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1020 struct snd_kcontrol *kcontrol, int event)
1021 {
1022 struct snd_soc_codec *codec = w->codec;
1023 struct wm8994 *control = codec->control_data;
1024 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
1025 int i;
1026 int dac;
1027 int adc;
1028 int val;
1029
1030 switch (control->type) {
1031 case WM8994:
1032 case WM8958:
1033 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1034 break;
1035 default:
1036 break;
1037 }
1038
1039 switch (event) {
1040 case SND_SOC_DAPM_PRE_PMU:
1041 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
1042 if ((val & WM8994_AIF1ADCL_SRC) &&
1043 (val & WM8994_AIF1ADCR_SRC))
1044 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1045 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1046 !(val & WM8994_AIF1ADCR_SRC))
1047 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1048 else
1049 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1050 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1051
1052 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
1053 if ((val & WM8994_AIF1DACL_SRC) &&
1054 (val & WM8994_AIF1DACR_SRC))
1055 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1056 else if (!(val & WM8994_AIF1DACL_SRC) &&
1057 !(val & WM8994_AIF1DACR_SRC))
1058 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1059 else
1060 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1061 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1062
1063 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1064 mask, adc);
1065 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1066 mask, dac);
1067 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1068 WM8994_AIF1DSPCLK_ENA |
1069 WM8994_SYSDSPCLK_ENA,
1070 WM8994_AIF1DSPCLK_ENA |
1071 WM8994_SYSDSPCLK_ENA);
1072 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
1073 WM8994_AIF1ADC1R_ENA |
1074 WM8994_AIF1ADC1L_ENA |
1075 WM8994_AIF1ADC2R_ENA |
1076 WM8994_AIF1ADC2L_ENA);
1077 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
1078 WM8994_AIF1DAC1R_ENA |
1079 WM8994_AIF1DAC1L_ENA |
1080 WM8994_AIF1DAC2R_ENA |
1081 WM8994_AIF1DAC2L_ENA);
1082 break;
1083
1084 case SND_SOC_DAPM_POST_PMU:
1085 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1086 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1087 snd_soc_read(codec,
1088 wm8994_vu_bits[i].reg));
1089 break;
1090
1091 case SND_SOC_DAPM_PRE_PMD:
1092 case SND_SOC_DAPM_POST_PMD:
1093 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1094 mask, 0);
1095 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1096 mask, 0);
1097
1098 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1099 if (val & WM8994_AIF2DSPCLK_ENA)
1100 val = WM8994_SYSDSPCLK_ENA;
1101 else
1102 val = 0;
1103 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1104 WM8994_SYSDSPCLK_ENA |
1105 WM8994_AIF1DSPCLK_ENA, val);
1106 break;
1107 }
1108
1109 return 0;
1110 }
1111
1112 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1113 struct snd_kcontrol *kcontrol, int event)
1114 {
1115 struct snd_soc_codec *codec = w->codec;
1116 int i;
1117 int dac;
1118 int adc;
1119 int val;
1120
1121 switch (event) {
1122 case SND_SOC_DAPM_PRE_PMU:
1123 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1124 if ((val & WM8994_AIF2ADCL_SRC) &&
1125 (val & WM8994_AIF2ADCR_SRC))
1126 adc = WM8994_AIF2ADCR_ENA;
1127 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1128 !(val & WM8994_AIF2ADCR_SRC))
1129 adc = WM8994_AIF2ADCL_ENA;
1130 else
1131 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1132
1133
1134 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1135 if ((val & WM8994_AIF2DACL_SRC) &&
1136 (val & WM8994_AIF2DACR_SRC))
1137 dac = WM8994_AIF2DACR_ENA;
1138 else if (!(val & WM8994_AIF2DACL_SRC) &&
1139 !(val & WM8994_AIF2DACR_SRC))
1140 dac = WM8994_AIF2DACL_ENA;
1141 else
1142 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1143
1144 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1145 WM8994_AIF2ADCL_ENA |
1146 WM8994_AIF2ADCR_ENA, adc);
1147 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1148 WM8994_AIF2DACL_ENA |
1149 WM8994_AIF2DACR_ENA, dac);
1150 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1151 WM8994_AIF2DSPCLK_ENA |
1152 WM8994_SYSDSPCLK_ENA,
1153 WM8994_AIF2DSPCLK_ENA |
1154 WM8994_SYSDSPCLK_ENA);
1155 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1156 WM8994_AIF2ADCL_ENA |
1157 WM8994_AIF2ADCR_ENA,
1158 WM8994_AIF2ADCL_ENA |
1159 WM8994_AIF2ADCR_ENA);
1160 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1161 WM8994_AIF2DACL_ENA |
1162 WM8994_AIF2DACR_ENA,
1163 WM8994_AIF2DACL_ENA |
1164 WM8994_AIF2DACR_ENA);
1165 break;
1166
1167 case SND_SOC_DAPM_POST_PMU:
1168 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1169 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1170 snd_soc_read(codec,
1171 wm8994_vu_bits[i].reg));
1172 break;
1173
1174 case SND_SOC_DAPM_PRE_PMD:
1175 case SND_SOC_DAPM_POST_PMD:
1176 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1177 WM8994_AIF2DACL_ENA |
1178 WM8994_AIF2DACR_ENA, 0);
1179 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1180 WM8994_AIF2ADCL_ENA |
1181 WM8994_AIF2ADCR_ENA, 0);
1182
1183 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1184 if (val & WM8994_AIF1DSPCLK_ENA)
1185 val = WM8994_SYSDSPCLK_ENA;
1186 else
1187 val = 0;
1188 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1189 WM8994_SYSDSPCLK_ENA |
1190 WM8994_AIF2DSPCLK_ENA, val);
1191 break;
1192 }
1193
1194 return 0;
1195 }
1196
1197 static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1198 struct snd_kcontrol *kcontrol, int event)
1199 {
1200 struct snd_soc_codec *codec = w->codec;
1201 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1202
1203 switch (event) {
1204 case SND_SOC_DAPM_PRE_PMU:
1205 wm8994->aif1clk_enable = 1;
1206 break;
1207 case SND_SOC_DAPM_POST_PMD:
1208 wm8994->aif1clk_disable = 1;
1209 break;
1210 }
1211
1212 return 0;
1213 }
1214
1215 static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1216 struct snd_kcontrol *kcontrol, int event)
1217 {
1218 struct snd_soc_codec *codec = w->codec;
1219 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1220
1221 switch (event) {
1222 case SND_SOC_DAPM_PRE_PMU:
1223 wm8994->aif2clk_enable = 1;
1224 break;
1225 case SND_SOC_DAPM_POST_PMD:
1226 wm8994->aif2clk_disable = 1;
1227 break;
1228 }
1229
1230 return 0;
1231 }
1232
1233 static int late_enable_ev(struct snd_soc_dapm_widget *w,
1234 struct snd_kcontrol *kcontrol, int event)
1235 {
1236 struct snd_soc_codec *codec = w->codec;
1237 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1238
1239 switch (event) {
1240 case SND_SOC_DAPM_PRE_PMU:
1241 if (wm8994->aif1clk_enable) {
1242 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1243 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1244 WM8994_AIF1CLK_ENA_MASK,
1245 WM8994_AIF1CLK_ENA);
1246 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1247 wm8994->aif1clk_enable = 0;
1248 }
1249 if (wm8994->aif2clk_enable) {
1250 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1251 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1252 WM8994_AIF2CLK_ENA_MASK,
1253 WM8994_AIF2CLK_ENA);
1254 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1255 wm8994->aif2clk_enable = 0;
1256 }
1257 break;
1258 }
1259
1260 /* We may also have postponed startup of DSP, handle that. */
1261 wm8958_aif_ev(w, kcontrol, event);
1262
1263 return 0;
1264 }
1265
1266 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1267 struct snd_kcontrol *kcontrol, int event)
1268 {
1269 struct snd_soc_codec *codec = w->codec;
1270 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1271
1272 switch (event) {
1273 case SND_SOC_DAPM_POST_PMD:
1274 if (wm8994->aif1clk_disable) {
1275 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1276 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1277 WM8994_AIF1CLK_ENA_MASK, 0);
1278 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1279 wm8994->aif1clk_disable = 0;
1280 }
1281 if (wm8994->aif2clk_disable) {
1282 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1283 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1284 WM8994_AIF2CLK_ENA_MASK, 0);
1285 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1286 wm8994->aif2clk_disable = 0;
1287 }
1288 break;
1289 }
1290
1291 return 0;
1292 }
1293
1294 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1295 struct snd_kcontrol *kcontrol, int event)
1296 {
1297 late_enable_ev(w, kcontrol, event);
1298 return 0;
1299 }
1300
1301 static int micbias_ev(struct snd_soc_dapm_widget *w,
1302 struct snd_kcontrol *kcontrol, int event)
1303 {
1304 late_enable_ev(w, kcontrol, event);
1305 return 0;
1306 }
1307
1308 static int dac_ev(struct snd_soc_dapm_widget *w,
1309 struct snd_kcontrol *kcontrol, int event)
1310 {
1311 struct snd_soc_codec *codec = w->codec;
1312 unsigned int mask = 1 << w->shift;
1313
1314 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1315 mask, mask);
1316 return 0;
1317 }
1318
1319 static const char *adc_mux_text[] = {
1320 "ADC",
1321 "DMIC",
1322 };
1323
1324 static const struct soc_enum adc_enum =
1325 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1326
1327 static const struct snd_kcontrol_new adcl_mux =
1328 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1329
1330 static const struct snd_kcontrol_new adcr_mux =
1331 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1332
1333 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1334 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1335 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1336 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1337 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1338 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1339 };
1340
1341 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1342 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1343 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1344 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1345 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1346 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1347 };
1348
1349 /* Debugging; dump chip status after DAPM transitions */
1350 static int post_ev(struct snd_soc_dapm_widget *w,
1351 struct snd_kcontrol *kcontrol, int event)
1352 {
1353 struct snd_soc_codec *codec = w->codec;
1354 dev_dbg(codec->dev, "SRC status: %x\n",
1355 snd_soc_read(codec,
1356 WM8994_RATE_STATUS));
1357 return 0;
1358 }
1359
1360 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1361 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1362 1, 1, 0),
1363 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1364 0, 1, 0),
1365 };
1366
1367 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1368 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1369 1, 1, 0),
1370 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1371 0, 1, 0),
1372 };
1373
1374 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1375 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1376 1, 1, 0),
1377 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1378 0, 1, 0),
1379 };
1380
1381 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1382 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1383 1, 1, 0),
1384 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1385 0, 1, 0),
1386 };
1387
1388 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1389 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1390 5, 1, 0),
1391 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1392 4, 1, 0),
1393 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1394 2, 1, 0),
1395 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1396 1, 1, 0),
1397 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1398 0, 1, 0),
1399 };
1400
1401 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1402 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1403 5, 1, 0),
1404 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1405 4, 1, 0),
1406 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1407 2, 1, 0),
1408 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1409 1, 1, 0),
1410 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1411 0, 1, 0),
1412 };
1413
1414 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1415 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1416 .info = snd_soc_info_volsw, \
1417 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1418 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1419
1420 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1421 struct snd_ctl_elem_value *ucontrol)
1422 {
1423 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1424 struct snd_soc_dapm_widget *w = wlist->widgets[0];
1425 struct snd_soc_codec *codec = w->codec;
1426 int ret;
1427
1428 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1429
1430 wm_hubs_update_class_w(codec);
1431
1432 return ret;
1433 }
1434
1435 static const struct snd_kcontrol_new dac1l_mix[] = {
1436 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1437 5, 1, 0),
1438 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1439 4, 1, 0),
1440 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1441 2, 1, 0),
1442 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1443 1, 1, 0),
1444 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1445 0, 1, 0),
1446 };
1447
1448 static const struct snd_kcontrol_new dac1r_mix[] = {
1449 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1450 5, 1, 0),
1451 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1452 4, 1, 0),
1453 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1454 2, 1, 0),
1455 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1456 1, 1, 0),
1457 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1458 0, 1, 0),
1459 };
1460
1461 static const char *sidetone_text[] = {
1462 "ADC/DMIC1", "DMIC2",
1463 };
1464
1465 static const struct soc_enum sidetone1_enum =
1466 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1467
1468 static const struct snd_kcontrol_new sidetone1_mux =
1469 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1470
1471 static const struct soc_enum sidetone2_enum =
1472 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1473
1474 static const struct snd_kcontrol_new sidetone2_mux =
1475 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1476
1477 static const char *aif1dac_text[] = {
1478 "AIF1DACDAT", "AIF3DACDAT",
1479 };
1480
1481 static const struct soc_enum aif1dac_enum =
1482 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1483
1484 static const struct snd_kcontrol_new aif1dac_mux =
1485 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1486
1487 static const char *aif2dac_text[] = {
1488 "AIF2DACDAT", "AIF3DACDAT",
1489 };
1490
1491 static const struct soc_enum aif2dac_enum =
1492 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1493
1494 static const struct snd_kcontrol_new aif2dac_mux =
1495 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1496
1497 static const char *aif2adc_text[] = {
1498 "AIF2ADCDAT", "AIF3DACDAT",
1499 };
1500
1501 static const struct soc_enum aif2adc_enum =
1502 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1503
1504 static const struct snd_kcontrol_new aif2adc_mux =
1505 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1506
1507 static const char *aif3adc_text[] = {
1508 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1509 };
1510
1511 static const struct soc_enum wm8994_aif3adc_enum =
1512 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1513
1514 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1515 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1516
1517 static const struct soc_enum wm8958_aif3adc_enum =
1518 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1519
1520 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1521 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1522
1523 static const char *mono_pcm_out_text[] = {
1524 "None", "AIF2ADCL", "AIF2ADCR",
1525 };
1526
1527 static const struct soc_enum mono_pcm_out_enum =
1528 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1529
1530 static const struct snd_kcontrol_new mono_pcm_out_mux =
1531 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1532
1533 static const char *aif2dac_src_text[] = {
1534 "AIF2", "AIF3",
1535 };
1536
1537 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1538 static const struct soc_enum aif2dacl_src_enum =
1539 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1540
1541 static const struct snd_kcontrol_new aif2dacl_src_mux =
1542 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1543
1544 static const struct soc_enum aif2dacr_src_enum =
1545 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1546
1547 static const struct snd_kcontrol_new aif2dacr_src_mux =
1548 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1549
1550 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1551 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
1552 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1553 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
1554 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1555
1556 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1557 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1558 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1559 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1560 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1561 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1562 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1563 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1564 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1565 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1566
1567 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1568 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1569 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1570 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1571 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1572 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1573 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
1574 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1575 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
1576 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1577
1578 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1579 };
1580
1581 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1582 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
1583 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1584 SND_SOC_DAPM_PRE_PMD),
1585 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
1586 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1587 SND_SOC_DAPM_PRE_PMD),
1588 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1589 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1590 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1591 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1592 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1593 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1594 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
1595 };
1596
1597 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1598 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1599 dac_ev, SND_SOC_DAPM_PRE_PMU),
1600 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1601 dac_ev, SND_SOC_DAPM_PRE_PMU),
1602 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1603 dac_ev, SND_SOC_DAPM_PRE_PMU),
1604 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1605 dac_ev, SND_SOC_DAPM_PRE_PMU),
1606 };
1607
1608 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1609 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1610 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1611 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1612 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1613 };
1614
1615 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1616 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1617 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1618 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1619 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1620 };
1621
1622 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1623 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1624 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1625 };
1626
1627 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1628 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1629 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1630 SND_SOC_DAPM_INPUT("Clock"),
1631
1632 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1633 SND_SOC_DAPM_PRE_PMU),
1634 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1635 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1636
1637 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1638 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1639
1640 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1641 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1642 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
1643
1644 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1645 0, SND_SOC_NOPM, 9, 0),
1646 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1647 0, SND_SOC_NOPM, 8, 0),
1648 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1649 SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
1650 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1651 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1652 SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
1653 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1654
1655 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1656 0, SND_SOC_NOPM, 11, 0),
1657 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1658 0, SND_SOC_NOPM, 10, 0),
1659 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1660 SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
1661 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1662 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1663 SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
1664 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1665
1666 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1667 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1668 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1669 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1670
1671 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1672 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1673 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1674 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1675
1676 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1677 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1678 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1679 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1680
1681 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1682 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1683
1684 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1685 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1686 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1687 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1688
1689 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1690 SND_SOC_NOPM, 13, 0),
1691 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1692 SND_SOC_NOPM, 12, 0),
1693 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1694 SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
1695 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1696 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1697 SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
1698 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1699
1700 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1701 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1702 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1703 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1704
1705 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1706 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1707 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1708
1709 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1710 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1711
1712 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1713
1714 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1715 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1716 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1717 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1718
1719 /* Power is done with the muxes since the ADC power also controls the
1720 * downsampling chain, the chip will automatically manage the analogue
1721 * specific portions.
1722 */
1723 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1724 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1725
1726 SND_SOC_DAPM_POST("Debug log", post_ev),
1727 };
1728
1729 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1730 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1731 };
1732
1733 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1734 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
1735 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1736 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1737 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1738 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1739 };
1740
1741 static const struct snd_soc_dapm_route intercon[] = {
1742 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1743 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1744
1745 { "DSP1CLK", NULL, "CLK_SYS" },
1746 { "DSP2CLK", NULL, "CLK_SYS" },
1747 { "DSPINTCLK", NULL, "CLK_SYS" },
1748
1749 { "AIF1ADC1L", NULL, "AIF1CLK" },
1750 { "AIF1ADC1L", NULL, "DSP1CLK" },
1751 { "AIF1ADC1R", NULL, "AIF1CLK" },
1752 { "AIF1ADC1R", NULL, "DSP1CLK" },
1753 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1754
1755 { "AIF1DAC1L", NULL, "AIF1CLK" },
1756 { "AIF1DAC1L", NULL, "DSP1CLK" },
1757 { "AIF1DAC1R", NULL, "AIF1CLK" },
1758 { "AIF1DAC1R", NULL, "DSP1CLK" },
1759 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1760
1761 { "AIF1ADC2L", NULL, "AIF1CLK" },
1762 { "AIF1ADC2L", NULL, "DSP1CLK" },
1763 { "AIF1ADC2R", NULL, "AIF1CLK" },
1764 { "AIF1ADC2R", NULL, "DSP1CLK" },
1765 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1766
1767 { "AIF1DAC2L", NULL, "AIF1CLK" },
1768 { "AIF1DAC2L", NULL, "DSP1CLK" },
1769 { "AIF1DAC2R", NULL, "AIF1CLK" },
1770 { "AIF1DAC2R", NULL, "DSP1CLK" },
1771 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1772
1773 { "AIF2ADCL", NULL, "AIF2CLK" },
1774 { "AIF2ADCL", NULL, "DSP2CLK" },
1775 { "AIF2ADCR", NULL, "AIF2CLK" },
1776 { "AIF2ADCR", NULL, "DSP2CLK" },
1777 { "AIF2ADCR", NULL, "DSPINTCLK" },
1778
1779 { "AIF2DACL", NULL, "AIF2CLK" },
1780 { "AIF2DACL", NULL, "DSP2CLK" },
1781 { "AIF2DACR", NULL, "AIF2CLK" },
1782 { "AIF2DACR", NULL, "DSP2CLK" },
1783 { "AIF2DACR", NULL, "DSPINTCLK" },
1784
1785 { "DMIC1L", NULL, "DMIC1DAT" },
1786 { "DMIC1L", NULL, "CLK_SYS" },
1787 { "DMIC1R", NULL, "DMIC1DAT" },
1788 { "DMIC1R", NULL, "CLK_SYS" },
1789 { "DMIC2L", NULL, "DMIC2DAT" },
1790 { "DMIC2L", NULL, "CLK_SYS" },
1791 { "DMIC2R", NULL, "DMIC2DAT" },
1792 { "DMIC2R", NULL, "CLK_SYS" },
1793
1794 { "ADCL", NULL, "AIF1CLK" },
1795 { "ADCL", NULL, "DSP1CLK" },
1796 { "ADCL", NULL, "DSPINTCLK" },
1797
1798 { "ADCR", NULL, "AIF1CLK" },
1799 { "ADCR", NULL, "DSP1CLK" },
1800 { "ADCR", NULL, "DSPINTCLK" },
1801
1802 { "ADCL Mux", "ADC", "ADCL" },
1803 { "ADCL Mux", "DMIC", "DMIC1L" },
1804 { "ADCR Mux", "ADC", "ADCR" },
1805 { "ADCR Mux", "DMIC", "DMIC1R" },
1806
1807 { "DAC1L", NULL, "AIF1CLK" },
1808 { "DAC1L", NULL, "DSP1CLK" },
1809 { "DAC1L", NULL, "DSPINTCLK" },
1810
1811 { "DAC1R", NULL, "AIF1CLK" },
1812 { "DAC1R", NULL, "DSP1CLK" },
1813 { "DAC1R", NULL, "DSPINTCLK" },
1814
1815 { "DAC2L", NULL, "AIF2CLK" },
1816 { "DAC2L", NULL, "DSP2CLK" },
1817 { "DAC2L", NULL, "DSPINTCLK" },
1818
1819 { "DAC2R", NULL, "AIF2DACR" },
1820 { "DAC2R", NULL, "AIF2CLK" },
1821 { "DAC2R", NULL, "DSP2CLK" },
1822 { "DAC2R", NULL, "DSPINTCLK" },
1823
1824 { "TOCLK", NULL, "CLK_SYS" },
1825
1826 { "AIF1DACDAT", NULL, "AIF1 Playback" },
1827 { "AIF2DACDAT", NULL, "AIF2 Playback" },
1828 { "AIF3DACDAT", NULL, "AIF3 Playback" },
1829
1830 { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1831 { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1832 { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1833
1834 /* AIF1 outputs */
1835 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1836 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1837 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1838
1839 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1840 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1841 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1842
1843 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1844 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1845 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1846
1847 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1848 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1849 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1850
1851 /* Pin level routing for AIF3 */
1852 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1853 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1854 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1855 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1856
1857 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1858 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1859 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1860 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1861 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1862 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1863 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1864
1865 /* DAC1 inputs */
1866 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1867 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1868 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1869 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1870 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1871
1872 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1873 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1874 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1875 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1876 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1877
1878 /* DAC2/AIF2 outputs */
1879 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1880 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1881 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1882 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1883 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1884 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1885
1886 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1887 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1888 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1889 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1890 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1891 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1892
1893 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1894 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1895 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1896 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1897
1898 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1899
1900 /* AIF3 output */
1901 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1902 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1903 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1904 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1905 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1906 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1907 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1908 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1909
1910 /* Sidetone */
1911 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1912 { "Left Sidetone", "DMIC2", "DMIC2L" },
1913 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1914 { "Right Sidetone", "DMIC2", "DMIC2R" },
1915
1916 /* Output stages */
1917 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1918 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1919
1920 { "SPKL", "DAC1 Switch", "DAC1L" },
1921 { "SPKL", "DAC2 Switch", "DAC2L" },
1922
1923 { "SPKR", "DAC1 Switch", "DAC1R" },
1924 { "SPKR", "DAC2 Switch", "DAC2R" },
1925
1926 { "Left Headphone Mux", "DAC", "DAC1L" },
1927 { "Right Headphone Mux", "DAC", "DAC1R" },
1928 };
1929
1930 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1931 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1932 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1933 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1934 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1935 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1936 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1937 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1938 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1939 };
1940
1941 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1942 { "DAC1L", NULL, "DAC1L Mixer" },
1943 { "DAC1R", NULL, "DAC1R Mixer" },
1944 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1945 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1946 };
1947
1948 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1949 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1950 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1951 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1952 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1953 { "MICBIAS1", NULL, "CLK_SYS" },
1954 { "MICBIAS1", NULL, "MICBIAS Supply" },
1955 { "MICBIAS2", NULL, "CLK_SYS" },
1956 { "MICBIAS2", NULL, "MICBIAS Supply" },
1957 };
1958
1959 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1960 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1961 { "AIF2DACR", NULL, "AIF2DAC Mux" },
1962 { "MICBIAS1", NULL, "VMID" },
1963 { "MICBIAS2", NULL, "VMID" },
1964 };
1965
1966 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1967 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1968 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1969
1970 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1971 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1972 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1973 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1974
1975 { "AIF3DACDAT", NULL, "AIF3" },
1976 { "AIF3ADCDAT", NULL, "AIF3" },
1977
1978 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1979 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1980
1981 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1982 };
1983
1984 /* The size in bits of the FLL divide multiplied by 10
1985 * to allow rounding later */
1986 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1987
1988 struct fll_div {
1989 u16 outdiv;
1990 u16 n;
1991 u16 k;
1992 u16 clk_ref_div;
1993 u16 fll_fratio;
1994 };
1995
1996 static int wm8994_get_fll_config(struct fll_div *fll,
1997 int freq_in, int freq_out)
1998 {
1999 u64 Kpart;
2000 unsigned int K, Ndiv, Nmod;
2001
2002 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2003
2004 /* Scale the input frequency down to <= 13.5MHz */
2005 fll->clk_ref_div = 0;
2006 while (freq_in > 13500000) {
2007 fll->clk_ref_div++;
2008 freq_in /= 2;
2009
2010 if (fll->clk_ref_div > 3)
2011 return -EINVAL;
2012 }
2013 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2014
2015 /* Scale the output to give 90MHz<=Fvco<=100MHz */
2016 fll->outdiv = 3;
2017 while (freq_out * (fll->outdiv + 1) < 90000000) {
2018 fll->outdiv++;
2019 if (fll->outdiv > 63)
2020 return -EINVAL;
2021 }
2022 freq_out *= fll->outdiv + 1;
2023 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2024
2025 if (freq_in > 1000000) {
2026 fll->fll_fratio = 0;
2027 } else if (freq_in > 256000) {
2028 fll->fll_fratio = 1;
2029 freq_in *= 2;
2030 } else if (freq_in > 128000) {
2031 fll->fll_fratio = 2;
2032 freq_in *= 4;
2033 } else if (freq_in > 64000) {
2034 fll->fll_fratio = 3;
2035 freq_in *= 8;
2036 } else {
2037 fll->fll_fratio = 4;
2038 freq_in *= 16;
2039 }
2040 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2041
2042 /* Now, calculate N.K */
2043 Ndiv = freq_out / freq_in;
2044
2045 fll->n = Ndiv;
2046 Nmod = freq_out % freq_in;
2047 pr_debug("Nmod=%d\n", Nmod);
2048
2049 /* Calculate fractional part - scale up so we can round. */
2050 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
2051
2052 do_div(Kpart, freq_in);
2053
2054 K = Kpart & 0xFFFFFFFF;
2055
2056 if ((K % 10) >= 5)
2057 K += 5;
2058
2059 /* Move down to proper range now rounding is done */
2060 fll->k = K / 10;
2061
2062 pr_debug("N=%x K=%x\n", fll->n, fll->k);
2063
2064 return 0;
2065 }
2066
2067 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
2068 unsigned int freq_in, unsigned int freq_out)
2069 {
2070 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2071 struct wm8994 *control = wm8994->wm8994;
2072 int reg_offset, ret;
2073 struct fll_div fll;
2074 u16 reg, clk1, aif_reg, aif_src;
2075 unsigned long timeout;
2076 bool was_enabled;
2077
2078 switch (id) {
2079 case WM8994_FLL1:
2080 reg_offset = 0;
2081 id = 0;
2082 aif_src = 0x10;
2083 break;
2084 case WM8994_FLL2:
2085 reg_offset = 0x20;
2086 id = 1;
2087 aif_src = 0x18;
2088 break;
2089 default:
2090 return -EINVAL;
2091 }
2092
2093 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2094 was_enabled = reg & WM8994_FLL1_ENA;
2095
2096 switch (src) {
2097 case 0:
2098 /* Allow no source specification when stopping */
2099 if (freq_out)
2100 return -EINVAL;
2101 src = wm8994->fll[id].src;
2102 break;
2103 case WM8994_FLL_SRC_MCLK1:
2104 case WM8994_FLL_SRC_MCLK2:
2105 case WM8994_FLL_SRC_LRCLK:
2106 case WM8994_FLL_SRC_BCLK:
2107 break;
2108 default:
2109 return -EINVAL;
2110 }
2111
2112 /* Are we changing anything? */
2113 if (wm8994->fll[id].src == src &&
2114 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2115 return 0;
2116
2117 /* If we're stopping the FLL redo the old config - no
2118 * registers will actually be written but we avoid GCC flow
2119 * analysis bugs spewing warnings.
2120 */
2121 if (freq_out)
2122 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
2123 else
2124 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
2125 wm8994->fll[id].out);
2126 if (ret < 0)
2127 return ret;
2128
2129 /* Make sure that we're not providing SYSCLK right now */
2130 clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
2131 if (clk1 & WM8994_SYSCLK_SRC)
2132 aif_reg = WM8994_AIF2_CLOCKING_1;
2133 else
2134 aif_reg = WM8994_AIF1_CLOCKING_1;
2135 reg = snd_soc_read(codec, aif_reg);
2136
2137 if ((reg & WM8994_AIF1CLK_ENA) &&
2138 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2139 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
2140 id + 1);
2141 return -EBUSY;
2142 }
2143
2144 /* We always need to disable the FLL while reconfiguring */
2145 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2146 WM8994_FLL1_ENA, 0);
2147
2148 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
2149 freq_in == freq_out && freq_out) {
2150 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
2151 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2152 WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2153 goto out;
2154 }
2155
2156 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2157 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2158 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2159 WM8994_FLL1_OUTDIV_MASK |
2160 WM8994_FLL1_FRATIO_MASK, reg);
2161
2162 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
2163 WM8994_FLL1_K_MASK, fll.k);
2164
2165 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2166 WM8994_FLL1_N_MASK,
2167 fll.n << WM8994_FLL1_N_SHIFT);
2168
2169 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2170 WM8958_FLL1_BYP |
2171 WM8994_FLL1_REFCLK_DIV_MASK |
2172 WM8994_FLL1_REFCLK_SRC_MASK,
2173 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2174 (src - 1));
2175
2176 /* Clear any pending completion from a previous failure */
2177 try_wait_for_completion(&wm8994->fll_locked[id]);
2178
2179 /* Enable (with fractional mode if required) */
2180 if (freq_out) {
2181 /* Enable VMID if we need it */
2182 if (!was_enabled) {
2183 active_reference(codec);
2184
2185 switch (control->type) {
2186 case WM8994:
2187 vmid_reference(codec);
2188 break;
2189 case WM8958:
2190 if (wm8994->revision < 1)
2191 vmid_reference(codec);
2192 break;
2193 default:
2194 break;
2195 }
2196 }
2197
2198 if (fll.k)
2199 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
2200 else
2201 reg = WM8994_FLL1_ENA;
2202 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2203 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
2204 reg);
2205
2206 if (wm8994->fll_locked_irq) {
2207 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2208 msecs_to_jiffies(10));
2209 if (timeout == 0)
2210 dev_warn(codec->dev,
2211 "Timed out waiting for FLL lock\n");
2212 } else {
2213 msleep(5);
2214 }
2215 } else {
2216 if (was_enabled) {
2217 switch (control->type) {
2218 case WM8994:
2219 vmid_dereference(codec);
2220 break;
2221 case WM8958:
2222 if (wm8994->revision < 1)
2223 vmid_dereference(codec);
2224 break;
2225 default:
2226 break;
2227 }
2228
2229 active_dereference(codec);
2230 }
2231 }
2232
2233 out:
2234 wm8994->fll[id].in = freq_in;
2235 wm8994->fll[id].out = freq_out;
2236 wm8994->fll[id].src = src;
2237
2238 configure_clock(codec);
2239
2240 return 0;
2241 }
2242
2243 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2244 {
2245 struct completion *completion = data;
2246
2247 complete(completion);
2248
2249 return IRQ_HANDLED;
2250 }
2251
2252 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2253
2254 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2255 unsigned int freq_in, unsigned int freq_out)
2256 {
2257 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2258 }
2259
2260 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2261 int clk_id, unsigned int freq, int dir)
2262 {
2263 struct snd_soc_codec *codec = dai->codec;
2264 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2265 int i;
2266
2267 switch (dai->id) {
2268 case 1:
2269 case 2:
2270 break;
2271
2272 default:
2273 /* AIF3 shares clocking with AIF1/2 */
2274 return -EINVAL;
2275 }
2276
2277 switch (clk_id) {
2278 case WM8994_SYSCLK_MCLK1:
2279 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2280 wm8994->mclk[0] = freq;
2281 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2282 dai->id, freq);
2283 break;
2284
2285 case WM8994_SYSCLK_MCLK2:
2286 /* TODO: Set GPIO AF */
2287 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2288 wm8994->mclk[1] = freq;
2289 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2290 dai->id, freq);
2291 break;
2292
2293 case WM8994_SYSCLK_FLL1:
2294 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2295 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2296 break;
2297
2298 case WM8994_SYSCLK_FLL2:
2299 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2300 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2301 break;
2302
2303 case WM8994_SYSCLK_OPCLK:
2304 /* Special case - a division (times 10) is given and
2305 * no effect on main clocking.
2306 */
2307 if (freq) {
2308 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2309 if (opclk_divs[i] == freq)
2310 break;
2311 if (i == ARRAY_SIZE(opclk_divs))
2312 return -EINVAL;
2313 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2314 WM8994_OPCLK_DIV_MASK, i);
2315 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2316 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2317 } else {
2318 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2319 WM8994_OPCLK_ENA, 0);
2320 }
2321
2322 default:
2323 return -EINVAL;
2324 }
2325
2326 configure_clock(codec);
2327
2328 return 0;
2329 }
2330
2331 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2332 enum snd_soc_bias_level level)
2333 {
2334 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2335 struct wm8994 *control = wm8994->wm8994;
2336
2337 wm_hubs_set_bias_level(codec, level);
2338
2339 switch (level) {
2340 case SND_SOC_BIAS_ON:
2341 break;
2342
2343 case SND_SOC_BIAS_PREPARE:
2344 /* MICBIAS into regulating mode */
2345 switch (control->type) {
2346 case WM8958:
2347 case WM1811:
2348 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2349 WM8958_MICB1_MODE, 0);
2350 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2351 WM8958_MICB2_MODE, 0);
2352 break;
2353 default:
2354 break;
2355 }
2356
2357 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2358 active_reference(codec);
2359 break;
2360
2361 case SND_SOC_BIAS_STANDBY:
2362 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2363 switch (control->type) {
2364 case WM8958:
2365 if (wm8994->revision == 0) {
2366 /* Optimise performance for rev A */
2367 snd_soc_update_bits(codec,
2368 WM8958_CHARGE_PUMP_2,
2369 WM8958_CP_DISCH,
2370 WM8958_CP_DISCH);
2371 }
2372 break;
2373
2374 default:
2375 break;
2376 }
2377
2378 /* Discharge LINEOUT1 & 2 */
2379 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2380 WM8994_LINEOUT1_DISCH |
2381 WM8994_LINEOUT2_DISCH,
2382 WM8994_LINEOUT1_DISCH |
2383 WM8994_LINEOUT2_DISCH);
2384 }
2385
2386 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2387 active_dereference(codec);
2388
2389 /* MICBIAS into bypass mode on newer devices */
2390 switch (control->type) {
2391 case WM8958:
2392 case WM1811:
2393 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2394 WM8958_MICB1_MODE,
2395 WM8958_MICB1_MODE);
2396 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2397 WM8958_MICB2_MODE,
2398 WM8958_MICB2_MODE);
2399 break;
2400 default:
2401 break;
2402 }
2403 break;
2404
2405 case SND_SOC_BIAS_OFF:
2406 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2407 wm8994->cur_fw = NULL;
2408 break;
2409 }
2410
2411 codec->dapm.bias_level = level;
2412
2413 return 0;
2414 }
2415
2416 int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2417 {
2418 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2419
2420 switch (mode) {
2421 case WM8994_VMID_NORMAL:
2422 if (wm8994->hubs.lineout1_se) {
2423 snd_soc_dapm_disable_pin(&codec->dapm,
2424 "LINEOUT1N Driver");
2425 snd_soc_dapm_disable_pin(&codec->dapm,
2426 "LINEOUT1P Driver");
2427 }
2428 if (wm8994->hubs.lineout2_se) {
2429 snd_soc_dapm_disable_pin(&codec->dapm,
2430 "LINEOUT2N Driver");
2431 snd_soc_dapm_disable_pin(&codec->dapm,
2432 "LINEOUT2P Driver");
2433 }
2434
2435 /* Do the sync with the old mode to allow it to clean up */
2436 snd_soc_dapm_sync(&codec->dapm);
2437 wm8994->vmid_mode = mode;
2438 break;
2439
2440 case WM8994_VMID_FORCE:
2441 if (wm8994->hubs.lineout1_se) {
2442 snd_soc_dapm_force_enable_pin(&codec->dapm,
2443 "LINEOUT1N Driver");
2444 snd_soc_dapm_force_enable_pin(&codec->dapm,
2445 "LINEOUT1P Driver");
2446 }
2447 if (wm8994->hubs.lineout2_se) {
2448 snd_soc_dapm_force_enable_pin(&codec->dapm,
2449 "LINEOUT2N Driver");
2450 snd_soc_dapm_force_enable_pin(&codec->dapm,
2451 "LINEOUT2P Driver");
2452 }
2453
2454 wm8994->vmid_mode = mode;
2455 snd_soc_dapm_sync(&codec->dapm);
2456 break;
2457
2458 default:
2459 return -EINVAL;
2460 }
2461
2462 return 0;
2463 }
2464
2465 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2466 {
2467 struct snd_soc_codec *codec = dai->codec;
2468 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2469 struct wm8994 *control = wm8994->wm8994;
2470 int ms_reg;
2471 int aif1_reg;
2472 int ms = 0;
2473 int aif1 = 0;
2474
2475 switch (dai->id) {
2476 case 1:
2477 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2478 aif1_reg = WM8994_AIF1_CONTROL_1;
2479 break;
2480 case 2:
2481 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2482 aif1_reg = WM8994_AIF2_CONTROL_1;
2483 break;
2484 default:
2485 return -EINVAL;
2486 }
2487
2488 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2489 case SND_SOC_DAIFMT_CBS_CFS:
2490 break;
2491 case SND_SOC_DAIFMT_CBM_CFM:
2492 ms = WM8994_AIF1_MSTR;
2493 break;
2494 default:
2495 return -EINVAL;
2496 }
2497
2498 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2499 case SND_SOC_DAIFMT_DSP_B:
2500 aif1 |= WM8994_AIF1_LRCLK_INV;
2501 case SND_SOC_DAIFMT_DSP_A:
2502 aif1 |= 0x18;
2503 break;
2504 case SND_SOC_DAIFMT_I2S:
2505 aif1 |= 0x10;
2506 break;
2507 case SND_SOC_DAIFMT_RIGHT_J:
2508 break;
2509 case SND_SOC_DAIFMT_LEFT_J:
2510 aif1 |= 0x8;
2511 break;
2512 default:
2513 return -EINVAL;
2514 }
2515
2516 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2517 case SND_SOC_DAIFMT_DSP_A:
2518 case SND_SOC_DAIFMT_DSP_B:
2519 /* frame inversion not valid for DSP modes */
2520 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2521 case SND_SOC_DAIFMT_NB_NF:
2522 break;
2523 case SND_SOC_DAIFMT_IB_NF:
2524 aif1 |= WM8994_AIF1_BCLK_INV;
2525 break;
2526 default:
2527 return -EINVAL;
2528 }
2529 break;
2530
2531 case SND_SOC_DAIFMT_I2S:
2532 case SND_SOC_DAIFMT_RIGHT_J:
2533 case SND_SOC_DAIFMT_LEFT_J:
2534 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2535 case SND_SOC_DAIFMT_NB_NF:
2536 break;
2537 case SND_SOC_DAIFMT_IB_IF:
2538 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2539 break;
2540 case SND_SOC_DAIFMT_IB_NF:
2541 aif1 |= WM8994_AIF1_BCLK_INV;
2542 break;
2543 case SND_SOC_DAIFMT_NB_IF:
2544 aif1 |= WM8994_AIF1_LRCLK_INV;
2545 break;
2546 default:
2547 return -EINVAL;
2548 }
2549 break;
2550 default:
2551 return -EINVAL;
2552 }
2553
2554 /* The AIF2 format configuration needs to be mirrored to AIF3
2555 * on WM8958 if it's in use so just do it all the time. */
2556 switch (control->type) {
2557 case WM1811:
2558 case WM8958:
2559 if (dai->id == 2)
2560 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2561 WM8994_AIF1_LRCLK_INV |
2562 WM8958_AIF3_FMT_MASK, aif1);
2563 break;
2564
2565 default:
2566 break;
2567 }
2568
2569 snd_soc_update_bits(codec, aif1_reg,
2570 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2571 WM8994_AIF1_FMT_MASK,
2572 aif1);
2573 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2574 ms);
2575
2576 return 0;
2577 }
2578
2579 static struct {
2580 int val, rate;
2581 } srs[] = {
2582 { 0, 8000 },
2583 { 1, 11025 },
2584 { 2, 12000 },
2585 { 3, 16000 },
2586 { 4, 22050 },
2587 { 5, 24000 },
2588 { 6, 32000 },
2589 { 7, 44100 },
2590 { 8, 48000 },
2591 { 9, 88200 },
2592 { 10, 96000 },
2593 };
2594
2595 static int fs_ratios[] = {
2596 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2597 };
2598
2599 static int bclk_divs[] = {
2600 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2601 640, 880, 960, 1280, 1760, 1920
2602 };
2603
2604 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2605 struct snd_pcm_hw_params *params,
2606 struct snd_soc_dai *dai)
2607 {
2608 struct snd_soc_codec *codec = dai->codec;
2609 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2610 int aif1_reg;
2611 int aif2_reg;
2612 int bclk_reg;
2613 int lrclk_reg;
2614 int rate_reg;
2615 int aif1 = 0;
2616 int aif2 = 0;
2617 int bclk = 0;
2618 int lrclk = 0;
2619 int rate_val = 0;
2620 int id = dai->id - 1;
2621
2622 int i, cur_val, best_val, bclk_rate, best;
2623
2624 switch (dai->id) {
2625 case 1:
2626 aif1_reg = WM8994_AIF1_CONTROL_1;
2627 aif2_reg = WM8994_AIF1_CONTROL_2;
2628 bclk_reg = WM8994_AIF1_BCLK;
2629 rate_reg = WM8994_AIF1_RATE;
2630 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2631 wm8994->lrclk_shared[0]) {
2632 lrclk_reg = WM8994_AIF1DAC_LRCLK;
2633 } else {
2634 lrclk_reg = WM8994_AIF1ADC_LRCLK;
2635 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2636 }
2637 break;
2638 case 2:
2639 aif1_reg = WM8994_AIF2_CONTROL_1;
2640 aif2_reg = WM8994_AIF2_CONTROL_2;
2641 bclk_reg = WM8994_AIF2_BCLK;
2642 rate_reg = WM8994_AIF2_RATE;
2643 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2644 wm8994->lrclk_shared[1]) {
2645 lrclk_reg = WM8994_AIF2DAC_LRCLK;
2646 } else {
2647 lrclk_reg = WM8994_AIF2ADC_LRCLK;
2648 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2649 }
2650 break;
2651 default:
2652 return -EINVAL;
2653 }
2654
2655 bclk_rate = params_rate(params) * 2;
2656 switch (params_format(params)) {
2657 case SNDRV_PCM_FORMAT_S16_LE:
2658 bclk_rate *= 16;
2659 break;
2660 case SNDRV_PCM_FORMAT_S20_3LE:
2661 bclk_rate *= 20;
2662 aif1 |= 0x20;
2663 break;
2664 case SNDRV_PCM_FORMAT_S24_LE:
2665 bclk_rate *= 24;
2666 aif1 |= 0x40;
2667 break;
2668 case SNDRV_PCM_FORMAT_S32_LE:
2669 bclk_rate *= 32;
2670 aif1 |= 0x60;
2671 break;
2672 default:
2673 return -EINVAL;
2674 }
2675
2676 /* Try to find an appropriate sample rate; look for an exact match. */
2677 for (i = 0; i < ARRAY_SIZE(srs); i++)
2678 if (srs[i].rate == params_rate(params))
2679 break;
2680 if (i == ARRAY_SIZE(srs))
2681 return -EINVAL;
2682 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2683
2684 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2685 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2686 dai->id, wm8994->aifclk[id], bclk_rate);
2687
2688 if (params_channels(params) == 1 &&
2689 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2690 aif2 |= WM8994_AIF1_MONO;
2691
2692 if (wm8994->aifclk[id] == 0) {
2693 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2694 return -EINVAL;
2695 }
2696
2697 /* AIFCLK/fs ratio; look for a close match in either direction */
2698 best = 0;
2699 best_val = abs((fs_ratios[0] * params_rate(params))
2700 - wm8994->aifclk[id]);
2701 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2702 cur_val = abs((fs_ratios[i] * params_rate(params))
2703 - wm8994->aifclk[id]);
2704 if (cur_val >= best_val)
2705 continue;
2706 best = i;
2707 best_val = cur_val;
2708 }
2709 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2710 dai->id, fs_ratios[best]);
2711 rate_val |= best;
2712
2713 /* We may not get quite the right frequency if using
2714 * approximate clocks so look for the closest match that is
2715 * higher than the target (we need to ensure that there enough
2716 * BCLKs to clock out the samples).
2717 */
2718 best = 0;
2719 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2720 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2721 if (cur_val < 0) /* BCLK table is sorted */
2722 break;
2723 best = i;
2724 }
2725 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2726 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2727 bclk_divs[best], bclk_rate);
2728 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2729
2730 lrclk = bclk_rate / params_rate(params);
2731 if (!lrclk) {
2732 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2733 bclk_rate);
2734 return -EINVAL;
2735 }
2736 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2737 lrclk, bclk_rate / lrclk);
2738
2739 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2740 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2741 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2742 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2743 lrclk);
2744 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2745 WM8994_AIF1CLK_RATE_MASK, rate_val);
2746
2747 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2748 switch (dai->id) {
2749 case 1:
2750 wm8994->dac_rates[0] = params_rate(params);
2751 wm8994_set_retune_mobile(codec, 0);
2752 wm8994_set_retune_mobile(codec, 1);
2753 break;
2754 case 2:
2755 wm8994->dac_rates[1] = params_rate(params);
2756 wm8994_set_retune_mobile(codec, 2);
2757 break;
2758 }
2759 }
2760
2761 return 0;
2762 }
2763
2764 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2765 struct snd_pcm_hw_params *params,
2766 struct snd_soc_dai *dai)
2767 {
2768 struct snd_soc_codec *codec = dai->codec;
2769 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2770 struct wm8994 *control = wm8994->wm8994;
2771 int aif1_reg;
2772 int aif1 = 0;
2773
2774 switch (dai->id) {
2775 case 3:
2776 switch (control->type) {
2777 case WM1811:
2778 case WM8958:
2779 aif1_reg = WM8958_AIF3_CONTROL_1;
2780 break;
2781 default:
2782 return 0;
2783 }
2784 default:
2785 return 0;
2786 }
2787
2788 switch (params_format(params)) {
2789 case SNDRV_PCM_FORMAT_S16_LE:
2790 break;
2791 case SNDRV_PCM_FORMAT_S20_3LE:
2792 aif1 |= 0x20;
2793 break;
2794 case SNDRV_PCM_FORMAT_S24_LE:
2795 aif1 |= 0x40;
2796 break;
2797 case SNDRV_PCM_FORMAT_S32_LE:
2798 aif1 |= 0x60;
2799 break;
2800 default:
2801 return -EINVAL;
2802 }
2803
2804 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2805 }
2806
2807 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2808 {
2809 struct snd_soc_codec *codec = codec_dai->codec;
2810 int mute_reg;
2811 int reg;
2812
2813 switch (codec_dai->id) {
2814 case 1:
2815 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2816 break;
2817 case 2:
2818 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2819 break;
2820 default:
2821 return -EINVAL;
2822 }
2823
2824 if (mute)
2825 reg = WM8994_AIF1DAC1_MUTE;
2826 else
2827 reg = 0;
2828
2829 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2830
2831 return 0;
2832 }
2833
2834 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2835 {
2836 struct snd_soc_codec *codec = codec_dai->codec;
2837 int reg, val, mask;
2838
2839 switch (codec_dai->id) {
2840 case 1:
2841 reg = WM8994_AIF1_MASTER_SLAVE;
2842 mask = WM8994_AIF1_TRI;
2843 break;
2844 case 2:
2845 reg = WM8994_AIF2_MASTER_SLAVE;
2846 mask = WM8994_AIF2_TRI;
2847 break;
2848 default:
2849 return -EINVAL;
2850 }
2851
2852 if (tristate)
2853 val = mask;
2854 else
2855 val = 0;
2856
2857 return snd_soc_update_bits(codec, reg, mask, val);
2858 }
2859
2860 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2861 {
2862 struct snd_soc_codec *codec = dai->codec;
2863
2864 /* Disable the pulls on the AIF if we're using it to save power. */
2865 snd_soc_update_bits(codec, WM8994_GPIO_3,
2866 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2867 snd_soc_update_bits(codec, WM8994_GPIO_4,
2868 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2869 snd_soc_update_bits(codec, WM8994_GPIO_5,
2870 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2871
2872 return 0;
2873 }
2874
2875 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2876
2877 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2878 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2879
2880 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2881 .set_sysclk = wm8994_set_dai_sysclk,
2882 .set_fmt = wm8994_set_dai_fmt,
2883 .hw_params = wm8994_hw_params,
2884 .digital_mute = wm8994_aif_mute,
2885 .set_pll = wm8994_set_fll,
2886 .set_tristate = wm8994_set_tristate,
2887 };
2888
2889 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2890 .set_sysclk = wm8994_set_dai_sysclk,
2891 .set_fmt = wm8994_set_dai_fmt,
2892 .hw_params = wm8994_hw_params,
2893 .digital_mute = wm8994_aif_mute,
2894 .set_pll = wm8994_set_fll,
2895 .set_tristate = wm8994_set_tristate,
2896 };
2897
2898 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2899 .hw_params = wm8994_aif3_hw_params,
2900 };
2901
2902 static struct snd_soc_dai_driver wm8994_dai[] = {
2903 {
2904 .name = "wm8994-aif1",
2905 .id = 1,
2906 .playback = {
2907 .stream_name = "AIF1 Playback",
2908 .channels_min = 1,
2909 .channels_max = 2,
2910 .rates = WM8994_RATES,
2911 .formats = WM8994_FORMATS,
2912 .sig_bits = 24,
2913 },
2914 .capture = {
2915 .stream_name = "AIF1 Capture",
2916 .channels_min = 1,
2917 .channels_max = 2,
2918 .rates = WM8994_RATES,
2919 .formats = WM8994_FORMATS,
2920 .sig_bits = 24,
2921 },
2922 .ops = &wm8994_aif1_dai_ops,
2923 },
2924 {
2925 .name = "wm8994-aif2",
2926 .id = 2,
2927 .playback = {
2928 .stream_name = "AIF2 Playback",
2929 .channels_min = 1,
2930 .channels_max = 2,
2931 .rates = WM8994_RATES,
2932 .formats = WM8994_FORMATS,
2933 .sig_bits = 24,
2934 },
2935 .capture = {
2936 .stream_name = "AIF2 Capture",
2937 .channels_min = 1,
2938 .channels_max = 2,
2939 .rates = WM8994_RATES,
2940 .formats = WM8994_FORMATS,
2941 .sig_bits = 24,
2942 },
2943 .probe = wm8994_aif2_probe,
2944 .ops = &wm8994_aif2_dai_ops,
2945 },
2946 {
2947 .name = "wm8994-aif3",
2948 .id = 3,
2949 .playback = {
2950 .stream_name = "AIF3 Playback",
2951 .channels_min = 1,
2952 .channels_max = 2,
2953 .rates = WM8994_RATES,
2954 .formats = WM8994_FORMATS,
2955 .sig_bits = 24,
2956 },
2957 .capture = {
2958 .stream_name = "AIF3 Capture",
2959 .channels_min = 1,
2960 .channels_max = 2,
2961 .rates = WM8994_RATES,
2962 .formats = WM8994_FORMATS,
2963 .sig_bits = 24,
2964 },
2965 .ops = &wm8994_aif3_dai_ops,
2966 }
2967 };
2968
2969 #ifdef CONFIG_PM
2970 static int wm8994_codec_suspend(struct snd_soc_codec *codec)
2971 {
2972 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2973 struct wm8994 *control = wm8994->wm8994;
2974 int i, ret;
2975
2976 switch (control->type) {
2977 case WM8994:
2978 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2979 break;
2980 case WM1811:
2981 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2982 WM1811_JACKDET_MODE_MASK, 0);
2983 /* Fall through */
2984 case WM8958:
2985 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2986 WM8958_MICD_ENA, 0);
2987 break;
2988 }
2989
2990 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2991 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2992 sizeof(struct wm8994_fll_config));
2993 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2994 if (ret < 0)
2995 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2996 i + 1, ret);
2997 }
2998
2999 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3000
3001 return 0;
3002 }
3003
3004 static int wm8994_codec_resume(struct snd_soc_codec *codec)
3005 {
3006 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3007 struct wm8994 *control = wm8994->wm8994;
3008 int i, ret;
3009 unsigned int val, mask;
3010
3011 if (wm8994->revision < 4) {
3012 /* force a HW read */
3013 ret = regmap_read(control->regmap,
3014 WM8994_POWER_MANAGEMENT_5, &val);
3015
3016 /* modify the cache only */
3017 codec->cache_only = 1;
3018 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
3019 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
3020 val &= mask;
3021 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
3022 mask, val);
3023 codec->cache_only = 0;
3024 }
3025
3026 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3027 if (!wm8994->fll_suspend[i].out)
3028 continue;
3029
3030 ret = _wm8994_set_fll(codec, i + 1,
3031 wm8994->fll_suspend[i].src,
3032 wm8994->fll_suspend[i].in,
3033 wm8994->fll_suspend[i].out);
3034 if (ret < 0)
3035 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
3036 i + 1, ret);
3037 }
3038
3039 switch (control->type) {
3040 case WM8994:
3041 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3042 snd_soc_update_bits(codec, WM8994_MICBIAS,
3043 WM8994_MICD_ENA, WM8994_MICD_ENA);
3044 break;
3045 case WM1811:
3046 if (wm8994->jackdet && wm8994->jack_cb) {
3047 /* Restart from idle */
3048 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
3049 WM1811_JACKDET_MODE_MASK,
3050 WM1811_JACKDET_MODE_JACK);
3051 break;
3052 }
3053 break;
3054 case WM8958:
3055 if (wm8994->jack_cb)
3056 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3057 WM8958_MICD_ENA, WM8958_MICD_ENA);
3058 break;
3059 }
3060
3061 return 0;
3062 }
3063 #else
3064 #define wm8994_codec_suspend NULL
3065 #define wm8994_codec_resume NULL
3066 #endif
3067
3068 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3069 {
3070 struct snd_soc_codec *codec = wm8994->codec;
3071 struct wm8994_pdata *pdata = wm8994->pdata;
3072 struct snd_kcontrol_new controls[] = {
3073 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3074 wm8994->retune_mobile_enum,
3075 wm8994_get_retune_mobile_enum,
3076 wm8994_put_retune_mobile_enum),
3077 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3078 wm8994->retune_mobile_enum,
3079 wm8994_get_retune_mobile_enum,
3080 wm8994_put_retune_mobile_enum),
3081 SOC_ENUM_EXT("AIF2 EQ Mode",
3082 wm8994->retune_mobile_enum,
3083 wm8994_get_retune_mobile_enum,
3084 wm8994_put_retune_mobile_enum),
3085 };
3086 int ret, i, j;
3087 const char **t;
3088
3089 /* We need an array of texts for the enum API but the number
3090 * of texts is likely to be less than the number of
3091 * configurations due to the sample rate dependency of the
3092 * configurations. */
3093 wm8994->num_retune_mobile_texts = 0;
3094 wm8994->retune_mobile_texts = NULL;
3095 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3096 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3097 if (strcmp(pdata->retune_mobile_cfgs[i].name,
3098 wm8994->retune_mobile_texts[j]) == 0)
3099 break;
3100 }
3101
3102 if (j != wm8994->num_retune_mobile_texts)
3103 continue;
3104
3105 /* Expand the array... */
3106 t = krealloc(wm8994->retune_mobile_texts,
3107 sizeof(char *) *
3108 (wm8994->num_retune_mobile_texts + 1),
3109 GFP_KERNEL);
3110 if (t == NULL)
3111 continue;
3112
3113 /* ...store the new entry... */
3114 t[wm8994->num_retune_mobile_texts] =
3115 pdata->retune_mobile_cfgs[i].name;
3116
3117 /* ...and remember the new version. */
3118 wm8994->num_retune_mobile_texts++;
3119 wm8994->retune_mobile_texts = t;
3120 }
3121
3122 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3123 wm8994->num_retune_mobile_texts);
3124
3125 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
3126 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3127
3128 ret = snd_soc_add_codec_controls(wm8994->codec, controls,
3129 ARRAY_SIZE(controls));
3130 if (ret != 0)
3131 dev_err(wm8994->codec->dev,
3132 "Failed to add ReTune Mobile controls: %d\n", ret);
3133 }
3134
3135 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3136 {
3137 struct snd_soc_codec *codec = wm8994->codec;
3138 struct wm8994_pdata *pdata = wm8994->pdata;
3139 int ret, i;
3140
3141 if (!pdata)
3142 return;
3143
3144 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3145 pdata->lineout2_diff,
3146 pdata->lineout1fb,
3147 pdata->lineout2fb,
3148 pdata->jd_scthr,
3149 pdata->jd_thr,
3150 pdata->micbias1_lvl,
3151 pdata->micbias2_lvl);
3152
3153 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3154
3155 if (pdata->num_drc_cfgs) {
3156 struct snd_kcontrol_new controls[] = {
3157 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3158 wm8994_get_drc_enum, wm8994_put_drc_enum),
3159 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3160 wm8994_get_drc_enum, wm8994_put_drc_enum),
3161 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3162 wm8994_get_drc_enum, wm8994_put_drc_enum),
3163 };
3164
3165 /* We need an array of texts for the enum API */
3166 wm8994->drc_texts = devm_kzalloc(wm8994->codec->dev,
3167 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
3168 if (!wm8994->drc_texts) {
3169 dev_err(wm8994->codec->dev,
3170 "Failed to allocate %d DRC config texts\n",
3171 pdata->num_drc_cfgs);
3172 return;
3173 }
3174
3175 for (i = 0; i < pdata->num_drc_cfgs; i++)
3176 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3177
3178 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3179 wm8994->drc_enum.texts = wm8994->drc_texts;
3180
3181 ret = snd_soc_add_codec_controls(wm8994->codec, controls,
3182 ARRAY_SIZE(controls));
3183 if (ret != 0)
3184 dev_err(wm8994->codec->dev,
3185 "Failed to add DRC mode controls: %d\n", ret);
3186
3187 for (i = 0; i < WM8994_NUM_DRC; i++)
3188 wm8994_set_drc(codec, i);
3189 }
3190
3191 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3192 pdata->num_retune_mobile_cfgs);
3193
3194 if (pdata->num_retune_mobile_cfgs)
3195 wm8994_handle_retune_mobile_pdata(wm8994);
3196 else
3197 snd_soc_add_codec_controls(wm8994->codec, wm8994_eq_controls,
3198 ARRAY_SIZE(wm8994_eq_controls));
3199
3200 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3201 if (pdata->micbias[i]) {
3202 snd_soc_write(codec, WM8958_MICBIAS1 + i,
3203 pdata->micbias[i] & 0xffff);
3204 }
3205 }
3206 }
3207
3208 /**
3209 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3210 *
3211 * @codec: WM8994 codec
3212 * @jack: jack to report detection events on
3213 * @micbias: microphone bias to detect on
3214 *
3215 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3216 * being used to bring out signals to the processor then only platform
3217 * data configuration is needed for WM8994 and processor GPIOs should
3218 * be configured using snd_soc_jack_add_gpios() instead.
3219 *
3220 * Configuration of detection levels is available via the micbias1_lvl
3221 * and micbias2_lvl platform data members.
3222 */
3223 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3224 int micbias)
3225 {
3226 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3227 struct wm8994_micdet *micdet;
3228 struct wm8994 *control = wm8994->wm8994;
3229 int reg, ret;
3230
3231 if (control->type != WM8994) {
3232 dev_warn(codec->dev, "Not a WM8994\n");
3233 return -EINVAL;
3234 }
3235
3236 switch (micbias) {
3237 case 1:
3238 micdet = &wm8994->micdet[0];
3239 if (jack)
3240 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3241 "MICBIAS1");
3242 else
3243 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3244 "MICBIAS1");
3245 break;
3246 case 2:
3247 micdet = &wm8994->micdet[1];
3248 if (jack)
3249 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3250 "MICBIAS1");
3251 else
3252 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3253 "MICBIAS1");
3254 break;
3255 default:
3256 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
3257 return -EINVAL;
3258 }
3259
3260 if (ret != 0)
3261 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3262 micbias, ret);
3263
3264 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3265 micbias, jack);
3266
3267 /* Store the configuration */
3268 micdet->jack = jack;
3269 micdet->detecting = true;
3270
3271 /* If either of the jacks is set up then enable detection */
3272 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3273 reg = WM8994_MICD_ENA;
3274 else
3275 reg = 0;
3276
3277 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3278
3279 snd_soc_dapm_sync(&codec->dapm);
3280
3281 return 0;
3282 }
3283 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3284
3285 static void wm8994_mic_work(struct work_struct *work)
3286 {
3287 struct wm8994_priv *priv = container_of(work,
3288 struct wm8994_priv,
3289 mic_work.work);
3290 struct regmap *regmap = priv->wm8994->regmap;
3291 struct device *dev = priv->wm8994->dev;
3292 unsigned int reg;
3293 int ret;
3294 int report;
3295
3296 ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, &reg);
3297 if (ret < 0) {
3298 dev_err(dev, "Failed to read microphone status: %d\n",
3299 ret);
3300 return;
3301 }
3302
3303 dev_dbg(dev, "Microphone status: %x\n", reg);
3304
3305 report = 0;
3306 if (reg & WM8994_MIC1_DET_STS) {
3307 if (priv->micdet[0].detecting)
3308 report = SND_JACK_HEADSET;
3309 }
3310 if (reg & WM8994_MIC1_SHRT_STS) {
3311 if (priv->micdet[0].detecting)
3312 report = SND_JACK_HEADPHONE;
3313 else
3314 report |= SND_JACK_BTN_0;
3315 }
3316 if (report)
3317 priv->micdet[0].detecting = false;
3318 else
3319 priv->micdet[0].detecting = true;
3320
3321 snd_soc_jack_report(priv->micdet[0].jack, report,
3322 SND_JACK_HEADSET | SND_JACK_BTN_0);
3323
3324 report = 0;
3325 if (reg & WM8994_MIC2_DET_STS) {
3326 if (priv->micdet[1].detecting)
3327 report = SND_JACK_HEADSET;
3328 }
3329 if (reg & WM8994_MIC2_SHRT_STS) {
3330 if (priv->micdet[1].detecting)
3331 report = SND_JACK_HEADPHONE;
3332 else
3333 report |= SND_JACK_BTN_0;
3334 }
3335 if (report)
3336 priv->micdet[1].detecting = false;
3337 else
3338 priv->micdet[1].detecting = true;
3339
3340 snd_soc_jack_report(priv->micdet[1].jack, report,
3341 SND_JACK_HEADSET | SND_JACK_BTN_0);
3342 }
3343
3344 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3345 {
3346 struct wm8994_priv *priv = data;
3347 struct snd_soc_codec *codec = priv->codec;
3348
3349 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3350 trace_snd_soc_jack_irq(dev_name(codec->dev));
3351 #endif
3352
3353 pm_wakeup_event(codec->dev, 300);
3354
3355 schedule_delayed_work(&priv->mic_work, msecs_to_jiffies(250));
3356
3357 return IRQ_HANDLED;
3358 }
3359
3360 /* Default microphone detection handler for WM8958 - the user can
3361 * override this if they wish.
3362 */
3363 static void wm8958_default_micdet(u16 status, void *data)
3364 {
3365 struct snd_soc_codec *codec = data;
3366 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3367 int report;
3368
3369 dev_dbg(codec->dev, "MICDET %x\n", status);
3370
3371 /* Either nothing present or just starting detection */
3372 if (!(status & WM8958_MICD_STS)) {
3373 if (!wm8994->jackdet) {
3374 /* If nothing present then clear our statuses */
3375 dev_dbg(codec->dev, "Detected open circuit\n");
3376 wm8994->jack_mic = false;
3377 wm8994->mic_detecting = true;
3378
3379 wm8958_micd_set_rate(codec);
3380
3381 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3382 wm8994->btn_mask |
3383 SND_JACK_HEADSET);
3384 }
3385 return;
3386 }
3387
3388 /* If the measurement is showing a high impedence we've got a
3389 * microphone.
3390 */
3391 if (wm8994->mic_detecting && (status & 0x600)) {
3392 dev_dbg(codec->dev, "Detected microphone\n");
3393
3394 wm8994->mic_detecting = false;
3395 wm8994->jack_mic = true;
3396
3397 wm8958_micd_set_rate(codec);
3398
3399 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3400 SND_JACK_HEADSET);
3401 }
3402
3403
3404 if (wm8994->mic_detecting && status & 0xfc) {
3405 dev_dbg(codec->dev, "Detected headphone\n");
3406 wm8994->mic_detecting = false;
3407
3408 wm8958_micd_set_rate(codec);
3409
3410 /* If we have jackdet that will detect removal */
3411 if (wm8994->jackdet) {
3412 mutex_lock(&wm8994->accdet_lock);
3413
3414 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3415 WM8958_MICD_ENA, 0);
3416
3417 wm1811_jackdet_set_mode(codec,
3418 WM1811_JACKDET_MODE_JACK);
3419
3420 mutex_unlock(&wm8994->accdet_lock);
3421
3422 if (wm8994->pdata->jd_ext_cap)
3423 snd_soc_dapm_disable_pin(&codec->dapm,
3424 "MICBIAS2");
3425 }
3426
3427 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3428 SND_JACK_HEADSET);
3429 }
3430
3431 /* Report short circuit as a button */
3432 if (wm8994->jack_mic) {
3433 report = 0;
3434 if (status & 0x4)
3435 report |= SND_JACK_BTN_0;
3436
3437 if (status & 0x8)
3438 report |= SND_JACK_BTN_1;
3439
3440 if (status & 0x10)
3441 report |= SND_JACK_BTN_2;
3442
3443 if (status & 0x20)
3444 report |= SND_JACK_BTN_3;
3445
3446 if (status & 0x40)
3447 report |= SND_JACK_BTN_4;
3448
3449 if (status & 0x80)
3450 report |= SND_JACK_BTN_5;
3451
3452 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3453 wm8994->btn_mask);
3454 }
3455 }
3456
3457 static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3458 {
3459 struct wm8994_priv *wm8994 = data;
3460 struct snd_soc_codec *codec = wm8994->codec;
3461 int reg;
3462 bool present;
3463
3464 mutex_lock(&wm8994->accdet_lock);
3465
3466 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3467 if (reg < 0) {
3468 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3469 mutex_unlock(&wm8994->accdet_lock);
3470 return IRQ_NONE;
3471 }
3472
3473 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3474
3475 present = reg & WM1811_JACKDET_LVL;
3476
3477 if (present) {
3478 dev_dbg(codec->dev, "Jack detected\n");
3479
3480 wm8958_micd_set_rate(codec);
3481
3482 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3483 WM8958_MICB2_DISCH, 0);
3484
3485 /* Disable debounce while inserted */
3486 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3487 WM1811_JACKDET_DB, 0);
3488
3489 /*
3490 * Start off measument of microphone impedence to find
3491 * out what's actually there.
3492 */
3493 wm8994->mic_detecting = true;
3494 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3495
3496 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3497 WM8958_MICD_ENA, WM8958_MICD_ENA);
3498 } else {
3499 dev_dbg(codec->dev, "Jack not detected\n");
3500
3501 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3502 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3503
3504 /* Enable debounce while removed */
3505 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3506 WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3507
3508 wm8994->mic_detecting = false;
3509 wm8994->jack_mic = false;
3510 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3511 WM8958_MICD_ENA, 0);
3512 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3513 }
3514
3515 mutex_unlock(&wm8994->accdet_lock);
3516
3517 /* If required for an external cap force MICBIAS on */
3518 if (wm8994->pdata->jd_ext_cap) {
3519 if (present)
3520 snd_soc_dapm_force_enable_pin(&codec->dapm,
3521 "MICBIAS2");
3522 else
3523 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
3524 }
3525
3526 if (present)
3527 snd_soc_jack_report(wm8994->micdet[0].jack,
3528 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3529 else
3530 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3531 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3532 wm8994->btn_mask);
3533
3534 return IRQ_HANDLED;
3535 }
3536
3537 /**
3538 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3539 *
3540 * @codec: WM8958 codec
3541 * @jack: jack to report detection events on
3542 *
3543 * Enable microphone detection functionality for the WM8958. By
3544 * default simple detection which supports the detection of up to 6
3545 * buttons plus video and microphone functionality is supported.
3546 *
3547 * The WM8958 has an advanced jack detection facility which is able to
3548 * support complex accessory detection, especially when used in
3549 * conjunction with external circuitry. In order to provide maximum
3550 * flexiblity a callback is provided which allows a completely custom
3551 * detection algorithm.
3552 */
3553 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3554 wm8958_micdet_cb cb, void *cb_data)
3555 {
3556 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3557 struct wm8994 *control = wm8994->wm8994;
3558 u16 micd_lvl_sel;
3559
3560 switch (control->type) {
3561 case WM1811:
3562 case WM8958:
3563 break;
3564 default:
3565 return -EINVAL;
3566 }
3567
3568 if (jack) {
3569 if (!cb) {
3570 dev_dbg(codec->dev, "Using default micdet callback\n");
3571 cb = wm8958_default_micdet;
3572 cb_data = codec;
3573 }
3574
3575 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3576 snd_soc_dapm_sync(&codec->dapm);
3577
3578 wm8994->micdet[0].jack = jack;
3579 wm8994->jack_cb = cb;
3580 wm8994->jack_cb_data = cb_data;
3581
3582 wm8994->mic_detecting = true;
3583 wm8994->jack_mic = false;
3584
3585 wm8958_micd_set_rate(codec);
3586
3587 /* Detect microphones and short circuits by default */
3588 if (wm8994->pdata->micd_lvl_sel)
3589 micd_lvl_sel = wm8994->pdata->micd_lvl_sel;
3590 else
3591 micd_lvl_sel = 0x41;
3592
3593 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3594 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3595 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3596
3597 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
3598 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3599
3600 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3601
3602 /*
3603 * If we can use jack detection start off with that,
3604 * otherwise jump straight to microphone detection.
3605 */
3606 if (wm8994->jackdet) {
3607 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3608 WM8958_MICB2_DISCH,
3609 WM8958_MICB2_DISCH);
3610 snd_soc_update_bits(codec, WM8994_LDO_1,
3611 WM8994_LDO1_DISCH, 0);
3612 wm1811_jackdet_set_mode(codec,
3613 WM1811_JACKDET_MODE_JACK);
3614 } else {
3615 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3616 WM8958_MICD_ENA, WM8958_MICD_ENA);
3617 }
3618
3619 } else {
3620 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3621 WM8958_MICD_ENA, 0);
3622 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
3623 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
3624 snd_soc_dapm_sync(&codec->dapm);
3625 }
3626
3627 return 0;
3628 }
3629 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3630
3631 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3632 {
3633 struct wm8994_priv *wm8994 = data;
3634 struct snd_soc_codec *codec = wm8994->codec;
3635 int reg, count;
3636
3637 /*
3638 * Jack detection may have detected a removal simulataneously
3639 * with an update of the MICDET status; if so it will have
3640 * stopped detection and we can ignore this interrupt.
3641 */
3642 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
3643 return IRQ_HANDLED;
3644
3645 /* We may occasionally read a detection without an impedence
3646 * range being provided - if that happens loop again.
3647 */
3648 count = 10;
3649 do {
3650 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3651 if (reg < 0) {
3652 dev_err(codec->dev,
3653 "Failed to read mic detect status: %d\n",
3654 reg);
3655 return IRQ_NONE;
3656 }
3657
3658 if (!(reg & WM8958_MICD_VALID)) {
3659 dev_dbg(codec->dev, "Mic detect data not valid\n");
3660 goto out;
3661 }
3662
3663 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3664 break;
3665
3666 msleep(1);
3667 } while (count--);
3668
3669 if (count == 0)
3670 dev_warn(codec->dev, "No impedence range reported for jack\n");
3671
3672 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3673 trace_snd_soc_jack_irq(dev_name(codec->dev));
3674 #endif
3675
3676 if (wm8994->jack_cb)
3677 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3678 else
3679 dev_warn(codec->dev, "Accessory detection with no callback\n");
3680
3681 out:
3682 return IRQ_HANDLED;
3683 }
3684
3685 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3686 {
3687 struct snd_soc_codec *codec = data;
3688
3689 dev_err(codec->dev, "FIFO error\n");
3690
3691 return IRQ_HANDLED;
3692 }
3693
3694 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3695 {
3696 struct snd_soc_codec *codec = data;
3697
3698 dev_err(codec->dev, "Thermal warning\n");
3699
3700 return IRQ_HANDLED;
3701 }
3702
3703 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3704 {
3705 struct snd_soc_codec *codec = data;
3706
3707 dev_crit(codec->dev, "Thermal shutdown\n");
3708
3709 return IRQ_HANDLED;
3710 }
3711
3712 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3713 {
3714 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
3715 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3716 struct snd_soc_dapm_context *dapm = &codec->dapm;
3717 unsigned int reg;
3718 int ret, i;
3719
3720 wm8994->codec = codec;
3721 codec->control_data = control->regmap;
3722
3723 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
3724
3725 wm8994->codec = codec;
3726
3727 mutex_init(&wm8994->accdet_lock);
3728 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
3729
3730 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3731 init_completion(&wm8994->fll_locked[i]);
3732
3733 if (wm8994->pdata && wm8994->pdata->micdet_irq)
3734 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3735 else if (wm8994->pdata && wm8994->pdata->irq_base)
3736 wm8994->micdet_irq = wm8994->pdata->irq_base +
3737 WM8994_IRQ_MIC1_DET;
3738
3739 pm_runtime_enable(codec->dev);
3740 pm_runtime_idle(codec->dev);
3741
3742 /* By default use idle_bias_off, will override for WM8994 */
3743 codec->dapm.idle_bias_off = 1;
3744
3745 /* Set revision-specific configuration */
3746 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3747 switch (control->type) {
3748 case WM8994:
3749 /* Single ended line outputs should have VMID on. */
3750 if (!wm8994->pdata->lineout1_diff ||
3751 !wm8994->pdata->lineout2_diff)
3752 codec->dapm.idle_bias_off = 0;
3753
3754 switch (wm8994->revision) {
3755 case 2:
3756 case 3:
3757 wm8994->hubs.dcs_codes_l = -5;
3758 wm8994->hubs.dcs_codes_r = -5;
3759 wm8994->hubs.hp_startup_mode = 1;
3760 wm8994->hubs.dcs_readback_mode = 1;
3761 wm8994->hubs.series_startup = 1;
3762 break;
3763 default:
3764 wm8994->hubs.dcs_readback_mode = 2;
3765 break;
3766 }
3767 break;
3768
3769 case WM8958:
3770 wm8994->hubs.dcs_readback_mode = 1;
3771 wm8994->hubs.hp_startup_mode = 1;
3772
3773 switch (wm8994->revision) {
3774 case 0:
3775 break;
3776 default:
3777 wm8994->fll_byp = true;
3778 break;
3779 }
3780 break;
3781
3782 case WM1811:
3783 wm8994->hubs.dcs_readback_mode = 2;
3784 wm8994->hubs.no_series_update = 1;
3785 wm8994->hubs.hp_startup_mode = 1;
3786 wm8994->hubs.no_cache_dac_hp_direct = true;
3787 wm8994->fll_byp = true;
3788
3789 switch (wm8994->revision) {
3790 case 0:
3791 case 1:
3792 case 2:
3793 case 3:
3794 wm8994->hubs.dcs_codes_l = -9;
3795 wm8994->hubs.dcs_codes_r = -7;
3796 break;
3797 default:
3798 break;
3799 }
3800
3801 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3802 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3803 break;
3804
3805 default:
3806 break;
3807 }
3808
3809 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3810 wm8994_fifo_error, "FIFO error", codec);
3811 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
3812 wm8994_temp_warn, "Thermal warning", codec);
3813 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
3814 wm8994_temp_shut, "Thermal shutdown", codec);
3815
3816 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3817 wm_hubs_dcs_done, "DC servo done",
3818 &wm8994->hubs);
3819 if (ret == 0)
3820 wm8994->hubs.dcs_done_irq = true;
3821
3822 switch (control->type) {
3823 case WM8994:
3824 if (wm8994->micdet_irq) {
3825 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3826 wm8994_mic_irq,
3827 IRQF_TRIGGER_RISING,
3828 "Mic1 detect",
3829 wm8994);
3830 if (ret != 0)
3831 dev_warn(codec->dev,
3832 "Failed to request Mic1 detect IRQ: %d\n",
3833 ret);
3834 }
3835
3836 ret = wm8994_request_irq(wm8994->wm8994,
3837 WM8994_IRQ_MIC1_SHRT,
3838 wm8994_mic_irq, "Mic 1 short",
3839 wm8994);
3840 if (ret != 0)
3841 dev_warn(codec->dev,
3842 "Failed to request Mic1 short IRQ: %d\n",
3843 ret);
3844
3845 ret = wm8994_request_irq(wm8994->wm8994,
3846 WM8994_IRQ_MIC2_DET,
3847 wm8994_mic_irq, "Mic 2 detect",
3848 wm8994);
3849 if (ret != 0)
3850 dev_warn(codec->dev,
3851 "Failed to request Mic2 detect IRQ: %d\n",
3852 ret);
3853
3854 ret = wm8994_request_irq(wm8994->wm8994,
3855 WM8994_IRQ_MIC2_SHRT,
3856 wm8994_mic_irq, "Mic 2 short",
3857 wm8994);
3858 if (ret != 0)
3859 dev_warn(codec->dev,
3860 "Failed to request Mic2 short IRQ: %d\n",
3861 ret);
3862 break;
3863
3864 case WM8958:
3865 case WM1811:
3866 if (wm8994->micdet_irq) {
3867 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3868 wm8958_mic_irq,
3869 IRQF_TRIGGER_RISING,
3870 "Mic detect",
3871 wm8994);
3872 if (ret != 0)
3873 dev_warn(codec->dev,
3874 "Failed to request Mic detect IRQ: %d\n",
3875 ret);
3876 }
3877 }
3878
3879 switch (control->type) {
3880 case WM1811:
3881 if (wm8994->revision > 1) {
3882 ret = wm8994_request_irq(wm8994->wm8994,
3883 WM8994_IRQ_GPIO(6),
3884 wm1811_jackdet_irq, "JACKDET",
3885 wm8994);
3886 if (ret == 0)
3887 wm8994->jackdet = true;
3888 }
3889 break;
3890 default:
3891 break;
3892 }
3893
3894 wm8994->fll_locked_irq = true;
3895 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
3896 ret = wm8994_request_irq(wm8994->wm8994,
3897 WM8994_IRQ_FLL1_LOCK + i,
3898 wm8994_fll_locked_irq, "FLL lock",
3899 &wm8994->fll_locked[i]);
3900 if (ret != 0)
3901 wm8994->fll_locked_irq = false;
3902 }
3903
3904 /* Make sure we can read from the GPIOs if they're inputs */
3905 pm_runtime_get_sync(codec->dev);
3906
3907 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3908 * configured on init - if a system wants to do this dynamically
3909 * at runtime we can deal with that then.
3910 */
3911 ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
3912 if (ret < 0) {
3913 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3914 goto err_irq;
3915 }
3916 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3917 wm8994->lrclk_shared[0] = 1;
3918 wm8994_dai[0].symmetric_rates = 1;
3919 } else {
3920 wm8994->lrclk_shared[0] = 0;
3921 }
3922
3923 ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
3924 if (ret < 0) {
3925 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3926 goto err_irq;
3927 }
3928 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3929 wm8994->lrclk_shared[1] = 1;
3930 wm8994_dai[1].symmetric_rates = 1;
3931 } else {
3932 wm8994->lrclk_shared[1] = 0;
3933 }
3934
3935 pm_runtime_put(codec->dev);
3936
3937 /* Latch volume update bits */
3938 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
3939 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg,
3940 wm8994_vu_bits[i].mask,
3941 wm8994_vu_bits[i].mask);
3942
3943 /* Set the low bit of the 3D stereo depth so TLV matches */
3944 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3945 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3946 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3947 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3948 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3949 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3950 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3951 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3952 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3953
3954 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3955 * use this; it only affects behaviour on idle TDM clock
3956 * cycles. */
3957 switch (control->type) {
3958 case WM8994:
3959 case WM8958:
3960 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3961 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3962 break;
3963 default:
3964 break;
3965 }
3966
3967 /* Put MICBIAS into bypass mode by default on newer devices */
3968 switch (control->type) {
3969 case WM8958:
3970 case WM1811:
3971 snd_soc_update_bits(codec, WM8958_MICBIAS1,
3972 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
3973 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3974 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
3975 break;
3976 default:
3977 break;
3978 }
3979
3980 wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
3981 wm_hubs_update_class_w(codec);
3982
3983 wm8994_handle_pdata(wm8994);
3984
3985 wm_hubs_add_analogue_controls(codec);
3986 snd_soc_add_codec_controls(codec, wm8994_snd_controls,
3987 ARRAY_SIZE(wm8994_snd_controls));
3988 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3989 ARRAY_SIZE(wm8994_dapm_widgets));
3990
3991 switch (control->type) {
3992 case WM8994:
3993 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3994 ARRAY_SIZE(wm8994_specific_dapm_widgets));
3995 if (wm8994->revision < 4) {
3996 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3997 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3998 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3999 ARRAY_SIZE(wm8994_adc_revd_widgets));
4000 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4001 ARRAY_SIZE(wm8994_dac_revd_widgets));
4002 } else {
4003 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4004 ARRAY_SIZE(wm8994_lateclk_widgets));
4005 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4006 ARRAY_SIZE(wm8994_adc_widgets));
4007 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4008 ARRAY_SIZE(wm8994_dac_widgets));
4009 }
4010 break;
4011 case WM8958:
4012 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4013 ARRAY_SIZE(wm8958_snd_controls));
4014 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4015 ARRAY_SIZE(wm8958_dapm_widgets));
4016 if (wm8994->revision < 1) {
4017 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4018 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4019 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4020 ARRAY_SIZE(wm8994_adc_revd_widgets));
4021 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4022 ARRAY_SIZE(wm8994_dac_revd_widgets));
4023 } else {
4024 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4025 ARRAY_SIZE(wm8994_lateclk_widgets));
4026 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4027 ARRAY_SIZE(wm8994_adc_widgets));
4028 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4029 ARRAY_SIZE(wm8994_dac_widgets));
4030 }
4031 break;
4032
4033 case WM1811:
4034 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4035 ARRAY_SIZE(wm8958_snd_controls));
4036 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4037 ARRAY_SIZE(wm8958_dapm_widgets));
4038 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4039 ARRAY_SIZE(wm8994_lateclk_widgets));
4040 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4041 ARRAY_SIZE(wm8994_adc_widgets));
4042 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4043 ARRAY_SIZE(wm8994_dac_widgets));
4044 break;
4045 }
4046
4047 wm_hubs_add_analogue_routes(codec, 0, 0);
4048 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
4049
4050 switch (control->type) {
4051 case WM8994:
4052 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4053 ARRAY_SIZE(wm8994_intercon));
4054
4055 if (wm8994->revision < 4) {
4056 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4057 ARRAY_SIZE(wm8994_revd_intercon));
4058 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4059 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4060 } else {
4061 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4062 ARRAY_SIZE(wm8994_lateclk_intercon));
4063 }
4064 break;
4065 case WM8958:
4066 if (wm8994->revision < 1) {
4067 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4068 ARRAY_SIZE(wm8994_revd_intercon));
4069 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4070 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4071 } else {
4072 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4073 ARRAY_SIZE(wm8994_lateclk_intercon));
4074 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4075 ARRAY_SIZE(wm8958_intercon));
4076 }
4077
4078 wm8958_dsp2_init(codec);
4079 break;
4080 case WM1811:
4081 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4082 ARRAY_SIZE(wm8994_lateclk_intercon));
4083 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4084 ARRAY_SIZE(wm8958_intercon));
4085 break;
4086 }
4087
4088 return 0;
4089
4090 err_irq:
4091 if (wm8994->jackdet)
4092 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4093 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4094 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4095 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
4096 if (wm8994->micdet_irq)
4097 free_irq(wm8994->micdet_irq, wm8994);
4098 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4099 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4100 &wm8994->fll_locked[i]);
4101 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4102 &wm8994->hubs);
4103 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4104 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4105 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4106
4107 return ret;
4108 }
4109
4110 static int wm8994_codec_remove(struct snd_soc_codec *codec)
4111 {
4112 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4113 struct wm8994 *control = wm8994->wm8994;
4114 int i;
4115
4116 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
4117
4118 pm_runtime_disable(codec->dev);
4119
4120 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4121 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4122 &wm8994->fll_locked[i]);
4123
4124 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4125 &wm8994->hubs);
4126 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4127 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4128 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4129
4130 if (wm8994->jackdet)
4131 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4132
4133 switch (control->type) {
4134 case WM8994:
4135 if (wm8994->micdet_irq)
4136 free_irq(wm8994->micdet_irq, wm8994);
4137 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
4138 wm8994);
4139 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
4140 wm8994);
4141 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4142 wm8994);
4143 break;
4144
4145 case WM1811:
4146 case WM8958:
4147 if (wm8994->micdet_irq)
4148 free_irq(wm8994->micdet_irq, wm8994);
4149 break;
4150 }
4151 release_firmware(wm8994->mbc);
4152 release_firmware(wm8994->mbc_vss);
4153 release_firmware(wm8994->enh_eq);
4154 kfree(wm8994->retune_mobile_texts);
4155 return 0;
4156 }
4157
4158 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4159 .probe = wm8994_codec_probe,
4160 .remove = wm8994_codec_remove,
4161 .suspend = wm8994_codec_suspend,
4162 .resume = wm8994_codec_resume,
4163 .set_bias_level = wm8994_set_bias_level,
4164 };
4165
4166 static int __devinit wm8994_probe(struct platform_device *pdev)
4167 {
4168 struct wm8994_priv *wm8994;
4169
4170 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4171 GFP_KERNEL);
4172 if (wm8994 == NULL)
4173 return -ENOMEM;
4174 platform_set_drvdata(pdev, wm8994);
4175
4176 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
4177 wm8994->pdata = dev_get_platdata(pdev->dev.parent);
4178
4179 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4180 wm8994_dai, ARRAY_SIZE(wm8994_dai));
4181 }
4182
4183 static int __devexit wm8994_remove(struct platform_device *pdev)
4184 {
4185 snd_soc_unregister_codec(&pdev->dev);
4186 return 0;
4187 }
4188
4189 #ifdef CONFIG_PM_SLEEP
4190 static int wm8994_suspend(struct device *dev)
4191 {
4192 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4193
4194 /* Drop down to power saving mode when system is suspended */
4195 if (wm8994->jackdet && !wm8994->active_refcount)
4196 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4197 WM1811_JACKDET_MODE_MASK,
4198 wm8994->jackdet_mode);
4199
4200 return 0;
4201 }
4202
4203 static int wm8994_resume(struct device *dev)
4204 {
4205 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4206
4207 if (wm8994->jackdet && wm8994->jack_cb)
4208 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4209 WM1811_JACKDET_MODE_MASK,
4210 WM1811_JACKDET_MODE_AUDIO);
4211
4212 return 0;
4213 }
4214 #endif
4215
4216 static const struct dev_pm_ops wm8994_pm_ops = {
4217 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4218 };
4219
4220 static struct platform_driver wm8994_codec_driver = {
4221 .driver = {
4222 .name = "wm8994-codec",
4223 .owner = THIS_MODULE,
4224 .pm = &wm8994_pm_ops,
4225 },
4226 .probe = wm8994_probe,
4227 .remove = __devexit_p(wm8994_remove),
4228 };
4229
4230 module_platform_driver(wm8994_codec_driver);
4231
4232 MODULE_DESCRIPTION("ASoC WM8994 driver");
4233 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4234 MODULE_LICENSE("GPL");
4235 MODULE_ALIAS("platform:wm8994-codec");
Linux kernel - Deliverables
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