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Merge branch 'for-2.6.37' into for-2.6.38
[deliverable/linux.git] / sound / soc / codecs / wm8994.c
1 /*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/slab.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
27 #include <sound/soc-dapm.h>
28 #include <sound/initval.h>
29 #include <sound/tlv.h>
30
31 #include <linux/mfd/wm8994/core.h>
32 #include <linux/mfd/wm8994/registers.h>
33 #include <linux/mfd/wm8994/pdata.h>
34 #include <linux/mfd/wm8994/gpio.h>
35
36 #include "wm8994.h"
37 #include "wm_hubs.h"
38
39 struct fll_config {
40 int src;
41 int in;
42 int out;
43 };
44
45 #define WM8994_NUM_DRC 3
46 #define WM8994_NUM_EQ 3
47
48 static int wm8994_drc_base[] = {
49 WM8994_AIF1_DRC1_1,
50 WM8994_AIF1_DRC2_1,
51 WM8994_AIF2_DRC_1,
52 };
53
54 static int wm8994_retune_mobile_base[] = {
55 WM8994_AIF1_DAC1_EQ_GAINS_1,
56 WM8994_AIF1_DAC2_EQ_GAINS_1,
57 WM8994_AIF2_EQ_GAINS_1,
58 };
59
60 #define WM8994_REG_CACHE_SIZE 0x621
61
62 struct wm8994_micdet {
63 struct snd_soc_jack *jack;
64 int det;
65 int shrt;
66 };
67
68 /* codec private data */
69 struct wm8994_priv {
70 struct wm_hubs_data hubs;
71 enum snd_soc_control_type control_type;
72 void *control_data;
73 struct snd_soc_codec *codec;
74 u16 reg_cache[WM8994_REG_CACHE_SIZE + 1];
75 int sysclk[2];
76 int sysclk_rate[2];
77 int mclk[2];
78 int aifclk[2];
79 struct fll_config fll[2], fll_suspend[2];
80
81 int dac_rates[2];
82 int lrclk_shared[2];
83
84 /* Platform dependant DRC configuration */
85 const char **drc_texts;
86 int drc_cfg[WM8994_NUM_DRC];
87 struct soc_enum drc_enum;
88
89 /* Platform dependant ReTune mobile configuration */
90 int num_retune_mobile_texts;
91 const char **retune_mobile_texts;
92 int retune_mobile_cfg[WM8994_NUM_EQ];
93 struct soc_enum retune_mobile_enum;
94
95 struct wm8994_micdet micdet[2];
96
97 int revision;
98 struct wm8994_pdata *pdata;
99 };
100
101 static int wm8994_readable(unsigned int reg)
102 {
103 switch (reg) {
104 case WM8994_GPIO_1:
105 case WM8994_GPIO_2:
106 case WM8994_GPIO_3:
107 case WM8994_GPIO_4:
108 case WM8994_GPIO_5:
109 case WM8994_GPIO_6:
110 case WM8994_GPIO_7:
111 case WM8994_GPIO_8:
112 case WM8994_GPIO_9:
113 case WM8994_GPIO_10:
114 case WM8994_GPIO_11:
115 case WM8994_INTERRUPT_STATUS_1:
116 case WM8994_INTERRUPT_STATUS_2:
117 case WM8994_INTERRUPT_RAW_STATUS_2:
118 return 1;
119 default:
120 break;
121 }
122
123 if (reg >= WM8994_CACHE_SIZE)
124 return 0;
125 return wm8994_access_masks[reg].readable != 0;
126 }
127
128 static int wm8994_volatile(unsigned int reg)
129 {
130 if (reg >= WM8994_REG_CACHE_SIZE)
131 return 1;
132
133 switch (reg) {
134 case WM8994_SOFTWARE_RESET:
135 case WM8994_CHIP_REVISION:
136 case WM8994_DC_SERVO_1:
137 case WM8994_DC_SERVO_READBACK:
138 case WM8994_RATE_STATUS:
139 case WM8994_LDO_1:
140 case WM8994_LDO_2:
141 return 1;
142 default:
143 return 0;
144 }
145 }
146
147 static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
148 unsigned int value)
149 {
150 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
151
152 BUG_ON(reg > WM8994_MAX_REGISTER);
153
154 if (!wm8994_volatile(reg))
155 wm8994->reg_cache[reg] = value;
156
157 return wm8994_reg_write(codec->control_data, reg, value);
158 }
159
160 static unsigned int wm8994_read(struct snd_soc_codec *codec,
161 unsigned int reg)
162 {
163 u16 *reg_cache = codec->reg_cache;
164
165 BUG_ON(reg > WM8994_MAX_REGISTER);
166
167 if (wm8994_volatile(reg))
168 return wm8994_reg_read(codec->control_data, reg);
169 else
170 return reg_cache[reg];
171 }
172
173 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
174 {
175 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
176 int rate;
177 int reg1 = 0;
178 int offset;
179
180 if (aif)
181 offset = 4;
182 else
183 offset = 0;
184
185 switch (wm8994->sysclk[aif]) {
186 case WM8994_SYSCLK_MCLK1:
187 rate = wm8994->mclk[0];
188 break;
189
190 case WM8994_SYSCLK_MCLK2:
191 reg1 |= 0x8;
192 rate = wm8994->mclk[1];
193 break;
194
195 case WM8994_SYSCLK_FLL1:
196 reg1 |= 0x10;
197 rate = wm8994->fll[0].out;
198 break;
199
200 case WM8994_SYSCLK_FLL2:
201 reg1 |= 0x18;
202 rate = wm8994->fll[1].out;
203 break;
204
205 default:
206 return -EINVAL;
207 }
208
209 if (rate >= 13500000) {
210 rate /= 2;
211 reg1 |= WM8994_AIF1CLK_DIV;
212
213 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
214 aif + 1, rate);
215 }
216
217 if (rate && rate < 3000000)
218 dev_warn(codec->dev, "AIF%dCLK is %dHz, should be >=3MHz for optimal performance\n",
219 aif + 1, rate);
220
221 wm8994->aifclk[aif] = rate;
222
223 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
224 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
225 reg1);
226
227 return 0;
228 }
229
230 static int configure_clock(struct snd_soc_codec *codec)
231 {
232 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
233 int old, new;
234
235 /* Bring up the AIF clocks first */
236 configure_aif_clock(codec, 0);
237 configure_aif_clock(codec, 1);
238
239 /* Then switch CLK_SYS over to the higher of them; a change
240 * can only happen as a result of a clocking change which can
241 * only be made outside of DAPM so we can safely redo the
242 * clocking.
243 */
244
245 /* If they're equal it doesn't matter which is used */
246 if (wm8994->aifclk[0] == wm8994->aifclk[1])
247 return 0;
248
249 if (wm8994->aifclk[0] < wm8994->aifclk[1])
250 new = WM8994_SYSCLK_SRC;
251 else
252 new = 0;
253
254 old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
255
256 /* If there's no change then we're done. */
257 if (old == new)
258 return 0;
259
260 snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
261
262 snd_soc_dapm_sync(&codec->dapm);
263
264 return 0;
265 }
266
267 static int check_clk_sys(struct snd_soc_dapm_widget *source,
268 struct snd_soc_dapm_widget *sink)
269 {
270 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
271 const char *clk;
272
273 /* Check what we're currently using for CLK_SYS */
274 if (reg & WM8994_SYSCLK_SRC)
275 clk = "AIF2CLK";
276 else
277 clk = "AIF1CLK";
278
279 return strcmp(source->name, clk) == 0;
280 }
281
282 static const char *sidetone_hpf_text[] = {
283 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
284 };
285
286 static const struct soc_enum sidetone_hpf =
287 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
288
289 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
290 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
291 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
292 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
293 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
294
295 #define WM8994_DRC_SWITCH(xname, reg, shift) \
296 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
297 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
298 .put = wm8994_put_drc_sw, \
299 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
300
301 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
302 struct snd_ctl_elem_value *ucontrol)
303 {
304 struct soc_mixer_control *mc =
305 (struct soc_mixer_control *)kcontrol->private_value;
306 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
307 int mask, ret;
308
309 /* Can't enable both ADC and DAC paths simultaneously */
310 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
311 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
312 WM8994_AIF1ADC1R_DRC_ENA_MASK;
313 else
314 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
315
316 ret = snd_soc_read(codec, mc->reg);
317 if (ret < 0)
318 return ret;
319 if (ret & mask)
320 return -EINVAL;
321
322 return snd_soc_put_volsw(kcontrol, ucontrol);
323 }
324
325 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
326 {
327 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
328 struct wm8994_pdata *pdata = wm8994->pdata;
329 int base = wm8994_drc_base[drc];
330 int cfg = wm8994->drc_cfg[drc];
331 int save, i;
332
333 /* Save any enables; the configuration should clear them. */
334 save = snd_soc_read(codec, base);
335 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
336 WM8994_AIF1ADC1R_DRC_ENA;
337
338 for (i = 0; i < WM8994_DRC_REGS; i++)
339 snd_soc_update_bits(codec, base + i, 0xffff,
340 pdata->drc_cfgs[cfg].regs[i]);
341
342 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
343 WM8994_AIF1ADC1L_DRC_ENA |
344 WM8994_AIF1ADC1R_DRC_ENA, save);
345 }
346
347 /* Icky as hell but saves code duplication */
348 static int wm8994_get_drc(const char *name)
349 {
350 if (strcmp(name, "AIF1DRC1 Mode") == 0)
351 return 0;
352 if (strcmp(name, "AIF1DRC2 Mode") == 0)
353 return 1;
354 if (strcmp(name, "AIF2DRC Mode") == 0)
355 return 2;
356 return -EINVAL;
357 }
358
359 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
360 struct snd_ctl_elem_value *ucontrol)
361 {
362 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
363 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
364 struct wm8994_pdata *pdata = wm8994->pdata;
365 int drc = wm8994_get_drc(kcontrol->id.name);
366 int value = ucontrol->value.integer.value[0];
367
368 if (drc < 0)
369 return drc;
370
371 if (value >= pdata->num_drc_cfgs)
372 return -EINVAL;
373
374 wm8994->drc_cfg[drc] = value;
375
376 wm8994_set_drc(codec, drc);
377
378 return 0;
379 }
380
381 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
382 struct snd_ctl_elem_value *ucontrol)
383 {
384 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
385 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
386 int drc = wm8994_get_drc(kcontrol->id.name);
387
388 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
389
390 return 0;
391 }
392
393 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
394 {
395 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
396 struct wm8994_pdata *pdata = wm8994->pdata;
397 int base = wm8994_retune_mobile_base[block];
398 int iface, best, best_val, save, i, cfg;
399
400 if (!pdata || !wm8994->num_retune_mobile_texts)
401 return;
402
403 switch (block) {
404 case 0:
405 case 1:
406 iface = 0;
407 break;
408 case 2:
409 iface = 1;
410 break;
411 default:
412 return;
413 }
414
415 /* Find the version of the currently selected configuration
416 * with the nearest sample rate. */
417 cfg = wm8994->retune_mobile_cfg[block];
418 best = 0;
419 best_val = INT_MAX;
420 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
421 if (strcmp(pdata->retune_mobile_cfgs[i].name,
422 wm8994->retune_mobile_texts[cfg]) == 0 &&
423 abs(pdata->retune_mobile_cfgs[i].rate
424 - wm8994->dac_rates[iface]) < best_val) {
425 best = i;
426 best_val = abs(pdata->retune_mobile_cfgs[i].rate
427 - wm8994->dac_rates[iface]);
428 }
429 }
430
431 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
432 block,
433 pdata->retune_mobile_cfgs[best].name,
434 pdata->retune_mobile_cfgs[best].rate,
435 wm8994->dac_rates[iface]);
436
437 /* The EQ will be disabled while reconfiguring it, remember the
438 * current configuration.
439 */
440 save = snd_soc_read(codec, base);
441 save &= WM8994_AIF1DAC1_EQ_ENA;
442
443 for (i = 0; i < WM8994_EQ_REGS; i++)
444 snd_soc_update_bits(codec, base + i, 0xffff,
445 pdata->retune_mobile_cfgs[best].regs[i]);
446
447 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
448 }
449
450 /* Icky as hell but saves code duplication */
451 static int wm8994_get_retune_mobile_block(const char *name)
452 {
453 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
454 return 0;
455 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
456 return 1;
457 if (strcmp(name, "AIF2 EQ Mode") == 0)
458 return 2;
459 return -EINVAL;
460 }
461
462 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
463 struct snd_ctl_elem_value *ucontrol)
464 {
465 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
466 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
467 struct wm8994_pdata *pdata = wm8994->pdata;
468 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
469 int value = ucontrol->value.integer.value[0];
470
471 if (block < 0)
472 return block;
473
474 if (value >= pdata->num_retune_mobile_cfgs)
475 return -EINVAL;
476
477 wm8994->retune_mobile_cfg[block] = value;
478
479 wm8994_set_retune_mobile(codec, block);
480
481 return 0;
482 }
483
484 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
485 struct snd_ctl_elem_value *ucontrol)
486 {
487 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
488 struct wm8994_priv *wm8994 =snd_soc_codec_get_drvdata(codec);
489 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
490
491 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
492
493 return 0;
494 }
495
496 static const char *aif_chan_src_text[] = {
497 "Left", "Right"
498 };
499
500 static const struct soc_enum aif1adcl_src =
501 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
502
503 static const struct soc_enum aif1adcr_src =
504 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
505
506 static const struct soc_enum aif2adcl_src =
507 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
508
509 static const struct soc_enum aif2adcr_src =
510 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
511
512 static const struct soc_enum aif1dacl_src =
513 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
514
515 static const struct soc_enum aif1dacr_src =
516 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
517
518 static const struct soc_enum aif2dacl_src =
519 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
520
521 static const struct soc_enum aif2dacr_src =
522 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
523
524 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
525 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
526 WM8994_AIF1_ADC1_RIGHT_VOLUME,
527 1, 119, 0, digital_tlv),
528 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
529 WM8994_AIF1_ADC2_RIGHT_VOLUME,
530 1, 119, 0, digital_tlv),
531 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
532 WM8994_AIF2_ADC_RIGHT_VOLUME,
533 1, 119, 0, digital_tlv),
534
535 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
536 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
537 SOC_ENUM("AIF2ADCL Source", aif1adcl_src),
538 SOC_ENUM("AIF2ADCR Source", aif1adcr_src),
539
540 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
541 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
542 SOC_ENUM("AIF2DACL Source", aif1dacl_src),
543 SOC_ENUM("AIF2DACR Source", aif1dacr_src),
544
545 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
546 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
547 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
548 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
549 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
550 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
551
552 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
553 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
554
555 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
556 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
557 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
558
559 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
560 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
561 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
562
563 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
564 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
565 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
566
567 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
568 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
569 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
570
571 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
572 5, 12, 0, st_tlv),
573 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
574 0, 12, 0, st_tlv),
575 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
576 5, 12, 0, st_tlv),
577 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
578 0, 12, 0, st_tlv),
579 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
580 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
581
582 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
583 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
584 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
585 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
586
587 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
588 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
589 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
590 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
591
592 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
593 6, 1, 1, wm_hubs_spkmix_tlv),
594 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
595 2, 1, 1, wm_hubs_spkmix_tlv),
596
597 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
598 6, 1, 1, wm_hubs_spkmix_tlv),
599 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
600 2, 1, 1, wm_hubs_spkmix_tlv),
601
602 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
603 10, 15, 0, wm8994_3d_tlv),
604 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
605 8, 1, 0),
606 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
607 10, 15, 0, wm8994_3d_tlv),
608 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
609 8, 1, 0),
610 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
611 10, 15, 0, wm8994_3d_tlv),
612 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
613 8, 1, 0),
614 };
615
616 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
617 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
618 eq_tlv),
619 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
620 eq_tlv),
621 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
622 eq_tlv),
623 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
624 eq_tlv),
625 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
626 eq_tlv),
627
628 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
629 eq_tlv),
630 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
631 eq_tlv),
632 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
633 eq_tlv),
634 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
635 eq_tlv),
636 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
637 eq_tlv),
638
639 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
640 eq_tlv),
641 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
642 eq_tlv),
643 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
644 eq_tlv),
645 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
646 eq_tlv),
647 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
648 eq_tlv),
649 };
650
651 static int clk_sys_event(struct snd_soc_dapm_widget *w,
652 struct snd_kcontrol *kcontrol, int event)
653 {
654 struct snd_soc_codec *codec = w->codec;
655
656 switch (event) {
657 case SND_SOC_DAPM_PRE_PMU:
658 return configure_clock(codec);
659
660 case SND_SOC_DAPM_POST_PMD:
661 configure_clock(codec);
662 break;
663 }
664
665 return 0;
666 }
667
668 static void wm8994_update_class_w(struct snd_soc_codec *codec)
669 {
670 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
671 int enable = 1;
672 int source = 0; /* GCC flow analysis can't track enable */
673 int reg, reg_r;
674
675 /* Only support direct DAC->headphone paths */
676 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
677 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
678 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
679 enable = 0;
680 }
681
682 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
683 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
684 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
685 enable = 0;
686 }
687
688 /* We also need the same setting for L/R and only one path */
689 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
690 switch (reg) {
691 case WM8994_AIF2DACL_TO_DAC1L:
692 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
693 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
694 break;
695 case WM8994_AIF1DAC2L_TO_DAC1L:
696 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
697 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
698 break;
699 case WM8994_AIF1DAC1L_TO_DAC1L:
700 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
701 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
702 break;
703 default:
704 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
705 enable = 0;
706 break;
707 }
708
709 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
710 if (reg_r != reg) {
711 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
712 enable = 0;
713 }
714
715 if (enable) {
716 dev_dbg(codec->dev, "Class W enabled\n");
717 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
718 WM8994_CP_DYN_PWR |
719 WM8994_CP_DYN_SRC_SEL_MASK,
720 source | WM8994_CP_DYN_PWR);
721 wm8994->hubs.class_w = true;
722
723 } else {
724 dev_dbg(codec->dev, "Class W disabled\n");
725 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
726 WM8994_CP_DYN_PWR, 0);
727 wm8994->hubs.class_w = false;
728 }
729 }
730
731 static const char *hp_mux_text[] = {
732 "Mixer",
733 "DAC",
734 };
735
736 #define WM8994_HP_ENUM(xname, xenum) \
737 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
738 .info = snd_soc_info_enum_double, \
739 .get = snd_soc_dapm_get_enum_double, \
740 .put = wm8994_put_hp_enum, \
741 .private_value = (unsigned long)&xenum }
742
743 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
744 struct snd_ctl_elem_value *ucontrol)
745 {
746 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
747 struct snd_soc_codec *codec = w->codec;
748 int ret;
749
750 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
751
752 wm8994_update_class_w(codec);
753
754 return ret;
755 }
756
757 static const struct soc_enum hpl_enum =
758 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
759
760 static const struct snd_kcontrol_new hpl_mux =
761 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
762
763 static const struct soc_enum hpr_enum =
764 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
765
766 static const struct snd_kcontrol_new hpr_mux =
767 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
768
769 static const char *adc_mux_text[] = {
770 "ADC",
771 "DMIC",
772 };
773
774 static const struct soc_enum adc_enum =
775 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
776
777 static const struct snd_kcontrol_new adcl_mux =
778 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
779
780 static const struct snd_kcontrol_new adcr_mux =
781 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
782
783 static const struct snd_kcontrol_new left_speaker_mixer[] = {
784 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
785 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
786 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
787 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
788 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
789 };
790
791 static const struct snd_kcontrol_new right_speaker_mixer[] = {
792 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
793 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
794 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
795 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
796 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
797 };
798
799 /* Debugging; dump chip status after DAPM transitions */
800 static int post_ev(struct snd_soc_dapm_widget *w,
801 struct snd_kcontrol *kcontrol, int event)
802 {
803 struct snd_soc_codec *codec = w->codec;
804 dev_dbg(codec->dev, "SRC status: %x\n",
805 snd_soc_read(codec,
806 WM8994_RATE_STATUS));
807 return 0;
808 }
809
810 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
811 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
812 1, 1, 0),
813 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
814 0, 1, 0),
815 };
816
817 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
818 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
819 1, 1, 0),
820 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
821 0, 1, 0),
822 };
823
824 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
825 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
826 1, 1, 0),
827 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
828 0, 1, 0),
829 };
830
831 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
832 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
833 1, 1, 0),
834 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
835 0, 1, 0),
836 };
837
838 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
839 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
840 5, 1, 0),
841 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
842 4, 1, 0),
843 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
844 2, 1, 0),
845 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
846 1, 1, 0),
847 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
848 0, 1, 0),
849 };
850
851 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
852 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
853 5, 1, 0),
854 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
855 4, 1, 0),
856 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
857 2, 1, 0),
858 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
859 1, 1, 0),
860 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
861 0, 1, 0),
862 };
863
864 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
865 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
866 .info = snd_soc_info_volsw, \
867 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
868 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
869
870 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
871 struct snd_ctl_elem_value *ucontrol)
872 {
873 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
874 struct snd_soc_codec *codec = w->codec;
875 int ret;
876
877 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
878
879 wm8994_update_class_w(codec);
880
881 return ret;
882 }
883
884 static const struct snd_kcontrol_new dac1l_mix[] = {
885 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
886 5, 1, 0),
887 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
888 4, 1, 0),
889 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
890 2, 1, 0),
891 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
892 1, 1, 0),
893 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
894 0, 1, 0),
895 };
896
897 static const struct snd_kcontrol_new dac1r_mix[] = {
898 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
899 5, 1, 0),
900 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
901 4, 1, 0),
902 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
903 2, 1, 0),
904 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
905 1, 1, 0),
906 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
907 0, 1, 0),
908 };
909
910 static const char *sidetone_text[] = {
911 "ADC/DMIC1", "DMIC2",
912 };
913
914 static const struct soc_enum sidetone1_enum =
915 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
916
917 static const struct snd_kcontrol_new sidetone1_mux =
918 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
919
920 static const struct soc_enum sidetone2_enum =
921 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
922
923 static const struct snd_kcontrol_new sidetone2_mux =
924 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
925
926 static const char *aif1dac_text[] = {
927 "AIF1DACDAT", "AIF3DACDAT",
928 };
929
930 static const struct soc_enum aif1dac_enum =
931 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
932
933 static const struct snd_kcontrol_new aif1dac_mux =
934 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
935
936 static const char *aif2dac_text[] = {
937 "AIF2DACDAT", "AIF3DACDAT",
938 };
939
940 static const struct soc_enum aif2dac_enum =
941 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
942
943 static const struct snd_kcontrol_new aif2dac_mux =
944 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
945
946 static const char *aif2adc_text[] = {
947 "AIF2ADCDAT", "AIF3DACDAT",
948 };
949
950 static const struct soc_enum aif2adc_enum =
951 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
952
953 static const struct snd_kcontrol_new aif2adc_mux =
954 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
955
956 static const char *aif3adc_text[] = {
957 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT",
958 };
959
960 static const struct soc_enum aif3adc_enum =
961 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
962
963 static const struct snd_kcontrol_new aif3adc_mux =
964 SOC_DAPM_ENUM("AIF3ADC Mux", aif3adc_enum);
965
966 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
967 SND_SOC_DAPM_INPUT("DMIC1DAT"),
968 SND_SOC_DAPM_INPUT("DMIC2DAT"),
969 SND_SOC_DAPM_INPUT("Clock"),
970
971 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
972 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
973
974 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
975 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
976 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
977
978 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
979 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
980
981 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture",
982 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
983 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture",
984 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
985 SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0,
986 WM8994_POWER_MANAGEMENT_5, 9, 0),
987 SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0,
988 WM8994_POWER_MANAGEMENT_5, 8, 0),
989
990 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture",
991 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
992 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture",
993 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
994 SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0,
995 WM8994_POWER_MANAGEMENT_5, 11, 0),
996 SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0,
997 WM8994_POWER_MANAGEMENT_5, 10, 0),
998
999 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1000 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1001 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1002 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1003
1004 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1005 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1006 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1007 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1008
1009 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1010 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1011 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1012 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1013
1014 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1015 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1016
1017 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1018 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1019 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1020 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1021
1022 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1023 WM8994_POWER_MANAGEMENT_4, 13, 0),
1024 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1025 WM8994_POWER_MANAGEMENT_4, 12, 0),
1026 SND_SOC_DAPM_AIF_IN("AIF2DACL", NULL, 0,
1027 WM8994_POWER_MANAGEMENT_5, 13, 0),
1028 SND_SOC_DAPM_AIF_IN("AIF2DACR", NULL, 0,
1029 WM8994_POWER_MANAGEMENT_5, 12, 0),
1030
1031 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1032 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1033 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1034
1035 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1036 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1037 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1038 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &aif3adc_mux),
1039
1040 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1041 SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1042
1043 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1044
1045 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1046 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1047 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1048 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1049
1050 /* Power is done with the muxes since the ADC power also controls the
1051 * downsampling chain, the chip will automatically manage the analogue
1052 * specific portions.
1053 */
1054 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1055 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1056
1057 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1058 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1059
1060 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1061 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1062 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1063 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1064
1065 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1066 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1067
1068 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1069 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1070 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1071 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1072
1073 SND_SOC_DAPM_POST("Debug log", post_ev),
1074 };
1075
1076 static const struct snd_soc_dapm_route intercon[] = {
1077
1078 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1079 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1080
1081 { "DSP1CLK", NULL, "CLK_SYS" },
1082 { "DSP2CLK", NULL, "CLK_SYS" },
1083 { "DSPINTCLK", NULL, "CLK_SYS" },
1084
1085 { "AIF1ADC1L", NULL, "AIF1CLK" },
1086 { "AIF1ADC1L", NULL, "DSP1CLK" },
1087 { "AIF1ADC1R", NULL, "AIF1CLK" },
1088 { "AIF1ADC1R", NULL, "DSP1CLK" },
1089 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1090
1091 { "AIF1DAC1L", NULL, "AIF1CLK" },
1092 { "AIF1DAC1L", NULL, "DSP1CLK" },
1093 { "AIF1DAC1R", NULL, "AIF1CLK" },
1094 { "AIF1DAC1R", NULL, "DSP1CLK" },
1095 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1096
1097 { "AIF1ADC2L", NULL, "AIF1CLK" },
1098 { "AIF1ADC2L", NULL, "DSP1CLK" },
1099 { "AIF1ADC2R", NULL, "AIF1CLK" },
1100 { "AIF1ADC2R", NULL, "DSP1CLK" },
1101 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1102
1103 { "AIF1DAC2L", NULL, "AIF1CLK" },
1104 { "AIF1DAC2L", NULL, "DSP1CLK" },
1105 { "AIF1DAC2R", NULL, "AIF1CLK" },
1106 { "AIF1DAC2R", NULL, "DSP1CLK" },
1107 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1108
1109 { "AIF2ADCL", NULL, "AIF2CLK" },
1110 { "AIF2ADCL", NULL, "DSP2CLK" },
1111 { "AIF2ADCR", NULL, "AIF2CLK" },
1112 { "AIF2ADCR", NULL, "DSP2CLK" },
1113 { "AIF2ADCR", NULL, "DSPINTCLK" },
1114
1115 { "AIF2DACL", NULL, "AIF2CLK" },
1116 { "AIF2DACL", NULL, "DSP2CLK" },
1117 { "AIF2DACR", NULL, "AIF2CLK" },
1118 { "AIF2DACR", NULL, "DSP2CLK" },
1119 { "AIF2DACR", NULL, "DSPINTCLK" },
1120
1121 { "DMIC1L", NULL, "DMIC1DAT" },
1122 { "DMIC1L", NULL, "CLK_SYS" },
1123 { "DMIC1R", NULL, "DMIC1DAT" },
1124 { "DMIC1R", NULL, "CLK_SYS" },
1125 { "DMIC2L", NULL, "DMIC2DAT" },
1126 { "DMIC2L", NULL, "CLK_SYS" },
1127 { "DMIC2R", NULL, "DMIC2DAT" },
1128 { "DMIC2R", NULL, "CLK_SYS" },
1129
1130 { "ADCL", NULL, "AIF1CLK" },
1131 { "ADCL", NULL, "DSP1CLK" },
1132 { "ADCL", NULL, "DSPINTCLK" },
1133
1134 { "ADCR", NULL, "AIF1CLK" },
1135 { "ADCR", NULL, "DSP1CLK" },
1136 { "ADCR", NULL, "DSPINTCLK" },
1137
1138 { "ADCL Mux", "ADC", "ADCL" },
1139 { "ADCL Mux", "DMIC", "DMIC1L" },
1140 { "ADCR Mux", "ADC", "ADCR" },
1141 { "ADCR Mux", "DMIC", "DMIC1R" },
1142
1143 { "DAC1L", NULL, "AIF1CLK" },
1144 { "DAC1L", NULL, "DSP1CLK" },
1145 { "DAC1L", NULL, "DSPINTCLK" },
1146
1147 { "DAC1R", NULL, "AIF1CLK" },
1148 { "DAC1R", NULL, "DSP1CLK" },
1149 { "DAC1R", NULL, "DSPINTCLK" },
1150
1151 { "DAC2L", NULL, "AIF2CLK" },
1152 { "DAC2L", NULL, "DSP2CLK" },
1153 { "DAC2L", NULL, "DSPINTCLK" },
1154
1155 { "DAC2R", NULL, "AIF2DACR" },
1156 { "DAC2R", NULL, "AIF2CLK" },
1157 { "DAC2R", NULL, "DSP2CLK" },
1158 { "DAC2R", NULL, "DSPINTCLK" },
1159
1160 { "TOCLK", NULL, "CLK_SYS" },
1161
1162 /* AIF1 outputs */
1163 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1164 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1165 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1166
1167 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1168 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1169 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1170
1171 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1172 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1173 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1174
1175 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1176 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1177 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1178
1179 /* Pin level routing for AIF3 */
1180 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1181 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1182 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1183 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1184
1185 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1186 { "AIF2DACR", NULL, "AIF2DAC Mux" },
1187
1188 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1189 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1190 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1191 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1192 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1193 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1194 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1195
1196 /* DAC1 inputs */
1197 { "DAC1L", NULL, "DAC1L Mixer" },
1198 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1199 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1200 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1201 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1202 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1203
1204 { "DAC1R", NULL, "DAC1R Mixer" },
1205 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1206 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1207 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1208 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1209 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1210
1211 /* DAC2/AIF2 outputs */
1212 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1213 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1214 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1215 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1216 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1217 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1218 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1219
1220 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1221 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1222 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1223 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1224 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1225 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1226 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1227
1228 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1229
1230 /* AIF3 output */
1231 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1232 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1233 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1234 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1235 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1236 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1237 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1238 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1239
1240 /* Sidetone */
1241 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1242 { "Left Sidetone", "DMIC2", "DMIC2L" },
1243 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1244 { "Right Sidetone", "DMIC2", "DMIC2R" },
1245
1246 /* Output stages */
1247 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1248 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1249
1250 { "SPKL", "DAC1 Switch", "DAC1L" },
1251 { "SPKL", "DAC2 Switch", "DAC2L" },
1252
1253 { "SPKR", "DAC1 Switch", "DAC1R" },
1254 { "SPKR", "DAC2 Switch", "DAC2R" },
1255
1256 { "Left Headphone Mux", "DAC", "DAC1L" },
1257 { "Right Headphone Mux", "DAC", "DAC1R" },
1258 };
1259
1260 /* The size in bits of the FLL divide multiplied by 10
1261 * to allow rounding later */
1262 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1263
1264 struct fll_div {
1265 u16 outdiv;
1266 u16 n;
1267 u16 k;
1268 u16 clk_ref_div;
1269 u16 fll_fratio;
1270 };
1271
1272 static int wm8994_get_fll_config(struct fll_div *fll,
1273 int freq_in, int freq_out)
1274 {
1275 u64 Kpart;
1276 unsigned int K, Ndiv, Nmod;
1277
1278 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1279
1280 /* Scale the input frequency down to <= 13.5MHz */
1281 fll->clk_ref_div = 0;
1282 while (freq_in > 13500000) {
1283 fll->clk_ref_div++;
1284 freq_in /= 2;
1285
1286 if (fll->clk_ref_div > 3)
1287 return -EINVAL;
1288 }
1289 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1290
1291 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1292 fll->outdiv = 3;
1293 while (freq_out * (fll->outdiv + 1) < 90000000) {
1294 fll->outdiv++;
1295 if (fll->outdiv > 63)
1296 return -EINVAL;
1297 }
1298 freq_out *= fll->outdiv + 1;
1299 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1300
1301 if (freq_in > 1000000) {
1302 fll->fll_fratio = 0;
1303 } else if (freq_in > 256000) {
1304 fll->fll_fratio = 1;
1305 freq_in *= 2;
1306 } else if (freq_in > 128000) {
1307 fll->fll_fratio = 2;
1308 freq_in *= 4;
1309 } else if (freq_in > 64000) {
1310 fll->fll_fratio = 3;
1311 freq_in *= 8;
1312 } else {
1313 fll->fll_fratio = 4;
1314 freq_in *= 16;
1315 }
1316 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1317
1318 /* Now, calculate N.K */
1319 Ndiv = freq_out / freq_in;
1320
1321 fll->n = Ndiv;
1322 Nmod = freq_out % freq_in;
1323 pr_debug("Nmod=%d\n", Nmod);
1324
1325 /* Calculate fractional part - scale up so we can round. */
1326 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1327
1328 do_div(Kpart, freq_in);
1329
1330 K = Kpart & 0xFFFFFFFF;
1331
1332 if ((K % 10) >= 5)
1333 K += 5;
1334
1335 /* Move down to proper range now rounding is done */
1336 fll->k = K / 10;
1337
1338 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1339
1340 return 0;
1341 }
1342
1343 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1344 unsigned int freq_in, unsigned int freq_out)
1345 {
1346 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1347 int reg_offset, ret;
1348 struct fll_div fll;
1349 u16 reg, aif1, aif2;
1350
1351 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1352 & WM8994_AIF1CLK_ENA;
1353
1354 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1355 & WM8994_AIF2CLK_ENA;
1356
1357 switch (id) {
1358 case WM8994_FLL1:
1359 reg_offset = 0;
1360 id = 0;
1361 break;
1362 case WM8994_FLL2:
1363 reg_offset = 0x20;
1364 id = 1;
1365 break;
1366 default:
1367 return -EINVAL;
1368 }
1369
1370 switch (src) {
1371 case 0:
1372 /* Allow no source specification when stopping */
1373 if (freq_out)
1374 return -EINVAL;
1375 break;
1376 case WM8994_FLL_SRC_MCLK1:
1377 case WM8994_FLL_SRC_MCLK2:
1378 case WM8994_FLL_SRC_LRCLK:
1379 case WM8994_FLL_SRC_BCLK:
1380 break;
1381 default:
1382 return -EINVAL;
1383 }
1384
1385 /* Are we changing anything? */
1386 if (wm8994->fll[id].src == src &&
1387 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1388 return 0;
1389
1390 /* If we're stopping the FLL redo the old config - no
1391 * registers will actually be written but we avoid GCC flow
1392 * analysis bugs spewing warnings.
1393 */
1394 if (freq_out)
1395 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1396 else
1397 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1398 wm8994->fll[id].out);
1399 if (ret < 0)
1400 return ret;
1401
1402 /* Gate the AIF clocks while we reclock */
1403 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1404 WM8994_AIF1CLK_ENA, 0);
1405 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1406 WM8994_AIF2CLK_ENA, 0);
1407
1408 /* We always need to disable the FLL while reconfiguring */
1409 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1410 WM8994_FLL1_ENA, 0);
1411
1412 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1413 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1414 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1415 WM8994_FLL1_OUTDIV_MASK |
1416 WM8994_FLL1_FRATIO_MASK, reg);
1417
1418 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1419
1420 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1421 WM8994_FLL1_N_MASK,
1422 fll.n << WM8994_FLL1_N_SHIFT);
1423
1424 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1425 WM8994_FLL1_REFCLK_DIV_MASK |
1426 WM8994_FLL1_REFCLK_SRC_MASK,
1427 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1428 (src - 1));
1429
1430 /* Enable (with fractional mode if required) */
1431 if (freq_out) {
1432 if (fll.k)
1433 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1434 else
1435 reg = WM8994_FLL1_ENA;
1436 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1437 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1438 reg);
1439 }
1440
1441 wm8994->fll[id].in = freq_in;
1442 wm8994->fll[id].out = freq_out;
1443 wm8994->fll[id].src = src;
1444
1445 /* Enable any gated AIF clocks */
1446 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1447 WM8994_AIF1CLK_ENA, aif1);
1448 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1449 WM8994_AIF2CLK_ENA, aif2);
1450
1451 configure_clock(codec);
1452
1453 return 0;
1454 }
1455
1456
1457 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1458
1459 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1460 unsigned int freq_in, unsigned int freq_out)
1461 {
1462 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1463 }
1464
1465 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1466 int clk_id, unsigned int freq, int dir)
1467 {
1468 struct snd_soc_codec *codec = dai->codec;
1469 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1470 int i;
1471
1472 switch (dai->id) {
1473 case 1:
1474 case 2:
1475 break;
1476
1477 default:
1478 /* AIF3 shares clocking with AIF1/2 */
1479 return -EINVAL;
1480 }
1481
1482 switch (clk_id) {
1483 case WM8994_SYSCLK_MCLK1:
1484 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
1485 wm8994->mclk[0] = freq;
1486 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1487 dai->id, freq);
1488 break;
1489
1490 case WM8994_SYSCLK_MCLK2:
1491 /* TODO: Set GPIO AF */
1492 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
1493 wm8994->mclk[1] = freq;
1494 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1495 dai->id, freq);
1496 break;
1497
1498 case WM8994_SYSCLK_FLL1:
1499 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
1500 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
1501 break;
1502
1503 case WM8994_SYSCLK_FLL2:
1504 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
1505 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
1506 break;
1507
1508 case WM8994_SYSCLK_OPCLK:
1509 /* Special case - a division (times 10) is given and
1510 * no effect on main clocking.
1511 */
1512 if (freq) {
1513 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
1514 if (opclk_divs[i] == freq)
1515 break;
1516 if (i == ARRAY_SIZE(opclk_divs))
1517 return -EINVAL;
1518 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
1519 WM8994_OPCLK_DIV_MASK, i);
1520 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1521 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
1522 } else {
1523 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1524 WM8994_OPCLK_ENA, 0);
1525 }
1526
1527 default:
1528 return -EINVAL;
1529 }
1530
1531 configure_clock(codec);
1532
1533 return 0;
1534 }
1535
1536 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
1537 enum snd_soc_bias_level level)
1538 {
1539 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1540
1541 switch (level) {
1542 case SND_SOC_BIAS_ON:
1543 break;
1544
1545 case SND_SOC_BIAS_PREPARE:
1546 /* VMID=2x40k */
1547 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1548 WM8994_VMID_SEL_MASK, 0x2);
1549 break;
1550
1551 case SND_SOC_BIAS_STANDBY:
1552 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1553 /* Tweak DC servo and DSP configuration for
1554 * improved performance. */
1555 if (wm8994->revision < 4) {
1556 /* Tweak DC servo and DSP configuration for
1557 * improved performance. */
1558 snd_soc_write(codec, 0x102, 0x3);
1559 snd_soc_write(codec, 0x56, 0x3);
1560 snd_soc_write(codec, 0x817, 0);
1561 snd_soc_write(codec, 0x102, 0);
1562 }
1563
1564 /* Discharge LINEOUT1 & 2 */
1565 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1566 WM8994_LINEOUT1_DISCH |
1567 WM8994_LINEOUT2_DISCH,
1568 WM8994_LINEOUT1_DISCH |
1569 WM8994_LINEOUT2_DISCH);
1570
1571 /* Startup bias, VMID ramp & buffer */
1572 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1573 WM8994_STARTUP_BIAS_ENA |
1574 WM8994_VMID_BUF_ENA |
1575 WM8994_VMID_RAMP_MASK,
1576 WM8994_STARTUP_BIAS_ENA |
1577 WM8994_VMID_BUF_ENA |
1578 (0x11 << WM8994_VMID_RAMP_SHIFT));
1579
1580 /* Main bias enable, VMID=2x40k */
1581 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1582 WM8994_BIAS_ENA |
1583 WM8994_VMID_SEL_MASK,
1584 WM8994_BIAS_ENA | 0x2);
1585
1586 msleep(20);
1587 }
1588
1589 /* VMID=2x500k */
1590 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1591 WM8994_VMID_SEL_MASK, 0x4);
1592
1593 break;
1594
1595 case SND_SOC_BIAS_OFF:
1596 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
1597 /* Switch over to startup biases */
1598 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1599 WM8994_BIAS_SRC |
1600 WM8994_STARTUP_BIAS_ENA |
1601 WM8994_VMID_BUF_ENA |
1602 WM8994_VMID_RAMP_MASK,
1603 WM8994_BIAS_SRC |
1604 WM8994_STARTUP_BIAS_ENA |
1605 WM8994_VMID_BUF_ENA |
1606 (1 << WM8994_VMID_RAMP_SHIFT));
1607
1608 /* Disable main biases */
1609 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1610 WM8994_BIAS_ENA |
1611 WM8994_VMID_SEL_MASK, 0);
1612
1613 /* Discharge line */
1614 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1615 WM8994_LINEOUT1_DISCH |
1616 WM8994_LINEOUT2_DISCH,
1617 WM8994_LINEOUT1_DISCH |
1618 WM8994_LINEOUT2_DISCH);
1619
1620 msleep(5);
1621
1622 /* Switch off startup biases */
1623 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1624 WM8994_BIAS_SRC |
1625 WM8994_STARTUP_BIAS_ENA |
1626 WM8994_VMID_BUF_ENA |
1627 WM8994_VMID_RAMP_MASK, 0);
1628 }
1629 break;
1630 }
1631 codec->dapm.bias_level = level;
1632 return 0;
1633 }
1634
1635 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1636 {
1637 struct snd_soc_codec *codec = dai->codec;
1638 int ms_reg;
1639 int aif1_reg;
1640 int ms = 0;
1641 int aif1 = 0;
1642
1643 switch (dai->id) {
1644 case 1:
1645 ms_reg = WM8994_AIF1_MASTER_SLAVE;
1646 aif1_reg = WM8994_AIF1_CONTROL_1;
1647 break;
1648 case 2:
1649 ms_reg = WM8994_AIF2_MASTER_SLAVE;
1650 aif1_reg = WM8994_AIF2_CONTROL_1;
1651 break;
1652 default:
1653 return -EINVAL;
1654 }
1655
1656 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1657 case SND_SOC_DAIFMT_CBS_CFS:
1658 break;
1659 case SND_SOC_DAIFMT_CBM_CFM:
1660 ms = WM8994_AIF1_MSTR;
1661 break;
1662 default:
1663 return -EINVAL;
1664 }
1665
1666 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1667 case SND_SOC_DAIFMT_DSP_B:
1668 aif1 |= WM8994_AIF1_LRCLK_INV;
1669 case SND_SOC_DAIFMT_DSP_A:
1670 aif1 |= 0x18;
1671 break;
1672 case SND_SOC_DAIFMT_I2S:
1673 aif1 |= 0x10;
1674 break;
1675 case SND_SOC_DAIFMT_RIGHT_J:
1676 break;
1677 case SND_SOC_DAIFMT_LEFT_J:
1678 aif1 |= 0x8;
1679 break;
1680 default:
1681 return -EINVAL;
1682 }
1683
1684 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1685 case SND_SOC_DAIFMT_DSP_A:
1686 case SND_SOC_DAIFMT_DSP_B:
1687 /* frame inversion not valid for DSP modes */
1688 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1689 case SND_SOC_DAIFMT_NB_NF:
1690 break;
1691 case SND_SOC_DAIFMT_IB_NF:
1692 aif1 |= WM8994_AIF1_BCLK_INV;
1693 break;
1694 default:
1695 return -EINVAL;
1696 }
1697 break;
1698
1699 case SND_SOC_DAIFMT_I2S:
1700 case SND_SOC_DAIFMT_RIGHT_J:
1701 case SND_SOC_DAIFMT_LEFT_J:
1702 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1703 case SND_SOC_DAIFMT_NB_NF:
1704 break;
1705 case SND_SOC_DAIFMT_IB_IF:
1706 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
1707 break;
1708 case SND_SOC_DAIFMT_IB_NF:
1709 aif1 |= WM8994_AIF1_BCLK_INV;
1710 break;
1711 case SND_SOC_DAIFMT_NB_IF:
1712 aif1 |= WM8994_AIF1_LRCLK_INV;
1713 break;
1714 default:
1715 return -EINVAL;
1716 }
1717 break;
1718 default:
1719 return -EINVAL;
1720 }
1721
1722 snd_soc_update_bits(codec, aif1_reg,
1723 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
1724 WM8994_AIF1_FMT_MASK,
1725 aif1);
1726 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
1727 ms);
1728
1729 return 0;
1730 }
1731
1732 static struct {
1733 int val, rate;
1734 } srs[] = {
1735 { 0, 8000 },
1736 { 1, 11025 },
1737 { 2, 12000 },
1738 { 3, 16000 },
1739 { 4, 22050 },
1740 { 5, 24000 },
1741 { 6, 32000 },
1742 { 7, 44100 },
1743 { 8, 48000 },
1744 { 9, 88200 },
1745 { 10, 96000 },
1746 };
1747
1748 static int fs_ratios[] = {
1749 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
1750 };
1751
1752 static int bclk_divs[] = {
1753 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
1754 640, 880, 960, 1280, 1760, 1920
1755 };
1756
1757 static int wm8994_hw_params(struct snd_pcm_substream *substream,
1758 struct snd_pcm_hw_params *params,
1759 struct snd_soc_dai *dai)
1760 {
1761 struct snd_soc_codec *codec = dai->codec;
1762 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1763 int aif1_reg;
1764 int bclk_reg;
1765 int lrclk_reg;
1766 int rate_reg;
1767 int aif1 = 0;
1768 int bclk = 0;
1769 int lrclk = 0;
1770 int rate_val = 0;
1771 int id = dai->id - 1;
1772
1773 int i, cur_val, best_val, bclk_rate, best;
1774
1775 switch (dai->id) {
1776 case 1:
1777 aif1_reg = WM8994_AIF1_CONTROL_1;
1778 bclk_reg = WM8994_AIF1_BCLK;
1779 rate_reg = WM8994_AIF1_RATE;
1780 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1781 wm8994->lrclk_shared[0]) {
1782 lrclk_reg = WM8994_AIF1DAC_LRCLK;
1783 } else {
1784 lrclk_reg = WM8994_AIF1ADC_LRCLK;
1785 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
1786 }
1787 break;
1788 case 2:
1789 aif1_reg = WM8994_AIF2_CONTROL_1;
1790 bclk_reg = WM8994_AIF2_BCLK;
1791 rate_reg = WM8994_AIF2_RATE;
1792 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1793 wm8994->lrclk_shared[1]) {
1794 lrclk_reg = WM8994_AIF2DAC_LRCLK;
1795 } else {
1796 lrclk_reg = WM8994_AIF2ADC_LRCLK;
1797 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
1798 }
1799 break;
1800 default:
1801 return -EINVAL;
1802 }
1803
1804 bclk_rate = params_rate(params) * 2;
1805 switch (params_format(params)) {
1806 case SNDRV_PCM_FORMAT_S16_LE:
1807 bclk_rate *= 16;
1808 break;
1809 case SNDRV_PCM_FORMAT_S20_3LE:
1810 bclk_rate *= 20;
1811 aif1 |= 0x20;
1812 break;
1813 case SNDRV_PCM_FORMAT_S24_LE:
1814 bclk_rate *= 24;
1815 aif1 |= 0x40;
1816 break;
1817 case SNDRV_PCM_FORMAT_S32_LE:
1818 bclk_rate *= 32;
1819 aif1 |= 0x60;
1820 break;
1821 default:
1822 return -EINVAL;
1823 }
1824
1825 /* Try to find an appropriate sample rate; look for an exact match. */
1826 for (i = 0; i < ARRAY_SIZE(srs); i++)
1827 if (srs[i].rate == params_rate(params))
1828 break;
1829 if (i == ARRAY_SIZE(srs))
1830 return -EINVAL;
1831 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
1832
1833 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
1834 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
1835 dai->id, wm8994->aifclk[id], bclk_rate);
1836
1837 if (wm8994->aifclk[id] == 0) {
1838 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
1839 return -EINVAL;
1840 }
1841
1842 /* AIFCLK/fs ratio; look for a close match in either direction */
1843 best = 0;
1844 best_val = abs((fs_ratios[0] * params_rate(params))
1845 - wm8994->aifclk[id]);
1846 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
1847 cur_val = abs((fs_ratios[i] * params_rate(params))
1848 - wm8994->aifclk[id]);
1849 if (cur_val >= best_val)
1850 continue;
1851 best = i;
1852 best_val = cur_val;
1853 }
1854 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
1855 dai->id, fs_ratios[best]);
1856 rate_val |= best;
1857
1858 /* We may not get quite the right frequency if using
1859 * approximate clocks so look for the closest match that is
1860 * higher than the target (we need to ensure that there enough
1861 * BCLKs to clock out the samples).
1862 */
1863 best = 0;
1864 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1865 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
1866 if (cur_val < 0) /* BCLK table is sorted */
1867 break;
1868 best = i;
1869 }
1870 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
1871 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1872 bclk_divs[best], bclk_rate);
1873 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
1874
1875 lrclk = bclk_rate / params_rate(params);
1876 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1877 lrclk, bclk_rate / lrclk);
1878
1879 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
1880 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
1881 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
1882 lrclk);
1883 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
1884 WM8994_AIF1CLK_RATE_MASK, rate_val);
1885
1886 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1887 switch (dai->id) {
1888 case 1:
1889 wm8994->dac_rates[0] = params_rate(params);
1890 wm8994_set_retune_mobile(codec, 0);
1891 wm8994_set_retune_mobile(codec, 1);
1892 break;
1893 case 2:
1894 wm8994->dac_rates[1] = params_rate(params);
1895 wm8994_set_retune_mobile(codec, 2);
1896 break;
1897 }
1898 }
1899
1900 return 0;
1901 }
1902
1903 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
1904 {
1905 struct snd_soc_codec *codec = codec_dai->codec;
1906 int mute_reg;
1907 int reg;
1908
1909 switch (codec_dai->id) {
1910 case 1:
1911 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
1912 break;
1913 case 2:
1914 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
1915 break;
1916 default:
1917 return -EINVAL;
1918 }
1919
1920 if (mute)
1921 reg = WM8994_AIF1DAC1_MUTE;
1922 else
1923 reg = 0;
1924
1925 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
1926
1927 return 0;
1928 }
1929
1930 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
1931 {
1932 struct snd_soc_codec *codec = codec_dai->codec;
1933 int reg, val, mask;
1934
1935 switch (codec_dai->id) {
1936 case 1:
1937 reg = WM8994_AIF1_MASTER_SLAVE;
1938 mask = WM8994_AIF1_TRI;
1939 break;
1940 case 2:
1941 reg = WM8994_AIF2_MASTER_SLAVE;
1942 mask = WM8994_AIF2_TRI;
1943 break;
1944 case 3:
1945 reg = WM8994_POWER_MANAGEMENT_6;
1946 mask = WM8994_AIF3_TRI;
1947 break;
1948 default:
1949 return -EINVAL;
1950 }
1951
1952 if (tristate)
1953 val = mask;
1954 else
1955 val = 0;
1956
1957 return snd_soc_update_bits(codec, reg, mask, reg);
1958 }
1959
1960 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
1961
1962 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1963 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1964
1965 static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
1966 .set_sysclk = wm8994_set_dai_sysclk,
1967 .set_fmt = wm8994_set_dai_fmt,
1968 .hw_params = wm8994_hw_params,
1969 .digital_mute = wm8994_aif_mute,
1970 .set_pll = wm8994_set_fll,
1971 .set_tristate = wm8994_set_tristate,
1972 };
1973
1974 static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
1975 .set_sysclk = wm8994_set_dai_sysclk,
1976 .set_fmt = wm8994_set_dai_fmt,
1977 .hw_params = wm8994_hw_params,
1978 .digital_mute = wm8994_aif_mute,
1979 .set_pll = wm8994_set_fll,
1980 .set_tristate = wm8994_set_tristate,
1981 };
1982
1983 static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
1984 .set_tristate = wm8994_set_tristate,
1985 };
1986
1987 static struct snd_soc_dai_driver wm8994_dai[] = {
1988 {
1989 .name = "wm8994-aif1",
1990 .id = 1,
1991 .playback = {
1992 .stream_name = "AIF1 Playback",
1993 .channels_min = 2,
1994 .channels_max = 2,
1995 .rates = WM8994_RATES,
1996 .formats = WM8994_FORMATS,
1997 },
1998 .capture = {
1999 .stream_name = "AIF1 Capture",
2000 .channels_min = 2,
2001 .channels_max = 2,
2002 .rates = WM8994_RATES,
2003 .formats = WM8994_FORMATS,
2004 },
2005 .ops = &wm8994_aif1_dai_ops,
2006 },
2007 {
2008 .name = "wm8994-aif2",
2009 .id = 2,
2010 .playback = {
2011 .stream_name = "AIF2 Playback",
2012 .channels_min = 2,
2013 .channels_max = 2,
2014 .rates = WM8994_RATES,
2015 .formats = WM8994_FORMATS,
2016 },
2017 .capture = {
2018 .stream_name = "AIF2 Capture",
2019 .channels_min = 2,
2020 .channels_max = 2,
2021 .rates = WM8994_RATES,
2022 .formats = WM8994_FORMATS,
2023 },
2024 .ops = &wm8994_aif2_dai_ops,
2025 },
2026 {
2027 .name = "wm8994-aif3",
2028 .id = 3,
2029 .playback = {
2030 .stream_name = "AIF3 Playback",
2031 .channels_min = 2,
2032 .channels_max = 2,
2033 .rates = WM8994_RATES,
2034 .formats = WM8994_FORMATS,
2035 },
2036 .capture = {
2037 .stream_name = "AIF3 Capture",
2038 .channels_min = 2,
2039 .channels_max = 2,
2040 .rates = WM8994_RATES,
2041 .formats = WM8994_FORMATS,
2042 },
2043 .ops = &wm8994_aif3_dai_ops,
2044 }
2045 };
2046
2047 #ifdef CONFIG_PM
2048 static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
2049 {
2050 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2051 int i, ret;
2052
2053 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2054 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2055 sizeof(struct fll_config));
2056 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2057 if (ret < 0)
2058 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2059 i + 1, ret);
2060 }
2061
2062 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2063
2064 return 0;
2065 }
2066
2067 static int wm8994_resume(struct snd_soc_codec *codec)
2068 {
2069 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2070 u16 *reg_cache = codec->reg_cache;
2071 int i, ret;
2072
2073 /* Restore the registers */
2074 for (i = 1; i < ARRAY_SIZE(wm8994->reg_cache); i++) {
2075 switch (i) {
2076 case WM8994_LDO_1:
2077 case WM8994_LDO_2:
2078 case WM8994_SOFTWARE_RESET:
2079 /* Handled by other MFD drivers */
2080 continue;
2081 default:
2082 break;
2083 }
2084
2085 if (!wm8994_access_masks[i].writable)
2086 continue;
2087
2088 wm8994_reg_write(codec->control_data, i, reg_cache[i]);
2089 }
2090
2091 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2092
2093 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2094 if (!wm8994->fll_suspend[i].out)
2095 continue;
2096
2097 ret = _wm8994_set_fll(codec, i + 1,
2098 wm8994->fll_suspend[i].src,
2099 wm8994->fll_suspend[i].in,
2100 wm8994->fll_suspend[i].out);
2101 if (ret < 0)
2102 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2103 i + 1, ret);
2104 }
2105
2106 return 0;
2107 }
2108 #else
2109 #define wm8994_suspend NULL
2110 #define wm8994_resume NULL
2111 #endif
2112
2113 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2114 {
2115 struct snd_soc_codec *codec = wm8994->codec;
2116 struct wm8994_pdata *pdata = wm8994->pdata;
2117 struct snd_kcontrol_new controls[] = {
2118 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2119 wm8994->retune_mobile_enum,
2120 wm8994_get_retune_mobile_enum,
2121 wm8994_put_retune_mobile_enum),
2122 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2123 wm8994->retune_mobile_enum,
2124 wm8994_get_retune_mobile_enum,
2125 wm8994_put_retune_mobile_enum),
2126 SOC_ENUM_EXT("AIF2 EQ Mode",
2127 wm8994->retune_mobile_enum,
2128 wm8994_get_retune_mobile_enum,
2129 wm8994_put_retune_mobile_enum),
2130 };
2131 int ret, i, j;
2132 const char **t;
2133
2134 /* We need an array of texts for the enum API but the number
2135 * of texts is likely to be less than the number of
2136 * configurations due to the sample rate dependency of the
2137 * configurations. */
2138 wm8994->num_retune_mobile_texts = 0;
2139 wm8994->retune_mobile_texts = NULL;
2140 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2141 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2142 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2143 wm8994->retune_mobile_texts[j]) == 0)
2144 break;
2145 }
2146
2147 if (j != wm8994->num_retune_mobile_texts)
2148 continue;
2149
2150 /* Expand the array... */
2151 t = krealloc(wm8994->retune_mobile_texts,
2152 sizeof(char *) *
2153 (wm8994->num_retune_mobile_texts + 1),
2154 GFP_KERNEL);
2155 if (t == NULL)
2156 continue;
2157
2158 /* ...store the new entry... */
2159 t[wm8994->num_retune_mobile_texts] =
2160 pdata->retune_mobile_cfgs[i].name;
2161
2162 /* ...and remember the new version. */
2163 wm8994->num_retune_mobile_texts++;
2164 wm8994->retune_mobile_texts = t;
2165 }
2166
2167 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2168 wm8994->num_retune_mobile_texts);
2169
2170 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2171 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2172
2173 ret = snd_soc_add_controls(wm8994->codec, controls,
2174 ARRAY_SIZE(controls));
2175 if (ret != 0)
2176 dev_err(wm8994->codec->dev,
2177 "Failed to add ReTune Mobile controls: %d\n", ret);
2178 }
2179
2180 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2181 {
2182 struct snd_soc_codec *codec = wm8994->codec;
2183 struct wm8994_pdata *pdata = wm8994->pdata;
2184 int ret, i;
2185
2186 if (!pdata)
2187 return;
2188
2189 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2190 pdata->lineout2_diff,
2191 pdata->lineout1fb,
2192 pdata->lineout2fb,
2193 pdata->jd_scthr,
2194 pdata->jd_thr,
2195 pdata->micbias1_lvl,
2196 pdata->micbias2_lvl);
2197
2198 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2199
2200 if (pdata->num_drc_cfgs) {
2201 struct snd_kcontrol_new controls[] = {
2202 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2203 wm8994_get_drc_enum, wm8994_put_drc_enum),
2204 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2205 wm8994_get_drc_enum, wm8994_put_drc_enum),
2206 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2207 wm8994_get_drc_enum, wm8994_put_drc_enum),
2208 };
2209
2210 /* We need an array of texts for the enum API */
2211 wm8994->drc_texts = kmalloc(sizeof(char *)
2212 * pdata->num_drc_cfgs, GFP_KERNEL);
2213 if (!wm8994->drc_texts) {
2214 dev_err(wm8994->codec->dev,
2215 "Failed to allocate %d DRC config texts\n",
2216 pdata->num_drc_cfgs);
2217 return;
2218 }
2219
2220 for (i = 0; i < pdata->num_drc_cfgs; i++)
2221 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2222
2223 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2224 wm8994->drc_enum.texts = wm8994->drc_texts;
2225
2226 ret = snd_soc_add_controls(wm8994->codec, controls,
2227 ARRAY_SIZE(controls));
2228 if (ret != 0)
2229 dev_err(wm8994->codec->dev,
2230 "Failed to add DRC mode controls: %d\n", ret);
2231
2232 for (i = 0; i < WM8994_NUM_DRC; i++)
2233 wm8994_set_drc(codec, i);
2234 }
2235
2236 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2237 pdata->num_retune_mobile_cfgs);
2238
2239 if (pdata->num_retune_mobile_cfgs)
2240 wm8994_handle_retune_mobile_pdata(wm8994);
2241 else
2242 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
2243 ARRAY_SIZE(wm8994_eq_controls));
2244 }
2245
2246 /**
2247 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2248 *
2249 * @codec: WM8994 codec
2250 * @jack: jack to report detection events on
2251 * @micbias: microphone bias to detect on
2252 * @det: value to report for presence detection
2253 * @shrt: value to report for short detection
2254 *
2255 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
2256 * being used to bring out signals to the processor then only platform
2257 * data configuration is needed for WM8994 and processor GPIOs should
2258 * be configured using snd_soc_jack_add_gpios() instead.
2259 *
2260 * Configuration of detection levels is available via the micbias1_lvl
2261 * and micbias2_lvl platform data members.
2262 */
2263 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2264 int micbias, int det, int shrt)
2265 {
2266 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2267 struct wm8994_micdet *micdet;
2268 int reg;
2269
2270 switch (micbias) {
2271 case 1:
2272 micdet = &wm8994->micdet[0];
2273 break;
2274 case 2:
2275 micdet = &wm8994->micdet[1];
2276 break;
2277 default:
2278 return -EINVAL;
2279 }
2280
2281 dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2282 micbias, det, shrt);
2283
2284 /* Store the configuration */
2285 micdet->jack = jack;
2286 micdet->det = det;
2287 micdet->shrt = shrt;
2288
2289 /* If either of the jacks is set up then enable detection */
2290 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2291 reg = WM8994_MICD_ENA;
2292 else
2293 reg = 0;
2294
2295 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2296
2297 return 0;
2298 }
2299 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
2300
2301 static irqreturn_t wm8994_mic_irq(int irq, void *data)
2302 {
2303 struct wm8994_priv *priv = data;
2304 struct snd_soc_codec *codec = priv->codec;
2305 int reg;
2306 int report;
2307
2308 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2309 if (reg < 0) {
2310 dev_err(codec->dev, "Failed to read microphone status: %d\n",
2311 reg);
2312 return IRQ_HANDLED;
2313 }
2314
2315 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
2316
2317 report = 0;
2318 if (reg & WM8994_MIC1_DET_STS)
2319 report |= priv->micdet[0].det;
2320 if (reg & WM8994_MIC1_SHRT_STS)
2321 report |= priv->micdet[0].shrt;
2322 snd_soc_jack_report(priv->micdet[0].jack, report,
2323 priv->micdet[0].det | priv->micdet[0].shrt);
2324
2325 report = 0;
2326 if (reg & WM8994_MIC2_DET_STS)
2327 report |= priv->micdet[1].det;
2328 if (reg & WM8994_MIC2_SHRT_STS)
2329 report |= priv->micdet[1].shrt;
2330 snd_soc_jack_report(priv->micdet[1].jack, report,
2331 priv->micdet[1].det | priv->micdet[1].shrt);
2332
2333 return IRQ_HANDLED;
2334 }
2335
2336 static int wm8994_codec_probe(struct snd_soc_codec *codec)
2337 {
2338 struct wm8994_priv *wm8994;
2339 struct snd_soc_dapm_context *dapm = &codec->dapm;
2340 int ret, i;
2341
2342 codec->control_data = dev_get_drvdata(codec->dev->parent);
2343
2344 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
2345 if (wm8994 == NULL)
2346 return -ENOMEM;
2347 snd_soc_codec_set_drvdata(codec, wm8994);
2348
2349 codec->reg_cache = &wm8994->reg_cache;
2350
2351 wm8994->pdata = dev_get_platdata(codec->dev->parent);
2352 wm8994->codec = codec;
2353
2354 /* Fill the cache with physical values we inherited; don't reset */
2355 ret = wm8994_bulk_read(codec->control_data, 0,
2356 ARRAY_SIZE(wm8994->reg_cache) - 1,
2357 codec->reg_cache);
2358 if (ret < 0) {
2359 dev_err(codec->dev, "Failed to fill register cache: %d\n",
2360 ret);
2361 goto err;
2362 }
2363
2364 /* Clear the cached values for unreadable/volatile registers to
2365 * avoid potential confusion.
2366 */
2367 for (i = 0; i < ARRAY_SIZE(wm8994->reg_cache); i++)
2368 if (wm8994_volatile(i) || !wm8994_readable(i))
2369 wm8994->reg_cache[i] = 0;
2370
2371 /* Set revision-specific configuration */
2372 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
2373 switch (wm8994->revision) {
2374 case 2:
2375 case 3:
2376 wm8994->hubs.dcs_codes = -5;
2377 wm8994->hubs.hp_startup_mode = 1;
2378 wm8994->hubs.dcs_readback_mode = 1;
2379 break;
2380 default:
2381 wm8994->hubs.dcs_readback_mode = 1;
2382 break;
2383 }
2384
2385 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
2386 wm8994_mic_irq, "Mic 1 detect", wm8994);
2387 if (ret != 0)
2388 dev_warn(codec->dev,
2389 "Failed to request Mic1 detect IRQ: %d\n", ret);
2390
2391 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
2392 wm8994_mic_irq, "Mic 1 short", wm8994);
2393 if (ret != 0)
2394 dev_warn(codec->dev,
2395 "Failed to request Mic1 short IRQ: %d\n", ret);
2396
2397 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
2398 wm8994_mic_irq, "Mic 2 detect", wm8994);
2399 if (ret != 0)
2400 dev_warn(codec->dev,
2401 "Failed to request Mic2 detect IRQ: %d\n", ret);
2402
2403 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT,
2404 wm8994_mic_irq, "Mic 2 short", wm8994);
2405 if (ret != 0)
2406 dev_warn(codec->dev,
2407 "Failed to request Mic2 short IRQ: %d\n", ret);
2408
2409 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
2410 * configured on init - if a system wants to do this dynamically
2411 * at runtime we can deal with that then.
2412 */
2413 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
2414 if (ret < 0) {
2415 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
2416 goto err_irq;
2417 }
2418 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
2419 wm8994->lrclk_shared[0] = 1;
2420 wm8994_dai[0].symmetric_rates = 1;
2421 } else {
2422 wm8994->lrclk_shared[0] = 0;
2423 }
2424
2425 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
2426 if (ret < 0) {
2427 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
2428 goto err_irq;
2429 }
2430 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
2431 wm8994->lrclk_shared[1] = 1;
2432 wm8994_dai[1].symmetric_rates = 1;
2433 } else {
2434 wm8994->lrclk_shared[1] = 0;
2435 }
2436
2437 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2438
2439 /* Latch volume updates (right only; we always do left then right). */
2440 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
2441 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
2442 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
2443 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
2444 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
2445 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
2446 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
2447 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
2448 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
2449 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
2450 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
2451 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
2452 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
2453 WM8994_DAC1_VU, WM8994_DAC1_VU);
2454 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
2455 WM8994_DAC2_VU, WM8994_DAC2_VU);
2456
2457 /* Set the low bit of the 3D stereo depth so TLV matches */
2458 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
2459 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
2460 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
2461 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
2462 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
2463 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
2464 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
2465 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
2466 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
2467
2468 /* Unconditionally enable AIF1 ADC TDM mode; it only affects
2469 * behaviour on idle TDM clock cycles. */
2470 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
2471 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
2472
2473 wm8994_update_class_w(codec);
2474
2475 wm8994_handle_pdata(wm8994);
2476
2477 wm_hubs_add_analogue_controls(codec);
2478 snd_soc_add_controls(codec, wm8994_snd_controls,
2479 ARRAY_SIZE(wm8994_snd_controls));
2480 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
2481 ARRAY_SIZE(wm8994_dapm_widgets));
2482 wm_hubs_add_analogue_routes(codec, 0, 0);
2483 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
2484
2485 return 0;
2486
2487 err_irq:
2488 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
2489 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
2490 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
2491 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994);
2492 err:
2493 kfree(wm8994);
2494 return ret;
2495 }
2496
2497 static int wm8994_codec_remove(struct snd_soc_codec *codec)
2498 {
2499 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2500
2501 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2502
2503 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
2504 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
2505 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
2506 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994);
2507 kfree(wm8994);
2508
2509 return 0;
2510 }
2511
2512 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
2513 .probe = wm8994_codec_probe,
2514 .remove = wm8994_codec_remove,
2515 .suspend = wm8994_suspend,
2516 .resume = wm8994_resume,
2517 .read = wm8994_read,
2518 .write = wm8994_write,
2519 .set_bias_level = wm8994_set_bias_level,
2520 };
2521
2522 static int __devinit wm8994_probe(struct platform_device *pdev)
2523 {
2524 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
2525 wm8994_dai, ARRAY_SIZE(wm8994_dai));
2526 }
2527
2528 static int __devexit wm8994_remove(struct platform_device *pdev)
2529 {
2530 snd_soc_unregister_codec(&pdev->dev);
2531 return 0;
2532 }
2533
2534 static struct platform_driver wm8994_codec_driver = {
2535 .driver = {
2536 .name = "wm8994-codec",
2537 .owner = THIS_MODULE,
2538 },
2539 .probe = wm8994_probe,
2540 .remove = __devexit_p(wm8994_remove),
2541 };
2542
2543 static __init int wm8994_init(void)
2544 {
2545 return platform_driver_register(&wm8994_codec_driver);
2546 }
2547 module_init(wm8994_init);
2548
2549 static __exit void wm8994_exit(void)
2550 {
2551 platform_driver_unregister(&wm8994_codec_driver);
2552 }
2553 module_exit(wm8994_exit);
2554
2555
2556 MODULE_DESCRIPTION("ASoC WM8994 driver");
2557 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2558 MODULE_LICENSE("GPL");
2559 MODULE_ALIAS("platform:wm8994-codec");
Linux kernel - Deliverables
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