2 * wm8994.c -- WM8994 ALSA SoC Audio driver
4 * Copyright 2009 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/jack.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <trace/events/asoc.h>
33 #include <linux/mfd/wm8994/core.h>
34 #include <linux/mfd/wm8994/registers.h>
35 #include <linux/mfd/wm8994/pdata.h>
36 #include <linux/mfd/wm8994/gpio.h>
41 #define WM1811_JACKDET_MODE_NONE 0x0000
42 #define WM1811_JACKDET_MODE_JACK 0x0100
43 #define WM1811_JACKDET_MODE_MIC 0x0080
44 #define WM1811_JACKDET_MODE_AUDIO 0x0180
46 #define WM8994_NUM_DRC 3
47 #define WM8994_NUM_EQ 3
49 static int wm8994_drc_base
[] = {
55 static int wm8994_retune_mobile_base
[] = {
56 WM8994_AIF1_DAC1_EQ_GAINS_1
,
57 WM8994_AIF1_DAC2_EQ_GAINS_1
,
58 WM8994_AIF2_EQ_GAINS_1
,
61 static void wm8958_default_micdet(u16 status
, void *data
);
63 static const struct wm8958_micd_rate micdet_rates
[] = {
64 { 32768, true, 1, 4 },
65 { 32768, false, 1, 1 },
66 { 44100 * 256, true, 7, 10 },
67 { 44100 * 256, false, 7, 10 },
70 static const struct wm8958_micd_rate jackdet_rates
[] = {
71 { 32768, true, 0, 1 },
72 { 32768, false, 0, 1 },
73 { 44100 * 256, true, 7, 10 },
74 { 44100 * 256, false, 7, 10 },
77 static void wm8958_micd_set_rate(struct snd_soc_codec
*codec
)
79 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
80 int best
, i
, sysclk
, val
;
82 const struct wm8958_micd_rate
*rates
;
85 if (wm8994
->jack_cb
!= wm8958_default_micdet
)
88 idle
= !wm8994
->jack_mic
;
90 sysclk
= snd_soc_read(codec
, WM8994_CLOCKING_1
);
91 if (sysclk
& WM8994_SYSCLK_SRC
)
92 sysclk
= wm8994
->aifclk
[1];
94 sysclk
= wm8994
->aifclk
[0];
96 if (wm8994
->pdata
&& wm8994
->pdata
->micd_rates
) {
97 rates
= wm8994
->pdata
->micd_rates
;
98 num_rates
= wm8994
->pdata
->num_micd_rates
;
99 } else if (wm8994
->jackdet
) {
100 rates
= jackdet_rates
;
101 num_rates
= ARRAY_SIZE(jackdet_rates
);
103 rates
= micdet_rates
;
104 num_rates
= ARRAY_SIZE(micdet_rates
);
108 for (i
= 0; i
< num_rates
; i
++) {
109 if (rates
[i
].idle
!= idle
)
111 if (abs(rates
[i
].sysclk
- sysclk
) <
112 abs(rates
[best
].sysclk
- sysclk
))
114 else if (rates
[best
].idle
!= idle
)
118 val
= rates
[best
].start
<< WM8958_MICD_BIAS_STARTTIME_SHIFT
119 | rates
[best
].rate
<< WM8958_MICD_RATE_SHIFT
;
121 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
122 WM8958_MICD_BIAS_STARTTIME_MASK
|
123 WM8958_MICD_RATE_MASK
, val
);
126 static int configure_aif_clock(struct snd_soc_codec
*codec
, int aif
)
128 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
138 switch (wm8994
->sysclk
[aif
]) {
139 case WM8994_SYSCLK_MCLK1
:
140 rate
= wm8994
->mclk
[0];
143 case WM8994_SYSCLK_MCLK2
:
145 rate
= wm8994
->mclk
[1];
148 case WM8994_SYSCLK_FLL1
:
150 rate
= wm8994
->fll
[0].out
;
153 case WM8994_SYSCLK_FLL2
:
155 rate
= wm8994
->fll
[1].out
;
162 if (rate
>= 13500000) {
164 reg1
|= WM8994_AIF1CLK_DIV
;
166 dev_dbg(codec
->dev
, "Dividing AIF%d clock to %dHz\n",
170 wm8994
->aifclk
[aif
] = rate
;
172 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
+ offset
,
173 WM8994_AIF1CLK_SRC_MASK
| WM8994_AIF1CLK_DIV
,
179 static int configure_clock(struct snd_soc_codec
*codec
)
181 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
184 /* Bring up the AIF clocks first */
185 configure_aif_clock(codec
, 0);
186 configure_aif_clock(codec
, 1);
188 /* Then switch CLK_SYS over to the higher of them; a change
189 * can only happen as a result of a clocking change which can
190 * only be made outside of DAPM so we can safely redo the
194 /* If they're equal it doesn't matter which is used */
195 if (wm8994
->aifclk
[0] == wm8994
->aifclk
[1]) {
196 wm8958_micd_set_rate(codec
);
200 if (wm8994
->aifclk
[0] < wm8994
->aifclk
[1])
201 new = WM8994_SYSCLK_SRC
;
205 change
= snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
206 WM8994_SYSCLK_SRC
, new);
208 snd_soc_dapm_sync(&codec
->dapm
);
210 wm8958_micd_set_rate(codec
);
215 static int check_clk_sys(struct snd_soc_dapm_widget
*source
,
216 struct snd_soc_dapm_widget
*sink
)
218 int reg
= snd_soc_read(source
->codec
, WM8994_CLOCKING_1
);
221 /* Check what we're currently using for CLK_SYS */
222 if (reg
& WM8994_SYSCLK_SRC
)
227 return strcmp(source
->name
, clk
) == 0;
230 static const char *sidetone_hpf_text
[] = {
231 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
234 static const struct soc_enum sidetone_hpf
=
235 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 7, 7, sidetone_hpf_text
);
237 static const char *adc_hpf_text
[] = {
238 "HiFi", "Voice 1", "Voice 2", "Voice 3"
241 static const struct soc_enum aif1adc1_hpf
=
242 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS
, 13, 4, adc_hpf_text
);
244 static const struct soc_enum aif1adc2_hpf
=
245 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS
, 13, 4, adc_hpf_text
);
247 static const struct soc_enum aif2adc_hpf
=
248 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS
, 13, 4, adc_hpf_text
);
250 static const DECLARE_TLV_DB_SCALE(aif_tlv
, 0, 600, 0);
251 static const DECLARE_TLV_DB_SCALE(digital_tlv
, -7200, 75, 1);
252 static const DECLARE_TLV_DB_SCALE(st_tlv
, -3600, 300, 0);
253 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv
, -1600, 183, 0);
254 static const DECLARE_TLV_DB_SCALE(eq_tlv
, -1200, 100, 0);
255 static const DECLARE_TLV_DB_SCALE(ng_tlv
, -10200, 600, 0);
256 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv
, 0, 900, 0);
258 #define WM8994_DRC_SWITCH(xname, reg, shift) \
259 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
260 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
261 .put = wm8994_put_drc_sw, \
262 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
264 static int wm8994_put_drc_sw(struct snd_kcontrol
*kcontrol
,
265 struct snd_ctl_elem_value
*ucontrol
)
267 struct soc_mixer_control
*mc
=
268 (struct soc_mixer_control
*)kcontrol
->private_value
;
269 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
272 /* Can't enable both ADC and DAC paths simultaneously */
273 if (mc
->shift
== WM8994_AIF1DAC1_DRC_ENA_SHIFT
)
274 mask
= WM8994_AIF1ADC1L_DRC_ENA_MASK
|
275 WM8994_AIF1ADC1R_DRC_ENA_MASK
;
277 mask
= WM8994_AIF1DAC1_DRC_ENA_MASK
;
279 ret
= snd_soc_read(codec
, mc
->reg
);
285 return snd_soc_put_volsw(kcontrol
, ucontrol
);
288 static void wm8994_set_drc(struct snd_soc_codec
*codec
, int drc
)
290 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
291 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
292 int base
= wm8994_drc_base
[drc
];
293 int cfg
= wm8994
->drc_cfg
[drc
];
296 /* Save any enables; the configuration should clear them. */
297 save
= snd_soc_read(codec
, base
);
298 save
&= WM8994_AIF1DAC1_DRC_ENA
| WM8994_AIF1ADC1L_DRC_ENA
|
299 WM8994_AIF1ADC1R_DRC_ENA
;
301 for (i
= 0; i
< WM8994_DRC_REGS
; i
++)
302 snd_soc_update_bits(codec
, base
+ i
, 0xffff,
303 pdata
->drc_cfgs
[cfg
].regs
[i
]);
305 snd_soc_update_bits(codec
, base
, WM8994_AIF1DAC1_DRC_ENA
|
306 WM8994_AIF1ADC1L_DRC_ENA
|
307 WM8994_AIF1ADC1R_DRC_ENA
, save
);
310 /* Icky as hell but saves code duplication */
311 static int wm8994_get_drc(const char *name
)
313 if (strcmp(name
, "AIF1DRC1 Mode") == 0)
315 if (strcmp(name
, "AIF1DRC2 Mode") == 0)
317 if (strcmp(name
, "AIF2DRC Mode") == 0)
322 static int wm8994_put_drc_enum(struct snd_kcontrol
*kcontrol
,
323 struct snd_ctl_elem_value
*ucontrol
)
325 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
326 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
327 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
328 int drc
= wm8994_get_drc(kcontrol
->id
.name
);
329 int value
= ucontrol
->value
.integer
.value
[0];
334 if (value
>= pdata
->num_drc_cfgs
)
337 wm8994
->drc_cfg
[drc
] = value
;
339 wm8994_set_drc(codec
, drc
);
344 static int wm8994_get_drc_enum(struct snd_kcontrol
*kcontrol
,
345 struct snd_ctl_elem_value
*ucontrol
)
347 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
348 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
349 int drc
= wm8994_get_drc(kcontrol
->id
.name
);
351 ucontrol
->value
.enumerated
.item
[0] = wm8994
->drc_cfg
[drc
];
356 static void wm8994_set_retune_mobile(struct snd_soc_codec
*codec
, int block
)
358 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
359 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
360 int base
= wm8994_retune_mobile_base
[block
];
361 int iface
, best
, best_val
, save
, i
, cfg
;
363 if (!pdata
|| !wm8994
->num_retune_mobile_texts
)
378 /* Find the version of the currently selected configuration
379 * with the nearest sample rate. */
380 cfg
= wm8994
->retune_mobile_cfg
[block
];
383 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
384 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
385 wm8994
->retune_mobile_texts
[cfg
]) == 0 &&
386 abs(pdata
->retune_mobile_cfgs
[i
].rate
387 - wm8994
->dac_rates
[iface
]) < best_val
) {
389 best_val
= abs(pdata
->retune_mobile_cfgs
[i
].rate
390 - wm8994
->dac_rates
[iface
]);
394 dev_dbg(codec
->dev
, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
396 pdata
->retune_mobile_cfgs
[best
].name
,
397 pdata
->retune_mobile_cfgs
[best
].rate
,
398 wm8994
->dac_rates
[iface
]);
400 /* The EQ will be disabled while reconfiguring it, remember the
401 * current configuration.
403 save
= snd_soc_read(codec
, base
);
404 save
&= WM8994_AIF1DAC1_EQ_ENA
;
406 for (i
= 0; i
< WM8994_EQ_REGS
; i
++)
407 snd_soc_update_bits(codec
, base
+ i
, 0xffff,
408 pdata
->retune_mobile_cfgs
[best
].regs
[i
]);
410 snd_soc_update_bits(codec
, base
, WM8994_AIF1DAC1_EQ_ENA
, save
);
413 /* Icky as hell but saves code duplication */
414 static int wm8994_get_retune_mobile_block(const char *name
)
416 if (strcmp(name
, "AIF1.1 EQ Mode") == 0)
418 if (strcmp(name
, "AIF1.2 EQ Mode") == 0)
420 if (strcmp(name
, "AIF2 EQ Mode") == 0)
425 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
426 struct snd_ctl_elem_value
*ucontrol
)
428 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
429 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
430 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
431 int block
= wm8994_get_retune_mobile_block(kcontrol
->id
.name
);
432 int value
= ucontrol
->value
.integer
.value
[0];
437 if (value
>= pdata
->num_retune_mobile_cfgs
)
440 wm8994
->retune_mobile_cfg
[block
] = value
;
442 wm8994_set_retune_mobile(codec
, block
);
447 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
448 struct snd_ctl_elem_value
*ucontrol
)
450 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
451 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
452 int block
= wm8994_get_retune_mobile_block(kcontrol
->id
.name
);
454 ucontrol
->value
.enumerated
.item
[0] = wm8994
->retune_mobile_cfg
[block
];
459 static const char *aif_chan_src_text
[] = {
463 static const struct soc_enum aif1adcl_src
=
464 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1
, 15, 2, aif_chan_src_text
);
466 static const struct soc_enum aif1adcr_src
=
467 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1
, 14, 2, aif_chan_src_text
);
469 static const struct soc_enum aif2adcl_src
=
470 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1
, 15, 2, aif_chan_src_text
);
472 static const struct soc_enum aif2adcr_src
=
473 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1
, 14, 2, aif_chan_src_text
);
475 static const struct soc_enum aif1dacl_src
=
476 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2
, 15, 2, aif_chan_src_text
);
478 static const struct soc_enum aif1dacr_src
=
479 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2
, 14, 2, aif_chan_src_text
);
481 static const struct soc_enum aif2dacl_src
=
482 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2
, 15, 2, aif_chan_src_text
);
484 static const struct soc_enum aif2dacr_src
=
485 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2
, 14, 2, aif_chan_src_text
);
487 static const char *osr_text
[] = {
488 "Low Power", "High Performance",
491 static const struct soc_enum dac_osr
=
492 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING
, 0, 2, osr_text
);
494 static const struct soc_enum adc_osr
=
495 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING
, 1, 2, osr_text
);
497 static const struct snd_kcontrol_new wm8994_snd_controls
[] = {
498 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME
,
499 WM8994_AIF1_ADC1_RIGHT_VOLUME
,
500 1, 119, 0, digital_tlv
),
501 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME
,
502 WM8994_AIF1_ADC2_RIGHT_VOLUME
,
503 1, 119, 0, digital_tlv
),
504 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME
,
505 WM8994_AIF2_ADC_RIGHT_VOLUME
,
506 1, 119, 0, digital_tlv
),
508 SOC_ENUM("AIF1ADCL Source", aif1adcl_src
),
509 SOC_ENUM("AIF1ADCR Source", aif1adcr_src
),
510 SOC_ENUM("AIF2ADCL Source", aif2adcl_src
),
511 SOC_ENUM("AIF2ADCR Source", aif2adcr_src
),
513 SOC_ENUM("AIF1DACL Source", aif1dacl_src
),
514 SOC_ENUM("AIF1DACR Source", aif1dacr_src
),
515 SOC_ENUM("AIF2DACL Source", aif2dacl_src
),
516 SOC_ENUM("AIF2DACR Source", aif2dacr_src
),
518 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME
,
519 WM8994_AIF1_DAC1_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
520 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME
,
521 WM8994_AIF1_DAC2_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
522 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME
,
523 WM8994_AIF2_DAC_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
525 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2
, 10, 3, 0, aif_tlv
),
526 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2
, 10, 3, 0, aif_tlv
),
528 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1
, 0, 1, 0),
529 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1
, 0, 1, 0),
530 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1
, 0, 1, 0),
532 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1
, 2),
533 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1
, 1),
534 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1
, 0),
536 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1
, 2),
537 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1
, 1),
538 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1
, 0),
540 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1
, 2),
541 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1
, 1),
542 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1
, 0),
544 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES
,
546 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES
,
548 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES
,
550 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES
,
552 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf
),
553 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE
, 6, 1, 0),
555 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf
),
556 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS
, 12, 11, 1, 0),
558 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf
),
559 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS
, 12, 11, 1, 0),
561 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf
),
562 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS
, 12, 11, 1, 0),
564 SOC_ENUM("ADC OSR", adc_osr
),
565 SOC_ENUM("DAC OSR", dac_osr
),
567 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME
,
568 WM8994_DAC1_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
569 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME
,
570 WM8994_DAC1_RIGHT_VOLUME
, 9, 1, 1),
572 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME
,
573 WM8994_DAC2_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
574 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME
,
575 WM8994_DAC2_RIGHT_VOLUME
, 9, 1, 1),
577 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION
,
578 6, 1, 1, wm_hubs_spkmix_tlv
),
579 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION
,
580 2, 1, 1, wm_hubs_spkmix_tlv
),
582 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION
,
583 6, 1, 1, wm_hubs_spkmix_tlv
),
584 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION
,
585 2, 1, 1, wm_hubs_spkmix_tlv
),
587 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2
,
588 10, 15, 0, wm8994_3d_tlv
),
589 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2
,
591 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2
,
592 10, 15, 0, wm8994_3d_tlv
),
593 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2
,
595 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2
,
596 10, 15, 0, wm8994_3d_tlv
),
597 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2
,
601 static const struct snd_kcontrol_new wm8994_eq_controls
[] = {
602 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 11, 31, 0,
604 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 6, 31, 0,
606 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 1, 31, 0,
608 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2
, 11, 31, 0,
610 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2
, 6, 31, 0,
613 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 11, 31, 0,
615 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 6, 31, 0,
617 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 1, 31, 0,
619 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2
, 11, 31, 0,
621 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2
, 6, 31, 0,
624 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1
, 11, 31, 0,
626 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1
, 6, 31, 0,
628 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1
, 1, 31, 0,
630 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2
, 11, 31, 0,
632 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2
, 6, 31, 0,
636 static const char *wm8958_ng_text
[] = {
637 "30ms", "125ms", "250ms", "500ms",
640 static const struct soc_enum wm8958_aif1dac1_ng_hold
=
641 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE
,
642 WM8958_AIF1DAC1_NG_THR_SHIFT
, 4, wm8958_ng_text
);
644 static const struct soc_enum wm8958_aif1dac2_ng_hold
=
645 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE
,
646 WM8958_AIF1DAC2_NG_THR_SHIFT
, 4, wm8958_ng_text
);
648 static const struct soc_enum wm8958_aif2dac_ng_hold
=
649 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE
,
650 WM8958_AIF2DAC_NG_THR_SHIFT
, 4, wm8958_ng_text
);
652 static const struct snd_kcontrol_new wm8958_snd_controls
[] = {
653 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2
, 10, 3, 0, aif_tlv
),
655 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE
,
656 WM8958_AIF1DAC1_NG_ENA_SHIFT
, 1, 0),
657 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold
),
658 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
659 WM8958_AIF1_DAC1_NOISE_GATE
, WM8958_AIF1DAC1_NG_THR_SHIFT
,
662 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE
,
663 WM8958_AIF1DAC2_NG_ENA_SHIFT
, 1, 0),
664 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold
),
665 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
666 WM8958_AIF1_DAC2_NOISE_GATE
, WM8958_AIF1DAC2_NG_THR_SHIFT
,
669 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE
,
670 WM8958_AIF2DAC_NG_ENA_SHIFT
, 1, 0),
671 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold
),
672 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
673 WM8958_AIF2_DAC_NOISE_GATE
, WM8958_AIF2DAC_NG_THR_SHIFT
,
677 static const struct snd_kcontrol_new wm1811_snd_controls
[] = {
678 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1
, 7, 1, 0,
680 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1
, 8, 1, 0,
684 /* We run all mode setting through a function to enforce audio mode */
685 static void wm1811_jackdet_set_mode(struct snd_soc_codec
*codec
, u16 mode
)
687 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
689 if (wm8994
->active_refcount
)
690 mode
= WM1811_JACKDET_MODE_AUDIO
;
692 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
693 WM1811_JACKDET_MODE_MASK
, mode
);
695 if (mode
== WM1811_JACKDET_MODE_MIC
)
699 static void active_reference(struct snd_soc_codec
*codec
)
701 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
703 mutex_lock(&wm8994
->accdet_lock
);
705 wm8994
->active_refcount
++;
707 dev_dbg(codec
->dev
, "Active refcount incremented, now %d\n",
708 wm8994
->active_refcount
);
710 if (wm8994
->active_refcount
== 1) {
711 /* If we're using jack detection go into audio mode */
712 if (wm8994
->jackdet
&& wm8994
->jack_cb
) {
713 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
714 WM1811_JACKDET_MODE_MASK
,
715 WM1811_JACKDET_MODE_AUDIO
);
720 mutex_unlock(&wm8994
->accdet_lock
);
723 static void active_dereference(struct snd_soc_codec
*codec
)
725 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
728 mutex_lock(&wm8994
->accdet_lock
);
730 wm8994
->active_refcount
--;
732 dev_dbg(codec
->dev
, "Active refcount decremented, now %d\n",
733 wm8994
->active_refcount
);
735 if (wm8994
->active_refcount
== 0) {
736 /* Go into appropriate detection only mode */
737 if (wm8994
->jackdet
&& wm8994
->jack_cb
) {
738 if (wm8994
->jack_mic
|| wm8994
->mic_detecting
)
739 mode
= WM1811_JACKDET_MODE_MIC
;
741 mode
= WM1811_JACKDET_MODE_JACK
;
743 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
744 WM1811_JACKDET_MODE_MASK
,
749 mutex_unlock(&wm8994
->accdet_lock
);
752 static int clk_sys_event(struct snd_soc_dapm_widget
*w
,
753 struct snd_kcontrol
*kcontrol
, int event
)
755 struct snd_soc_codec
*codec
= w
->codec
;
758 case SND_SOC_DAPM_PRE_PMU
:
759 return configure_clock(codec
);
761 case SND_SOC_DAPM_POST_PMD
:
762 configure_clock(codec
);
769 static void vmid_reference(struct snd_soc_codec
*codec
)
771 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
773 wm8994
->vmid_refcount
++;
775 dev_dbg(codec
->dev
, "Referencing VMID, refcount is now %d\n",
776 wm8994
->vmid_refcount
);
778 if (wm8994
->vmid_refcount
== 1) {
779 /* Startup bias, VMID ramp & buffer */
780 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
781 WM8994_STARTUP_BIAS_ENA
|
782 WM8994_VMID_BUF_ENA
|
783 WM8994_VMID_RAMP_MASK
,
784 WM8994_STARTUP_BIAS_ENA
|
785 WM8994_VMID_BUF_ENA
|
786 (0x11 << WM8994_VMID_RAMP_SHIFT
));
788 /* Main bias enable, VMID=2x40k */
789 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
791 WM8994_VMID_SEL_MASK
,
792 WM8994_BIAS_ENA
| 0x2);
798 static void vmid_dereference(struct snd_soc_codec
*codec
)
800 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
802 wm8994
->vmid_refcount
--;
804 dev_dbg(codec
->dev
, "Dereferencing VMID, refcount is now %d\n",
805 wm8994
->vmid_refcount
);
807 if (wm8994
->vmid_refcount
== 0) {
808 /* Switch over to startup biases */
809 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
811 WM8994_STARTUP_BIAS_ENA
|
812 WM8994_VMID_BUF_ENA
|
813 WM8994_VMID_RAMP_MASK
,
815 WM8994_STARTUP_BIAS_ENA
|
816 WM8994_VMID_BUF_ENA
|
817 (1 << WM8994_VMID_RAMP_SHIFT
));
819 /* Disable main biases */
820 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
822 WM8994_VMID_SEL_MASK
, 0);
825 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
826 WM8994_LINEOUT1_DISCH
|
827 WM8994_LINEOUT2_DISCH
,
828 WM8994_LINEOUT1_DISCH
|
829 WM8994_LINEOUT2_DISCH
);
833 /* Switch off startup biases */
834 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
836 WM8994_STARTUP_BIAS_ENA
|
837 WM8994_VMID_BUF_ENA
|
838 WM8994_VMID_RAMP_MASK
, 0);
842 static int vmid_event(struct snd_soc_dapm_widget
*w
,
843 struct snd_kcontrol
*kcontrol
, int event
)
845 struct snd_soc_codec
*codec
= w
->codec
;
848 case SND_SOC_DAPM_PRE_PMU
:
849 vmid_reference(codec
);
852 case SND_SOC_DAPM_POST_PMD
:
853 vmid_dereference(codec
);
860 static void wm8994_update_class_w(struct snd_soc_codec
*codec
)
862 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
864 int source
= 0; /* GCC flow analysis can't track enable */
867 /* Only support direct DAC->headphone paths */
868 reg
= snd_soc_read(codec
, WM8994_OUTPUT_MIXER_1
);
869 if (!(reg
& WM8994_DAC1L_TO_HPOUT1L
)) {
870 dev_vdbg(codec
->dev
, "HPL connected to output mixer\n");
874 reg
= snd_soc_read(codec
, WM8994_OUTPUT_MIXER_2
);
875 if (!(reg
& WM8994_DAC1R_TO_HPOUT1R
)) {
876 dev_vdbg(codec
->dev
, "HPR connected to output mixer\n");
880 /* We also need the same setting for L/R and only one path */
881 reg
= snd_soc_read(codec
, WM8994_DAC1_LEFT_MIXER_ROUTING
);
883 case WM8994_AIF2DACL_TO_DAC1L
:
884 dev_vdbg(codec
->dev
, "Class W source AIF2DAC\n");
885 source
= 2 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
887 case WM8994_AIF1DAC2L_TO_DAC1L
:
888 dev_vdbg(codec
->dev
, "Class W source AIF1DAC2\n");
889 source
= 1 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
891 case WM8994_AIF1DAC1L_TO_DAC1L
:
892 dev_vdbg(codec
->dev
, "Class W source AIF1DAC1\n");
893 source
= 0 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
896 dev_vdbg(codec
->dev
, "DAC mixer setting: %x\n", reg
);
901 reg_r
= snd_soc_read(codec
, WM8994_DAC1_RIGHT_MIXER_ROUTING
);
903 dev_vdbg(codec
->dev
, "Left and right DAC mixers different\n");
908 dev_dbg(codec
->dev
, "Class W enabled\n");
909 snd_soc_update_bits(codec
, WM8994_CLASS_W_1
,
911 WM8994_CP_DYN_SRC_SEL_MASK
,
912 source
| WM8994_CP_DYN_PWR
);
913 wm8994
->hubs
.class_w
= true;
916 dev_dbg(codec
->dev
, "Class W disabled\n");
917 snd_soc_update_bits(codec
, WM8994_CLASS_W_1
,
918 WM8994_CP_DYN_PWR
, 0);
919 wm8994
->hubs
.class_w
= false;
923 static int late_enable_ev(struct snd_soc_dapm_widget
*w
,
924 struct snd_kcontrol
*kcontrol
, int event
)
926 struct snd_soc_codec
*codec
= w
->codec
;
927 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
930 case SND_SOC_DAPM_PRE_PMU
:
931 if (wm8994
->aif1clk_enable
) {
932 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
933 WM8994_AIF1CLK_ENA_MASK
,
935 wm8994
->aif1clk_enable
= 0;
937 if (wm8994
->aif2clk_enable
) {
938 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
939 WM8994_AIF2CLK_ENA_MASK
,
941 wm8994
->aif2clk_enable
= 0;
946 /* We may also have postponed startup of DSP, handle that. */
947 wm8958_aif_ev(w
, kcontrol
, event
);
952 static int late_disable_ev(struct snd_soc_dapm_widget
*w
,
953 struct snd_kcontrol
*kcontrol
, int event
)
955 struct snd_soc_codec
*codec
= w
->codec
;
956 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
959 case SND_SOC_DAPM_POST_PMD
:
960 if (wm8994
->aif1clk_disable
) {
961 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
962 WM8994_AIF1CLK_ENA_MASK
, 0);
963 wm8994
->aif1clk_disable
= 0;
965 if (wm8994
->aif2clk_disable
) {
966 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
967 WM8994_AIF2CLK_ENA_MASK
, 0);
968 wm8994
->aif2clk_disable
= 0;
976 static int aif1clk_ev(struct snd_soc_dapm_widget
*w
,
977 struct snd_kcontrol
*kcontrol
, int event
)
979 struct snd_soc_codec
*codec
= w
->codec
;
980 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
983 case SND_SOC_DAPM_PRE_PMU
:
984 wm8994
->aif1clk_enable
= 1;
986 case SND_SOC_DAPM_POST_PMD
:
987 wm8994
->aif1clk_disable
= 1;
994 static int aif2clk_ev(struct snd_soc_dapm_widget
*w
,
995 struct snd_kcontrol
*kcontrol
, int event
)
997 struct snd_soc_codec
*codec
= w
->codec
;
998 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1001 case SND_SOC_DAPM_PRE_PMU
:
1002 wm8994
->aif2clk_enable
= 1;
1004 case SND_SOC_DAPM_POST_PMD
:
1005 wm8994
->aif2clk_disable
= 1;
1012 static int adc_mux_ev(struct snd_soc_dapm_widget
*w
,
1013 struct snd_kcontrol
*kcontrol
, int event
)
1015 late_enable_ev(w
, kcontrol
, event
);
1019 static int micbias_ev(struct snd_soc_dapm_widget
*w
,
1020 struct snd_kcontrol
*kcontrol
, int event
)
1022 late_enable_ev(w
, kcontrol
, event
);
1026 static int dac_ev(struct snd_soc_dapm_widget
*w
,
1027 struct snd_kcontrol
*kcontrol
, int event
)
1029 struct snd_soc_codec
*codec
= w
->codec
;
1030 unsigned int mask
= 1 << w
->shift
;
1032 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1037 static const char *hp_mux_text
[] = {
1042 #define WM8994_HP_ENUM(xname, xenum) \
1043 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1044 .info = snd_soc_info_enum_double, \
1045 .get = snd_soc_dapm_get_enum_double, \
1046 .put = wm8994_put_hp_enum, \
1047 .private_value = (unsigned long)&xenum }
1049 static int wm8994_put_hp_enum(struct snd_kcontrol
*kcontrol
,
1050 struct snd_ctl_elem_value
*ucontrol
)
1052 struct snd_soc_dapm_widget_list
*wlist
= snd_kcontrol_chip(kcontrol
);
1053 struct snd_soc_dapm_widget
*w
= wlist
->widgets
[0];
1054 struct snd_soc_codec
*codec
= w
->codec
;
1057 ret
= snd_soc_dapm_put_enum_double(kcontrol
, ucontrol
);
1059 wm8994_update_class_w(codec
);
1064 static const struct soc_enum hpl_enum
=
1065 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1
, 8, 2, hp_mux_text
);
1067 static const struct snd_kcontrol_new hpl_mux
=
1068 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum
);
1070 static const struct soc_enum hpr_enum
=
1071 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2
, 8, 2, hp_mux_text
);
1073 static const struct snd_kcontrol_new hpr_mux
=
1074 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum
);
1076 static const char *adc_mux_text
[] = {
1081 static const struct soc_enum adc_enum
=
1082 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text
);
1084 static const struct snd_kcontrol_new adcl_mux
=
1085 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum
);
1087 static const struct snd_kcontrol_new adcr_mux
=
1088 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum
);
1090 static const struct snd_kcontrol_new left_speaker_mixer
[] = {
1091 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER
, 9, 1, 0),
1092 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER
, 7, 1, 0),
1093 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER
, 5, 1, 0),
1094 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER
, 3, 1, 0),
1095 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER
, 1, 1, 0),
1098 static const struct snd_kcontrol_new right_speaker_mixer
[] = {
1099 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER
, 8, 1, 0),
1100 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER
, 6, 1, 0),
1101 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER
, 4, 1, 0),
1102 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER
, 2, 1, 0),
1103 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER
, 0, 1, 0),
1106 /* Debugging; dump chip status after DAPM transitions */
1107 static int post_ev(struct snd_soc_dapm_widget
*w
,
1108 struct snd_kcontrol
*kcontrol
, int event
)
1110 struct snd_soc_codec
*codec
= w
->codec
;
1111 dev_dbg(codec
->dev
, "SRC status: %x\n",
1113 WM8994_RATE_STATUS
));
1117 static const struct snd_kcontrol_new aif1adc1l_mix
[] = {
1118 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING
,
1120 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING
,
1124 static const struct snd_kcontrol_new aif1adc1r_mix
[] = {
1125 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING
,
1127 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING
,
1131 static const struct snd_kcontrol_new aif1adc2l_mix
[] = {
1132 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING
,
1134 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING
,
1138 static const struct snd_kcontrol_new aif1adc2r_mix
[] = {
1139 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING
,
1141 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING
,
1145 static const struct snd_kcontrol_new aif2dac2l_mix
[] = {
1146 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1148 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1150 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1152 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1154 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1158 static const struct snd_kcontrol_new aif2dac2r_mix
[] = {
1159 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1161 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1163 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1165 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1167 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1171 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1172 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1173 .info = snd_soc_info_volsw, \
1174 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1175 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1177 static int wm8994_put_class_w(struct snd_kcontrol
*kcontrol
,
1178 struct snd_ctl_elem_value
*ucontrol
)
1180 struct snd_soc_dapm_widget_list
*wlist
= snd_kcontrol_chip(kcontrol
);
1181 struct snd_soc_dapm_widget
*w
= wlist
->widgets
[0];
1182 struct snd_soc_codec
*codec
= w
->codec
;
1185 ret
= snd_soc_dapm_put_volsw(kcontrol
, ucontrol
);
1187 wm8994_update_class_w(codec
);
1192 static const struct snd_kcontrol_new dac1l_mix
[] = {
1193 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1195 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1197 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1199 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1201 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1205 static const struct snd_kcontrol_new dac1r_mix
[] = {
1206 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1208 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1210 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1212 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1214 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1218 static const char *sidetone_text
[] = {
1219 "ADC/DMIC1", "DMIC2",
1222 static const struct soc_enum sidetone1_enum
=
1223 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 0, 2, sidetone_text
);
1225 static const struct snd_kcontrol_new sidetone1_mux
=
1226 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum
);
1228 static const struct soc_enum sidetone2_enum
=
1229 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 1, 2, sidetone_text
);
1231 static const struct snd_kcontrol_new sidetone2_mux
=
1232 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum
);
1234 static const char *aif1dac_text
[] = {
1235 "AIF1DACDAT", "AIF3DACDAT",
1238 static const struct soc_enum aif1dac_enum
=
1239 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 0, 2, aif1dac_text
);
1241 static const struct snd_kcontrol_new aif1dac_mux
=
1242 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum
);
1244 static const char *aif2dac_text
[] = {
1245 "AIF2DACDAT", "AIF3DACDAT",
1248 static const struct soc_enum aif2dac_enum
=
1249 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 1, 2, aif2dac_text
);
1251 static const struct snd_kcontrol_new aif2dac_mux
=
1252 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum
);
1254 static const char *aif2adc_text
[] = {
1255 "AIF2ADCDAT", "AIF3DACDAT",
1258 static const struct soc_enum aif2adc_enum
=
1259 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 2, 2, aif2adc_text
);
1261 static const struct snd_kcontrol_new aif2adc_mux
=
1262 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum
);
1264 static const char *aif3adc_text
[] = {
1265 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1268 static const struct soc_enum wm8994_aif3adc_enum
=
1269 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 3, 3, aif3adc_text
);
1271 static const struct snd_kcontrol_new wm8994_aif3adc_mux
=
1272 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum
);
1274 static const struct soc_enum wm8958_aif3adc_enum
=
1275 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 3, 4, aif3adc_text
);
1277 static const struct snd_kcontrol_new wm8958_aif3adc_mux
=
1278 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum
);
1280 static const char *mono_pcm_out_text
[] = {
1281 "None", "AIF2ADCL", "AIF2ADCR",
1284 static const struct soc_enum mono_pcm_out_enum
=
1285 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 9, 3, mono_pcm_out_text
);
1287 static const struct snd_kcontrol_new mono_pcm_out_mux
=
1288 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum
);
1290 static const char *aif2dac_src_text
[] = {
1294 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1295 static const struct soc_enum aif2dacl_src_enum
=
1296 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 7, 2, aif2dac_src_text
);
1298 static const struct snd_kcontrol_new aif2dacl_src_mux
=
1299 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum
);
1301 static const struct soc_enum aif2dacr_src_enum
=
1302 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 8, 2, aif2dac_src_text
);
1304 static const struct snd_kcontrol_new aif2dacr_src_mux
=
1305 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum
);
1307 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets
[] = {
1308 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM
, 0, 0, aif1clk_ev
,
1309 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1310 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM
, 0, 0, aif2clk_ev
,
1311 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1313 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1314 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1315 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1316 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1317 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1318 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1319 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1320 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1321 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1322 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1324 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3
, 8, 0,
1325 left_speaker_mixer
, ARRAY_SIZE(left_speaker_mixer
),
1326 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1327 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3
, 9, 0,
1328 right_speaker_mixer
, ARRAY_SIZE(right_speaker_mixer
),
1329 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1330 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM
, 0, 0, &hpl_mux
,
1331 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1332 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM
, 0, 0, &hpr_mux
,
1333 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1335 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev
)
1338 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets
[] = {
1339 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1
, 0, 0, NULL
, 0),
1340 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1
, 0, 0, NULL
, 0),
1341 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM
, 0, 0, NULL
, 0),
1342 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3
, 8, 0,
1343 left_speaker_mixer
, ARRAY_SIZE(left_speaker_mixer
)),
1344 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3
, 9, 0,
1345 right_speaker_mixer
, ARRAY_SIZE(right_speaker_mixer
)),
1346 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM
, 0, 0, &hpl_mux
),
1347 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM
, 0, 0, &hpr_mux
),
1350 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets
[] = {
1351 SND_SOC_DAPM_DAC_E("DAC2L", NULL
, SND_SOC_NOPM
, 3, 0,
1352 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1353 SND_SOC_DAPM_DAC_E("DAC2R", NULL
, SND_SOC_NOPM
, 2, 0,
1354 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1355 SND_SOC_DAPM_DAC_E("DAC1L", NULL
, SND_SOC_NOPM
, 1, 0,
1356 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1357 SND_SOC_DAPM_DAC_E("DAC1R", NULL
, SND_SOC_NOPM
, 0, 0,
1358 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1361 static const struct snd_soc_dapm_widget wm8994_dac_widgets
[] = {
1362 SND_SOC_DAPM_DAC("DAC2L", NULL
, WM8994_POWER_MANAGEMENT_5
, 3, 0),
1363 SND_SOC_DAPM_DAC("DAC2R", NULL
, WM8994_POWER_MANAGEMENT_5
, 2, 0),
1364 SND_SOC_DAPM_DAC("DAC1L", NULL
, WM8994_POWER_MANAGEMENT_5
, 1, 0),
1365 SND_SOC_DAPM_DAC("DAC1R", NULL
, WM8994_POWER_MANAGEMENT_5
, 0, 0),
1368 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets
[] = {
1369 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4
, 1, 0, &adcl_mux
,
1370 adc_mux_ev
, SND_SOC_DAPM_PRE_PMU
),
1371 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4
, 0, 0, &adcr_mux
,
1372 adc_mux_ev
, SND_SOC_DAPM_PRE_PMU
),
1375 static const struct snd_soc_dapm_widget wm8994_adc_widgets
[] = {
1376 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4
, 1, 0, &adcl_mux
),
1377 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4
, 0, 0, &adcr_mux
),
1380 static const struct snd_soc_dapm_widget wm8994_dapm_widgets
[] = {
1381 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1382 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1383 SND_SOC_DAPM_INPUT("Clock"),
1385 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM
, 0, 0, micbias_ev
,
1386 SND_SOC_DAPM_PRE_PMU
),
1387 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM
, 0, 0, vmid_event
,
1388 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1390 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM
, 0, 0, clk_sys_event
,
1391 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1393 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1
, 3, 0, NULL
, 0),
1394 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1
, 2, 0, NULL
, 0),
1395 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1
, 1, 0, NULL
, 0),
1397 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL
,
1398 0, WM8994_POWER_MANAGEMENT_4
, 9, 0),
1399 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL
,
1400 0, WM8994_POWER_MANAGEMENT_4
, 8, 0),
1401 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL
, 0,
1402 WM8994_POWER_MANAGEMENT_5
, 9, 0, wm8958_aif_ev
,
1403 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1404 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL
, 0,
1405 WM8994_POWER_MANAGEMENT_5
, 8, 0, wm8958_aif_ev
,
1406 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1408 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL
,
1409 0, WM8994_POWER_MANAGEMENT_4
, 11, 0),
1410 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL
,
1411 0, WM8994_POWER_MANAGEMENT_4
, 10, 0),
1412 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL
, 0,
1413 WM8994_POWER_MANAGEMENT_5
, 11, 0, wm8958_aif_ev
,
1414 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1415 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL
, 0,
1416 WM8994_POWER_MANAGEMENT_5
, 10, 0, wm8958_aif_ev
,
1417 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1419 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM
, 0, 0,
1420 aif1adc1l_mix
, ARRAY_SIZE(aif1adc1l_mix
)),
1421 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM
, 0, 0,
1422 aif1adc1r_mix
, ARRAY_SIZE(aif1adc1r_mix
)),
1424 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM
, 0, 0,
1425 aif1adc2l_mix
, ARRAY_SIZE(aif1adc2l_mix
)),
1426 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM
, 0, 0,
1427 aif1adc2r_mix
, ARRAY_SIZE(aif1adc2r_mix
)),
1429 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM
, 0, 0,
1430 aif2dac2l_mix
, ARRAY_SIZE(aif2dac2l_mix
)),
1431 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM
, 0, 0,
1432 aif2dac2r_mix
, ARRAY_SIZE(aif2dac2r_mix
)),
1434 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM
, 0, 0, &sidetone1_mux
),
1435 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM
, 0, 0, &sidetone2_mux
),
1437 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM
, 0, 0,
1438 dac1l_mix
, ARRAY_SIZE(dac1l_mix
)),
1439 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM
, 0, 0,
1440 dac1r_mix
, ARRAY_SIZE(dac1r_mix
)),
1442 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL
, 0,
1443 WM8994_POWER_MANAGEMENT_4
, 13, 0),
1444 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL
, 0,
1445 WM8994_POWER_MANAGEMENT_4
, 12, 0),
1446 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL
, 0,
1447 WM8994_POWER_MANAGEMENT_5
, 13, 0, wm8958_aif_ev
,
1448 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1449 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL
, 0,
1450 WM8994_POWER_MANAGEMENT_5
, 12, 0, wm8958_aif_ev
,
1451 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1453 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM
, 0, 0),
1454 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM
, 0, 0),
1455 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM
, 0, 0),
1456 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM
, 0, 0),
1458 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM
, 0, 0, &aif1dac_mux
),
1459 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM
, 0, 0, &aif2dac_mux
),
1460 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM
, 0, 0, &aif2adc_mux
),
1462 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM
, 0, 0),
1463 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM
, 0, 0),
1465 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1
, 4, 0, NULL
, 0),
1467 SND_SOC_DAPM_ADC("DMIC2L", NULL
, WM8994_POWER_MANAGEMENT_4
, 5, 0),
1468 SND_SOC_DAPM_ADC("DMIC2R", NULL
, WM8994_POWER_MANAGEMENT_4
, 4, 0),
1469 SND_SOC_DAPM_ADC("DMIC1L", NULL
, WM8994_POWER_MANAGEMENT_4
, 3, 0),
1470 SND_SOC_DAPM_ADC("DMIC1R", NULL
, WM8994_POWER_MANAGEMENT_4
, 2, 0),
1472 /* Power is done with the muxes since the ADC power also controls the
1473 * downsampling chain, the chip will automatically manage the analogue
1474 * specific portions.
1476 SND_SOC_DAPM_ADC("ADCL", NULL
, SND_SOC_NOPM
, 1, 0),
1477 SND_SOC_DAPM_ADC("ADCR", NULL
, SND_SOC_NOPM
, 0, 0),
1479 SND_SOC_DAPM_POST("Debug log", post_ev
),
1482 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets
[] = {
1483 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM
, 0, 0, &wm8994_aif3adc_mux
),
1486 static const struct snd_soc_dapm_widget wm8958_dapm_widgets
[] = {
1487 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM
, 0, 0, &mono_pcm_out_mux
),
1488 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM
, 0, 0, &aif2dacl_src_mux
),
1489 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM
, 0, 0, &aif2dacr_src_mux
),
1490 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM
, 0, 0, &wm8958_aif3adc_mux
),
1493 static const struct snd_soc_dapm_route intercon
[] = {
1494 { "CLK_SYS", NULL
, "AIF1CLK", check_clk_sys
},
1495 { "CLK_SYS", NULL
, "AIF2CLK", check_clk_sys
},
1497 { "DSP1CLK", NULL
, "CLK_SYS" },
1498 { "DSP2CLK", NULL
, "CLK_SYS" },
1499 { "DSPINTCLK", NULL
, "CLK_SYS" },
1501 { "AIF1ADC1L", NULL
, "AIF1CLK" },
1502 { "AIF1ADC1L", NULL
, "DSP1CLK" },
1503 { "AIF1ADC1R", NULL
, "AIF1CLK" },
1504 { "AIF1ADC1R", NULL
, "DSP1CLK" },
1505 { "AIF1ADC1R", NULL
, "DSPINTCLK" },
1507 { "AIF1DAC1L", NULL
, "AIF1CLK" },
1508 { "AIF1DAC1L", NULL
, "DSP1CLK" },
1509 { "AIF1DAC1R", NULL
, "AIF1CLK" },
1510 { "AIF1DAC1R", NULL
, "DSP1CLK" },
1511 { "AIF1DAC1R", NULL
, "DSPINTCLK" },
1513 { "AIF1ADC2L", NULL
, "AIF1CLK" },
1514 { "AIF1ADC2L", NULL
, "DSP1CLK" },
1515 { "AIF1ADC2R", NULL
, "AIF1CLK" },
1516 { "AIF1ADC2R", NULL
, "DSP1CLK" },
1517 { "AIF1ADC2R", NULL
, "DSPINTCLK" },
1519 { "AIF1DAC2L", NULL
, "AIF1CLK" },
1520 { "AIF1DAC2L", NULL
, "DSP1CLK" },
1521 { "AIF1DAC2R", NULL
, "AIF1CLK" },
1522 { "AIF1DAC2R", NULL
, "DSP1CLK" },
1523 { "AIF1DAC2R", NULL
, "DSPINTCLK" },
1525 { "AIF2ADCL", NULL
, "AIF2CLK" },
1526 { "AIF2ADCL", NULL
, "DSP2CLK" },
1527 { "AIF2ADCR", NULL
, "AIF2CLK" },
1528 { "AIF2ADCR", NULL
, "DSP2CLK" },
1529 { "AIF2ADCR", NULL
, "DSPINTCLK" },
1531 { "AIF2DACL", NULL
, "AIF2CLK" },
1532 { "AIF2DACL", NULL
, "DSP2CLK" },
1533 { "AIF2DACR", NULL
, "AIF2CLK" },
1534 { "AIF2DACR", NULL
, "DSP2CLK" },
1535 { "AIF2DACR", NULL
, "DSPINTCLK" },
1537 { "DMIC1L", NULL
, "DMIC1DAT" },
1538 { "DMIC1L", NULL
, "CLK_SYS" },
1539 { "DMIC1R", NULL
, "DMIC1DAT" },
1540 { "DMIC1R", NULL
, "CLK_SYS" },
1541 { "DMIC2L", NULL
, "DMIC2DAT" },
1542 { "DMIC2L", NULL
, "CLK_SYS" },
1543 { "DMIC2R", NULL
, "DMIC2DAT" },
1544 { "DMIC2R", NULL
, "CLK_SYS" },
1546 { "ADCL", NULL
, "AIF1CLK" },
1547 { "ADCL", NULL
, "DSP1CLK" },
1548 { "ADCL", NULL
, "DSPINTCLK" },
1550 { "ADCR", NULL
, "AIF1CLK" },
1551 { "ADCR", NULL
, "DSP1CLK" },
1552 { "ADCR", NULL
, "DSPINTCLK" },
1554 { "ADCL Mux", "ADC", "ADCL" },
1555 { "ADCL Mux", "DMIC", "DMIC1L" },
1556 { "ADCR Mux", "ADC", "ADCR" },
1557 { "ADCR Mux", "DMIC", "DMIC1R" },
1559 { "DAC1L", NULL
, "AIF1CLK" },
1560 { "DAC1L", NULL
, "DSP1CLK" },
1561 { "DAC1L", NULL
, "DSPINTCLK" },
1563 { "DAC1R", NULL
, "AIF1CLK" },
1564 { "DAC1R", NULL
, "DSP1CLK" },
1565 { "DAC1R", NULL
, "DSPINTCLK" },
1567 { "DAC2L", NULL
, "AIF2CLK" },
1568 { "DAC2L", NULL
, "DSP2CLK" },
1569 { "DAC2L", NULL
, "DSPINTCLK" },
1571 { "DAC2R", NULL
, "AIF2DACR" },
1572 { "DAC2R", NULL
, "AIF2CLK" },
1573 { "DAC2R", NULL
, "DSP2CLK" },
1574 { "DAC2R", NULL
, "DSPINTCLK" },
1576 { "TOCLK", NULL
, "CLK_SYS" },
1579 { "AIF1ADC1L", NULL
, "AIF1ADC1L Mixer" },
1580 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1581 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1583 { "AIF1ADC1R", NULL
, "AIF1ADC1R Mixer" },
1584 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1585 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1587 { "AIF1ADC2L", NULL
, "AIF1ADC2L Mixer" },
1588 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1589 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1591 { "AIF1ADC2R", NULL
, "AIF1ADC2R Mixer" },
1592 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1593 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1595 /* Pin level routing for AIF3 */
1596 { "AIF1DAC1L", NULL
, "AIF1DAC Mux" },
1597 { "AIF1DAC1R", NULL
, "AIF1DAC Mux" },
1598 { "AIF1DAC2L", NULL
, "AIF1DAC Mux" },
1599 { "AIF1DAC2R", NULL
, "AIF1DAC Mux" },
1601 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1602 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1603 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1604 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1605 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1606 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1607 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1610 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1611 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1612 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1613 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1614 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1616 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1617 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1618 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1619 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1620 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1622 /* DAC2/AIF2 outputs */
1623 { "AIF2ADCL", NULL
, "AIF2DAC2L Mixer" },
1624 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1625 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1626 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1627 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1628 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1630 { "AIF2ADCR", NULL
, "AIF2DAC2R Mixer" },
1631 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1632 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1633 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1634 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1635 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1637 { "AIF1ADCDAT", NULL
, "AIF1ADC1L" },
1638 { "AIF1ADCDAT", NULL
, "AIF1ADC1R" },
1639 { "AIF1ADCDAT", NULL
, "AIF1ADC2L" },
1640 { "AIF1ADCDAT", NULL
, "AIF1ADC2R" },
1642 { "AIF2ADCDAT", NULL
, "AIF2ADC Mux" },
1645 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1646 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1647 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1648 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1649 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1650 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1651 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1652 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1655 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1656 { "Left Sidetone", "DMIC2", "DMIC2L" },
1657 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1658 { "Right Sidetone", "DMIC2", "DMIC2R" },
1661 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1662 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1664 { "SPKL", "DAC1 Switch", "DAC1L" },
1665 { "SPKL", "DAC2 Switch", "DAC2L" },
1667 { "SPKR", "DAC1 Switch", "DAC1R" },
1668 { "SPKR", "DAC2 Switch", "DAC2R" },
1670 { "Left Headphone Mux", "DAC", "DAC1L" },
1671 { "Right Headphone Mux", "DAC", "DAC1R" },
1674 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon
[] = {
1675 { "DAC1L", NULL
, "Late DAC1L Enable PGA" },
1676 { "Late DAC1L Enable PGA", NULL
, "DAC1L Mixer" },
1677 { "DAC1R", NULL
, "Late DAC1R Enable PGA" },
1678 { "Late DAC1R Enable PGA", NULL
, "DAC1R Mixer" },
1679 { "DAC2L", NULL
, "Late DAC2L Enable PGA" },
1680 { "Late DAC2L Enable PGA", NULL
, "AIF2DAC2L Mixer" },
1681 { "DAC2R", NULL
, "Late DAC2R Enable PGA" },
1682 { "Late DAC2R Enable PGA", NULL
, "AIF2DAC2R Mixer" }
1685 static const struct snd_soc_dapm_route wm8994_lateclk_intercon
[] = {
1686 { "DAC1L", NULL
, "DAC1L Mixer" },
1687 { "DAC1R", NULL
, "DAC1R Mixer" },
1688 { "DAC2L", NULL
, "AIF2DAC2L Mixer" },
1689 { "DAC2R", NULL
, "AIF2DAC2R Mixer" },
1692 static const struct snd_soc_dapm_route wm8994_revd_intercon
[] = {
1693 { "AIF1DACDAT", NULL
, "AIF2DACDAT" },
1694 { "AIF2DACDAT", NULL
, "AIF1DACDAT" },
1695 { "AIF1ADCDAT", NULL
, "AIF2ADCDAT" },
1696 { "AIF2ADCDAT", NULL
, "AIF1ADCDAT" },
1697 { "MICBIAS1", NULL
, "CLK_SYS" },
1698 { "MICBIAS1", NULL
, "MICBIAS Supply" },
1699 { "MICBIAS2", NULL
, "CLK_SYS" },
1700 { "MICBIAS2", NULL
, "MICBIAS Supply" },
1703 static const struct snd_soc_dapm_route wm8994_intercon
[] = {
1704 { "AIF2DACL", NULL
, "AIF2DAC Mux" },
1705 { "AIF2DACR", NULL
, "AIF2DAC Mux" },
1706 { "MICBIAS1", NULL
, "VMID" },
1707 { "MICBIAS2", NULL
, "VMID" },
1710 static const struct snd_soc_dapm_route wm8958_intercon
[] = {
1711 { "AIF2DACL", NULL
, "AIF2DACL Mux" },
1712 { "AIF2DACR", NULL
, "AIF2DACR Mux" },
1714 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1715 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1716 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1717 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1719 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1720 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1722 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1725 /* The size in bits of the FLL divide multiplied by 10
1726 * to allow rounding later */
1727 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1737 static int wm8994_get_fll_config(struct fll_div
*fll
,
1738 int freq_in
, int freq_out
)
1741 unsigned int K
, Ndiv
, Nmod
;
1743 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in
, freq_out
);
1745 /* Scale the input frequency down to <= 13.5MHz */
1746 fll
->clk_ref_div
= 0;
1747 while (freq_in
> 13500000) {
1751 if (fll
->clk_ref_div
> 3)
1754 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll
->clk_ref_div
, freq_in
);
1756 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1758 while (freq_out
* (fll
->outdiv
+ 1) < 90000000) {
1760 if (fll
->outdiv
> 63)
1763 freq_out
*= fll
->outdiv
+ 1;
1764 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll
->outdiv
, freq_out
);
1766 if (freq_in
> 1000000) {
1767 fll
->fll_fratio
= 0;
1768 } else if (freq_in
> 256000) {
1769 fll
->fll_fratio
= 1;
1771 } else if (freq_in
> 128000) {
1772 fll
->fll_fratio
= 2;
1774 } else if (freq_in
> 64000) {
1775 fll
->fll_fratio
= 3;
1778 fll
->fll_fratio
= 4;
1781 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll
->fll_fratio
, freq_in
);
1783 /* Now, calculate N.K */
1784 Ndiv
= freq_out
/ freq_in
;
1787 Nmod
= freq_out
% freq_in
;
1788 pr_debug("Nmod=%d\n", Nmod
);
1790 /* Calculate fractional part - scale up so we can round. */
1791 Kpart
= FIXED_FLL_SIZE
* (long long)Nmod
;
1793 do_div(Kpart
, freq_in
);
1795 K
= Kpart
& 0xFFFFFFFF;
1800 /* Move down to proper range now rounding is done */
1803 pr_debug("N=%x K=%x\n", fll
->n
, fll
->k
);
1808 static int _wm8994_set_fll(struct snd_soc_codec
*codec
, int id
, int src
,
1809 unsigned int freq_in
, unsigned int freq_out
)
1811 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1812 struct wm8994
*control
= wm8994
->wm8994
;
1813 int reg_offset
, ret
;
1815 u16 reg
, aif1
, aif2
;
1816 unsigned long timeout
;
1819 aif1
= snd_soc_read(codec
, WM8994_AIF1_CLOCKING_1
)
1820 & WM8994_AIF1CLK_ENA
;
1822 aif2
= snd_soc_read(codec
, WM8994_AIF2_CLOCKING_1
)
1823 & WM8994_AIF2CLK_ENA
;
1838 reg
= snd_soc_read(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
);
1839 was_enabled
= reg
& WM8994_FLL1_ENA
;
1843 /* Allow no source specification when stopping */
1846 src
= wm8994
->fll
[id
].src
;
1848 case WM8994_FLL_SRC_MCLK1
:
1849 case WM8994_FLL_SRC_MCLK2
:
1850 case WM8994_FLL_SRC_LRCLK
:
1851 case WM8994_FLL_SRC_BCLK
:
1857 /* Are we changing anything? */
1858 if (wm8994
->fll
[id
].src
== src
&&
1859 wm8994
->fll
[id
].in
== freq_in
&& wm8994
->fll
[id
].out
== freq_out
)
1862 /* If we're stopping the FLL redo the old config - no
1863 * registers will actually be written but we avoid GCC flow
1864 * analysis bugs spewing warnings.
1867 ret
= wm8994_get_fll_config(&fll
, freq_in
, freq_out
);
1869 ret
= wm8994_get_fll_config(&fll
, wm8994
->fll
[id
].in
,
1870 wm8994
->fll
[id
].out
);
1874 /* Gate the AIF clocks while we reclock */
1875 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
1876 WM8994_AIF1CLK_ENA
, 0);
1877 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
1878 WM8994_AIF2CLK_ENA
, 0);
1880 /* We always need to disable the FLL while reconfiguring */
1881 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
,
1882 WM8994_FLL1_ENA
, 0);
1884 reg
= (fll
.outdiv
<< WM8994_FLL1_OUTDIV_SHIFT
) |
1885 (fll
.fll_fratio
<< WM8994_FLL1_FRATIO_SHIFT
);
1886 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_2
+ reg_offset
,
1887 WM8994_FLL1_OUTDIV_MASK
|
1888 WM8994_FLL1_FRATIO_MASK
, reg
);
1890 snd_soc_write(codec
, WM8994_FLL1_CONTROL_3
+ reg_offset
, fll
.k
);
1892 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_4
+ reg_offset
,
1894 fll
.n
<< WM8994_FLL1_N_SHIFT
);
1896 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_5
+ reg_offset
,
1897 WM8994_FLL1_REFCLK_DIV_MASK
|
1898 WM8994_FLL1_REFCLK_SRC_MASK
,
1899 (fll
.clk_ref_div
<< WM8994_FLL1_REFCLK_DIV_SHIFT
) |
1902 /* Clear any pending completion from a previous failure */
1903 try_wait_for_completion(&wm8994
->fll_locked
[id
]);
1905 /* Enable (with fractional mode if required) */
1907 /* Enable VMID if we need it */
1909 active_reference(codec
);
1911 switch (control
->type
) {
1913 vmid_reference(codec
);
1916 if (wm8994
->revision
< 1)
1917 vmid_reference(codec
);
1925 reg
= WM8994_FLL1_ENA
| WM8994_FLL1_FRAC
;
1927 reg
= WM8994_FLL1_ENA
;
1928 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
,
1929 WM8994_FLL1_ENA
| WM8994_FLL1_FRAC
,
1932 if (wm8994
->fll_locked_irq
) {
1933 timeout
= wait_for_completion_timeout(&wm8994
->fll_locked
[id
],
1934 msecs_to_jiffies(10));
1936 dev_warn(codec
->dev
,
1937 "Timed out waiting for FLL lock\n");
1943 switch (control
->type
) {
1945 vmid_dereference(codec
);
1948 if (wm8994
->revision
< 1)
1949 vmid_dereference(codec
);
1955 active_dereference(codec
);
1959 wm8994
->fll
[id
].in
= freq_in
;
1960 wm8994
->fll
[id
].out
= freq_out
;
1961 wm8994
->fll
[id
].src
= src
;
1963 /* Enable any gated AIF clocks */
1964 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
1965 WM8994_AIF1CLK_ENA
, aif1
);
1966 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
1967 WM8994_AIF2CLK_ENA
, aif2
);
1969 configure_clock(codec
);
1974 static irqreturn_t
wm8994_fll_locked_irq(int irq
, void *data
)
1976 struct completion
*completion
= data
;
1978 complete(completion
);
1983 static int opclk_divs
[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1985 static int wm8994_set_fll(struct snd_soc_dai
*dai
, int id
, int src
,
1986 unsigned int freq_in
, unsigned int freq_out
)
1988 return _wm8994_set_fll(dai
->codec
, id
, src
, freq_in
, freq_out
);
1991 static int wm8994_set_dai_sysclk(struct snd_soc_dai
*dai
,
1992 int clk_id
, unsigned int freq
, int dir
)
1994 struct snd_soc_codec
*codec
= dai
->codec
;
1995 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2004 /* AIF3 shares clocking with AIF1/2 */
2009 case WM8994_SYSCLK_MCLK1
:
2010 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_MCLK1
;
2011 wm8994
->mclk
[0] = freq
;
2012 dev_dbg(dai
->dev
, "AIF%d using MCLK1 at %uHz\n",
2016 case WM8994_SYSCLK_MCLK2
:
2017 /* TODO: Set GPIO AF */
2018 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_MCLK2
;
2019 wm8994
->mclk
[1] = freq
;
2020 dev_dbg(dai
->dev
, "AIF%d using MCLK2 at %uHz\n",
2024 case WM8994_SYSCLK_FLL1
:
2025 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_FLL1
;
2026 dev_dbg(dai
->dev
, "AIF%d using FLL1\n", dai
->id
);
2029 case WM8994_SYSCLK_FLL2
:
2030 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_FLL2
;
2031 dev_dbg(dai
->dev
, "AIF%d using FLL2\n", dai
->id
);
2034 case WM8994_SYSCLK_OPCLK
:
2035 /* Special case - a division (times 10) is given and
2036 * no effect on main clocking.
2039 for (i
= 0; i
< ARRAY_SIZE(opclk_divs
); i
++)
2040 if (opclk_divs
[i
] == freq
)
2042 if (i
== ARRAY_SIZE(opclk_divs
))
2044 snd_soc_update_bits(codec
, WM8994_CLOCKING_2
,
2045 WM8994_OPCLK_DIV_MASK
, i
);
2046 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_2
,
2047 WM8994_OPCLK_ENA
, WM8994_OPCLK_ENA
);
2049 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_2
,
2050 WM8994_OPCLK_ENA
, 0);
2057 configure_clock(codec
);
2062 static int wm8994_set_bias_level(struct snd_soc_codec
*codec
,
2063 enum snd_soc_bias_level level
)
2065 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2066 struct wm8994
*control
= wm8994
->wm8994
;
2069 case SND_SOC_BIAS_ON
:
2072 case SND_SOC_BIAS_PREPARE
:
2073 /* MICBIAS into regulating mode */
2074 switch (control
->type
) {
2077 snd_soc_update_bits(codec
, WM8958_MICBIAS1
,
2078 WM8958_MICB1_MODE
, 0);
2079 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
2080 WM8958_MICB2_MODE
, 0);
2086 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_STANDBY
)
2087 active_reference(codec
);
2090 case SND_SOC_BIAS_STANDBY
:
2091 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
2092 switch (control
->type
) {
2094 if (wm8994
->revision
< 4) {
2095 /* Tweak DC servo and DSP
2096 * configuration for improved
2098 snd_soc_write(codec
, 0x102, 0x3);
2099 snd_soc_write(codec
, 0x56, 0x3);
2100 snd_soc_write(codec
, 0x817, 0);
2101 snd_soc_write(codec
, 0x102, 0);
2106 if (wm8994
->revision
== 0) {
2107 /* Optimise performance for rev A */
2108 snd_soc_write(codec
, 0x102, 0x3);
2109 snd_soc_write(codec
, 0xcb, 0x81);
2110 snd_soc_write(codec
, 0x817, 0);
2111 snd_soc_write(codec
, 0x102, 0);
2113 snd_soc_update_bits(codec
,
2114 WM8958_CHARGE_PUMP_2
,
2121 if (wm8994
->revision
< 2) {
2122 snd_soc_write(codec
, 0x102, 0x3);
2123 snd_soc_write(codec
, 0x5d, 0x7e);
2124 snd_soc_write(codec
, 0x5e, 0x0);
2125 snd_soc_write(codec
, 0x102, 0x0);
2130 /* Discharge LINEOUT1 & 2 */
2131 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
2132 WM8994_LINEOUT1_DISCH
|
2133 WM8994_LINEOUT2_DISCH
,
2134 WM8994_LINEOUT1_DISCH
|
2135 WM8994_LINEOUT2_DISCH
);
2138 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_PREPARE
)
2139 active_dereference(codec
);
2141 /* MICBIAS into bypass mode on newer devices */
2142 switch (control
->type
) {
2145 snd_soc_update_bits(codec
, WM8958_MICBIAS1
,
2148 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
2157 case SND_SOC_BIAS_OFF
:
2158 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_STANDBY
)
2159 wm8994
->cur_fw
= NULL
;
2162 codec
->dapm
.bias_level
= level
;
2167 static int wm8994_set_dai_fmt(struct snd_soc_dai
*dai
, unsigned int fmt
)
2169 struct snd_soc_codec
*codec
= dai
->codec
;
2170 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2171 struct wm8994
*control
= wm8994
->wm8994
;
2179 ms_reg
= WM8994_AIF1_MASTER_SLAVE
;
2180 aif1_reg
= WM8994_AIF1_CONTROL_1
;
2183 ms_reg
= WM8994_AIF2_MASTER_SLAVE
;
2184 aif1_reg
= WM8994_AIF2_CONTROL_1
;
2190 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
2191 case SND_SOC_DAIFMT_CBS_CFS
:
2193 case SND_SOC_DAIFMT_CBM_CFM
:
2194 ms
= WM8994_AIF1_MSTR
;
2200 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
2201 case SND_SOC_DAIFMT_DSP_B
:
2202 aif1
|= WM8994_AIF1_LRCLK_INV
;
2203 case SND_SOC_DAIFMT_DSP_A
:
2206 case SND_SOC_DAIFMT_I2S
:
2209 case SND_SOC_DAIFMT_RIGHT_J
:
2211 case SND_SOC_DAIFMT_LEFT_J
:
2218 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
2219 case SND_SOC_DAIFMT_DSP_A
:
2220 case SND_SOC_DAIFMT_DSP_B
:
2221 /* frame inversion not valid for DSP modes */
2222 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
2223 case SND_SOC_DAIFMT_NB_NF
:
2225 case SND_SOC_DAIFMT_IB_NF
:
2226 aif1
|= WM8994_AIF1_BCLK_INV
;
2233 case SND_SOC_DAIFMT_I2S
:
2234 case SND_SOC_DAIFMT_RIGHT_J
:
2235 case SND_SOC_DAIFMT_LEFT_J
:
2236 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
2237 case SND_SOC_DAIFMT_NB_NF
:
2239 case SND_SOC_DAIFMT_IB_IF
:
2240 aif1
|= WM8994_AIF1_BCLK_INV
| WM8994_AIF1_LRCLK_INV
;
2242 case SND_SOC_DAIFMT_IB_NF
:
2243 aif1
|= WM8994_AIF1_BCLK_INV
;
2245 case SND_SOC_DAIFMT_NB_IF
:
2246 aif1
|= WM8994_AIF1_LRCLK_INV
;
2256 /* The AIF2 format configuration needs to be mirrored to AIF3
2257 * on WM8958 if it's in use so just do it all the time. */
2258 switch (control
->type
) {
2262 snd_soc_update_bits(codec
, WM8958_AIF3_CONTROL_1
,
2263 WM8994_AIF1_LRCLK_INV
|
2264 WM8958_AIF3_FMT_MASK
, aif1
);
2271 snd_soc_update_bits(codec
, aif1_reg
,
2272 WM8994_AIF1_BCLK_INV
| WM8994_AIF1_LRCLK_INV
|
2273 WM8994_AIF1_FMT_MASK
,
2275 snd_soc_update_bits(codec
, ms_reg
, WM8994_AIF1_MSTR
,
2297 static int fs_ratios
[] = {
2298 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2301 static int bclk_divs
[] = {
2302 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2303 640, 880, 960, 1280, 1760, 1920
2306 static int wm8994_hw_params(struct snd_pcm_substream
*substream
,
2307 struct snd_pcm_hw_params
*params
,
2308 struct snd_soc_dai
*dai
)
2310 struct snd_soc_codec
*codec
= dai
->codec
;
2311 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2322 int id
= dai
->id
- 1;
2324 int i
, cur_val
, best_val
, bclk_rate
, best
;
2328 aif1_reg
= WM8994_AIF1_CONTROL_1
;
2329 aif2_reg
= WM8994_AIF1_CONTROL_2
;
2330 bclk_reg
= WM8994_AIF1_BCLK
;
2331 rate_reg
= WM8994_AIF1_RATE
;
2332 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
||
2333 wm8994
->lrclk_shared
[0]) {
2334 lrclk_reg
= WM8994_AIF1DAC_LRCLK
;
2336 lrclk_reg
= WM8994_AIF1ADC_LRCLK
;
2337 dev_dbg(codec
->dev
, "AIF1 using split LRCLK\n");
2341 aif1_reg
= WM8994_AIF2_CONTROL_1
;
2342 aif2_reg
= WM8994_AIF2_CONTROL_2
;
2343 bclk_reg
= WM8994_AIF2_BCLK
;
2344 rate_reg
= WM8994_AIF2_RATE
;
2345 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
||
2346 wm8994
->lrclk_shared
[1]) {
2347 lrclk_reg
= WM8994_AIF2DAC_LRCLK
;
2349 lrclk_reg
= WM8994_AIF2ADC_LRCLK
;
2350 dev_dbg(codec
->dev
, "AIF2 using split LRCLK\n");
2357 bclk_rate
= params_rate(params
) * 2;
2358 switch (params_format(params
)) {
2359 case SNDRV_PCM_FORMAT_S16_LE
:
2362 case SNDRV_PCM_FORMAT_S20_3LE
:
2366 case SNDRV_PCM_FORMAT_S24_LE
:
2370 case SNDRV_PCM_FORMAT_S32_LE
:
2378 /* Try to find an appropriate sample rate; look for an exact match. */
2379 for (i
= 0; i
< ARRAY_SIZE(srs
); i
++)
2380 if (srs
[i
].rate
== params_rate(params
))
2382 if (i
== ARRAY_SIZE(srs
))
2384 rate_val
|= srs
[i
].val
<< WM8994_AIF1_SR_SHIFT
;
2386 dev_dbg(dai
->dev
, "Sample rate is %dHz\n", srs
[i
].rate
);
2387 dev_dbg(dai
->dev
, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2388 dai
->id
, wm8994
->aifclk
[id
], bclk_rate
);
2390 if (params_channels(params
) == 1 &&
2391 (snd_soc_read(codec
, aif1_reg
) & 0x18) == 0x18)
2392 aif2
|= WM8994_AIF1_MONO
;
2394 if (wm8994
->aifclk
[id
] == 0) {
2395 dev_err(dai
->dev
, "AIF%dCLK not configured\n", dai
->id
);
2399 /* AIFCLK/fs ratio; look for a close match in either direction */
2401 best_val
= abs((fs_ratios
[0] * params_rate(params
))
2402 - wm8994
->aifclk
[id
]);
2403 for (i
= 1; i
< ARRAY_SIZE(fs_ratios
); i
++) {
2404 cur_val
= abs((fs_ratios
[i
] * params_rate(params
))
2405 - wm8994
->aifclk
[id
]);
2406 if (cur_val
>= best_val
)
2411 dev_dbg(dai
->dev
, "Selected AIF%dCLK/fs = %d\n",
2412 dai
->id
, fs_ratios
[best
]);
2415 /* We may not get quite the right frequency if using
2416 * approximate clocks so look for the closest match that is
2417 * higher than the target (we need to ensure that there enough
2418 * BCLKs to clock out the samples).
2421 for (i
= 0; i
< ARRAY_SIZE(bclk_divs
); i
++) {
2422 cur_val
= (wm8994
->aifclk
[id
] * 10 / bclk_divs
[i
]) - bclk_rate
;
2423 if (cur_val
< 0) /* BCLK table is sorted */
2427 bclk_rate
= wm8994
->aifclk
[id
] * 10 / bclk_divs
[best
];
2428 dev_dbg(dai
->dev
, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2429 bclk_divs
[best
], bclk_rate
);
2430 bclk
|= best
<< WM8994_AIF1_BCLK_DIV_SHIFT
;
2432 lrclk
= bclk_rate
/ params_rate(params
);
2434 dev_err(dai
->dev
, "Unable to generate LRCLK from %dHz BCLK\n",
2438 dev_dbg(dai
->dev
, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2439 lrclk
, bclk_rate
/ lrclk
);
2441 snd_soc_update_bits(codec
, aif1_reg
, WM8994_AIF1_WL_MASK
, aif1
);
2442 snd_soc_update_bits(codec
, aif2_reg
, WM8994_AIF1_MONO
, aif2
);
2443 snd_soc_update_bits(codec
, bclk_reg
, WM8994_AIF1_BCLK_DIV_MASK
, bclk
);
2444 snd_soc_update_bits(codec
, lrclk_reg
, WM8994_AIF1DAC_RATE_MASK
,
2446 snd_soc_update_bits(codec
, rate_reg
, WM8994_AIF1_SR_MASK
|
2447 WM8994_AIF1CLK_RATE_MASK
, rate_val
);
2449 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
2452 wm8994
->dac_rates
[0] = params_rate(params
);
2453 wm8994_set_retune_mobile(codec
, 0);
2454 wm8994_set_retune_mobile(codec
, 1);
2457 wm8994
->dac_rates
[1] = params_rate(params
);
2458 wm8994_set_retune_mobile(codec
, 2);
2466 static int wm8994_aif3_hw_params(struct snd_pcm_substream
*substream
,
2467 struct snd_pcm_hw_params
*params
,
2468 struct snd_soc_dai
*dai
)
2470 struct snd_soc_codec
*codec
= dai
->codec
;
2471 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2472 struct wm8994
*control
= wm8994
->wm8994
;
2478 switch (control
->type
) {
2481 aif1_reg
= WM8958_AIF3_CONTROL_1
;
2490 switch (params_format(params
)) {
2491 case SNDRV_PCM_FORMAT_S16_LE
:
2493 case SNDRV_PCM_FORMAT_S20_3LE
:
2496 case SNDRV_PCM_FORMAT_S24_LE
:
2499 case SNDRV_PCM_FORMAT_S32_LE
:
2506 return snd_soc_update_bits(codec
, aif1_reg
, WM8994_AIF1_WL_MASK
, aif1
);
2509 static void wm8994_aif_shutdown(struct snd_pcm_substream
*substream
,
2510 struct snd_soc_dai
*dai
)
2512 struct snd_soc_codec
*codec
= dai
->codec
;
2517 rate_reg
= WM8994_AIF1_RATE
;
2520 rate_reg
= WM8994_AIF2_RATE
;
2526 /* If the DAI is idle then configure the divider tree for the
2527 * lowest output rate to save a little power if the clock is
2528 * still active (eg, because it is system clock).
2530 if (rate_reg
&& !dai
->playback_active
&& !dai
->capture_active
)
2531 snd_soc_update_bits(codec
, rate_reg
,
2532 WM8994_AIF1_SR_MASK
|
2533 WM8994_AIF1CLK_RATE_MASK
, 0x9);
2536 static int wm8994_aif_mute(struct snd_soc_dai
*codec_dai
, int mute
)
2538 struct snd_soc_codec
*codec
= codec_dai
->codec
;
2542 switch (codec_dai
->id
) {
2544 mute_reg
= WM8994_AIF1_DAC1_FILTERS_1
;
2547 mute_reg
= WM8994_AIF2_DAC_FILTERS_1
;
2554 reg
= WM8994_AIF1DAC1_MUTE
;
2558 snd_soc_update_bits(codec
, mute_reg
, WM8994_AIF1DAC1_MUTE
, reg
);
2563 static int wm8994_set_tristate(struct snd_soc_dai
*codec_dai
, int tristate
)
2565 struct snd_soc_codec
*codec
= codec_dai
->codec
;
2568 switch (codec_dai
->id
) {
2570 reg
= WM8994_AIF1_MASTER_SLAVE
;
2571 mask
= WM8994_AIF1_TRI
;
2574 reg
= WM8994_AIF2_MASTER_SLAVE
;
2575 mask
= WM8994_AIF2_TRI
;
2578 reg
= WM8994_POWER_MANAGEMENT_6
;
2579 mask
= WM8994_AIF3_TRI
;
2590 return snd_soc_update_bits(codec
, reg
, mask
, val
);
2593 static int wm8994_aif2_probe(struct snd_soc_dai
*dai
)
2595 struct snd_soc_codec
*codec
= dai
->codec
;
2597 /* Disable the pulls on the AIF if we're using it to save power. */
2598 snd_soc_update_bits(codec
, WM8994_GPIO_3
,
2599 WM8994_GPN_PU
| WM8994_GPN_PD
, 0);
2600 snd_soc_update_bits(codec
, WM8994_GPIO_4
,
2601 WM8994_GPN_PU
| WM8994_GPN_PD
, 0);
2602 snd_soc_update_bits(codec
, WM8994_GPIO_5
,
2603 WM8994_GPN_PU
| WM8994_GPN_PD
, 0);
2608 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2610 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2611 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2613 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops
= {
2614 .set_sysclk
= wm8994_set_dai_sysclk
,
2615 .set_fmt
= wm8994_set_dai_fmt
,
2616 .hw_params
= wm8994_hw_params
,
2617 .shutdown
= wm8994_aif_shutdown
,
2618 .digital_mute
= wm8994_aif_mute
,
2619 .set_pll
= wm8994_set_fll
,
2620 .set_tristate
= wm8994_set_tristate
,
2623 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops
= {
2624 .set_sysclk
= wm8994_set_dai_sysclk
,
2625 .set_fmt
= wm8994_set_dai_fmt
,
2626 .hw_params
= wm8994_hw_params
,
2627 .shutdown
= wm8994_aif_shutdown
,
2628 .digital_mute
= wm8994_aif_mute
,
2629 .set_pll
= wm8994_set_fll
,
2630 .set_tristate
= wm8994_set_tristate
,
2633 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops
= {
2634 .hw_params
= wm8994_aif3_hw_params
,
2635 .set_tristate
= wm8994_set_tristate
,
2638 static struct snd_soc_dai_driver wm8994_dai
[] = {
2640 .name
= "wm8994-aif1",
2643 .stream_name
= "AIF1 Playback",
2646 .rates
= WM8994_RATES
,
2647 .formats
= WM8994_FORMATS
,
2650 .stream_name
= "AIF1 Capture",
2653 .rates
= WM8994_RATES
,
2654 .formats
= WM8994_FORMATS
,
2656 .ops
= &wm8994_aif1_dai_ops
,
2659 .name
= "wm8994-aif2",
2662 .stream_name
= "AIF2 Playback",
2665 .rates
= WM8994_RATES
,
2666 .formats
= WM8994_FORMATS
,
2669 .stream_name
= "AIF2 Capture",
2672 .rates
= WM8994_RATES
,
2673 .formats
= WM8994_FORMATS
,
2675 .probe
= wm8994_aif2_probe
,
2676 .ops
= &wm8994_aif2_dai_ops
,
2679 .name
= "wm8994-aif3",
2682 .stream_name
= "AIF3 Playback",
2685 .rates
= WM8994_RATES
,
2686 .formats
= WM8994_FORMATS
,
2689 .stream_name
= "AIF3 Capture",
2692 .rates
= WM8994_RATES
,
2693 .formats
= WM8994_FORMATS
,
2695 .ops
= &wm8994_aif3_dai_ops
,
2700 static int wm8994_suspend(struct snd_soc_codec
*codec
)
2702 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2703 struct wm8994
*control
= wm8994
->wm8994
;
2706 switch (control
->type
) {
2708 snd_soc_update_bits(codec
, WM8994_MICBIAS
, WM8994_MICD_ENA
, 0);
2711 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
2712 WM1811_JACKDET_MODE_MASK
, 0);
2715 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
2716 WM8958_MICD_ENA
, 0);
2720 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll
); i
++) {
2721 memcpy(&wm8994
->fll_suspend
[i
], &wm8994
->fll
[i
],
2722 sizeof(struct wm8994_fll_config
));
2723 ret
= _wm8994_set_fll(codec
, i
+ 1, 0, 0, 0);
2725 dev_warn(codec
->dev
, "Failed to stop FLL%d: %d\n",
2729 wm8994_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
2734 static int wm8994_resume(struct snd_soc_codec
*codec
)
2736 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2737 struct wm8994
*control
= wm8994
->wm8994
;
2739 unsigned int val
, mask
;
2741 if (wm8994
->revision
< 4) {
2742 /* force a HW read */
2743 ret
= regmap_read(control
->regmap
,
2744 WM8994_POWER_MANAGEMENT_5
, &val
);
2746 /* modify the cache only */
2747 codec
->cache_only
= 1;
2748 mask
= WM8994_DAC1R_ENA
| WM8994_DAC1L_ENA
|
2749 WM8994_DAC2R_ENA
| WM8994_DAC2L_ENA
;
2751 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
2753 codec
->cache_only
= 0;
2756 /* Restore the registers */
2757 ret
= snd_soc_cache_sync(codec
);
2759 dev_err(codec
->dev
, "Failed to sync cache: %d\n", ret
);
2761 wm8994_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
2763 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll
); i
++) {
2764 if (!wm8994
->fll_suspend
[i
].out
)
2767 ret
= _wm8994_set_fll(codec
, i
+ 1,
2768 wm8994
->fll_suspend
[i
].src
,
2769 wm8994
->fll_suspend
[i
].in
,
2770 wm8994
->fll_suspend
[i
].out
);
2772 dev_warn(codec
->dev
, "Failed to restore FLL%d: %d\n",
2776 switch (control
->type
) {
2778 if (wm8994
->micdet
[0].jack
|| wm8994
->micdet
[1].jack
)
2779 snd_soc_update_bits(codec
, WM8994_MICBIAS
,
2780 WM8994_MICD_ENA
, WM8994_MICD_ENA
);
2783 if (wm8994
->jackdet
&& wm8994
->jack_cb
) {
2784 /* Restart from idle */
2785 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
2786 WM1811_JACKDET_MODE_MASK
,
2787 WM1811_JACKDET_MODE_JACK
);
2791 if (wm8994
->jack_cb
)
2792 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
2793 WM8958_MICD_ENA
, WM8958_MICD_ENA
);
2800 #define wm8994_suspend NULL
2801 #define wm8994_resume NULL
2804 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv
*wm8994
)
2806 struct snd_soc_codec
*codec
= wm8994
->codec
;
2807 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
2808 struct snd_kcontrol_new controls
[] = {
2809 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2810 wm8994
->retune_mobile_enum
,
2811 wm8994_get_retune_mobile_enum
,
2812 wm8994_put_retune_mobile_enum
),
2813 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2814 wm8994
->retune_mobile_enum
,
2815 wm8994_get_retune_mobile_enum
,
2816 wm8994_put_retune_mobile_enum
),
2817 SOC_ENUM_EXT("AIF2 EQ Mode",
2818 wm8994
->retune_mobile_enum
,
2819 wm8994_get_retune_mobile_enum
,
2820 wm8994_put_retune_mobile_enum
),
2825 /* We need an array of texts for the enum API but the number
2826 * of texts is likely to be less than the number of
2827 * configurations due to the sample rate dependency of the
2828 * configurations. */
2829 wm8994
->num_retune_mobile_texts
= 0;
2830 wm8994
->retune_mobile_texts
= NULL
;
2831 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
2832 for (j
= 0; j
< wm8994
->num_retune_mobile_texts
; j
++) {
2833 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
2834 wm8994
->retune_mobile_texts
[j
]) == 0)
2838 if (j
!= wm8994
->num_retune_mobile_texts
)
2841 /* Expand the array... */
2842 t
= krealloc(wm8994
->retune_mobile_texts
,
2844 (wm8994
->num_retune_mobile_texts
+ 1),
2849 /* ...store the new entry... */
2850 t
[wm8994
->num_retune_mobile_texts
] =
2851 pdata
->retune_mobile_cfgs
[i
].name
;
2853 /* ...and remember the new version. */
2854 wm8994
->num_retune_mobile_texts
++;
2855 wm8994
->retune_mobile_texts
= t
;
2858 dev_dbg(codec
->dev
, "Allocated %d unique ReTune Mobile names\n",
2859 wm8994
->num_retune_mobile_texts
);
2861 wm8994
->retune_mobile_enum
.max
= wm8994
->num_retune_mobile_texts
;
2862 wm8994
->retune_mobile_enum
.texts
= wm8994
->retune_mobile_texts
;
2864 ret
= snd_soc_add_controls(wm8994
->codec
, controls
,
2865 ARRAY_SIZE(controls
));
2867 dev_err(wm8994
->codec
->dev
,
2868 "Failed to add ReTune Mobile controls: %d\n", ret
);
2871 static void wm8994_handle_pdata(struct wm8994_priv
*wm8994
)
2873 struct snd_soc_codec
*codec
= wm8994
->codec
;
2874 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
2880 wm_hubs_handle_analogue_pdata(codec
, pdata
->lineout1_diff
,
2881 pdata
->lineout2_diff
,
2886 pdata
->micbias1_lvl
,
2887 pdata
->micbias2_lvl
);
2889 dev_dbg(codec
->dev
, "%d DRC configurations\n", pdata
->num_drc_cfgs
);
2891 if (pdata
->num_drc_cfgs
) {
2892 struct snd_kcontrol_new controls
[] = {
2893 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994
->drc_enum
,
2894 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
2895 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994
->drc_enum
,
2896 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
2897 SOC_ENUM_EXT("AIF2DRC Mode", wm8994
->drc_enum
,
2898 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
2901 /* We need an array of texts for the enum API */
2902 wm8994
->drc_texts
= devm_kzalloc(wm8994
->codec
->dev
,
2903 sizeof(char *) * pdata
->num_drc_cfgs
, GFP_KERNEL
);
2904 if (!wm8994
->drc_texts
) {
2905 dev_err(wm8994
->codec
->dev
,
2906 "Failed to allocate %d DRC config texts\n",
2907 pdata
->num_drc_cfgs
);
2911 for (i
= 0; i
< pdata
->num_drc_cfgs
; i
++)
2912 wm8994
->drc_texts
[i
] = pdata
->drc_cfgs
[i
].name
;
2914 wm8994
->drc_enum
.max
= pdata
->num_drc_cfgs
;
2915 wm8994
->drc_enum
.texts
= wm8994
->drc_texts
;
2917 ret
= snd_soc_add_controls(wm8994
->codec
, controls
,
2918 ARRAY_SIZE(controls
));
2920 dev_err(wm8994
->codec
->dev
,
2921 "Failed to add DRC mode controls: %d\n", ret
);
2923 for (i
= 0; i
< WM8994_NUM_DRC
; i
++)
2924 wm8994_set_drc(codec
, i
);
2927 dev_dbg(codec
->dev
, "%d ReTune Mobile configurations\n",
2928 pdata
->num_retune_mobile_cfgs
);
2930 if (pdata
->num_retune_mobile_cfgs
)
2931 wm8994_handle_retune_mobile_pdata(wm8994
);
2933 snd_soc_add_controls(wm8994
->codec
, wm8994_eq_controls
,
2934 ARRAY_SIZE(wm8994_eq_controls
));
2936 for (i
= 0; i
< ARRAY_SIZE(pdata
->micbias
); i
++) {
2937 if (pdata
->micbias
[i
]) {
2938 snd_soc_write(codec
, WM8958_MICBIAS1
+ i
,
2939 pdata
->micbias
[i
] & 0xffff);
2945 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2947 * @codec: WM8994 codec
2948 * @jack: jack to report detection events on
2949 * @micbias: microphone bias to detect on
2950 * @det: value to report for presence detection
2951 * @shrt: value to report for short detection
2953 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
2954 * being used to bring out signals to the processor then only platform
2955 * data configuration is needed for WM8994 and processor GPIOs should
2956 * be configured using snd_soc_jack_add_gpios() instead.
2958 * Configuration of detection levels is available via the micbias1_lvl
2959 * and micbias2_lvl platform data members.
2961 int wm8994_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
2962 int micbias
, int det
, int shrt
)
2964 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2965 struct wm8994_micdet
*micdet
;
2966 struct wm8994
*control
= wm8994
->wm8994
;
2969 if (control
->type
!= WM8994
)
2974 micdet
= &wm8994
->micdet
[0];
2977 micdet
= &wm8994
->micdet
[1];
2983 dev_dbg(codec
->dev
, "Configuring microphone detection on %d: %x %x\n",
2984 micbias
, det
, shrt
);
2986 /* Store the configuration */
2987 micdet
->jack
= jack
;
2989 micdet
->shrt
= shrt
;
2991 /* If either of the jacks is set up then enable detection */
2992 if (wm8994
->micdet
[0].jack
|| wm8994
->micdet
[1].jack
)
2993 reg
= WM8994_MICD_ENA
;
2997 snd_soc_update_bits(codec
, WM8994_MICBIAS
, WM8994_MICD_ENA
, reg
);
3001 EXPORT_SYMBOL_GPL(wm8994_mic_detect
);
3003 static irqreturn_t
wm8994_mic_irq(int irq
, void *data
)
3005 struct wm8994_priv
*priv
= data
;
3006 struct snd_soc_codec
*codec
= priv
->codec
;
3010 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3011 trace_snd_soc_jack_irq(dev_name(codec
->dev
));
3014 reg
= snd_soc_read(codec
, WM8994_INTERRUPT_RAW_STATUS_2
);
3016 dev_err(codec
->dev
, "Failed to read microphone status: %d\n",
3021 dev_dbg(codec
->dev
, "Microphone status: %x\n", reg
);
3024 if (reg
& WM8994_MIC1_DET_STS
)
3025 report
|= priv
->micdet
[0].det
;
3026 if (reg
& WM8994_MIC1_SHRT_STS
)
3027 report
|= priv
->micdet
[0].shrt
;
3028 snd_soc_jack_report(priv
->micdet
[0].jack
, report
,
3029 priv
->micdet
[0].det
| priv
->micdet
[0].shrt
);
3032 if (reg
& WM8994_MIC2_DET_STS
)
3033 report
|= priv
->micdet
[1].det
;
3034 if (reg
& WM8994_MIC2_SHRT_STS
)
3035 report
|= priv
->micdet
[1].shrt
;
3036 snd_soc_jack_report(priv
->micdet
[1].jack
, report
,
3037 priv
->micdet
[1].det
| priv
->micdet
[1].shrt
);
3042 /* Default microphone detection handler for WM8958 - the user can
3043 * override this if they wish.
3045 static void wm8958_default_micdet(u16 status
, void *data
)
3047 struct snd_soc_codec
*codec
= data
;
3048 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3051 dev_dbg(codec
->dev
, "MICDET %x\n", status
);
3053 /* Either nothing present or just starting detection */
3054 if (!(status
& WM8958_MICD_STS
)) {
3055 if (!wm8994
->jackdet
) {
3056 /* If nothing present then clear our statuses */
3057 dev_dbg(codec
->dev
, "Detected open circuit\n");
3058 wm8994
->jack_mic
= false;
3059 wm8994
->mic_detecting
= true;
3061 wm8958_micd_set_rate(codec
);
3063 snd_soc_jack_report(wm8994
->micdet
[0].jack
, 0,
3070 /* If the measurement is showing a high impedence we've got a
3073 if (wm8994
->mic_detecting
&& (status
& 0x600)) {
3074 dev_dbg(codec
->dev
, "Detected microphone\n");
3076 wm8994
->mic_detecting
= false;
3077 wm8994
->jack_mic
= true;
3079 wm8958_micd_set_rate(codec
);
3081 snd_soc_jack_report(wm8994
->micdet
[0].jack
, SND_JACK_HEADSET
,
3086 if (wm8994
->mic_detecting
&& status
& 0x4) {
3087 dev_dbg(codec
->dev
, "Detected headphone\n");
3088 wm8994
->mic_detecting
= false;
3090 wm8958_micd_set_rate(codec
);
3092 snd_soc_jack_report(wm8994
->micdet
[0].jack
, SND_JACK_HEADPHONE
,
3095 /* If we have jackdet that will detect removal */
3096 if (wm8994
->jackdet
) {
3097 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3098 WM8958_MICD_ENA
, 0);
3100 wm1811_jackdet_set_mode(codec
,
3101 WM1811_JACKDET_MODE_JACK
);
3105 /* Report short circuit as a button */
3106 if (wm8994
->jack_mic
) {
3109 report
|= SND_JACK_BTN_0
;
3112 report
|= SND_JACK_BTN_1
;
3115 report
|= SND_JACK_BTN_2
;
3118 report
|= SND_JACK_BTN_3
;
3121 report
|= SND_JACK_BTN_4
;
3124 report
|= SND_JACK_BTN_5
;
3126 snd_soc_jack_report(wm8994
->micdet
[0].jack
, report
,
3131 static irqreturn_t
wm1811_jackdet_irq(int irq
, void *data
)
3133 struct wm8994_priv
*wm8994
= data
;
3134 struct snd_soc_codec
*codec
= wm8994
->codec
;
3137 mutex_lock(&wm8994
->accdet_lock
);
3139 reg
= snd_soc_read(codec
, WM1811_JACKDET_CTRL
);
3141 dev_err(codec
->dev
, "Failed to read jack status: %d\n", reg
);
3142 mutex_unlock(&wm8994
->accdet_lock
);
3146 dev_dbg(codec
->dev
, "JACKDET %x\n", reg
);
3148 if (reg
& WM1811_JACKDET_LVL
) {
3149 dev_dbg(codec
->dev
, "Jack detected\n");
3151 snd_soc_jack_report(wm8994
->micdet
[0].jack
,
3152 SND_JACK_MECHANICAL
, SND_JACK_MECHANICAL
);
3155 * Start off measument of microphone impedence to find
3156 * out what's actually there.
3158 wm8994
->mic_detecting
= true;
3159 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_MIC
);
3160 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3161 WM8958_MICD_ENA
, WM8958_MICD_ENA
);
3163 dev_dbg(codec
->dev
, "Jack not detected\n");
3165 snd_soc_jack_report(wm8994
->micdet
[0].jack
, 0,
3166 SND_JACK_MECHANICAL
| SND_JACK_HEADSET
|
3169 wm8994
->mic_detecting
= false;
3170 wm8994
->jack_mic
= false;
3171 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3172 WM8958_MICD_ENA
, 0);
3173 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_JACK
);
3176 mutex_unlock(&wm8994
->accdet_lock
);
3182 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3184 * @codec: WM8958 codec
3185 * @jack: jack to report detection events on
3187 * Enable microphone detection functionality for the WM8958. By
3188 * default simple detection which supports the detection of up to 6
3189 * buttons plus video and microphone functionality is supported.
3191 * The WM8958 has an advanced jack detection facility which is able to
3192 * support complex accessory detection, especially when used in
3193 * conjunction with external circuitry. In order to provide maximum
3194 * flexiblity a callback is provided which allows a completely custom
3195 * detection algorithm.
3197 int wm8958_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
3198 wm8958_micdet_cb cb
, void *cb_data
)
3200 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3201 struct wm8994
*control
= wm8994
->wm8994
;
3204 switch (control
->type
) {
3214 dev_dbg(codec
->dev
, "Using default micdet callback\n");
3215 cb
= wm8958_default_micdet
;
3219 snd_soc_dapm_force_enable_pin(&codec
->dapm
, "CLK_SYS");
3221 wm8994
->micdet
[0].jack
= jack
;
3222 wm8994
->jack_cb
= cb
;
3223 wm8994
->jack_cb_data
= cb_data
;
3225 wm8994
->mic_detecting
= true;
3226 wm8994
->jack_mic
= false;
3228 wm8958_micd_set_rate(codec
);
3230 /* Detect microphones and short circuits by default */
3231 if (wm8994
->pdata
->micd_lvl_sel
)
3232 micd_lvl_sel
= wm8994
->pdata
->micd_lvl_sel
;
3234 micd_lvl_sel
= 0x41;
3236 wm8994
->btn_mask
= SND_JACK_BTN_0
| SND_JACK_BTN_1
|
3237 SND_JACK_BTN_2
| SND_JACK_BTN_3
|
3238 SND_JACK_BTN_4
| SND_JACK_BTN_5
;
3240 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_2
,
3241 WM8958_MICD_LVL_SEL_MASK
, micd_lvl_sel
);
3243 WARN_ON(codec
->dapm
.bias_level
> SND_SOC_BIAS_STANDBY
);
3246 * If we can use jack detection start off with that,
3247 * otherwise jump straight to microphone detection.
3249 if (wm8994
->jackdet
) {
3250 snd_soc_update_bits(codec
, WM8994_LDO_1
,
3251 WM8994_LDO1_DISCH
, 0);
3252 wm1811_jackdet_set_mode(codec
,
3253 WM1811_JACKDET_MODE_JACK
);
3255 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3256 WM8958_MICD_ENA
, WM8958_MICD_ENA
);
3260 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3261 WM8958_MICD_ENA
, 0);
3262 snd_soc_dapm_disable_pin(&codec
->dapm
, "CLK_SYS");
3267 EXPORT_SYMBOL_GPL(wm8958_mic_detect
);
3269 static irqreturn_t
wm8958_mic_irq(int irq
, void *data
)
3271 struct wm8994_priv
*wm8994
= data
;
3272 struct snd_soc_codec
*codec
= wm8994
->codec
;
3275 mutex_lock(&wm8994
->accdet_lock
);
3278 * Jack detection may have detected a removal simulataneously
3279 * with an update of the MICDET status; if so it will have
3280 * stopped detection and we can ignore this interrupt.
3282 if (!(snd_soc_read(codec
, WM8958_MIC_DETECT_1
) & WM8958_MICD_ENA
)) {
3283 mutex_unlock(&wm8994
->accdet_lock
);
3287 /* We may occasionally read a detection without an impedence
3288 * range being provided - if that happens loop again.
3292 reg
= snd_soc_read(codec
, WM8958_MIC_DETECT_3
);
3294 mutex_unlock(&wm8994
->accdet_lock
);
3296 "Failed to read mic detect status: %d\n",
3301 if (!(reg
& WM8958_MICD_VALID
)) {
3302 dev_dbg(codec
->dev
, "Mic detect data not valid\n");
3306 if (!(reg
& WM8958_MICD_STS
) || (reg
& WM8958_MICD_LVL_MASK
))
3313 dev_warn(codec
->dev
, "No impedence range reported for jack\n");
3315 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3316 trace_snd_soc_jack_irq(dev_name(codec
->dev
));
3319 if (wm8994
->jack_cb
)
3320 wm8994
->jack_cb(reg
, wm8994
->jack_cb_data
);
3322 dev_warn(codec
->dev
, "Accessory detection with no callback\n");
3325 mutex_unlock(&wm8994
->accdet_lock
);
3330 static irqreturn_t
wm8994_fifo_error(int irq
, void *data
)
3332 struct snd_soc_codec
*codec
= data
;
3334 dev_err(codec
->dev
, "FIFO error\n");
3339 static irqreturn_t
wm8994_temp_warn(int irq
, void *data
)
3341 struct snd_soc_codec
*codec
= data
;
3343 dev_err(codec
->dev
, "Thermal warning\n");
3348 static irqreturn_t
wm8994_temp_shut(int irq
, void *data
)
3350 struct snd_soc_codec
*codec
= data
;
3352 dev_crit(codec
->dev
, "Thermal shutdown\n");
3357 static int wm8994_codec_probe(struct snd_soc_codec
*codec
)
3359 struct wm8994
*control
= dev_get_drvdata(codec
->dev
->parent
);
3360 struct wm8994_priv
*wm8994
;
3361 struct snd_soc_dapm_context
*dapm
= &codec
->dapm
;
3365 codec
->control_data
= control
->regmap
;
3367 wm8994
= devm_kzalloc(codec
->dev
, sizeof(struct wm8994_priv
),
3371 snd_soc_codec_set_drvdata(codec
, wm8994
);
3373 snd_soc_codec_set_cache_io(codec
, 16, 16, SND_SOC_REGMAP
);
3375 wm8994
->wm8994
= dev_get_drvdata(codec
->dev
->parent
);
3376 wm8994
->pdata
= dev_get_platdata(codec
->dev
->parent
);
3377 wm8994
->codec
= codec
;
3379 mutex_init(&wm8994
->accdet_lock
);
3381 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++)
3382 init_completion(&wm8994
->fll_locked
[i
]);
3384 if (wm8994
->pdata
&& wm8994
->pdata
->micdet_irq
)
3385 wm8994
->micdet_irq
= wm8994
->pdata
->micdet_irq
;
3386 else if (wm8994
->pdata
&& wm8994
->pdata
->irq_base
)
3387 wm8994
->micdet_irq
= wm8994
->pdata
->irq_base
+
3388 WM8994_IRQ_MIC1_DET
;
3390 pm_runtime_enable(codec
->dev
);
3391 pm_runtime_resume(codec
->dev
);
3393 /* Set revision-specific configuration */
3394 wm8994
->revision
= snd_soc_read(codec
, WM8994_CHIP_REVISION
);
3395 switch (control
->type
) {
3397 switch (wm8994
->revision
) {
3400 wm8994
->hubs
.dcs_codes_l
= -5;
3401 wm8994
->hubs
.dcs_codes_r
= -5;
3402 wm8994
->hubs
.hp_startup_mode
= 1;
3403 wm8994
->hubs
.dcs_readback_mode
= 1;
3404 wm8994
->hubs
.series_startup
= 1;
3407 wm8994
->hubs
.dcs_readback_mode
= 2;
3413 wm8994
->hubs
.dcs_readback_mode
= 1;
3417 wm8994
->hubs
.dcs_readback_mode
= 2;
3418 wm8994
->hubs
.no_series_update
= 1;
3420 switch (wm8994
->revision
) {
3425 wm8994
->hubs
.dcs_codes_l
= -9;
3426 wm8994
->hubs
.dcs_codes_r
= -5;
3432 snd_soc_update_bits(codec
, WM8994_ANALOGUE_HP_1
,
3433 WM1811_HPOUT1_ATTN
, WM1811_HPOUT1_ATTN
);
3440 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_FIFOS_ERR
,
3441 wm8994_fifo_error
, "FIFO error", codec
);
3442 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_WARN
,
3443 wm8994_temp_warn
, "Thermal warning", codec
);
3444 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_SHUT
,
3445 wm8994_temp_shut
, "Thermal shutdown", codec
);
3447 ret
= wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_DCS_DONE
,
3448 wm_hubs_dcs_done
, "DC servo done",
3451 wm8994
->hubs
.dcs_done_irq
= true;
3453 switch (control
->type
) {
3455 if (wm8994
->micdet_irq
) {
3456 ret
= request_threaded_irq(wm8994
->micdet_irq
, NULL
,
3458 IRQF_TRIGGER_RISING
,
3462 dev_warn(codec
->dev
,
3463 "Failed to request Mic1 detect IRQ: %d\n",
3467 ret
= wm8994_request_irq(wm8994
->wm8994
,
3468 WM8994_IRQ_MIC1_SHRT
,
3469 wm8994_mic_irq
, "Mic 1 short",
3472 dev_warn(codec
->dev
,
3473 "Failed to request Mic1 short IRQ: %d\n",
3476 ret
= wm8994_request_irq(wm8994
->wm8994
,
3477 WM8994_IRQ_MIC2_DET
,
3478 wm8994_mic_irq
, "Mic 2 detect",
3481 dev_warn(codec
->dev
,
3482 "Failed to request Mic2 detect IRQ: %d\n",
3485 ret
= wm8994_request_irq(wm8994
->wm8994
,
3486 WM8994_IRQ_MIC2_SHRT
,
3487 wm8994_mic_irq
, "Mic 2 short",
3490 dev_warn(codec
->dev
,
3491 "Failed to request Mic2 short IRQ: %d\n",
3497 if (wm8994
->micdet_irq
) {
3498 ret
= request_threaded_irq(wm8994
->micdet_irq
, NULL
,
3500 IRQF_TRIGGER_RISING
,
3504 dev_warn(codec
->dev
,
3505 "Failed to request Mic detect IRQ: %d\n",
3510 switch (control
->type
) {
3512 if (wm8994
->revision
> 1) {
3513 ret
= wm8994_request_irq(wm8994
->wm8994
,
3515 wm1811_jackdet_irq
, "JACKDET",
3518 wm8994
->jackdet
= true;
3525 wm8994
->fll_locked_irq
= true;
3526 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++) {
3527 ret
= wm8994_request_irq(wm8994
->wm8994
,
3528 WM8994_IRQ_FLL1_LOCK
+ i
,
3529 wm8994_fll_locked_irq
, "FLL lock",
3530 &wm8994
->fll_locked
[i
]);
3532 wm8994
->fll_locked_irq
= false;
3535 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3536 * configured on init - if a system wants to do this dynamically
3537 * at runtime we can deal with that then.
3539 ret
= regmap_read(control
->regmap
, WM8994_GPIO_1
, ®
);
3541 dev_err(codec
->dev
, "Failed to read GPIO1 state: %d\n", ret
);
3544 if ((reg
& WM8994_GPN_FN_MASK
) != WM8994_GP_FN_PIN_SPECIFIC
) {
3545 wm8994
->lrclk_shared
[0] = 1;
3546 wm8994_dai
[0].symmetric_rates
= 1;
3548 wm8994
->lrclk_shared
[0] = 0;
3551 ret
= regmap_read(control
->regmap
, WM8994_GPIO_6
, ®
);
3553 dev_err(codec
->dev
, "Failed to read GPIO6 state: %d\n", ret
);
3556 if ((reg
& WM8994_GPN_FN_MASK
) != WM8994_GP_FN_PIN_SPECIFIC
) {
3557 wm8994
->lrclk_shared
[1] = 1;
3558 wm8994_dai
[1].symmetric_rates
= 1;
3560 wm8994
->lrclk_shared
[1] = 0;
3563 wm8994_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
3565 /* Latch volume updates (right only; we always do left then right). */
3566 snd_soc_update_bits(codec
, WM8994_AIF1_DAC1_LEFT_VOLUME
,
3567 WM8994_AIF1DAC1_VU
, WM8994_AIF1DAC1_VU
);
3568 snd_soc_update_bits(codec
, WM8994_AIF1_DAC1_RIGHT_VOLUME
,
3569 WM8994_AIF1DAC1_VU
, WM8994_AIF1DAC1_VU
);
3570 snd_soc_update_bits(codec
, WM8994_AIF1_DAC2_LEFT_VOLUME
,
3571 WM8994_AIF1DAC2_VU
, WM8994_AIF1DAC2_VU
);
3572 snd_soc_update_bits(codec
, WM8994_AIF1_DAC2_RIGHT_VOLUME
,
3573 WM8994_AIF1DAC2_VU
, WM8994_AIF1DAC2_VU
);
3574 snd_soc_update_bits(codec
, WM8994_AIF2_DAC_LEFT_VOLUME
,
3575 WM8994_AIF2DAC_VU
, WM8994_AIF2DAC_VU
);
3576 snd_soc_update_bits(codec
, WM8994_AIF2_DAC_RIGHT_VOLUME
,
3577 WM8994_AIF2DAC_VU
, WM8994_AIF2DAC_VU
);
3578 snd_soc_update_bits(codec
, WM8994_AIF1_ADC1_LEFT_VOLUME
,
3579 WM8994_AIF1ADC1_VU
, WM8994_AIF1ADC1_VU
);
3580 snd_soc_update_bits(codec
, WM8994_AIF1_ADC1_RIGHT_VOLUME
,
3581 WM8994_AIF1ADC1_VU
, WM8994_AIF1ADC1_VU
);
3582 snd_soc_update_bits(codec
, WM8994_AIF1_ADC2_LEFT_VOLUME
,
3583 WM8994_AIF1ADC2_VU
, WM8994_AIF1ADC2_VU
);
3584 snd_soc_update_bits(codec
, WM8994_AIF1_ADC2_RIGHT_VOLUME
,
3585 WM8994_AIF1ADC2_VU
, WM8994_AIF1ADC2_VU
);
3586 snd_soc_update_bits(codec
, WM8994_AIF2_ADC_LEFT_VOLUME
,
3587 WM8994_AIF2ADC_VU
, WM8994_AIF1ADC2_VU
);
3588 snd_soc_update_bits(codec
, WM8994_AIF2_ADC_RIGHT_VOLUME
,
3589 WM8994_AIF2ADC_VU
, WM8994_AIF1ADC2_VU
);
3590 snd_soc_update_bits(codec
, WM8994_DAC1_LEFT_VOLUME
,
3591 WM8994_DAC1_VU
, WM8994_DAC1_VU
);
3592 snd_soc_update_bits(codec
, WM8994_DAC1_RIGHT_VOLUME
,
3593 WM8994_DAC1_VU
, WM8994_DAC1_VU
);
3594 snd_soc_update_bits(codec
, WM8994_DAC2_LEFT_VOLUME
,
3595 WM8994_DAC2_VU
, WM8994_DAC2_VU
);
3596 snd_soc_update_bits(codec
, WM8994_DAC2_RIGHT_VOLUME
,
3597 WM8994_DAC2_VU
, WM8994_DAC2_VU
);
3599 /* Set the low bit of the 3D stereo depth so TLV matches */
3600 snd_soc_update_bits(codec
, WM8994_AIF1_DAC1_FILTERS_2
,
3601 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT
,
3602 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT
);
3603 snd_soc_update_bits(codec
, WM8994_AIF1_DAC2_FILTERS_2
,
3604 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT
,
3605 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT
);
3606 snd_soc_update_bits(codec
, WM8994_AIF2_DAC_FILTERS_2
,
3607 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT
,
3608 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT
);
3610 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3611 * use this; it only affects behaviour on idle TDM clock
3613 switch (control
->type
) {
3616 snd_soc_update_bits(codec
, WM8994_AIF1_CONTROL_1
,
3617 WM8994_AIF1ADC_TDM
, WM8994_AIF1ADC_TDM
);
3623 /* Put MICBIAS into bypass mode by default on newer devices */
3624 switch (control
->type
) {
3627 snd_soc_update_bits(codec
, WM8958_MICBIAS1
,
3628 WM8958_MICB1_MODE
, WM8958_MICB1_MODE
);
3629 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
3630 WM8958_MICB2_MODE
, WM8958_MICB2_MODE
);
3636 wm8994_update_class_w(codec
);
3638 wm8994_handle_pdata(wm8994
);
3640 wm_hubs_add_analogue_controls(codec
);
3641 snd_soc_add_controls(codec
, wm8994_snd_controls
,
3642 ARRAY_SIZE(wm8994_snd_controls
));
3643 snd_soc_dapm_new_controls(dapm
, wm8994_dapm_widgets
,
3644 ARRAY_SIZE(wm8994_dapm_widgets
));
3646 switch (control
->type
) {
3648 snd_soc_dapm_new_controls(dapm
, wm8994_specific_dapm_widgets
,
3649 ARRAY_SIZE(wm8994_specific_dapm_widgets
));
3650 if (wm8994
->revision
< 4) {
3651 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_revd_widgets
,
3652 ARRAY_SIZE(wm8994_lateclk_revd_widgets
));
3653 snd_soc_dapm_new_controls(dapm
, wm8994_adc_revd_widgets
,
3654 ARRAY_SIZE(wm8994_adc_revd_widgets
));
3655 snd_soc_dapm_new_controls(dapm
, wm8994_dac_revd_widgets
,
3656 ARRAY_SIZE(wm8994_dac_revd_widgets
));
3658 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_widgets
,
3659 ARRAY_SIZE(wm8994_lateclk_widgets
));
3660 snd_soc_dapm_new_controls(dapm
, wm8994_adc_widgets
,
3661 ARRAY_SIZE(wm8994_adc_widgets
));
3662 snd_soc_dapm_new_controls(dapm
, wm8994_dac_widgets
,
3663 ARRAY_SIZE(wm8994_dac_widgets
));
3667 snd_soc_add_controls(codec
, wm8958_snd_controls
,
3668 ARRAY_SIZE(wm8958_snd_controls
));
3669 snd_soc_dapm_new_controls(dapm
, wm8958_dapm_widgets
,
3670 ARRAY_SIZE(wm8958_dapm_widgets
));
3671 if (wm8994
->revision
< 1) {
3672 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_revd_widgets
,
3673 ARRAY_SIZE(wm8994_lateclk_revd_widgets
));
3674 snd_soc_dapm_new_controls(dapm
, wm8994_adc_revd_widgets
,
3675 ARRAY_SIZE(wm8994_adc_revd_widgets
));
3676 snd_soc_dapm_new_controls(dapm
, wm8994_dac_revd_widgets
,
3677 ARRAY_SIZE(wm8994_dac_revd_widgets
));
3679 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_widgets
,
3680 ARRAY_SIZE(wm8994_lateclk_widgets
));
3681 snd_soc_dapm_new_controls(dapm
, wm8994_adc_widgets
,
3682 ARRAY_SIZE(wm8994_adc_widgets
));
3683 snd_soc_dapm_new_controls(dapm
, wm8994_dac_widgets
,
3684 ARRAY_SIZE(wm8994_dac_widgets
));
3689 snd_soc_add_controls(codec
, wm8958_snd_controls
,
3690 ARRAY_SIZE(wm8958_snd_controls
));
3691 snd_soc_dapm_new_controls(dapm
, wm8958_dapm_widgets
,
3692 ARRAY_SIZE(wm8958_dapm_widgets
));
3693 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_widgets
,
3694 ARRAY_SIZE(wm8994_lateclk_widgets
));
3695 snd_soc_dapm_new_controls(dapm
, wm8994_adc_widgets
,
3696 ARRAY_SIZE(wm8994_adc_widgets
));
3697 snd_soc_dapm_new_controls(dapm
, wm8994_dac_widgets
,
3698 ARRAY_SIZE(wm8994_dac_widgets
));
3703 wm_hubs_add_analogue_routes(codec
, 0, 0);
3704 snd_soc_dapm_add_routes(dapm
, intercon
, ARRAY_SIZE(intercon
));
3706 switch (control
->type
) {
3708 snd_soc_dapm_add_routes(dapm
, wm8994_intercon
,
3709 ARRAY_SIZE(wm8994_intercon
));
3711 if (wm8994
->revision
< 4) {
3712 snd_soc_dapm_add_routes(dapm
, wm8994_revd_intercon
,
3713 ARRAY_SIZE(wm8994_revd_intercon
));
3714 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_revd_intercon
,
3715 ARRAY_SIZE(wm8994_lateclk_revd_intercon
));
3717 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_intercon
,
3718 ARRAY_SIZE(wm8994_lateclk_intercon
));
3722 if (wm8994
->revision
< 1) {
3723 snd_soc_dapm_add_routes(dapm
, wm8994_revd_intercon
,
3724 ARRAY_SIZE(wm8994_revd_intercon
));
3725 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_revd_intercon
,
3726 ARRAY_SIZE(wm8994_lateclk_revd_intercon
));
3728 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_intercon
,
3729 ARRAY_SIZE(wm8994_lateclk_intercon
));
3730 snd_soc_dapm_add_routes(dapm
, wm8958_intercon
,
3731 ARRAY_SIZE(wm8958_intercon
));
3734 wm8958_dsp2_init(codec
);
3737 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_intercon
,
3738 ARRAY_SIZE(wm8994_lateclk_intercon
));
3739 snd_soc_dapm_add_routes(dapm
, wm8958_intercon
,
3740 ARRAY_SIZE(wm8958_intercon
));
3747 if (wm8994
->jackdet
)
3748 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_GPIO(6), wm8994
);
3749 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC2_SHRT
, wm8994
);
3750 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC2_DET
, wm8994
);
3751 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_SHRT
, wm8994
);
3752 if (wm8994
->micdet_irq
)
3753 free_irq(wm8994
->micdet_irq
, wm8994
);
3754 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++)
3755 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FLL1_LOCK
+ i
,
3756 &wm8994
->fll_locked
[i
]);
3757 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_DCS_DONE
,
3759 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FIFOS_ERR
, codec
);
3760 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_SHUT
, codec
);
3761 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_WARN
, codec
);
3766 static int wm8994_codec_remove(struct snd_soc_codec
*codec
)
3768 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3769 struct wm8994
*control
= wm8994
->wm8994
;
3772 wm8994_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
3774 pm_runtime_disable(codec
->dev
);
3776 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++)
3777 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FLL1_LOCK
+ i
,
3778 &wm8994
->fll_locked
[i
]);
3780 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_DCS_DONE
,
3782 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FIFOS_ERR
, codec
);
3783 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_SHUT
, codec
);
3784 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_WARN
, codec
);
3786 if (wm8994
->jackdet
)
3787 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_GPIO(6), wm8994
);
3789 switch (control
->type
) {
3791 if (wm8994
->micdet_irq
)
3792 free_irq(wm8994
->micdet_irq
, wm8994
);
3793 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC2_DET
,
3795 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_SHRT
,
3797 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_DET
,
3803 if (wm8994
->micdet_irq
)
3804 free_irq(wm8994
->micdet_irq
, wm8994
);
3808 release_firmware(wm8994
->mbc
);
3809 if (wm8994
->mbc_vss
)
3810 release_firmware(wm8994
->mbc_vss
);
3812 release_firmware(wm8994
->enh_eq
);
3813 kfree(wm8994
->retune_mobile_texts
);
3818 static int wm8994_soc_volatile(struct snd_soc_codec
*codec
,
3824 static struct snd_soc_codec_driver soc_codec_dev_wm8994
= {
3825 .probe
= wm8994_codec_probe
,
3826 .remove
= wm8994_codec_remove
,
3827 .suspend
= wm8994_suspend
,
3828 .resume
= wm8994_resume
,
3829 .set_bias_level
= wm8994_set_bias_level
,
3830 .reg_cache_size
= WM8994_MAX_REGISTER
,
3831 .volatile_register
= wm8994_soc_volatile
,
3834 static int __devinit
wm8994_probe(struct platform_device
*pdev
)
3836 return snd_soc_register_codec(&pdev
->dev
, &soc_codec_dev_wm8994
,
3837 wm8994_dai
, ARRAY_SIZE(wm8994_dai
));
3840 static int __devexit
wm8994_remove(struct platform_device
*pdev
)
3842 snd_soc_unregister_codec(&pdev
->dev
);
3846 static struct platform_driver wm8994_codec_driver
= {
3848 .name
= "wm8994-codec",
3849 .owner
= THIS_MODULE
,
3851 .probe
= wm8994_probe
,
3852 .remove
= __devexit_p(wm8994_remove
),
3855 module_platform_driver(wm8994_codec_driver
);
3857 MODULE_DESCRIPTION("ASoC WM8994 driver");
3858 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3859 MODULE_LICENSE("GPL");
3860 MODULE_ALIAS("platform:wm8994-codec");