2 * wm8994.c -- WM8994 ALSA SoC Audio driver
4 * Copyright 2009-12 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
19 #include <linux/gcd.h>
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/slab.h>
25 #include <sound/core.h>
26 #include <sound/jack.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
32 #include <trace/events/asoc.h>
34 #include <linux/mfd/wm8994/core.h>
35 #include <linux/mfd/wm8994/registers.h>
36 #include <linux/mfd/wm8994/pdata.h>
37 #include <linux/mfd/wm8994/gpio.h>
42 #define WM1811_JACKDET_MODE_NONE 0x0000
43 #define WM1811_JACKDET_MODE_JACK 0x0100
44 #define WM1811_JACKDET_MODE_MIC 0x0080
45 #define WM1811_JACKDET_MODE_AUDIO 0x0180
47 #define WM8994_NUM_DRC 3
48 #define WM8994_NUM_EQ 3
53 } wm8994_vu_bits
[] = {
54 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME
, WM8994_IN1_VU
},
55 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME
, WM8994_IN1_VU
},
56 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME
, WM8994_IN2_VU
},
57 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME
, WM8994_IN2_VU
},
58 { WM8994_SPEAKER_VOLUME_LEFT
, WM8994_SPKOUT_VU
},
59 { WM8994_SPEAKER_VOLUME_RIGHT
, WM8994_SPKOUT_VU
},
60 { WM8994_LEFT_OUTPUT_VOLUME
, WM8994_HPOUT1_VU
},
61 { WM8994_RIGHT_OUTPUT_VOLUME
, WM8994_HPOUT1_VU
},
62 { WM8994_LEFT_OPGA_VOLUME
, WM8994_MIXOUT_VU
},
63 { WM8994_RIGHT_OPGA_VOLUME
, WM8994_MIXOUT_VU
},
65 { WM8994_AIF1_DAC1_LEFT_VOLUME
, WM8994_AIF1DAC1_VU
},
66 { WM8994_AIF1_DAC1_RIGHT_VOLUME
, WM8994_AIF1DAC1_VU
},
67 { WM8994_AIF1_DAC2_LEFT_VOLUME
, WM8994_AIF1DAC2_VU
},
68 { WM8994_AIF1_DAC2_RIGHT_VOLUME
, WM8994_AIF1DAC2_VU
},
69 { WM8994_AIF2_DAC_LEFT_VOLUME
, WM8994_AIF2DAC_VU
},
70 { WM8994_AIF2_DAC_RIGHT_VOLUME
, WM8994_AIF2DAC_VU
},
71 { WM8994_AIF1_ADC1_LEFT_VOLUME
, WM8994_AIF1ADC1_VU
},
72 { WM8994_AIF1_ADC1_RIGHT_VOLUME
, WM8994_AIF1ADC1_VU
},
73 { WM8994_AIF1_ADC2_LEFT_VOLUME
, WM8994_AIF1ADC2_VU
},
74 { WM8994_AIF1_ADC2_RIGHT_VOLUME
, WM8994_AIF1ADC2_VU
},
75 { WM8994_AIF2_ADC_LEFT_VOLUME
, WM8994_AIF2ADC_VU
},
76 { WM8994_AIF2_ADC_RIGHT_VOLUME
, WM8994_AIF1ADC2_VU
},
77 { WM8994_DAC1_LEFT_VOLUME
, WM8994_DAC1_VU
},
78 { WM8994_DAC1_RIGHT_VOLUME
, WM8994_DAC1_VU
},
79 { WM8994_DAC2_LEFT_VOLUME
, WM8994_DAC2_VU
},
80 { WM8994_DAC2_RIGHT_VOLUME
, WM8994_DAC2_VU
},
83 static int wm8994_drc_base
[] = {
89 static int wm8994_retune_mobile_base
[] = {
90 WM8994_AIF1_DAC1_EQ_GAINS_1
,
91 WM8994_AIF1_DAC2_EQ_GAINS_1
,
92 WM8994_AIF2_EQ_GAINS_1
,
95 static const struct wm8958_micd_rate micdet_rates
[] = {
96 { 32768, true, 1, 4 },
97 { 32768, false, 1, 1 },
98 { 44100 * 256, true, 7, 10 },
99 { 44100 * 256, false, 7, 10 },
102 static const struct wm8958_micd_rate jackdet_rates
[] = {
103 { 32768, true, 0, 1 },
104 { 32768, false, 0, 1 },
105 { 44100 * 256, true, 10, 10 },
106 { 44100 * 256, false, 7, 8 },
109 static void wm8958_micd_set_rate(struct snd_soc_codec
*codec
)
111 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
112 struct wm8994
*control
= wm8994
->wm8994
;
113 int best
, i
, sysclk
, val
;
115 const struct wm8958_micd_rate
*rates
;
118 idle
= !wm8994
->jack_mic
;
120 sysclk
= snd_soc_read(codec
, WM8994_CLOCKING_1
);
121 if (sysclk
& WM8994_SYSCLK_SRC
)
122 sysclk
= wm8994
->aifclk
[1];
124 sysclk
= wm8994
->aifclk
[0];
126 if (control
->pdata
.micd_rates
) {
127 rates
= control
->pdata
.micd_rates
;
128 num_rates
= control
->pdata
.num_micd_rates
;
129 } else if (wm8994
->jackdet
) {
130 rates
= jackdet_rates
;
131 num_rates
= ARRAY_SIZE(jackdet_rates
);
133 rates
= micdet_rates
;
134 num_rates
= ARRAY_SIZE(micdet_rates
);
138 for (i
= 0; i
< num_rates
; i
++) {
139 if (rates
[i
].idle
!= idle
)
141 if (abs(rates
[i
].sysclk
- sysclk
) <
142 abs(rates
[best
].sysclk
- sysclk
))
144 else if (rates
[best
].idle
!= idle
)
148 val
= rates
[best
].start
<< WM8958_MICD_BIAS_STARTTIME_SHIFT
149 | rates
[best
].rate
<< WM8958_MICD_RATE_SHIFT
;
151 dev_dbg(codec
->dev
, "MICD rate %d,%d for %dHz %s\n",
152 rates
[best
].start
, rates
[best
].rate
, sysclk
,
153 idle
? "idle" : "active");
155 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
156 WM8958_MICD_BIAS_STARTTIME_MASK
|
157 WM8958_MICD_RATE_MASK
, val
);
160 static int configure_aif_clock(struct snd_soc_codec
*codec
, int aif
)
162 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
172 switch (wm8994
->sysclk
[aif
]) {
173 case WM8994_SYSCLK_MCLK1
:
174 rate
= wm8994
->mclk
[0];
177 case WM8994_SYSCLK_MCLK2
:
179 rate
= wm8994
->mclk
[1];
182 case WM8994_SYSCLK_FLL1
:
184 rate
= wm8994
->fll
[0].out
;
187 case WM8994_SYSCLK_FLL2
:
189 rate
= wm8994
->fll
[1].out
;
196 if (rate
>= 13500000) {
198 reg1
|= WM8994_AIF1CLK_DIV
;
200 dev_dbg(codec
->dev
, "Dividing AIF%d clock to %dHz\n",
204 wm8994
->aifclk
[aif
] = rate
;
206 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
+ offset
,
207 WM8994_AIF1CLK_SRC_MASK
| WM8994_AIF1CLK_DIV
,
213 static int configure_clock(struct snd_soc_codec
*codec
)
215 struct snd_soc_dapm_context
*dapm
= snd_soc_codec_get_dapm(codec
);
216 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
219 /* Bring up the AIF clocks first */
220 configure_aif_clock(codec
, 0);
221 configure_aif_clock(codec
, 1);
223 /* Then switch CLK_SYS over to the higher of them; a change
224 * can only happen as a result of a clocking change which can
225 * only be made outside of DAPM so we can safely redo the
229 /* If they're equal it doesn't matter which is used */
230 if (wm8994
->aifclk
[0] == wm8994
->aifclk
[1]) {
231 wm8958_micd_set_rate(codec
);
235 if (wm8994
->aifclk
[0] < wm8994
->aifclk
[1])
236 new = WM8994_SYSCLK_SRC
;
240 change
= snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
241 WM8994_SYSCLK_SRC
, new);
243 snd_soc_dapm_sync(dapm
);
245 wm8958_micd_set_rate(codec
);
250 static int check_clk_sys(struct snd_soc_dapm_widget
*source
,
251 struct snd_soc_dapm_widget
*sink
)
253 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(source
->dapm
);
254 int reg
= snd_soc_read(codec
, WM8994_CLOCKING_1
);
257 /* Check what we're currently using for CLK_SYS */
258 if (reg
& WM8994_SYSCLK_SRC
)
263 return strcmp(source
->name
, clk
) == 0;
266 static const char *sidetone_hpf_text
[] = {
267 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
270 static SOC_ENUM_SINGLE_DECL(sidetone_hpf
,
271 WM8994_SIDETONE
, 7, sidetone_hpf_text
);
273 static const char *adc_hpf_text
[] = {
274 "HiFi", "Voice 1", "Voice 2", "Voice 3"
277 static SOC_ENUM_SINGLE_DECL(aif1adc1_hpf
,
278 WM8994_AIF1_ADC1_FILTERS
, 13, adc_hpf_text
);
280 static SOC_ENUM_SINGLE_DECL(aif1adc2_hpf
,
281 WM8994_AIF1_ADC2_FILTERS
, 13, adc_hpf_text
);
283 static SOC_ENUM_SINGLE_DECL(aif2adc_hpf
,
284 WM8994_AIF2_ADC_FILTERS
, 13, adc_hpf_text
);
286 static const DECLARE_TLV_DB_SCALE(aif_tlv
, 0, 600, 0);
287 static const DECLARE_TLV_DB_SCALE(digital_tlv
, -7200, 75, 1);
288 static const DECLARE_TLV_DB_SCALE(st_tlv
, -3600, 300, 0);
289 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv
, -1600, 183, 0);
290 static const DECLARE_TLV_DB_SCALE(eq_tlv
, -1200, 100, 0);
291 static const DECLARE_TLV_DB_SCALE(ng_tlv
, -10200, 600, 0);
292 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv
, 0, 900, 0);
294 #define WM8994_DRC_SWITCH(xname, reg, shift) \
295 SOC_SINGLE_EXT(xname, reg, shift, 1, 0, \
296 snd_soc_get_volsw, wm8994_put_drc_sw)
298 static int wm8994_put_drc_sw(struct snd_kcontrol
*kcontrol
,
299 struct snd_ctl_elem_value
*ucontrol
)
301 struct soc_mixer_control
*mc
=
302 (struct soc_mixer_control
*)kcontrol
->private_value
;
303 struct snd_soc_codec
*codec
= snd_soc_kcontrol_codec(kcontrol
);
306 /* Can't enable both ADC and DAC paths simultaneously */
307 if (mc
->shift
== WM8994_AIF1DAC1_DRC_ENA_SHIFT
)
308 mask
= WM8994_AIF1ADC1L_DRC_ENA_MASK
|
309 WM8994_AIF1ADC1R_DRC_ENA_MASK
;
311 mask
= WM8994_AIF1DAC1_DRC_ENA_MASK
;
313 ret
= snd_soc_read(codec
, mc
->reg
);
319 return snd_soc_put_volsw(kcontrol
, ucontrol
);
322 static void wm8994_set_drc(struct snd_soc_codec
*codec
, int drc
)
324 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
325 struct wm8994
*control
= wm8994
->wm8994
;
326 struct wm8994_pdata
*pdata
= &control
->pdata
;
327 int base
= wm8994_drc_base
[drc
];
328 int cfg
= wm8994
->drc_cfg
[drc
];
331 /* Save any enables; the configuration should clear them. */
332 save
= snd_soc_read(codec
, base
);
333 save
&= WM8994_AIF1DAC1_DRC_ENA
| WM8994_AIF1ADC1L_DRC_ENA
|
334 WM8994_AIF1ADC1R_DRC_ENA
;
336 for (i
= 0; i
< WM8994_DRC_REGS
; i
++)
337 snd_soc_update_bits(codec
, base
+ i
, 0xffff,
338 pdata
->drc_cfgs
[cfg
].regs
[i
]);
340 snd_soc_update_bits(codec
, base
, WM8994_AIF1DAC1_DRC_ENA
|
341 WM8994_AIF1ADC1L_DRC_ENA
|
342 WM8994_AIF1ADC1R_DRC_ENA
, save
);
345 /* Icky as hell but saves code duplication */
346 static int wm8994_get_drc(const char *name
)
348 if (strcmp(name
, "AIF1DRC1 Mode") == 0)
350 if (strcmp(name
, "AIF1DRC2 Mode") == 0)
352 if (strcmp(name
, "AIF2DRC Mode") == 0)
357 static int wm8994_put_drc_enum(struct snd_kcontrol
*kcontrol
,
358 struct snd_ctl_elem_value
*ucontrol
)
360 struct snd_soc_codec
*codec
= snd_soc_kcontrol_codec(kcontrol
);
361 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
362 struct wm8994
*control
= wm8994
->wm8994
;
363 struct wm8994_pdata
*pdata
= &control
->pdata
;
364 int drc
= wm8994_get_drc(kcontrol
->id
.name
);
365 int value
= ucontrol
->value
.integer
.value
[0];
370 if (value
>= pdata
->num_drc_cfgs
)
373 wm8994
->drc_cfg
[drc
] = value
;
375 wm8994_set_drc(codec
, drc
);
380 static int wm8994_get_drc_enum(struct snd_kcontrol
*kcontrol
,
381 struct snd_ctl_elem_value
*ucontrol
)
383 struct snd_soc_codec
*codec
= snd_soc_kcontrol_codec(kcontrol
);
384 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
385 int drc
= wm8994_get_drc(kcontrol
->id
.name
);
389 ucontrol
->value
.enumerated
.item
[0] = wm8994
->drc_cfg
[drc
];
394 static void wm8994_set_retune_mobile(struct snd_soc_codec
*codec
, int block
)
396 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
397 struct wm8994
*control
= wm8994
->wm8994
;
398 struct wm8994_pdata
*pdata
= &control
->pdata
;
399 int base
= wm8994_retune_mobile_base
[block
];
400 int iface
, best
, best_val
, save
, i
, cfg
;
402 if (!pdata
|| !wm8994
->num_retune_mobile_texts
)
417 /* Find the version of the currently selected configuration
418 * with the nearest sample rate. */
419 cfg
= wm8994
->retune_mobile_cfg
[block
];
422 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
423 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
424 wm8994
->retune_mobile_texts
[cfg
]) == 0 &&
425 abs(pdata
->retune_mobile_cfgs
[i
].rate
426 - wm8994
->dac_rates
[iface
]) < best_val
) {
428 best_val
= abs(pdata
->retune_mobile_cfgs
[i
].rate
429 - wm8994
->dac_rates
[iface
]);
433 dev_dbg(codec
->dev
, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
435 pdata
->retune_mobile_cfgs
[best
].name
,
436 pdata
->retune_mobile_cfgs
[best
].rate
,
437 wm8994
->dac_rates
[iface
]);
439 /* The EQ will be disabled while reconfiguring it, remember the
440 * current configuration.
442 save
= snd_soc_read(codec
, base
);
443 save
&= WM8994_AIF1DAC1_EQ_ENA
;
445 for (i
= 0; i
< WM8994_EQ_REGS
; i
++)
446 snd_soc_update_bits(codec
, base
+ i
, 0xffff,
447 pdata
->retune_mobile_cfgs
[best
].regs
[i
]);
449 snd_soc_update_bits(codec
, base
, WM8994_AIF1DAC1_EQ_ENA
, save
);
452 /* Icky as hell but saves code duplication */
453 static int wm8994_get_retune_mobile_block(const char *name
)
455 if (strcmp(name
, "AIF1.1 EQ Mode") == 0)
457 if (strcmp(name
, "AIF1.2 EQ Mode") == 0)
459 if (strcmp(name
, "AIF2 EQ Mode") == 0)
464 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
465 struct snd_ctl_elem_value
*ucontrol
)
467 struct snd_soc_codec
*codec
= snd_soc_kcontrol_codec(kcontrol
);
468 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
469 struct wm8994
*control
= wm8994
->wm8994
;
470 struct wm8994_pdata
*pdata
= &control
->pdata
;
471 int block
= wm8994_get_retune_mobile_block(kcontrol
->id
.name
);
472 int value
= ucontrol
->value
.integer
.value
[0];
477 if (value
>= pdata
->num_retune_mobile_cfgs
)
480 wm8994
->retune_mobile_cfg
[block
] = value
;
482 wm8994_set_retune_mobile(codec
, block
);
487 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
488 struct snd_ctl_elem_value
*ucontrol
)
490 struct snd_soc_codec
*codec
= snd_soc_kcontrol_codec(kcontrol
);
491 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
492 int block
= wm8994_get_retune_mobile_block(kcontrol
->id
.name
);
497 ucontrol
->value
.enumerated
.item
[0] = wm8994
->retune_mobile_cfg
[block
];
502 static const char *aif_chan_src_text
[] = {
506 static SOC_ENUM_SINGLE_DECL(aif1adcl_src
,
507 WM8994_AIF1_CONTROL_1
, 15, aif_chan_src_text
);
509 static SOC_ENUM_SINGLE_DECL(aif1adcr_src
,
510 WM8994_AIF1_CONTROL_1
, 14, aif_chan_src_text
);
512 static SOC_ENUM_SINGLE_DECL(aif2adcl_src
,
513 WM8994_AIF2_CONTROL_1
, 15, aif_chan_src_text
);
515 static SOC_ENUM_SINGLE_DECL(aif2adcr_src
,
516 WM8994_AIF2_CONTROL_1
, 14, aif_chan_src_text
);
518 static SOC_ENUM_SINGLE_DECL(aif1dacl_src
,
519 WM8994_AIF1_CONTROL_2
, 15, aif_chan_src_text
);
521 static SOC_ENUM_SINGLE_DECL(aif1dacr_src
,
522 WM8994_AIF1_CONTROL_2
, 14, aif_chan_src_text
);
524 static SOC_ENUM_SINGLE_DECL(aif2dacl_src
,
525 WM8994_AIF2_CONTROL_2
, 15, aif_chan_src_text
);
527 static SOC_ENUM_SINGLE_DECL(aif2dacr_src
,
528 WM8994_AIF2_CONTROL_2
, 14, aif_chan_src_text
);
530 static const char *osr_text
[] = {
531 "Low Power", "High Performance",
534 static SOC_ENUM_SINGLE_DECL(dac_osr
,
535 WM8994_OVERSAMPLING
, 0, osr_text
);
537 static SOC_ENUM_SINGLE_DECL(adc_osr
,
538 WM8994_OVERSAMPLING
, 1, osr_text
);
540 static const struct snd_kcontrol_new wm8994_snd_controls
[] = {
541 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME
,
542 WM8994_AIF1_ADC1_RIGHT_VOLUME
,
543 1, 119, 0, digital_tlv
),
544 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME
,
545 WM8994_AIF1_ADC2_RIGHT_VOLUME
,
546 1, 119, 0, digital_tlv
),
547 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME
,
548 WM8994_AIF2_ADC_RIGHT_VOLUME
,
549 1, 119, 0, digital_tlv
),
551 SOC_ENUM("AIF1ADCL Source", aif1adcl_src
),
552 SOC_ENUM("AIF1ADCR Source", aif1adcr_src
),
553 SOC_ENUM("AIF2ADCL Source", aif2adcl_src
),
554 SOC_ENUM("AIF2ADCR Source", aif2adcr_src
),
556 SOC_ENUM("AIF1DACL Source", aif1dacl_src
),
557 SOC_ENUM("AIF1DACR Source", aif1dacr_src
),
558 SOC_ENUM("AIF2DACL Source", aif2dacl_src
),
559 SOC_ENUM("AIF2DACR Source", aif2dacr_src
),
561 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME
,
562 WM8994_AIF1_DAC1_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
563 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME
,
564 WM8994_AIF1_DAC2_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
565 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME
,
566 WM8994_AIF2_DAC_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
568 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2
, 10, 3, 0, aif_tlv
),
569 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2
, 10, 3, 0, aif_tlv
),
571 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1
, 0, 1, 0),
572 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1
, 0, 1, 0),
573 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1
, 0, 1, 0),
575 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1
, 2),
576 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1
, 1),
577 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1
, 0),
579 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1
, 2),
580 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1
, 1),
581 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1
, 0),
583 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1
, 2),
584 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1
, 1),
585 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1
, 0),
587 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES
,
589 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES
,
591 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES
,
593 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES
,
595 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf
),
596 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE
, 6, 1, 0),
598 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf
),
599 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS
, 12, 11, 1, 0),
601 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf
),
602 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS
, 12, 11, 1, 0),
604 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf
),
605 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS
, 12, 11, 1, 0),
607 SOC_ENUM("ADC OSR", adc_osr
),
608 SOC_ENUM("DAC OSR", dac_osr
),
610 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME
,
611 WM8994_DAC1_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
612 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME
,
613 WM8994_DAC1_RIGHT_VOLUME
, 9, 1, 1),
615 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME
,
616 WM8994_DAC2_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
617 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME
,
618 WM8994_DAC2_RIGHT_VOLUME
, 9, 1, 1),
620 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION
,
621 6, 1, 1, wm_hubs_spkmix_tlv
),
622 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION
,
623 2, 1, 1, wm_hubs_spkmix_tlv
),
625 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION
,
626 6, 1, 1, wm_hubs_spkmix_tlv
),
627 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION
,
628 2, 1, 1, wm_hubs_spkmix_tlv
),
630 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2
,
631 10, 15, 0, wm8994_3d_tlv
),
632 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2
,
634 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2
,
635 10, 15, 0, wm8994_3d_tlv
),
636 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2
,
638 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2
,
639 10, 15, 0, wm8994_3d_tlv
),
640 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2
,
644 static const struct snd_kcontrol_new wm8994_eq_controls
[] = {
645 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 11, 31, 0,
647 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 6, 31, 0,
649 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 1, 31, 0,
651 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2
, 11, 31, 0,
653 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2
, 6, 31, 0,
656 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 11, 31, 0,
658 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 6, 31, 0,
660 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 1, 31, 0,
662 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2
, 11, 31, 0,
664 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2
, 6, 31, 0,
667 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1
, 11, 31, 0,
669 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1
, 6, 31, 0,
671 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1
, 1, 31, 0,
673 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2
, 11, 31, 0,
675 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2
, 6, 31, 0,
679 static const struct snd_kcontrol_new wm8994_drc_controls
[] = {
680 SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1
, 5,
681 WM8994_AIF1DAC1_DRC_ENA
| WM8994_AIF1ADC1L_DRC_ENA
|
682 WM8994_AIF1ADC1R_DRC_ENA
),
683 SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1
, 5,
684 WM8994_AIF1DAC2_DRC_ENA
| WM8994_AIF1ADC2L_DRC_ENA
|
685 WM8994_AIF1ADC2R_DRC_ENA
),
686 SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1
, 5,
687 WM8994_AIF2DAC_DRC_ENA
| WM8994_AIF2ADCL_DRC_ENA
|
688 WM8994_AIF2ADCR_DRC_ENA
),
691 static const char *wm8958_ng_text
[] = {
692 "30ms", "125ms", "250ms", "500ms",
695 static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac1_ng_hold
,
696 WM8958_AIF1_DAC1_NOISE_GATE
,
697 WM8958_AIF1DAC1_NG_THR_SHIFT
,
700 static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac2_ng_hold
,
701 WM8958_AIF1_DAC2_NOISE_GATE
,
702 WM8958_AIF1DAC2_NG_THR_SHIFT
,
705 static SOC_ENUM_SINGLE_DECL(wm8958_aif2dac_ng_hold
,
706 WM8958_AIF2_DAC_NOISE_GATE
,
707 WM8958_AIF2DAC_NG_THR_SHIFT
,
710 static const struct snd_kcontrol_new wm8958_snd_controls
[] = {
711 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2
, 10, 3, 0, aif_tlv
),
713 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE
,
714 WM8958_AIF1DAC1_NG_ENA_SHIFT
, 1, 0),
715 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold
),
716 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
717 WM8958_AIF1_DAC1_NOISE_GATE
, WM8958_AIF1DAC1_NG_THR_SHIFT
,
720 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE
,
721 WM8958_AIF1DAC2_NG_ENA_SHIFT
, 1, 0),
722 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold
),
723 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
724 WM8958_AIF1_DAC2_NOISE_GATE
, WM8958_AIF1DAC2_NG_THR_SHIFT
,
727 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE
,
728 WM8958_AIF2DAC_NG_ENA_SHIFT
, 1, 0),
729 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold
),
730 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
731 WM8958_AIF2_DAC_NOISE_GATE
, WM8958_AIF2DAC_NG_THR_SHIFT
,
735 static const struct snd_kcontrol_new wm1811_snd_controls
[] = {
736 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1
, 7, 1, 0,
738 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1
, 8, 1, 0,
742 /* We run all mode setting through a function to enforce audio mode */
743 static void wm1811_jackdet_set_mode(struct snd_soc_codec
*codec
, u16 mode
)
745 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
747 if (!wm8994
->jackdet
|| !wm8994
->micdet
[0].jack
)
750 if (wm8994
->active_refcount
)
751 mode
= WM1811_JACKDET_MODE_AUDIO
;
753 if (mode
== wm8994
->jackdet_mode
)
756 wm8994
->jackdet_mode
= mode
;
758 /* Always use audio mode to detect while the system is active */
759 if (mode
!= WM1811_JACKDET_MODE_NONE
)
760 mode
= WM1811_JACKDET_MODE_AUDIO
;
762 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
763 WM1811_JACKDET_MODE_MASK
, mode
);
766 static void active_reference(struct snd_soc_codec
*codec
)
768 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
770 mutex_lock(&wm8994
->accdet_lock
);
772 wm8994
->active_refcount
++;
774 dev_dbg(codec
->dev
, "Active refcount incremented, now %d\n",
775 wm8994
->active_refcount
);
777 /* If we're using jack detection go into audio mode */
778 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_AUDIO
);
780 mutex_unlock(&wm8994
->accdet_lock
);
783 static void active_dereference(struct snd_soc_codec
*codec
)
785 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
788 mutex_lock(&wm8994
->accdet_lock
);
790 wm8994
->active_refcount
--;
792 dev_dbg(codec
->dev
, "Active refcount decremented, now %d\n",
793 wm8994
->active_refcount
);
795 if (wm8994
->active_refcount
== 0) {
796 /* Go into appropriate detection only mode */
797 if (wm8994
->jack_mic
|| wm8994
->mic_detecting
)
798 mode
= WM1811_JACKDET_MODE_MIC
;
800 mode
= WM1811_JACKDET_MODE_JACK
;
802 wm1811_jackdet_set_mode(codec
, mode
);
805 mutex_unlock(&wm8994
->accdet_lock
);
808 static int clk_sys_event(struct snd_soc_dapm_widget
*w
,
809 struct snd_kcontrol
*kcontrol
, int event
)
811 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
812 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
815 case SND_SOC_DAPM_PRE_PMU
:
816 return configure_clock(codec
);
818 case SND_SOC_DAPM_POST_PMU
:
820 * JACKDET won't run until we start the clock and it
821 * only reports deltas, make sure we notify the state
822 * up the stack on startup. Use a *very* generous
823 * timeout for paranoia, there's no urgency and we
824 * don't want false reports.
826 if (wm8994
->jackdet
&& !wm8994
->clk_has_run
) {
827 queue_delayed_work(system_power_efficient_wq
,
828 &wm8994
->jackdet_bootstrap
,
829 msecs_to_jiffies(1000));
830 wm8994
->clk_has_run
= true;
834 case SND_SOC_DAPM_POST_PMD
:
835 configure_clock(codec
);
842 static void vmid_reference(struct snd_soc_codec
*codec
)
844 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
846 pm_runtime_get_sync(codec
->dev
);
848 wm8994
->vmid_refcount
++;
850 dev_dbg(codec
->dev
, "Referencing VMID, refcount is now %d\n",
851 wm8994
->vmid_refcount
);
853 if (wm8994
->vmid_refcount
== 1) {
854 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
855 WM8994_LINEOUT1_DISCH
|
856 WM8994_LINEOUT2_DISCH
, 0);
858 wm_hubs_vmid_ena(codec
);
860 switch (wm8994
->vmid_mode
) {
862 WARN_ON(NULL
== "Invalid VMID mode");
863 case WM8994_VMID_NORMAL
:
864 /* Startup bias, VMID ramp & buffer */
865 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
868 WM8994_STARTUP_BIAS_ENA
|
869 WM8994_VMID_BUF_ENA
|
870 WM8994_VMID_RAMP_MASK
,
872 WM8994_STARTUP_BIAS_ENA
|
873 WM8994_VMID_BUF_ENA
|
874 (0x2 << WM8994_VMID_RAMP_SHIFT
));
876 /* Main bias enable, VMID=2x40k */
877 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
879 WM8994_VMID_SEL_MASK
,
880 WM8994_BIAS_ENA
| 0x2);
884 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
885 WM8994_VMID_RAMP_MASK
|
890 case WM8994_VMID_FORCE
:
891 /* Startup bias, slow VMID ramp & buffer */
892 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
895 WM8994_STARTUP_BIAS_ENA
|
896 WM8994_VMID_BUF_ENA
|
897 WM8994_VMID_RAMP_MASK
,
899 WM8994_STARTUP_BIAS_ENA
|
900 WM8994_VMID_BUF_ENA
|
901 (0x2 << WM8994_VMID_RAMP_SHIFT
));
903 /* Main bias enable, VMID=2x40k */
904 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
906 WM8994_VMID_SEL_MASK
,
907 WM8994_BIAS_ENA
| 0x2);
911 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
912 WM8994_VMID_RAMP_MASK
|
920 static void vmid_dereference(struct snd_soc_codec
*codec
)
922 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
924 wm8994
->vmid_refcount
--;
926 dev_dbg(codec
->dev
, "Dereferencing VMID, refcount is now %d\n",
927 wm8994
->vmid_refcount
);
929 if (wm8994
->vmid_refcount
== 0) {
930 if (wm8994
->hubs
.lineout1_se
)
931 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_3
,
932 WM8994_LINEOUT1N_ENA
|
933 WM8994_LINEOUT1P_ENA
,
934 WM8994_LINEOUT1N_ENA
|
935 WM8994_LINEOUT1P_ENA
);
937 if (wm8994
->hubs
.lineout2_se
)
938 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_3
,
939 WM8994_LINEOUT2N_ENA
|
940 WM8994_LINEOUT2P_ENA
,
941 WM8994_LINEOUT2N_ENA
|
942 WM8994_LINEOUT2P_ENA
);
944 /* Start discharging VMID */
945 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
951 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
952 WM8994_VMID_SEL_MASK
, 0);
956 /* Active discharge */
957 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
958 WM8994_LINEOUT1_DISCH
|
959 WM8994_LINEOUT2_DISCH
,
960 WM8994_LINEOUT1_DISCH
|
961 WM8994_LINEOUT2_DISCH
);
963 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_3
,
964 WM8994_LINEOUT1N_ENA
|
965 WM8994_LINEOUT1P_ENA
|
966 WM8994_LINEOUT2N_ENA
|
967 WM8994_LINEOUT2P_ENA
, 0);
969 /* Switch off startup biases */
970 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
972 WM8994_STARTUP_BIAS_ENA
|
973 WM8994_VMID_BUF_ENA
|
974 WM8994_VMID_RAMP_MASK
, 0);
976 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
977 WM8994_VMID_SEL_MASK
, 0);
980 pm_runtime_put(codec
->dev
);
983 static int vmid_event(struct snd_soc_dapm_widget
*w
,
984 struct snd_kcontrol
*kcontrol
, int event
)
986 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
989 case SND_SOC_DAPM_PRE_PMU
:
990 vmid_reference(codec
);
993 case SND_SOC_DAPM_POST_PMD
:
994 vmid_dereference(codec
);
1001 static bool wm8994_check_class_w_digital(struct snd_soc_codec
*codec
)
1003 int source
= 0; /* GCC flow analysis can't track enable */
1006 /* We also need the same AIF source for L/R and only one path */
1007 reg
= snd_soc_read(codec
, WM8994_DAC1_LEFT_MIXER_ROUTING
);
1009 case WM8994_AIF2DACL_TO_DAC1L
:
1010 dev_vdbg(codec
->dev
, "Class W source AIF2DAC\n");
1011 source
= 2 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
1013 case WM8994_AIF1DAC2L_TO_DAC1L
:
1014 dev_vdbg(codec
->dev
, "Class W source AIF1DAC2\n");
1015 source
= 1 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
1017 case WM8994_AIF1DAC1L_TO_DAC1L
:
1018 dev_vdbg(codec
->dev
, "Class W source AIF1DAC1\n");
1019 source
= 0 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
1022 dev_vdbg(codec
->dev
, "DAC mixer setting: %x\n", reg
);
1026 reg_r
= snd_soc_read(codec
, WM8994_DAC1_RIGHT_MIXER_ROUTING
);
1028 dev_vdbg(codec
->dev
, "Left and right DAC mixers different\n");
1032 /* Set the source up */
1033 snd_soc_update_bits(codec
, WM8994_CLASS_W_1
,
1034 WM8994_CP_DYN_SRC_SEL_MASK
, source
);
1039 static int aif1clk_ev(struct snd_soc_dapm_widget
*w
,
1040 struct snd_kcontrol
*kcontrol
, int event
)
1042 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
1043 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1044 struct wm8994
*control
= wm8994
->wm8994
;
1045 int mask
= WM8994_AIF1DAC1L_ENA
| WM8994_AIF1DAC1R_ENA
;
1051 switch (control
->type
) {
1054 mask
|= WM8994_AIF1DAC2L_ENA
| WM8994_AIF1DAC2R_ENA
;
1061 case SND_SOC_DAPM_PRE_PMU
:
1062 /* Don't enable timeslot 2 if not in use */
1063 if (wm8994
->channels
[0] <= 2)
1064 mask
&= ~(WM8994_AIF1DAC2L_ENA
| WM8994_AIF1DAC2R_ENA
);
1066 val
= snd_soc_read(codec
, WM8994_AIF1_CONTROL_1
);
1067 if ((val
& WM8994_AIF1ADCL_SRC
) &&
1068 (val
& WM8994_AIF1ADCR_SRC
))
1069 adc
= WM8994_AIF1ADC1R_ENA
| WM8994_AIF1ADC2R_ENA
;
1070 else if (!(val
& WM8994_AIF1ADCL_SRC
) &&
1071 !(val
& WM8994_AIF1ADCR_SRC
))
1072 adc
= WM8994_AIF1ADC1L_ENA
| WM8994_AIF1ADC2L_ENA
;
1074 adc
= WM8994_AIF1ADC1R_ENA
| WM8994_AIF1ADC2R_ENA
|
1075 WM8994_AIF1ADC1L_ENA
| WM8994_AIF1ADC2L_ENA
;
1077 val
= snd_soc_read(codec
, WM8994_AIF1_CONTROL_2
);
1078 if ((val
& WM8994_AIF1DACL_SRC
) &&
1079 (val
& WM8994_AIF1DACR_SRC
))
1080 dac
= WM8994_AIF1DAC1R_ENA
| WM8994_AIF1DAC2R_ENA
;
1081 else if (!(val
& WM8994_AIF1DACL_SRC
) &&
1082 !(val
& WM8994_AIF1DACR_SRC
))
1083 dac
= WM8994_AIF1DAC1L_ENA
| WM8994_AIF1DAC2L_ENA
;
1085 dac
= WM8994_AIF1DAC1R_ENA
| WM8994_AIF1DAC2R_ENA
|
1086 WM8994_AIF1DAC1L_ENA
| WM8994_AIF1DAC2L_ENA
;
1088 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
,
1090 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1092 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
1093 WM8994_AIF1DSPCLK_ENA
|
1094 WM8994_SYSDSPCLK_ENA
,
1095 WM8994_AIF1DSPCLK_ENA
|
1096 WM8994_SYSDSPCLK_ENA
);
1097 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
, mask
,
1098 WM8994_AIF1ADC1R_ENA
|
1099 WM8994_AIF1ADC1L_ENA
|
1100 WM8994_AIF1ADC2R_ENA
|
1101 WM8994_AIF1ADC2L_ENA
);
1102 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
, mask
,
1103 WM8994_AIF1DAC1R_ENA
|
1104 WM8994_AIF1DAC1L_ENA
|
1105 WM8994_AIF1DAC2R_ENA
|
1106 WM8994_AIF1DAC2L_ENA
);
1109 case SND_SOC_DAPM_POST_PMU
:
1110 for (i
= 0; i
< ARRAY_SIZE(wm8994_vu_bits
); i
++)
1111 snd_soc_write(codec
, wm8994_vu_bits
[i
].reg
,
1113 wm8994_vu_bits
[i
].reg
));
1116 case SND_SOC_DAPM_PRE_PMD
:
1117 case SND_SOC_DAPM_POST_PMD
:
1118 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1120 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
,
1123 val
= snd_soc_read(codec
, WM8994_CLOCKING_1
);
1124 if (val
& WM8994_AIF2DSPCLK_ENA
)
1125 val
= WM8994_SYSDSPCLK_ENA
;
1128 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
1129 WM8994_SYSDSPCLK_ENA
|
1130 WM8994_AIF1DSPCLK_ENA
, val
);
1137 static int aif2clk_ev(struct snd_soc_dapm_widget
*w
,
1138 struct snd_kcontrol
*kcontrol
, int event
)
1140 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
1147 case SND_SOC_DAPM_PRE_PMU
:
1148 val
= snd_soc_read(codec
, WM8994_AIF2_CONTROL_1
);
1149 if ((val
& WM8994_AIF2ADCL_SRC
) &&
1150 (val
& WM8994_AIF2ADCR_SRC
))
1151 adc
= WM8994_AIF2ADCR_ENA
;
1152 else if (!(val
& WM8994_AIF2ADCL_SRC
) &&
1153 !(val
& WM8994_AIF2ADCR_SRC
))
1154 adc
= WM8994_AIF2ADCL_ENA
;
1156 adc
= WM8994_AIF2ADCL_ENA
| WM8994_AIF2ADCR_ENA
;
1159 val
= snd_soc_read(codec
, WM8994_AIF2_CONTROL_2
);
1160 if ((val
& WM8994_AIF2DACL_SRC
) &&
1161 (val
& WM8994_AIF2DACR_SRC
))
1162 dac
= WM8994_AIF2DACR_ENA
;
1163 else if (!(val
& WM8994_AIF2DACL_SRC
) &&
1164 !(val
& WM8994_AIF2DACR_SRC
))
1165 dac
= WM8994_AIF2DACL_ENA
;
1167 dac
= WM8994_AIF2DACL_ENA
| WM8994_AIF2DACR_ENA
;
1169 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
,
1170 WM8994_AIF2ADCL_ENA
|
1171 WM8994_AIF2ADCR_ENA
, adc
);
1172 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1173 WM8994_AIF2DACL_ENA
|
1174 WM8994_AIF2DACR_ENA
, dac
);
1175 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
1176 WM8994_AIF2DSPCLK_ENA
|
1177 WM8994_SYSDSPCLK_ENA
,
1178 WM8994_AIF2DSPCLK_ENA
|
1179 WM8994_SYSDSPCLK_ENA
);
1180 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
,
1181 WM8994_AIF2ADCL_ENA
|
1182 WM8994_AIF2ADCR_ENA
,
1183 WM8994_AIF2ADCL_ENA
|
1184 WM8994_AIF2ADCR_ENA
);
1185 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1186 WM8994_AIF2DACL_ENA
|
1187 WM8994_AIF2DACR_ENA
,
1188 WM8994_AIF2DACL_ENA
|
1189 WM8994_AIF2DACR_ENA
);
1192 case SND_SOC_DAPM_POST_PMU
:
1193 for (i
= 0; i
< ARRAY_SIZE(wm8994_vu_bits
); i
++)
1194 snd_soc_write(codec
, wm8994_vu_bits
[i
].reg
,
1196 wm8994_vu_bits
[i
].reg
));
1199 case SND_SOC_DAPM_PRE_PMD
:
1200 case SND_SOC_DAPM_POST_PMD
:
1201 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1202 WM8994_AIF2DACL_ENA
|
1203 WM8994_AIF2DACR_ENA
, 0);
1204 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
,
1205 WM8994_AIF2ADCL_ENA
|
1206 WM8994_AIF2ADCR_ENA
, 0);
1208 val
= snd_soc_read(codec
, WM8994_CLOCKING_1
);
1209 if (val
& WM8994_AIF1DSPCLK_ENA
)
1210 val
= WM8994_SYSDSPCLK_ENA
;
1213 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
1214 WM8994_SYSDSPCLK_ENA
|
1215 WM8994_AIF2DSPCLK_ENA
, val
);
1222 static int aif1clk_late_ev(struct snd_soc_dapm_widget
*w
,
1223 struct snd_kcontrol
*kcontrol
, int event
)
1225 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
1226 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1229 case SND_SOC_DAPM_PRE_PMU
:
1230 wm8994
->aif1clk_enable
= 1;
1232 case SND_SOC_DAPM_POST_PMD
:
1233 wm8994
->aif1clk_disable
= 1;
1240 static int aif2clk_late_ev(struct snd_soc_dapm_widget
*w
,
1241 struct snd_kcontrol
*kcontrol
, int event
)
1243 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
1244 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1247 case SND_SOC_DAPM_PRE_PMU
:
1248 wm8994
->aif2clk_enable
= 1;
1250 case SND_SOC_DAPM_POST_PMD
:
1251 wm8994
->aif2clk_disable
= 1;
1258 static int late_enable_ev(struct snd_soc_dapm_widget
*w
,
1259 struct snd_kcontrol
*kcontrol
, int event
)
1261 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
1262 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1265 case SND_SOC_DAPM_PRE_PMU
:
1266 if (wm8994
->aif1clk_enable
) {
1267 aif1clk_ev(w
, kcontrol
, SND_SOC_DAPM_PRE_PMU
);
1268 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
1269 WM8994_AIF1CLK_ENA_MASK
,
1270 WM8994_AIF1CLK_ENA
);
1271 aif1clk_ev(w
, kcontrol
, SND_SOC_DAPM_POST_PMU
);
1272 wm8994
->aif1clk_enable
= 0;
1274 if (wm8994
->aif2clk_enable
) {
1275 aif2clk_ev(w
, kcontrol
, SND_SOC_DAPM_PRE_PMU
);
1276 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
1277 WM8994_AIF2CLK_ENA_MASK
,
1278 WM8994_AIF2CLK_ENA
);
1279 aif2clk_ev(w
, kcontrol
, SND_SOC_DAPM_POST_PMU
);
1280 wm8994
->aif2clk_enable
= 0;
1285 /* We may also have postponed startup of DSP, handle that. */
1286 wm8958_aif_ev(w
, kcontrol
, event
);
1291 static int late_disable_ev(struct snd_soc_dapm_widget
*w
,
1292 struct snd_kcontrol
*kcontrol
, int event
)
1294 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
1295 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1298 case SND_SOC_DAPM_POST_PMD
:
1299 if (wm8994
->aif1clk_disable
) {
1300 aif1clk_ev(w
, kcontrol
, SND_SOC_DAPM_PRE_PMD
);
1301 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
1302 WM8994_AIF1CLK_ENA_MASK
, 0);
1303 aif1clk_ev(w
, kcontrol
, SND_SOC_DAPM_POST_PMD
);
1304 wm8994
->aif1clk_disable
= 0;
1306 if (wm8994
->aif2clk_disable
) {
1307 aif2clk_ev(w
, kcontrol
, SND_SOC_DAPM_PRE_PMD
);
1308 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
1309 WM8994_AIF2CLK_ENA_MASK
, 0);
1310 aif2clk_ev(w
, kcontrol
, SND_SOC_DAPM_POST_PMD
);
1311 wm8994
->aif2clk_disable
= 0;
1319 static int adc_mux_ev(struct snd_soc_dapm_widget
*w
,
1320 struct snd_kcontrol
*kcontrol
, int event
)
1322 late_enable_ev(w
, kcontrol
, event
);
1326 static int micbias_ev(struct snd_soc_dapm_widget
*w
,
1327 struct snd_kcontrol
*kcontrol
, int event
)
1329 late_enable_ev(w
, kcontrol
, event
);
1333 static int dac_ev(struct snd_soc_dapm_widget
*w
,
1334 struct snd_kcontrol
*kcontrol
, int event
)
1336 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
1337 unsigned int mask
= 1 << w
->shift
;
1339 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1344 static const char *adc_mux_text
[] = {
1349 static SOC_ENUM_SINGLE_VIRT_DECL(adc_enum
, adc_mux_text
);
1351 static const struct snd_kcontrol_new adcl_mux
=
1352 SOC_DAPM_ENUM("ADCL Mux", adc_enum
);
1354 static const struct snd_kcontrol_new adcr_mux
=
1355 SOC_DAPM_ENUM("ADCR Mux", adc_enum
);
1357 static const struct snd_kcontrol_new left_speaker_mixer
[] = {
1358 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER
, 9, 1, 0),
1359 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER
, 7, 1, 0),
1360 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER
, 5, 1, 0),
1361 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER
, 3, 1, 0),
1362 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER
, 1, 1, 0),
1365 static const struct snd_kcontrol_new right_speaker_mixer
[] = {
1366 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER
, 8, 1, 0),
1367 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER
, 6, 1, 0),
1368 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER
, 4, 1, 0),
1369 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER
, 2, 1, 0),
1370 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER
, 0, 1, 0),
1373 /* Debugging; dump chip status after DAPM transitions */
1374 static int post_ev(struct snd_soc_dapm_widget
*w
,
1375 struct snd_kcontrol
*kcontrol
, int event
)
1377 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
1378 dev_dbg(codec
->dev
, "SRC status: %x\n",
1380 WM8994_RATE_STATUS
));
1384 static const struct snd_kcontrol_new aif1adc1l_mix
[] = {
1385 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING
,
1387 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING
,
1391 static const struct snd_kcontrol_new aif1adc1r_mix
[] = {
1392 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING
,
1394 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING
,
1398 static const struct snd_kcontrol_new aif1adc2l_mix
[] = {
1399 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING
,
1401 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING
,
1405 static const struct snd_kcontrol_new aif1adc2r_mix
[] = {
1406 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING
,
1408 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING
,
1412 static const struct snd_kcontrol_new aif2dac2l_mix
[] = {
1413 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1415 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1417 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1419 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1421 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1425 static const struct snd_kcontrol_new aif2dac2r_mix
[] = {
1426 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1428 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1430 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1432 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1434 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1438 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1439 SOC_SINGLE_EXT(xname, reg, shift, max, invert, \
1440 snd_soc_dapm_get_volsw, wm8994_put_class_w)
1442 static int wm8994_put_class_w(struct snd_kcontrol
*kcontrol
,
1443 struct snd_ctl_elem_value
*ucontrol
)
1445 struct snd_soc_codec
*codec
= snd_soc_dapm_kcontrol_codec(kcontrol
);
1448 ret
= snd_soc_dapm_put_volsw(kcontrol
, ucontrol
);
1450 wm_hubs_update_class_w(codec
);
1455 static const struct snd_kcontrol_new dac1l_mix
[] = {
1456 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1458 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1460 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1462 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1464 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1468 static const struct snd_kcontrol_new dac1r_mix
[] = {
1469 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1471 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1473 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1475 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1477 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1481 static const char *sidetone_text
[] = {
1482 "ADC/DMIC1", "DMIC2",
1485 static SOC_ENUM_SINGLE_DECL(sidetone1_enum
,
1486 WM8994_SIDETONE
, 0, sidetone_text
);
1488 static const struct snd_kcontrol_new sidetone1_mux
=
1489 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum
);
1491 static SOC_ENUM_SINGLE_DECL(sidetone2_enum
,
1492 WM8994_SIDETONE
, 1, sidetone_text
);
1494 static const struct snd_kcontrol_new sidetone2_mux
=
1495 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum
);
1497 static const char *aif1dac_text
[] = {
1498 "AIF1DACDAT", "AIF3DACDAT",
1501 static const char *loopback_text
[] = {
1505 static SOC_ENUM_SINGLE_DECL(aif1_loopback_enum
,
1506 WM8994_AIF1_CONTROL_2
,
1507 WM8994_AIF1_LOOPBACK_SHIFT
,
1510 static const struct snd_kcontrol_new aif1_loopback
=
1511 SOC_DAPM_ENUM("AIF1 Loopback", aif1_loopback_enum
);
1513 static SOC_ENUM_SINGLE_DECL(aif2_loopback_enum
,
1514 WM8994_AIF2_CONTROL_2
,
1515 WM8994_AIF2_LOOPBACK_SHIFT
,
1518 static const struct snd_kcontrol_new aif2_loopback
=
1519 SOC_DAPM_ENUM("AIF2 Loopback", aif2_loopback_enum
);
1521 static SOC_ENUM_SINGLE_DECL(aif1dac_enum
,
1522 WM8994_POWER_MANAGEMENT_6
, 0, aif1dac_text
);
1524 static const struct snd_kcontrol_new aif1dac_mux
=
1525 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum
);
1527 static const char *aif2dac_text
[] = {
1528 "AIF2DACDAT", "AIF3DACDAT",
1531 static SOC_ENUM_SINGLE_DECL(aif2dac_enum
,
1532 WM8994_POWER_MANAGEMENT_6
, 1, aif2dac_text
);
1534 static const struct snd_kcontrol_new aif2dac_mux
=
1535 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum
);
1537 static const char *aif2adc_text
[] = {
1538 "AIF2ADCDAT", "AIF3DACDAT",
1541 static SOC_ENUM_SINGLE_DECL(aif2adc_enum
,
1542 WM8994_POWER_MANAGEMENT_6
, 2, aif2adc_text
);
1544 static const struct snd_kcontrol_new aif2adc_mux
=
1545 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum
);
1547 static const char *aif3adc_text
[] = {
1548 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1551 static SOC_ENUM_SINGLE_DECL(wm8994_aif3adc_enum
,
1552 WM8994_POWER_MANAGEMENT_6
, 3, aif3adc_text
);
1554 static const struct snd_kcontrol_new wm8994_aif3adc_mux
=
1555 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum
);
1557 static SOC_ENUM_SINGLE_DECL(wm8958_aif3adc_enum
,
1558 WM8994_POWER_MANAGEMENT_6
, 3, aif3adc_text
);
1560 static const struct snd_kcontrol_new wm8958_aif3adc_mux
=
1561 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum
);
1563 static const char *mono_pcm_out_text
[] = {
1564 "None", "AIF2ADCL", "AIF2ADCR",
1567 static SOC_ENUM_SINGLE_DECL(mono_pcm_out_enum
,
1568 WM8994_POWER_MANAGEMENT_6
, 9, mono_pcm_out_text
);
1570 static const struct snd_kcontrol_new mono_pcm_out_mux
=
1571 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum
);
1573 static const char *aif2dac_src_text
[] = {
1577 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1578 static SOC_ENUM_SINGLE_DECL(aif2dacl_src_enum
,
1579 WM8994_POWER_MANAGEMENT_6
, 7, aif2dac_src_text
);
1581 static const struct snd_kcontrol_new aif2dacl_src_mux
=
1582 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum
);
1584 static SOC_ENUM_SINGLE_DECL(aif2dacr_src_enum
,
1585 WM8994_POWER_MANAGEMENT_6
, 8, aif2dac_src_text
);
1587 static const struct snd_kcontrol_new aif2dacr_src_mux
=
1588 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum
);
1590 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets
[] = {
1591 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM
, 0, 0, aif1clk_late_ev
,
1592 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1593 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM
, 0, 0, aif2clk_late_ev
,
1594 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1596 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1597 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1598 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1599 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1600 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1601 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1602 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1603 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1604 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1605 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1607 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3
, 8, 0,
1608 left_speaker_mixer
, ARRAY_SIZE(left_speaker_mixer
),
1609 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1610 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3
, 9, 0,
1611 right_speaker_mixer
, ARRAY_SIZE(right_speaker_mixer
),
1612 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1613 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM
, 0, 0, &wm_hubs_hpl_mux
,
1614 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1615 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM
, 0, 0, &wm_hubs_hpr_mux
,
1616 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1618 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev
)
1621 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets
[] = {
1622 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1
, 0, 0, aif1clk_ev
,
1623 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMU
|
1624 SND_SOC_DAPM_PRE_PMD
),
1625 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1
, 0, 0, aif2clk_ev
,
1626 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMU
|
1627 SND_SOC_DAPM_PRE_PMD
),
1628 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM
, 0, 0, NULL
, 0),
1629 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3
, 8, 0,
1630 left_speaker_mixer
, ARRAY_SIZE(left_speaker_mixer
)),
1631 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3
, 9, 0,
1632 right_speaker_mixer
, ARRAY_SIZE(right_speaker_mixer
)),
1633 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM
, 0, 0, &wm_hubs_hpl_mux
),
1634 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM
, 0, 0, &wm_hubs_hpr_mux
),
1637 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets
[] = {
1638 SND_SOC_DAPM_DAC_E("DAC2L", NULL
, SND_SOC_NOPM
, 3, 0,
1639 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1640 SND_SOC_DAPM_DAC_E("DAC2R", NULL
, SND_SOC_NOPM
, 2, 0,
1641 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1642 SND_SOC_DAPM_DAC_E("DAC1L", NULL
, SND_SOC_NOPM
, 1, 0,
1643 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1644 SND_SOC_DAPM_DAC_E("DAC1R", NULL
, SND_SOC_NOPM
, 0, 0,
1645 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1648 static const struct snd_soc_dapm_widget wm8994_dac_widgets
[] = {
1649 SND_SOC_DAPM_DAC("DAC2L", NULL
, WM8994_POWER_MANAGEMENT_5
, 3, 0),
1650 SND_SOC_DAPM_DAC("DAC2R", NULL
, WM8994_POWER_MANAGEMENT_5
, 2, 0),
1651 SND_SOC_DAPM_DAC("DAC1L", NULL
, WM8994_POWER_MANAGEMENT_5
, 1, 0),
1652 SND_SOC_DAPM_DAC("DAC1R", NULL
, WM8994_POWER_MANAGEMENT_5
, 0, 0),
1655 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets
[] = {
1656 SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4
, 1, 0, &adcl_mux
,
1657 adc_mux_ev
, SND_SOC_DAPM_PRE_PMU
),
1658 SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4
, 0, 0, &adcr_mux
,
1659 adc_mux_ev
, SND_SOC_DAPM_PRE_PMU
),
1662 static const struct snd_soc_dapm_widget wm8994_adc_widgets
[] = {
1663 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4
, 1, 0, &adcl_mux
),
1664 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4
, 0, 0, &adcr_mux
),
1667 static const struct snd_soc_dapm_widget wm8994_dapm_widgets
[] = {
1668 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1669 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1670 SND_SOC_DAPM_INPUT("Clock"),
1672 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM
, 0, 0, micbias_ev
,
1673 SND_SOC_DAPM_PRE_PMU
),
1674 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM
, 0, 0, vmid_event
,
1675 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1677 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM
, 0, 0, clk_sys_event
,
1678 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMU
|
1679 SND_SOC_DAPM_PRE_PMD
),
1681 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM
, 3, 0, NULL
, 0),
1682 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM
, 2, 0, NULL
, 0),
1683 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM
, 1, 0, NULL
, 0),
1685 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL
,
1686 0, SND_SOC_NOPM
, 9, 0),
1687 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL
,
1688 0, SND_SOC_NOPM
, 8, 0),
1689 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL
, 0,
1690 SND_SOC_NOPM
, 9, 0, wm8958_aif_ev
,
1691 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1692 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL
, 0,
1693 SND_SOC_NOPM
, 8, 0, wm8958_aif_ev
,
1694 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1696 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL
,
1697 0, SND_SOC_NOPM
, 11, 0),
1698 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL
,
1699 0, SND_SOC_NOPM
, 10, 0),
1700 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL
, 0,
1701 SND_SOC_NOPM
, 11, 0, wm8958_aif_ev
,
1702 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1703 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL
, 0,
1704 SND_SOC_NOPM
, 10, 0, wm8958_aif_ev
,
1705 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1707 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM
, 0, 0,
1708 aif1adc1l_mix
, ARRAY_SIZE(aif1adc1l_mix
)),
1709 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM
, 0, 0,
1710 aif1adc1r_mix
, ARRAY_SIZE(aif1adc1r_mix
)),
1712 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM
, 0, 0,
1713 aif1adc2l_mix
, ARRAY_SIZE(aif1adc2l_mix
)),
1714 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM
, 0, 0,
1715 aif1adc2r_mix
, ARRAY_SIZE(aif1adc2r_mix
)),
1717 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM
, 0, 0,
1718 aif2dac2l_mix
, ARRAY_SIZE(aif2dac2l_mix
)),
1719 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM
, 0, 0,
1720 aif2dac2r_mix
, ARRAY_SIZE(aif2dac2r_mix
)),
1722 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM
, 0, 0, &sidetone1_mux
),
1723 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM
, 0, 0, &sidetone2_mux
),
1725 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM
, 0, 0,
1726 dac1l_mix
, ARRAY_SIZE(dac1l_mix
)),
1727 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM
, 0, 0,
1728 dac1r_mix
, ARRAY_SIZE(dac1r_mix
)),
1730 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL
, 0,
1731 SND_SOC_NOPM
, 13, 0),
1732 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL
, 0,
1733 SND_SOC_NOPM
, 12, 0),
1734 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL
, 0,
1735 SND_SOC_NOPM
, 13, 0, wm8958_aif_ev
,
1736 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1737 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL
, 0,
1738 SND_SOC_NOPM
, 12, 0, wm8958_aif_ev
,
1739 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1741 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1742 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1743 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1744 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1746 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM
, 0, 0, &aif1dac_mux
),
1747 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM
, 0, 0, &aif2dac_mux
),
1748 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM
, 0, 0, &aif2adc_mux
),
1750 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1751 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1753 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1
, 4, 0, NULL
, 0),
1755 SND_SOC_DAPM_ADC("DMIC2L", NULL
, WM8994_POWER_MANAGEMENT_4
, 5, 0),
1756 SND_SOC_DAPM_ADC("DMIC2R", NULL
, WM8994_POWER_MANAGEMENT_4
, 4, 0),
1757 SND_SOC_DAPM_ADC("DMIC1L", NULL
, WM8994_POWER_MANAGEMENT_4
, 3, 0),
1758 SND_SOC_DAPM_ADC("DMIC1R", NULL
, WM8994_POWER_MANAGEMENT_4
, 2, 0),
1760 /* Power is done with the muxes since the ADC power also controls the
1761 * downsampling chain, the chip will automatically manage the analogue
1762 * specific portions.
1764 SND_SOC_DAPM_ADC("ADCL", NULL
, SND_SOC_NOPM
, 1, 0),
1765 SND_SOC_DAPM_ADC("ADCR", NULL
, SND_SOC_NOPM
, 0, 0),
1767 SND_SOC_DAPM_MUX("AIF1 Loopback", SND_SOC_NOPM
, 0, 0, &aif1_loopback
),
1768 SND_SOC_DAPM_MUX("AIF2 Loopback", SND_SOC_NOPM
, 0, 0, &aif2_loopback
),
1770 SND_SOC_DAPM_POST("Debug log", post_ev
),
1773 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets
[] = {
1774 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM
, 0, 0, &wm8994_aif3adc_mux
),
1777 static const struct snd_soc_dapm_widget wm8958_dapm_widgets
[] = {
1778 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6
, 5, 1, NULL
, 0),
1779 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM
, 0, 0, &mono_pcm_out_mux
),
1780 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM
, 0, 0, &aif2dacl_src_mux
),
1781 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM
, 0, 0, &aif2dacr_src_mux
),
1782 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM
, 0, 0, &wm8958_aif3adc_mux
),
1785 static const struct snd_soc_dapm_route intercon
[] = {
1786 { "CLK_SYS", NULL
, "AIF1CLK", check_clk_sys
},
1787 { "CLK_SYS", NULL
, "AIF2CLK", check_clk_sys
},
1789 { "DSP1CLK", NULL
, "CLK_SYS" },
1790 { "DSP2CLK", NULL
, "CLK_SYS" },
1791 { "DSPINTCLK", NULL
, "CLK_SYS" },
1793 { "AIF1ADC1L", NULL
, "AIF1CLK" },
1794 { "AIF1ADC1L", NULL
, "DSP1CLK" },
1795 { "AIF1ADC1R", NULL
, "AIF1CLK" },
1796 { "AIF1ADC1R", NULL
, "DSP1CLK" },
1797 { "AIF1ADC1R", NULL
, "DSPINTCLK" },
1799 { "AIF1DAC1L", NULL
, "AIF1CLK" },
1800 { "AIF1DAC1L", NULL
, "DSP1CLK" },
1801 { "AIF1DAC1R", NULL
, "AIF1CLK" },
1802 { "AIF1DAC1R", NULL
, "DSP1CLK" },
1803 { "AIF1DAC1R", NULL
, "DSPINTCLK" },
1805 { "AIF1ADC2L", NULL
, "AIF1CLK" },
1806 { "AIF1ADC2L", NULL
, "DSP1CLK" },
1807 { "AIF1ADC2R", NULL
, "AIF1CLK" },
1808 { "AIF1ADC2R", NULL
, "DSP1CLK" },
1809 { "AIF1ADC2R", NULL
, "DSPINTCLK" },
1811 { "AIF1DAC2L", NULL
, "AIF1CLK" },
1812 { "AIF1DAC2L", NULL
, "DSP1CLK" },
1813 { "AIF1DAC2R", NULL
, "AIF1CLK" },
1814 { "AIF1DAC2R", NULL
, "DSP1CLK" },
1815 { "AIF1DAC2R", NULL
, "DSPINTCLK" },
1817 { "AIF2ADCL", NULL
, "AIF2CLK" },
1818 { "AIF2ADCL", NULL
, "DSP2CLK" },
1819 { "AIF2ADCR", NULL
, "AIF2CLK" },
1820 { "AIF2ADCR", NULL
, "DSP2CLK" },
1821 { "AIF2ADCR", NULL
, "DSPINTCLK" },
1823 { "AIF2DACL", NULL
, "AIF2CLK" },
1824 { "AIF2DACL", NULL
, "DSP2CLK" },
1825 { "AIF2DACR", NULL
, "AIF2CLK" },
1826 { "AIF2DACR", NULL
, "DSP2CLK" },
1827 { "AIF2DACR", NULL
, "DSPINTCLK" },
1829 { "DMIC1L", NULL
, "DMIC1DAT" },
1830 { "DMIC1L", NULL
, "CLK_SYS" },
1831 { "DMIC1R", NULL
, "DMIC1DAT" },
1832 { "DMIC1R", NULL
, "CLK_SYS" },
1833 { "DMIC2L", NULL
, "DMIC2DAT" },
1834 { "DMIC2L", NULL
, "CLK_SYS" },
1835 { "DMIC2R", NULL
, "DMIC2DAT" },
1836 { "DMIC2R", NULL
, "CLK_SYS" },
1838 { "ADCL", NULL
, "AIF1CLK" },
1839 { "ADCL", NULL
, "DSP1CLK" },
1840 { "ADCL", NULL
, "DSPINTCLK" },
1842 { "ADCR", NULL
, "AIF1CLK" },
1843 { "ADCR", NULL
, "DSP1CLK" },
1844 { "ADCR", NULL
, "DSPINTCLK" },
1846 { "ADCL Mux", "ADC", "ADCL" },
1847 { "ADCL Mux", "DMIC", "DMIC1L" },
1848 { "ADCR Mux", "ADC", "ADCR" },
1849 { "ADCR Mux", "DMIC", "DMIC1R" },
1851 { "DAC1L", NULL
, "AIF1CLK" },
1852 { "DAC1L", NULL
, "DSP1CLK" },
1853 { "DAC1L", NULL
, "DSPINTCLK" },
1855 { "DAC1R", NULL
, "AIF1CLK" },
1856 { "DAC1R", NULL
, "DSP1CLK" },
1857 { "DAC1R", NULL
, "DSPINTCLK" },
1859 { "DAC2L", NULL
, "AIF2CLK" },
1860 { "DAC2L", NULL
, "DSP2CLK" },
1861 { "DAC2L", NULL
, "DSPINTCLK" },
1863 { "DAC2R", NULL
, "AIF2DACR" },
1864 { "DAC2R", NULL
, "AIF2CLK" },
1865 { "DAC2R", NULL
, "DSP2CLK" },
1866 { "DAC2R", NULL
, "DSPINTCLK" },
1868 { "TOCLK", NULL
, "CLK_SYS" },
1870 { "AIF1DACDAT", NULL
, "AIF1 Playback" },
1871 { "AIF2DACDAT", NULL
, "AIF2 Playback" },
1872 { "AIF3DACDAT", NULL
, "AIF3 Playback" },
1874 { "AIF1 Capture", NULL
, "AIF1ADCDAT" },
1875 { "AIF2 Capture", NULL
, "AIF2ADCDAT" },
1876 { "AIF3 Capture", NULL
, "AIF3ADCDAT" },
1879 { "AIF1ADC1L", NULL
, "AIF1ADC1L Mixer" },
1880 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1881 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1883 { "AIF1ADC1R", NULL
, "AIF1ADC1R Mixer" },
1884 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1885 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1887 { "AIF1ADC2L", NULL
, "AIF1ADC2L Mixer" },
1888 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1889 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1891 { "AIF1ADC2R", NULL
, "AIF1ADC2R Mixer" },
1892 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1893 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1895 /* Pin level routing for AIF3 */
1896 { "AIF1DAC1L", NULL
, "AIF1DAC Mux" },
1897 { "AIF1DAC1R", NULL
, "AIF1DAC Mux" },
1898 { "AIF1DAC2L", NULL
, "AIF1DAC Mux" },
1899 { "AIF1DAC2R", NULL
, "AIF1DAC Mux" },
1901 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1 Loopback" },
1902 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1903 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2 Loopback" },
1904 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1905 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1906 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1907 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1910 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1911 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1912 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1913 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1914 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1916 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1917 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1918 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1919 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1920 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1922 /* DAC2/AIF2 outputs */
1923 { "AIF2ADCL", NULL
, "AIF2DAC2L Mixer" },
1924 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1925 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1926 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1927 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1928 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1930 { "AIF2ADCR", NULL
, "AIF2DAC2R Mixer" },
1931 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1932 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1933 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1934 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1935 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1937 { "AIF1ADCDAT", NULL
, "AIF1ADC1L" },
1938 { "AIF1ADCDAT", NULL
, "AIF1ADC1R" },
1939 { "AIF1ADCDAT", NULL
, "AIF1ADC2L" },
1940 { "AIF1ADCDAT", NULL
, "AIF1ADC2R" },
1942 { "AIF2ADCDAT", NULL
, "AIF2ADC Mux" },
1945 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1946 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1947 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1948 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1949 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1950 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1951 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1952 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1955 { "AIF1 Loopback", "ADCDAT", "AIF1ADCDAT" },
1956 { "AIF1 Loopback", "None", "AIF1DACDAT" },
1957 { "AIF2 Loopback", "ADCDAT", "AIF2ADCDAT" },
1958 { "AIF2 Loopback", "None", "AIF2DACDAT" },
1961 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1962 { "Left Sidetone", "DMIC2", "DMIC2L" },
1963 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1964 { "Right Sidetone", "DMIC2", "DMIC2R" },
1967 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1968 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1970 { "SPKL", "DAC1 Switch", "DAC1L" },
1971 { "SPKL", "DAC2 Switch", "DAC2L" },
1973 { "SPKR", "DAC1 Switch", "DAC1R" },
1974 { "SPKR", "DAC2 Switch", "DAC2R" },
1976 { "Left Headphone Mux", "DAC", "DAC1L" },
1977 { "Right Headphone Mux", "DAC", "DAC1R" },
1980 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon
[] = {
1981 { "DAC1L", NULL
, "Late DAC1L Enable PGA" },
1982 { "Late DAC1L Enable PGA", NULL
, "DAC1L Mixer" },
1983 { "DAC1R", NULL
, "Late DAC1R Enable PGA" },
1984 { "Late DAC1R Enable PGA", NULL
, "DAC1R Mixer" },
1985 { "DAC2L", NULL
, "Late DAC2L Enable PGA" },
1986 { "Late DAC2L Enable PGA", NULL
, "AIF2DAC2L Mixer" },
1987 { "DAC2R", NULL
, "Late DAC2R Enable PGA" },
1988 { "Late DAC2R Enable PGA", NULL
, "AIF2DAC2R Mixer" }
1991 static const struct snd_soc_dapm_route wm8994_lateclk_intercon
[] = {
1992 { "DAC1L", NULL
, "DAC1L Mixer" },
1993 { "DAC1R", NULL
, "DAC1R Mixer" },
1994 { "DAC2L", NULL
, "AIF2DAC2L Mixer" },
1995 { "DAC2R", NULL
, "AIF2DAC2R Mixer" },
1998 static const struct snd_soc_dapm_route wm8994_revd_intercon
[] = {
1999 { "AIF1DACDAT", NULL
, "AIF2DACDAT" },
2000 { "AIF2DACDAT", NULL
, "AIF1DACDAT" },
2001 { "AIF1ADCDAT", NULL
, "AIF2ADCDAT" },
2002 { "AIF2ADCDAT", NULL
, "AIF1ADCDAT" },
2003 { "MICBIAS1", NULL
, "CLK_SYS" },
2004 { "MICBIAS1", NULL
, "MICBIAS Supply" },
2005 { "MICBIAS2", NULL
, "CLK_SYS" },
2006 { "MICBIAS2", NULL
, "MICBIAS Supply" },
2009 static const struct snd_soc_dapm_route wm8994_intercon
[] = {
2010 { "AIF2DACL", NULL
, "AIF2DAC Mux" },
2011 { "AIF2DACR", NULL
, "AIF2DAC Mux" },
2012 { "MICBIAS1", NULL
, "VMID" },
2013 { "MICBIAS2", NULL
, "VMID" },
2016 static const struct snd_soc_dapm_route wm8958_intercon
[] = {
2017 { "AIF2DACL", NULL
, "AIF2DACL Mux" },
2018 { "AIF2DACR", NULL
, "AIF2DACR Mux" },
2020 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
2021 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
2022 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
2023 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
2025 { "AIF3DACDAT", NULL
, "AIF3" },
2026 { "AIF3ADCDAT", NULL
, "AIF3" },
2028 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
2029 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
2031 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
2034 /* The size in bits of the FLL divide multiplied by 10
2035 * to allow rounding later */
2036 #define FIXED_FLL_SIZE ((1 << 16) * 10)
2047 static int wm8994_get_fll_config(struct wm8994
*control
, struct fll_div
*fll
,
2048 int freq_in
, int freq_out
)
2051 unsigned int K
, Ndiv
, Nmod
, gcd_fll
;
2053 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in
, freq_out
);
2055 /* Scale the input frequency down to <= 13.5MHz */
2056 fll
->clk_ref_div
= 0;
2057 while (freq_in
> 13500000) {
2061 if (fll
->clk_ref_div
> 3)
2064 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll
->clk_ref_div
, freq_in
);
2066 /* Scale the output to give 90MHz<=Fvco<=100MHz */
2068 while (freq_out
* (fll
->outdiv
+ 1) < 90000000) {
2070 if (fll
->outdiv
> 63)
2073 freq_out
*= fll
->outdiv
+ 1;
2074 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll
->outdiv
, freq_out
);
2076 if (freq_in
> 1000000) {
2077 fll
->fll_fratio
= 0;
2078 } else if (freq_in
> 256000) {
2079 fll
->fll_fratio
= 1;
2081 } else if (freq_in
> 128000) {
2082 fll
->fll_fratio
= 2;
2084 } else if (freq_in
> 64000) {
2085 fll
->fll_fratio
= 3;
2088 fll
->fll_fratio
= 4;
2091 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll
->fll_fratio
, freq_in
);
2093 /* Now, calculate N.K */
2094 Ndiv
= freq_out
/ freq_in
;
2097 Nmod
= freq_out
% freq_in
;
2098 pr_debug("Nmod=%d\n", Nmod
);
2100 switch (control
->type
) {
2102 /* Calculate fractional part - scale up so we can round. */
2103 Kpart
= FIXED_FLL_SIZE
* (long long)Nmod
;
2105 do_div(Kpart
, freq_in
);
2107 K
= Kpart
& 0xFFFFFFFF;
2112 /* Move down to proper range now rounding is done */
2116 pr_debug("N=%x K=%x\n", fll
->n
, fll
->k
);
2120 gcd_fll
= gcd(freq_out
, freq_in
);
2122 fll
->k
= (freq_out
- (freq_in
* fll
->n
)) / gcd_fll
;
2123 fll
->lambda
= freq_in
/ gcd_fll
;
2130 static int _wm8994_set_fll(struct snd_soc_codec
*codec
, int id
, int src
,
2131 unsigned int freq_in
, unsigned int freq_out
)
2133 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2134 struct wm8994
*control
= wm8994
->wm8994
;
2135 int reg_offset
, ret
;
2137 u16 reg
, clk1
, aif_reg
, aif_src
;
2138 unsigned long timeout
;
2156 reg
= snd_soc_read(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
);
2157 was_enabled
= reg
& WM8994_FLL1_ENA
;
2161 /* Allow no source specification when stopping */
2164 src
= wm8994
->fll
[id
].src
;
2166 case WM8994_FLL_SRC_MCLK1
:
2167 case WM8994_FLL_SRC_MCLK2
:
2168 case WM8994_FLL_SRC_LRCLK
:
2169 case WM8994_FLL_SRC_BCLK
:
2171 case WM8994_FLL_SRC_INTERNAL
:
2173 freq_out
= 12000000;
2179 /* Are we changing anything? */
2180 if (wm8994
->fll
[id
].src
== src
&&
2181 wm8994
->fll
[id
].in
== freq_in
&& wm8994
->fll
[id
].out
== freq_out
)
2184 /* If we're stopping the FLL redo the old config - no
2185 * registers will actually be written but we avoid GCC flow
2186 * analysis bugs spewing warnings.
2189 ret
= wm8994_get_fll_config(control
, &fll
, freq_in
, freq_out
);
2191 ret
= wm8994_get_fll_config(control
, &fll
, wm8994
->fll
[id
].in
,
2192 wm8994
->fll
[id
].out
);
2196 /* Make sure that we're not providing SYSCLK right now */
2197 clk1
= snd_soc_read(codec
, WM8994_CLOCKING_1
);
2198 if (clk1
& WM8994_SYSCLK_SRC
)
2199 aif_reg
= WM8994_AIF2_CLOCKING_1
;
2201 aif_reg
= WM8994_AIF1_CLOCKING_1
;
2202 reg
= snd_soc_read(codec
, aif_reg
);
2204 if ((reg
& WM8994_AIF1CLK_ENA
) &&
2205 (reg
& WM8994_AIF1CLK_SRC_MASK
) == aif_src
) {
2206 dev_err(codec
->dev
, "FLL%d is currently providing SYSCLK\n",
2211 /* We always need to disable the FLL while reconfiguring */
2212 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
,
2213 WM8994_FLL1_ENA
, 0);
2215 if (wm8994
->fll_byp
&& src
== WM8994_FLL_SRC_BCLK
&&
2216 freq_in
== freq_out
&& freq_out
) {
2217 dev_dbg(codec
->dev
, "Bypassing FLL%d\n", id
+ 1);
2218 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_5
+ reg_offset
,
2219 WM8958_FLL1_BYP
, WM8958_FLL1_BYP
);
2223 reg
= (fll
.outdiv
<< WM8994_FLL1_OUTDIV_SHIFT
) |
2224 (fll
.fll_fratio
<< WM8994_FLL1_FRATIO_SHIFT
);
2225 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_2
+ reg_offset
,
2226 WM8994_FLL1_OUTDIV_MASK
|
2227 WM8994_FLL1_FRATIO_MASK
, reg
);
2229 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_3
+ reg_offset
,
2230 WM8994_FLL1_K_MASK
, fll
.k
);
2232 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_4
+ reg_offset
,
2234 fll
.n
<< WM8994_FLL1_N_SHIFT
);
2237 snd_soc_update_bits(codec
, WM8958_FLL1_EFS_1
+ reg_offset
,
2238 WM8958_FLL1_LAMBDA_MASK
,
2240 snd_soc_update_bits(codec
, WM8958_FLL1_EFS_2
+ reg_offset
,
2241 WM8958_FLL1_EFS_ENA
, WM8958_FLL1_EFS_ENA
);
2243 snd_soc_update_bits(codec
, WM8958_FLL1_EFS_2
+ reg_offset
,
2244 WM8958_FLL1_EFS_ENA
, 0);
2247 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_5
+ reg_offset
,
2248 WM8994_FLL1_FRC_NCO
| WM8958_FLL1_BYP
|
2249 WM8994_FLL1_REFCLK_DIV_MASK
|
2250 WM8994_FLL1_REFCLK_SRC_MASK
,
2251 ((src
== WM8994_FLL_SRC_INTERNAL
)
2252 << WM8994_FLL1_FRC_NCO_SHIFT
) |
2253 (fll
.clk_ref_div
<< WM8994_FLL1_REFCLK_DIV_SHIFT
) |
2256 /* Clear any pending completion from a previous failure */
2257 try_wait_for_completion(&wm8994
->fll_locked
[id
]);
2259 /* Enable (with fractional mode if required) */
2261 /* Enable VMID if we need it */
2263 active_reference(codec
);
2265 switch (control
->type
) {
2267 vmid_reference(codec
);
2270 if (control
->revision
< 1)
2271 vmid_reference(codec
);
2278 reg
= WM8994_FLL1_ENA
;
2281 reg
|= WM8994_FLL1_FRAC
;
2282 if (src
== WM8994_FLL_SRC_INTERNAL
)
2283 reg
|= WM8994_FLL1_OSC_ENA
;
2285 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
,
2286 WM8994_FLL1_ENA
| WM8994_FLL1_OSC_ENA
|
2287 WM8994_FLL1_FRAC
, reg
);
2289 if (wm8994
->fll_locked_irq
) {
2290 timeout
= wait_for_completion_timeout(&wm8994
->fll_locked
[id
],
2291 msecs_to_jiffies(10));
2293 dev_warn(codec
->dev
,
2294 "Timed out waiting for FLL lock\n");
2300 switch (control
->type
) {
2302 vmid_dereference(codec
);
2305 if (control
->revision
< 1)
2306 vmid_dereference(codec
);
2312 active_dereference(codec
);
2317 wm8994
->fll
[id
].in
= freq_in
;
2318 wm8994
->fll
[id
].out
= freq_out
;
2319 wm8994
->fll
[id
].src
= src
;
2321 configure_clock(codec
);
2324 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2327 if (max(wm8994
->aifclk
[0], wm8994
->aifclk
[1]) < 50000) {
2328 dev_dbg(codec
->dev
, "Configuring AIFs for 128fs\n");
2330 wm8994
->aifdiv
[0] = snd_soc_read(codec
, WM8994_AIF1_RATE
)
2331 & WM8994_AIF1CLK_RATE_MASK
;
2332 wm8994
->aifdiv
[1] = snd_soc_read(codec
, WM8994_AIF2_RATE
)
2333 & WM8994_AIF1CLK_RATE_MASK
;
2335 snd_soc_update_bits(codec
, WM8994_AIF1_RATE
,
2336 WM8994_AIF1CLK_RATE_MASK
, 0x1);
2337 snd_soc_update_bits(codec
, WM8994_AIF2_RATE
,
2338 WM8994_AIF2CLK_RATE_MASK
, 0x1);
2339 } else if (wm8994
->aifdiv
[0]) {
2340 snd_soc_update_bits(codec
, WM8994_AIF1_RATE
,
2341 WM8994_AIF1CLK_RATE_MASK
,
2343 snd_soc_update_bits(codec
, WM8994_AIF2_RATE
,
2344 WM8994_AIF2CLK_RATE_MASK
,
2347 wm8994
->aifdiv
[0] = 0;
2348 wm8994
->aifdiv
[1] = 0;
2354 static irqreturn_t
wm8994_fll_locked_irq(int irq
, void *data
)
2356 struct completion
*completion
= data
;
2358 complete(completion
);
2363 static int opclk_divs
[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2365 static int wm8994_set_fll(struct snd_soc_dai
*dai
, int id
, int src
,
2366 unsigned int freq_in
, unsigned int freq_out
)
2368 return _wm8994_set_fll(dai
->codec
, id
, src
, freq_in
, freq_out
);
2371 static int wm8994_set_dai_sysclk(struct snd_soc_dai
*dai
,
2372 int clk_id
, unsigned int freq
, int dir
)
2374 struct snd_soc_codec
*codec
= dai
->codec
;
2375 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2384 /* AIF3 shares clocking with AIF1/2 */
2389 case WM8994_SYSCLK_MCLK1
:
2390 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_MCLK1
;
2391 wm8994
->mclk
[0] = freq
;
2392 dev_dbg(dai
->dev
, "AIF%d using MCLK1 at %uHz\n",
2396 case WM8994_SYSCLK_MCLK2
:
2397 /* TODO: Set GPIO AF */
2398 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_MCLK2
;
2399 wm8994
->mclk
[1] = freq
;
2400 dev_dbg(dai
->dev
, "AIF%d using MCLK2 at %uHz\n",
2404 case WM8994_SYSCLK_FLL1
:
2405 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_FLL1
;
2406 dev_dbg(dai
->dev
, "AIF%d using FLL1\n", dai
->id
);
2409 case WM8994_SYSCLK_FLL2
:
2410 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_FLL2
;
2411 dev_dbg(dai
->dev
, "AIF%d using FLL2\n", dai
->id
);
2414 case WM8994_SYSCLK_OPCLK
:
2415 /* Special case - a division (times 10) is given and
2416 * no effect on main clocking.
2419 for (i
= 0; i
< ARRAY_SIZE(opclk_divs
); i
++)
2420 if (opclk_divs
[i
] == freq
)
2422 if (i
== ARRAY_SIZE(opclk_divs
))
2424 snd_soc_update_bits(codec
, WM8994_CLOCKING_2
,
2425 WM8994_OPCLK_DIV_MASK
, i
);
2426 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_2
,
2427 WM8994_OPCLK_ENA
, WM8994_OPCLK_ENA
);
2429 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_2
,
2430 WM8994_OPCLK_ENA
, 0);
2437 configure_clock(codec
);
2440 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2443 if (max(wm8994
->aifclk
[0], wm8994
->aifclk
[1]) < 50000) {
2444 dev_dbg(codec
->dev
, "Configuring AIFs for 128fs\n");
2446 wm8994
->aifdiv
[0] = snd_soc_read(codec
, WM8994_AIF1_RATE
)
2447 & WM8994_AIF1CLK_RATE_MASK
;
2448 wm8994
->aifdiv
[1] = snd_soc_read(codec
, WM8994_AIF2_RATE
)
2449 & WM8994_AIF1CLK_RATE_MASK
;
2451 snd_soc_update_bits(codec
, WM8994_AIF1_RATE
,
2452 WM8994_AIF1CLK_RATE_MASK
, 0x1);
2453 snd_soc_update_bits(codec
, WM8994_AIF2_RATE
,
2454 WM8994_AIF2CLK_RATE_MASK
, 0x1);
2455 } else if (wm8994
->aifdiv
[0]) {
2456 snd_soc_update_bits(codec
, WM8994_AIF1_RATE
,
2457 WM8994_AIF1CLK_RATE_MASK
,
2459 snd_soc_update_bits(codec
, WM8994_AIF2_RATE
,
2460 WM8994_AIF2CLK_RATE_MASK
,
2463 wm8994
->aifdiv
[0] = 0;
2464 wm8994
->aifdiv
[1] = 0;
2470 static int wm8994_set_bias_level(struct snd_soc_codec
*codec
,
2471 enum snd_soc_bias_level level
)
2473 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2474 struct wm8994
*control
= wm8994
->wm8994
;
2476 wm_hubs_set_bias_level(codec
, level
);
2479 case SND_SOC_BIAS_ON
:
2482 case SND_SOC_BIAS_PREPARE
:
2483 /* MICBIAS into regulating mode */
2484 switch (control
->type
) {
2487 snd_soc_update_bits(codec
, WM8958_MICBIAS1
,
2488 WM8958_MICB1_MODE
, 0);
2489 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
2490 WM8958_MICB2_MODE
, 0);
2496 if (snd_soc_codec_get_bias_level(codec
) == SND_SOC_BIAS_STANDBY
)
2497 active_reference(codec
);
2500 case SND_SOC_BIAS_STANDBY
:
2501 if (snd_soc_codec_get_bias_level(codec
) == SND_SOC_BIAS_OFF
) {
2502 switch (control
->type
) {
2504 if (control
->revision
== 0) {
2505 /* Optimise performance for rev A */
2506 snd_soc_update_bits(codec
,
2507 WM8958_CHARGE_PUMP_2
,
2517 /* Discharge LINEOUT1 & 2 */
2518 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
2519 WM8994_LINEOUT1_DISCH
|
2520 WM8994_LINEOUT2_DISCH
,
2521 WM8994_LINEOUT1_DISCH
|
2522 WM8994_LINEOUT2_DISCH
);
2525 if (snd_soc_codec_get_bias_level(codec
) == SND_SOC_BIAS_PREPARE
)
2526 active_dereference(codec
);
2528 /* MICBIAS into bypass mode on newer devices */
2529 switch (control
->type
) {
2532 snd_soc_update_bits(codec
, WM8958_MICBIAS1
,
2535 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
2544 case SND_SOC_BIAS_OFF
:
2545 if (snd_soc_codec_get_bias_level(codec
) == SND_SOC_BIAS_STANDBY
)
2546 wm8994
->cur_fw
= NULL
;
2553 int wm8994_vmid_mode(struct snd_soc_codec
*codec
, enum wm8994_vmid_mode mode
)
2555 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2556 struct snd_soc_dapm_context
*dapm
= snd_soc_codec_get_dapm(codec
);
2559 case WM8994_VMID_NORMAL
:
2560 snd_soc_dapm_mutex_lock(dapm
);
2562 if (wm8994
->hubs
.lineout1_se
) {
2563 snd_soc_dapm_disable_pin_unlocked(dapm
,
2564 "LINEOUT1N Driver");
2565 snd_soc_dapm_disable_pin_unlocked(dapm
,
2566 "LINEOUT1P Driver");
2568 if (wm8994
->hubs
.lineout2_se
) {
2569 snd_soc_dapm_disable_pin_unlocked(dapm
,
2570 "LINEOUT2N Driver");
2571 snd_soc_dapm_disable_pin_unlocked(dapm
,
2572 "LINEOUT2P Driver");
2575 /* Do the sync with the old mode to allow it to clean up */
2576 snd_soc_dapm_sync_unlocked(dapm
);
2577 wm8994
->vmid_mode
= mode
;
2579 snd_soc_dapm_mutex_unlock(dapm
);
2582 case WM8994_VMID_FORCE
:
2583 snd_soc_dapm_mutex_lock(dapm
);
2585 if (wm8994
->hubs
.lineout1_se
) {
2586 snd_soc_dapm_force_enable_pin_unlocked(dapm
,
2587 "LINEOUT1N Driver");
2588 snd_soc_dapm_force_enable_pin_unlocked(dapm
,
2589 "LINEOUT1P Driver");
2591 if (wm8994
->hubs
.lineout2_se
) {
2592 snd_soc_dapm_force_enable_pin_unlocked(dapm
,
2593 "LINEOUT2N Driver");
2594 snd_soc_dapm_force_enable_pin_unlocked(dapm
,
2595 "LINEOUT2P Driver");
2598 wm8994
->vmid_mode
= mode
;
2599 snd_soc_dapm_sync_unlocked(dapm
);
2601 snd_soc_dapm_mutex_unlock(dapm
);
2611 static int wm8994_set_dai_fmt(struct snd_soc_dai
*dai
, unsigned int fmt
)
2613 struct snd_soc_codec
*codec
= dai
->codec
;
2614 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2615 struct wm8994
*control
= wm8994
->wm8994
;
2626 ms_reg
= WM8994_AIF1_MASTER_SLAVE
;
2627 aif1_reg
= WM8994_AIF1_CONTROL_1
;
2628 dac_reg
= WM8994_AIF1DAC_LRCLK
;
2629 adc_reg
= WM8994_AIF1ADC_LRCLK
;
2632 ms_reg
= WM8994_AIF2_MASTER_SLAVE
;
2633 aif1_reg
= WM8994_AIF2_CONTROL_1
;
2634 dac_reg
= WM8994_AIF1DAC_LRCLK
;
2635 adc_reg
= WM8994_AIF1ADC_LRCLK
;
2641 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
2642 case SND_SOC_DAIFMT_CBS_CFS
:
2644 case SND_SOC_DAIFMT_CBM_CFM
:
2645 ms
= WM8994_AIF1_MSTR
;
2651 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
2652 case SND_SOC_DAIFMT_DSP_B
:
2653 aif1
|= WM8994_AIF1_LRCLK_INV
;
2654 lrclk
|= WM8958_AIF1_LRCLK_INV
;
2655 case SND_SOC_DAIFMT_DSP_A
:
2658 case SND_SOC_DAIFMT_I2S
:
2661 case SND_SOC_DAIFMT_RIGHT_J
:
2663 case SND_SOC_DAIFMT_LEFT_J
:
2670 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
2671 case SND_SOC_DAIFMT_DSP_A
:
2672 case SND_SOC_DAIFMT_DSP_B
:
2673 /* frame inversion not valid for DSP modes */
2674 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
2675 case SND_SOC_DAIFMT_NB_NF
:
2677 case SND_SOC_DAIFMT_IB_NF
:
2678 aif1
|= WM8994_AIF1_BCLK_INV
;
2685 case SND_SOC_DAIFMT_I2S
:
2686 case SND_SOC_DAIFMT_RIGHT_J
:
2687 case SND_SOC_DAIFMT_LEFT_J
:
2688 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
2689 case SND_SOC_DAIFMT_NB_NF
:
2691 case SND_SOC_DAIFMT_IB_IF
:
2692 aif1
|= WM8994_AIF1_BCLK_INV
| WM8994_AIF1_LRCLK_INV
;
2693 lrclk
|= WM8958_AIF1_LRCLK_INV
;
2695 case SND_SOC_DAIFMT_IB_NF
:
2696 aif1
|= WM8994_AIF1_BCLK_INV
;
2698 case SND_SOC_DAIFMT_NB_IF
:
2699 aif1
|= WM8994_AIF1_LRCLK_INV
;
2700 lrclk
|= WM8958_AIF1_LRCLK_INV
;
2710 /* The AIF2 format configuration needs to be mirrored to AIF3
2711 * on WM8958 if it's in use so just do it all the time. */
2712 switch (control
->type
) {
2716 snd_soc_update_bits(codec
, WM8958_AIF3_CONTROL_1
,
2717 WM8994_AIF1_LRCLK_INV
|
2718 WM8958_AIF3_FMT_MASK
, aif1
);
2725 snd_soc_update_bits(codec
, aif1_reg
,
2726 WM8994_AIF1_BCLK_INV
| WM8994_AIF1_LRCLK_INV
|
2727 WM8994_AIF1_FMT_MASK
,
2729 snd_soc_update_bits(codec
, ms_reg
, WM8994_AIF1_MSTR
,
2731 snd_soc_update_bits(codec
, dac_reg
,
2732 WM8958_AIF1_LRCLK_INV
, lrclk
);
2733 snd_soc_update_bits(codec
, adc_reg
,
2734 WM8958_AIF1_LRCLK_INV
, lrclk
);
2755 static int fs_ratios
[] = {
2756 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536
2759 static int bclk_divs
[] = {
2760 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2761 640, 880, 960, 1280, 1760, 1920
2764 static int wm8994_hw_params(struct snd_pcm_substream
*substream
,
2765 struct snd_pcm_hw_params
*params
,
2766 struct snd_soc_dai
*dai
)
2768 struct snd_soc_codec
*codec
= dai
->codec
;
2769 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2770 struct wm8994
*control
= wm8994
->wm8994
;
2771 struct wm8994_pdata
*pdata
= &control
->pdata
;
2782 int id
= dai
->id
- 1;
2784 int i
, cur_val
, best_val
, bclk_rate
, best
;
2788 aif1_reg
= WM8994_AIF1_CONTROL_1
;
2789 aif2_reg
= WM8994_AIF1_CONTROL_2
;
2790 bclk_reg
= WM8994_AIF1_BCLK
;
2791 rate_reg
= WM8994_AIF1_RATE
;
2792 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
||
2793 wm8994
->lrclk_shared
[0]) {
2794 lrclk_reg
= WM8994_AIF1DAC_LRCLK
;
2796 lrclk_reg
= WM8994_AIF1ADC_LRCLK
;
2797 dev_dbg(codec
->dev
, "AIF1 using split LRCLK\n");
2801 aif1_reg
= WM8994_AIF2_CONTROL_1
;
2802 aif2_reg
= WM8994_AIF2_CONTROL_2
;
2803 bclk_reg
= WM8994_AIF2_BCLK
;
2804 rate_reg
= WM8994_AIF2_RATE
;
2805 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
||
2806 wm8994
->lrclk_shared
[1]) {
2807 lrclk_reg
= WM8994_AIF2DAC_LRCLK
;
2809 lrclk_reg
= WM8994_AIF2ADC_LRCLK
;
2810 dev_dbg(codec
->dev
, "AIF2 using split LRCLK\n");
2817 bclk_rate
= params_rate(params
);
2818 switch (params_width(params
)) {
2838 wm8994
->channels
[id
] = params_channels(params
);
2839 if (pdata
->max_channels_clocked
[id
] &&
2840 wm8994
->channels
[id
] > pdata
->max_channels_clocked
[id
]) {
2841 dev_dbg(dai
->dev
, "Constraining channels to %d from %d\n",
2842 pdata
->max_channels_clocked
[id
], wm8994
->channels
[id
]);
2843 wm8994
->channels
[id
] = pdata
->max_channels_clocked
[id
];
2846 switch (wm8994
->channels
[id
]) {
2856 /* Try to find an appropriate sample rate; look for an exact match. */
2857 for (i
= 0; i
< ARRAY_SIZE(srs
); i
++)
2858 if (srs
[i
].rate
== params_rate(params
))
2860 if (i
== ARRAY_SIZE(srs
))
2862 rate_val
|= srs
[i
].val
<< WM8994_AIF1_SR_SHIFT
;
2864 dev_dbg(dai
->dev
, "Sample rate is %dHz\n", srs
[i
].rate
);
2865 dev_dbg(dai
->dev
, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2866 dai
->id
, wm8994
->aifclk
[id
], bclk_rate
);
2868 if (wm8994
->channels
[id
] == 1 &&
2869 (snd_soc_read(codec
, aif1_reg
) & 0x18) == 0x18)
2870 aif2
|= WM8994_AIF1_MONO
;
2872 if (wm8994
->aifclk
[id
] == 0) {
2873 dev_err(dai
->dev
, "AIF%dCLK not configured\n", dai
->id
);
2877 /* AIFCLK/fs ratio; look for a close match in either direction */
2879 best_val
= abs((fs_ratios
[0] * params_rate(params
))
2880 - wm8994
->aifclk
[id
]);
2881 for (i
= 1; i
< ARRAY_SIZE(fs_ratios
); i
++) {
2882 cur_val
= abs((fs_ratios
[i
] * params_rate(params
))
2883 - wm8994
->aifclk
[id
]);
2884 if (cur_val
>= best_val
)
2889 dev_dbg(dai
->dev
, "Selected AIF%dCLK/fs = %d\n",
2890 dai
->id
, fs_ratios
[best
]);
2893 /* We may not get quite the right frequency if using
2894 * approximate clocks so look for the closest match that is
2895 * higher than the target (we need to ensure that there enough
2896 * BCLKs to clock out the samples).
2899 for (i
= 0; i
< ARRAY_SIZE(bclk_divs
); i
++) {
2900 cur_val
= (wm8994
->aifclk
[id
] * 10 / bclk_divs
[i
]) - bclk_rate
;
2901 if (cur_val
< 0) /* BCLK table is sorted */
2905 bclk_rate
= wm8994
->aifclk
[id
] * 10 / bclk_divs
[best
];
2906 dev_dbg(dai
->dev
, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2907 bclk_divs
[best
], bclk_rate
);
2908 bclk
|= best
<< WM8994_AIF1_BCLK_DIV_SHIFT
;
2910 lrclk
= bclk_rate
/ params_rate(params
);
2912 dev_err(dai
->dev
, "Unable to generate LRCLK from %dHz BCLK\n",
2916 dev_dbg(dai
->dev
, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2917 lrclk
, bclk_rate
/ lrclk
);
2919 snd_soc_update_bits(codec
, aif1_reg
, WM8994_AIF1_WL_MASK
, aif1
);
2920 snd_soc_update_bits(codec
, aif2_reg
, WM8994_AIF1_MONO
, aif2
);
2921 snd_soc_update_bits(codec
, bclk_reg
, WM8994_AIF1_BCLK_DIV_MASK
, bclk
);
2922 snd_soc_update_bits(codec
, lrclk_reg
, WM8994_AIF1DAC_RATE_MASK
,
2924 snd_soc_update_bits(codec
, rate_reg
, WM8994_AIF1_SR_MASK
|
2925 WM8994_AIF1CLK_RATE_MASK
, rate_val
);
2927 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
2930 wm8994
->dac_rates
[0] = params_rate(params
);
2931 wm8994_set_retune_mobile(codec
, 0);
2932 wm8994_set_retune_mobile(codec
, 1);
2935 wm8994
->dac_rates
[1] = params_rate(params
);
2936 wm8994_set_retune_mobile(codec
, 2);
2944 static int wm8994_aif3_hw_params(struct snd_pcm_substream
*substream
,
2945 struct snd_pcm_hw_params
*params
,
2946 struct snd_soc_dai
*dai
)
2948 struct snd_soc_codec
*codec
= dai
->codec
;
2949 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2950 struct wm8994
*control
= wm8994
->wm8994
;
2956 switch (control
->type
) {
2959 aif1_reg
= WM8958_AIF3_CONTROL_1
;
2969 switch (params_width(params
)) {
2985 return snd_soc_update_bits(codec
, aif1_reg
, WM8994_AIF1_WL_MASK
, aif1
);
2988 static int wm8994_aif_mute(struct snd_soc_dai
*codec_dai
, int mute
)
2990 struct snd_soc_codec
*codec
= codec_dai
->codec
;
2994 switch (codec_dai
->id
) {
2996 mute_reg
= WM8994_AIF1_DAC1_FILTERS_1
;
2999 mute_reg
= WM8994_AIF2_DAC_FILTERS_1
;
3006 reg
= WM8994_AIF1DAC1_MUTE
;
3010 snd_soc_update_bits(codec
, mute_reg
, WM8994_AIF1DAC1_MUTE
, reg
);
3015 static int wm8994_set_tristate(struct snd_soc_dai
*codec_dai
, int tristate
)
3017 struct snd_soc_codec
*codec
= codec_dai
->codec
;
3020 switch (codec_dai
->id
) {
3022 reg
= WM8994_AIF1_MASTER_SLAVE
;
3023 mask
= WM8994_AIF1_TRI
;
3026 reg
= WM8994_AIF2_MASTER_SLAVE
;
3027 mask
= WM8994_AIF2_TRI
;
3038 return snd_soc_update_bits(codec
, reg
, mask
, val
);
3041 static int wm8994_aif2_probe(struct snd_soc_dai
*dai
)
3043 struct snd_soc_codec
*codec
= dai
->codec
;
3045 /* Disable the pulls on the AIF if we're using it to save power. */
3046 snd_soc_update_bits(codec
, WM8994_GPIO_3
,
3047 WM8994_GPN_PU
| WM8994_GPN_PD
, 0);
3048 snd_soc_update_bits(codec
, WM8994_GPIO_4
,
3049 WM8994_GPN_PU
| WM8994_GPN_PD
, 0);
3050 snd_soc_update_bits(codec
, WM8994_GPIO_5
,
3051 WM8994_GPN_PU
| WM8994_GPN_PD
, 0);
3056 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
3058 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3059 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
3061 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops
= {
3062 .set_sysclk
= wm8994_set_dai_sysclk
,
3063 .set_fmt
= wm8994_set_dai_fmt
,
3064 .hw_params
= wm8994_hw_params
,
3065 .digital_mute
= wm8994_aif_mute
,
3066 .set_pll
= wm8994_set_fll
,
3067 .set_tristate
= wm8994_set_tristate
,
3070 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops
= {
3071 .set_sysclk
= wm8994_set_dai_sysclk
,
3072 .set_fmt
= wm8994_set_dai_fmt
,
3073 .hw_params
= wm8994_hw_params
,
3074 .digital_mute
= wm8994_aif_mute
,
3075 .set_pll
= wm8994_set_fll
,
3076 .set_tristate
= wm8994_set_tristate
,
3079 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops
= {
3080 .hw_params
= wm8994_aif3_hw_params
,
3083 static struct snd_soc_dai_driver wm8994_dai
[] = {
3085 .name
= "wm8994-aif1",
3088 .stream_name
= "AIF1 Playback",
3091 .rates
= WM8994_RATES
,
3092 .formats
= WM8994_FORMATS
,
3096 .stream_name
= "AIF1 Capture",
3099 .rates
= WM8994_RATES
,
3100 .formats
= WM8994_FORMATS
,
3103 .ops
= &wm8994_aif1_dai_ops
,
3106 .name
= "wm8994-aif2",
3109 .stream_name
= "AIF2 Playback",
3112 .rates
= WM8994_RATES
,
3113 .formats
= WM8994_FORMATS
,
3117 .stream_name
= "AIF2 Capture",
3120 .rates
= WM8994_RATES
,
3121 .formats
= WM8994_FORMATS
,
3124 .probe
= wm8994_aif2_probe
,
3125 .ops
= &wm8994_aif2_dai_ops
,
3128 .name
= "wm8994-aif3",
3131 .stream_name
= "AIF3 Playback",
3134 .rates
= WM8994_RATES
,
3135 .formats
= WM8994_FORMATS
,
3139 .stream_name
= "AIF3 Capture",
3142 .rates
= WM8994_RATES
,
3143 .formats
= WM8994_FORMATS
,
3146 .ops
= &wm8994_aif3_dai_ops
,
3151 static int wm8994_codec_suspend(struct snd_soc_codec
*codec
)
3153 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3156 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll
); i
++) {
3157 memcpy(&wm8994
->fll_suspend
[i
], &wm8994
->fll
[i
],
3158 sizeof(struct wm8994_fll_config
));
3159 ret
= _wm8994_set_fll(codec
, i
+ 1, 0, 0, 0);
3161 dev_warn(codec
->dev
, "Failed to stop FLL%d: %d\n",
3165 snd_soc_codec_force_bias_level(codec
, SND_SOC_BIAS_OFF
);
3170 static int wm8994_codec_resume(struct snd_soc_codec
*codec
)
3172 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3175 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll
); i
++) {
3176 if (!wm8994
->fll_suspend
[i
].out
)
3179 ret
= _wm8994_set_fll(codec
, i
+ 1,
3180 wm8994
->fll_suspend
[i
].src
,
3181 wm8994
->fll_suspend
[i
].in
,
3182 wm8994
->fll_suspend
[i
].out
);
3184 dev_warn(codec
->dev
, "Failed to restore FLL%d: %d\n",
3191 #define wm8994_codec_suspend NULL
3192 #define wm8994_codec_resume NULL
3195 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv
*wm8994
)
3197 struct snd_soc_codec
*codec
= wm8994
->hubs
.codec
;
3198 struct wm8994
*control
= wm8994
->wm8994
;
3199 struct wm8994_pdata
*pdata
= &control
->pdata
;
3200 struct snd_kcontrol_new controls
[] = {
3201 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3202 wm8994
->retune_mobile_enum
,
3203 wm8994_get_retune_mobile_enum
,
3204 wm8994_put_retune_mobile_enum
),
3205 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3206 wm8994
->retune_mobile_enum
,
3207 wm8994_get_retune_mobile_enum
,
3208 wm8994_put_retune_mobile_enum
),
3209 SOC_ENUM_EXT("AIF2 EQ Mode",
3210 wm8994
->retune_mobile_enum
,
3211 wm8994_get_retune_mobile_enum
,
3212 wm8994_put_retune_mobile_enum
),
3217 /* We need an array of texts for the enum API but the number
3218 * of texts is likely to be less than the number of
3219 * configurations due to the sample rate dependency of the
3220 * configurations. */
3221 wm8994
->num_retune_mobile_texts
= 0;
3222 wm8994
->retune_mobile_texts
= NULL
;
3223 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
3224 for (j
= 0; j
< wm8994
->num_retune_mobile_texts
; j
++) {
3225 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
3226 wm8994
->retune_mobile_texts
[j
]) == 0)
3230 if (j
!= wm8994
->num_retune_mobile_texts
)
3233 /* Expand the array... */
3234 t
= krealloc(wm8994
->retune_mobile_texts
,
3236 (wm8994
->num_retune_mobile_texts
+ 1),
3241 /* ...store the new entry... */
3242 t
[wm8994
->num_retune_mobile_texts
] =
3243 pdata
->retune_mobile_cfgs
[i
].name
;
3245 /* ...and remember the new version. */
3246 wm8994
->num_retune_mobile_texts
++;
3247 wm8994
->retune_mobile_texts
= t
;
3250 dev_dbg(codec
->dev
, "Allocated %d unique ReTune Mobile names\n",
3251 wm8994
->num_retune_mobile_texts
);
3253 wm8994
->retune_mobile_enum
.items
= wm8994
->num_retune_mobile_texts
;
3254 wm8994
->retune_mobile_enum
.texts
= wm8994
->retune_mobile_texts
;
3256 ret
= snd_soc_add_codec_controls(wm8994
->hubs
.codec
, controls
,
3257 ARRAY_SIZE(controls
));
3259 dev_err(wm8994
->hubs
.codec
->dev
,
3260 "Failed to add ReTune Mobile controls: %d\n", ret
);
3263 static void wm8994_handle_pdata(struct wm8994_priv
*wm8994
)
3265 struct snd_soc_codec
*codec
= wm8994
->hubs
.codec
;
3266 struct wm8994
*control
= wm8994
->wm8994
;
3267 struct wm8994_pdata
*pdata
= &control
->pdata
;
3273 wm_hubs_handle_analogue_pdata(codec
, pdata
->lineout1_diff
,
3274 pdata
->lineout2_diff
,
3281 pdata
->micbias1_lvl
,
3282 pdata
->micbias2_lvl
);
3284 dev_dbg(codec
->dev
, "%d DRC configurations\n", pdata
->num_drc_cfgs
);
3286 if (pdata
->num_drc_cfgs
) {
3287 struct snd_kcontrol_new controls
[] = {
3288 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994
->drc_enum
,
3289 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
3290 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994
->drc_enum
,
3291 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
3292 SOC_ENUM_EXT("AIF2DRC Mode", wm8994
->drc_enum
,
3293 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
3296 /* We need an array of texts for the enum API */
3297 wm8994
->drc_texts
= devm_kzalloc(wm8994
->hubs
.codec
->dev
,
3298 sizeof(char *) * pdata
->num_drc_cfgs
, GFP_KERNEL
);
3299 if (!wm8994
->drc_texts
)
3302 for (i
= 0; i
< pdata
->num_drc_cfgs
; i
++)
3303 wm8994
->drc_texts
[i
] = pdata
->drc_cfgs
[i
].name
;
3305 wm8994
->drc_enum
.items
= pdata
->num_drc_cfgs
;
3306 wm8994
->drc_enum
.texts
= wm8994
->drc_texts
;
3308 ret
= snd_soc_add_codec_controls(wm8994
->hubs
.codec
, controls
,
3309 ARRAY_SIZE(controls
));
3310 for (i
= 0; i
< WM8994_NUM_DRC
; i
++)
3311 wm8994_set_drc(codec
, i
);
3313 ret
= snd_soc_add_codec_controls(wm8994
->hubs
.codec
,
3314 wm8994_drc_controls
,
3315 ARRAY_SIZE(wm8994_drc_controls
));
3319 dev_err(wm8994
->hubs
.codec
->dev
,
3320 "Failed to add DRC mode controls: %d\n", ret
);
3323 dev_dbg(codec
->dev
, "%d ReTune Mobile configurations\n",
3324 pdata
->num_retune_mobile_cfgs
);
3326 if (pdata
->num_retune_mobile_cfgs
)
3327 wm8994_handle_retune_mobile_pdata(wm8994
);
3329 snd_soc_add_codec_controls(wm8994
->hubs
.codec
, wm8994_eq_controls
,
3330 ARRAY_SIZE(wm8994_eq_controls
));
3332 for (i
= 0; i
< ARRAY_SIZE(pdata
->micbias
); i
++) {
3333 if (pdata
->micbias
[i
]) {
3334 snd_soc_write(codec
, WM8958_MICBIAS1
+ i
,
3335 pdata
->micbias
[i
] & 0xffff);
3341 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3343 * @codec: WM8994 codec
3344 * @jack: jack to report detection events on
3345 * @micbias: microphone bias to detect on
3347 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3348 * being used to bring out signals to the processor then only platform
3349 * data configuration is needed for WM8994 and processor GPIOs should
3350 * be configured using snd_soc_jack_add_gpios() instead.
3352 * Configuration of detection levels is available via the micbias1_lvl
3353 * and micbias2_lvl platform data members.
3355 int wm8994_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
3358 struct snd_soc_dapm_context
*dapm
= snd_soc_codec_get_dapm(codec
);
3359 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3360 struct wm8994_micdet
*micdet
;
3361 struct wm8994
*control
= wm8994
->wm8994
;
3364 if (control
->type
!= WM8994
) {
3365 dev_warn(codec
->dev
, "Not a WM8994\n");
3371 micdet
= &wm8994
->micdet
[0];
3373 ret
= snd_soc_dapm_force_enable_pin(dapm
, "MICBIAS1");
3375 ret
= snd_soc_dapm_disable_pin(dapm
, "MICBIAS1");
3378 micdet
= &wm8994
->micdet
[1];
3380 ret
= snd_soc_dapm_force_enable_pin(dapm
, "MICBIAS1");
3382 ret
= snd_soc_dapm_disable_pin(dapm
, "MICBIAS1");
3385 dev_warn(codec
->dev
, "Invalid MICBIAS %d\n", micbias
);
3390 dev_warn(codec
->dev
, "Failed to configure MICBIAS%d: %d\n",
3393 dev_dbg(codec
->dev
, "Configuring microphone detection on %d %p\n",
3396 /* Store the configuration */
3397 micdet
->jack
= jack
;
3398 micdet
->detecting
= true;
3400 /* If either of the jacks is set up then enable detection */
3401 if (wm8994
->micdet
[0].jack
|| wm8994
->micdet
[1].jack
)
3402 reg
= WM8994_MICD_ENA
;
3406 snd_soc_update_bits(codec
, WM8994_MICBIAS
, WM8994_MICD_ENA
, reg
);
3408 /* enable MICDET and MICSHRT deboune */
3409 snd_soc_update_bits(codec
, WM8994_IRQ_DEBOUNCE
,
3410 WM8994_MIC1_DET_DB_MASK
| WM8994_MIC1_SHRT_DB_MASK
|
3411 WM8994_MIC2_DET_DB_MASK
| WM8994_MIC2_SHRT_DB_MASK
,
3412 WM8994_MIC1_DET_DB
| WM8994_MIC1_SHRT_DB
);
3414 snd_soc_dapm_sync(dapm
);
3418 EXPORT_SYMBOL_GPL(wm8994_mic_detect
);
3420 static void wm8994_mic_work(struct work_struct
*work
)
3422 struct wm8994_priv
*priv
= container_of(work
,
3425 struct regmap
*regmap
= priv
->wm8994
->regmap
;
3426 struct device
*dev
= priv
->wm8994
->dev
;
3431 pm_runtime_get_sync(dev
);
3433 ret
= regmap_read(regmap
, WM8994_INTERRUPT_RAW_STATUS_2
, ®
);
3435 dev_err(dev
, "Failed to read microphone status: %d\n",
3437 pm_runtime_put(dev
);
3441 dev_dbg(dev
, "Microphone status: %x\n", reg
);
3444 if (reg
& WM8994_MIC1_DET_STS
) {
3445 if (priv
->micdet
[0].detecting
)
3446 report
= SND_JACK_HEADSET
;
3448 if (reg
& WM8994_MIC1_SHRT_STS
) {
3449 if (priv
->micdet
[0].detecting
)
3450 report
= SND_JACK_HEADPHONE
;
3452 report
|= SND_JACK_BTN_0
;
3455 priv
->micdet
[0].detecting
= false;
3457 priv
->micdet
[0].detecting
= true;
3459 snd_soc_jack_report(priv
->micdet
[0].jack
, report
,
3460 SND_JACK_HEADSET
| SND_JACK_BTN_0
);
3463 if (reg
& WM8994_MIC2_DET_STS
) {
3464 if (priv
->micdet
[1].detecting
)
3465 report
= SND_JACK_HEADSET
;
3467 if (reg
& WM8994_MIC2_SHRT_STS
) {
3468 if (priv
->micdet
[1].detecting
)
3469 report
= SND_JACK_HEADPHONE
;
3471 report
|= SND_JACK_BTN_0
;
3474 priv
->micdet
[1].detecting
= false;
3476 priv
->micdet
[1].detecting
= true;
3478 snd_soc_jack_report(priv
->micdet
[1].jack
, report
,
3479 SND_JACK_HEADSET
| SND_JACK_BTN_0
);
3481 pm_runtime_put(dev
);
3484 static irqreturn_t
wm8994_mic_irq(int irq
, void *data
)
3486 struct wm8994_priv
*priv
= data
;
3487 struct snd_soc_codec
*codec
= priv
->hubs
.codec
;
3489 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3490 trace_snd_soc_jack_irq(dev_name(codec
->dev
));
3493 pm_wakeup_event(codec
->dev
, 300);
3495 queue_delayed_work(system_power_efficient_wq
,
3496 &priv
->mic_work
, msecs_to_jiffies(250));
3501 /* Should be called with accdet_lock held */
3502 static void wm1811_micd_stop(struct snd_soc_codec
*codec
)
3504 struct snd_soc_dapm_context
*dapm
= snd_soc_codec_get_dapm(codec
);
3505 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3507 if (!wm8994
->jackdet
)
3510 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
, WM8958_MICD_ENA
, 0);
3512 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_JACK
);
3514 if (wm8994
->wm8994
->pdata
.jd_ext_cap
)
3515 snd_soc_dapm_disable_pin(dapm
, "MICBIAS2");
3518 static void wm8958_button_det(struct snd_soc_codec
*codec
, u16 status
)
3520 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3525 report
|= SND_JACK_BTN_0
;
3528 report
|= SND_JACK_BTN_1
;
3531 report
|= SND_JACK_BTN_2
;
3534 report
|= SND_JACK_BTN_3
;
3537 report
|= SND_JACK_BTN_4
;
3540 report
|= SND_JACK_BTN_5
;
3542 snd_soc_jack_report(wm8994
->micdet
[0].jack
, report
,
3546 static void wm8958_open_circuit_work(struct work_struct
*work
)
3548 struct wm8994_priv
*wm8994
= container_of(work
,
3550 open_circuit_work
.work
);
3551 struct device
*dev
= wm8994
->wm8994
->dev
;
3553 mutex_lock(&wm8994
->accdet_lock
);
3555 wm1811_micd_stop(wm8994
->hubs
.codec
);
3557 dev_dbg(dev
, "Reporting open circuit\n");
3559 wm8994
->jack_mic
= false;
3560 wm8994
->mic_detecting
= true;
3562 wm8958_micd_set_rate(wm8994
->hubs
.codec
);
3564 snd_soc_jack_report(wm8994
->micdet
[0].jack
, 0,
3568 mutex_unlock(&wm8994
->accdet_lock
);
3571 static void wm8958_mic_id(void *data
, u16 status
)
3573 struct snd_soc_codec
*codec
= data
;
3574 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3576 /* Either nothing present or just starting detection */
3577 if (!(status
& WM8958_MICD_STS
)) {
3578 /* If nothing present then clear our statuses */
3579 dev_dbg(codec
->dev
, "Detected open circuit\n");
3581 queue_delayed_work(system_power_efficient_wq
,
3582 &wm8994
->open_circuit_work
,
3583 msecs_to_jiffies(2500));
3587 /* If the measurement is showing a high impedence we've got a
3590 if (status
& 0x600) {
3591 dev_dbg(codec
->dev
, "Detected microphone\n");
3593 wm8994
->mic_detecting
= false;
3594 wm8994
->jack_mic
= true;
3596 wm8958_micd_set_rate(codec
);
3598 snd_soc_jack_report(wm8994
->micdet
[0].jack
, SND_JACK_HEADSET
,
3603 if (status
& 0xfc) {
3604 dev_dbg(codec
->dev
, "Detected headphone\n");
3605 wm8994
->mic_detecting
= false;
3607 wm8958_micd_set_rate(codec
);
3609 /* If we have jackdet that will detect removal */
3610 wm1811_micd_stop(codec
);
3612 snd_soc_jack_report(wm8994
->micdet
[0].jack
, SND_JACK_HEADPHONE
,
3617 /* Deferred mic detection to allow for extra settling time */
3618 static void wm1811_mic_work(struct work_struct
*work
)
3620 struct wm8994_priv
*wm8994
= container_of(work
, struct wm8994_priv
,
3622 struct wm8994
*control
= wm8994
->wm8994
;
3623 struct snd_soc_codec
*codec
= wm8994
->hubs
.codec
;
3624 struct snd_soc_dapm_context
*dapm
= snd_soc_codec_get_dapm(codec
);
3626 pm_runtime_get_sync(codec
->dev
);
3628 /* If required for an external cap force MICBIAS on */
3629 if (control
->pdata
.jd_ext_cap
) {
3630 snd_soc_dapm_force_enable_pin(dapm
, "MICBIAS2");
3631 snd_soc_dapm_sync(dapm
);
3634 mutex_lock(&wm8994
->accdet_lock
);
3636 dev_dbg(codec
->dev
, "Starting mic detection\n");
3638 /* Use a user-supplied callback if we have one */
3639 if (wm8994
->micd_cb
) {
3640 wm8994
->micd_cb(wm8994
->micd_cb_data
);
3643 * Start off measument of microphone impedence to find out
3644 * what's actually there.
3646 wm8994
->mic_detecting
= true;
3647 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_MIC
);
3649 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3650 WM8958_MICD_ENA
, WM8958_MICD_ENA
);
3653 mutex_unlock(&wm8994
->accdet_lock
);
3655 pm_runtime_put(codec
->dev
);
3658 static irqreturn_t
wm1811_jackdet_irq(int irq
, void *data
)
3660 struct wm8994_priv
*wm8994
= data
;
3661 struct wm8994
*control
= wm8994
->wm8994
;
3662 struct snd_soc_codec
*codec
= wm8994
->hubs
.codec
;
3663 struct snd_soc_dapm_context
*dapm
= snd_soc_codec_get_dapm(codec
);
3667 pm_runtime_get_sync(codec
->dev
);
3669 cancel_delayed_work_sync(&wm8994
->mic_complete_work
);
3671 mutex_lock(&wm8994
->accdet_lock
);
3673 reg
= snd_soc_read(codec
, WM1811_JACKDET_CTRL
);
3675 dev_err(codec
->dev
, "Failed to read jack status: %d\n", reg
);
3676 mutex_unlock(&wm8994
->accdet_lock
);
3677 pm_runtime_put(codec
->dev
);
3681 dev_dbg(codec
->dev
, "JACKDET %x\n", reg
);
3683 present
= reg
& WM1811_JACKDET_LVL
;
3686 dev_dbg(codec
->dev
, "Jack detected\n");
3688 wm8958_micd_set_rate(codec
);
3690 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
3691 WM8958_MICB2_DISCH
, 0);
3693 /* Disable debounce while inserted */
3694 snd_soc_update_bits(codec
, WM1811_JACKDET_CTRL
,
3695 WM1811_JACKDET_DB
, 0);
3697 delay
= control
->pdata
.micdet_delay
;
3698 queue_delayed_work(system_power_efficient_wq
,
3700 msecs_to_jiffies(delay
));
3702 dev_dbg(codec
->dev
, "Jack not detected\n");
3704 cancel_delayed_work_sync(&wm8994
->mic_work
);
3706 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
3707 WM8958_MICB2_DISCH
, WM8958_MICB2_DISCH
);
3709 /* Enable debounce while removed */
3710 snd_soc_update_bits(codec
, WM1811_JACKDET_CTRL
,
3711 WM1811_JACKDET_DB
, WM1811_JACKDET_DB
);
3713 wm8994
->mic_detecting
= false;
3714 wm8994
->jack_mic
= false;
3715 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3716 WM8958_MICD_ENA
, 0);
3717 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_JACK
);
3720 mutex_unlock(&wm8994
->accdet_lock
);
3722 /* Turn off MICBIAS if it was on for an external cap */
3723 if (control
->pdata
.jd_ext_cap
&& !present
)
3724 snd_soc_dapm_disable_pin(dapm
, "MICBIAS2");
3727 snd_soc_jack_report(wm8994
->micdet
[0].jack
,
3728 SND_JACK_MECHANICAL
, SND_JACK_MECHANICAL
);
3730 snd_soc_jack_report(wm8994
->micdet
[0].jack
, 0,
3731 SND_JACK_MECHANICAL
| SND_JACK_HEADSET
|
3734 /* Since we only report deltas force an update, ensures we
3735 * avoid bootstrapping issues with the core. */
3736 snd_soc_jack_report(wm8994
->micdet
[0].jack
, 0, 0);
3738 pm_runtime_put(codec
->dev
);
3742 static void wm1811_jackdet_bootstrap(struct work_struct
*work
)
3744 struct wm8994_priv
*wm8994
= container_of(work
,
3746 jackdet_bootstrap
.work
);
3747 wm1811_jackdet_irq(0, wm8994
);
3751 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3753 * @codec: WM8958 codec
3754 * @jack: jack to report detection events on
3756 * Enable microphone detection functionality for the WM8958. By
3757 * default simple detection which supports the detection of up to 6
3758 * buttons plus video and microphone functionality is supported.
3760 * The WM8958 has an advanced jack detection facility which is able to
3761 * support complex accessory detection, especially when used in
3762 * conjunction with external circuitry. In order to provide maximum
3763 * flexiblity a callback is provided which allows a completely custom
3764 * detection algorithm.
3766 int wm8958_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
3767 wm1811_micdet_cb det_cb
, void *det_cb_data
,
3768 wm1811_mic_id_cb id_cb
, void *id_cb_data
)
3770 struct snd_soc_dapm_context
*dapm
= snd_soc_codec_get_dapm(codec
);
3771 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3772 struct wm8994
*control
= wm8994
->wm8994
;
3775 switch (control
->type
) {
3784 snd_soc_dapm_force_enable_pin(dapm
, "CLK_SYS");
3785 snd_soc_dapm_sync(dapm
);
3787 wm8994
->micdet
[0].jack
= jack
;
3790 wm8994
->micd_cb
= det_cb
;
3791 wm8994
->micd_cb_data
= det_cb_data
;
3793 wm8994
->mic_detecting
= true;
3794 wm8994
->jack_mic
= false;
3798 wm8994
->mic_id_cb
= id_cb
;
3799 wm8994
->mic_id_cb_data
= id_cb_data
;
3801 wm8994
->mic_id_cb
= wm8958_mic_id
;
3802 wm8994
->mic_id_cb_data
= codec
;
3805 wm8958_micd_set_rate(codec
);
3807 /* Detect microphones and short circuits by default */
3808 if (control
->pdata
.micd_lvl_sel
)
3809 micd_lvl_sel
= control
->pdata
.micd_lvl_sel
;
3811 micd_lvl_sel
= 0x41;
3813 wm8994
->btn_mask
= SND_JACK_BTN_0
| SND_JACK_BTN_1
|
3814 SND_JACK_BTN_2
| SND_JACK_BTN_3
|
3815 SND_JACK_BTN_4
| SND_JACK_BTN_5
;
3817 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_2
,
3818 WM8958_MICD_LVL_SEL_MASK
, micd_lvl_sel
);
3820 WARN_ON(snd_soc_codec_get_bias_level(codec
) > SND_SOC_BIAS_STANDBY
);
3823 * If we can use jack detection start off with that,
3824 * otherwise jump straight to microphone detection.
3826 if (wm8994
->jackdet
) {
3827 /* Disable debounce for the initial detect */
3828 snd_soc_update_bits(codec
, WM1811_JACKDET_CTRL
,
3829 WM1811_JACKDET_DB
, 0);
3831 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
3833 WM8958_MICB2_DISCH
);
3834 snd_soc_update_bits(codec
, WM8994_LDO_1
,
3835 WM8994_LDO1_DISCH
, 0);
3836 wm1811_jackdet_set_mode(codec
,
3837 WM1811_JACKDET_MODE_JACK
);
3839 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3840 WM8958_MICD_ENA
, WM8958_MICD_ENA
);
3844 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3845 WM8958_MICD_ENA
, 0);
3846 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_NONE
);
3847 snd_soc_dapm_disable_pin(dapm
, "CLK_SYS");
3848 snd_soc_dapm_sync(dapm
);
3853 EXPORT_SYMBOL_GPL(wm8958_mic_detect
);
3855 static void wm8958_mic_work(struct work_struct
*work
)
3857 struct wm8994_priv
*wm8994
= container_of(work
,
3859 mic_complete_work
.work
);
3860 struct snd_soc_codec
*codec
= wm8994
->hubs
.codec
;
3862 pm_runtime_get_sync(codec
->dev
);
3864 mutex_lock(&wm8994
->accdet_lock
);
3866 wm8994
->mic_id_cb(wm8994
->mic_id_cb_data
, wm8994
->mic_status
);
3868 mutex_unlock(&wm8994
->accdet_lock
);
3870 pm_runtime_put(codec
->dev
);
3873 static irqreturn_t
wm8958_mic_irq(int irq
, void *data
)
3875 struct wm8994_priv
*wm8994
= data
;
3876 struct snd_soc_codec
*codec
= wm8994
->hubs
.codec
;
3877 int reg
, count
, ret
, id_delay
;
3880 * Jack detection may have detected a removal simulataneously
3881 * with an update of the MICDET status; if so it will have
3882 * stopped detection and we can ignore this interrupt.
3884 if (!(snd_soc_read(codec
, WM8958_MIC_DETECT_1
) & WM8958_MICD_ENA
))
3887 cancel_delayed_work_sync(&wm8994
->mic_complete_work
);
3888 cancel_delayed_work_sync(&wm8994
->open_circuit_work
);
3890 pm_runtime_get_sync(codec
->dev
);
3892 /* We may occasionally read a detection without an impedence
3893 * range being provided - if that happens loop again.
3897 reg
= snd_soc_read(codec
, WM8958_MIC_DETECT_3
);
3900 "Failed to read mic detect status: %d\n",
3902 pm_runtime_put(codec
->dev
);
3906 if (!(reg
& WM8958_MICD_VALID
)) {
3907 dev_dbg(codec
->dev
, "Mic detect data not valid\n");
3911 if (!(reg
& WM8958_MICD_STS
) || (reg
& WM8958_MICD_LVL_MASK
))
3918 dev_warn(codec
->dev
, "No impedance range reported for jack\n");
3920 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3921 trace_snd_soc_jack_irq(dev_name(codec
->dev
));
3924 /* Avoid a transient report when the accessory is being removed */
3925 if (wm8994
->jackdet
) {
3926 ret
= snd_soc_read(codec
, WM1811_JACKDET_CTRL
);
3928 dev_err(codec
->dev
, "Failed to read jack status: %d\n",
3930 } else if (!(ret
& WM1811_JACKDET_LVL
)) {
3931 dev_dbg(codec
->dev
, "Ignoring removed jack\n");
3934 } else if (!(reg
& WM8958_MICD_STS
)) {
3935 snd_soc_jack_report(wm8994
->micdet
[0].jack
, 0,
3936 SND_JACK_MECHANICAL
| SND_JACK_HEADSET
|
3938 wm8994
->mic_detecting
= true;
3942 wm8994
->mic_status
= reg
;
3943 id_delay
= wm8994
->wm8994
->pdata
.mic_id_delay
;
3945 if (wm8994
->mic_detecting
)
3946 queue_delayed_work(system_power_efficient_wq
,
3947 &wm8994
->mic_complete_work
,
3948 msecs_to_jiffies(id_delay
));
3950 wm8958_button_det(codec
, reg
);
3953 pm_runtime_put(codec
->dev
);
3957 static irqreturn_t
wm8994_fifo_error(int irq
, void *data
)
3959 struct snd_soc_codec
*codec
= data
;
3961 dev_err(codec
->dev
, "FIFO error\n");
3966 static irqreturn_t
wm8994_temp_warn(int irq
, void *data
)
3968 struct snd_soc_codec
*codec
= data
;
3970 dev_err(codec
->dev
, "Thermal warning\n");
3975 static irqreturn_t
wm8994_temp_shut(int irq
, void *data
)
3977 struct snd_soc_codec
*codec
= data
;
3979 dev_crit(codec
->dev
, "Thermal shutdown\n");
3984 static int wm8994_codec_probe(struct snd_soc_codec
*codec
)
3986 struct snd_soc_dapm_context
*dapm
= snd_soc_codec_get_dapm(codec
);
3987 struct wm8994
*control
= dev_get_drvdata(codec
->dev
->parent
);
3988 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3992 wm8994
->hubs
.codec
= codec
;
3994 mutex_init(&wm8994
->accdet_lock
);
3995 INIT_DELAYED_WORK(&wm8994
->jackdet_bootstrap
,
3996 wm1811_jackdet_bootstrap
);
3997 INIT_DELAYED_WORK(&wm8994
->open_circuit_work
,
3998 wm8958_open_circuit_work
);
4000 switch (control
->type
) {
4002 INIT_DELAYED_WORK(&wm8994
->mic_work
, wm8994_mic_work
);
4005 INIT_DELAYED_WORK(&wm8994
->mic_work
, wm1811_mic_work
);
4011 INIT_DELAYED_WORK(&wm8994
->mic_complete_work
, wm8958_mic_work
);
4013 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++)
4014 init_completion(&wm8994
->fll_locked
[i
]);
4016 wm8994
->micdet_irq
= control
->pdata
.micdet_irq
;
4018 /* By default use idle_bias_off, will override for WM8994 */
4019 dapm
->idle_bias_off
= 1;
4021 /* Set revision-specific configuration */
4022 switch (control
->type
) {
4024 /* Single ended line outputs should have VMID on. */
4025 if (!control
->pdata
.lineout1_diff
||
4026 !control
->pdata
.lineout2_diff
)
4027 dapm
->idle_bias_off
= 0;
4029 switch (control
->revision
) {
4032 wm8994
->hubs
.dcs_codes_l
= -5;
4033 wm8994
->hubs
.dcs_codes_r
= -5;
4034 wm8994
->hubs
.hp_startup_mode
= 1;
4035 wm8994
->hubs
.dcs_readback_mode
= 1;
4036 wm8994
->hubs
.series_startup
= 1;
4039 wm8994
->hubs
.dcs_readback_mode
= 2;
4045 wm8994
->hubs
.dcs_readback_mode
= 1;
4046 wm8994
->hubs
.hp_startup_mode
= 1;
4048 switch (control
->revision
) {
4052 wm8994
->fll_byp
= true;
4058 wm8994
->hubs
.dcs_readback_mode
= 2;
4059 wm8994
->hubs
.no_series_update
= 1;
4060 wm8994
->hubs
.hp_startup_mode
= 1;
4061 wm8994
->hubs
.no_cache_dac_hp_direct
= true;
4062 wm8994
->fll_byp
= true;
4064 wm8994
->hubs
.dcs_codes_l
= -9;
4065 wm8994
->hubs
.dcs_codes_r
= -7;
4067 snd_soc_update_bits(codec
, WM8994_ANALOGUE_HP_1
,
4068 WM1811_HPOUT1_ATTN
, WM1811_HPOUT1_ATTN
);
4075 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_FIFOS_ERR
,
4076 wm8994_fifo_error
, "FIFO error", codec
);
4077 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_WARN
,
4078 wm8994_temp_warn
, "Thermal warning", codec
);
4079 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_SHUT
,
4080 wm8994_temp_shut
, "Thermal shutdown", codec
);
4082 switch (control
->type
) {
4084 if (wm8994
->micdet_irq
)
4085 ret
= request_threaded_irq(wm8994
->micdet_irq
, NULL
,
4087 IRQF_TRIGGER_RISING
|
4092 ret
= wm8994_request_irq(wm8994
->wm8994
,
4093 WM8994_IRQ_MIC1_DET
,
4094 wm8994_mic_irq
, "Mic 1 detect",
4098 dev_warn(codec
->dev
,
4099 "Failed to request Mic1 detect IRQ: %d\n",
4103 ret
= wm8994_request_irq(wm8994
->wm8994
,
4104 WM8994_IRQ_MIC1_SHRT
,
4105 wm8994_mic_irq
, "Mic 1 short",
4108 dev_warn(codec
->dev
,
4109 "Failed to request Mic1 short IRQ: %d\n",
4112 ret
= wm8994_request_irq(wm8994
->wm8994
,
4113 WM8994_IRQ_MIC2_DET
,
4114 wm8994_mic_irq
, "Mic 2 detect",
4117 dev_warn(codec
->dev
,
4118 "Failed to request Mic2 detect IRQ: %d\n",
4121 ret
= wm8994_request_irq(wm8994
->wm8994
,
4122 WM8994_IRQ_MIC2_SHRT
,
4123 wm8994_mic_irq
, "Mic 2 short",
4126 dev_warn(codec
->dev
,
4127 "Failed to request Mic2 short IRQ: %d\n",
4133 if (wm8994
->micdet_irq
) {
4134 ret
= request_threaded_irq(wm8994
->micdet_irq
, NULL
,
4136 IRQF_TRIGGER_RISING
|
4141 dev_warn(codec
->dev
,
4142 "Failed to request Mic detect IRQ: %d\n",
4145 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_DET
,
4146 wm8958_mic_irq
, "Mic detect",
4151 switch (control
->type
) {
4153 if (control
->cust_id
> 1 || control
->revision
> 1) {
4154 ret
= wm8994_request_irq(wm8994
->wm8994
,
4156 wm1811_jackdet_irq
, "JACKDET",
4159 wm8994
->jackdet
= true;
4166 wm8994
->fll_locked_irq
= true;
4167 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++) {
4168 ret
= wm8994_request_irq(wm8994
->wm8994
,
4169 WM8994_IRQ_FLL1_LOCK
+ i
,
4170 wm8994_fll_locked_irq
, "FLL lock",
4171 &wm8994
->fll_locked
[i
]);
4173 wm8994
->fll_locked_irq
= false;
4176 /* Make sure we can read from the GPIOs if they're inputs */
4177 pm_runtime_get_sync(codec
->dev
);
4179 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
4180 * configured on init - if a system wants to do this dynamically
4181 * at runtime we can deal with that then.
4183 ret
= regmap_read(control
->regmap
, WM8994_GPIO_1
, ®
);
4185 dev_err(codec
->dev
, "Failed to read GPIO1 state: %d\n", ret
);
4188 if ((reg
& WM8994_GPN_FN_MASK
) != WM8994_GP_FN_PIN_SPECIFIC
) {
4189 wm8994
->lrclk_shared
[0] = 1;
4190 wm8994_dai
[0].symmetric_rates
= 1;
4192 wm8994
->lrclk_shared
[0] = 0;
4195 ret
= regmap_read(control
->regmap
, WM8994_GPIO_6
, ®
);
4197 dev_err(codec
->dev
, "Failed to read GPIO6 state: %d\n", ret
);
4200 if ((reg
& WM8994_GPN_FN_MASK
) != WM8994_GP_FN_PIN_SPECIFIC
) {
4201 wm8994
->lrclk_shared
[1] = 1;
4202 wm8994_dai
[1].symmetric_rates
= 1;
4204 wm8994
->lrclk_shared
[1] = 0;
4207 pm_runtime_put(codec
->dev
);
4209 /* Latch volume update bits */
4210 for (i
= 0; i
< ARRAY_SIZE(wm8994_vu_bits
); i
++)
4211 snd_soc_update_bits(codec
, wm8994_vu_bits
[i
].reg
,
4212 wm8994_vu_bits
[i
].mask
,
4213 wm8994_vu_bits
[i
].mask
);
4215 /* Set the low bit of the 3D stereo depth so TLV matches */
4216 snd_soc_update_bits(codec
, WM8994_AIF1_DAC1_FILTERS_2
,
4217 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT
,
4218 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT
);
4219 snd_soc_update_bits(codec
, WM8994_AIF1_DAC2_FILTERS_2
,
4220 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT
,
4221 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT
);
4222 snd_soc_update_bits(codec
, WM8994_AIF2_DAC_FILTERS_2
,
4223 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT
,
4224 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT
);
4226 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
4227 * use this; it only affects behaviour on idle TDM clock
4229 switch (control
->type
) {
4232 snd_soc_update_bits(codec
, WM8994_AIF1_CONTROL_1
,
4233 WM8994_AIF1ADC_TDM
, WM8994_AIF1ADC_TDM
);
4239 /* Put MICBIAS into bypass mode by default on newer devices */
4240 switch (control
->type
) {
4243 snd_soc_update_bits(codec
, WM8958_MICBIAS1
,
4244 WM8958_MICB1_MODE
, WM8958_MICB1_MODE
);
4245 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
4246 WM8958_MICB2_MODE
, WM8958_MICB2_MODE
);
4252 wm8994
->hubs
.check_class_w_digital
= wm8994_check_class_w_digital
;
4253 wm_hubs_update_class_w(codec
);
4255 wm8994_handle_pdata(wm8994
);
4257 wm_hubs_add_analogue_controls(codec
);
4258 snd_soc_add_codec_controls(codec
, wm8994_snd_controls
,
4259 ARRAY_SIZE(wm8994_snd_controls
));
4260 snd_soc_dapm_new_controls(dapm
, wm8994_dapm_widgets
,
4261 ARRAY_SIZE(wm8994_dapm_widgets
));
4263 switch (control
->type
) {
4265 snd_soc_dapm_new_controls(dapm
, wm8994_specific_dapm_widgets
,
4266 ARRAY_SIZE(wm8994_specific_dapm_widgets
));
4267 if (control
->revision
< 4) {
4268 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_revd_widgets
,
4269 ARRAY_SIZE(wm8994_lateclk_revd_widgets
));
4270 snd_soc_dapm_new_controls(dapm
, wm8994_adc_revd_widgets
,
4271 ARRAY_SIZE(wm8994_adc_revd_widgets
));
4272 snd_soc_dapm_new_controls(dapm
, wm8994_dac_revd_widgets
,
4273 ARRAY_SIZE(wm8994_dac_revd_widgets
));
4275 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_widgets
,
4276 ARRAY_SIZE(wm8994_lateclk_widgets
));
4277 snd_soc_dapm_new_controls(dapm
, wm8994_adc_widgets
,
4278 ARRAY_SIZE(wm8994_adc_widgets
));
4279 snd_soc_dapm_new_controls(dapm
, wm8994_dac_widgets
,
4280 ARRAY_SIZE(wm8994_dac_widgets
));
4284 snd_soc_add_codec_controls(codec
, wm8958_snd_controls
,
4285 ARRAY_SIZE(wm8958_snd_controls
));
4286 snd_soc_dapm_new_controls(dapm
, wm8958_dapm_widgets
,
4287 ARRAY_SIZE(wm8958_dapm_widgets
));
4288 if (control
->revision
< 1) {
4289 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_revd_widgets
,
4290 ARRAY_SIZE(wm8994_lateclk_revd_widgets
));
4291 snd_soc_dapm_new_controls(dapm
, wm8994_adc_revd_widgets
,
4292 ARRAY_SIZE(wm8994_adc_revd_widgets
));
4293 snd_soc_dapm_new_controls(dapm
, wm8994_dac_revd_widgets
,
4294 ARRAY_SIZE(wm8994_dac_revd_widgets
));
4296 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_widgets
,
4297 ARRAY_SIZE(wm8994_lateclk_widgets
));
4298 snd_soc_dapm_new_controls(dapm
, wm8994_adc_widgets
,
4299 ARRAY_SIZE(wm8994_adc_widgets
));
4300 snd_soc_dapm_new_controls(dapm
, wm8994_dac_widgets
,
4301 ARRAY_SIZE(wm8994_dac_widgets
));
4306 snd_soc_add_codec_controls(codec
, wm8958_snd_controls
,
4307 ARRAY_SIZE(wm8958_snd_controls
));
4308 snd_soc_dapm_new_controls(dapm
, wm8958_dapm_widgets
,
4309 ARRAY_SIZE(wm8958_dapm_widgets
));
4310 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_widgets
,
4311 ARRAY_SIZE(wm8994_lateclk_widgets
));
4312 snd_soc_dapm_new_controls(dapm
, wm8994_adc_widgets
,
4313 ARRAY_SIZE(wm8994_adc_widgets
));
4314 snd_soc_dapm_new_controls(dapm
, wm8994_dac_widgets
,
4315 ARRAY_SIZE(wm8994_dac_widgets
));
4319 wm_hubs_add_analogue_routes(codec
, 0, 0);
4320 ret
= wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_DCS_DONE
,
4321 wm_hubs_dcs_done
, "DC servo done",
4324 wm8994
->hubs
.dcs_done_irq
= true;
4325 snd_soc_dapm_add_routes(dapm
, intercon
, ARRAY_SIZE(intercon
));
4327 switch (control
->type
) {
4329 snd_soc_dapm_add_routes(dapm
, wm8994_intercon
,
4330 ARRAY_SIZE(wm8994_intercon
));
4332 if (control
->revision
< 4) {
4333 snd_soc_dapm_add_routes(dapm
, wm8994_revd_intercon
,
4334 ARRAY_SIZE(wm8994_revd_intercon
));
4335 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_revd_intercon
,
4336 ARRAY_SIZE(wm8994_lateclk_revd_intercon
));
4338 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_intercon
,
4339 ARRAY_SIZE(wm8994_lateclk_intercon
));
4343 if (control
->revision
< 1) {
4344 snd_soc_dapm_add_routes(dapm
, wm8994_intercon
,
4345 ARRAY_SIZE(wm8994_intercon
));
4346 snd_soc_dapm_add_routes(dapm
, wm8994_revd_intercon
,
4347 ARRAY_SIZE(wm8994_revd_intercon
));
4348 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_revd_intercon
,
4349 ARRAY_SIZE(wm8994_lateclk_revd_intercon
));
4351 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_intercon
,
4352 ARRAY_SIZE(wm8994_lateclk_intercon
));
4353 snd_soc_dapm_add_routes(dapm
, wm8958_intercon
,
4354 ARRAY_SIZE(wm8958_intercon
));
4357 wm8958_dsp2_init(codec
);
4360 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_intercon
,
4361 ARRAY_SIZE(wm8994_lateclk_intercon
));
4362 snd_soc_dapm_add_routes(dapm
, wm8958_intercon
,
4363 ARRAY_SIZE(wm8958_intercon
));
4370 if (wm8994
->jackdet
)
4371 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_GPIO(6), wm8994
);
4372 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC2_SHRT
, wm8994
);
4373 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC2_DET
, wm8994
);
4374 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_SHRT
, wm8994
);
4375 if (wm8994
->micdet_irq
)
4376 free_irq(wm8994
->micdet_irq
, wm8994
);
4377 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++)
4378 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FLL1_LOCK
+ i
,
4379 &wm8994
->fll_locked
[i
]);
4380 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_DCS_DONE
,
4382 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FIFOS_ERR
, codec
);
4383 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_SHUT
, codec
);
4384 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_WARN
, codec
);
4389 static int wm8994_codec_remove(struct snd_soc_codec
*codec
)
4391 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
4392 struct wm8994
*control
= wm8994
->wm8994
;
4395 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++)
4396 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FLL1_LOCK
+ i
,
4397 &wm8994
->fll_locked
[i
]);
4399 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_DCS_DONE
,
4401 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FIFOS_ERR
, codec
);
4402 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_SHUT
, codec
);
4403 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_WARN
, codec
);
4405 if (wm8994
->jackdet
)
4406 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_GPIO(6), wm8994
);
4408 switch (control
->type
) {
4410 if (wm8994
->micdet_irq
)
4411 free_irq(wm8994
->micdet_irq
, wm8994
);
4412 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC2_DET
,
4414 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_SHRT
,
4416 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_DET
,
4422 if (wm8994
->micdet_irq
)
4423 free_irq(wm8994
->micdet_irq
, wm8994
);
4426 release_firmware(wm8994
->mbc
);
4427 release_firmware(wm8994
->mbc_vss
);
4428 release_firmware(wm8994
->enh_eq
);
4429 kfree(wm8994
->retune_mobile_texts
);
4433 static struct regmap
*wm8994_get_regmap(struct device
*dev
)
4435 struct wm8994
*control
= dev_get_drvdata(dev
->parent
);
4437 return control
->regmap
;
4440 static struct snd_soc_codec_driver soc_codec_dev_wm8994
= {
4441 .probe
= wm8994_codec_probe
,
4442 .remove
= wm8994_codec_remove
,
4443 .suspend
= wm8994_codec_suspend
,
4444 .resume
= wm8994_codec_resume
,
4445 .get_regmap
= wm8994_get_regmap
,
4446 .set_bias_level
= wm8994_set_bias_level
,
4449 static int wm8994_probe(struct platform_device
*pdev
)
4451 struct wm8994_priv
*wm8994
;
4453 wm8994
= devm_kzalloc(&pdev
->dev
, sizeof(struct wm8994_priv
),
4457 platform_set_drvdata(pdev
, wm8994
);
4459 mutex_init(&wm8994
->fw_lock
);
4461 wm8994
->wm8994
= dev_get_drvdata(pdev
->dev
.parent
);
4463 pm_runtime_enable(&pdev
->dev
);
4464 pm_runtime_idle(&pdev
->dev
);
4466 return snd_soc_register_codec(&pdev
->dev
, &soc_codec_dev_wm8994
,
4467 wm8994_dai
, ARRAY_SIZE(wm8994_dai
));
4470 static int wm8994_remove(struct platform_device
*pdev
)
4472 snd_soc_unregister_codec(&pdev
->dev
);
4473 pm_runtime_disable(&pdev
->dev
);
4478 #ifdef CONFIG_PM_SLEEP
4479 static int wm8994_suspend(struct device
*dev
)
4481 struct wm8994_priv
*wm8994
= dev_get_drvdata(dev
);
4483 /* Drop down to power saving mode when system is suspended */
4484 if (wm8994
->jackdet
&& !wm8994
->active_refcount
)
4485 regmap_update_bits(wm8994
->wm8994
->regmap
, WM8994_ANTIPOP_2
,
4486 WM1811_JACKDET_MODE_MASK
,
4487 wm8994
->jackdet_mode
);
4492 static int wm8994_resume(struct device
*dev
)
4494 struct wm8994_priv
*wm8994
= dev_get_drvdata(dev
);
4496 if (wm8994
->jackdet
&& wm8994
->jackdet_mode
)
4497 regmap_update_bits(wm8994
->wm8994
->regmap
, WM8994_ANTIPOP_2
,
4498 WM1811_JACKDET_MODE_MASK
,
4499 WM1811_JACKDET_MODE_AUDIO
);
4505 static const struct dev_pm_ops wm8994_pm_ops
= {
4506 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend
, wm8994_resume
)
4509 static struct platform_driver wm8994_codec_driver
= {
4511 .name
= "wm8994-codec",
4512 .pm
= &wm8994_pm_ops
,
4514 .probe
= wm8994_probe
,
4515 .remove
= wm8994_remove
,
4518 module_platform_driver(wm8994_codec_driver
);
4520 MODULE_DESCRIPTION("ASoC WM8994 driver");
4521 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4522 MODULE_LICENSE("GPL");
4523 MODULE_ALIAS("platform:wm8994-codec");