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ASoC: wm8994: Handle LRCLK inversion for WM8958 and WM1811A
[deliverable/linux.git] / sound / soc / codecs / wm8994.c
1 /*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009-12 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/gcd.h>
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/slab.h>
25 #include <sound/core.h>
26 #include <sound/jack.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
32 #include <trace/events/asoc.h>
33
34 #include <linux/mfd/wm8994/core.h>
35 #include <linux/mfd/wm8994/registers.h>
36 #include <linux/mfd/wm8994/pdata.h>
37 #include <linux/mfd/wm8994/gpio.h>
38
39 #include "wm8994.h"
40 #include "wm_hubs.h"
41
42 #define WM1811_JACKDET_MODE_NONE 0x0000
43 #define WM1811_JACKDET_MODE_JACK 0x0100
44 #define WM1811_JACKDET_MODE_MIC 0x0080
45 #define WM1811_JACKDET_MODE_AUDIO 0x0180
46
47 #define WM8994_NUM_DRC 3
48 #define WM8994_NUM_EQ 3
49
50 static struct {
51 unsigned int reg;
52 unsigned int mask;
53 } wm8994_vu_bits[] = {
54 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
55 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
56 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
57 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
58 { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
59 { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
60 { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
61 { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
62 { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
63 { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
64
65 { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
66 { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
67 { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
68 { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
69 { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
70 { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
71 { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
72 { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
73 { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
74 { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
75 { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
76 { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
77 { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
78 { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
79 { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
80 { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
81 };
82
83 static int wm8994_drc_base[] = {
84 WM8994_AIF1_DRC1_1,
85 WM8994_AIF1_DRC2_1,
86 WM8994_AIF2_DRC_1,
87 };
88
89 static int wm8994_retune_mobile_base[] = {
90 WM8994_AIF1_DAC1_EQ_GAINS_1,
91 WM8994_AIF1_DAC2_EQ_GAINS_1,
92 WM8994_AIF2_EQ_GAINS_1,
93 };
94
95 static const struct wm8958_micd_rate micdet_rates[] = {
96 { 32768, true, 1, 4 },
97 { 32768, false, 1, 1 },
98 { 44100 * 256, true, 7, 10 },
99 { 44100 * 256, false, 7, 10 },
100 };
101
102 static const struct wm8958_micd_rate jackdet_rates[] = {
103 { 32768, true, 0, 1 },
104 { 32768, false, 0, 1 },
105 { 44100 * 256, true, 10, 10 },
106 { 44100 * 256, false, 7, 8 },
107 };
108
109 static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
110 {
111 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
112 struct wm8994 *control = wm8994->wm8994;
113 int best, i, sysclk, val;
114 bool idle;
115 const struct wm8958_micd_rate *rates;
116 int num_rates;
117
118 idle = !wm8994->jack_mic;
119
120 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
121 if (sysclk & WM8994_SYSCLK_SRC)
122 sysclk = wm8994->aifclk[1];
123 else
124 sysclk = wm8994->aifclk[0];
125
126 if (control->pdata.micd_rates) {
127 rates = control->pdata.micd_rates;
128 num_rates = control->pdata.num_micd_rates;
129 } else if (wm8994->jackdet) {
130 rates = jackdet_rates;
131 num_rates = ARRAY_SIZE(jackdet_rates);
132 } else {
133 rates = micdet_rates;
134 num_rates = ARRAY_SIZE(micdet_rates);
135 }
136
137 best = 0;
138 for (i = 0; i < num_rates; i++) {
139 if (rates[i].idle != idle)
140 continue;
141 if (abs(rates[i].sysclk - sysclk) <
142 abs(rates[best].sysclk - sysclk))
143 best = i;
144 else if (rates[best].idle != idle)
145 best = i;
146 }
147
148 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
149 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
150
151 dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n",
152 rates[best].start, rates[best].rate, sysclk,
153 idle ? "idle" : "active");
154
155 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
156 WM8958_MICD_BIAS_STARTTIME_MASK |
157 WM8958_MICD_RATE_MASK, val);
158 }
159
160 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
161 {
162 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
163 int rate;
164 int reg1 = 0;
165 int offset;
166
167 if (aif)
168 offset = 4;
169 else
170 offset = 0;
171
172 switch (wm8994->sysclk[aif]) {
173 case WM8994_SYSCLK_MCLK1:
174 rate = wm8994->mclk[0];
175 break;
176
177 case WM8994_SYSCLK_MCLK2:
178 reg1 |= 0x8;
179 rate = wm8994->mclk[1];
180 break;
181
182 case WM8994_SYSCLK_FLL1:
183 reg1 |= 0x10;
184 rate = wm8994->fll[0].out;
185 break;
186
187 case WM8994_SYSCLK_FLL2:
188 reg1 |= 0x18;
189 rate = wm8994->fll[1].out;
190 break;
191
192 default:
193 return -EINVAL;
194 }
195
196 if (rate >= 13500000) {
197 rate /= 2;
198 reg1 |= WM8994_AIF1CLK_DIV;
199
200 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
201 aif + 1, rate);
202 }
203
204 wm8994->aifclk[aif] = rate;
205
206 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
207 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
208 reg1);
209
210 return 0;
211 }
212
213 static int configure_clock(struct snd_soc_codec *codec)
214 {
215 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
216 int change, new;
217
218 /* Bring up the AIF clocks first */
219 configure_aif_clock(codec, 0);
220 configure_aif_clock(codec, 1);
221
222 /* Then switch CLK_SYS over to the higher of them; a change
223 * can only happen as a result of a clocking change which can
224 * only be made outside of DAPM so we can safely redo the
225 * clocking.
226 */
227
228 /* If they're equal it doesn't matter which is used */
229 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
230 wm8958_micd_set_rate(codec);
231 return 0;
232 }
233
234 if (wm8994->aifclk[0] < wm8994->aifclk[1])
235 new = WM8994_SYSCLK_SRC;
236 else
237 new = 0;
238
239 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
240 WM8994_SYSCLK_SRC, new);
241 if (change)
242 snd_soc_dapm_sync(&codec->dapm);
243
244 wm8958_micd_set_rate(codec);
245
246 return 0;
247 }
248
249 static int check_clk_sys(struct snd_soc_dapm_widget *source,
250 struct snd_soc_dapm_widget *sink)
251 {
252 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
253 const char *clk;
254
255 /* Check what we're currently using for CLK_SYS */
256 if (reg & WM8994_SYSCLK_SRC)
257 clk = "AIF2CLK";
258 else
259 clk = "AIF1CLK";
260
261 return strcmp(source->name, clk) == 0;
262 }
263
264 static const char *sidetone_hpf_text[] = {
265 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
266 };
267
268 static const struct soc_enum sidetone_hpf =
269 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
270
271 static const char *adc_hpf_text[] = {
272 "HiFi", "Voice 1", "Voice 2", "Voice 3"
273 };
274
275 static const struct soc_enum aif1adc1_hpf =
276 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
277
278 static const struct soc_enum aif1adc2_hpf =
279 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
280
281 static const struct soc_enum aif2adc_hpf =
282 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
283
284 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
285 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
286 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
287 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
288 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
289 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
290 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
291
292 #define WM8994_DRC_SWITCH(xname, reg, shift) \
293 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
294 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
295 .put = wm8994_put_drc_sw, \
296 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
297
298 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
299 struct snd_ctl_elem_value *ucontrol)
300 {
301 struct soc_mixer_control *mc =
302 (struct soc_mixer_control *)kcontrol->private_value;
303 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
304 int mask, ret;
305
306 /* Can't enable both ADC and DAC paths simultaneously */
307 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
308 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
309 WM8994_AIF1ADC1R_DRC_ENA_MASK;
310 else
311 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
312
313 ret = snd_soc_read(codec, mc->reg);
314 if (ret < 0)
315 return ret;
316 if (ret & mask)
317 return -EINVAL;
318
319 return snd_soc_put_volsw(kcontrol, ucontrol);
320 }
321
322 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
323 {
324 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
325 struct wm8994 *control = wm8994->wm8994;
326 struct wm8994_pdata *pdata = &control->pdata;
327 int base = wm8994_drc_base[drc];
328 int cfg = wm8994->drc_cfg[drc];
329 int save, i;
330
331 /* Save any enables; the configuration should clear them. */
332 save = snd_soc_read(codec, base);
333 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
334 WM8994_AIF1ADC1R_DRC_ENA;
335
336 for (i = 0; i < WM8994_DRC_REGS; i++)
337 snd_soc_update_bits(codec, base + i, 0xffff,
338 pdata->drc_cfgs[cfg].regs[i]);
339
340 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
341 WM8994_AIF1ADC1L_DRC_ENA |
342 WM8994_AIF1ADC1R_DRC_ENA, save);
343 }
344
345 /* Icky as hell but saves code duplication */
346 static int wm8994_get_drc(const char *name)
347 {
348 if (strcmp(name, "AIF1DRC1 Mode") == 0)
349 return 0;
350 if (strcmp(name, "AIF1DRC2 Mode") == 0)
351 return 1;
352 if (strcmp(name, "AIF2DRC Mode") == 0)
353 return 2;
354 return -EINVAL;
355 }
356
357 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
358 struct snd_ctl_elem_value *ucontrol)
359 {
360 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
361 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
362 struct wm8994 *control = wm8994->wm8994;
363 struct wm8994_pdata *pdata = &control->pdata;
364 int drc = wm8994_get_drc(kcontrol->id.name);
365 int value = ucontrol->value.integer.value[0];
366
367 if (drc < 0)
368 return drc;
369
370 if (value >= pdata->num_drc_cfgs)
371 return -EINVAL;
372
373 wm8994->drc_cfg[drc] = value;
374
375 wm8994_set_drc(codec, drc);
376
377 return 0;
378 }
379
380 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
381 struct snd_ctl_elem_value *ucontrol)
382 {
383 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
384 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
385 int drc = wm8994_get_drc(kcontrol->id.name);
386
387 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
388
389 return 0;
390 }
391
392 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
393 {
394 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
395 struct wm8994 *control = wm8994->wm8994;
396 struct wm8994_pdata *pdata = &control->pdata;
397 int base = wm8994_retune_mobile_base[block];
398 int iface, best, best_val, save, i, cfg;
399
400 if (!pdata || !wm8994->num_retune_mobile_texts)
401 return;
402
403 switch (block) {
404 case 0:
405 case 1:
406 iface = 0;
407 break;
408 case 2:
409 iface = 1;
410 break;
411 default:
412 return;
413 }
414
415 /* Find the version of the currently selected configuration
416 * with the nearest sample rate. */
417 cfg = wm8994->retune_mobile_cfg[block];
418 best = 0;
419 best_val = INT_MAX;
420 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
421 if (strcmp(pdata->retune_mobile_cfgs[i].name,
422 wm8994->retune_mobile_texts[cfg]) == 0 &&
423 abs(pdata->retune_mobile_cfgs[i].rate
424 - wm8994->dac_rates[iface]) < best_val) {
425 best = i;
426 best_val = abs(pdata->retune_mobile_cfgs[i].rate
427 - wm8994->dac_rates[iface]);
428 }
429 }
430
431 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
432 block,
433 pdata->retune_mobile_cfgs[best].name,
434 pdata->retune_mobile_cfgs[best].rate,
435 wm8994->dac_rates[iface]);
436
437 /* The EQ will be disabled while reconfiguring it, remember the
438 * current configuration.
439 */
440 save = snd_soc_read(codec, base);
441 save &= WM8994_AIF1DAC1_EQ_ENA;
442
443 for (i = 0; i < WM8994_EQ_REGS; i++)
444 snd_soc_update_bits(codec, base + i, 0xffff,
445 pdata->retune_mobile_cfgs[best].regs[i]);
446
447 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
448 }
449
450 /* Icky as hell but saves code duplication */
451 static int wm8994_get_retune_mobile_block(const char *name)
452 {
453 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
454 return 0;
455 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
456 return 1;
457 if (strcmp(name, "AIF2 EQ Mode") == 0)
458 return 2;
459 return -EINVAL;
460 }
461
462 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
463 struct snd_ctl_elem_value *ucontrol)
464 {
465 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
466 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
467 struct wm8994 *control = wm8994->wm8994;
468 struct wm8994_pdata *pdata = &control->pdata;
469 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
470 int value = ucontrol->value.integer.value[0];
471
472 if (block < 0)
473 return block;
474
475 if (value >= pdata->num_retune_mobile_cfgs)
476 return -EINVAL;
477
478 wm8994->retune_mobile_cfg[block] = value;
479
480 wm8994_set_retune_mobile(codec, block);
481
482 return 0;
483 }
484
485 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
486 struct snd_ctl_elem_value *ucontrol)
487 {
488 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
489 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
490 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
491
492 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
493
494 return 0;
495 }
496
497 static const char *aif_chan_src_text[] = {
498 "Left", "Right"
499 };
500
501 static const struct soc_enum aif1adcl_src =
502 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
503
504 static const struct soc_enum aif1adcr_src =
505 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
506
507 static const struct soc_enum aif2adcl_src =
508 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
509
510 static const struct soc_enum aif2adcr_src =
511 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
512
513 static const struct soc_enum aif1dacl_src =
514 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
515
516 static const struct soc_enum aif1dacr_src =
517 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
518
519 static const struct soc_enum aif2dacl_src =
520 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
521
522 static const struct soc_enum aif2dacr_src =
523 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
524
525 static const char *osr_text[] = {
526 "Low Power", "High Performance",
527 };
528
529 static const struct soc_enum dac_osr =
530 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
531
532 static const struct soc_enum adc_osr =
533 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
534
535 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
536 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
537 WM8994_AIF1_ADC1_RIGHT_VOLUME,
538 1, 119, 0, digital_tlv),
539 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
540 WM8994_AIF1_ADC2_RIGHT_VOLUME,
541 1, 119, 0, digital_tlv),
542 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
543 WM8994_AIF2_ADC_RIGHT_VOLUME,
544 1, 119, 0, digital_tlv),
545
546 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
547 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
548 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
549 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
550
551 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
552 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
553 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
554 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
555
556 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
557 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
558 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
559 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
560 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
561 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
562
563 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
564 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
565
566 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
567 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
568 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
569
570 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
571 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
572 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
573
574 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
575 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
576 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
577
578 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
579 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
580 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
581
582 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
583 5, 12, 0, st_tlv),
584 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
585 0, 12, 0, st_tlv),
586 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
587 5, 12, 0, st_tlv),
588 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
589 0, 12, 0, st_tlv),
590 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
591 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
592
593 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
594 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
595
596 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
597 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
598
599 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
600 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
601
602 SOC_ENUM("ADC OSR", adc_osr),
603 SOC_ENUM("DAC OSR", dac_osr),
604
605 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
606 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
607 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
608 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
609
610 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
611 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
612 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
613 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
614
615 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
616 6, 1, 1, wm_hubs_spkmix_tlv),
617 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
618 2, 1, 1, wm_hubs_spkmix_tlv),
619
620 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
621 6, 1, 1, wm_hubs_spkmix_tlv),
622 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
623 2, 1, 1, wm_hubs_spkmix_tlv),
624
625 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
626 10, 15, 0, wm8994_3d_tlv),
627 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
628 8, 1, 0),
629 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
630 10, 15, 0, wm8994_3d_tlv),
631 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
632 8, 1, 0),
633 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
634 10, 15, 0, wm8994_3d_tlv),
635 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
636 8, 1, 0),
637 };
638
639 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
640 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
641 eq_tlv),
642 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
643 eq_tlv),
644 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
645 eq_tlv),
646 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
647 eq_tlv),
648 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
649 eq_tlv),
650
651 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
652 eq_tlv),
653 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
654 eq_tlv),
655 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
656 eq_tlv),
657 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
658 eq_tlv),
659 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
660 eq_tlv),
661
662 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
663 eq_tlv),
664 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
665 eq_tlv),
666 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
667 eq_tlv),
668 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
669 eq_tlv),
670 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
671 eq_tlv),
672 };
673
674 static const struct snd_kcontrol_new wm8994_drc_controls[] = {
675 SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5,
676 WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
677 WM8994_AIF1ADC1R_DRC_ENA),
678 SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5,
679 WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA |
680 WM8994_AIF1ADC2R_DRC_ENA),
681 SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5,
682 WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA |
683 WM8994_AIF2ADCR_DRC_ENA),
684 };
685
686 static const char *wm8958_ng_text[] = {
687 "30ms", "125ms", "250ms", "500ms",
688 };
689
690 static const struct soc_enum wm8958_aif1dac1_ng_hold =
691 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
692 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
693
694 static const struct soc_enum wm8958_aif1dac2_ng_hold =
695 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
696 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
697
698 static const struct soc_enum wm8958_aif2dac_ng_hold =
699 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
700 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
701
702 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
703 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
704
705 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
706 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
707 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
708 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
709 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
710 7, 1, ng_tlv),
711
712 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
713 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
714 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
715 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
716 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
717 7, 1, ng_tlv),
718
719 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
720 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
721 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
722 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
723 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
724 7, 1, ng_tlv),
725 };
726
727 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
728 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
729 mixin_boost_tlv),
730 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
731 mixin_boost_tlv),
732 };
733
734 /* We run all mode setting through a function to enforce audio mode */
735 static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
736 {
737 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
738
739 if (!wm8994->jackdet || !wm8994->micdet[0].jack)
740 return;
741
742 if (wm8994->active_refcount)
743 mode = WM1811_JACKDET_MODE_AUDIO;
744
745 if (mode == wm8994->jackdet_mode)
746 return;
747
748 wm8994->jackdet_mode = mode;
749
750 /* Always use audio mode to detect while the system is active */
751 if (mode != WM1811_JACKDET_MODE_NONE)
752 mode = WM1811_JACKDET_MODE_AUDIO;
753
754 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
755 WM1811_JACKDET_MODE_MASK, mode);
756 }
757
758 static void active_reference(struct snd_soc_codec *codec)
759 {
760 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
761
762 mutex_lock(&wm8994->accdet_lock);
763
764 wm8994->active_refcount++;
765
766 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
767 wm8994->active_refcount);
768
769 /* If we're using jack detection go into audio mode */
770 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
771
772 mutex_unlock(&wm8994->accdet_lock);
773 }
774
775 static void active_dereference(struct snd_soc_codec *codec)
776 {
777 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
778 u16 mode;
779
780 mutex_lock(&wm8994->accdet_lock);
781
782 wm8994->active_refcount--;
783
784 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
785 wm8994->active_refcount);
786
787 if (wm8994->active_refcount == 0) {
788 /* Go into appropriate detection only mode */
789 if (wm8994->jack_mic || wm8994->mic_detecting)
790 mode = WM1811_JACKDET_MODE_MIC;
791 else
792 mode = WM1811_JACKDET_MODE_JACK;
793
794 wm1811_jackdet_set_mode(codec, mode);
795 }
796
797 mutex_unlock(&wm8994->accdet_lock);
798 }
799
800 static int clk_sys_event(struct snd_soc_dapm_widget *w,
801 struct snd_kcontrol *kcontrol, int event)
802 {
803 struct snd_soc_codec *codec = w->codec;
804 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
805
806 switch (event) {
807 case SND_SOC_DAPM_PRE_PMU:
808 return configure_clock(codec);
809
810 case SND_SOC_DAPM_POST_PMU:
811 /*
812 * JACKDET won't run until we start the clock and it
813 * only reports deltas, make sure we notify the state
814 * up the stack on startup. Use a *very* generous
815 * timeout for paranoia, there's no urgency and we
816 * don't want false reports.
817 */
818 if (wm8994->jackdet && !wm8994->clk_has_run) {
819 schedule_delayed_work(&wm8994->jackdet_bootstrap,
820 msecs_to_jiffies(1000));
821 wm8994->clk_has_run = true;
822 }
823 break;
824
825 case SND_SOC_DAPM_POST_PMD:
826 configure_clock(codec);
827 break;
828 }
829
830 return 0;
831 }
832
833 static void vmid_reference(struct snd_soc_codec *codec)
834 {
835 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
836
837 pm_runtime_get_sync(codec->dev);
838
839 wm8994->vmid_refcount++;
840
841 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
842 wm8994->vmid_refcount);
843
844 if (wm8994->vmid_refcount == 1) {
845 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
846 WM8994_LINEOUT1_DISCH |
847 WM8994_LINEOUT2_DISCH, 0);
848
849 wm_hubs_vmid_ena(codec);
850
851 switch (wm8994->vmid_mode) {
852 default:
853 WARN_ON(NULL == "Invalid VMID mode");
854 case WM8994_VMID_NORMAL:
855 /* Startup bias, VMID ramp & buffer */
856 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
857 WM8994_BIAS_SRC |
858 WM8994_VMID_DISCH |
859 WM8994_STARTUP_BIAS_ENA |
860 WM8994_VMID_BUF_ENA |
861 WM8994_VMID_RAMP_MASK,
862 WM8994_BIAS_SRC |
863 WM8994_STARTUP_BIAS_ENA |
864 WM8994_VMID_BUF_ENA |
865 (0x2 << WM8994_VMID_RAMP_SHIFT));
866
867 /* Main bias enable, VMID=2x40k */
868 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
869 WM8994_BIAS_ENA |
870 WM8994_VMID_SEL_MASK,
871 WM8994_BIAS_ENA | 0x2);
872
873 msleep(300);
874
875 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
876 WM8994_VMID_RAMP_MASK |
877 WM8994_BIAS_SRC,
878 0);
879 break;
880
881 case WM8994_VMID_FORCE:
882 /* Startup bias, slow VMID ramp & buffer */
883 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
884 WM8994_BIAS_SRC |
885 WM8994_VMID_DISCH |
886 WM8994_STARTUP_BIAS_ENA |
887 WM8994_VMID_BUF_ENA |
888 WM8994_VMID_RAMP_MASK,
889 WM8994_BIAS_SRC |
890 WM8994_STARTUP_BIAS_ENA |
891 WM8994_VMID_BUF_ENA |
892 (0x2 << WM8994_VMID_RAMP_SHIFT));
893
894 /* Main bias enable, VMID=2x40k */
895 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
896 WM8994_BIAS_ENA |
897 WM8994_VMID_SEL_MASK,
898 WM8994_BIAS_ENA | 0x2);
899
900 msleep(400);
901
902 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
903 WM8994_VMID_RAMP_MASK |
904 WM8994_BIAS_SRC,
905 0);
906 break;
907 }
908 }
909 }
910
911 static void vmid_dereference(struct snd_soc_codec *codec)
912 {
913 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
914
915 wm8994->vmid_refcount--;
916
917 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
918 wm8994->vmid_refcount);
919
920 if (wm8994->vmid_refcount == 0) {
921 if (wm8994->hubs.lineout1_se)
922 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
923 WM8994_LINEOUT1N_ENA |
924 WM8994_LINEOUT1P_ENA,
925 WM8994_LINEOUT1N_ENA |
926 WM8994_LINEOUT1P_ENA);
927
928 if (wm8994->hubs.lineout2_se)
929 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
930 WM8994_LINEOUT2N_ENA |
931 WM8994_LINEOUT2P_ENA,
932 WM8994_LINEOUT2N_ENA |
933 WM8994_LINEOUT2P_ENA);
934
935 /* Start discharging VMID */
936 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
937 WM8994_BIAS_SRC |
938 WM8994_VMID_DISCH,
939 WM8994_BIAS_SRC |
940 WM8994_VMID_DISCH);
941
942 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
943 WM8994_VMID_SEL_MASK, 0);
944
945 msleep(400);
946
947 /* Active discharge */
948 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
949 WM8994_LINEOUT1_DISCH |
950 WM8994_LINEOUT2_DISCH,
951 WM8994_LINEOUT1_DISCH |
952 WM8994_LINEOUT2_DISCH);
953
954 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
955 WM8994_LINEOUT1N_ENA |
956 WM8994_LINEOUT1P_ENA |
957 WM8994_LINEOUT2N_ENA |
958 WM8994_LINEOUT2P_ENA, 0);
959
960 /* Switch off startup biases */
961 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
962 WM8994_BIAS_SRC |
963 WM8994_STARTUP_BIAS_ENA |
964 WM8994_VMID_BUF_ENA |
965 WM8994_VMID_RAMP_MASK, 0);
966
967 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
968 WM8994_VMID_SEL_MASK, 0);
969 }
970
971 pm_runtime_put(codec->dev);
972 }
973
974 static int vmid_event(struct snd_soc_dapm_widget *w,
975 struct snd_kcontrol *kcontrol, int event)
976 {
977 struct snd_soc_codec *codec = w->codec;
978
979 switch (event) {
980 case SND_SOC_DAPM_PRE_PMU:
981 vmid_reference(codec);
982 break;
983
984 case SND_SOC_DAPM_POST_PMD:
985 vmid_dereference(codec);
986 break;
987 }
988
989 return 0;
990 }
991
992 static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec)
993 {
994 int source = 0; /* GCC flow analysis can't track enable */
995 int reg, reg_r;
996
997 /* We also need the same AIF source for L/R and only one path */
998 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
999 switch (reg) {
1000 case WM8994_AIF2DACL_TO_DAC1L:
1001 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
1002 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1003 break;
1004 case WM8994_AIF1DAC2L_TO_DAC1L:
1005 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
1006 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1007 break;
1008 case WM8994_AIF1DAC1L_TO_DAC1L:
1009 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
1010 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1011 break;
1012 default:
1013 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
1014 return false;
1015 }
1016
1017 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1018 if (reg_r != reg) {
1019 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
1020 return false;
1021 }
1022
1023 /* Set the source up */
1024 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1025 WM8994_CP_DYN_SRC_SEL_MASK, source);
1026
1027 return true;
1028 }
1029
1030 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1031 struct snd_kcontrol *kcontrol, int event)
1032 {
1033 struct snd_soc_codec *codec = w->codec;
1034 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1035 struct wm8994 *control = codec->control_data;
1036 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
1037 int i;
1038 int dac;
1039 int adc;
1040 int val;
1041
1042 switch (control->type) {
1043 case WM8994:
1044 case WM8958:
1045 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1046 break;
1047 default:
1048 break;
1049 }
1050
1051 switch (event) {
1052 case SND_SOC_DAPM_PRE_PMU:
1053 /* Don't enable timeslot 2 if not in use */
1054 if (wm8994->channels[0] <= 2)
1055 mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
1056
1057 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
1058 if ((val & WM8994_AIF1ADCL_SRC) &&
1059 (val & WM8994_AIF1ADCR_SRC))
1060 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1061 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1062 !(val & WM8994_AIF1ADCR_SRC))
1063 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1064 else
1065 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1066 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1067
1068 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
1069 if ((val & WM8994_AIF1DACL_SRC) &&
1070 (val & WM8994_AIF1DACR_SRC))
1071 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1072 else if (!(val & WM8994_AIF1DACL_SRC) &&
1073 !(val & WM8994_AIF1DACR_SRC))
1074 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1075 else
1076 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1077 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1078
1079 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1080 mask, adc);
1081 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1082 mask, dac);
1083 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1084 WM8994_AIF1DSPCLK_ENA |
1085 WM8994_SYSDSPCLK_ENA,
1086 WM8994_AIF1DSPCLK_ENA |
1087 WM8994_SYSDSPCLK_ENA);
1088 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
1089 WM8994_AIF1ADC1R_ENA |
1090 WM8994_AIF1ADC1L_ENA |
1091 WM8994_AIF1ADC2R_ENA |
1092 WM8994_AIF1ADC2L_ENA);
1093 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
1094 WM8994_AIF1DAC1R_ENA |
1095 WM8994_AIF1DAC1L_ENA |
1096 WM8994_AIF1DAC2R_ENA |
1097 WM8994_AIF1DAC2L_ENA);
1098 break;
1099
1100 case SND_SOC_DAPM_POST_PMU:
1101 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1102 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1103 snd_soc_read(codec,
1104 wm8994_vu_bits[i].reg));
1105 break;
1106
1107 case SND_SOC_DAPM_PRE_PMD:
1108 case SND_SOC_DAPM_POST_PMD:
1109 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1110 mask, 0);
1111 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1112 mask, 0);
1113
1114 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1115 if (val & WM8994_AIF2DSPCLK_ENA)
1116 val = WM8994_SYSDSPCLK_ENA;
1117 else
1118 val = 0;
1119 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1120 WM8994_SYSDSPCLK_ENA |
1121 WM8994_AIF1DSPCLK_ENA, val);
1122 break;
1123 }
1124
1125 return 0;
1126 }
1127
1128 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1129 struct snd_kcontrol *kcontrol, int event)
1130 {
1131 struct snd_soc_codec *codec = w->codec;
1132 int i;
1133 int dac;
1134 int adc;
1135 int val;
1136
1137 switch (event) {
1138 case SND_SOC_DAPM_PRE_PMU:
1139 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1140 if ((val & WM8994_AIF2ADCL_SRC) &&
1141 (val & WM8994_AIF2ADCR_SRC))
1142 adc = WM8994_AIF2ADCR_ENA;
1143 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1144 !(val & WM8994_AIF2ADCR_SRC))
1145 adc = WM8994_AIF2ADCL_ENA;
1146 else
1147 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1148
1149
1150 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1151 if ((val & WM8994_AIF2DACL_SRC) &&
1152 (val & WM8994_AIF2DACR_SRC))
1153 dac = WM8994_AIF2DACR_ENA;
1154 else if (!(val & WM8994_AIF2DACL_SRC) &&
1155 !(val & WM8994_AIF2DACR_SRC))
1156 dac = WM8994_AIF2DACL_ENA;
1157 else
1158 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1159
1160 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1161 WM8994_AIF2ADCL_ENA |
1162 WM8994_AIF2ADCR_ENA, adc);
1163 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1164 WM8994_AIF2DACL_ENA |
1165 WM8994_AIF2DACR_ENA, dac);
1166 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1167 WM8994_AIF2DSPCLK_ENA |
1168 WM8994_SYSDSPCLK_ENA,
1169 WM8994_AIF2DSPCLK_ENA |
1170 WM8994_SYSDSPCLK_ENA);
1171 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1172 WM8994_AIF2ADCL_ENA |
1173 WM8994_AIF2ADCR_ENA,
1174 WM8994_AIF2ADCL_ENA |
1175 WM8994_AIF2ADCR_ENA);
1176 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1177 WM8994_AIF2DACL_ENA |
1178 WM8994_AIF2DACR_ENA,
1179 WM8994_AIF2DACL_ENA |
1180 WM8994_AIF2DACR_ENA);
1181 break;
1182
1183 case SND_SOC_DAPM_POST_PMU:
1184 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1185 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1186 snd_soc_read(codec,
1187 wm8994_vu_bits[i].reg));
1188 break;
1189
1190 case SND_SOC_DAPM_PRE_PMD:
1191 case SND_SOC_DAPM_POST_PMD:
1192 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1193 WM8994_AIF2DACL_ENA |
1194 WM8994_AIF2DACR_ENA, 0);
1195 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1196 WM8994_AIF2ADCL_ENA |
1197 WM8994_AIF2ADCR_ENA, 0);
1198
1199 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1200 if (val & WM8994_AIF1DSPCLK_ENA)
1201 val = WM8994_SYSDSPCLK_ENA;
1202 else
1203 val = 0;
1204 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1205 WM8994_SYSDSPCLK_ENA |
1206 WM8994_AIF2DSPCLK_ENA, val);
1207 break;
1208 }
1209
1210 return 0;
1211 }
1212
1213 static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1214 struct snd_kcontrol *kcontrol, int event)
1215 {
1216 struct snd_soc_codec *codec = w->codec;
1217 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1218
1219 switch (event) {
1220 case SND_SOC_DAPM_PRE_PMU:
1221 wm8994->aif1clk_enable = 1;
1222 break;
1223 case SND_SOC_DAPM_POST_PMD:
1224 wm8994->aif1clk_disable = 1;
1225 break;
1226 }
1227
1228 return 0;
1229 }
1230
1231 static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1232 struct snd_kcontrol *kcontrol, int event)
1233 {
1234 struct snd_soc_codec *codec = w->codec;
1235 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1236
1237 switch (event) {
1238 case SND_SOC_DAPM_PRE_PMU:
1239 wm8994->aif2clk_enable = 1;
1240 break;
1241 case SND_SOC_DAPM_POST_PMD:
1242 wm8994->aif2clk_disable = 1;
1243 break;
1244 }
1245
1246 return 0;
1247 }
1248
1249 static int late_enable_ev(struct snd_soc_dapm_widget *w,
1250 struct snd_kcontrol *kcontrol, int event)
1251 {
1252 struct snd_soc_codec *codec = w->codec;
1253 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1254
1255 switch (event) {
1256 case SND_SOC_DAPM_PRE_PMU:
1257 if (wm8994->aif1clk_enable) {
1258 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1259 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1260 WM8994_AIF1CLK_ENA_MASK,
1261 WM8994_AIF1CLK_ENA);
1262 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1263 wm8994->aif1clk_enable = 0;
1264 }
1265 if (wm8994->aif2clk_enable) {
1266 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1267 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1268 WM8994_AIF2CLK_ENA_MASK,
1269 WM8994_AIF2CLK_ENA);
1270 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1271 wm8994->aif2clk_enable = 0;
1272 }
1273 break;
1274 }
1275
1276 /* We may also have postponed startup of DSP, handle that. */
1277 wm8958_aif_ev(w, kcontrol, event);
1278
1279 return 0;
1280 }
1281
1282 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1283 struct snd_kcontrol *kcontrol, int event)
1284 {
1285 struct snd_soc_codec *codec = w->codec;
1286 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1287
1288 switch (event) {
1289 case SND_SOC_DAPM_POST_PMD:
1290 if (wm8994->aif1clk_disable) {
1291 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1292 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1293 WM8994_AIF1CLK_ENA_MASK, 0);
1294 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1295 wm8994->aif1clk_disable = 0;
1296 }
1297 if (wm8994->aif2clk_disable) {
1298 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1299 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1300 WM8994_AIF2CLK_ENA_MASK, 0);
1301 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1302 wm8994->aif2clk_disable = 0;
1303 }
1304 break;
1305 }
1306
1307 return 0;
1308 }
1309
1310 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1311 struct snd_kcontrol *kcontrol, int event)
1312 {
1313 late_enable_ev(w, kcontrol, event);
1314 return 0;
1315 }
1316
1317 static int micbias_ev(struct snd_soc_dapm_widget *w,
1318 struct snd_kcontrol *kcontrol, int event)
1319 {
1320 late_enable_ev(w, kcontrol, event);
1321 return 0;
1322 }
1323
1324 static int dac_ev(struct snd_soc_dapm_widget *w,
1325 struct snd_kcontrol *kcontrol, int event)
1326 {
1327 struct snd_soc_codec *codec = w->codec;
1328 unsigned int mask = 1 << w->shift;
1329
1330 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1331 mask, mask);
1332 return 0;
1333 }
1334
1335 static const char *adc_mux_text[] = {
1336 "ADC",
1337 "DMIC",
1338 };
1339
1340 static const struct soc_enum adc_enum =
1341 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1342
1343 static const struct snd_kcontrol_new adcl_mux =
1344 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1345
1346 static const struct snd_kcontrol_new adcr_mux =
1347 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1348
1349 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1350 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1351 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1352 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1353 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1354 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1355 };
1356
1357 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1358 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1359 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1360 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1361 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1362 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1363 };
1364
1365 /* Debugging; dump chip status after DAPM transitions */
1366 static int post_ev(struct snd_soc_dapm_widget *w,
1367 struct snd_kcontrol *kcontrol, int event)
1368 {
1369 struct snd_soc_codec *codec = w->codec;
1370 dev_dbg(codec->dev, "SRC status: %x\n",
1371 snd_soc_read(codec,
1372 WM8994_RATE_STATUS));
1373 return 0;
1374 }
1375
1376 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1377 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1378 1, 1, 0),
1379 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1380 0, 1, 0),
1381 };
1382
1383 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1384 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1385 1, 1, 0),
1386 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1387 0, 1, 0),
1388 };
1389
1390 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1391 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1392 1, 1, 0),
1393 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1394 0, 1, 0),
1395 };
1396
1397 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1398 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1399 1, 1, 0),
1400 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1401 0, 1, 0),
1402 };
1403
1404 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1405 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1406 5, 1, 0),
1407 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1408 4, 1, 0),
1409 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1410 2, 1, 0),
1411 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1412 1, 1, 0),
1413 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1414 0, 1, 0),
1415 };
1416
1417 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1418 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1419 5, 1, 0),
1420 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1421 4, 1, 0),
1422 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1423 2, 1, 0),
1424 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1425 1, 1, 0),
1426 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1427 0, 1, 0),
1428 };
1429
1430 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1431 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1432 .info = snd_soc_info_volsw, \
1433 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1434 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1435
1436 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1437 struct snd_ctl_elem_value *ucontrol)
1438 {
1439 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1440 struct snd_soc_dapm_widget *w = wlist->widgets[0];
1441 struct snd_soc_codec *codec = w->codec;
1442 int ret;
1443
1444 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1445
1446 wm_hubs_update_class_w(codec);
1447
1448 return ret;
1449 }
1450
1451 static const struct snd_kcontrol_new dac1l_mix[] = {
1452 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1453 5, 1, 0),
1454 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1455 4, 1, 0),
1456 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1457 2, 1, 0),
1458 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1459 1, 1, 0),
1460 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1461 0, 1, 0),
1462 };
1463
1464 static const struct snd_kcontrol_new dac1r_mix[] = {
1465 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1466 5, 1, 0),
1467 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1468 4, 1, 0),
1469 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1470 2, 1, 0),
1471 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1472 1, 1, 0),
1473 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1474 0, 1, 0),
1475 };
1476
1477 static const char *sidetone_text[] = {
1478 "ADC/DMIC1", "DMIC2",
1479 };
1480
1481 static const struct soc_enum sidetone1_enum =
1482 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1483
1484 static const struct snd_kcontrol_new sidetone1_mux =
1485 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1486
1487 static const struct soc_enum sidetone2_enum =
1488 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1489
1490 static const struct snd_kcontrol_new sidetone2_mux =
1491 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1492
1493 static const char *aif1dac_text[] = {
1494 "AIF1DACDAT", "AIF3DACDAT",
1495 };
1496
1497 static const struct soc_enum aif1dac_enum =
1498 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1499
1500 static const struct snd_kcontrol_new aif1dac_mux =
1501 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1502
1503 static const char *aif2dac_text[] = {
1504 "AIF2DACDAT", "AIF3DACDAT",
1505 };
1506
1507 static const struct soc_enum aif2dac_enum =
1508 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1509
1510 static const struct snd_kcontrol_new aif2dac_mux =
1511 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1512
1513 static const char *aif2adc_text[] = {
1514 "AIF2ADCDAT", "AIF3DACDAT",
1515 };
1516
1517 static const struct soc_enum aif2adc_enum =
1518 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1519
1520 static const struct snd_kcontrol_new aif2adc_mux =
1521 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1522
1523 static const char *aif3adc_text[] = {
1524 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1525 };
1526
1527 static const struct soc_enum wm8994_aif3adc_enum =
1528 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1529
1530 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1531 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1532
1533 static const struct soc_enum wm8958_aif3adc_enum =
1534 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1535
1536 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1537 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1538
1539 static const char *mono_pcm_out_text[] = {
1540 "None", "AIF2ADCL", "AIF2ADCR",
1541 };
1542
1543 static const struct soc_enum mono_pcm_out_enum =
1544 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1545
1546 static const struct snd_kcontrol_new mono_pcm_out_mux =
1547 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1548
1549 static const char *aif2dac_src_text[] = {
1550 "AIF2", "AIF3",
1551 };
1552
1553 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1554 static const struct soc_enum aif2dacl_src_enum =
1555 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1556
1557 static const struct snd_kcontrol_new aif2dacl_src_mux =
1558 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1559
1560 static const struct soc_enum aif2dacr_src_enum =
1561 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1562
1563 static const struct snd_kcontrol_new aif2dacr_src_mux =
1564 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1565
1566 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1567 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
1568 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1569 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
1570 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1571
1572 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1573 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1574 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1575 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1576 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1577 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1578 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1579 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1580 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1581 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1582
1583 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1584 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1585 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1586 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1587 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1588 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1589 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
1590 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1591 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
1592 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1593
1594 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1595 };
1596
1597 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1598 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
1599 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1600 SND_SOC_DAPM_PRE_PMD),
1601 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
1602 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1603 SND_SOC_DAPM_PRE_PMD),
1604 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1605 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1606 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1607 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1608 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1609 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1610 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
1611 };
1612
1613 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1614 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1615 dac_ev, SND_SOC_DAPM_PRE_PMU),
1616 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1617 dac_ev, SND_SOC_DAPM_PRE_PMU),
1618 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1619 dac_ev, SND_SOC_DAPM_PRE_PMU),
1620 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1621 dac_ev, SND_SOC_DAPM_PRE_PMU),
1622 };
1623
1624 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1625 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1626 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1627 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1628 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1629 };
1630
1631 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1632 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1633 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1634 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1635 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1636 };
1637
1638 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1639 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1640 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1641 };
1642
1643 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1644 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1645 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1646 SND_SOC_DAPM_INPUT("Clock"),
1647
1648 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1649 SND_SOC_DAPM_PRE_PMU),
1650 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1651 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1652
1653 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1654 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1655 SND_SOC_DAPM_PRE_PMD),
1656
1657 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1658 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1659 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
1660
1661 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1662 0, SND_SOC_NOPM, 9, 0),
1663 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1664 0, SND_SOC_NOPM, 8, 0),
1665 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1666 SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
1667 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1668 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1669 SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
1670 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1671
1672 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1673 0, SND_SOC_NOPM, 11, 0),
1674 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1675 0, SND_SOC_NOPM, 10, 0),
1676 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1677 SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
1678 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1679 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1680 SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
1681 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1682
1683 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1684 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1685 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1686 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1687
1688 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1689 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1690 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1691 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1692
1693 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1694 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1695 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1696 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1697
1698 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1699 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1700
1701 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1702 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1703 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1704 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1705
1706 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1707 SND_SOC_NOPM, 13, 0),
1708 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1709 SND_SOC_NOPM, 12, 0),
1710 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1711 SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
1712 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1713 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1714 SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
1715 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1716
1717 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1718 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1719 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1720 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1721
1722 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1723 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1724 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1725
1726 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1727 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1728
1729 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1730
1731 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1732 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1733 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1734 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1735
1736 /* Power is done with the muxes since the ADC power also controls the
1737 * downsampling chain, the chip will automatically manage the analogue
1738 * specific portions.
1739 */
1740 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1741 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1742
1743 SND_SOC_DAPM_POST("Debug log", post_ev),
1744 };
1745
1746 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1747 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1748 };
1749
1750 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1751 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
1752 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1753 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1754 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1755 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1756 };
1757
1758 static const struct snd_soc_dapm_route intercon[] = {
1759 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1760 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1761
1762 { "DSP1CLK", NULL, "CLK_SYS" },
1763 { "DSP2CLK", NULL, "CLK_SYS" },
1764 { "DSPINTCLK", NULL, "CLK_SYS" },
1765
1766 { "AIF1ADC1L", NULL, "AIF1CLK" },
1767 { "AIF1ADC1L", NULL, "DSP1CLK" },
1768 { "AIF1ADC1R", NULL, "AIF1CLK" },
1769 { "AIF1ADC1R", NULL, "DSP1CLK" },
1770 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1771
1772 { "AIF1DAC1L", NULL, "AIF1CLK" },
1773 { "AIF1DAC1L", NULL, "DSP1CLK" },
1774 { "AIF1DAC1R", NULL, "AIF1CLK" },
1775 { "AIF1DAC1R", NULL, "DSP1CLK" },
1776 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1777
1778 { "AIF1ADC2L", NULL, "AIF1CLK" },
1779 { "AIF1ADC2L", NULL, "DSP1CLK" },
1780 { "AIF1ADC2R", NULL, "AIF1CLK" },
1781 { "AIF1ADC2R", NULL, "DSP1CLK" },
1782 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1783
1784 { "AIF1DAC2L", NULL, "AIF1CLK" },
1785 { "AIF1DAC2L", NULL, "DSP1CLK" },
1786 { "AIF1DAC2R", NULL, "AIF1CLK" },
1787 { "AIF1DAC2R", NULL, "DSP1CLK" },
1788 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1789
1790 { "AIF2ADCL", NULL, "AIF2CLK" },
1791 { "AIF2ADCL", NULL, "DSP2CLK" },
1792 { "AIF2ADCR", NULL, "AIF2CLK" },
1793 { "AIF2ADCR", NULL, "DSP2CLK" },
1794 { "AIF2ADCR", NULL, "DSPINTCLK" },
1795
1796 { "AIF2DACL", NULL, "AIF2CLK" },
1797 { "AIF2DACL", NULL, "DSP2CLK" },
1798 { "AIF2DACR", NULL, "AIF2CLK" },
1799 { "AIF2DACR", NULL, "DSP2CLK" },
1800 { "AIF2DACR", NULL, "DSPINTCLK" },
1801
1802 { "DMIC1L", NULL, "DMIC1DAT" },
1803 { "DMIC1L", NULL, "CLK_SYS" },
1804 { "DMIC1R", NULL, "DMIC1DAT" },
1805 { "DMIC1R", NULL, "CLK_SYS" },
1806 { "DMIC2L", NULL, "DMIC2DAT" },
1807 { "DMIC2L", NULL, "CLK_SYS" },
1808 { "DMIC2R", NULL, "DMIC2DAT" },
1809 { "DMIC2R", NULL, "CLK_SYS" },
1810
1811 { "ADCL", NULL, "AIF1CLK" },
1812 { "ADCL", NULL, "DSP1CLK" },
1813 { "ADCL", NULL, "DSPINTCLK" },
1814
1815 { "ADCR", NULL, "AIF1CLK" },
1816 { "ADCR", NULL, "DSP1CLK" },
1817 { "ADCR", NULL, "DSPINTCLK" },
1818
1819 { "ADCL Mux", "ADC", "ADCL" },
1820 { "ADCL Mux", "DMIC", "DMIC1L" },
1821 { "ADCR Mux", "ADC", "ADCR" },
1822 { "ADCR Mux", "DMIC", "DMIC1R" },
1823
1824 { "DAC1L", NULL, "AIF1CLK" },
1825 { "DAC1L", NULL, "DSP1CLK" },
1826 { "DAC1L", NULL, "DSPINTCLK" },
1827
1828 { "DAC1R", NULL, "AIF1CLK" },
1829 { "DAC1R", NULL, "DSP1CLK" },
1830 { "DAC1R", NULL, "DSPINTCLK" },
1831
1832 { "DAC2L", NULL, "AIF2CLK" },
1833 { "DAC2L", NULL, "DSP2CLK" },
1834 { "DAC2L", NULL, "DSPINTCLK" },
1835
1836 { "DAC2R", NULL, "AIF2DACR" },
1837 { "DAC2R", NULL, "AIF2CLK" },
1838 { "DAC2R", NULL, "DSP2CLK" },
1839 { "DAC2R", NULL, "DSPINTCLK" },
1840
1841 { "TOCLK", NULL, "CLK_SYS" },
1842
1843 { "AIF1DACDAT", NULL, "AIF1 Playback" },
1844 { "AIF2DACDAT", NULL, "AIF2 Playback" },
1845 { "AIF3DACDAT", NULL, "AIF3 Playback" },
1846
1847 { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1848 { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1849 { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1850
1851 /* AIF1 outputs */
1852 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1853 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1854 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1855
1856 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1857 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1858 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1859
1860 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1861 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1862 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1863
1864 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1865 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1866 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1867
1868 /* Pin level routing for AIF3 */
1869 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1870 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1871 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1872 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1873
1874 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1875 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1876 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1877 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1878 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1879 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1880 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1881
1882 /* DAC1 inputs */
1883 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1884 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1885 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1886 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1887 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1888
1889 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1890 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1891 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1892 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1893 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1894
1895 /* DAC2/AIF2 outputs */
1896 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1897 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1898 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1899 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1900 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1901 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1902
1903 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1904 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1905 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1906 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1907 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1908 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1909
1910 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1911 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1912 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1913 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1914
1915 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1916
1917 /* AIF3 output */
1918 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1919 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1920 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1921 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1922 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1923 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1924 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1925 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1926
1927 /* Sidetone */
1928 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1929 { "Left Sidetone", "DMIC2", "DMIC2L" },
1930 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1931 { "Right Sidetone", "DMIC2", "DMIC2R" },
1932
1933 /* Output stages */
1934 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1935 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1936
1937 { "SPKL", "DAC1 Switch", "DAC1L" },
1938 { "SPKL", "DAC2 Switch", "DAC2L" },
1939
1940 { "SPKR", "DAC1 Switch", "DAC1R" },
1941 { "SPKR", "DAC2 Switch", "DAC2R" },
1942
1943 { "Left Headphone Mux", "DAC", "DAC1L" },
1944 { "Right Headphone Mux", "DAC", "DAC1R" },
1945 };
1946
1947 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1948 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1949 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1950 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1951 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1952 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1953 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1954 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1955 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1956 };
1957
1958 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1959 { "DAC1L", NULL, "DAC1L Mixer" },
1960 { "DAC1R", NULL, "DAC1R Mixer" },
1961 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1962 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1963 };
1964
1965 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1966 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1967 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1968 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1969 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1970 { "MICBIAS1", NULL, "CLK_SYS" },
1971 { "MICBIAS1", NULL, "MICBIAS Supply" },
1972 { "MICBIAS2", NULL, "CLK_SYS" },
1973 { "MICBIAS2", NULL, "MICBIAS Supply" },
1974 };
1975
1976 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1977 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1978 { "AIF2DACR", NULL, "AIF2DAC Mux" },
1979 { "MICBIAS1", NULL, "VMID" },
1980 { "MICBIAS2", NULL, "VMID" },
1981 };
1982
1983 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1984 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1985 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1986
1987 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1988 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1989 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1990 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1991
1992 { "AIF3DACDAT", NULL, "AIF3" },
1993 { "AIF3ADCDAT", NULL, "AIF3" },
1994
1995 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1996 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1997
1998 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1999 };
2000
2001 /* The size in bits of the FLL divide multiplied by 10
2002 * to allow rounding later */
2003 #define FIXED_FLL_SIZE ((1 << 16) * 10)
2004
2005 struct fll_div {
2006 u16 outdiv;
2007 u16 n;
2008 u16 k;
2009 u16 lambda;
2010 u16 clk_ref_div;
2011 u16 fll_fratio;
2012 };
2013
2014 static int wm8994_get_fll_config(struct wm8994 *control, struct fll_div *fll,
2015 int freq_in, int freq_out)
2016 {
2017 u64 Kpart;
2018 unsigned int K, Ndiv, Nmod, gcd_fll;
2019
2020 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2021
2022 /* Scale the input frequency down to <= 13.5MHz */
2023 fll->clk_ref_div = 0;
2024 while (freq_in > 13500000) {
2025 fll->clk_ref_div++;
2026 freq_in /= 2;
2027
2028 if (fll->clk_ref_div > 3)
2029 return -EINVAL;
2030 }
2031 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2032
2033 /* Scale the output to give 90MHz<=Fvco<=100MHz */
2034 fll->outdiv = 3;
2035 while (freq_out * (fll->outdiv + 1) < 90000000) {
2036 fll->outdiv++;
2037 if (fll->outdiv > 63)
2038 return -EINVAL;
2039 }
2040 freq_out *= fll->outdiv + 1;
2041 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2042
2043 if (freq_in > 1000000) {
2044 fll->fll_fratio = 0;
2045 } else if (freq_in > 256000) {
2046 fll->fll_fratio = 1;
2047 freq_in *= 2;
2048 } else if (freq_in > 128000) {
2049 fll->fll_fratio = 2;
2050 freq_in *= 4;
2051 } else if (freq_in > 64000) {
2052 fll->fll_fratio = 3;
2053 freq_in *= 8;
2054 } else {
2055 fll->fll_fratio = 4;
2056 freq_in *= 16;
2057 }
2058 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2059
2060 /* Now, calculate N.K */
2061 Ndiv = freq_out / freq_in;
2062
2063 fll->n = Ndiv;
2064 Nmod = freq_out % freq_in;
2065 pr_debug("Nmod=%d\n", Nmod);
2066
2067 switch (control->type) {
2068 case WM8994:
2069 /* Calculate fractional part - scale up so we can round. */
2070 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
2071
2072 do_div(Kpart, freq_in);
2073
2074 K = Kpart & 0xFFFFFFFF;
2075
2076 if ((K % 10) >= 5)
2077 K += 5;
2078
2079 /* Move down to proper range now rounding is done */
2080 fll->k = K / 10;
2081
2082 pr_debug("N=%x K=%x\n", fll->n, fll->k);
2083 break;
2084
2085 default:
2086 gcd_fll = gcd(freq_out, freq_in);
2087
2088 fll->k = (freq_out - (freq_in * fll->n)) / gcd_fll;
2089 fll->lambda = freq_in / gcd_fll;
2090
2091 }
2092
2093 return 0;
2094 }
2095
2096 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
2097 unsigned int freq_in, unsigned int freq_out)
2098 {
2099 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2100 struct wm8994 *control = wm8994->wm8994;
2101 int reg_offset, ret;
2102 struct fll_div fll;
2103 u16 reg, clk1, aif_reg, aif_src;
2104 unsigned long timeout;
2105 bool was_enabled;
2106
2107 switch (id) {
2108 case WM8994_FLL1:
2109 reg_offset = 0;
2110 id = 0;
2111 aif_src = 0x10;
2112 break;
2113 case WM8994_FLL2:
2114 reg_offset = 0x20;
2115 id = 1;
2116 aif_src = 0x18;
2117 break;
2118 default:
2119 return -EINVAL;
2120 }
2121
2122 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2123 was_enabled = reg & WM8994_FLL1_ENA;
2124
2125 switch (src) {
2126 case 0:
2127 /* Allow no source specification when stopping */
2128 if (freq_out)
2129 return -EINVAL;
2130 src = wm8994->fll[id].src;
2131 break;
2132 case WM8994_FLL_SRC_MCLK1:
2133 case WM8994_FLL_SRC_MCLK2:
2134 case WM8994_FLL_SRC_LRCLK:
2135 case WM8994_FLL_SRC_BCLK:
2136 break;
2137 case WM8994_FLL_SRC_INTERNAL:
2138 freq_in = 12000000;
2139 freq_out = 12000000;
2140 break;
2141 default:
2142 return -EINVAL;
2143 }
2144
2145 /* Are we changing anything? */
2146 if (wm8994->fll[id].src == src &&
2147 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2148 return 0;
2149
2150 /* If we're stopping the FLL redo the old config - no
2151 * registers will actually be written but we avoid GCC flow
2152 * analysis bugs spewing warnings.
2153 */
2154 if (freq_out)
2155 ret = wm8994_get_fll_config(control, &fll, freq_in, freq_out);
2156 else
2157 ret = wm8994_get_fll_config(control, &fll, wm8994->fll[id].in,
2158 wm8994->fll[id].out);
2159 if (ret < 0)
2160 return ret;
2161
2162 /* Make sure that we're not providing SYSCLK right now */
2163 clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
2164 if (clk1 & WM8994_SYSCLK_SRC)
2165 aif_reg = WM8994_AIF2_CLOCKING_1;
2166 else
2167 aif_reg = WM8994_AIF1_CLOCKING_1;
2168 reg = snd_soc_read(codec, aif_reg);
2169
2170 if ((reg & WM8994_AIF1CLK_ENA) &&
2171 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2172 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
2173 id + 1);
2174 return -EBUSY;
2175 }
2176
2177 /* We always need to disable the FLL while reconfiguring */
2178 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2179 WM8994_FLL1_ENA, 0);
2180
2181 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
2182 freq_in == freq_out && freq_out) {
2183 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
2184 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2185 WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2186 goto out;
2187 }
2188
2189 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2190 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2191 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2192 WM8994_FLL1_OUTDIV_MASK |
2193 WM8994_FLL1_FRATIO_MASK, reg);
2194
2195 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
2196 WM8994_FLL1_K_MASK, fll.k);
2197
2198 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2199 WM8994_FLL1_N_MASK,
2200 fll.n << WM8994_FLL1_N_SHIFT);
2201
2202 if (fll.lambda) {
2203 snd_soc_update_bits(codec, WM8958_FLL1_EFS_1 + reg_offset,
2204 WM8958_FLL1_LAMBDA_MASK,
2205 fll.lambda);
2206 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset,
2207 WM8958_FLL1_EFS_ENA, WM8958_FLL1_EFS_ENA);
2208 } else {
2209 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset,
2210 WM8958_FLL1_EFS_ENA, 0);
2211 }
2212
2213 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2214 WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
2215 WM8994_FLL1_REFCLK_DIV_MASK |
2216 WM8994_FLL1_REFCLK_SRC_MASK,
2217 ((src == WM8994_FLL_SRC_INTERNAL)
2218 << WM8994_FLL1_FRC_NCO_SHIFT) |
2219 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2220 (src - 1));
2221
2222 /* Clear any pending completion from a previous failure */
2223 try_wait_for_completion(&wm8994->fll_locked[id]);
2224
2225 /* Enable (with fractional mode if required) */
2226 if (freq_out) {
2227 /* Enable VMID if we need it */
2228 if (!was_enabled) {
2229 active_reference(codec);
2230
2231 switch (control->type) {
2232 case WM8994:
2233 vmid_reference(codec);
2234 break;
2235 case WM8958:
2236 if (control->revision < 1)
2237 vmid_reference(codec);
2238 break;
2239 default:
2240 break;
2241 }
2242 }
2243
2244 reg = WM8994_FLL1_ENA;
2245
2246 if (fll.k)
2247 reg |= WM8994_FLL1_FRAC;
2248 if (src == WM8994_FLL_SRC_INTERNAL)
2249 reg |= WM8994_FLL1_OSC_ENA;
2250
2251 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2252 WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
2253 WM8994_FLL1_FRAC, reg);
2254
2255 if (wm8994->fll_locked_irq) {
2256 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2257 msecs_to_jiffies(10));
2258 if (timeout == 0)
2259 dev_warn(codec->dev,
2260 "Timed out waiting for FLL lock\n");
2261 } else {
2262 msleep(5);
2263 }
2264 } else {
2265 if (was_enabled) {
2266 switch (control->type) {
2267 case WM8994:
2268 vmid_dereference(codec);
2269 break;
2270 case WM8958:
2271 if (control->revision < 1)
2272 vmid_dereference(codec);
2273 break;
2274 default:
2275 break;
2276 }
2277
2278 active_dereference(codec);
2279 }
2280 }
2281
2282 out:
2283 wm8994->fll[id].in = freq_in;
2284 wm8994->fll[id].out = freq_out;
2285 wm8994->fll[id].src = src;
2286
2287 configure_clock(codec);
2288
2289 /*
2290 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2291 * for detection.
2292 */
2293 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2294 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2295
2296 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2297 & WM8994_AIF1CLK_RATE_MASK;
2298 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2299 & WM8994_AIF1CLK_RATE_MASK;
2300
2301 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2302 WM8994_AIF1CLK_RATE_MASK, 0x1);
2303 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2304 WM8994_AIF2CLK_RATE_MASK, 0x1);
2305 } else if (wm8994->aifdiv[0]) {
2306 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2307 WM8994_AIF1CLK_RATE_MASK,
2308 wm8994->aifdiv[0]);
2309 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2310 WM8994_AIF2CLK_RATE_MASK,
2311 wm8994->aifdiv[1]);
2312
2313 wm8994->aifdiv[0] = 0;
2314 wm8994->aifdiv[1] = 0;
2315 }
2316
2317 return 0;
2318 }
2319
2320 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2321 {
2322 struct completion *completion = data;
2323
2324 complete(completion);
2325
2326 return IRQ_HANDLED;
2327 }
2328
2329 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2330
2331 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2332 unsigned int freq_in, unsigned int freq_out)
2333 {
2334 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2335 }
2336
2337 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2338 int clk_id, unsigned int freq, int dir)
2339 {
2340 struct snd_soc_codec *codec = dai->codec;
2341 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2342 int i;
2343
2344 switch (dai->id) {
2345 case 1:
2346 case 2:
2347 break;
2348
2349 default:
2350 /* AIF3 shares clocking with AIF1/2 */
2351 return -EINVAL;
2352 }
2353
2354 switch (clk_id) {
2355 case WM8994_SYSCLK_MCLK1:
2356 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2357 wm8994->mclk[0] = freq;
2358 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2359 dai->id, freq);
2360 break;
2361
2362 case WM8994_SYSCLK_MCLK2:
2363 /* TODO: Set GPIO AF */
2364 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2365 wm8994->mclk[1] = freq;
2366 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2367 dai->id, freq);
2368 break;
2369
2370 case WM8994_SYSCLK_FLL1:
2371 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2372 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2373 break;
2374
2375 case WM8994_SYSCLK_FLL2:
2376 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2377 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2378 break;
2379
2380 case WM8994_SYSCLK_OPCLK:
2381 /* Special case - a division (times 10) is given and
2382 * no effect on main clocking.
2383 */
2384 if (freq) {
2385 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2386 if (opclk_divs[i] == freq)
2387 break;
2388 if (i == ARRAY_SIZE(opclk_divs))
2389 return -EINVAL;
2390 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2391 WM8994_OPCLK_DIV_MASK, i);
2392 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2393 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2394 } else {
2395 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2396 WM8994_OPCLK_ENA, 0);
2397 }
2398
2399 default:
2400 return -EINVAL;
2401 }
2402
2403 configure_clock(codec);
2404
2405 /*
2406 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2407 * for detection.
2408 */
2409 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2410 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2411
2412 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2413 & WM8994_AIF1CLK_RATE_MASK;
2414 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2415 & WM8994_AIF1CLK_RATE_MASK;
2416
2417 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2418 WM8994_AIF1CLK_RATE_MASK, 0x1);
2419 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2420 WM8994_AIF2CLK_RATE_MASK, 0x1);
2421 } else if (wm8994->aifdiv[0]) {
2422 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2423 WM8994_AIF1CLK_RATE_MASK,
2424 wm8994->aifdiv[0]);
2425 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2426 WM8994_AIF2CLK_RATE_MASK,
2427 wm8994->aifdiv[1]);
2428
2429 wm8994->aifdiv[0] = 0;
2430 wm8994->aifdiv[1] = 0;
2431 }
2432
2433 return 0;
2434 }
2435
2436 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2437 enum snd_soc_bias_level level)
2438 {
2439 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2440 struct wm8994 *control = wm8994->wm8994;
2441
2442 wm_hubs_set_bias_level(codec, level);
2443
2444 switch (level) {
2445 case SND_SOC_BIAS_ON:
2446 break;
2447
2448 case SND_SOC_BIAS_PREPARE:
2449 /* MICBIAS into regulating mode */
2450 switch (control->type) {
2451 case WM8958:
2452 case WM1811:
2453 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2454 WM8958_MICB1_MODE, 0);
2455 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2456 WM8958_MICB2_MODE, 0);
2457 break;
2458 default:
2459 break;
2460 }
2461
2462 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2463 active_reference(codec);
2464 break;
2465
2466 case SND_SOC_BIAS_STANDBY:
2467 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2468 switch (control->type) {
2469 case WM8958:
2470 if (control->revision == 0) {
2471 /* Optimise performance for rev A */
2472 snd_soc_update_bits(codec,
2473 WM8958_CHARGE_PUMP_2,
2474 WM8958_CP_DISCH,
2475 WM8958_CP_DISCH);
2476 }
2477 break;
2478
2479 default:
2480 break;
2481 }
2482
2483 /* Discharge LINEOUT1 & 2 */
2484 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2485 WM8994_LINEOUT1_DISCH |
2486 WM8994_LINEOUT2_DISCH,
2487 WM8994_LINEOUT1_DISCH |
2488 WM8994_LINEOUT2_DISCH);
2489 }
2490
2491 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2492 active_dereference(codec);
2493
2494 /* MICBIAS into bypass mode on newer devices */
2495 switch (control->type) {
2496 case WM8958:
2497 case WM1811:
2498 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2499 WM8958_MICB1_MODE,
2500 WM8958_MICB1_MODE);
2501 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2502 WM8958_MICB2_MODE,
2503 WM8958_MICB2_MODE);
2504 break;
2505 default:
2506 break;
2507 }
2508 break;
2509
2510 case SND_SOC_BIAS_OFF:
2511 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2512 wm8994->cur_fw = NULL;
2513 break;
2514 }
2515
2516 codec->dapm.bias_level = level;
2517
2518 return 0;
2519 }
2520
2521 int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2522 {
2523 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2524
2525 switch (mode) {
2526 case WM8994_VMID_NORMAL:
2527 if (wm8994->hubs.lineout1_se) {
2528 snd_soc_dapm_disable_pin(&codec->dapm,
2529 "LINEOUT1N Driver");
2530 snd_soc_dapm_disable_pin(&codec->dapm,
2531 "LINEOUT1P Driver");
2532 }
2533 if (wm8994->hubs.lineout2_se) {
2534 snd_soc_dapm_disable_pin(&codec->dapm,
2535 "LINEOUT2N Driver");
2536 snd_soc_dapm_disable_pin(&codec->dapm,
2537 "LINEOUT2P Driver");
2538 }
2539
2540 /* Do the sync with the old mode to allow it to clean up */
2541 snd_soc_dapm_sync(&codec->dapm);
2542 wm8994->vmid_mode = mode;
2543 break;
2544
2545 case WM8994_VMID_FORCE:
2546 if (wm8994->hubs.lineout1_se) {
2547 snd_soc_dapm_force_enable_pin(&codec->dapm,
2548 "LINEOUT1N Driver");
2549 snd_soc_dapm_force_enable_pin(&codec->dapm,
2550 "LINEOUT1P Driver");
2551 }
2552 if (wm8994->hubs.lineout2_se) {
2553 snd_soc_dapm_force_enable_pin(&codec->dapm,
2554 "LINEOUT2N Driver");
2555 snd_soc_dapm_force_enable_pin(&codec->dapm,
2556 "LINEOUT2P Driver");
2557 }
2558
2559 wm8994->vmid_mode = mode;
2560 snd_soc_dapm_sync(&codec->dapm);
2561 break;
2562
2563 default:
2564 return -EINVAL;
2565 }
2566
2567 return 0;
2568 }
2569
2570 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2571 {
2572 struct snd_soc_codec *codec = dai->codec;
2573 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2574 struct wm8994 *control = wm8994->wm8994;
2575 int ms_reg;
2576 int aif1_reg;
2577 int dac_reg;
2578 int adc_reg;
2579 int ms = 0;
2580 int aif1 = 0;
2581 int lrclk = 0;
2582
2583 switch (dai->id) {
2584 case 1:
2585 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2586 aif1_reg = WM8994_AIF1_CONTROL_1;
2587 dac_reg = WM8994_AIF1DAC_LRCLK;
2588 adc_reg = WM8994_AIF1ADC_LRCLK;
2589 break;
2590 case 2:
2591 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2592 aif1_reg = WM8994_AIF2_CONTROL_1;
2593 dac_reg = WM8994_AIF1DAC_LRCLK;
2594 adc_reg = WM8994_AIF1ADC_LRCLK;
2595 break;
2596 default:
2597 return -EINVAL;
2598 }
2599
2600 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2601 case SND_SOC_DAIFMT_CBS_CFS:
2602 break;
2603 case SND_SOC_DAIFMT_CBM_CFM:
2604 ms = WM8994_AIF1_MSTR;
2605 break;
2606 default:
2607 return -EINVAL;
2608 }
2609
2610 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2611 case SND_SOC_DAIFMT_DSP_B:
2612 aif1 |= WM8994_AIF1_LRCLK_INV;
2613 lrclk |= WM8958_AIF1_LRCLK_INV;
2614 case SND_SOC_DAIFMT_DSP_A:
2615 aif1 |= 0x18;
2616 break;
2617 case SND_SOC_DAIFMT_I2S:
2618 aif1 |= 0x10;
2619 break;
2620 case SND_SOC_DAIFMT_RIGHT_J:
2621 break;
2622 case SND_SOC_DAIFMT_LEFT_J:
2623 aif1 |= 0x8;
2624 break;
2625 default:
2626 return -EINVAL;
2627 }
2628
2629 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2630 case SND_SOC_DAIFMT_DSP_A:
2631 case SND_SOC_DAIFMT_DSP_B:
2632 /* frame inversion not valid for DSP modes */
2633 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2634 case SND_SOC_DAIFMT_NB_NF:
2635 break;
2636 case SND_SOC_DAIFMT_IB_NF:
2637 aif1 |= WM8994_AIF1_BCLK_INV;
2638 break;
2639 default:
2640 return -EINVAL;
2641 }
2642 break;
2643
2644 case SND_SOC_DAIFMT_I2S:
2645 case SND_SOC_DAIFMT_RIGHT_J:
2646 case SND_SOC_DAIFMT_LEFT_J:
2647 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2648 case SND_SOC_DAIFMT_NB_NF:
2649 break;
2650 case SND_SOC_DAIFMT_IB_IF:
2651 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2652 lrclk |= WM8958_AIF1_LRCLK_INV;
2653 break;
2654 case SND_SOC_DAIFMT_IB_NF:
2655 aif1 |= WM8994_AIF1_BCLK_INV;
2656 break;
2657 case SND_SOC_DAIFMT_NB_IF:
2658 aif1 |= WM8994_AIF1_LRCLK_INV;
2659 lrclk |= WM8958_AIF1_LRCLK_INV;
2660 break;
2661 default:
2662 return -EINVAL;
2663 }
2664 break;
2665 default:
2666 return -EINVAL;
2667 }
2668
2669 /* The AIF2 format configuration needs to be mirrored to AIF3
2670 * on WM8958 if it's in use so just do it all the time. */
2671 switch (control->type) {
2672 case WM1811:
2673 case WM8958:
2674 if (dai->id == 2)
2675 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2676 WM8994_AIF1_LRCLK_INV |
2677 WM8958_AIF3_FMT_MASK, aif1);
2678 break;
2679
2680 default:
2681 break;
2682 }
2683
2684 snd_soc_update_bits(codec, aif1_reg,
2685 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2686 WM8994_AIF1_FMT_MASK,
2687 aif1);
2688 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2689 ms);
2690 snd_soc_update_bits(codec, dac_reg,
2691 WM8958_AIF1_LRCLK_INV, lrclk);
2692 snd_soc_update_bits(codec, adc_reg,
2693 WM8958_AIF1_LRCLK_INV, lrclk);
2694
2695 return 0;
2696 }
2697
2698 static struct {
2699 int val, rate;
2700 } srs[] = {
2701 { 0, 8000 },
2702 { 1, 11025 },
2703 { 2, 12000 },
2704 { 3, 16000 },
2705 { 4, 22050 },
2706 { 5, 24000 },
2707 { 6, 32000 },
2708 { 7, 44100 },
2709 { 8, 48000 },
2710 { 9, 88200 },
2711 { 10, 96000 },
2712 };
2713
2714 static int fs_ratios[] = {
2715 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2716 };
2717
2718 static int bclk_divs[] = {
2719 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2720 640, 880, 960, 1280, 1760, 1920
2721 };
2722
2723 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2724 struct snd_pcm_hw_params *params,
2725 struct snd_soc_dai *dai)
2726 {
2727 struct snd_soc_codec *codec = dai->codec;
2728 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2729 struct wm8994 *control = wm8994->wm8994;
2730 struct wm8994_pdata *pdata = &control->pdata;
2731 int aif1_reg;
2732 int aif2_reg;
2733 int bclk_reg;
2734 int lrclk_reg;
2735 int rate_reg;
2736 int aif1 = 0;
2737 int aif2 = 0;
2738 int bclk = 0;
2739 int lrclk = 0;
2740 int rate_val = 0;
2741 int id = dai->id - 1;
2742
2743 int i, cur_val, best_val, bclk_rate, best;
2744
2745 switch (dai->id) {
2746 case 1:
2747 aif1_reg = WM8994_AIF1_CONTROL_1;
2748 aif2_reg = WM8994_AIF1_CONTROL_2;
2749 bclk_reg = WM8994_AIF1_BCLK;
2750 rate_reg = WM8994_AIF1_RATE;
2751 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2752 wm8994->lrclk_shared[0]) {
2753 lrclk_reg = WM8994_AIF1DAC_LRCLK;
2754 } else {
2755 lrclk_reg = WM8994_AIF1ADC_LRCLK;
2756 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2757 }
2758 break;
2759 case 2:
2760 aif1_reg = WM8994_AIF2_CONTROL_1;
2761 aif2_reg = WM8994_AIF2_CONTROL_2;
2762 bclk_reg = WM8994_AIF2_BCLK;
2763 rate_reg = WM8994_AIF2_RATE;
2764 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2765 wm8994->lrclk_shared[1]) {
2766 lrclk_reg = WM8994_AIF2DAC_LRCLK;
2767 } else {
2768 lrclk_reg = WM8994_AIF2ADC_LRCLK;
2769 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2770 }
2771 break;
2772 default:
2773 return -EINVAL;
2774 }
2775
2776 bclk_rate = params_rate(params);
2777 switch (params_format(params)) {
2778 case SNDRV_PCM_FORMAT_S16_LE:
2779 bclk_rate *= 16;
2780 break;
2781 case SNDRV_PCM_FORMAT_S20_3LE:
2782 bclk_rate *= 20;
2783 aif1 |= 0x20;
2784 break;
2785 case SNDRV_PCM_FORMAT_S24_LE:
2786 bclk_rate *= 24;
2787 aif1 |= 0x40;
2788 break;
2789 case SNDRV_PCM_FORMAT_S32_LE:
2790 bclk_rate *= 32;
2791 aif1 |= 0x60;
2792 break;
2793 default:
2794 return -EINVAL;
2795 }
2796
2797 wm8994->channels[id] = params_channels(params);
2798 if (pdata->max_channels_clocked[id] &&
2799 wm8994->channels[id] > pdata->max_channels_clocked[id]) {
2800 dev_dbg(dai->dev, "Constraining channels to %d from %d\n",
2801 pdata->max_channels_clocked[id], wm8994->channels[id]);
2802 wm8994->channels[id] = pdata->max_channels_clocked[id];
2803 }
2804
2805 switch (wm8994->channels[id]) {
2806 case 1:
2807 case 2:
2808 bclk_rate *= 2;
2809 break;
2810 default:
2811 bclk_rate *= 4;
2812 break;
2813 }
2814
2815 /* Try to find an appropriate sample rate; look for an exact match. */
2816 for (i = 0; i < ARRAY_SIZE(srs); i++)
2817 if (srs[i].rate == params_rate(params))
2818 break;
2819 if (i == ARRAY_SIZE(srs))
2820 return -EINVAL;
2821 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2822
2823 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2824 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2825 dai->id, wm8994->aifclk[id], bclk_rate);
2826
2827 if (wm8994->channels[id] == 1 &&
2828 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2829 aif2 |= WM8994_AIF1_MONO;
2830
2831 if (wm8994->aifclk[id] == 0) {
2832 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2833 return -EINVAL;
2834 }
2835
2836 /* AIFCLK/fs ratio; look for a close match in either direction */
2837 best = 0;
2838 best_val = abs((fs_ratios[0] * params_rate(params))
2839 - wm8994->aifclk[id]);
2840 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2841 cur_val = abs((fs_ratios[i] * params_rate(params))
2842 - wm8994->aifclk[id]);
2843 if (cur_val >= best_val)
2844 continue;
2845 best = i;
2846 best_val = cur_val;
2847 }
2848 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2849 dai->id, fs_ratios[best]);
2850 rate_val |= best;
2851
2852 /* We may not get quite the right frequency if using
2853 * approximate clocks so look for the closest match that is
2854 * higher than the target (we need to ensure that there enough
2855 * BCLKs to clock out the samples).
2856 */
2857 best = 0;
2858 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2859 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2860 if (cur_val < 0) /* BCLK table is sorted */
2861 break;
2862 best = i;
2863 }
2864 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2865 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2866 bclk_divs[best], bclk_rate);
2867 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2868
2869 lrclk = bclk_rate / params_rate(params);
2870 if (!lrclk) {
2871 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2872 bclk_rate);
2873 return -EINVAL;
2874 }
2875 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2876 lrclk, bclk_rate / lrclk);
2877
2878 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2879 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2880 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2881 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2882 lrclk);
2883 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2884 WM8994_AIF1CLK_RATE_MASK, rate_val);
2885
2886 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2887 switch (dai->id) {
2888 case 1:
2889 wm8994->dac_rates[0] = params_rate(params);
2890 wm8994_set_retune_mobile(codec, 0);
2891 wm8994_set_retune_mobile(codec, 1);
2892 break;
2893 case 2:
2894 wm8994->dac_rates[1] = params_rate(params);
2895 wm8994_set_retune_mobile(codec, 2);
2896 break;
2897 }
2898 }
2899
2900 return 0;
2901 }
2902
2903 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2904 struct snd_pcm_hw_params *params,
2905 struct snd_soc_dai *dai)
2906 {
2907 struct snd_soc_codec *codec = dai->codec;
2908 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2909 struct wm8994 *control = wm8994->wm8994;
2910 int aif1_reg;
2911 int aif1 = 0;
2912
2913 switch (dai->id) {
2914 case 3:
2915 switch (control->type) {
2916 case WM1811:
2917 case WM8958:
2918 aif1_reg = WM8958_AIF3_CONTROL_1;
2919 break;
2920 default:
2921 return 0;
2922 }
2923 break;
2924 default:
2925 return 0;
2926 }
2927
2928 switch (params_format(params)) {
2929 case SNDRV_PCM_FORMAT_S16_LE:
2930 break;
2931 case SNDRV_PCM_FORMAT_S20_3LE:
2932 aif1 |= 0x20;
2933 break;
2934 case SNDRV_PCM_FORMAT_S24_LE:
2935 aif1 |= 0x40;
2936 break;
2937 case SNDRV_PCM_FORMAT_S32_LE:
2938 aif1 |= 0x60;
2939 break;
2940 default:
2941 return -EINVAL;
2942 }
2943
2944 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2945 }
2946
2947 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2948 {
2949 struct snd_soc_codec *codec = codec_dai->codec;
2950 int mute_reg;
2951 int reg;
2952
2953 switch (codec_dai->id) {
2954 case 1:
2955 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2956 break;
2957 case 2:
2958 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2959 break;
2960 default:
2961 return -EINVAL;
2962 }
2963
2964 if (mute)
2965 reg = WM8994_AIF1DAC1_MUTE;
2966 else
2967 reg = 0;
2968
2969 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2970
2971 return 0;
2972 }
2973
2974 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2975 {
2976 struct snd_soc_codec *codec = codec_dai->codec;
2977 int reg, val, mask;
2978
2979 switch (codec_dai->id) {
2980 case 1:
2981 reg = WM8994_AIF1_MASTER_SLAVE;
2982 mask = WM8994_AIF1_TRI;
2983 break;
2984 case 2:
2985 reg = WM8994_AIF2_MASTER_SLAVE;
2986 mask = WM8994_AIF2_TRI;
2987 break;
2988 default:
2989 return -EINVAL;
2990 }
2991
2992 if (tristate)
2993 val = mask;
2994 else
2995 val = 0;
2996
2997 return snd_soc_update_bits(codec, reg, mask, val);
2998 }
2999
3000 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
3001 {
3002 struct snd_soc_codec *codec = dai->codec;
3003
3004 /* Disable the pulls on the AIF if we're using it to save power. */
3005 snd_soc_update_bits(codec, WM8994_GPIO_3,
3006 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3007 snd_soc_update_bits(codec, WM8994_GPIO_4,
3008 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3009 snd_soc_update_bits(codec, WM8994_GPIO_5,
3010 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3011
3012 return 0;
3013 }
3014
3015 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
3016
3017 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3018 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
3019
3020 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
3021 .set_sysclk = wm8994_set_dai_sysclk,
3022 .set_fmt = wm8994_set_dai_fmt,
3023 .hw_params = wm8994_hw_params,
3024 .digital_mute = wm8994_aif_mute,
3025 .set_pll = wm8994_set_fll,
3026 .set_tristate = wm8994_set_tristate,
3027 };
3028
3029 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
3030 .set_sysclk = wm8994_set_dai_sysclk,
3031 .set_fmt = wm8994_set_dai_fmt,
3032 .hw_params = wm8994_hw_params,
3033 .digital_mute = wm8994_aif_mute,
3034 .set_pll = wm8994_set_fll,
3035 .set_tristate = wm8994_set_tristate,
3036 };
3037
3038 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
3039 .hw_params = wm8994_aif3_hw_params,
3040 };
3041
3042 static struct snd_soc_dai_driver wm8994_dai[] = {
3043 {
3044 .name = "wm8994-aif1",
3045 .id = 1,
3046 .playback = {
3047 .stream_name = "AIF1 Playback",
3048 .channels_min = 1,
3049 .channels_max = 2,
3050 .rates = WM8994_RATES,
3051 .formats = WM8994_FORMATS,
3052 .sig_bits = 24,
3053 },
3054 .capture = {
3055 .stream_name = "AIF1 Capture",
3056 .channels_min = 1,
3057 .channels_max = 2,
3058 .rates = WM8994_RATES,
3059 .formats = WM8994_FORMATS,
3060 .sig_bits = 24,
3061 },
3062 .ops = &wm8994_aif1_dai_ops,
3063 },
3064 {
3065 .name = "wm8994-aif2",
3066 .id = 2,
3067 .playback = {
3068 .stream_name = "AIF2 Playback",
3069 .channels_min = 1,
3070 .channels_max = 2,
3071 .rates = WM8994_RATES,
3072 .formats = WM8994_FORMATS,
3073 .sig_bits = 24,
3074 },
3075 .capture = {
3076 .stream_name = "AIF2 Capture",
3077 .channels_min = 1,
3078 .channels_max = 2,
3079 .rates = WM8994_RATES,
3080 .formats = WM8994_FORMATS,
3081 .sig_bits = 24,
3082 },
3083 .probe = wm8994_aif2_probe,
3084 .ops = &wm8994_aif2_dai_ops,
3085 },
3086 {
3087 .name = "wm8994-aif3",
3088 .id = 3,
3089 .playback = {
3090 .stream_name = "AIF3 Playback",
3091 .channels_min = 1,
3092 .channels_max = 2,
3093 .rates = WM8994_RATES,
3094 .formats = WM8994_FORMATS,
3095 .sig_bits = 24,
3096 },
3097 .capture = {
3098 .stream_name = "AIF3 Capture",
3099 .channels_min = 1,
3100 .channels_max = 2,
3101 .rates = WM8994_RATES,
3102 .formats = WM8994_FORMATS,
3103 .sig_bits = 24,
3104 },
3105 .ops = &wm8994_aif3_dai_ops,
3106 }
3107 };
3108
3109 #ifdef CONFIG_PM
3110 static int wm8994_codec_suspend(struct snd_soc_codec *codec)
3111 {
3112 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3113 int i, ret;
3114
3115 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3116 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
3117 sizeof(struct wm8994_fll_config));
3118 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
3119 if (ret < 0)
3120 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
3121 i + 1, ret);
3122 }
3123
3124 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3125
3126 return 0;
3127 }
3128
3129 static int wm8994_codec_resume(struct snd_soc_codec *codec)
3130 {
3131 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3132 struct wm8994 *control = wm8994->wm8994;
3133 int i, ret;
3134 unsigned int val, mask;
3135
3136 if (control->revision < 4) {
3137 /* force a HW read */
3138 ret = regmap_read(control->regmap,
3139 WM8994_POWER_MANAGEMENT_5, &val);
3140
3141 /* modify the cache only */
3142 codec->cache_only = 1;
3143 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
3144 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
3145 val &= mask;
3146 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
3147 mask, val);
3148 codec->cache_only = 0;
3149 }
3150
3151 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3152 if (!wm8994->fll_suspend[i].out)
3153 continue;
3154
3155 ret = _wm8994_set_fll(codec, i + 1,
3156 wm8994->fll_suspend[i].src,
3157 wm8994->fll_suspend[i].in,
3158 wm8994->fll_suspend[i].out);
3159 if (ret < 0)
3160 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
3161 i + 1, ret);
3162 }
3163
3164 return 0;
3165 }
3166 #else
3167 #define wm8994_codec_suspend NULL
3168 #define wm8994_codec_resume NULL
3169 #endif
3170
3171 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3172 {
3173 struct snd_soc_codec *codec = wm8994->hubs.codec;
3174 struct wm8994 *control = wm8994->wm8994;
3175 struct wm8994_pdata *pdata = &control->pdata;
3176 struct snd_kcontrol_new controls[] = {
3177 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3178 wm8994->retune_mobile_enum,
3179 wm8994_get_retune_mobile_enum,
3180 wm8994_put_retune_mobile_enum),
3181 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3182 wm8994->retune_mobile_enum,
3183 wm8994_get_retune_mobile_enum,
3184 wm8994_put_retune_mobile_enum),
3185 SOC_ENUM_EXT("AIF2 EQ Mode",
3186 wm8994->retune_mobile_enum,
3187 wm8994_get_retune_mobile_enum,
3188 wm8994_put_retune_mobile_enum),
3189 };
3190 int ret, i, j;
3191 const char **t;
3192
3193 /* We need an array of texts for the enum API but the number
3194 * of texts is likely to be less than the number of
3195 * configurations due to the sample rate dependency of the
3196 * configurations. */
3197 wm8994->num_retune_mobile_texts = 0;
3198 wm8994->retune_mobile_texts = NULL;
3199 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3200 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3201 if (strcmp(pdata->retune_mobile_cfgs[i].name,
3202 wm8994->retune_mobile_texts[j]) == 0)
3203 break;
3204 }
3205
3206 if (j != wm8994->num_retune_mobile_texts)
3207 continue;
3208
3209 /* Expand the array... */
3210 t = krealloc(wm8994->retune_mobile_texts,
3211 sizeof(char *) *
3212 (wm8994->num_retune_mobile_texts + 1),
3213 GFP_KERNEL);
3214 if (t == NULL)
3215 continue;
3216
3217 /* ...store the new entry... */
3218 t[wm8994->num_retune_mobile_texts] =
3219 pdata->retune_mobile_cfgs[i].name;
3220
3221 /* ...and remember the new version. */
3222 wm8994->num_retune_mobile_texts++;
3223 wm8994->retune_mobile_texts = t;
3224 }
3225
3226 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3227 wm8994->num_retune_mobile_texts);
3228
3229 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
3230 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3231
3232 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3233 ARRAY_SIZE(controls));
3234 if (ret != 0)
3235 dev_err(wm8994->hubs.codec->dev,
3236 "Failed to add ReTune Mobile controls: %d\n", ret);
3237 }
3238
3239 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3240 {
3241 struct snd_soc_codec *codec = wm8994->hubs.codec;
3242 struct wm8994 *control = wm8994->wm8994;
3243 struct wm8994_pdata *pdata = &control->pdata;
3244 int ret, i;
3245
3246 if (!pdata)
3247 return;
3248
3249 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3250 pdata->lineout2_diff,
3251 pdata->lineout1fb,
3252 pdata->lineout2fb,
3253 pdata->jd_scthr,
3254 pdata->jd_thr,
3255 pdata->micb1_delay,
3256 pdata->micb2_delay,
3257 pdata->micbias1_lvl,
3258 pdata->micbias2_lvl);
3259
3260 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3261
3262 if (pdata->num_drc_cfgs) {
3263 struct snd_kcontrol_new controls[] = {
3264 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3265 wm8994_get_drc_enum, wm8994_put_drc_enum),
3266 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3267 wm8994_get_drc_enum, wm8994_put_drc_enum),
3268 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3269 wm8994_get_drc_enum, wm8994_put_drc_enum),
3270 };
3271
3272 /* We need an array of texts for the enum API */
3273 wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev,
3274 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
3275 if (!wm8994->drc_texts) {
3276 dev_err(wm8994->hubs.codec->dev,
3277 "Failed to allocate %d DRC config texts\n",
3278 pdata->num_drc_cfgs);
3279 return;
3280 }
3281
3282 for (i = 0; i < pdata->num_drc_cfgs; i++)
3283 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3284
3285 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3286 wm8994->drc_enum.texts = wm8994->drc_texts;
3287
3288 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3289 ARRAY_SIZE(controls));
3290 for (i = 0; i < WM8994_NUM_DRC; i++)
3291 wm8994_set_drc(codec, i);
3292 } else {
3293 ret = snd_soc_add_codec_controls(wm8994->hubs.codec,
3294 wm8994_drc_controls,
3295 ARRAY_SIZE(wm8994_drc_controls));
3296 }
3297
3298 if (ret != 0)
3299 dev_err(wm8994->hubs.codec->dev,
3300 "Failed to add DRC mode controls: %d\n", ret);
3301
3302
3303 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3304 pdata->num_retune_mobile_cfgs);
3305
3306 if (pdata->num_retune_mobile_cfgs)
3307 wm8994_handle_retune_mobile_pdata(wm8994);
3308 else
3309 snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls,
3310 ARRAY_SIZE(wm8994_eq_controls));
3311
3312 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3313 if (pdata->micbias[i]) {
3314 snd_soc_write(codec, WM8958_MICBIAS1 + i,
3315 pdata->micbias[i] & 0xffff);
3316 }
3317 }
3318 }
3319
3320 /**
3321 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3322 *
3323 * @codec: WM8994 codec
3324 * @jack: jack to report detection events on
3325 * @micbias: microphone bias to detect on
3326 *
3327 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3328 * being used to bring out signals to the processor then only platform
3329 * data configuration is needed for WM8994 and processor GPIOs should
3330 * be configured using snd_soc_jack_add_gpios() instead.
3331 *
3332 * Configuration of detection levels is available via the micbias1_lvl
3333 * and micbias2_lvl platform data members.
3334 */
3335 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3336 int micbias)
3337 {
3338 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3339 struct wm8994_micdet *micdet;
3340 struct wm8994 *control = wm8994->wm8994;
3341 int reg, ret;
3342
3343 if (control->type != WM8994) {
3344 dev_warn(codec->dev, "Not a WM8994\n");
3345 return -EINVAL;
3346 }
3347
3348 switch (micbias) {
3349 case 1:
3350 micdet = &wm8994->micdet[0];
3351 if (jack)
3352 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3353 "MICBIAS1");
3354 else
3355 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3356 "MICBIAS1");
3357 break;
3358 case 2:
3359 micdet = &wm8994->micdet[1];
3360 if (jack)
3361 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3362 "MICBIAS1");
3363 else
3364 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3365 "MICBIAS1");
3366 break;
3367 default:
3368 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
3369 return -EINVAL;
3370 }
3371
3372 if (ret != 0)
3373 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3374 micbias, ret);
3375
3376 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3377 micbias, jack);
3378
3379 /* Store the configuration */
3380 micdet->jack = jack;
3381 micdet->detecting = true;
3382
3383 /* If either of the jacks is set up then enable detection */
3384 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3385 reg = WM8994_MICD_ENA;
3386 else
3387 reg = 0;
3388
3389 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3390
3391 /* enable MICDET and MICSHRT deboune */
3392 snd_soc_update_bits(codec, WM8994_IRQ_DEBOUNCE,
3393 WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK |
3394 WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK,
3395 WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB);
3396
3397 snd_soc_dapm_sync(&codec->dapm);
3398
3399 return 0;
3400 }
3401 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3402
3403 static void wm8994_mic_work(struct work_struct *work)
3404 {
3405 struct wm8994_priv *priv = container_of(work,
3406 struct wm8994_priv,
3407 mic_work.work);
3408 struct regmap *regmap = priv->wm8994->regmap;
3409 struct device *dev = priv->wm8994->dev;
3410 unsigned int reg;
3411 int ret;
3412 int report;
3413
3414 pm_runtime_get_sync(dev);
3415
3416 ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, &reg);
3417 if (ret < 0) {
3418 dev_err(dev, "Failed to read microphone status: %d\n",
3419 ret);
3420 pm_runtime_put(dev);
3421 return;
3422 }
3423
3424 dev_dbg(dev, "Microphone status: %x\n", reg);
3425
3426 report = 0;
3427 if (reg & WM8994_MIC1_DET_STS) {
3428 if (priv->micdet[0].detecting)
3429 report = SND_JACK_HEADSET;
3430 }
3431 if (reg & WM8994_MIC1_SHRT_STS) {
3432 if (priv->micdet[0].detecting)
3433 report = SND_JACK_HEADPHONE;
3434 else
3435 report |= SND_JACK_BTN_0;
3436 }
3437 if (report)
3438 priv->micdet[0].detecting = false;
3439 else
3440 priv->micdet[0].detecting = true;
3441
3442 snd_soc_jack_report(priv->micdet[0].jack, report,
3443 SND_JACK_HEADSET | SND_JACK_BTN_0);
3444
3445 report = 0;
3446 if (reg & WM8994_MIC2_DET_STS) {
3447 if (priv->micdet[1].detecting)
3448 report = SND_JACK_HEADSET;
3449 }
3450 if (reg & WM8994_MIC2_SHRT_STS) {
3451 if (priv->micdet[1].detecting)
3452 report = SND_JACK_HEADPHONE;
3453 else
3454 report |= SND_JACK_BTN_0;
3455 }
3456 if (report)
3457 priv->micdet[1].detecting = false;
3458 else
3459 priv->micdet[1].detecting = true;
3460
3461 snd_soc_jack_report(priv->micdet[1].jack, report,
3462 SND_JACK_HEADSET | SND_JACK_BTN_0);
3463
3464 pm_runtime_put(dev);
3465 }
3466
3467 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3468 {
3469 struct wm8994_priv *priv = data;
3470 struct snd_soc_codec *codec = priv->hubs.codec;
3471
3472 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3473 trace_snd_soc_jack_irq(dev_name(codec->dev));
3474 #endif
3475
3476 pm_wakeup_event(codec->dev, 300);
3477
3478 schedule_delayed_work(&priv->mic_work, msecs_to_jiffies(250));
3479
3480 return IRQ_HANDLED;
3481 }
3482
3483 static void wm1811_micd_stop(struct snd_soc_codec *codec)
3484 {
3485 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3486
3487 if (!wm8994->jackdet)
3488 return;
3489
3490 mutex_lock(&wm8994->accdet_lock);
3491
3492 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0);
3493
3494 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3495
3496 mutex_unlock(&wm8994->accdet_lock);
3497
3498 if (wm8994->wm8994->pdata.jd_ext_cap)
3499 snd_soc_dapm_disable_pin(&codec->dapm,
3500 "MICBIAS2");
3501 }
3502
3503 static void wm8958_button_det(struct snd_soc_codec *codec, u16 status)
3504 {
3505 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3506 int report;
3507
3508 report = 0;
3509 if (status & 0x4)
3510 report |= SND_JACK_BTN_0;
3511
3512 if (status & 0x8)
3513 report |= SND_JACK_BTN_1;
3514
3515 if (status & 0x10)
3516 report |= SND_JACK_BTN_2;
3517
3518 if (status & 0x20)
3519 report |= SND_JACK_BTN_3;
3520
3521 if (status & 0x40)
3522 report |= SND_JACK_BTN_4;
3523
3524 if (status & 0x80)
3525 report |= SND_JACK_BTN_5;
3526
3527 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3528 wm8994->btn_mask);
3529 }
3530
3531 static void wm8958_mic_id(void *data, u16 status)
3532 {
3533 struct snd_soc_codec *codec = data;
3534 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3535
3536 /* Either nothing present or just starting detection */
3537 if (!(status & WM8958_MICD_STS)) {
3538 /* If nothing present then clear our statuses */
3539 dev_dbg(codec->dev, "Detected open circuit\n");
3540 wm8994->jack_mic = false;
3541 wm8994->mic_detecting = true;
3542
3543 wm1811_micd_stop(codec);
3544
3545 wm8958_micd_set_rate(codec);
3546
3547 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3548 wm8994->btn_mask |
3549 SND_JACK_HEADSET);
3550 return;
3551 }
3552
3553 /* If the measurement is showing a high impedence we've got a
3554 * microphone.
3555 */
3556 if (status & 0x600) {
3557 dev_dbg(codec->dev, "Detected microphone\n");
3558
3559 wm8994->mic_detecting = false;
3560 wm8994->jack_mic = true;
3561
3562 wm8958_micd_set_rate(codec);
3563
3564 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3565 SND_JACK_HEADSET);
3566 }
3567
3568
3569 if (status & 0xfc) {
3570 dev_dbg(codec->dev, "Detected headphone\n");
3571 wm8994->mic_detecting = false;
3572
3573 wm8958_micd_set_rate(codec);
3574
3575 /* If we have jackdet that will detect removal */
3576 wm1811_micd_stop(codec);
3577
3578 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3579 SND_JACK_HEADSET);
3580 }
3581 }
3582
3583 /* Deferred mic detection to allow for extra settling time */
3584 static void wm1811_mic_work(struct work_struct *work)
3585 {
3586 struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv,
3587 mic_work.work);
3588 struct wm8994 *control = wm8994->wm8994;
3589 struct snd_soc_codec *codec = wm8994->hubs.codec;
3590
3591 pm_runtime_get_sync(codec->dev);
3592
3593 /* If required for an external cap force MICBIAS on */
3594 if (control->pdata.jd_ext_cap) {
3595 snd_soc_dapm_force_enable_pin(&codec->dapm,
3596 "MICBIAS2");
3597 snd_soc_dapm_sync(&codec->dapm);
3598 }
3599
3600 mutex_lock(&wm8994->accdet_lock);
3601
3602 dev_dbg(codec->dev, "Starting mic detection\n");
3603
3604 /* Use a user-supplied callback if we have one */
3605 if (wm8994->micd_cb) {
3606 wm8994->micd_cb(wm8994->micd_cb_data);
3607 } else {
3608 /*
3609 * Start off measument of microphone impedence to find out
3610 * what's actually there.
3611 */
3612 wm8994->mic_detecting = true;
3613 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3614
3615 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3616 WM8958_MICD_ENA, WM8958_MICD_ENA);
3617 }
3618
3619 mutex_unlock(&wm8994->accdet_lock);
3620
3621 pm_runtime_put(codec->dev);
3622 }
3623
3624 static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3625 {
3626 struct wm8994_priv *wm8994 = data;
3627 struct wm8994 *control = wm8994->wm8994;
3628 struct snd_soc_codec *codec = wm8994->hubs.codec;
3629 int reg, delay;
3630 bool present;
3631
3632 pm_runtime_get_sync(codec->dev);
3633
3634 mutex_lock(&wm8994->accdet_lock);
3635
3636 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3637 if (reg < 0) {
3638 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3639 mutex_unlock(&wm8994->accdet_lock);
3640 pm_runtime_put(codec->dev);
3641 return IRQ_NONE;
3642 }
3643
3644 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3645
3646 present = reg & WM1811_JACKDET_LVL;
3647
3648 if (present) {
3649 dev_dbg(codec->dev, "Jack detected\n");
3650
3651 wm8958_micd_set_rate(codec);
3652
3653 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3654 WM8958_MICB2_DISCH, 0);
3655
3656 /* Disable debounce while inserted */
3657 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3658 WM1811_JACKDET_DB, 0);
3659
3660 delay = control->pdata.micdet_delay;
3661 schedule_delayed_work(&wm8994->mic_work,
3662 msecs_to_jiffies(delay));
3663 } else {
3664 dev_dbg(codec->dev, "Jack not detected\n");
3665
3666 cancel_delayed_work_sync(&wm8994->mic_work);
3667
3668 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3669 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3670
3671 /* Enable debounce while removed */
3672 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3673 WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3674
3675 wm8994->mic_detecting = false;
3676 wm8994->jack_mic = false;
3677 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3678 WM8958_MICD_ENA, 0);
3679 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3680 }
3681
3682 mutex_unlock(&wm8994->accdet_lock);
3683
3684 /* Turn off MICBIAS if it was on for an external cap */
3685 if (control->pdata.jd_ext_cap && !present)
3686 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
3687
3688 if (present)
3689 snd_soc_jack_report(wm8994->micdet[0].jack,
3690 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3691 else
3692 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3693 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3694 wm8994->btn_mask);
3695
3696 /* Since we only report deltas force an update, ensures we
3697 * avoid bootstrapping issues with the core. */
3698 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0);
3699
3700 pm_runtime_put(codec->dev);
3701 return IRQ_HANDLED;
3702 }
3703
3704 static void wm1811_jackdet_bootstrap(struct work_struct *work)
3705 {
3706 struct wm8994_priv *wm8994 = container_of(work,
3707 struct wm8994_priv,
3708 jackdet_bootstrap.work);
3709 wm1811_jackdet_irq(0, wm8994);
3710 }
3711
3712 /**
3713 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3714 *
3715 * @codec: WM8958 codec
3716 * @jack: jack to report detection events on
3717 *
3718 * Enable microphone detection functionality for the WM8958. By
3719 * default simple detection which supports the detection of up to 6
3720 * buttons plus video and microphone functionality is supported.
3721 *
3722 * The WM8958 has an advanced jack detection facility which is able to
3723 * support complex accessory detection, especially when used in
3724 * conjunction with external circuitry. In order to provide maximum
3725 * flexiblity a callback is provided which allows a completely custom
3726 * detection algorithm.
3727 */
3728 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3729 wm1811_micdet_cb det_cb, void *det_cb_data,
3730 wm1811_mic_id_cb id_cb, void *id_cb_data)
3731 {
3732 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3733 struct wm8994 *control = wm8994->wm8994;
3734 u16 micd_lvl_sel;
3735
3736 switch (control->type) {
3737 case WM1811:
3738 case WM8958:
3739 break;
3740 default:
3741 return -EINVAL;
3742 }
3743
3744 if (jack) {
3745 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3746 snd_soc_dapm_sync(&codec->dapm);
3747
3748 wm8994->micdet[0].jack = jack;
3749
3750 if (det_cb) {
3751 wm8994->micd_cb = det_cb;
3752 wm8994->micd_cb_data = det_cb_data;
3753 } else {
3754 wm8994->mic_detecting = true;
3755 wm8994->jack_mic = false;
3756 }
3757
3758 if (id_cb) {
3759 wm8994->mic_id_cb = id_cb;
3760 wm8994->mic_id_cb_data = id_cb_data;
3761 } else {
3762 wm8994->mic_id_cb = wm8958_mic_id;
3763 wm8994->mic_id_cb_data = codec;
3764 }
3765
3766 wm8958_micd_set_rate(codec);
3767
3768 /* Detect microphones and short circuits by default */
3769 if (control->pdata.micd_lvl_sel)
3770 micd_lvl_sel = control->pdata.micd_lvl_sel;
3771 else
3772 micd_lvl_sel = 0x41;
3773
3774 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3775 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3776 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3777
3778 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
3779 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3780
3781 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3782
3783 /*
3784 * If we can use jack detection start off with that,
3785 * otherwise jump straight to microphone detection.
3786 */
3787 if (wm8994->jackdet) {
3788 /* Disable debounce for the initial detect */
3789 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3790 WM1811_JACKDET_DB, 0);
3791
3792 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3793 WM8958_MICB2_DISCH,
3794 WM8958_MICB2_DISCH);
3795 snd_soc_update_bits(codec, WM8994_LDO_1,
3796 WM8994_LDO1_DISCH, 0);
3797 wm1811_jackdet_set_mode(codec,
3798 WM1811_JACKDET_MODE_JACK);
3799 } else {
3800 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3801 WM8958_MICD_ENA, WM8958_MICD_ENA);
3802 }
3803
3804 } else {
3805 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3806 WM8958_MICD_ENA, 0);
3807 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
3808 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
3809 snd_soc_dapm_sync(&codec->dapm);
3810 }
3811
3812 return 0;
3813 }
3814 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3815
3816 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3817 {
3818 struct wm8994_priv *wm8994 = data;
3819 struct snd_soc_codec *codec = wm8994->hubs.codec;
3820 int reg, count, ret;
3821
3822 /*
3823 * Jack detection may have detected a removal simulataneously
3824 * with an update of the MICDET status; if so it will have
3825 * stopped detection and we can ignore this interrupt.
3826 */
3827 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
3828 return IRQ_HANDLED;
3829
3830 pm_runtime_get_sync(codec->dev);
3831
3832 /* We may occasionally read a detection without an impedence
3833 * range being provided - if that happens loop again.
3834 */
3835 count = 10;
3836 do {
3837 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3838 if (reg < 0) {
3839 dev_err(codec->dev,
3840 "Failed to read mic detect status: %d\n",
3841 reg);
3842 pm_runtime_put(codec->dev);
3843 return IRQ_NONE;
3844 }
3845
3846 if (!(reg & WM8958_MICD_VALID)) {
3847 dev_dbg(codec->dev, "Mic detect data not valid\n");
3848 goto out;
3849 }
3850
3851 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3852 break;
3853
3854 msleep(1);
3855 } while (count--);
3856
3857 if (count == 0)
3858 dev_warn(codec->dev, "No impedance range reported for jack\n");
3859
3860 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3861 trace_snd_soc_jack_irq(dev_name(codec->dev));
3862 #endif
3863
3864 /* Avoid a transient report when the accessory is being removed */
3865 if (wm8994->jackdet) {
3866 ret = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3867 if (ret < 0) {
3868 dev_err(codec->dev, "Failed to read jack status: %d\n",
3869 ret);
3870 } else if (!(ret & WM1811_JACKDET_LVL)) {
3871 dev_dbg(codec->dev, "Ignoring removed jack\n");
3872 return IRQ_HANDLED;
3873 }
3874 }
3875
3876 if (wm8994->mic_detecting)
3877 wm8994->mic_id_cb(wm8994->mic_id_cb_data, reg);
3878 else
3879 wm8958_button_det(codec, reg);
3880
3881 out:
3882 pm_runtime_put(codec->dev);
3883 return IRQ_HANDLED;
3884 }
3885
3886 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3887 {
3888 struct snd_soc_codec *codec = data;
3889
3890 dev_err(codec->dev, "FIFO error\n");
3891
3892 return IRQ_HANDLED;
3893 }
3894
3895 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3896 {
3897 struct snd_soc_codec *codec = data;
3898
3899 dev_err(codec->dev, "Thermal warning\n");
3900
3901 return IRQ_HANDLED;
3902 }
3903
3904 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3905 {
3906 struct snd_soc_codec *codec = data;
3907
3908 dev_crit(codec->dev, "Thermal shutdown\n");
3909
3910 return IRQ_HANDLED;
3911 }
3912
3913 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3914 {
3915 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
3916 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3917 struct snd_soc_dapm_context *dapm = &codec->dapm;
3918 unsigned int reg;
3919 int ret, i;
3920
3921 wm8994->hubs.codec = codec;
3922 codec->control_data = control->regmap;
3923
3924 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
3925
3926 mutex_init(&wm8994->accdet_lock);
3927 INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
3928 wm1811_jackdet_bootstrap);
3929
3930 switch (control->type) {
3931 case WM8994:
3932 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
3933 break;
3934 case WM1811:
3935 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work);
3936 break;
3937 default:
3938 break;
3939 }
3940
3941 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3942 init_completion(&wm8994->fll_locked[i]);
3943
3944 wm8994->micdet_irq = control->pdata.micdet_irq;
3945
3946 pm_runtime_enable(codec->dev);
3947 pm_runtime_idle(codec->dev);
3948
3949 /* By default use idle_bias_off, will override for WM8994 */
3950 codec->dapm.idle_bias_off = 1;
3951
3952 /* Set revision-specific configuration */
3953 switch (control->type) {
3954 case WM8994:
3955 /* Single ended line outputs should have VMID on. */
3956 if (!control->pdata.lineout1_diff ||
3957 !control->pdata.lineout2_diff)
3958 codec->dapm.idle_bias_off = 0;
3959
3960 switch (control->revision) {
3961 case 2:
3962 case 3:
3963 wm8994->hubs.dcs_codes_l = -5;
3964 wm8994->hubs.dcs_codes_r = -5;
3965 wm8994->hubs.hp_startup_mode = 1;
3966 wm8994->hubs.dcs_readback_mode = 1;
3967 wm8994->hubs.series_startup = 1;
3968 break;
3969 default:
3970 wm8994->hubs.dcs_readback_mode = 2;
3971 break;
3972 }
3973 break;
3974
3975 case WM8958:
3976 wm8994->hubs.dcs_readback_mode = 1;
3977 wm8994->hubs.hp_startup_mode = 1;
3978
3979 switch (control->revision) {
3980 case 0:
3981 break;
3982 default:
3983 wm8994->fll_byp = true;
3984 break;
3985 }
3986 break;
3987
3988 case WM1811:
3989 wm8994->hubs.dcs_readback_mode = 2;
3990 wm8994->hubs.no_series_update = 1;
3991 wm8994->hubs.hp_startup_mode = 1;
3992 wm8994->hubs.no_cache_dac_hp_direct = true;
3993 wm8994->fll_byp = true;
3994
3995 wm8994->hubs.dcs_codes_l = -9;
3996 wm8994->hubs.dcs_codes_r = -7;
3997
3998 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3999 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
4000 break;
4001
4002 default:
4003 break;
4004 }
4005
4006 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
4007 wm8994_fifo_error, "FIFO error", codec);
4008 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
4009 wm8994_temp_warn, "Thermal warning", codec);
4010 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
4011 wm8994_temp_shut, "Thermal shutdown", codec);
4012
4013 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4014 wm_hubs_dcs_done, "DC servo done",
4015 &wm8994->hubs);
4016 if (ret == 0)
4017 wm8994->hubs.dcs_done_irq = true;
4018
4019 switch (control->type) {
4020 case WM8994:
4021 if (wm8994->micdet_irq) {
4022 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4023 wm8994_mic_irq,
4024 IRQF_TRIGGER_RISING,
4025 "Mic1 detect",
4026 wm8994);
4027 if (ret != 0)
4028 dev_warn(codec->dev,
4029 "Failed to request Mic1 detect IRQ: %d\n",
4030 ret);
4031 }
4032
4033 ret = wm8994_request_irq(wm8994->wm8994,
4034 WM8994_IRQ_MIC1_SHRT,
4035 wm8994_mic_irq, "Mic 1 short",
4036 wm8994);
4037 if (ret != 0)
4038 dev_warn(codec->dev,
4039 "Failed to request Mic1 short IRQ: %d\n",
4040 ret);
4041
4042 ret = wm8994_request_irq(wm8994->wm8994,
4043 WM8994_IRQ_MIC2_DET,
4044 wm8994_mic_irq, "Mic 2 detect",
4045 wm8994);
4046 if (ret != 0)
4047 dev_warn(codec->dev,
4048 "Failed to request Mic2 detect IRQ: %d\n",
4049 ret);
4050
4051 ret = wm8994_request_irq(wm8994->wm8994,
4052 WM8994_IRQ_MIC2_SHRT,
4053 wm8994_mic_irq, "Mic 2 short",
4054 wm8994);
4055 if (ret != 0)
4056 dev_warn(codec->dev,
4057 "Failed to request Mic2 short IRQ: %d\n",
4058 ret);
4059 break;
4060
4061 case WM8958:
4062 case WM1811:
4063 if (wm8994->micdet_irq) {
4064 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4065 wm8958_mic_irq,
4066 IRQF_TRIGGER_RISING,
4067 "Mic detect",
4068 wm8994);
4069 if (ret != 0)
4070 dev_warn(codec->dev,
4071 "Failed to request Mic detect IRQ: %d\n",
4072 ret);
4073 } else {
4074 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4075 wm8958_mic_irq, "Mic detect",
4076 wm8994);
4077 }
4078 }
4079
4080 switch (control->type) {
4081 case WM1811:
4082 if (control->cust_id > 1 || control->revision > 1) {
4083 ret = wm8994_request_irq(wm8994->wm8994,
4084 WM8994_IRQ_GPIO(6),
4085 wm1811_jackdet_irq, "JACKDET",
4086 wm8994);
4087 if (ret == 0)
4088 wm8994->jackdet = true;
4089 }
4090 break;
4091 default:
4092 break;
4093 }
4094
4095 wm8994->fll_locked_irq = true;
4096 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
4097 ret = wm8994_request_irq(wm8994->wm8994,
4098 WM8994_IRQ_FLL1_LOCK + i,
4099 wm8994_fll_locked_irq, "FLL lock",
4100 &wm8994->fll_locked[i]);
4101 if (ret != 0)
4102 wm8994->fll_locked_irq = false;
4103 }
4104
4105 /* Make sure we can read from the GPIOs if they're inputs */
4106 pm_runtime_get_sync(codec->dev);
4107
4108 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
4109 * configured on init - if a system wants to do this dynamically
4110 * at runtime we can deal with that then.
4111 */
4112 ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
4113 if (ret < 0) {
4114 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
4115 goto err_irq;
4116 }
4117 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4118 wm8994->lrclk_shared[0] = 1;
4119 wm8994_dai[0].symmetric_rates = 1;
4120 } else {
4121 wm8994->lrclk_shared[0] = 0;
4122 }
4123
4124 ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
4125 if (ret < 0) {
4126 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
4127 goto err_irq;
4128 }
4129 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4130 wm8994->lrclk_shared[1] = 1;
4131 wm8994_dai[1].symmetric_rates = 1;
4132 } else {
4133 wm8994->lrclk_shared[1] = 0;
4134 }
4135
4136 pm_runtime_put(codec->dev);
4137
4138 /* Latch volume update bits */
4139 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
4140 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg,
4141 wm8994_vu_bits[i].mask,
4142 wm8994_vu_bits[i].mask);
4143
4144 /* Set the low bit of the 3D stereo depth so TLV matches */
4145 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
4146 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
4147 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
4148 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
4149 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
4150 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
4151 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
4152 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
4153 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
4154
4155 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
4156 * use this; it only affects behaviour on idle TDM clock
4157 * cycles. */
4158 switch (control->type) {
4159 case WM8994:
4160 case WM8958:
4161 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
4162 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
4163 break;
4164 default:
4165 break;
4166 }
4167
4168 /* Put MICBIAS into bypass mode by default on newer devices */
4169 switch (control->type) {
4170 case WM8958:
4171 case WM1811:
4172 snd_soc_update_bits(codec, WM8958_MICBIAS1,
4173 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
4174 snd_soc_update_bits(codec, WM8958_MICBIAS2,
4175 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
4176 break;
4177 default:
4178 break;
4179 }
4180
4181 wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
4182 wm_hubs_update_class_w(codec);
4183
4184 wm8994_handle_pdata(wm8994);
4185
4186 wm_hubs_add_analogue_controls(codec);
4187 snd_soc_add_codec_controls(codec, wm8994_snd_controls,
4188 ARRAY_SIZE(wm8994_snd_controls));
4189 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
4190 ARRAY_SIZE(wm8994_dapm_widgets));
4191
4192 switch (control->type) {
4193 case WM8994:
4194 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
4195 ARRAY_SIZE(wm8994_specific_dapm_widgets));
4196 if (control->revision < 4) {
4197 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4198 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4199 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4200 ARRAY_SIZE(wm8994_adc_revd_widgets));
4201 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4202 ARRAY_SIZE(wm8994_dac_revd_widgets));
4203 } else {
4204 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4205 ARRAY_SIZE(wm8994_lateclk_widgets));
4206 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4207 ARRAY_SIZE(wm8994_adc_widgets));
4208 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4209 ARRAY_SIZE(wm8994_dac_widgets));
4210 }
4211 break;
4212 case WM8958:
4213 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4214 ARRAY_SIZE(wm8958_snd_controls));
4215 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4216 ARRAY_SIZE(wm8958_dapm_widgets));
4217 if (control->revision < 1) {
4218 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4219 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4220 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4221 ARRAY_SIZE(wm8994_adc_revd_widgets));
4222 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4223 ARRAY_SIZE(wm8994_dac_revd_widgets));
4224 } else {
4225 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4226 ARRAY_SIZE(wm8994_lateclk_widgets));
4227 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4228 ARRAY_SIZE(wm8994_adc_widgets));
4229 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4230 ARRAY_SIZE(wm8994_dac_widgets));
4231 }
4232 break;
4233
4234 case WM1811:
4235 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4236 ARRAY_SIZE(wm8958_snd_controls));
4237 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4238 ARRAY_SIZE(wm8958_dapm_widgets));
4239 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4240 ARRAY_SIZE(wm8994_lateclk_widgets));
4241 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4242 ARRAY_SIZE(wm8994_adc_widgets));
4243 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4244 ARRAY_SIZE(wm8994_dac_widgets));
4245 break;
4246 }
4247
4248 wm_hubs_add_analogue_routes(codec, 0, 0);
4249 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
4250
4251 switch (control->type) {
4252 case WM8994:
4253 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4254 ARRAY_SIZE(wm8994_intercon));
4255
4256 if (control->revision < 4) {
4257 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4258 ARRAY_SIZE(wm8994_revd_intercon));
4259 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4260 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4261 } else {
4262 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4263 ARRAY_SIZE(wm8994_lateclk_intercon));
4264 }
4265 break;
4266 case WM8958:
4267 if (control->revision < 1) {
4268 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4269 ARRAY_SIZE(wm8994_intercon));
4270 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4271 ARRAY_SIZE(wm8994_revd_intercon));
4272 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4273 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4274 } else {
4275 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4276 ARRAY_SIZE(wm8994_lateclk_intercon));
4277 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4278 ARRAY_SIZE(wm8958_intercon));
4279 }
4280
4281 wm8958_dsp2_init(codec);
4282 break;
4283 case WM1811:
4284 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4285 ARRAY_SIZE(wm8994_lateclk_intercon));
4286 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4287 ARRAY_SIZE(wm8958_intercon));
4288 break;
4289 }
4290
4291 return 0;
4292
4293 err_irq:
4294 if (wm8994->jackdet)
4295 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4296 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4297 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4298 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
4299 if (wm8994->micdet_irq)
4300 free_irq(wm8994->micdet_irq, wm8994);
4301 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4302 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4303 &wm8994->fll_locked[i]);
4304 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4305 &wm8994->hubs);
4306 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4307 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4308 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4309
4310 return ret;
4311 }
4312
4313 static int wm8994_codec_remove(struct snd_soc_codec *codec)
4314 {
4315 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4316 struct wm8994 *control = wm8994->wm8994;
4317 int i;
4318
4319 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
4320
4321 pm_runtime_disable(codec->dev);
4322
4323 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4324 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4325 &wm8994->fll_locked[i]);
4326
4327 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4328 &wm8994->hubs);
4329 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4330 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4331 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4332
4333 if (wm8994->jackdet)
4334 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4335
4336 switch (control->type) {
4337 case WM8994:
4338 if (wm8994->micdet_irq)
4339 free_irq(wm8994->micdet_irq, wm8994);
4340 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
4341 wm8994);
4342 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
4343 wm8994);
4344 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4345 wm8994);
4346 break;
4347
4348 case WM1811:
4349 case WM8958:
4350 if (wm8994->micdet_irq)
4351 free_irq(wm8994->micdet_irq, wm8994);
4352 break;
4353 }
4354 release_firmware(wm8994->mbc);
4355 release_firmware(wm8994->mbc_vss);
4356 release_firmware(wm8994->enh_eq);
4357 kfree(wm8994->retune_mobile_texts);
4358 return 0;
4359 }
4360
4361 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4362 .probe = wm8994_codec_probe,
4363 .remove = wm8994_codec_remove,
4364 .suspend = wm8994_codec_suspend,
4365 .resume = wm8994_codec_resume,
4366 .set_bias_level = wm8994_set_bias_level,
4367 };
4368
4369 static int wm8994_probe(struct platform_device *pdev)
4370 {
4371 struct wm8994_priv *wm8994;
4372
4373 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4374 GFP_KERNEL);
4375 if (wm8994 == NULL)
4376 return -ENOMEM;
4377 platform_set_drvdata(pdev, wm8994);
4378
4379 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
4380
4381 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4382 wm8994_dai, ARRAY_SIZE(wm8994_dai));
4383 }
4384
4385 static int wm8994_remove(struct platform_device *pdev)
4386 {
4387 snd_soc_unregister_codec(&pdev->dev);
4388 return 0;
4389 }
4390
4391 #ifdef CONFIG_PM_SLEEP
4392 static int wm8994_suspend(struct device *dev)
4393 {
4394 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4395
4396 /* Drop down to power saving mode when system is suspended */
4397 if (wm8994->jackdet && !wm8994->active_refcount)
4398 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4399 WM1811_JACKDET_MODE_MASK,
4400 wm8994->jackdet_mode);
4401
4402 return 0;
4403 }
4404
4405 static int wm8994_resume(struct device *dev)
4406 {
4407 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4408
4409 if (wm8994->jackdet && wm8994->jackdet_mode)
4410 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4411 WM1811_JACKDET_MODE_MASK,
4412 WM1811_JACKDET_MODE_AUDIO);
4413
4414 return 0;
4415 }
4416 #endif
4417
4418 static const struct dev_pm_ops wm8994_pm_ops = {
4419 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4420 };
4421
4422 static struct platform_driver wm8994_codec_driver = {
4423 .driver = {
4424 .name = "wm8994-codec",
4425 .owner = THIS_MODULE,
4426 .pm = &wm8994_pm_ops,
4427 },
4428 .probe = wm8994_probe,
4429 .remove = wm8994_remove,
4430 };
4431
4432 module_platform_driver(wm8994_codec_driver);
4433
4434 MODULE_DESCRIPTION("ASoC WM8994 driver");
4435 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4436 MODULE_LICENSE("GPL");
4437 MODULE_ALIAS("platform:wm8994-codec");
Linux kernel - Deliverables
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