2 * wm8994.c -- WM8994 ALSA SoC Audio driver
4 * Copyright 2009-12 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/jack.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <trace/events/asoc.h>
33 #include <linux/mfd/wm8994/core.h>
34 #include <linux/mfd/wm8994/registers.h>
35 #include <linux/mfd/wm8994/pdata.h>
36 #include <linux/mfd/wm8994/gpio.h>
41 #define WM1811_JACKDET_MODE_NONE 0x0000
42 #define WM1811_JACKDET_MODE_JACK 0x0100
43 #define WM1811_JACKDET_MODE_MIC 0x0080
44 #define WM1811_JACKDET_MODE_AUDIO 0x0180
46 #define WM8994_NUM_DRC 3
47 #define WM8994_NUM_EQ 3
52 } wm8994_vu_bits
[] = {
53 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME
, WM8994_IN1_VU
},
54 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME
, WM8994_IN1_VU
},
55 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME
, WM8994_IN2_VU
},
56 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME
, WM8994_IN2_VU
},
57 { WM8994_SPEAKER_VOLUME_LEFT
, WM8994_SPKOUT_VU
},
58 { WM8994_SPEAKER_VOLUME_RIGHT
, WM8994_SPKOUT_VU
},
59 { WM8994_LEFT_OUTPUT_VOLUME
, WM8994_HPOUT1_VU
},
60 { WM8994_RIGHT_OUTPUT_VOLUME
, WM8994_HPOUT1_VU
},
61 { WM8994_LEFT_OPGA_VOLUME
, WM8994_MIXOUT_VU
},
62 { WM8994_RIGHT_OPGA_VOLUME
, WM8994_MIXOUT_VU
},
64 { WM8994_AIF1_DAC1_LEFT_VOLUME
, WM8994_AIF1DAC1_VU
},
65 { WM8994_AIF1_DAC1_RIGHT_VOLUME
, WM8994_AIF1DAC1_VU
},
66 { WM8994_AIF1_DAC2_LEFT_VOLUME
, WM8994_AIF1DAC2_VU
},
67 { WM8994_AIF1_DAC2_RIGHT_VOLUME
, WM8994_AIF1DAC2_VU
},
68 { WM8994_AIF2_DAC_LEFT_VOLUME
, WM8994_AIF2DAC_VU
},
69 { WM8994_AIF2_DAC_RIGHT_VOLUME
, WM8994_AIF2DAC_VU
},
70 { WM8994_AIF1_ADC1_LEFT_VOLUME
, WM8994_AIF1ADC1_VU
},
71 { WM8994_AIF1_ADC1_RIGHT_VOLUME
, WM8994_AIF1ADC1_VU
},
72 { WM8994_AIF1_ADC2_LEFT_VOLUME
, WM8994_AIF1ADC2_VU
},
73 { WM8994_AIF1_ADC2_RIGHT_VOLUME
, WM8994_AIF1ADC2_VU
},
74 { WM8994_AIF2_ADC_LEFT_VOLUME
, WM8994_AIF2ADC_VU
},
75 { WM8994_AIF2_ADC_RIGHT_VOLUME
, WM8994_AIF1ADC2_VU
},
76 { WM8994_DAC1_LEFT_VOLUME
, WM8994_DAC1_VU
},
77 { WM8994_DAC1_RIGHT_VOLUME
, WM8994_DAC1_VU
},
78 { WM8994_DAC2_LEFT_VOLUME
, WM8994_DAC2_VU
},
79 { WM8994_DAC2_RIGHT_VOLUME
, WM8994_DAC2_VU
},
82 static int wm8994_drc_base
[] = {
88 static int wm8994_retune_mobile_base
[] = {
89 WM8994_AIF1_DAC1_EQ_GAINS_1
,
90 WM8994_AIF1_DAC2_EQ_GAINS_1
,
91 WM8994_AIF2_EQ_GAINS_1
,
94 static void wm8958_default_micdet(u16 status
, void *data
);
96 static const struct wm8958_micd_rate micdet_rates
[] = {
97 { 32768, true, 1, 4 },
98 { 32768, false, 1, 1 },
99 { 44100 * 256, true, 7, 10 },
100 { 44100 * 256, false, 7, 10 },
103 static const struct wm8958_micd_rate jackdet_rates
[] = {
104 { 32768, true, 0, 1 },
105 { 32768, false, 0, 1 },
106 { 44100 * 256, true, 10, 10 },
107 { 44100 * 256, false, 7, 8 },
110 static void wm8958_micd_set_rate(struct snd_soc_codec
*codec
)
112 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
113 int best
, i
, sysclk
, val
;
115 const struct wm8958_micd_rate
*rates
;
118 if (!(wm8994
->pdata
&& wm8994
->pdata
->micd_rates
) &&
119 wm8994
->jack_cb
!= wm8958_default_micdet
)
122 idle
= !wm8994
->jack_mic
;
124 sysclk
= snd_soc_read(codec
, WM8994_CLOCKING_1
);
125 if (sysclk
& WM8994_SYSCLK_SRC
)
126 sysclk
= wm8994
->aifclk
[1];
128 sysclk
= wm8994
->aifclk
[0];
130 if (wm8994
->pdata
&& wm8994
->pdata
->micd_rates
) {
131 rates
= wm8994
->pdata
->micd_rates
;
132 num_rates
= wm8994
->pdata
->num_micd_rates
;
133 } else if (wm8994
->jackdet
) {
134 rates
= jackdet_rates
;
135 num_rates
= ARRAY_SIZE(jackdet_rates
);
137 rates
= micdet_rates
;
138 num_rates
= ARRAY_SIZE(micdet_rates
);
142 for (i
= 0; i
< num_rates
; i
++) {
143 if (rates
[i
].idle
!= idle
)
145 if (abs(rates
[i
].sysclk
- sysclk
) <
146 abs(rates
[best
].sysclk
- sysclk
))
148 else if (rates
[best
].idle
!= idle
)
152 val
= rates
[best
].start
<< WM8958_MICD_BIAS_STARTTIME_SHIFT
153 | rates
[best
].rate
<< WM8958_MICD_RATE_SHIFT
;
155 dev_dbg(codec
->dev
, "MICD rate %d,%d for %dHz %s\n",
156 rates
[best
].start
, rates
[best
].rate
, sysclk
,
157 idle
? "idle" : "active");
159 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
160 WM8958_MICD_BIAS_STARTTIME_MASK
|
161 WM8958_MICD_RATE_MASK
, val
);
164 static int configure_aif_clock(struct snd_soc_codec
*codec
, int aif
)
166 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
176 switch (wm8994
->sysclk
[aif
]) {
177 case WM8994_SYSCLK_MCLK1
:
178 rate
= wm8994
->mclk
[0];
181 case WM8994_SYSCLK_MCLK2
:
183 rate
= wm8994
->mclk
[1];
186 case WM8994_SYSCLK_FLL1
:
188 rate
= wm8994
->fll
[0].out
;
191 case WM8994_SYSCLK_FLL2
:
193 rate
= wm8994
->fll
[1].out
;
200 if (rate
>= 13500000) {
202 reg1
|= WM8994_AIF1CLK_DIV
;
204 dev_dbg(codec
->dev
, "Dividing AIF%d clock to %dHz\n",
208 wm8994
->aifclk
[aif
] = rate
;
210 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
+ offset
,
211 WM8994_AIF1CLK_SRC_MASK
| WM8994_AIF1CLK_DIV
,
217 static int configure_clock(struct snd_soc_codec
*codec
)
219 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
222 /* Bring up the AIF clocks first */
223 configure_aif_clock(codec
, 0);
224 configure_aif_clock(codec
, 1);
226 /* Then switch CLK_SYS over to the higher of them; a change
227 * can only happen as a result of a clocking change which can
228 * only be made outside of DAPM so we can safely redo the
232 /* If they're equal it doesn't matter which is used */
233 if (wm8994
->aifclk
[0] == wm8994
->aifclk
[1]) {
234 wm8958_micd_set_rate(codec
);
238 if (wm8994
->aifclk
[0] < wm8994
->aifclk
[1])
239 new = WM8994_SYSCLK_SRC
;
243 change
= snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
244 WM8994_SYSCLK_SRC
, new);
246 snd_soc_dapm_sync(&codec
->dapm
);
248 wm8958_micd_set_rate(codec
);
253 static int check_clk_sys(struct snd_soc_dapm_widget
*source
,
254 struct snd_soc_dapm_widget
*sink
)
256 int reg
= snd_soc_read(source
->codec
, WM8994_CLOCKING_1
);
259 /* Check what we're currently using for CLK_SYS */
260 if (reg
& WM8994_SYSCLK_SRC
)
265 return strcmp(source
->name
, clk
) == 0;
268 static const char *sidetone_hpf_text
[] = {
269 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
272 static const struct soc_enum sidetone_hpf
=
273 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 7, 7, sidetone_hpf_text
);
275 static const char *adc_hpf_text
[] = {
276 "HiFi", "Voice 1", "Voice 2", "Voice 3"
279 static const struct soc_enum aif1adc1_hpf
=
280 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS
, 13, 4, adc_hpf_text
);
282 static const struct soc_enum aif1adc2_hpf
=
283 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS
, 13, 4, adc_hpf_text
);
285 static const struct soc_enum aif2adc_hpf
=
286 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS
, 13, 4, adc_hpf_text
);
288 static const DECLARE_TLV_DB_SCALE(aif_tlv
, 0, 600, 0);
289 static const DECLARE_TLV_DB_SCALE(digital_tlv
, -7200, 75, 1);
290 static const DECLARE_TLV_DB_SCALE(st_tlv
, -3600, 300, 0);
291 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv
, -1600, 183, 0);
292 static const DECLARE_TLV_DB_SCALE(eq_tlv
, -1200, 100, 0);
293 static const DECLARE_TLV_DB_SCALE(ng_tlv
, -10200, 600, 0);
294 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv
, 0, 900, 0);
296 #define WM8994_DRC_SWITCH(xname, reg, shift) \
297 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
298 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
299 .put = wm8994_put_drc_sw, \
300 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
302 static int wm8994_put_drc_sw(struct snd_kcontrol
*kcontrol
,
303 struct snd_ctl_elem_value
*ucontrol
)
305 struct soc_mixer_control
*mc
=
306 (struct soc_mixer_control
*)kcontrol
->private_value
;
307 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
310 /* Can't enable both ADC and DAC paths simultaneously */
311 if (mc
->shift
== WM8994_AIF1DAC1_DRC_ENA_SHIFT
)
312 mask
= WM8994_AIF1ADC1L_DRC_ENA_MASK
|
313 WM8994_AIF1ADC1R_DRC_ENA_MASK
;
315 mask
= WM8994_AIF1DAC1_DRC_ENA_MASK
;
317 ret
= snd_soc_read(codec
, mc
->reg
);
323 return snd_soc_put_volsw(kcontrol
, ucontrol
);
326 static void wm8994_set_drc(struct snd_soc_codec
*codec
, int drc
)
328 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
329 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
330 int base
= wm8994_drc_base
[drc
];
331 int cfg
= wm8994
->drc_cfg
[drc
];
334 /* Save any enables; the configuration should clear them. */
335 save
= snd_soc_read(codec
, base
);
336 save
&= WM8994_AIF1DAC1_DRC_ENA
| WM8994_AIF1ADC1L_DRC_ENA
|
337 WM8994_AIF1ADC1R_DRC_ENA
;
339 for (i
= 0; i
< WM8994_DRC_REGS
; i
++)
340 snd_soc_update_bits(codec
, base
+ i
, 0xffff,
341 pdata
->drc_cfgs
[cfg
].regs
[i
]);
343 snd_soc_update_bits(codec
, base
, WM8994_AIF1DAC1_DRC_ENA
|
344 WM8994_AIF1ADC1L_DRC_ENA
|
345 WM8994_AIF1ADC1R_DRC_ENA
, save
);
348 /* Icky as hell but saves code duplication */
349 static int wm8994_get_drc(const char *name
)
351 if (strcmp(name
, "AIF1DRC1 Mode") == 0)
353 if (strcmp(name
, "AIF1DRC2 Mode") == 0)
355 if (strcmp(name
, "AIF2DRC Mode") == 0)
360 static int wm8994_put_drc_enum(struct snd_kcontrol
*kcontrol
,
361 struct snd_ctl_elem_value
*ucontrol
)
363 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
364 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
365 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
366 int drc
= wm8994_get_drc(kcontrol
->id
.name
);
367 int value
= ucontrol
->value
.integer
.value
[0];
372 if (value
>= pdata
->num_drc_cfgs
)
375 wm8994
->drc_cfg
[drc
] = value
;
377 wm8994_set_drc(codec
, drc
);
382 static int wm8994_get_drc_enum(struct snd_kcontrol
*kcontrol
,
383 struct snd_ctl_elem_value
*ucontrol
)
385 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
386 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
387 int drc
= wm8994_get_drc(kcontrol
->id
.name
);
389 ucontrol
->value
.enumerated
.item
[0] = wm8994
->drc_cfg
[drc
];
394 static void wm8994_set_retune_mobile(struct snd_soc_codec
*codec
, int block
)
396 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
397 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
398 int base
= wm8994_retune_mobile_base
[block
];
399 int iface
, best
, best_val
, save
, i
, cfg
;
401 if (!pdata
|| !wm8994
->num_retune_mobile_texts
)
416 /* Find the version of the currently selected configuration
417 * with the nearest sample rate. */
418 cfg
= wm8994
->retune_mobile_cfg
[block
];
421 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
422 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
423 wm8994
->retune_mobile_texts
[cfg
]) == 0 &&
424 abs(pdata
->retune_mobile_cfgs
[i
].rate
425 - wm8994
->dac_rates
[iface
]) < best_val
) {
427 best_val
= abs(pdata
->retune_mobile_cfgs
[i
].rate
428 - wm8994
->dac_rates
[iface
]);
432 dev_dbg(codec
->dev
, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
434 pdata
->retune_mobile_cfgs
[best
].name
,
435 pdata
->retune_mobile_cfgs
[best
].rate
,
436 wm8994
->dac_rates
[iface
]);
438 /* The EQ will be disabled while reconfiguring it, remember the
439 * current configuration.
441 save
= snd_soc_read(codec
, base
);
442 save
&= WM8994_AIF1DAC1_EQ_ENA
;
444 for (i
= 0; i
< WM8994_EQ_REGS
; i
++)
445 snd_soc_update_bits(codec
, base
+ i
, 0xffff,
446 pdata
->retune_mobile_cfgs
[best
].regs
[i
]);
448 snd_soc_update_bits(codec
, base
, WM8994_AIF1DAC1_EQ_ENA
, save
);
451 /* Icky as hell but saves code duplication */
452 static int wm8994_get_retune_mobile_block(const char *name
)
454 if (strcmp(name
, "AIF1.1 EQ Mode") == 0)
456 if (strcmp(name
, "AIF1.2 EQ Mode") == 0)
458 if (strcmp(name
, "AIF2 EQ Mode") == 0)
463 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
464 struct snd_ctl_elem_value
*ucontrol
)
466 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
467 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
468 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
469 int block
= wm8994_get_retune_mobile_block(kcontrol
->id
.name
);
470 int value
= ucontrol
->value
.integer
.value
[0];
475 if (value
>= pdata
->num_retune_mobile_cfgs
)
478 wm8994
->retune_mobile_cfg
[block
] = value
;
480 wm8994_set_retune_mobile(codec
, block
);
485 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
486 struct snd_ctl_elem_value
*ucontrol
)
488 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
489 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
490 int block
= wm8994_get_retune_mobile_block(kcontrol
->id
.name
);
492 ucontrol
->value
.enumerated
.item
[0] = wm8994
->retune_mobile_cfg
[block
];
497 static const char *aif_chan_src_text
[] = {
501 static const struct soc_enum aif1adcl_src
=
502 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1
, 15, 2, aif_chan_src_text
);
504 static const struct soc_enum aif1adcr_src
=
505 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1
, 14, 2, aif_chan_src_text
);
507 static const struct soc_enum aif2adcl_src
=
508 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1
, 15, 2, aif_chan_src_text
);
510 static const struct soc_enum aif2adcr_src
=
511 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1
, 14, 2, aif_chan_src_text
);
513 static const struct soc_enum aif1dacl_src
=
514 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2
, 15, 2, aif_chan_src_text
);
516 static const struct soc_enum aif1dacr_src
=
517 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2
, 14, 2, aif_chan_src_text
);
519 static const struct soc_enum aif2dacl_src
=
520 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2
, 15, 2, aif_chan_src_text
);
522 static const struct soc_enum aif2dacr_src
=
523 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2
, 14, 2, aif_chan_src_text
);
525 static const char *osr_text
[] = {
526 "Low Power", "High Performance",
529 static const struct soc_enum dac_osr
=
530 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING
, 0, 2, osr_text
);
532 static const struct soc_enum adc_osr
=
533 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING
, 1, 2, osr_text
);
535 static const struct snd_kcontrol_new wm8994_snd_controls
[] = {
536 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME
,
537 WM8994_AIF1_ADC1_RIGHT_VOLUME
,
538 1, 119, 0, digital_tlv
),
539 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME
,
540 WM8994_AIF1_ADC2_RIGHT_VOLUME
,
541 1, 119, 0, digital_tlv
),
542 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME
,
543 WM8994_AIF2_ADC_RIGHT_VOLUME
,
544 1, 119, 0, digital_tlv
),
546 SOC_ENUM("AIF1ADCL Source", aif1adcl_src
),
547 SOC_ENUM("AIF1ADCR Source", aif1adcr_src
),
548 SOC_ENUM("AIF2ADCL Source", aif2adcl_src
),
549 SOC_ENUM("AIF2ADCR Source", aif2adcr_src
),
551 SOC_ENUM("AIF1DACL Source", aif1dacl_src
),
552 SOC_ENUM("AIF1DACR Source", aif1dacr_src
),
553 SOC_ENUM("AIF2DACL Source", aif2dacl_src
),
554 SOC_ENUM("AIF2DACR Source", aif2dacr_src
),
556 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME
,
557 WM8994_AIF1_DAC1_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
558 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME
,
559 WM8994_AIF1_DAC2_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
560 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME
,
561 WM8994_AIF2_DAC_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
563 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2
, 10, 3, 0, aif_tlv
),
564 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2
, 10, 3, 0, aif_tlv
),
566 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1
, 0, 1, 0),
567 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1
, 0, 1, 0),
568 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1
, 0, 1, 0),
570 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1
, 2),
571 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1
, 1),
572 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1
, 0),
574 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1
, 2),
575 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1
, 1),
576 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1
, 0),
578 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1
, 2),
579 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1
, 1),
580 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1
, 0),
582 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES
,
584 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES
,
586 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES
,
588 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES
,
590 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf
),
591 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE
, 6, 1, 0),
593 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf
),
594 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS
, 12, 11, 1, 0),
596 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf
),
597 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS
, 12, 11, 1, 0),
599 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf
),
600 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS
, 12, 11, 1, 0),
602 SOC_ENUM("ADC OSR", adc_osr
),
603 SOC_ENUM("DAC OSR", dac_osr
),
605 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME
,
606 WM8994_DAC1_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
607 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME
,
608 WM8994_DAC1_RIGHT_VOLUME
, 9, 1, 1),
610 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME
,
611 WM8994_DAC2_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
612 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME
,
613 WM8994_DAC2_RIGHT_VOLUME
, 9, 1, 1),
615 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION
,
616 6, 1, 1, wm_hubs_spkmix_tlv
),
617 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION
,
618 2, 1, 1, wm_hubs_spkmix_tlv
),
620 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION
,
621 6, 1, 1, wm_hubs_spkmix_tlv
),
622 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION
,
623 2, 1, 1, wm_hubs_spkmix_tlv
),
625 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2
,
626 10, 15, 0, wm8994_3d_tlv
),
627 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2
,
629 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2
,
630 10, 15, 0, wm8994_3d_tlv
),
631 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2
,
633 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2
,
634 10, 15, 0, wm8994_3d_tlv
),
635 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2
,
639 static const struct snd_kcontrol_new wm8994_eq_controls
[] = {
640 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 11, 31, 0,
642 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 6, 31, 0,
644 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 1, 31, 0,
646 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2
, 11, 31, 0,
648 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2
, 6, 31, 0,
651 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 11, 31, 0,
653 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 6, 31, 0,
655 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 1, 31, 0,
657 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2
, 11, 31, 0,
659 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2
, 6, 31, 0,
662 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1
, 11, 31, 0,
664 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1
, 6, 31, 0,
666 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1
, 1, 31, 0,
668 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2
, 11, 31, 0,
670 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2
, 6, 31, 0,
674 static const struct snd_kcontrol_new wm8994_drc_controls
[] = {
675 SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1
, 5,
676 WM8994_AIF1DAC1_DRC_ENA
| WM8994_AIF1ADC1L_DRC_ENA
|
677 WM8994_AIF1ADC1R_DRC_ENA
),
678 SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1
, 5,
679 WM8994_AIF1DAC2_DRC_ENA
| WM8994_AIF1ADC2L_DRC_ENA
|
680 WM8994_AIF1ADC2R_DRC_ENA
),
681 SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1
, 5,
682 WM8994_AIF2DAC_DRC_ENA
| WM8994_AIF2ADCL_DRC_ENA
|
683 WM8994_AIF2ADCR_DRC_ENA
),
686 static const char *wm8958_ng_text
[] = {
687 "30ms", "125ms", "250ms", "500ms",
690 static const struct soc_enum wm8958_aif1dac1_ng_hold
=
691 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE
,
692 WM8958_AIF1DAC1_NG_THR_SHIFT
, 4, wm8958_ng_text
);
694 static const struct soc_enum wm8958_aif1dac2_ng_hold
=
695 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE
,
696 WM8958_AIF1DAC2_NG_THR_SHIFT
, 4, wm8958_ng_text
);
698 static const struct soc_enum wm8958_aif2dac_ng_hold
=
699 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE
,
700 WM8958_AIF2DAC_NG_THR_SHIFT
, 4, wm8958_ng_text
);
702 static const struct snd_kcontrol_new wm8958_snd_controls
[] = {
703 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2
, 10, 3, 0, aif_tlv
),
705 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE
,
706 WM8958_AIF1DAC1_NG_ENA_SHIFT
, 1, 0),
707 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold
),
708 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
709 WM8958_AIF1_DAC1_NOISE_GATE
, WM8958_AIF1DAC1_NG_THR_SHIFT
,
712 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE
,
713 WM8958_AIF1DAC2_NG_ENA_SHIFT
, 1, 0),
714 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold
),
715 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
716 WM8958_AIF1_DAC2_NOISE_GATE
, WM8958_AIF1DAC2_NG_THR_SHIFT
,
719 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE
,
720 WM8958_AIF2DAC_NG_ENA_SHIFT
, 1, 0),
721 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold
),
722 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
723 WM8958_AIF2_DAC_NOISE_GATE
, WM8958_AIF2DAC_NG_THR_SHIFT
,
727 static const struct snd_kcontrol_new wm1811_snd_controls
[] = {
728 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1
, 7, 1, 0,
730 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1
, 8, 1, 0,
734 /* We run all mode setting through a function to enforce audio mode */
735 static void wm1811_jackdet_set_mode(struct snd_soc_codec
*codec
, u16 mode
)
737 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
739 if (!wm8994
->jackdet
|| !wm8994
->jack_cb
)
742 if (wm8994
->active_refcount
)
743 mode
= WM1811_JACKDET_MODE_AUDIO
;
745 if (mode
== wm8994
->jackdet_mode
)
748 wm8994
->jackdet_mode
= mode
;
750 /* Always use audio mode to detect while the system is active */
751 if (mode
!= WM1811_JACKDET_MODE_NONE
)
752 mode
= WM1811_JACKDET_MODE_AUDIO
;
754 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
755 WM1811_JACKDET_MODE_MASK
, mode
);
758 static void active_reference(struct snd_soc_codec
*codec
)
760 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
762 mutex_lock(&wm8994
->accdet_lock
);
764 wm8994
->active_refcount
++;
766 dev_dbg(codec
->dev
, "Active refcount incremented, now %d\n",
767 wm8994
->active_refcount
);
769 /* If we're using jack detection go into audio mode */
770 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_AUDIO
);
772 mutex_unlock(&wm8994
->accdet_lock
);
775 static void active_dereference(struct snd_soc_codec
*codec
)
777 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
780 mutex_lock(&wm8994
->accdet_lock
);
782 wm8994
->active_refcount
--;
784 dev_dbg(codec
->dev
, "Active refcount decremented, now %d\n",
785 wm8994
->active_refcount
);
787 if (wm8994
->active_refcount
== 0) {
788 /* Go into appropriate detection only mode */
789 if (wm8994
->jack_mic
|| wm8994
->mic_detecting
)
790 mode
= WM1811_JACKDET_MODE_MIC
;
792 mode
= WM1811_JACKDET_MODE_JACK
;
794 wm1811_jackdet_set_mode(codec
, mode
);
797 mutex_unlock(&wm8994
->accdet_lock
);
800 static int clk_sys_event(struct snd_soc_dapm_widget
*w
,
801 struct snd_kcontrol
*kcontrol
, int event
)
803 struct snd_soc_codec
*codec
= w
->codec
;
804 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
807 case SND_SOC_DAPM_PRE_PMU
:
808 return configure_clock(codec
);
810 case SND_SOC_DAPM_POST_PMU
:
812 * JACKDET won't run until we start the clock and it
813 * only reports deltas, make sure we notify the state
814 * up the stack on startup. Use a *very* generous
815 * timeout for paranoia, there's no urgency and we
816 * don't want false reports.
818 if (wm8994
->jackdet
&& !wm8994
->clk_has_run
) {
819 schedule_delayed_work(&wm8994
->jackdet_bootstrap
,
820 msecs_to_jiffies(1000));
821 wm8994
->clk_has_run
= true;
825 case SND_SOC_DAPM_POST_PMD
:
826 configure_clock(codec
);
833 static void vmid_reference(struct snd_soc_codec
*codec
)
835 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
837 pm_runtime_get_sync(codec
->dev
);
839 wm8994
->vmid_refcount
++;
841 dev_dbg(codec
->dev
, "Referencing VMID, refcount is now %d\n",
842 wm8994
->vmid_refcount
);
844 if (wm8994
->vmid_refcount
== 1) {
845 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
846 WM8994_LINEOUT1_DISCH
|
847 WM8994_LINEOUT2_DISCH
, 0);
849 wm_hubs_vmid_ena(codec
);
851 switch (wm8994
->vmid_mode
) {
853 WARN_ON(NULL
== "Invalid VMID mode");
854 case WM8994_VMID_NORMAL
:
855 /* Startup bias, VMID ramp & buffer */
856 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
859 WM8994_STARTUP_BIAS_ENA
|
860 WM8994_VMID_BUF_ENA
|
861 WM8994_VMID_RAMP_MASK
,
863 WM8994_STARTUP_BIAS_ENA
|
864 WM8994_VMID_BUF_ENA
|
865 (0x3 << WM8994_VMID_RAMP_SHIFT
));
867 /* Main bias enable, VMID=2x40k */
868 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
870 WM8994_VMID_SEL_MASK
,
871 WM8994_BIAS_ENA
| 0x2);
875 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
876 WM8994_VMID_RAMP_MASK
|
881 case WM8994_VMID_FORCE
:
882 /* Startup bias, slow VMID ramp & buffer */
883 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
886 WM8994_STARTUP_BIAS_ENA
|
887 WM8994_VMID_BUF_ENA
|
888 WM8994_VMID_RAMP_MASK
,
890 WM8994_STARTUP_BIAS_ENA
|
891 WM8994_VMID_BUF_ENA
|
892 (0x2 << WM8994_VMID_RAMP_SHIFT
));
894 /* Main bias enable, VMID=2x40k */
895 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
897 WM8994_VMID_SEL_MASK
,
898 WM8994_BIAS_ENA
| 0x2);
902 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
903 WM8994_VMID_RAMP_MASK
|
911 static void vmid_dereference(struct snd_soc_codec
*codec
)
913 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
915 wm8994
->vmid_refcount
--;
917 dev_dbg(codec
->dev
, "Dereferencing VMID, refcount is now %d\n",
918 wm8994
->vmid_refcount
);
920 if (wm8994
->vmid_refcount
== 0) {
921 if (wm8994
->hubs
.lineout1_se
)
922 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_3
,
923 WM8994_LINEOUT1N_ENA
|
924 WM8994_LINEOUT1P_ENA
,
925 WM8994_LINEOUT1N_ENA
|
926 WM8994_LINEOUT1P_ENA
);
928 if (wm8994
->hubs
.lineout2_se
)
929 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_3
,
930 WM8994_LINEOUT2N_ENA
|
931 WM8994_LINEOUT2P_ENA
,
932 WM8994_LINEOUT2N_ENA
|
933 WM8994_LINEOUT2P_ENA
);
935 /* Start discharging VMID */
936 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
942 switch (wm8994
->vmid_mode
) {
943 case WM8994_VMID_FORCE
:
950 snd_soc_update_bits(codec
, WM8994_ADDITIONAL_CONTROL
,
951 WM8994_VROI
, WM8994_VROI
);
953 /* Active discharge */
954 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
955 WM8994_LINEOUT1_DISCH
|
956 WM8994_LINEOUT2_DISCH
,
957 WM8994_LINEOUT1_DISCH
|
958 WM8994_LINEOUT2_DISCH
);
962 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_3
,
963 WM8994_LINEOUT1N_ENA
|
964 WM8994_LINEOUT1P_ENA
|
965 WM8994_LINEOUT2N_ENA
|
966 WM8994_LINEOUT2P_ENA
, 0);
968 snd_soc_update_bits(codec
, WM8994_ADDITIONAL_CONTROL
,
971 /* Switch off startup biases */
972 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
974 WM8994_STARTUP_BIAS_ENA
|
975 WM8994_VMID_BUF_ENA
|
976 WM8994_VMID_RAMP_MASK
, 0);
978 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
979 WM8994_BIAS_ENA
| WM8994_VMID_SEL_MASK
, 0);
981 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
982 WM8994_VMID_RAMP_MASK
, 0);
985 pm_runtime_put(codec
->dev
);
988 static int vmid_event(struct snd_soc_dapm_widget
*w
,
989 struct snd_kcontrol
*kcontrol
, int event
)
991 struct snd_soc_codec
*codec
= w
->codec
;
994 case SND_SOC_DAPM_PRE_PMU
:
995 vmid_reference(codec
);
998 case SND_SOC_DAPM_POST_PMD
:
999 vmid_dereference(codec
);
1006 static bool wm8994_check_class_w_digital(struct snd_soc_codec
*codec
)
1008 int source
= 0; /* GCC flow analysis can't track enable */
1011 /* We also need the same AIF source for L/R and only one path */
1012 reg
= snd_soc_read(codec
, WM8994_DAC1_LEFT_MIXER_ROUTING
);
1014 case WM8994_AIF2DACL_TO_DAC1L
:
1015 dev_vdbg(codec
->dev
, "Class W source AIF2DAC\n");
1016 source
= 2 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
1018 case WM8994_AIF1DAC2L_TO_DAC1L
:
1019 dev_vdbg(codec
->dev
, "Class W source AIF1DAC2\n");
1020 source
= 1 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
1022 case WM8994_AIF1DAC1L_TO_DAC1L
:
1023 dev_vdbg(codec
->dev
, "Class W source AIF1DAC1\n");
1024 source
= 0 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
1027 dev_vdbg(codec
->dev
, "DAC mixer setting: %x\n", reg
);
1031 reg_r
= snd_soc_read(codec
, WM8994_DAC1_RIGHT_MIXER_ROUTING
);
1033 dev_vdbg(codec
->dev
, "Left and right DAC mixers different\n");
1037 /* Set the source up */
1038 snd_soc_update_bits(codec
, WM8994_CLASS_W_1
,
1039 WM8994_CP_DYN_SRC_SEL_MASK
, source
);
1044 static int aif1clk_ev(struct snd_soc_dapm_widget
*w
,
1045 struct snd_kcontrol
*kcontrol
, int event
)
1047 struct snd_soc_codec
*codec
= w
->codec
;
1048 struct wm8994
*control
= codec
->control_data
;
1049 int mask
= WM8994_AIF1DAC1L_ENA
| WM8994_AIF1DAC1R_ENA
;
1055 switch (control
->type
) {
1058 mask
|= WM8994_AIF1DAC2L_ENA
| WM8994_AIF1DAC2R_ENA
;
1065 case SND_SOC_DAPM_PRE_PMU
:
1066 val
= snd_soc_read(codec
, WM8994_AIF1_CONTROL_1
);
1067 if ((val
& WM8994_AIF1ADCL_SRC
) &&
1068 (val
& WM8994_AIF1ADCR_SRC
))
1069 adc
= WM8994_AIF1ADC1R_ENA
| WM8994_AIF1ADC2R_ENA
;
1070 else if (!(val
& WM8994_AIF1ADCL_SRC
) &&
1071 !(val
& WM8994_AIF1ADCR_SRC
))
1072 adc
= WM8994_AIF1ADC1L_ENA
| WM8994_AIF1ADC2L_ENA
;
1074 adc
= WM8994_AIF1ADC1R_ENA
| WM8994_AIF1ADC2R_ENA
|
1075 WM8994_AIF1ADC1L_ENA
| WM8994_AIF1ADC2L_ENA
;
1077 val
= snd_soc_read(codec
, WM8994_AIF1_CONTROL_2
);
1078 if ((val
& WM8994_AIF1DACL_SRC
) &&
1079 (val
& WM8994_AIF1DACR_SRC
))
1080 dac
= WM8994_AIF1DAC1R_ENA
| WM8994_AIF1DAC2R_ENA
;
1081 else if (!(val
& WM8994_AIF1DACL_SRC
) &&
1082 !(val
& WM8994_AIF1DACR_SRC
))
1083 dac
= WM8994_AIF1DAC1L_ENA
| WM8994_AIF1DAC2L_ENA
;
1085 dac
= WM8994_AIF1DAC1R_ENA
| WM8994_AIF1DAC2R_ENA
|
1086 WM8994_AIF1DAC1L_ENA
| WM8994_AIF1DAC2L_ENA
;
1088 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
,
1090 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1092 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
1093 WM8994_AIF1DSPCLK_ENA
|
1094 WM8994_SYSDSPCLK_ENA
,
1095 WM8994_AIF1DSPCLK_ENA
|
1096 WM8994_SYSDSPCLK_ENA
);
1097 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
, mask
,
1098 WM8994_AIF1ADC1R_ENA
|
1099 WM8994_AIF1ADC1L_ENA
|
1100 WM8994_AIF1ADC2R_ENA
|
1101 WM8994_AIF1ADC2L_ENA
);
1102 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
, mask
,
1103 WM8994_AIF1DAC1R_ENA
|
1104 WM8994_AIF1DAC1L_ENA
|
1105 WM8994_AIF1DAC2R_ENA
|
1106 WM8994_AIF1DAC2L_ENA
);
1109 case SND_SOC_DAPM_POST_PMU
:
1110 for (i
= 0; i
< ARRAY_SIZE(wm8994_vu_bits
); i
++)
1111 snd_soc_write(codec
, wm8994_vu_bits
[i
].reg
,
1113 wm8994_vu_bits
[i
].reg
));
1116 case SND_SOC_DAPM_PRE_PMD
:
1117 case SND_SOC_DAPM_POST_PMD
:
1118 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1120 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
,
1123 val
= snd_soc_read(codec
, WM8994_CLOCKING_1
);
1124 if (val
& WM8994_AIF2DSPCLK_ENA
)
1125 val
= WM8994_SYSDSPCLK_ENA
;
1128 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
1129 WM8994_SYSDSPCLK_ENA
|
1130 WM8994_AIF1DSPCLK_ENA
, val
);
1137 static int aif2clk_ev(struct snd_soc_dapm_widget
*w
,
1138 struct snd_kcontrol
*kcontrol
, int event
)
1140 struct snd_soc_codec
*codec
= w
->codec
;
1147 case SND_SOC_DAPM_PRE_PMU
:
1148 val
= snd_soc_read(codec
, WM8994_AIF2_CONTROL_1
);
1149 if ((val
& WM8994_AIF2ADCL_SRC
) &&
1150 (val
& WM8994_AIF2ADCR_SRC
))
1151 adc
= WM8994_AIF2ADCR_ENA
;
1152 else if (!(val
& WM8994_AIF2ADCL_SRC
) &&
1153 !(val
& WM8994_AIF2ADCR_SRC
))
1154 adc
= WM8994_AIF2ADCL_ENA
;
1156 adc
= WM8994_AIF2ADCL_ENA
| WM8994_AIF2ADCR_ENA
;
1159 val
= snd_soc_read(codec
, WM8994_AIF2_CONTROL_2
);
1160 if ((val
& WM8994_AIF2DACL_SRC
) &&
1161 (val
& WM8994_AIF2DACR_SRC
))
1162 dac
= WM8994_AIF2DACR_ENA
;
1163 else if (!(val
& WM8994_AIF2DACL_SRC
) &&
1164 !(val
& WM8994_AIF2DACR_SRC
))
1165 dac
= WM8994_AIF2DACL_ENA
;
1167 dac
= WM8994_AIF2DACL_ENA
| WM8994_AIF2DACR_ENA
;
1169 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
,
1170 WM8994_AIF2ADCL_ENA
|
1171 WM8994_AIF2ADCR_ENA
, adc
);
1172 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1173 WM8994_AIF2DACL_ENA
|
1174 WM8994_AIF2DACR_ENA
, dac
);
1175 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
1176 WM8994_AIF2DSPCLK_ENA
|
1177 WM8994_SYSDSPCLK_ENA
,
1178 WM8994_AIF2DSPCLK_ENA
|
1179 WM8994_SYSDSPCLK_ENA
);
1180 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
,
1181 WM8994_AIF2ADCL_ENA
|
1182 WM8994_AIF2ADCR_ENA
,
1183 WM8994_AIF2ADCL_ENA
|
1184 WM8994_AIF2ADCR_ENA
);
1185 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1186 WM8994_AIF2DACL_ENA
|
1187 WM8994_AIF2DACR_ENA
,
1188 WM8994_AIF2DACL_ENA
|
1189 WM8994_AIF2DACR_ENA
);
1192 case SND_SOC_DAPM_POST_PMU
:
1193 for (i
= 0; i
< ARRAY_SIZE(wm8994_vu_bits
); i
++)
1194 snd_soc_write(codec
, wm8994_vu_bits
[i
].reg
,
1196 wm8994_vu_bits
[i
].reg
));
1199 case SND_SOC_DAPM_PRE_PMD
:
1200 case SND_SOC_DAPM_POST_PMD
:
1201 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1202 WM8994_AIF2DACL_ENA
|
1203 WM8994_AIF2DACR_ENA
, 0);
1204 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
,
1205 WM8994_AIF2ADCL_ENA
|
1206 WM8994_AIF2ADCR_ENA
, 0);
1208 val
= snd_soc_read(codec
, WM8994_CLOCKING_1
);
1209 if (val
& WM8994_AIF1DSPCLK_ENA
)
1210 val
= WM8994_SYSDSPCLK_ENA
;
1213 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
1214 WM8994_SYSDSPCLK_ENA
|
1215 WM8994_AIF2DSPCLK_ENA
, val
);
1222 static int aif1clk_late_ev(struct snd_soc_dapm_widget
*w
,
1223 struct snd_kcontrol
*kcontrol
, int event
)
1225 struct snd_soc_codec
*codec
= w
->codec
;
1226 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1229 case SND_SOC_DAPM_PRE_PMU
:
1230 wm8994
->aif1clk_enable
= 1;
1232 case SND_SOC_DAPM_POST_PMD
:
1233 wm8994
->aif1clk_disable
= 1;
1240 static int aif2clk_late_ev(struct snd_soc_dapm_widget
*w
,
1241 struct snd_kcontrol
*kcontrol
, int event
)
1243 struct snd_soc_codec
*codec
= w
->codec
;
1244 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1247 case SND_SOC_DAPM_PRE_PMU
:
1248 wm8994
->aif2clk_enable
= 1;
1250 case SND_SOC_DAPM_POST_PMD
:
1251 wm8994
->aif2clk_disable
= 1;
1258 static int late_enable_ev(struct snd_soc_dapm_widget
*w
,
1259 struct snd_kcontrol
*kcontrol
, int event
)
1261 struct snd_soc_codec
*codec
= w
->codec
;
1262 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1265 case SND_SOC_DAPM_PRE_PMU
:
1266 if (wm8994
->aif1clk_enable
) {
1267 aif1clk_ev(w
, kcontrol
, SND_SOC_DAPM_PRE_PMU
);
1268 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
1269 WM8994_AIF1CLK_ENA_MASK
,
1270 WM8994_AIF1CLK_ENA
);
1271 aif1clk_ev(w
, kcontrol
, SND_SOC_DAPM_POST_PMU
);
1272 wm8994
->aif1clk_enable
= 0;
1274 if (wm8994
->aif2clk_enable
) {
1275 aif2clk_ev(w
, kcontrol
, SND_SOC_DAPM_PRE_PMU
);
1276 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
1277 WM8994_AIF2CLK_ENA_MASK
,
1278 WM8994_AIF2CLK_ENA
);
1279 aif2clk_ev(w
, kcontrol
, SND_SOC_DAPM_POST_PMU
);
1280 wm8994
->aif2clk_enable
= 0;
1285 /* We may also have postponed startup of DSP, handle that. */
1286 wm8958_aif_ev(w
, kcontrol
, event
);
1291 static int late_disable_ev(struct snd_soc_dapm_widget
*w
,
1292 struct snd_kcontrol
*kcontrol
, int event
)
1294 struct snd_soc_codec
*codec
= w
->codec
;
1295 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1298 case SND_SOC_DAPM_POST_PMD
:
1299 if (wm8994
->aif1clk_disable
) {
1300 aif1clk_ev(w
, kcontrol
, SND_SOC_DAPM_PRE_PMD
);
1301 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
1302 WM8994_AIF1CLK_ENA_MASK
, 0);
1303 aif1clk_ev(w
, kcontrol
, SND_SOC_DAPM_POST_PMD
);
1304 wm8994
->aif1clk_disable
= 0;
1306 if (wm8994
->aif2clk_disable
) {
1307 aif2clk_ev(w
, kcontrol
, SND_SOC_DAPM_PRE_PMD
);
1308 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
1309 WM8994_AIF2CLK_ENA_MASK
, 0);
1310 aif2clk_ev(w
, kcontrol
, SND_SOC_DAPM_POST_PMD
);
1311 wm8994
->aif2clk_disable
= 0;
1319 static int adc_mux_ev(struct snd_soc_dapm_widget
*w
,
1320 struct snd_kcontrol
*kcontrol
, int event
)
1322 late_enable_ev(w
, kcontrol
, event
);
1326 static int micbias_ev(struct snd_soc_dapm_widget
*w
,
1327 struct snd_kcontrol
*kcontrol
, int event
)
1329 late_enable_ev(w
, kcontrol
, event
);
1333 static int dac_ev(struct snd_soc_dapm_widget
*w
,
1334 struct snd_kcontrol
*kcontrol
, int event
)
1336 struct snd_soc_codec
*codec
= w
->codec
;
1337 unsigned int mask
= 1 << w
->shift
;
1339 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1344 static const char *adc_mux_text
[] = {
1349 static const struct soc_enum adc_enum
=
1350 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text
);
1352 static const struct snd_kcontrol_new adcl_mux
=
1353 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum
);
1355 static const struct snd_kcontrol_new adcr_mux
=
1356 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum
);
1358 static const struct snd_kcontrol_new left_speaker_mixer
[] = {
1359 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER
, 9, 1, 0),
1360 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER
, 7, 1, 0),
1361 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER
, 5, 1, 0),
1362 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER
, 3, 1, 0),
1363 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER
, 1, 1, 0),
1366 static const struct snd_kcontrol_new right_speaker_mixer
[] = {
1367 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER
, 8, 1, 0),
1368 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER
, 6, 1, 0),
1369 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER
, 4, 1, 0),
1370 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER
, 2, 1, 0),
1371 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER
, 0, 1, 0),
1374 /* Debugging; dump chip status after DAPM transitions */
1375 static int post_ev(struct snd_soc_dapm_widget
*w
,
1376 struct snd_kcontrol
*kcontrol
, int event
)
1378 struct snd_soc_codec
*codec
= w
->codec
;
1379 dev_dbg(codec
->dev
, "SRC status: %x\n",
1381 WM8994_RATE_STATUS
));
1385 static const struct snd_kcontrol_new aif1adc1l_mix
[] = {
1386 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING
,
1388 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING
,
1392 static const struct snd_kcontrol_new aif1adc1r_mix
[] = {
1393 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING
,
1395 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING
,
1399 static const struct snd_kcontrol_new aif1adc2l_mix
[] = {
1400 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING
,
1402 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING
,
1406 static const struct snd_kcontrol_new aif1adc2r_mix
[] = {
1407 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING
,
1409 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING
,
1413 static const struct snd_kcontrol_new aif2dac2l_mix
[] = {
1414 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1416 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1418 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1420 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1422 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1426 static const struct snd_kcontrol_new aif2dac2r_mix
[] = {
1427 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1429 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1431 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1433 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1435 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1439 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1440 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1441 .info = snd_soc_info_volsw, \
1442 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1443 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1445 static int wm8994_put_class_w(struct snd_kcontrol
*kcontrol
,
1446 struct snd_ctl_elem_value
*ucontrol
)
1448 struct snd_soc_dapm_widget_list
*wlist
= snd_kcontrol_chip(kcontrol
);
1449 struct snd_soc_dapm_widget
*w
= wlist
->widgets
[0];
1450 struct snd_soc_codec
*codec
= w
->codec
;
1453 ret
= snd_soc_dapm_put_volsw(kcontrol
, ucontrol
);
1455 wm_hubs_update_class_w(codec
);
1460 static const struct snd_kcontrol_new dac1l_mix
[] = {
1461 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1463 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1465 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1467 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1469 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1473 static const struct snd_kcontrol_new dac1r_mix
[] = {
1474 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1476 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1478 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1480 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1482 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1486 static const char *sidetone_text
[] = {
1487 "ADC/DMIC1", "DMIC2",
1490 static const struct soc_enum sidetone1_enum
=
1491 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 0, 2, sidetone_text
);
1493 static const struct snd_kcontrol_new sidetone1_mux
=
1494 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum
);
1496 static const struct soc_enum sidetone2_enum
=
1497 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 1, 2, sidetone_text
);
1499 static const struct snd_kcontrol_new sidetone2_mux
=
1500 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum
);
1502 static const char *aif1dac_text
[] = {
1503 "AIF1DACDAT", "AIF3DACDAT",
1506 static const struct soc_enum aif1dac_enum
=
1507 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 0, 2, aif1dac_text
);
1509 static const struct snd_kcontrol_new aif1dac_mux
=
1510 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum
);
1512 static const char *aif2dac_text
[] = {
1513 "AIF2DACDAT", "AIF3DACDAT",
1516 static const struct soc_enum aif2dac_enum
=
1517 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 1, 2, aif2dac_text
);
1519 static const struct snd_kcontrol_new aif2dac_mux
=
1520 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum
);
1522 static const char *aif2adc_text
[] = {
1523 "AIF2ADCDAT", "AIF3DACDAT",
1526 static const struct soc_enum aif2adc_enum
=
1527 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 2, 2, aif2adc_text
);
1529 static const struct snd_kcontrol_new aif2adc_mux
=
1530 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum
);
1532 static const char *aif3adc_text
[] = {
1533 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1536 static const struct soc_enum wm8994_aif3adc_enum
=
1537 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 3, 3, aif3adc_text
);
1539 static const struct snd_kcontrol_new wm8994_aif3adc_mux
=
1540 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum
);
1542 static const struct soc_enum wm8958_aif3adc_enum
=
1543 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 3, 4, aif3adc_text
);
1545 static const struct snd_kcontrol_new wm8958_aif3adc_mux
=
1546 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum
);
1548 static const char *mono_pcm_out_text
[] = {
1549 "None", "AIF2ADCL", "AIF2ADCR",
1552 static const struct soc_enum mono_pcm_out_enum
=
1553 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 9, 3, mono_pcm_out_text
);
1555 static const struct snd_kcontrol_new mono_pcm_out_mux
=
1556 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum
);
1558 static const char *aif2dac_src_text
[] = {
1562 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1563 static const struct soc_enum aif2dacl_src_enum
=
1564 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 7, 2, aif2dac_src_text
);
1566 static const struct snd_kcontrol_new aif2dacl_src_mux
=
1567 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum
);
1569 static const struct soc_enum aif2dacr_src_enum
=
1570 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 8, 2, aif2dac_src_text
);
1572 static const struct snd_kcontrol_new aif2dacr_src_mux
=
1573 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum
);
1575 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets
[] = {
1576 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM
, 0, 0, aif1clk_late_ev
,
1577 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1578 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM
, 0, 0, aif2clk_late_ev
,
1579 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1581 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1582 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1583 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1584 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1585 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1586 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1587 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1588 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1589 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1590 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1592 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3
, 8, 0,
1593 left_speaker_mixer
, ARRAY_SIZE(left_speaker_mixer
),
1594 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1595 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3
, 9, 0,
1596 right_speaker_mixer
, ARRAY_SIZE(right_speaker_mixer
),
1597 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1598 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM
, 0, 0, &wm_hubs_hpl_mux
,
1599 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1600 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM
, 0, 0, &wm_hubs_hpr_mux
,
1601 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1603 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev
)
1606 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets
[] = {
1607 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1
, 0, 0, aif1clk_ev
,
1608 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMU
|
1609 SND_SOC_DAPM_PRE_PMD
),
1610 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1
, 0, 0, aif2clk_ev
,
1611 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMU
|
1612 SND_SOC_DAPM_PRE_PMD
),
1613 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM
, 0, 0, NULL
, 0),
1614 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3
, 8, 0,
1615 left_speaker_mixer
, ARRAY_SIZE(left_speaker_mixer
)),
1616 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3
, 9, 0,
1617 right_speaker_mixer
, ARRAY_SIZE(right_speaker_mixer
)),
1618 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM
, 0, 0, &wm_hubs_hpl_mux
),
1619 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM
, 0, 0, &wm_hubs_hpr_mux
),
1622 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets
[] = {
1623 SND_SOC_DAPM_DAC_E("DAC2L", NULL
, SND_SOC_NOPM
, 3, 0,
1624 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1625 SND_SOC_DAPM_DAC_E("DAC2R", NULL
, SND_SOC_NOPM
, 2, 0,
1626 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1627 SND_SOC_DAPM_DAC_E("DAC1L", NULL
, SND_SOC_NOPM
, 1, 0,
1628 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1629 SND_SOC_DAPM_DAC_E("DAC1R", NULL
, SND_SOC_NOPM
, 0, 0,
1630 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1633 static const struct snd_soc_dapm_widget wm8994_dac_widgets
[] = {
1634 SND_SOC_DAPM_DAC("DAC2L", NULL
, WM8994_POWER_MANAGEMENT_5
, 3, 0),
1635 SND_SOC_DAPM_DAC("DAC2R", NULL
, WM8994_POWER_MANAGEMENT_5
, 2, 0),
1636 SND_SOC_DAPM_DAC("DAC1L", NULL
, WM8994_POWER_MANAGEMENT_5
, 1, 0),
1637 SND_SOC_DAPM_DAC("DAC1R", NULL
, WM8994_POWER_MANAGEMENT_5
, 0, 0),
1640 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets
[] = {
1641 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4
, 1, 0, &adcl_mux
,
1642 adc_mux_ev
, SND_SOC_DAPM_PRE_PMU
),
1643 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4
, 0, 0, &adcr_mux
,
1644 adc_mux_ev
, SND_SOC_DAPM_PRE_PMU
),
1647 static const struct snd_soc_dapm_widget wm8994_adc_widgets
[] = {
1648 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4
, 1, 0, &adcl_mux
),
1649 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4
, 0, 0, &adcr_mux
),
1652 static const struct snd_soc_dapm_widget wm8994_dapm_widgets
[] = {
1653 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1654 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1655 SND_SOC_DAPM_INPUT("Clock"),
1657 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM
, 0, 0, micbias_ev
,
1658 SND_SOC_DAPM_PRE_PMU
),
1659 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM
, 0, 0, vmid_event
,
1660 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1662 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM
, 0, 0, clk_sys_event
,
1663 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMU
|
1664 SND_SOC_DAPM_PRE_PMD
),
1666 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM
, 3, 0, NULL
, 0),
1667 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM
, 2, 0, NULL
, 0),
1668 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM
, 1, 0, NULL
, 0),
1670 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL
,
1671 0, SND_SOC_NOPM
, 9, 0),
1672 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL
,
1673 0, SND_SOC_NOPM
, 8, 0),
1674 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL
, 0,
1675 SND_SOC_NOPM
, 9, 0, wm8958_aif_ev
,
1676 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1677 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL
, 0,
1678 SND_SOC_NOPM
, 8, 0, wm8958_aif_ev
,
1679 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1681 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL
,
1682 0, SND_SOC_NOPM
, 11, 0),
1683 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL
,
1684 0, SND_SOC_NOPM
, 10, 0),
1685 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL
, 0,
1686 SND_SOC_NOPM
, 11, 0, wm8958_aif_ev
,
1687 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1688 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL
, 0,
1689 SND_SOC_NOPM
, 10, 0, wm8958_aif_ev
,
1690 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1692 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM
, 0, 0,
1693 aif1adc1l_mix
, ARRAY_SIZE(aif1adc1l_mix
)),
1694 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM
, 0, 0,
1695 aif1adc1r_mix
, ARRAY_SIZE(aif1adc1r_mix
)),
1697 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM
, 0, 0,
1698 aif1adc2l_mix
, ARRAY_SIZE(aif1adc2l_mix
)),
1699 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM
, 0, 0,
1700 aif1adc2r_mix
, ARRAY_SIZE(aif1adc2r_mix
)),
1702 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM
, 0, 0,
1703 aif2dac2l_mix
, ARRAY_SIZE(aif2dac2l_mix
)),
1704 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM
, 0, 0,
1705 aif2dac2r_mix
, ARRAY_SIZE(aif2dac2r_mix
)),
1707 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM
, 0, 0, &sidetone1_mux
),
1708 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM
, 0, 0, &sidetone2_mux
),
1710 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM
, 0, 0,
1711 dac1l_mix
, ARRAY_SIZE(dac1l_mix
)),
1712 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM
, 0, 0,
1713 dac1r_mix
, ARRAY_SIZE(dac1r_mix
)),
1715 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL
, 0,
1716 SND_SOC_NOPM
, 13, 0),
1717 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL
, 0,
1718 SND_SOC_NOPM
, 12, 0),
1719 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL
, 0,
1720 SND_SOC_NOPM
, 13, 0, wm8958_aif_ev
,
1721 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1722 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL
, 0,
1723 SND_SOC_NOPM
, 12, 0, wm8958_aif_ev
,
1724 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1726 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1727 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1728 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1729 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1731 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM
, 0, 0, &aif1dac_mux
),
1732 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM
, 0, 0, &aif2dac_mux
),
1733 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM
, 0, 0, &aif2adc_mux
),
1735 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1736 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1738 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1
, 4, 0, NULL
, 0),
1740 SND_SOC_DAPM_ADC("DMIC2L", NULL
, WM8994_POWER_MANAGEMENT_4
, 5, 0),
1741 SND_SOC_DAPM_ADC("DMIC2R", NULL
, WM8994_POWER_MANAGEMENT_4
, 4, 0),
1742 SND_SOC_DAPM_ADC("DMIC1L", NULL
, WM8994_POWER_MANAGEMENT_4
, 3, 0),
1743 SND_SOC_DAPM_ADC("DMIC1R", NULL
, WM8994_POWER_MANAGEMENT_4
, 2, 0),
1745 /* Power is done with the muxes since the ADC power also controls the
1746 * downsampling chain, the chip will automatically manage the analogue
1747 * specific portions.
1749 SND_SOC_DAPM_ADC("ADCL", NULL
, SND_SOC_NOPM
, 1, 0),
1750 SND_SOC_DAPM_ADC("ADCR", NULL
, SND_SOC_NOPM
, 0, 0),
1752 SND_SOC_DAPM_POST("Debug log", post_ev
),
1755 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets
[] = {
1756 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM
, 0, 0, &wm8994_aif3adc_mux
),
1759 static const struct snd_soc_dapm_widget wm8958_dapm_widgets
[] = {
1760 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6
, 5, 1, NULL
, 0),
1761 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM
, 0, 0, &mono_pcm_out_mux
),
1762 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM
, 0, 0, &aif2dacl_src_mux
),
1763 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM
, 0, 0, &aif2dacr_src_mux
),
1764 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM
, 0, 0, &wm8958_aif3adc_mux
),
1767 static const struct snd_soc_dapm_route intercon
[] = {
1768 { "CLK_SYS", NULL
, "AIF1CLK", check_clk_sys
},
1769 { "CLK_SYS", NULL
, "AIF2CLK", check_clk_sys
},
1771 { "DSP1CLK", NULL
, "CLK_SYS" },
1772 { "DSP2CLK", NULL
, "CLK_SYS" },
1773 { "DSPINTCLK", NULL
, "CLK_SYS" },
1775 { "AIF1ADC1L", NULL
, "AIF1CLK" },
1776 { "AIF1ADC1L", NULL
, "DSP1CLK" },
1777 { "AIF1ADC1R", NULL
, "AIF1CLK" },
1778 { "AIF1ADC1R", NULL
, "DSP1CLK" },
1779 { "AIF1ADC1R", NULL
, "DSPINTCLK" },
1781 { "AIF1DAC1L", NULL
, "AIF1CLK" },
1782 { "AIF1DAC1L", NULL
, "DSP1CLK" },
1783 { "AIF1DAC1R", NULL
, "AIF1CLK" },
1784 { "AIF1DAC1R", NULL
, "DSP1CLK" },
1785 { "AIF1DAC1R", NULL
, "DSPINTCLK" },
1787 { "AIF1ADC2L", NULL
, "AIF1CLK" },
1788 { "AIF1ADC2L", NULL
, "DSP1CLK" },
1789 { "AIF1ADC2R", NULL
, "AIF1CLK" },
1790 { "AIF1ADC2R", NULL
, "DSP1CLK" },
1791 { "AIF1ADC2R", NULL
, "DSPINTCLK" },
1793 { "AIF1DAC2L", NULL
, "AIF1CLK" },
1794 { "AIF1DAC2L", NULL
, "DSP1CLK" },
1795 { "AIF1DAC2R", NULL
, "AIF1CLK" },
1796 { "AIF1DAC2R", NULL
, "DSP1CLK" },
1797 { "AIF1DAC2R", NULL
, "DSPINTCLK" },
1799 { "AIF2ADCL", NULL
, "AIF2CLK" },
1800 { "AIF2ADCL", NULL
, "DSP2CLK" },
1801 { "AIF2ADCR", NULL
, "AIF2CLK" },
1802 { "AIF2ADCR", NULL
, "DSP2CLK" },
1803 { "AIF2ADCR", NULL
, "DSPINTCLK" },
1805 { "AIF2DACL", NULL
, "AIF2CLK" },
1806 { "AIF2DACL", NULL
, "DSP2CLK" },
1807 { "AIF2DACR", NULL
, "AIF2CLK" },
1808 { "AIF2DACR", NULL
, "DSP2CLK" },
1809 { "AIF2DACR", NULL
, "DSPINTCLK" },
1811 { "DMIC1L", NULL
, "DMIC1DAT" },
1812 { "DMIC1L", NULL
, "CLK_SYS" },
1813 { "DMIC1R", NULL
, "DMIC1DAT" },
1814 { "DMIC1R", NULL
, "CLK_SYS" },
1815 { "DMIC2L", NULL
, "DMIC2DAT" },
1816 { "DMIC2L", NULL
, "CLK_SYS" },
1817 { "DMIC2R", NULL
, "DMIC2DAT" },
1818 { "DMIC2R", NULL
, "CLK_SYS" },
1820 { "ADCL", NULL
, "AIF1CLK" },
1821 { "ADCL", NULL
, "DSP1CLK" },
1822 { "ADCL", NULL
, "DSPINTCLK" },
1824 { "ADCR", NULL
, "AIF1CLK" },
1825 { "ADCR", NULL
, "DSP1CLK" },
1826 { "ADCR", NULL
, "DSPINTCLK" },
1828 { "ADCL Mux", "ADC", "ADCL" },
1829 { "ADCL Mux", "DMIC", "DMIC1L" },
1830 { "ADCR Mux", "ADC", "ADCR" },
1831 { "ADCR Mux", "DMIC", "DMIC1R" },
1833 { "DAC1L", NULL
, "AIF1CLK" },
1834 { "DAC1L", NULL
, "DSP1CLK" },
1835 { "DAC1L", NULL
, "DSPINTCLK" },
1837 { "DAC1R", NULL
, "AIF1CLK" },
1838 { "DAC1R", NULL
, "DSP1CLK" },
1839 { "DAC1R", NULL
, "DSPINTCLK" },
1841 { "DAC2L", NULL
, "AIF2CLK" },
1842 { "DAC2L", NULL
, "DSP2CLK" },
1843 { "DAC2L", NULL
, "DSPINTCLK" },
1845 { "DAC2R", NULL
, "AIF2DACR" },
1846 { "DAC2R", NULL
, "AIF2CLK" },
1847 { "DAC2R", NULL
, "DSP2CLK" },
1848 { "DAC2R", NULL
, "DSPINTCLK" },
1850 { "TOCLK", NULL
, "CLK_SYS" },
1852 { "AIF1DACDAT", NULL
, "AIF1 Playback" },
1853 { "AIF2DACDAT", NULL
, "AIF2 Playback" },
1854 { "AIF3DACDAT", NULL
, "AIF3 Playback" },
1856 { "AIF1 Capture", NULL
, "AIF1ADCDAT" },
1857 { "AIF2 Capture", NULL
, "AIF2ADCDAT" },
1858 { "AIF3 Capture", NULL
, "AIF3ADCDAT" },
1861 { "AIF1ADC1L", NULL
, "AIF1ADC1L Mixer" },
1862 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1863 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1865 { "AIF1ADC1R", NULL
, "AIF1ADC1R Mixer" },
1866 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1867 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1869 { "AIF1ADC2L", NULL
, "AIF1ADC2L Mixer" },
1870 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1871 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1873 { "AIF1ADC2R", NULL
, "AIF1ADC2R Mixer" },
1874 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1875 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1877 /* Pin level routing for AIF3 */
1878 { "AIF1DAC1L", NULL
, "AIF1DAC Mux" },
1879 { "AIF1DAC1R", NULL
, "AIF1DAC Mux" },
1880 { "AIF1DAC2L", NULL
, "AIF1DAC Mux" },
1881 { "AIF1DAC2R", NULL
, "AIF1DAC Mux" },
1883 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1884 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1885 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1886 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1887 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1888 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1889 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1892 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1893 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1894 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1895 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1896 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1898 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1899 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1900 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1901 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1902 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1904 /* DAC2/AIF2 outputs */
1905 { "AIF2ADCL", NULL
, "AIF2DAC2L Mixer" },
1906 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1907 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1908 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1909 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1910 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1912 { "AIF2ADCR", NULL
, "AIF2DAC2R Mixer" },
1913 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1914 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1915 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1916 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1917 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1919 { "AIF1ADCDAT", NULL
, "AIF1ADC1L" },
1920 { "AIF1ADCDAT", NULL
, "AIF1ADC1R" },
1921 { "AIF1ADCDAT", NULL
, "AIF1ADC2L" },
1922 { "AIF1ADCDAT", NULL
, "AIF1ADC2R" },
1924 { "AIF2ADCDAT", NULL
, "AIF2ADC Mux" },
1927 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1928 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1929 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1930 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1931 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1932 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1933 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1934 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1937 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1938 { "Left Sidetone", "DMIC2", "DMIC2L" },
1939 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1940 { "Right Sidetone", "DMIC2", "DMIC2R" },
1943 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1944 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1946 { "SPKL", "DAC1 Switch", "DAC1L" },
1947 { "SPKL", "DAC2 Switch", "DAC2L" },
1949 { "SPKR", "DAC1 Switch", "DAC1R" },
1950 { "SPKR", "DAC2 Switch", "DAC2R" },
1952 { "Left Headphone Mux", "DAC", "DAC1L" },
1953 { "Right Headphone Mux", "DAC", "DAC1R" },
1956 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon
[] = {
1957 { "DAC1L", NULL
, "Late DAC1L Enable PGA" },
1958 { "Late DAC1L Enable PGA", NULL
, "DAC1L Mixer" },
1959 { "DAC1R", NULL
, "Late DAC1R Enable PGA" },
1960 { "Late DAC1R Enable PGA", NULL
, "DAC1R Mixer" },
1961 { "DAC2L", NULL
, "Late DAC2L Enable PGA" },
1962 { "Late DAC2L Enable PGA", NULL
, "AIF2DAC2L Mixer" },
1963 { "DAC2R", NULL
, "Late DAC2R Enable PGA" },
1964 { "Late DAC2R Enable PGA", NULL
, "AIF2DAC2R Mixer" }
1967 static const struct snd_soc_dapm_route wm8994_lateclk_intercon
[] = {
1968 { "DAC1L", NULL
, "DAC1L Mixer" },
1969 { "DAC1R", NULL
, "DAC1R Mixer" },
1970 { "DAC2L", NULL
, "AIF2DAC2L Mixer" },
1971 { "DAC2R", NULL
, "AIF2DAC2R Mixer" },
1974 static const struct snd_soc_dapm_route wm8994_revd_intercon
[] = {
1975 { "AIF1DACDAT", NULL
, "AIF2DACDAT" },
1976 { "AIF2DACDAT", NULL
, "AIF1DACDAT" },
1977 { "AIF1ADCDAT", NULL
, "AIF2ADCDAT" },
1978 { "AIF2ADCDAT", NULL
, "AIF1ADCDAT" },
1979 { "MICBIAS1", NULL
, "CLK_SYS" },
1980 { "MICBIAS1", NULL
, "MICBIAS Supply" },
1981 { "MICBIAS2", NULL
, "CLK_SYS" },
1982 { "MICBIAS2", NULL
, "MICBIAS Supply" },
1985 static const struct snd_soc_dapm_route wm8994_intercon
[] = {
1986 { "AIF2DACL", NULL
, "AIF2DAC Mux" },
1987 { "AIF2DACR", NULL
, "AIF2DAC Mux" },
1988 { "MICBIAS1", NULL
, "VMID" },
1989 { "MICBIAS2", NULL
, "VMID" },
1992 static const struct snd_soc_dapm_route wm8958_intercon
[] = {
1993 { "AIF2DACL", NULL
, "AIF2DACL Mux" },
1994 { "AIF2DACR", NULL
, "AIF2DACR Mux" },
1996 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1997 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1998 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1999 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
2001 { "AIF3DACDAT", NULL
, "AIF3" },
2002 { "AIF3ADCDAT", NULL
, "AIF3" },
2004 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
2005 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
2007 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
2010 /* The size in bits of the FLL divide multiplied by 10
2011 * to allow rounding later */
2012 #define FIXED_FLL_SIZE ((1 << 16) * 10)
2022 static int wm8994_get_fll_config(struct fll_div
*fll
,
2023 int freq_in
, int freq_out
)
2026 unsigned int K
, Ndiv
, Nmod
;
2028 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in
, freq_out
);
2030 /* Scale the input frequency down to <= 13.5MHz */
2031 fll
->clk_ref_div
= 0;
2032 while (freq_in
> 13500000) {
2036 if (fll
->clk_ref_div
> 3)
2039 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll
->clk_ref_div
, freq_in
);
2041 /* Scale the output to give 90MHz<=Fvco<=100MHz */
2043 while (freq_out
* (fll
->outdiv
+ 1) < 90000000) {
2045 if (fll
->outdiv
> 63)
2048 freq_out
*= fll
->outdiv
+ 1;
2049 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll
->outdiv
, freq_out
);
2051 if (freq_in
> 1000000) {
2052 fll
->fll_fratio
= 0;
2053 } else if (freq_in
> 256000) {
2054 fll
->fll_fratio
= 1;
2056 } else if (freq_in
> 128000) {
2057 fll
->fll_fratio
= 2;
2059 } else if (freq_in
> 64000) {
2060 fll
->fll_fratio
= 3;
2063 fll
->fll_fratio
= 4;
2066 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll
->fll_fratio
, freq_in
);
2068 /* Now, calculate N.K */
2069 Ndiv
= freq_out
/ freq_in
;
2072 Nmod
= freq_out
% freq_in
;
2073 pr_debug("Nmod=%d\n", Nmod
);
2075 /* Calculate fractional part - scale up so we can round. */
2076 Kpart
= FIXED_FLL_SIZE
* (long long)Nmod
;
2078 do_div(Kpart
, freq_in
);
2080 K
= Kpart
& 0xFFFFFFFF;
2085 /* Move down to proper range now rounding is done */
2088 pr_debug("N=%x K=%x\n", fll
->n
, fll
->k
);
2093 static int _wm8994_set_fll(struct snd_soc_codec
*codec
, int id
, int src
,
2094 unsigned int freq_in
, unsigned int freq_out
)
2096 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2097 struct wm8994
*control
= wm8994
->wm8994
;
2098 int reg_offset
, ret
;
2100 u16 reg
, clk1
, aif_reg
, aif_src
;
2101 unsigned long timeout
;
2119 reg
= snd_soc_read(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
);
2120 was_enabled
= reg
& WM8994_FLL1_ENA
;
2124 /* Allow no source specification when stopping */
2127 src
= wm8994
->fll
[id
].src
;
2129 case WM8994_FLL_SRC_MCLK1
:
2130 case WM8994_FLL_SRC_MCLK2
:
2131 case WM8994_FLL_SRC_LRCLK
:
2132 case WM8994_FLL_SRC_BCLK
:
2134 case WM8994_FLL_SRC_INTERNAL
:
2136 freq_out
= 12000000;
2142 /* Are we changing anything? */
2143 if (wm8994
->fll
[id
].src
== src
&&
2144 wm8994
->fll
[id
].in
== freq_in
&& wm8994
->fll
[id
].out
== freq_out
)
2147 /* If we're stopping the FLL redo the old config - no
2148 * registers will actually be written but we avoid GCC flow
2149 * analysis bugs spewing warnings.
2152 ret
= wm8994_get_fll_config(&fll
, freq_in
, freq_out
);
2154 ret
= wm8994_get_fll_config(&fll
, wm8994
->fll
[id
].in
,
2155 wm8994
->fll
[id
].out
);
2159 /* Make sure that we're not providing SYSCLK right now */
2160 clk1
= snd_soc_read(codec
, WM8994_CLOCKING_1
);
2161 if (clk1
& WM8994_SYSCLK_SRC
)
2162 aif_reg
= WM8994_AIF2_CLOCKING_1
;
2164 aif_reg
= WM8994_AIF1_CLOCKING_1
;
2165 reg
= snd_soc_read(codec
, aif_reg
);
2167 if ((reg
& WM8994_AIF1CLK_ENA
) &&
2168 (reg
& WM8994_AIF1CLK_SRC_MASK
) == aif_src
) {
2169 dev_err(codec
->dev
, "FLL%d is currently providing SYSCLK\n",
2174 /* We always need to disable the FLL while reconfiguring */
2175 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
,
2176 WM8994_FLL1_ENA
, 0);
2178 if (wm8994
->fll_byp
&& src
== WM8994_FLL_SRC_BCLK
&&
2179 freq_in
== freq_out
&& freq_out
) {
2180 dev_dbg(codec
->dev
, "Bypassing FLL%d\n", id
+ 1);
2181 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_5
+ reg_offset
,
2182 WM8958_FLL1_BYP
, WM8958_FLL1_BYP
);
2186 reg
= (fll
.outdiv
<< WM8994_FLL1_OUTDIV_SHIFT
) |
2187 (fll
.fll_fratio
<< WM8994_FLL1_FRATIO_SHIFT
);
2188 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_2
+ reg_offset
,
2189 WM8994_FLL1_OUTDIV_MASK
|
2190 WM8994_FLL1_FRATIO_MASK
, reg
);
2192 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_3
+ reg_offset
,
2193 WM8994_FLL1_K_MASK
, fll
.k
);
2195 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_4
+ reg_offset
,
2197 fll
.n
<< WM8994_FLL1_N_SHIFT
);
2199 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_5
+ reg_offset
,
2200 WM8994_FLL1_FRC_NCO
| WM8958_FLL1_BYP
|
2201 WM8994_FLL1_REFCLK_DIV_MASK
|
2202 WM8994_FLL1_REFCLK_SRC_MASK
,
2203 ((src
== WM8994_FLL_SRC_INTERNAL
)
2204 << WM8994_FLL1_FRC_NCO_SHIFT
) |
2205 (fll
.clk_ref_div
<< WM8994_FLL1_REFCLK_DIV_SHIFT
) |
2208 /* Clear any pending completion from a previous failure */
2209 try_wait_for_completion(&wm8994
->fll_locked
[id
]);
2211 /* Enable (with fractional mode if required) */
2213 /* Enable VMID if we need it */
2215 active_reference(codec
);
2217 switch (control
->type
) {
2219 vmid_reference(codec
);
2222 if (wm8994
->revision
< 1)
2223 vmid_reference(codec
);
2230 reg
= WM8994_FLL1_ENA
;
2233 reg
|= WM8994_FLL1_FRAC
;
2234 if (src
== WM8994_FLL_SRC_INTERNAL
)
2235 reg
|= WM8994_FLL1_OSC_ENA
;
2237 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
,
2238 WM8994_FLL1_ENA
| WM8994_FLL1_OSC_ENA
|
2239 WM8994_FLL1_FRAC
, reg
);
2241 if (wm8994
->fll_locked_irq
) {
2242 timeout
= wait_for_completion_timeout(&wm8994
->fll_locked
[id
],
2243 msecs_to_jiffies(10));
2245 dev_warn(codec
->dev
,
2246 "Timed out waiting for FLL lock\n");
2252 switch (control
->type
) {
2254 vmid_dereference(codec
);
2257 if (wm8994
->revision
< 1)
2258 vmid_dereference(codec
);
2264 active_dereference(codec
);
2269 wm8994
->fll
[id
].in
= freq_in
;
2270 wm8994
->fll
[id
].out
= freq_out
;
2271 wm8994
->fll
[id
].src
= src
;
2273 configure_clock(codec
);
2278 static irqreturn_t
wm8994_fll_locked_irq(int irq
, void *data
)
2280 struct completion
*completion
= data
;
2282 complete(completion
);
2287 static int opclk_divs
[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2289 static int wm8994_set_fll(struct snd_soc_dai
*dai
, int id
, int src
,
2290 unsigned int freq_in
, unsigned int freq_out
)
2292 return _wm8994_set_fll(dai
->codec
, id
, src
, freq_in
, freq_out
);
2295 static int wm8994_set_dai_sysclk(struct snd_soc_dai
*dai
,
2296 int clk_id
, unsigned int freq
, int dir
)
2298 struct snd_soc_codec
*codec
= dai
->codec
;
2299 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2308 /* AIF3 shares clocking with AIF1/2 */
2313 case WM8994_SYSCLK_MCLK1
:
2314 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_MCLK1
;
2315 wm8994
->mclk
[0] = freq
;
2316 dev_dbg(dai
->dev
, "AIF%d using MCLK1 at %uHz\n",
2320 case WM8994_SYSCLK_MCLK2
:
2321 /* TODO: Set GPIO AF */
2322 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_MCLK2
;
2323 wm8994
->mclk
[1] = freq
;
2324 dev_dbg(dai
->dev
, "AIF%d using MCLK2 at %uHz\n",
2328 case WM8994_SYSCLK_FLL1
:
2329 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_FLL1
;
2330 dev_dbg(dai
->dev
, "AIF%d using FLL1\n", dai
->id
);
2333 case WM8994_SYSCLK_FLL2
:
2334 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_FLL2
;
2335 dev_dbg(dai
->dev
, "AIF%d using FLL2\n", dai
->id
);
2338 case WM8994_SYSCLK_OPCLK
:
2339 /* Special case - a division (times 10) is given and
2340 * no effect on main clocking.
2343 for (i
= 0; i
< ARRAY_SIZE(opclk_divs
); i
++)
2344 if (opclk_divs
[i
] == freq
)
2346 if (i
== ARRAY_SIZE(opclk_divs
))
2348 snd_soc_update_bits(codec
, WM8994_CLOCKING_2
,
2349 WM8994_OPCLK_DIV_MASK
, i
);
2350 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_2
,
2351 WM8994_OPCLK_ENA
, WM8994_OPCLK_ENA
);
2353 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_2
,
2354 WM8994_OPCLK_ENA
, 0);
2361 configure_clock(codec
);
2366 static int wm8994_set_bias_level(struct snd_soc_codec
*codec
,
2367 enum snd_soc_bias_level level
)
2369 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2370 struct wm8994
*control
= wm8994
->wm8994
;
2372 wm_hubs_set_bias_level(codec
, level
);
2375 case SND_SOC_BIAS_ON
:
2378 case SND_SOC_BIAS_PREPARE
:
2379 /* MICBIAS into regulating mode */
2380 switch (control
->type
) {
2383 snd_soc_update_bits(codec
, WM8958_MICBIAS1
,
2384 WM8958_MICB1_MODE
, 0);
2385 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
2386 WM8958_MICB2_MODE
, 0);
2392 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_STANDBY
)
2393 active_reference(codec
);
2396 case SND_SOC_BIAS_STANDBY
:
2397 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
2398 switch (control
->type
) {
2400 if (wm8994
->revision
== 0) {
2401 /* Optimise performance for rev A */
2402 snd_soc_update_bits(codec
,
2403 WM8958_CHARGE_PUMP_2
,
2413 /* Discharge LINEOUT1 & 2 */
2414 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
2415 WM8994_LINEOUT1_DISCH
|
2416 WM8994_LINEOUT2_DISCH
,
2417 WM8994_LINEOUT1_DISCH
|
2418 WM8994_LINEOUT2_DISCH
);
2421 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_PREPARE
)
2422 active_dereference(codec
);
2424 /* MICBIAS into bypass mode on newer devices */
2425 switch (control
->type
) {
2428 snd_soc_update_bits(codec
, WM8958_MICBIAS1
,
2431 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
2440 case SND_SOC_BIAS_OFF
:
2441 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_STANDBY
)
2442 wm8994
->cur_fw
= NULL
;
2446 codec
->dapm
.bias_level
= level
;
2451 int wm8994_vmid_mode(struct snd_soc_codec
*codec
, enum wm8994_vmid_mode mode
)
2453 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2456 case WM8994_VMID_NORMAL
:
2457 if (wm8994
->hubs
.lineout1_se
) {
2458 snd_soc_dapm_disable_pin(&codec
->dapm
,
2459 "LINEOUT1N Driver");
2460 snd_soc_dapm_disable_pin(&codec
->dapm
,
2461 "LINEOUT1P Driver");
2463 if (wm8994
->hubs
.lineout2_se
) {
2464 snd_soc_dapm_disable_pin(&codec
->dapm
,
2465 "LINEOUT2N Driver");
2466 snd_soc_dapm_disable_pin(&codec
->dapm
,
2467 "LINEOUT2P Driver");
2470 /* Do the sync with the old mode to allow it to clean up */
2471 snd_soc_dapm_sync(&codec
->dapm
);
2472 wm8994
->vmid_mode
= mode
;
2475 case WM8994_VMID_FORCE
:
2476 if (wm8994
->hubs
.lineout1_se
) {
2477 snd_soc_dapm_force_enable_pin(&codec
->dapm
,
2478 "LINEOUT1N Driver");
2479 snd_soc_dapm_force_enable_pin(&codec
->dapm
,
2480 "LINEOUT1P Driver");
2482 if (wm8994
->hubs
.lineout2_se
) {
2483 snd_soc_dapm_force_enable_pin(&codec
->dapm
,
2484 "LINEOUT2N Driver");
2485 snd_soc_dapm_force_enable_pin(&codec
->dapm
,
2486 "LINEOUT2P Driver");
2489 wm8994
->vmid_mode
= mode
;
2490 snd_soc_dapm_sync(&codec
->dapm
);
2500 static int wm8994_set_dai_fmt(struct snd_soc_dai
*dai
, unsigned int fmt
)
2502 struct snd_soc_codec
*codec
= dai
->codec
;
2503 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2504 struct wm8994
*control
= wm8994
->wm8994
;
2512 ms_reg
= WM8994_AIF1_MASTER_SLAVE
;
2513 aif1_reg
= WM8994_AIF1_CONTROL_1
;
2516 ms_reg
= WM8994_AIF2_MASTER_SLAVE
;
2517 aif1_reg
= WM8994_AIF2_CONTROL_1
;
2523 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
2524 case SND_SOC_DAIFMT_CBS_CFS
:
2526 case SND_SOC_DAIFMT_CBM_CFM
:
2527 ms
= WM8994_AIF1_MSTR
;
2533 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
2534 case SND_SOC_DAIFMT_DSP_B
:
2535 aif1
|= WM8994_AIF1_LRCLK_INV
;
2536 case SND_SOC_DAIFMT_DSP_A
:
2539 case SND_SOC_DAIFMT_I2S
:
2542 case SND_SOC_DAIFMT_RIGHT_J
:
2544 case SND_SOC_DAIFMT_LEFT_J
:
2551 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
2552 case SND_SOC_DAIFMT_DSP_A
:
2553 case SND_SOC_DAIFMT_DSP_B
:
2554 /* frame inversion not valid for DSP modes */
2555 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
2556 case SND_SOC_DAIFMT_NB_NF
:
2558 case SND_SOC_DAIFMT_IB_NF
:
2559 aif1
|= WM8994_AIF1_BCLK_INV
;
2566 case SND_SOC_DAIFMT_I2S
:
2567 case SND_SOC_DAIFMT_RIGHT_J
:
2568 case SND_SOC_DAIFMT_LEFT_J
:
2569 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
2570 case SND_SOC_DAIFMT_NB_NF
:
2572 case SND_SOC_DAIFMT_IB_IF
:
2573 aif1
|= WM8994_AIF1_BCLK_INV
| WM8994_AIF1_LRCLK_INV
;
2575 case SND_SOC_DAIFMT_IB_NF
:
2576 aif1
|= WM8994_AIF1_BCLK_INV
;
2578 case SND_SOC_DAIFMT_NB_IF
:
2579 aif1
|= WM8994_AIF1_LRCLK_INV
;
2589 /* The AIF2 format configuration needs to be mirrored to AIF3
2590 * on WM8958 if it's in use so just do it all the time. */
2591 switch (control
->type
) {
2595 snd_soc_update_bits(codec
, WM8958_AIF3_CONTROL_1
,
2596 WM8994_AIF1_LRCLK_INV
|
2597 WM8958_AIF3_FMT_MASK
, aif1
);
2604 snd_soc_update_bits(codec
, aif1_reg
,
2605 WM8994_AIF1_BCLK_INV
| WM8994_AIF1_LRCLK_INV
|
2606 WM8994_AIF1_FMT_MASK
,
2608 snd_soc_update_bits(codec
, ms_reg
, WM8994_AIF1_MSTR
,
2630 static int fs_ratios
[] = {
2631 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2634 static int bclk_divs
[] = {
2635 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2636 640, 880, 960, 1280, 1760, 1920
2639 static int wm8994_hw_params(struct snd_pcm_substream
*substream
,
2640 struct snd_pcm_hw_params
*params
,
2641 struct snd_soc_dai
*dai
)
2643 struct snd_soc_codec
*codec
= dai
->codec
;
2644 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2655 int id
= dai
->id
- 1;
2657 int i
, cur_val
, best_val
, bclk_rate
, best
;
2661 aif1_reg
= WM8994_AIF1_CONTROL_1
;
2662 aif2_reg
= WM8994_AIF1_CONTROL_2
;
2663 bclk_reg
= WM8994_AIF1_BCLK
;
2664 rate_reg
= WM8994_AIF1_RATE
;
2665 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
||
2666 wm8994
->lrclk_shared
[0]) {
2667 lrclk_reg
= WM8994_AIF1DAC_LRCLK
;
2669 lrclk_reg
= WM8994_AIF1ADC_LRCLK
;
2670 dev_dbg(codec
->dev
, "AIF1 using split LRCLK\n");
2674 aif1_reg
= WM8994_AIF2_CONTROL_1
;
2675 aif2_reg
= WM8994_AIF2_CONTROL_2
;
2676 bclk_reg
= WM8994_AIF2_BCLK
;
2677 rate_reg
= WM8994_AIF2_RATE
;
2678 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
||
2679 wm8994
->lrclk_shared
[1]) {
2680 lrclk_reg
= WM8994_AIF2DAC_LRCLK
;
2682 lrclk_reg
= WM8994_AIF2ADC_LRCLK
;
2683 dev_dbg(codec
->dev
, "AIF2 using split LRCLK\n");
2690 bclk_rate
= params_rate(params
) * 4;
2691 switch (params_format(params
)) {
2692 case SNDRV_PCM_FORMAT_S16_LE
:
2695 case SNDRV_PCM_FORMAT_S20_3LE
:
2699 case SNDRV_PCM_FORMAT_S24_LE
:
2703 case SNDRV_PCM_FORMAT_S32_LE
:
2711 /* Try to find an appropriate sample rate; look for an exact match. */
2712 for (i
= 0; i
< ARRAY_SIZE(srs
); i
++)
2713 if (srs
[i
].rate
== params_rate(params
))
2715 if (i
== ARRAY_SIZE(srs
))
2717 rate_val
|= srs
[i
].val
<< WM8994_AIF1_SR_SHIFT
;
2719 dev_dbg(dai
->dev
, "Sample rate is %dHz\n", srs
[i
].rate
);
2720 dev_dbg(dai
->dev
, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2721 dai
->id
, wm8994
->aifclk
[id
], bclk_rate
);
2723 if (params_channels(params
) == 1 &&
2724 (snd_soc_read(codec
, aif1_reg
) & 0x18) == 0x18)
2725 aif2
|= WM8994_AIF1_MONO
;
2727 if (wm8994
->aifclk
[id
] == 0) {
2728 dev_err(dai
->dev
, "AIF%dCLK not configured\n", dai
->id
);
2732 /* AIFCLK/fs ratio; look for a close match in either direction */
2734 best_val
= abs((fs_ratios
[0] * params_rate(params
))
2735 - wm8994
->aifclk
[id
]);
2736 for (i
= 1; i
< ARRAY_SIZE(fs_ratios
); i
++) {
2737 cur_val
= abs((fs_ratios
[i
] * params_rate(params
))
2738 - wm8994
->aifclk
[id
]);
2739 if (cur_val
>= best_val
)
2744 dev_dbg(dai
->dev
, "Selected AIF%dCLK/fs = %d\n",
2745 dai
->id
, fs_ratios
[best
]);
2748 /* We may not get quite the right frequency if using
2749 * approximate clocks so look for the closest match that is
2750 * higher than the target (we need to ensure that there enough
2751 * BCLKs to clock out the samples).
2754 for (i
= 0; i
< ARRAY_SIZE(bclk_divs
); i
++) {
2755 cur_val
= (wm8994
->aifclk
[id
] * 10 / bclk_divs
[i
]) - bclk_rate
;
2756 if (cur_val
< 0) /* BCLK table is sorted */
2760 bclk_rate
= wm8994
->aifclk
[id
] * 10 / bclk_divs
[best
];
2761 dev_dbg(dai
->dev
, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2762 bclk_divs
[best
], bclk_rate
);
2763 bclk
|= best
<< WM8994_AIF1_BCLK_DIV_SHIFT
;
2765 lrclk
= bclk_rate
/ params_rate(params
);
2767 dev_err(dai
->dev
, "Unable to generate LRCLK from %dHz BCLK\n",
2771 dev_dbg(dai
->dev
, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2772 lrclk
, bclk_rate
/ lrclk
);
2774 snd_soc_update_bits(codec
, aif1_reg
, WM8994_AIF1_WL_MASK
, aif1
);
2775 snd_soc_update_bits(codec
, aif2_reg
, WM8994_AIF1_MONO
, aif2
);
2776 snd_soc_update_bits(codec
, bclk_reg
, WM8994_AIF1_BCLK_DIV_MASK
, bclk
);
2777 snd_soc_update_bits(codec
, lrclk_reg
, WM8994_AIF1DAC_RATE_MASK
,
2779 snd_soc_update_bits(codec
, rate_reg
, WM8994_AIF1_SR_MASK
|
2780 WM8994_AIF1CLK_RATE_MASK
, rate_val
);
2782 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
2785 wm8994
->dac_rates
[0] = params_rate(params
);
2786 wm8994_set_retune_mobile(codec
, 0);
2787 wm8994_set_retune_mobile(codec
, 1);
2790 wm8994
->dac_rates
[1] = params_rate(params
);
2791 wm8994_set_retune_mobile(codec
, 2);
2799 static int wm8994_aif3_hw_params(struct snd_pcm_substream
*substream
,
2800 struct snd_pcm_hw_params
*params
,
2801 struct snd_soc_dai
*dai
)
2803 struct snd_soc_codec
*codec
= dai
->codec
;
2804 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2805 struct wm8994
*control
= wm8994
->wm8994
;
2811 switch (control
->type
) {
2814 aif1_reg
= WM8958_AIF3_CONTROL_1
;
2823 switch (params_format(params
)) {
2824 case SNDRV_PCM_FORMAT_S16_LE
:
2826 case SNDRV_PCM_FORMAT_S20_3LE
:
2829 case SNDRV_PCM_FORMAT_S24_LE
:
2832 case SNDRV_PCM_FORMAT_S32_LE
:
2839 return snd_soc_update_bits(codec
, aif1_reg
, WM8994_AIF1_WL_MASK
, aif1
);
2842 static int wm8994_aif_mute(struct snd_soc_dai
*codec_dai
, int mute
)
2844 struct snd_soc_codec
*codec
= codec_dai
->codec
;
2848 switch (codec_dai
->id
) {
2850 mute_reg
= WM8994_AIF1_DAC1_FILTERS_1
;
2853 mute_reg
= WM8994_AIF2_DAC_FILTERS_1
;
2860 reg
= WM8994_AIF1DAC1_MUTE
;
2864 snd_soc_update_bits(codec
, mute_reg
, WM8994_AIF1DAC1_MUTE
, reg
);
2869 static int wm8994_set_tristate(struct snd_soc_dai
*codec_dai
, int tristate
)
2871 struct snd_soc_codec
*codec
= codec_dai
->codec
;
2874 switch (codec_dai
->id
) {
2876 reg
= WM8994_AIF1_MASTER_SLAVE
;
2877 mask
= WM8994_AIF1_TRI
;
2880 reg
= WM8994_AIF2_MASTER_SLAVE
;
2881 mask
= WM8994_AIF2_TRI
;
2892 return snd_soc_update_bits(codec
, reg
, mask
, val
);
2895 static int wm8994_aif2_probe(struct snd_soc_dai
*dai
)
2897 struct snd_soc_codec
*codec
= dai
->codec
;
2899 /* Disable the pulls on the AIF if we're using it to save power. */
2900 snd_soc_update_bits(codec
, WM8994_GPIO_3
,
2901 WM8994_GPN_PU
| WM8994_GPN_PD
, 0);
2902 snd_soc_update_bits(codec
, WM8994_GPIO_4
,
2903 WM8994_GPN_PU
| WM8994_GPN_PD
, 0);
2904 snd_soc_update_bits(codec
, WM8994_GPIO_5
,
2905 WM8994_GPN_PU
| WM8994_GPN_PD
, 0);
2910 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2912 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2913 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2915 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops
= {
2916 .set_sysclk
= wm8994_set_dai_sysclk
,
2917 .set_fmt
= wm8994_set_dai_fmt
,
2918 .hw_params
= wm8994_hw_params
,
2919 .digital_mute
= wm8994_aif_mute
,
2920 .set_pll
= wm8994_set_fll
,
2921 .set_tristate
= wm8994_set_tristate
,
2924 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops
= {
2925 .set_sysclk
= wm8994_set_dai_sysclk
,
2926 .set_fmt
= wm8994_set_dai_fmt
,
2927 .hw_params
= wm8994_hw_params
,
2928 .digital_mute
= wm8994_aif_mute
,
2929 .set_pll
= wm8994_set_fll
,
2930 .set_tristate
= wm8994_set_tristate
,
2933 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops
= {
2934 .hw_params
= wm8994_aif3_hw_params
,
2937 static struct snd_soc_dai_driver wm8994_dai
[] = {
2939 .name
= "wm8994-aif1",
2942 .stream_name
= "AIF1 Playback",
2945 .rates
= WM8994_RATES
,
2946 .formats
= WM8994_FORMATS
,
2950 .stream_name
= "AIF1 Capture",
2953 .rates
= WM8994_RATES
,
2954 .formats
= WM8994_FORMATS
,
2957 .ops
= &wm8994_aif1_dai_ops
,
2960 .name
= "wm8994-aif2",
2963 .stream_name
= "AIF2 Playback",
2966 .rates
= WM8994_RATES
,
2967 .formats
= WM8994_FORMATS
,
2971 .stream_name
= "AIF2 Capture",
2974 .rates
= WM8994_RATES
,
2975 .formats
= WM8994_FORMATS
,
2978 .probe
= wm8994_aif2_probe
,
2979 .ops
= &wm8994_aif2_dai_ops
,
2982 .name
= "wm8994-aif3",
2985 .stream_name
= "AIF3 Playback",
2988 .rates
= WM8994_RATES
,
2989 .formats
= WM8994_FORMATS
,
2993 .stream_name
= "AIF3 Capture",
2996 .rates
= WM8994_RATES
,
2997 .formats
= WM8994_FORMATS
,
3000 .ops
= &wm8994_aif3_dai_ops
,
3005 static int wm8994_codec_suspend(struct snd_soc_codec
*codec
)
3007 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3010 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll
); i
++) {
3011 memcpy(&wm8994
->fll_suspend
[i
], &wm8994
->fll
[i
],
3012 sizeof(struct wm8994_fll_config
));
3013 ret
= _wm8994_set_fll(codec
, i
+ 1, 0, 0, 0);
3015 dev_warn(codec
->dev
, "Failed to stop FLL%d: %d\n",
3019 wm8994_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
3024 static int wm8994_codec_resume(struct snd_soc_codec
*codec
)
3026 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3027 struct wm8994
*control
= wm8994
->wm8994
;
3029 unsigned int val
, mask
;
3031 if (wm8994
->revision
< 4) {
3032 /* force a HW read */
3033 ret
= regmap_read(control
->regmap
,
3034 WM8994_POWER_MANAGEMENT_5
, &val
);
3036 /* modify the cache only */
3037 codec
->cache_only
= 1;
3038 mask
= WM8994_DAC1R_ENA
| WM8994_DAC1L_ENA
|
3039 WM8994_DAC2R_ENA
| WM8994_DAC2L_ENA
;
3041 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
3043 codec
->cache_only
= 0;
3046 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll
); i
++) {
3047 if (!wm8994
->fll_suspend
[i
].out
)
3050 ret
= _wm8994_set_fll(codec
, i
+ 1,
3051 wm8994
->fll_suspend
[i
].src
,
3052 wm8994
->fll_suspend
[i
].in
,
3053 wm8994
->fll_suspend
[i
].out
);
3055 dev_warn(codec
->dev
, "Failed to restore FLL%d: %d\n",
3062 #define wm8994_codec_suspend NULL
3063 #define wm8994_codec_resume NULL
3066 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv
*wm8994
)
3068 struct snd_soc_codec
*codec
= wm8994
->hubs
.codec
;
3069 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
3070 struct snd_kcontrol_new controls
[] = {
3071 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3072 wm8994
->retune_mobile_enum
,
3073 wm8994_get_retune_mobile_enum
,
3074 wm8994_put_retune_mobile_enum
),
3075 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3076 wm8994
->retune_mobile_enum
,
3077 wm8994_get_retune_mobile_enum
,
3078 wm8994_put_retune_mobile_enum
),
3079 SOC_ENUM_EXT("AIF2 EQ Mode",
3080 wm8994
->retune_mobile_enum
,
3081 wm8994_get_retune_mobile_enum
,
3082 wm8994_put_retune_mobile_enum
),
3087 /* We need an array of texts for the enum API but the number
3088 * of texts is likely to be less than the number of
3089 * configurations due to the sample rate dependency of the
3090 * configurations. */
3091 wm8994
->num_retune_mobile_texts
= 0;
3092 wm8994
->retune_mobile_texts
= NULL
;
3093 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
3094 for (j
= 0; j
< wm8994
->num_retune_mobile_texts
; j
++) {
3095 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
3096 wm8994
->retune_mobile_texts
[j
]) == 0)
3100 if (j
!= wm8994
->num_retune_mobile_texts
)
3103 /* Expand the array... */
3104 t
= krealloc(wm8994
->retune_mobile_texts
,
3106 (wm8994
->num_retune_mobile_texts
+ 1),
3111 /* ...store the new entry... */
3112 t
[wm8994
->num_retune_mobile_texts
] =
3113 pdata
->retune_mobile_cfgs
[i
].name
;
3115 /* ...and remember the new version. */
3116 wm8994
->num_retune_mobile_texts
++;
3117 wm8994
->retune_mobile_texts
= t
;
3120 dev_dbg(codec
->dev
, "Allocated %d unique ReTune Mobile names\n",
3121 wm8994
->num_retune_mobile_texts
);
3123 wm8994
->retune_mobile_enum
.max
= wm8994
->num_retune_mobile_texts
;
3124 wm8994
->retune_mobile_enum
.texts
= wm8994
->retune_mobile_texts
;
3126 ret
= snd_soc_add_codec_controls(wm8994
->hubs
.codec
, controls
,
3127 ARRAY_SIZE(controls
));
3129 dev_err(wm8994
->hubs
.codec
->dev
,
3130 "Failed to add ReTune Mobile controls: %d\n", ret
);
3133 static void wm8994_handle_pdata(struct wm8994_priv
*wm8994
)
3135 struct snd_soc_codec
*codec
= wm8994
->hubs
.codec
;
3136 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
3142 wm_hubs_handle_analogue_pdata(codec
, pdata
->lineout1_diff
,
3143 pdata
->lineout2_diff
,
3150 pdata
->micbias1_lvl
,
3151 pdata
->micbias2_lvl
);
3153 dev_dbg(codec
->dev
, "%d DRC configurations\n", pdata
->num_drc_cfgs
);
3155 if (pdata
->num_drc_cfgs
) {
3156 struct snd_kcontrol_new controls
[] = {
3157 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994
->drc_enum
,
3158 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
3159 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994
->drc_enum
,
3160 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
3161 SOC_ENUM_EXT("AIF2DRC Mode", wm8994
->drc_enum
,
3162 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
3165 /* We need an array of texts for the enum API */
3166 wm8994
->drc_texts
= devm_kzalloc(wm8994
->hubs
.codec
->dev
,
3167 sizeof(char *) * pdata
->num_drc_cfgs
, GFP_KERNEL
);
3168 if (!wm8994
->drc_texts
) {
3169 dev_err(wm8994
->hubs
.codec
->dev
,
3170 "Failed to allocate %d DRC config texts\n",
3171 pdata
->num_drc_cfgs
);
3175 for (i
= 0; i
< pdata
->num_drc_cfgs
; i
++)
3176 wm8994
->drc_texts
[i
] = pdata
->drc_cfgs
[i
].name
;
3178 wm8994
->drc_enum
.max
= pdata
->num_drc_cfgs
;
3179 wm8994
->drc_enum
.texts
= wm8994
->drc_texts
;
3181 ret
= snd_soc_add_codec_controls(wm8994
->hubs
.codec
, controls
,
3182 ARRAY_SIZE(controls
));
3183 for (i
= 0; i
< WM8994_NUM_DRC
; i
++)
3184 wm8994_set_drc(codec
, i
);
3186 ret
= snd_soc_add_codec_controls(wm8994
->hubs
.codec
,
3187 wm8994_drc_controls
,
3188 ARRAY_SIZE(wm8994_drc_controls
));
3192 dev_err(wm8994
->hubs
.codec
->dev
,
3193 "Failed to add DRC mode controls: %d\n", ret
);
3196 dev_dbg(codec
->dev
, "%d ReTune Mobile configurations\n",
3197 pdata
->num_retune_mobile_cfgs
);
3199 if (pdata
->num_retune_mobile_cfgs
)
3200 wm8994_handle_retune_mobile_pdata(wm8994
);
3202 snd_soc_add_codec_controls(wm8994
->hubs
.codec
, wm8994_eq_controls
,
3203 ARRAY_SIZE(wm8994_eq_controls
));
3205 for (i
= 0; i
< ARRAY_SIZE(pdata
->micbias
); i
++) {
3206 if (pdata
->micbias
[i
]) {
3207 snd_soc_write(codec
, WM8958_MICBIAS1
+ i
,
3208 pdata
->micbias
[i
] & 0xffff);
3214 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3216 * @codec: WM8994 codec
3217 * @jack: jack to report detection events on
3218 * @micbias: microphone bias to detect on
3220 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3221 * being used to bring out signals to the processor then only platform
3222 * data configuration is needed for WM8994 and processor GPIOs should
3223 * be configured using snd_soc_jack_add_gpios() instead.
3225 * Configuration of detection levels is available via the micbias1_lvl
3226 * and micbias2_lvl platform data members.
3228 int wm8994_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
3231 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3232 struct wm8994_micdet
*micdet
;
3233 struct wm8994
*control
= wm8994
->wm8994
;
3236 if (control
->type
!= WM8994
) {
3237 dev_warn(codec
->dev
, "Not a WM8994\n");
3243 micdet
= &wm8994
->micdet
[0];
3245 ret
= snd_soc_dapm_force_enable_pin(&codec
->dapm
,
3248 ret
= snd_soc_dapm_disable_pin(&codec
->dapm
,
3252 micdet
= &wm8994
->micdet
[1];
3254 ret
= snd_soc_dapm_force_enable_pin(&codec
->dapm
,
3257 ret
= snd_soc_dapm_disable_pin(&codec
->dapm
,
3261 dev_warn(codec
->dev
, "Invalid MICBIAS %d\n", micbias
);
3266 dev_warn(codec
->dev
, "Failed to configure MICBIAS%d: %d\n",
3269 dev_dbg(codec
->dev
, "Configuring microphone detection on %d %p\n",
3272 /* Store the configuration */
3273 micdet
->jack
= jack
;
3274 micdet
->detecting
= true;
3276 /* If either of the jacks is set up then enable detection */
3277 if (wm8994
->micdet
[0].jack
|| wm8994
->micdet
[1].jack
)
3278 reg
= WM8994_MICD_ENA
;
3282 snd_soc_update_bits(codec
, WM8994_MICBIAS
, WM8994_MICD_ENA
, reg
);
3284 /* enable MICDET and MICSHRT deboune */
3285 snd_soc_update_bits(codec
, WM8994_IRQ_DEBOUNCE
,
3286 WM8994_MIC1_DET_DB_MASK
| WM8994_MIC1_SHRT_DB_MASK
|
3287 WM8994_MIC2_DET_DB_MASK
| WM8994_MIC2_SHRT_DB_MASK
,
3288 WM8994_MIC1_DET_DB
| WM8994_MIC1_SHRT_DB
);
3290 snd_soc_dapm_sync(&codec
->dapm
);
3294 EXPORT_SYMBOL_GPL(wm8994_mic_detect
);
3296 static void wm8994_mic_work(struct work_struct
*work
)
3298 struct wm8994_priv
*priv
= container_of(work
,
3301 struct regmap
*regmap
= priv
->wm8994
->regmap
;
3302 struct device
*dev
= priv
->wm8994
->dev
;
3307 pm_runtime_get_sync(dev
);
3309 ret
= regmap_read(regmap
, WM8994_INTERRUPT_RAW_STATUS_2
, ®
);
3311 dev_err(dev
, "Failed to read microphone status: %d\n",
3313 pm_runtime_put(dev
);
3317 dev_dbg(dev
, "Microphone status: %x\n", reg
);
3320 if (reg
& WM8994_MIC1_DET_STS
) {
3321 if (priv
->micdet
[0].detecting
)
3322 report
= SND_JACK_HEADSET
;
3324 if (reg
& WM8994_MIC1_SHRT_STS
) {
3325 if (priv
->micdet
[0].detecting
)
3326 report
= SND_JACK_HEADPHONE
;
3328 report
|= SND_JACK_BTN_0
;
3331 priv
->micdet
[0].detecting
= false;
3333 priv
->micdet
[0].detecting
= true;
3335 snd_soc_jack_report(priv
->micdet
[0].jack
, report
,
3336 SND_JACK_HEADSET
| SND_JACK_BTN_0
);
3339 if (reg
& WM8994_MIC2_DET_STS
) {
3340 if (priv
->micdet
[1].detecting
)
3341 report
= SND_JACK_HEADSET
;
3343 if (reg
& WM8994_MIC2_SHRT_STS
) {
3344 if (priv
->micdet
[1].detecting
)
3345 report
= SND_JACK_HEADPHONE
;
3347 report
|= SND_JACK_BTN_0
;
3350 priv
->micdet
[1].detecting
= false;
3352 priv
->micdet
[1].detecting
= true;
3354 snd_soc_jack_report(priv
->micdet
[1].jack
, report
,
3355 SND_JACK_HEADSET
| SND_JACK_BTN_0
);
3357 pm_runtime_put(dev
);
3360 static irqreturn_t
wm8994_mic_irq(int irq
, void *data
)
3362 struct wm8994_priv
*priv
= data
;
3363 struct snd_soc_codec
*codec
= priv
->hubs
.codec
;
3365 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3366 trace_snd_soc_jack_irq(dev_name(codec
->dev
));
3369 pm_wakeup_event(codec
->dev
, 300);
3371 schedule_delayed_work(&priv
->mic_work
, msecs_to_jiffies(250));
3376 /* Default microphone detection handler for WM8958 - the user can
3377 * override this if they wish.
3379 static void wm8958_default_micdet(u16 status
, void *data
)
3381 struct snd_soc_codec
*codec
= data
;
3382 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3385 dev_dbg(codec
->dev
, "MICDET %x\n", status
);
3387 /* Either nothing present or just starting detection */
3388 if (!(status
& WM8958_MICD_STS
)) {
3389 if (!wm8994
->jackdet
) {
3390 /* If nothing present then clear our statuses */
3391 dev_dbg(codec
->dev
, "Detected open circuit\n");
3392 wm8994
->jack_mic
= false;
3393 wm8994
->mic_detecting
= true;
3395 wm8958_micd_set_rate(codec
);
3397 snd_soc_jack_report(wm8994
->micdet
[0].jack
, 0,
3404 /* If the measurement is showing a high impedence we've got a
3407 if (wm8994
->mic_detecting
&& (status
& 0x600)) {
3408 dev_dbg(codec
->dev
, "Detected microphone\n");
3410 wm8994
->mic_detecting
= false;
3411 wm8994
->jack_mic
= true;
3413 wm8958_micd_set_rate(codec
);
3415 snd_soc_jack_report(wm8994
->micdet
[0].jack
, SND_JACK_HEADSET
,
3420 if (wm8994
->mic_detecting
&& status
& 0xfc) {
3421 dev_dbg(codec
->dev
, "Detected headphone\n");
3422 wm8994
->mic_detecting
= false;
3424 wm8958_micd_set_rate(codec
);
3426 /* If we have jackdet that will detect removal */
3427 if (wm8994
->jackdet
) {
3428 mutex_lock(&wm8994
->accdet_lock
);
3430 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3431 WM8958_MICD_ENA
, 0);
3433 wm1811_jackdet_set_mode(codec
,
3434 WM1811_JACKDET_MODE_JACK
);
3436 mutex_unlock(&wm8994
->accdet_lock
);
3438 if (wm8994
->pdata
->jd_ext_cap
)
3439 snd_soc_dapm_disable_pin(&codec
->dapm
,
3443 snd_soc_jack_report(wm8994
->micdet
[0].jack
, SND_JACK_HEADPHONE
,
3447 /* Report short circuit as a button */
3448 if (wm8994
->jack_mic
) {
3451 report
|= SND_JACK_BTN_0
;
3454 report
|= SND_JACK_BTN_1
;
3457 report
|= SND_JACK_BTN_2
;
3460 report
|= SND_JACK_BTN_3
;
3463 report
|= SND_JACK_BTN_4
;
3466 report
|= SND_JACK_BTN_5
;
3468 snd_soc_jack_report(wm8994
->micdet
[0].jack
, report
,
3473 static irqreturn_t
wm1811_jackdet_irq(int irq
, void *data
)
3475 struct wm8994_priv
*wm8994
= data
;
3476 struct snd_soc_codec
*codec
= wm8994
->hubs
.codec
;
3480 pm_runtime_get_sync(codec
->dev
);
3482 mutex_lock(&wm8994
->accdet_lock
);
3484 reg
= snd_soc_read(codec
, WM1811_JACKDET_CTRL
);
3486 dev_err(codec
->dev
, "Failed to read jack status: %d\n", reg
);
3487 mutex_unlock(&wm8994
->accdet_lock
);
3488 pm_runtime_put(codec
->dev
);
3492 dev_dbg(codec
->dev
, "JACKDET %x\n", reg
);
3494 present
= reg
& WM1811_JACKDET_LVL
;
3497 dev_dbg(codec
->dev
, "Jack detected\n");
3499 wm8958_micd_set_rate(codec
);
3501 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
3502 WM8958_MICB2_DISCH
, 0);
3504 /* Disable debounce while inserted */
3505 snd_soc_update_bits(codec
, WM1811_JACKDET_CTRL
,
3506 WM1811_JACKDET_DB
, 0);
3509 * Start off measument of microphone impedence to find
3510 * out what's actually there.
3512 wm8994
->mic_detecting
= true;
3513 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_MIC
);
3515 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3516 WM8958_MICD_ENA
, WM8958_MICD_ENA
);
3518 dev_dbg(codec
->dev
, "Jack not detected\n");
3520 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
3521 WM8958_MICB2_DISCH
, WM8958_MICB2_DISCH
);
3523 /* Enable debounce while removed */
3524 snd_soc_update_bits(codec
, WM1811_JACKDET_CTRL
,
3525 WM1811_JACKDET_DB
, WM1811_JACKDET_DB
);
3527 wm8994
->mic_detecting
= false;
3528 wm8994
->jack_mic
= false;
3529 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3530 WM8958_MICD_ENA
, 0);
3531 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_JACK
);
3534 mutex_unlock(&wm8994
->accdet_lock
);
3536 /* If required for an external cap force MICBIAS on */
3537 if (wm8994
->pdata
->jd_ext_cap
) {
3539 snd_soc_dapm_force_enable_pin(&codec
->dapm
,
3542 snd_soc_dapm_disable_pin(&codec
->dapm
, "MICBIAS2");
3546 snd_soc_jack_report(wm8994
->micdet
[0].jack
,
3547 SND_JACK_MECHANICAL
, SND_JACK_MECHANICAL
);
3549 snd_soc_jack_report(wm8994
->micdet
[0].jack
, 0,
3550 SND_JACK_MECHANICAL
| SND_JACK_HEADSET
|
3553 /* Since we only report deltas force an update, ensures we
3554 * avoid bootstrapping issues with the core. */
3555 snd_soc_jack_report(wm8994
->micdet
[0].jack
, 0, 0);
3557 pm_runtime_put(codec
->dev
);
3561 static void wm1811_jackdet_bootstrap(struct work_struct
*work
)
3563 struct wm8994_priv
*wm8994
= container_of(work
,
3565 jackdet_bootstrap
.work
);
3566 wm1811_jackdet_irq(0, wm8994
);
3570 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3572 * @codec: WM8958 codec
3573 * @jack: jack to report detection events on
3575 * Enable microphone detection functionality for the WM8958. By
3576 * default simple detection which supports the detection of up to 6
3577 * buttons plus video and microphone functionality is supported.
3579 * The WM8958 has an advanced jack detection facility which is able to
3580 * support complex accessory detection, especially when used in
3581 * conjunction with external circuitry. In order to provide maximum
3582 * flexiblity a callback is provided which allows a completely custom
3583 * detection algorithm.
3585 int wm8958_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
3586 wm8958_micdet_cb cb
, void *cb_data
)
3588 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3589 struct wm8994
*control
= wm8994
->wm8994
;
3592 switch (control
->type
) {
3602 dev_dbg(codec
->dev
, "Using default micdet callback\n");
3603 cb
= wm8958_default_micdet
;
3607 snd_soc_dapm_force_enable_pin(&codec
->dapm
, "CLK_SYS");
3608 snd_soc_dapm_sync(&codec
->dapm
);
3610 wm8994
->micdet
[0].jack
= jack
;
3611 wm8994
->jack_cb
= cb
;
3612 wm8994
->jack_cb_data
= cb_data
;
3614 wm8994
->mic_detecting
= true;
3615 wm8994
->jack_mic
= false;
3617 wm8958_micd_set_rate(codec
);
3619 /* Detect microphones and short circuits by default */
3620 if (wm8994
->pdata
->micd_lvl_sel
)
3621 micd_lvl_sel
= wm8994
->pdata
->micd_lvl_sel
;
3623 micd_lvl_sel
= 0x41;
3625 wm8994
->btn_mask
= SND_JACK_BTN_0
| SND_JACK_BTN_1
|
3626 SND_JACK_BTN_2
| SND_JACK_BTN_3
|
3627 SND_JACK_BTN_4
| SND_JACK_BTN_5
;
3629 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_2
,
3630 WM8958_MICD_LVL_SEL_MASK
, micd_lvl_sel
);
3632 WARN_ON(codec
->dapm
.bias_level
> SND_SOC_BIAS_STANDBY
);
3635 * If we can use jack detection start off with that,
3636 * otherwise jump straight to microphone detection.
3638 if (wm8994
->jackdet
) {
3639 /* Disable debounce for the initial detect */
3640 snd_soc_update_bits(codec
, WM1811_JACKDET_CTRL
,
3641 WM1811_JACKDET_DB
, 0);
3643 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
3645 WM8958_MICB2_DISCH
);
3646 snd_soc_update_bits(codec
, WM8994_LDO_1
,
3647 WM8994_LDO1_DISCH
, 0);
3648 wm1811_jackdet_set_mode(codec
,
3649 WM1811_JACKDET_MODE_JACK
);
3651 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3652 WM8958_MICD_ENA
, WM8958_MICD_ENA
);
3656 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3657 WM8958_MICD_ENA
, 0);
3658 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_NONE
);
3659 snd_soc_dapm_disable_pin(&codec
->dapm
, "CLK_SYS");
3660 snd_soc_dapm_sync(&codec
->dapm
);
3665 EXPORT_SYMBOL_GPL(wm8958_mic_detect
);
3667 static irqreturn_t
wm8958_mic_irq(int irq
, void *data
)
3669 struct wm8994_priv
*wm8994
= data
;
3670 struct snd_soc_codec
*codec
= wm8994
->hubs
.codec
;
3674 * Jack detection may have detected a removal simulataneously
3675 * with an update of the MICDET status; if so it will have
3676 * stopped detection and we can ignore this interrupt.
3678 if (!(snd_soc_read(codec
, WM8958_MIC_DETECT_1
) & WM8958_MICD_ENA
))
3681 pm_runtime_get_sync(codec
->dev
);
3683 /* We may occasionally read a detection without an impedence
3684 * range being provided - if that happens loop again.
3688 reg
= snd_soc_read(codec
, WM8958_MIC_DETECT_3
);
3691 "Failed to read mic detect status: %d\n",
3693 pm_runtime_put(codec
->dev
);
3697 if (!(reg
& WM8958_MICD_VALID
)) {
3698 dev_dbg(codec
->dev
, "Mic detect data not valid\n");
3702 if (!(reg
& WM8958_MICD_STS
) || (reg
& WM8958_MICD_LVL_MASK
))
3709 dev_warn(codec
->dev
, "No impedence range reported for jack\n");
3711 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3712 trace_snd_soc_jack_irq(dev_name(codec
->dev
));
3715 if (wm8994
->jack_cb
)
3716 wm8994
->jack_cb(reg
, wm8994
->jack_cb_data
);
3718 dev_warn(codec
->dev
, "Accessory detection with no callback\n");
3721 pm_runtime_put(codec
->dev
);
3725 static irqreturn_t
wm8994_fifo_error(int irq
, void *data
)
3727 struct snd_soc_codec
*codec
= data
;
3729 dev_err(codec
->dev
, "FIFO error\n");
3734 static irqreturn_t
wm8994_temp_warn(int irq
, void *data
)
3736 struct snd_soc_codec
*codec
= data
;
3738 dev_err(codec
->dev
, "Thermal warning\n");
3743 static irqreturn_t
wm8994_temp_shut(int irq
, void *data
)
3745 struct snd_soc_codec
*codec
= data
;
3747 dev_crit(codec
->dev
, "Thermal shutdown\n");
3752 static int wm8994_codec_probe(struct snd_soc_codec
*codec
)
3754 struct wm8994
*control
= dev_get_drvdata(codec
->dev
->parent
);
3755 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3756 struct snd_soc_dapm_context
*dapm
= &codec
->dapm
;
3760 wm8994
->hubs
.codec
= codec
;
3761 codec
->control_data
= control
->regmap
;
3763 snd_soc_codec_set_cache_io(codec
, 16, 16, SND_SOC_REGMAP
);
3765 mutex_init(&wm8994
->accdet_lock
);
3766 INIT_DELAYED_WORK(&wm8994
->mic_work
, wm8994_mic_work
);
3767 INIT_DELAYED_WORK(&wm8994
->jackdet_bootstrap
,
3768 wm1811_jackdet_bootstrap
);
3770 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++)
3771 init_completion(&wm8994
->fll_locked
[i
]);
3773 if (wm8994
->pdata
&& wm8994
->pdata
->micdet_irq
)
3774 wm8994
->micdet_irq
= wm8994
->pdata
->micdet_irq
;
3776 pm_runtime_enable(codec
->dev
);
3777 pm_runtime_idle(codec
->dev
);
3779 /* By default use idle_bias_off, will override for WM8994 */
3780 codec
->dapm
.idle_bias_off
= 1;
3782 /* Set revision-specific configuration */
3783 wm8994
->revision
= snd_soc_read(codec
, WM8994_CHIP_REVISION
);
3784 switch (control
->type
) {
3786 /* Single ended line outputs should have VMID on. */
3787 if (!wm8994
->pdata
->lineout1_diff
||
3788 !wm8994
->pdata
->lineout2_diff
)
3789 codec
->dapm
.idle_bias_off
= 0;
3791 switch (wm8994
->revision
) {
3794 wm8994
->hubs
.dcs_codes_l
= -5;
3795 wm8994
->hubs
.dcs_codes_r
= -5;
3796 wm8994
->hubs
.hp_startup_mode
= 1;
3797 wm8994
->hubs
.dcs_readback_mode
= 1;
3798 wm8994
->hubs
.series_startup
= 1;
3801 wm8994
->hubs
.dcs_readback_mode
= 2;
3807 wm8994
->hubs
.dcs_readback_mode
= 1;
3808 wm8994
->hubs
.hp_startup_mode
= 1;
3810 switch (wm8994
->revision
) {
3814 wm8994
->fll_byp
= true;
3820 wm8994
->hubs
.dcs_readback_mode
= 2;
3821 wm8994
->hubs
.no_series_update
= 1;
3822 wm8994
->hubs
.hp_startup_mode
= 1;
3823 wm8994
->hubs
.no_cache_dac_hp_direct
= true;
3824 wm8994
->fll_byp
= true;
3826 switch (control
->cust_id
) {
3829 wm8994
->hubs
.dcs_codes_l
= -9;
3830 wm8994
->hubs
.dcs_codes_r
= -7;
3834 wm8994
->hubs
.dcs_codes_l
= -8;
3835 wm8994
->hubs
.dcs_codes_r
= -7;
3841 snd_soc_update_bits(codec
, WM8994_ANALOGUE_HP_1
,
3842 WM1811_HPOUT1_ATTN
, WM1811_HPOUT1_ATTN
);
3849 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_FIFOS_ERR
,
3850 wm8994_fifo_error
, "FIFO error", codec
);
3851 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_WARN
,
3852 wm8994_temp_warn
, "Thermal warning", codec
);
3853 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_SHUT
,
3854 wm8994_temp_shut
, "Thermal shutdown", codec
);
3856 ret
= wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_DCS_DONE
,
3857 wm_hubs_dcs_done
, "DC servo done",
3860 wm8994
->hubs
.dcs_done_irq
= true;
3862 switch (control
->type
) {
3864 if (wm8994
->micdet_irq
) {
3865 ret
= request_threaded_irq(wm8994
->micdet_irq
, NULL
,
3867 IRQF_TRIGGER_RISING
,
3871 dev_warn(codec
->dev
,
3872 "Failed to request Mic1 detect IRQ: %d\n",
3876 ret
= wm8994_request_irq(wm8994
->wm8994
,
3877 WM8994_IRQ_MIC1_SHRT
,
3878 wm8994_mic_irq
, "Mic 1 short",
3881 dev_warn(codec
->dev
,
3882 "Failed to request Mic1 short IRQ: %d\n",
3885 ret
= wm8994_request_irq(wm8994
->wm8994
,
3886 WM8994_IRQ_MIC2_DET
,
3887 wm8994_mic_irq
, "Mic 2 detect",
3890 dev_warn(codec
->dev
,
3891 "Failed to request Mic2 detect IRQ: %d\n",
3894 ret
= wm8994_request_irq(wm8994
->wm8994
,
3895 WM8994_IRQ_MIC2_SHRT
,
3896 wm8994_mic_irq
, "Mic 2 short",
3899 dev_warn(codec
->dev
,
3900 "Failed to request Mic2 short IRQ: %d\n",
3906 if (wm8994
->micdet_irq
) {
3907 ret
= request_threaded_irq(wm8994
->micdet_irq
, NULL
,
3909 IRQF_TRIGGER_RISING
,
3913 dev_warn(codec
->dev
,
3914 "Failed to request Mic detect IRQ: %d\n",
3917 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_DET
,
3918 wm8958_mic_irq
, "Mic detect",
3923 switch (control
->type
) {
3925 if (control
->cust_id
> 1 || wm8994
->revision
> 1) {
3926 ret
= wm8994_request_irq(wm8994
->wm8994
,
3928 wm1811_jackdet_irq
, "JACKDET",
3931 wm8994
->jackdet
= true;
3938 wm8994
->fll_locked_irq
= true;
3939 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++) {
3940 ret
= wm8994_request_irq(wm8994
->wm8994
,
3941 WM8994_IRQ_FLL1_LOCK
+ i
,
3942 wm8994_fll_locked_irq
, "FLL lock",
3943 &wm8994
->fll_locked
[i
]);
3945 wm8994
->fll_locked_irq
= false;
3948 /* Make sure we can read from the GPIOs if they're inputs */
3949 pm_runtime_get_sync(codec
->dev
);
3951 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3952 * configured on init - if a system wants to do this dynamically
3953 * at runtime we can deal with that then.
3955 ret
= regmap_read(control
->regmap
, WM8994_GPIO_1
, ®
);
3957 dev_err(codec
->dev
, "Failed to read GPIO1 state: %d\n", ret
);
3960 if ((reg
& WM8994_GPN_FN_MASK
) != WM8994_GP_FN_PIN_SPECIFIC
) {
3961 wm8994
->lrclk_shared
[0] = 1;
3962 wm8994_dai
[0].symmetric_rates
= 1;
3964 wm8994
->lrclk_shared
[0] = 0;
3967 ret
= regmap_read(control
->regmap
, WM8994_GPIO_6
, ®
);
3969 dev_err(codec
->dev
, "Failed to read GPIO6 state: %d\n", ret
);
3972 if ((reg
& WM8994_GPN_FN_MASK
) != WM8994_GP_FN_PIN_SPECIFIC
) {
3973 wm8994
->lrclk_shared
[1] = 1;
3974 wm8994_dai
[1].symmetric_rates
= 1;
3976 wm8994
->lrclk_shared
[1] = 0;
3979 pm_runtime_put(codec
->dev
);
3981 /* Latch volume update bits */
3982 for (i
= 0; i
< ARRAY_SIZE(wm8994_vu_bits
); i
++)
3983 snd_soc_update_bits(codec
, wm8994_vu_bits
[i
].reg
,
3984 wm8994_vu_bits
[i
].mask
,
3985 wm8994_vu_bits
[i
].mask
);
3987 /* Set the low bit of the 3D stereo depth so TLV matches */
3988 snd_soc_update_bits(codec
, WM8994_AIF1_DAC1_FILTERS_2
,
3989 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT
,
3990 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT
);
3991 snd_soc_update_bits(codec
, WM8994_AIF1_DAC2_FILTERS_2
,
3992 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT
,
3993 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT
);
3994 snd_soc_update_bits(codec
, WM8994_AIF2_DAC_FILTERS_2
,
3995 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT
,
3996 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT
);
3998 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3999 * use this; it only affects behaviour on idle TDM clock
4001 switch (control
->type
) {
4004 snd_soc_update_bits(codec
, WM8994_AIF1_CONTROL_1
,
4005 WM8994_AIF1ADC_TDM
, WM8994_AIF1ADC_TDM
);
4011 /* Put MICBIAS into bypass mode by default on newer devices */
4012 switch (control
->type
) {
4015 snd_soc_update_bits(codec
, WM8958_MICBIAS1
,
4016 WM8958_MICB1_MODE
, WM8958_MICB1_MODE
);
4017 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
4018 WM8958_MICB2_MODE
, WM8958_MICB2_MODE
);
4024 wm8994
->hubs
.check_class_w_digital
= wm8994_check_class_w_digital
;
4025 wm_hubs_update_class_w(codec
);
4027 wm8994_handle_pdata(wm8994
);
4029 wm_hubs_add_analogue_controls(codec
);
4030 snd_soc_add_codec_controls(codec
, wm8994_snd_controls
,
4031 ARRAY_SIZE(wm8994_snd_controls
));
4032 snd_soc_dapm_new_controls(dapm
, wm8994_dapm_widgets
,
4033 ARRAY_SIZE(wm8994_dapm_widgets
));
4035 switch (control
->type
) {
4037 snd_soc_dapm_new_controls(dapm
, wm8994_specific_dapm_widgets
,
4038 ARRAY_SIZE(wm8994_specific_dapm_widgets
));
4039 if (wm8994
->revision
< 4) {
4040 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_revd_widgets
,
4041 ARRAY_SIZE(wm8994_lateclk_revd_widgets
));
4042 snd_soc_dapm_new_controls(dapm
, wm8994_adc_revd_widgets
,
4043 ARRAY_SIZE(wm8994_adc_revd_widgets
));
4044 snd_soc_dapm_new_controls(dapm
, wm8994_dac_revd_widgets
,
4045 ARRAY_SIZE(wm8994_dac_revd_widgets
));
4047 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_widgets
,
4048 ARRAY_SIZE(wm8994_lateclk_widgets
));
4049 snd_soc_dapm_new_controls(dapm
, wm8994_adc_widgets
,
4050 ARRAY_SIZE(wm8994_adc_widgets
));
4051 snd_soc_dapm_new_controls(dapm
, wm8994_dac_widgets
,
4052 ARRAY_SIZE(wm8994_dac_widgets
));
4056 snd_soc_add_codec_controls(codec
, wm8958_snd_controls
,
4057 ARRAY_SIZE(wm8958_snd_controls
));
4058 snd_soc_dapm_new_controls(dapm
, wm8958_dapm_widgets
,
4059 ARRAY_SIZE(wm8958_dapm_widgets
));
4060 if (wm8994
->revision
< 1) {
4061 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_revd_widgets
,
4062 ARRAY_SIZE(wm8994_lateclk_revd_widgets
));
4063 snd_soc_dapm_new_controls(dapm
, wm8994_adc_revd_widgets
,
4064 ARRAY_SIZE(wm8994_adc_revd_widgets
));
4065 snd_soc_dapm_new_controls(dapm
, wm8994_dac_revd_widgets
,
4066 ARRAY_SIZE(wm8994_dac_revd_widgets
));
4068 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_widgets
,
4069 ARRAY_SIZE(wm8994_lateclk_widgets
));
4070 snd_soc_dapm_new_controls(dapm
, wm8994_adc_widgets
,
4071 ARRAY_SIZE(wm8994_adc_widgets
));
4072 snd_soc_dapm_new_controls(dapm
, wm8994_dac_widgets
,
4073 ARRAY_SIZE(wm8994_dac_widgets
));
4078 snd_soc_add_codec_controls(codec
, wm8958_snd_controls
,
4079 ARRAY_SIZE(wm8958_snd_controls
));
4080 snd_soc_dapm_new_controls(dapm
, wm8958_dapm_widgets
,
4081 ARRAY_SIZE(wm8958_dapm_widgets
));
4082 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_widgets
,
4083 ARRAY_SIZE(wm8994_lateclk_widgets
));
4084 snd_soc_dapm_new_controls(dapm
, wm8994_adc_widgets
,
4085 ARRAY_SIZE(wm8994_adc_widgets
));
4086 snd_soc_dapm_new_controls(dapm
, wm8994_dac_widgets
,
4087 ARRAY_SIZE(wm8994_dac_widgets
));
4091 wm_hubs_add_analogue_routes(codec
, 0, 0);
4092 snd_soc_dapm_add_routes(dapm
, intercon
, ARRAY_SIZE(intercon
));
4094 switch (control
->type
) {
4096 snd_soc_dapm_add_routes(dapm
, wm8994_intercon
,
4097 ARRAY_SIZE(wm8994_intercon
));
4099 if (wm8994
->revision
< 4) {
4100 snd_soc_dapm_add_routes(dapm
, wm8994_revd_intercon
,
4101 ARRAY_SIZE(wm8994_revd_intercon
));
4102 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_revd_intercon
,
4103 ARRAY_SIZE(wm8994_lateclk_revd_intercon
));
4105 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_intercon
,
4106 ARRAY_SIZE(wm8994_lateclk_intercon
));
4110 if (wm8994
->revision
< 1) {
4111 snd_soc_dapm_add_routes(dapm
, wm8994_intercon
,
4112 ARRAY_SIZE(wm8994_intercon
));
4113 snd_soc_dapm_add_routes(dapm
, wm8994_revd_intercon
,
4114 ARRAY_SIZE(wm8994_revd_intercon
));
4115 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_revd_intercon
,
4116 ARRAY_SIZE(wm8994_lateclk_revd_intercon
));
4118 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_intercon
,
4119 ARRAY_SIZE(wm8994_lateclk_intercon
));
4120 snd_soc_dapm_add_routes(dapm
, wm8958_intercon
,
4121 ARRAY_SIZE(wm8958_intercon
));
4124 wm8958_dsp2_init(codec
);
4127 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_intercon
,
4128 ARRAY_SIZE(wm8994_lateclk_intercon
));
4129 snd_soc_dapm_add_routes(dapm
, wm8958_intercon
,
4130 ARRAY_SIZE(wm8958_intercon
));
4137 if (wm8994
->jackdet
)
4138 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_GPIO(6), wm8994
);
4139 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC2_SHRT
, wm8994
);
4140 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC2_DET
, wm8994
);
4141 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_SHRT
, wm8994
);
4142 if (wm8994
->micdet_irq
)
4143 free_irq(wm8994
->micdet_irq
, wm8994
);
4144 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++)
4145 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FLL1_LOCK
+ i
,
4146 &wm8994
->fll_locked
[i
]);
4147 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_DCS_DONE
,
4149 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FIFOS_ERR
, codec
);
4150 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_SHUT
, codec
);
4151 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_WARN
, codec
);
4156 static int wm8994_codec_remove(struct snd_soc_codec
*codec
)
4158 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
4159 struct wm8994
*control
= wm8994
->wm8994
;
4162 wm8994_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
4164 pm_runtime_disable(codec
->dev
);
4166 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++)
4167 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FLL1_LOCK
+ i
,
4168 &wm8994
->fll_locked
[i
]);
4170 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_DCS_DONE
,
4172 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FIFOS_ERR
, codec
);
4173 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_SHUT
, codec
);
4174 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_WARN
, codec
);
4176 if (wm8994
->jackdet
)
4177 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_GPIO(6), wm8994
);
4179 switch (control
->type
) {
4181 if (wm8994
->micdet_irq
)
4182 free_irq(wm8994
->micdet_irq
, wm8994
);
4183 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC2_DET
,
4185 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_SHRT
,
4187 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_DET
,
4193 if (wm8994
->micdet_irq
)
4194 free_irq(wm8994
->micdet_irq
, wm8994
);
4197 release_firmware(wm8994
->mbc
);
4198 release_firmware(wm8994
->mbc_vss
);
4199 release_firmware(wm8994
->enh_eq
);
4200 kfree(wm8994
->retune_mobile_texts
);
4204 static struct snd_soc_codec_driver soc_codec_dev_wm8994
= {
4205 .probe
= wm8994_codec_probe
,
4206 .remove
= wm8994_codec_remove
,
4207 .suspend
= wm8994_codec_suspend
,
4208 .resume
= wm8994_codec_resume
,
4209 .set_bias_level
= wm8994_set_bias_level
,
4212 static int __devinit
wm8994_probe(struct platform_device
*pdev
)
4214 struct wm8994_priv
*wm8994
;
4216 wm8994
= devm_kzalloc(&pdev
->dev
, sizeof(struct wm8994_priv
),
4220 platform_set_drvdata(pdev
, wm8994
);
4222 wm8994
->wm8994
= dev_get_drvdata(pdev
->dev
.parent
);
4223 wm8994
->pdata
= dev_get_platdata(pdev
->dev
.parent
);
4225 return snd_soc_register_codec(&pdev
->dev
, &soc_codec_dev_wm8994
,
4226 wm8994_dai
, ARRAY_SIZE(wm8994_dai
));
4229 static int __devexit
wm8994_remove(struct platform_device
*pdev
)
4231 snd_soc_unregister_codec(&pdev
->dev
);
4235 #ifdef CONFIG_PM_SLEEP
4236 static int wm8994_suspend(struct device
*dev
)
4238 struct wm8994_priv
*wm8994
= dev_get_drvdata(dev
);
4240 /* Drop down to power saving mode when system is suspended */
4241 if (wm8994
->jackdet
&& !wm8994
->active_refcount
)
4242 regmap_update_bits(wm8994
->wm8994
->regmap
, WM8994_ANTIPOP_2
,
4243 WM1811_JACKDET_MODE_MASK
,
4244 wm8994
->jackdet_mode
);
4249 static int wm8994_resume(struct device
*dev
)
4251 struct wm8994_priv
*wm8994
= dev_get_drvdata(dev
);
4253 if (wm8994
->jackdet
&& wm8994
->jack_cb
)
4254 regmap_update_bits(wm8994
->wm8994
->regmap
, WM8994_ANTIPOP_2
,
4255 WM1811_JACKDET_MODE_MASK
,
4256 WM1811_JACKDET_MODE_AUDIO
);
4262 static const struct dev_pm_ops wm8994_pm_ops
= {
4263 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend
, wm8994_resume
)
4266 static struct platform_driver wm8994_codec_driver
= {
4268 .name
= "wm8994-codec",
4269 .owner
= THIS_MODULE
,
4270 .pm
= &wm8994_pm_ops
,
4272 .probe
= wm8994_probe
,
4273 .remove
= __devexit_p(wm8994_remove
),
4276 module_platform_driver(wm8994_codec_driver
);
4278 MODULE_DESCRIPTION("ASoC WM8994 driver");
4279 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4280 MODULE_LICENSE("GPL");
4281 MODULE_ALIAS("platform:wm8994-codec");