2 * wm8994.c -- WM8994 ALSA SoC Audio driver
4 * Copyright 2009 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/slab.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
30 #include <linux/mfd/wm8994/core.h>
31 #include <linux/mfd/wm8994/registers.h>
32 #include <linux/mfd/wm8994/pdata.h>
33 #include <linux/mfd/wm8994/gpio.h>
44 #define WM8994_NUM_DRC 3
45 #define WM8994_NUM_EQ 3
47 static int wm8994_drc_base
[] = {
53 static int wm8994_retune_mobile_base
[] = {
54 WM8994_AIF1_DAC1_EQ_GAINS_1
,
55 WM8994_AIF1_DAC2_EQ_GAINS_1
,
56 WM8994_AIF2_EQ_GAINS_1
,
59 #define WM8994_REG_CACHE_SIZE 0x621
61 struct wm8994_micdet
{
62 struct snd_soc_jack
*jack
;
67 /* codec private data */
69 struct wm_hubs_data hubs
;
70 enum snd_soc_control_type control_type
;
72 struct snd_soc_codec
*codec
;
73 u16 reg_cache
[WM8994_REG_CACHE_SIZE
+ 1];
78 struct fll_config fll
[2], fll_suspend
[2];
83 /* Platform dependant DRC configuration */
84 const char **drc_texts
;
85 int drc_cfg
[WM8994_NUM_DRC
];
86 struct soc_enum drc_enum
;
88 /* Platform dependant ReTune mobile configuration */
89 int num_retune_mobile_texts
;
90 const char **retune_mobile_texts
;
91 int retune_mobile_cfg
[WM8994_NUM_EQ
];
92 struct soc_enum retune_mobile_enum
;
94 struct wm8994_micdet micdet
[2];
97 struct wm8994_pdata
*pdata
;
100 static int wm8994_readable(unsigned int reg
)
114 case WM8994_INTERRUPT_STATUS_1
:
115 case WM8994_INTERRUPT_STATUS_2
:
116 case WM8994_INTERRUPT_RAW_STATUS_2
:
122 if (reg
>= WM8994_CACHE_SIZE
)
124 return wm8994_access_masks
[reg
].readable
!= 0;
127 static int wm8994_volatile(unsigned int reg
)
129 if (reg
>= WM8994_REG_CACHE_SIZE
)
133 case WM8994_SOFTWARE_RESET
:
134 case WM8994_CHIP_REVISION
:
135 case WM8994_DC_SERVO_1
:
136 case WM8994_DC_SERVO_READBACK
:
137 case WM8994_RATE_STATUS
:
146 static int wm8994_write(struct snd_soc_codec
*codec
, unsigned int reg
,
149 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
151 BUG_ON(reg
> WM8994_MAX_REGISTER
);
153 if (!wm8994_volatile(reg
))
154 wm8994
->reg_cache
[reg
] = value
;
156 return wm8994_reg_write(codec
->control_data
, reg
, value
);
159 static unsigned int wm8994_read(struct snd_soc_codec
*codec
,
162 u16
*reg_cache
= codec
->reg_cache
;
164 BUG_ON(reg
> WM8994_MAX_REGISTER
);
166 if (wm8994_volatile(reg
))
167 return wm8994_reg_read(codec
->control_data
, reg
);
169 return reg_cache
[reg
];
172 static int configure_aif_clock(struct snd_soc_codec
*codec
, int aif
)
174 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
184 switch (wm8994
->sysclk
[aif
]) {
185 case WM8994_SYSCLK_MCLK1
:
186 rate
= wm8994
->mclk
[0];
189 case WM8994_SYSCLK_MCLK2
:
191 rate
= wm8994
->mclk
[1];
194 case WM8994_SYSCLK_FLL1
:
196 rate
= wm8994
->fll
[0].out
;
199 case WM8994_SYSCLK_FLL2
:
201 rate
= wm8994
->fll
[1].out
;
208 if (rate
>= 13500000) {
210 reg1
|= WM8994_AIF1CLK_DIV
;
212 dev_dbg(codec
->dev
, "Dividing AIF%d clock to %dHz\n",
216 if (rate
&& rate
< 3000000)
217 dev_warn(codec
->dev
, "AIF%dCLK is %dHz, should be >=3MHz for optimal performance\n",
220 wm8994
->aifclk
[aif
] = rate
;
222 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
+ offset
,
223 WM8994_AIF1CLK_SRC_MASK
| WM8994_AIF1CLK_DIV
,
229 static int configure_clock(struct snd_soc_codec
*codec
)
231 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
234 /* Bring up the AIF clocks first */
235 configure_aif_clock(codec
, 0);
236 configure_aif_clock(codec
, 1);
238 /* Then switch CLK_SYS over to the higher of them; a change
239 * can only happen as a result of a clocking change which can
240 * only be made outside of DAPM so we can safely redo the
244 /* If they're equal it doesn't matter which is used */
245 if (wm8994
->aifclk
[0] == wm8994
->aifclk
[1])
248 if (wm8994
->aifclk
[0] < wm8994
->aifclk
[1])
249 new = WM8994_SYSCLK_SRC
;
253 old
= snd_soc_read(codec
, WM8994_CLOCKING_1
) & WM8994_SYSCLK_SRC
;
255 /* If there's no change then we're done. */
259 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
, WM8994_SYSCLK_SRC
, new);
261 snd_soc_dapm_sync(&codec
->dapm
);
266 static int check_clk_sys(struct snd_soc_dapm_widget
*source
,
267 struct snd_soc_dapm_widget
*sink
)
269 int reg
= snd_soc_read(source
->codec
, WM8994_CLOCKING_1
);
272 /* Check what we're currently using for CLK_SYS */
273 if (reg
& WM8994_SYSCLK_SRC
)
278 return strcmp(source
->name
, clk
) == 0;
281 static const char *sidetone_hpf_text
[] = {
282 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
285 static const struct soc_enum sidetone_hpf
=
286 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 7, 7, sidetone_hpf_text
);
288 static const DECLARE_TLV_DB_SCALE(aif_tlv
, 0, 600, 0);
289 static const DECLARE_TLV_DB_SCALE(digital_tlv
, -7200, 75, 1);
290 static const DECLARE_TLV_DB_SCALE(st_tlv
, -3600, 300, 0);
291 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv
, -1600, 183, 0);
292 static const DECLARE_TLV_DB_SCALE(eq_tlv
, -1200, 100, 0);
294 #define WM8994_DRC_SWITCH(xname, reg, shift) \
295 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
296 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
297 .put = wm8994_put_drc_sw, \
298 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
300 static int wm8994_put_drc_sw(struct snd_kcontrol
*kcontrol
,
301 struct snd_ctl_elem_value
*ucontrol
)
303 struct soc_mixer_control
*mc
=
304 (struct soc_mixer_control
*)kcontrol
->private_value
;
305 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
308 /* Can't enable both ADC and DAC paths simultaneously */
309 if (mc
->shift
== WM8994_AIF1DAC1_DRC_ENA_SHIFT
)
310 mask
= WM8994_AIF1ADC1L_DRC_ENA_MASK
|
311 WM8994_AIF1ADC1R_DRC_ENA_MASK
;
313 mask
= WM8994_AIF1DAC1_DRC_ENA_MASK
;
315 ret
= snd_soc_read(codec
, mc
->reg
);
321 return snd_soc_put_volsw(kcontrol
, ucontrol
);
324 static void wm8994_set_drc(struct snd_soc_codec
*codec
, int drc
)
326 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
327 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
328 int base
= wm8994_drc_base
[drc
];
329 int cfg
= wm8994
->drc_cfg
[drc
];
332 /* Save any enables; the configuration should clear them. */
333 save
= snd_soc_read(codec
, base
);
334 save
&= WM8994_AIF1DAC1_DRC_ENA
| WM8994_AIF1ADC1L_DRC_ENA
|
335 WM8994_AIF1ADC1R_DRC_ENA
;
337 for (i
= 0; i
< WM8994_DRC_REGS
; i
++)
338 snd_soc_update_bits(codec
, base
+ i
, 0xffff,
339 pdata
->drc_cfgs
[cfg
].regs
[i
]);
341 snd_soc_update_bits(codec
, base
, WM8994_AIF1DAC1_DRC_ENA
|
342 WM8994_AIF1ADC1L_DRC_ENA
|
343 WM8994_AIF1ADC1R_DRC_ENA
, save
);
346 /* Icky as hell but saves code duplication */
347 static int wm8994_get_drc(const char *name
)
349 if (strcmp(name
, "AIF1DRC1 Mode") == 0)
351 if (strcmp(name
, "AIF1DRC2 Mode") == 0)
353 if (strcmp(name
, "AIF2DRC Mode") == 0)
358 static int wm8994_put_drc_enum(struct snd_kcontrol
*kcontrol
,
359 struct snd_ctl_elem_value
*ucontrol
)
361 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
362 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
363 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
364 int drc
= wm8994_get_drc(kcontrol
->id
.name
);
365 int value
= ucontrol
->value
.integer
.value
[0];
370 if (value
>= pdata
->num_drc_cfgs
)
373 wm8994
->drc_cfg
[drc
] = value
;
375 wm8994_set_drc(codec
, drc
);
380 static int wm8994_get_drc_enum(struct snd_kcontrol
*kcontrol
,
381 struct snd_ctl_elem_value
*ucontrol
)
383 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
384 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
385 int drc
= wm8994_get_drc(kcontrol
->id
.name
);
387 ucontrol
->value
.enumerated
.item
[0] = wm8994
->drc_cfg
[drc
];
392 static void wm8994_set_retune_mobile(struct snd_soc_codec
*codec
, int block
)
394 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
395 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
396 int base
= wm8994_retune_mobile_base
[block
];
397 int iface
, best
, best_val
, save
, i
, cfg
;
399 if (!pdata
|| !wm8994
->num_retune_mobile_texts
)
414 /* Find the version of the currently selected configuration
415 * with the nearest sample rate. */
416 cfg
= wm8994
->retune_mobile_cfg
[block
];
419 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
420 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
421 wm8994
->retune_mobile_texts
[cfg
]) == 0 &&
422 abs(pdata
->retune_mobile_cfgs
[i
].rate
423 - wm8994
->dac_rates
[iface
]) < best_val
) {
425 best_val
= abs(pdata
->retune_mobile_cfgs
[i
].rate
426 - wm8994
->dac_rates
[iface
]);
430 dev_dbg(codec
->dev
, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
432 pdata
->retune_mobile_cfgs
[best
].name
,
433 pdata
->retune_mobile_cfgs
[best
].rate
,
434 wm8994
->dac_rates
[iface
]);
436 /* The EQ will be disabled while reconfiguring it, remember the
437 * current configuration.
439 save
= snd_soc_read(codec
, base
);
440 save
&= WM8994_AIF1DAC1_EQ_ENA
;
442 for (i
= 0; i
< WM8994_EQ_REGS
; i
++)
443 snd_soc_update_bits(codec
, base
+ i
, 0xffff,
444 pdata
->retune_mobile_cfgs
[best
].regs
[i
]);
446 snd_soc_update_bits(codec
, base
, WM8994_AIF1DAC1_EQ_ENA
, save
);
449 /* Icky as hell but saves code duplication */
450 static int wm8994_get_retune_mobile_block(const char *name
)
452 if (strcmp(name
, "AIF1.1 EQ Mode") == 0)
454 if (strcmp(name
, "AIF1.2 EQ Mode") == 0)
456 if (strcmp(name
, "AIF2 EQ Mode") == 0)
461 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
462 struct snd_ctl_elem_value
*ucontrol
)
464 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
465 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
466 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
467 int block
= wm8994_get_retune_mobile_block(kcontrol
->id
.name
);
468 int value
= ucontrol
->value
.integer
.value
[0];
473 if (value
>= pdata
->num_retune_mobile_cfgs
)
476 wm8994
->retune_mobile_cfg
[block
] = value
;
478 wm8994_set_retune_mobile(codec
, block
);
483 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
484 struct snd_ctl_elem_value
*ucontrol
)
486 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
487 struct wm8994_priv
*wm8994
=snd_soc_codec_get_drvdata(codec
);
488 int block
= wm8994_get_retune_mobile_block(kcontrol
->id
.name
);
490 ucontrol
->value
.enumerated
.item
[0] = wm8994
->retune_mobile_cfg
[block
];
495 static const char *aif_chan_src_text
[] = {
499 static const struct soc_enum aif1adcl_src
=
500 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1
, 15, 2, aif_chan_src_text
);
502 static const struct soc_enum aif1adcr_src
=
503 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1
, 14, 2, aif_chan_src_text
);
505 static const struct soc_enum aif2adcl_src
=
506 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1
, 15, 2, aif_chan_src_text
);
508 static const struct soc_enum aif2adcr_src
=
509 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1
, 14, 2, aif_chan_src_text
);
511 static const struct soc_enum aif1dacl_src
=
512 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2
, 15, 2, aif_chan_src_text
);
514 static const struct soc_enum aif1dacr_src
=
515 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2
, 14, 2, aif_chan_src_text
);
517 static const struct soc_enum aif2dacl_src
=
518 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2
, 15, 2, aif_chan_src_text
);
520 static const struct soc_enum aif2dacr_src
=
521 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2
, 14, 2, aif_chan_src_text
);
523 static const struct snd_kcontrol_new wm8994_snd_controls
[] = {
524 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME
,
525 WM8994_AIF1_ADC1_RIGHT_VOLUME
,
526 1, 119, 0, digital_tlv
),
527 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME
,
528 WM8994_AIF1_ADC2_RIGHT_VOLUME
,
529 1, 119, 0, digital_tlv
),
530 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME
,
531 WM8994_AIF2_ADC_RIGHT_VOLUME
,
532 1, 119, 0, digital_tlv
),
534 SOC_ENUM("AIF1ADCL Source", aif1adcl_src
),
535 SOC_ENUM("AIF1ADCR Source", aif1adcr_src
),
536 SOC_ENUM("AIF2ADCL Source", aif1adcl_src
),
537 SOC_ENUM("AIF2ADCR Source", aif1adcr_src
),
539 SOC_ENUM("AIF1DACL Source", aif1dacl_src
),
540 SOC_ENUM("AIF1DACR Source", aif1dacr_src
),
541 SOC_ENUM("AIF2DACL Source", aif1dacl_src
),
542 SOC_ENUM("AIF2DACR Source", aif1dacr_src
),
544 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME
,
545 WM8994_AIF1_DAC1_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
546 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME
,
547 WM8994_AIF1_DAC2_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
548 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME
,
549 WM8994_AIF2_DAC_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
551 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2
, 10, 3, 0, aif_tlv
),
552 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2
, 10, 3, 0, aif_tlv
),
554 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1
, 0, 1, 0),
555 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1
, 0, 1, 0),
556 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1
, 0, 1, 0),
558 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1
, 2),
559 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1
, 1),
560 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1
, 0),
562 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1
, 2),
563 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1
, 1),
564 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1
, 0),
566 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1
, 2),
567 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1
, 1),
568 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1
, 0),
570 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES
,
572 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES
,
574 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES
,
576 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES
,
578 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf
),
579 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE
, 6, 1, 0),
581 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME
,
582 WM8994_DAC1_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
583 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME
,
584 WM8994_DAC1_RIGHT_VOLUME
, 9, 1, 1),
586 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME
,
587 WM8994_DAC2_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
588 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME
,
589 WM8994_DAC2_RIGHT_VOLUME
, 9, 1, 1),
591 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION
,
592 6, 1, 1, wm_hubs_spkmix_tlv
),
593 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION
,
594 2, 1, 1, wm_hubs_spkmix_tlv
),
596 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION
,
597 6, 1, 1, wm_hubs_spkmix_tlv
),
598 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION
,
599 2, 1, 1, wm_hubs_spkmix_tlv
),
601 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2
,
602 10, 15, 0, wm8994_3d_tlv
),
603 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2
,
605 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2
,
606 10, 15, 0, wm8994_3d_tlv
),
607 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2
,
609 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2
,
610 10, 15, 0, wm8994_3d_tlv
),
611 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2
,
615 static const struct snd_kcontrol_new wm8994_eq_controls
[] = {
616 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 11, 31, 0,
618 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 6, 31, 0,
620 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 1, 31, 0,
622 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2
, 11, 31, 0,
624 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2
, 6, 31, 0,
627 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 11, 31, 0,
629 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 6, 31, 0,
631 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 1, 31, 0,
633 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2
, 11, 31, 0,
635 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2
, 6, 31, 0,
638 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1
, 11, 31, 0,
640 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1
, 6, 31, 0,
642 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1
, 1, 31, 0,
644 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2
, 11, 31, 0,
646 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2
, 6, 31, 0,
650 static int clk_sys_event(struct snd_soc_dapm_widget
*w
,
651 struct snd_kcontrol
*kcontrol
, int event
)
653 struct snd_soc_codec
*codec
= w
->codec
;
656 case SND_SOC_DAPM_PRE_PMU
:
657 return configure_clock(codec
);
659 case SND_SOC_DAPM_POST_PMD
:
660 configure_clock(codec
);
667 static void wm8994_update_class_w(struct snd_soc_codec
*codec
)
669 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
671 int source
= 0; /* GCC flow analysis can't track enable */
674 /* Only support direct DAC->headphone paths */
675 reg
= snd_soc_read(codec
, WM8994_OUTPUT_MIXER_1
);
676 if (!(reg
& WM8994_DAC1L_TO_HPOUT1L
)) {
677 dev_vdbg(codec
->dev
, "HPL connected to output mixer\n");
681 reg
= snd_soc_read(codec
, WM8994_OUTPUT_MIXER_2
);
682 if (!(reg
& WM8994_DAC1R_TO_HPOUT1R
)) {
683 dev_vdbg(codec
->dev
, "HPR connected to output mixer\n");
687 /* We also need the same setting for L/R and only one path */
688 reg
= snd_soc_read(codec
, WM8994_DAC1_LEFT_MIXER_ROUTING
);
690 case WM8994_AIF2DACL_TO_DAC1L
:
691 dev_vdbg(codec
->dev
, "Class W source AIF2DAC\n");
692 source
= 2 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
694 case WM8994_AIF1DAC2L_TO_DAC1L
:
695 dev_vdbg(codec
->dev
, "Class W source AIF1DAC2\n");
696 source
= 1 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
698 case WM8994_AIF1DAC1L_TO_DAC1L
:
699 dev_vdbg(codec
->dev
, "Class W source AIF1DAC1\n");
700 source
= 0 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
703 dev_vdbg(codec
->dev
, "DAC mixer setting: %x\n", reg
);
708 reg_r
= snd_soc_read(codec
, WM8994_DAC1_RIGHT_MIXER_ROUTING
);
710 dev_vdbg(codec
->dev
, "Left and right DAC mixers different\n");
715 dev_dbg(codec
->dev
, "Class W enabled\n");
716 snd_soc_update_bits(codec
, WM8994_CLASS_W_1
,
718 WM8994_CP_DYN_SRC_SEL_MASK
,
719 source
| WM8994_CP_DYN_PWR
);
720 wm8994
->hubs
.class_w
= true;
723 dev_dbg(codec
->dev
, "Class W disabled\n");
724 snd_soc_update_bits(codec
, WM8994_CLASS_W_1
,
725 WM8994_CP_DYN_PWR
, 0);
726 wm8994
->hubs
.class_w
= false;
730 static const char *hp_mux_text
[] = {
735 #define WM8994_HP_ENUM(xname, xenum) \
736 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
737 .info = snd_soc_info_enum_double, \
738 .get = snd_soc_dapm_get_enum_double, \
739 .put = wm8994_put_hp_enum, \
740 .private_value = (unsigned long)&xenum }
742 static int wm8994_put_hp_enum(struct snd_kcontrol
*kcontrol
,
743 struct snd_ctl_elem_value
*ucontrol
)
745 struct snd_soc_dapm_widget
*w
= snd_kcontrol_chip(kcontrol
);
746 struct snd_soc_codec
*codec
= w
->codec
;
749 ret
= snd_soc_dapm_put_enum_double(kcontrol
, ucontrol
);
751 wm8994_update_class_w(codec
);
756 static const struct soc_enum hpl_enum
=
757 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1
, 8, 2, hp_mux_text
);
759 static const struct snd_kcontrol_new hpl_mux
=
760 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum
);
762 static const struct soc_enum hpr_enum
=
763 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2
, 8, 2, hp_mux_text
);
765 static const struct snd_kcontrol_new hpr_mux
=
766 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum
);
768 static const char *adc_mux_text
[] = {
773 static const struct soc_enum adc_enum
=
774 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text
);
776 static const struct snd_kcontrol_new adcl_mux
=
777 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum
);
779 static const struct snd_kcontrol_new adcr_mux
=
780 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum
);
782 static const struct snd_kcontrol_new left_speaker_mixer
[] = {
783 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER
, 9, 1, 0),
784 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER
, 7, 1, 0),
785 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER
, 5, 1, 0),
786 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER
, 3, 1, 0),
787 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER
, 1, 1, 0),
790 static const struct snd_kcontrol_new right_speaker_mixer
[] = {
791 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER
, 8, 1, 0),
792 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER
, 6, 1, 0),
793 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER
, 4, 1, 0),
794 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER
, 2, 1, 0),
795 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER
, 0, 1, 0),
798 /* Debugging; dump chip status after DAPM transitions */
799 static int post_ev(struct snd_soc_dapm_widget
*w
,
800 struct snd_kcontrol
*kcontrol
, int event
)
802 struct snd_soc_codec
*codec
= w
->codec
;
803 dev_dbg(codec
->dev
, "SRC status: %x\n",
805 WM8994_RATE_STATUS
));
809 static const struct snd_kcontrol_new aif1adc1l_mix
[] = {
810 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING
,
812 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING
,
816 static const struct snd_kcontrol_new aif1adc1r_mix
[] = {
817 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING
,
819 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING
,
823 static const struct snd_kcontrol_new aif1adc2l_mix
[] = {
824 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING
,
826 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING
,
830 static const struct snd_kcontrol_new aif1adc2r_mix
[] = {
831 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING
,
833 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING
,
837 static const struct snd_kcontrol_new aif2dac2l_mix
[] = {
838 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
840 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
842 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
844 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
846 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
850 static const struct snd_kcontrol_new aif2dac2r_mix
[] = {
851 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
853 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
855 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
857 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
859 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
863 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
864 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
865 .info = snd_soc_info_volsw, \
866 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
867 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
869 static int wm8994_put_class_w(struct snd_kcontrol
*kcontrol
,
870 struct snd_ctl_elem_value
*ucontrol
)
872 struct snd_soc_dapm_widget
*w
= snd_kcontrol_chip(kcontrol
);
873 struct snd_soc_codec
*codec
= w
->codec
;
876 ret
= snd_soc_dapm_put_volsw(kcontrol
, ucontrol
);
878 wm8994_update_class_w(codec
);
883 static const struct snd_kcontrol_new dac1l_mix
[] = {
884 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
886 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
888 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
890 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
892 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
896 static const struct snd_kcontrol_new dac1r_mix
[] = {
897 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
899 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
901 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
903 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
905 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
909 static const char *sidetone_text
[] = {
910 "ADC/DMIC1", "DMIC2",
913 static const struct soc_enum sidetone1_enum
=
914 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 0, 2, sidetone_text
);
916 static const struct snd_kcontrol_new sidetone1_mux
=
917 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum
);
919 static const struct soc_enum sidetone2_enum
=
920 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 1, 2, sidetone_text
);
922 static const struct snd_kcontrol_new sidetone2_mux
=
923 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum
);
925 static const char *aif1dac_text
[] = {
926 "AIF1DACDAT", "AIF3DACDAT",
929 static const struct soc_enum aif1dac_enum
=
930 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 0, 2, aif1dac_text
);
932 static const struct snd_kcontrol_new aif1dac_mux
=
933 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum
);
935 static const char *aif2dac_text
[] = {
936 "AIF2DACDAT", "AIF3DACDAT",
939 static const struct soc_enum aif2dac_enum
=
940 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 1, 2, aif2dac_text
);
942 static const struct snd_kcontrol_new aif2dac_mux
=
943 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum
);
945 static const char *aif2adc_text
[] = {
946 "AIF2ADCDAT", "AIF3DACDAT",
949 static const struct soc_enum aif2adc_enum
=
950 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 2, 2, aif2adc_text
);
952 static const struct snd_kcontrol_new aif2adc_mux
=
953 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum
);
955 static const char *aif3adc_text
[] = {
956 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT",
959 static const struct soc_enum aif3adc_enum
=
960 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 3, 3, aif3adc_text
);
962 static const struct snd_kcontrol_new aif3adc_mux
=
963 SOC_DAPM_ENUM("AIF3ADC Mux", aif3adc_enum
);
965 static const struct snd_soc_dapm_widget wm8994_dapm_widgets
[] = {
966 SND_SOC_DAPM_INPUT("DMIC1DAT"),
967 SND_SOC_DAPM_INPUT("DMIC2DAT"),
968 SND_SOC_DAPM_INPUT("Clock"),
970 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM
, 0, 0, clk_sys_event
,
971 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
973 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1
, 3, 0, NULL
, 0),
974 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1
, 2, 0, NULL
, 0),
975 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1
, 1, 0, NULL
, 0),
977 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1
, 0, 0, NULL
, 0),
978 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1
, 0, 0, NULL
, 0),
980 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture",
981 0, WM8994_POWER_MANAGEMENT_4
, 9, 0),
982 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture",
983 0, WM8994_POWER_MANAGEMENT_4
, 8, 0),
984 SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL
, 0,
985 WM8994_POWER_MANAGEMENT_5
, 9, 0),
986 SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL
, 0,
987 WM8994_POWER_MANAGEMENT_5
, 8, 0),
989 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture",
990 0, WM8994_POWER_MANAGEMENT_4
, 11, 0),
991 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture",
992 0, WM8994_POWER_MANAGEMENT_4
, 10, 0),
993 SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL
, 0,
994 WM8994_POWER_MANAGEMENT_5
, 11, 0),
995 SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL
, 0,
996 WM8994_POWER_MANAGEMENT_5
, 10, 0),
998 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM
, 0, 0,
999 aif1adc1l_mix
, ARRAY_SIZE(aif1adc1l_mix
)),
1000 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM
, 0, 0,
1001 aif1adc1r_mix
, ARRAY_SIZE(aif1adc1r_mix
)),
1003 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM
, 0, 0,
1004 aif1adc2l_mix
, ARRAY_SIZE(aif1adc2l_mix
)),
1005 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM
, 0, 0,
1006 aif1adc2r_mix
, ARRAY_SIZE(aif1adc2r_mix
)),
1008 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM
, 0, 0,
1009 aif2dac2l_mix
, ARRAY_SIZE(aif2dac2l_mix
)),
1010 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM
, 0, 0,
1011 aif2dac2r_mix
, ARRAY_SIZE(aif2dac2r_mix
)),
1013 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM
, 0, 0, &sidetone1_mux
),
1014 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM
, 0, 0, &sidetone2_mux
),
1016 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM
, 0, 0,
1017 dac1l_mix
, ARRAY_SIZE(dac1l_mix
)),
1018 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM
, 0, 0,
1019 dac1r_mix
, ARRAY_SIZE(dac1r_mix
)),
1021 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL
, 0,
1022 WM8994_POWER_MANAGEMENT_4
, 13, 0),
1023 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL
, 0,
1024 WM8994_POWER_MANAGEMENT_4
, 12, 0),
1025 SND_SOC_DAPM_AIF_IN("AIF2DACL", NULL
, 0,
1026 WM8994_POWER_MANAGEMENT_5
, 13, 0),
1027 SND_SOC_DAPM_AIF_IN("AIF2DACR", NULL
, 0,
1028 WM8994_POWER_MANAGEMENT_5
, 12, 0),
1030 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM
, 0, 0),
1031 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM
, 0, 0),
1032 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM
, 0, 0),
1034 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM
, 0, 0, &aif1dac_mux
),
1035 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM
, 0, 0, &aif2dac_mux
),
1036 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM
, 0, 0, &aif2adc_mux
),
1037 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM
, 0, 0, &aif3adc_mux
),
1039 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM
, 0, 0),
1040 SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM
, 0, 0),
1042 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1
, 4, 0, NULL
, 0),
1044 SND_SOC_DAPM_ADC("DMIC2L", NULL
, WM8994_POWER_MANAGEMENT_4
, 5, 0),
1045 SND_SOC_DAPM_ADC("DMIC2R", NULL
, WM8994_POWER_MANAGEMENT_4
, 4, 0),
1046 SND_SOC_DAPM_ADC("DMIC1L", NULL
, WM8994_POWER_MANAGEMENT_4
, 3, 0),
1047 SND_SOC_DAPM_ADC("DMIC1R", NULL
, WM8994_POWER_MANAGEMENT_4
, 2, 0),
1049 /* Power is done with the muxes since the ADC power also controls the
1050 * downsampling chain, the chip will automatically manage the analogue
1051 * specific portions.
1053 SND_SOC_DAPM_ADC("ADCL", NULL
, SND_SOC_NOPM
, 1, 0),
1054 SND_SOC_DAPM_ADC("ADCR", NULL
, SND_SOC_NOPM
, 0, 0),
1056 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4
, 1, 0, &adcl_mux
),
1057 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4
, 0, 0, &adcr_mux
),
1059 SND_SOC_DAPM_DAC("DAC2L", NULL
, WM8994_POWER_MANAGEMENT_5
, 3, 0),
1060 SND_SOC_DAPM_DAC("DAC2R", NULL
, WM8994_POWER_MANAGEMENT_5
, 2, 0),
1061 SND_SOC_DAPM_DAC("DAC1L", NULL
, WM8994_POWER_MANAGEMENT_5
, 1, 0),
1062 SND_SOC_DAPM_DAC("DAC1R", NULL
, WM8994_POWER_MANAGEMENT_5
, 0, 0),
1064 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM
, 0, 0, &hpl_mux
),
1065 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM
, 0, 0, &hpr_mux
),
1067 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3
, 8, 0,
1068 left_speaker_mixer
, ARRAY_SIZE(left_speaker_mixer
)),
1069 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3
, 9, 0,
1070 right_speaker_mixer
, ARRAY_SIZE(right_speaker_mixer
)),
1072 SND_SOC_DAPM_POST("Debug log", post_ev
),
1075 static const struct snd_soc_dapm_route intercon
[] = {
1077 { "CLK_SYS", NULL
, "AIF1CLK", check_clk_sys
},
1078 { "CLK_SYS", NULL
, "AIF2CLK", check_clk_sys
},
1080 { "DSP1CLK", NULL
, "CLK_SYS" },
1081 { "DSP2CLK", NULL
, "CLK_SYS" },
1082 { "DSPINTCLK", NULL
, "CLK_SYS" },
1084 { "AIF1ADC1L", NULL
, "AIF1CLK" },
1085 { "AIF1ADC1L", NULL
, "DSP1CLK" },
1086 { "AIF1ADC1R", NULL
, "AIF1CLK" },
1087 { "AIF1ADC1R", NULL
, "DSP1CLK" },
1088 { "AIF1ADC1R", NULL
, "DSPINTCLK" },
1090 { "AIF1DAC1L", NULL
, "AIF1CLK" },
1091 { "AIF1DAC1L", NULL
, "DSP1CLK" },
1092 { "AIF1DAC1R", NULL
, "AIF1CLK" },
1093 { "AIF1DAC1R", NULL
, "DSP1CLK" },
1094 { "AIF1DAC1R", NULL
, "DSPINTCLK" },
1096 { "AIF1ADC2L", NULL
, "AIF1CLK" },
1097 { "AIF1ADC2L", NULL
, "DSP1CLK" },
1098 { "AIF1ADC2R", NULL
, "AIF1CLK" },
1099 { "AIF1ADC2R", NULL
, "DSP1CLK" },
1100 { "AIF1ADC2R", NULL
, "DSPINTCLK" },
1102 { "AIF1DAC2L", NULL
, "AIF1CLK" },
1103 { "AIF1DAC2L", NULL
, "DSP1CLK" },
1104 { "AIF1DAC2R", NULL
, "AIF1CLK" },
1105 { "AIF1DAC2R", NULL
, "DSP1CLK" },
1106 { "AIF1DAC2R", NULL
, "DSPINTCLK" },
1108 { "AIF2ADCL", NULL
, "AIF2CLK" },
1109 { "AIF2ADCL", NULL
, "DSP2CLK" },
1110 { "AIF2ADCR", NULL
, "AIF2CLK" },
1111 { "AIF2ADCR", NULL
, "DSP2CLK" },
1112 { "AIF2ADCR", NULL
, "DSPINTCLK" },
1114 { "AIF2DACL", NULL
, "AIF2CLK" },
1115 { "AIF2DACL", NULL
, "DSP2CLK" },
1116 { "AIF2DACR", NULL
, "AIF2CLK" },
1117 { "AIF2DACR", NULL
, "DSP2CLK" },
1118 { "AIF2DACR", NULL
, "DSPINTCLK" },
1120 { "DMIC1L", NULL
, "DMIC1DAT" },
1121 { "DMIC1L", NULL
, "CLK_SYS" },
1122 { "DMIC1R", NULL
, "DMIC1DAT" },
1123 { "DMIC1R", NULL
, "CLK_SYS" },
1124 { "DMIC2L", NULL
, "DMIC2DAT" },
1125 { "DMIC2L", NULL
, "CLK_SYS" },
1126 { "DMIC2R", NULL
, "DMIC2DAT" },
1127 { "DMIC2R", NULL
, "CLK_SYS" },
1129 { "ADCL", NULL
, "AIF1CLK" },
1130 { "ADCL", NULL
, "DSP1CLK" },
1131 { "ADCL", NULL
, "DSPINTCLK" },
1133 { "ADCR", NULL
, "AIF1CLK" },
1134 { "ADCR", NULL
, "DSP1CLK" },
1135 { "ADCR", NULL
, "DSPINTCLK" },
1137 { "ADCL Mux", "ADC", "ADCL" },
1138 { "ADCL Mux", "DMIC", "DMIC1L" },
1139 { "ADCR Mux", "ADC", "ADCR" },
1140 { "ADCR Mux", "DMIC", "DMIC1R" },
1142 { "DAC1L", NULL
, "AIF1CLK" },
1143 { "DAC1L", NULL
, "DSP1CLK" },
1144 { "DAC1L", NULL
, "DSPINTCLK" },
1146 { "DAC1R", NULL
, "AIF1CLK" },
1147 { "DAC1R", NULL
, "DSP1CLK" },
1148 { "DAC1R", NULL
, "DSPINTCLK" },
1150 { "DAC2L", NULL
, "AIF2CLK" },
1151 { "DAC2L", NULL
, "DSP2CLK" },
1152 { "DAC2L", NULL
, "DSPINTCLK" },
1154 { "DAC2R", NULL
, "AIF2DACR" },
1155 { "DAC2R", NULL
, "AIF2CLK" },
1156 { "DAC2R", NULL
, "DSP2CLK" },
1157 { "DAC2R", NULL
, "DSPINTCLK" },
1159 { "TOCLK", NULL
, "CLK_SYS" },
1162 { "AIF1ADC1L", NULL
, "AIF1ADC1L Mixer" },
1163 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1164 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1166 { "AIF1ADC1R", NULL
, "AIF1ADC1R Mixer" },
1167 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1168 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1170 { "AIF1ADC2L", NULL
, "AIF1ADC2L Mixer" },
1171 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1172 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1174 { "AIF1ADC2R", NULL
, "AIF1ADC2R Mixer" },
1175 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1176 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1178 /* Pin level routing for AIF3 */
1179 { "AIF1DAC1L", NULL
, "AIF1DAC Mux" },
1180 { "AIF1DAC1R", NULL
, "AIF1DAC Mux" },
1181 { "AIF1DAC2L", NULL
, "AIF1DAC Mux" },
1182 { "AIF1DAC2R", NULL
, "AIF1DAC Mux" },
1184 { "AIF2DACL", NULL
, "AIF2DAC Mux" },
1185 { "AIF2DACR", NULL
, "AIF2DAC Mux" },
1187 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1188 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1189 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1190 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1191 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1192 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1193 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1196 { "DAC1L", NULL
, "DAC1L Mixer" },
1197 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1198 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1199 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1200 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1201 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1203 { "DAC1R", NULL
, "DAC1R Mixer" },
1204 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1205 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1206 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1207 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1208 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1210 /* DAC2/AIF2 outputs */
1211 { "AIF2ADCL", NULL
, "AIF2DAC2L Mixer" },
1212 { "DAC2L", NULL
, "AIF2DAC2L Mixer" },
1213 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1214 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1215 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1216 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1217 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1219 { "AIF2ADCR", NULL
, "AIF2DAC2R Mixer" },
1220 { "DAC2R", NULL
, "AIF2DAC2R Mixer" },
1221 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1222 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1223 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1224 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1225 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1227 { "AIF2ADCDAT", NULL
, "AIF2ADC Mux" },
1230 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1231 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1232 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1233 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1234 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1235 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1236 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1237 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1240 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1241 { "Left Sidetone", "DMIC2", "DMIC2L" },
1242 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1243 { "Right Sidetone", "DMIC2", "DMIC2R" },
1246 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1247 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1249 { "SPKL", "DAC1 Switch", "DAC1L" },
1250 { "SPKL", "DAC2 Switch", "DAC2L" },
1252 { "SPKR", "DAC1 Switch", "DAC1R" },
1253 { "SPKR", "DAC2 Switch", "DAC2R" },
1255 { "Left Headphone Mux", "DAC", "DAC1L" },
1256 { "Right Headphone Mux", "DAC", "DAC1R" },
1259 /* The size in bits of the FLL divide multiplied by 10
1260 * to allow rounding later */
1261 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1271 static int wm8994_get_fll_config(struct fll_div
*fll
,
1272 int freq_in
, int freq_out
)
1275 unsigned int K
, Ndiv
, Nmod
;
1277 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in
, freq_out
);
1279 /* Scale the input frequency down to <= 13.5MHz */
1280 fll
->clk_ref_div
= 0;
1281 while (freq_in
> 13500000) {
1285 if (fll
->clk_ref_div
> 3)
1288 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll
->clk_ref_div
, freq_in
);
1290 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1292 while (freq_out
* (fll
->outdiv
+ 1) < 90000000) {
1294 if (fll
->outdiv
> 63)
1297 freq_out
*= fll
->outdiv
+ 1;
1298 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll
->outdiv
, freq_out
);
1300 if (freq_in
> 1000000) {
1301 fll
->fll_fratio
= 0;
1302 } else if (freq_in
> 256000) {
1303 fll
->fll_fratio
= 1;
1305 } else if (freq_in
> 128000) {
1306 fll
->fll_fratio
= 2;
1308 } else if (freq_in
> 64000) {
1309 fll
->fll_fratio
= 3;
1312 fll
->fll_fratio
= 4;
1315 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll
->fll_fratio
, freq_in
);
1317 /* Now, calculate N.K */
1318 Ndiv
= freq_out
/ freq_in
;
1321 Nmod
= freq_out
% freq_in
;
1322 pr_debug("Nmod=%d\n", Nmod
);
1324 /* Calculate fractional part - scale up so we can round. */
1325 Kpart
= FIXED_FLL_SIZE
* (long long)Nmod
;
1327 do_div(Kpart
, freq_in
);
1329 K
= Kpart
& 0xFFFFFFFF;
1334 /* Move down to proper range now rounding is done */
1337 pr_debug("N=%x K=%x\n", fll
->n
, fll
->k
);
1342 static int _wm8994_set_fll(struct snd_soc_codec
*codec
, int id
, int src
,
1343 unsigned int freq_in
, unsigned int freq_out
)
1345 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1346 int reg_offset
, ret
;
1348 u16 reg
, aif1
, aif2
;
1350 aif1
= snd_soc_read(codec
, WM8994_AIF1_CLOCKING_1
)
1351 & WM8994_AIF1CLK_ENA
;
1353 aif2
= snd_soc_read(codec
, WM8994_AIF2_CLOCKING_1
)
1354 & WM8994_AIF2CLK_ENA
;
1371 /* Allow no source specification when stopping */
1375 case WM8994_FLL_SRC_MCLK1
:
1376 case WM8994_FLL_SRC_MCLK2
:
1377 case WM8994_FLL_SRC_LRCLK
:
1378 case WM8994_FLL_SRC_BCLK
:
1384 /* Are we changing anything? */
1385 if (wm8994
->fll
[id
].src
== src
&&
1386 wm8994
->fll
[id
].in
== freq_in
&& wm8994
->fll
[id
].out
== freq_out
)
1389 /* If we're stopping the FLL redo the old config - no
1390 * registers will actually be written but we avoid GCC flow
1391 * analysis bugs spewing warnings.
1394 ret
= wm8994_get_fll_config(&fll
, freq_in
, freq_out
);
1396 ret
= wm8994_get_fll_config(&fll
, wm8994
->fll
[id
].in
,
1397 wm8994
->fll
[id
].out
);
1401 /* Gate the AIF clocks while we reclock */
1402 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
1403 WM8994_AIF1CLK_ENA
, 0);
1404 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
1405 WM8994_AIF2CLK_ENA
, 0);
1407 /* We always need to disable the FLL while reconfiguring */
1408 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
,
1409 WM8994_FLL1_ENA
, 0);
1411 reg
= (fll
.outdiv
<< WM8994_FLL1_OUTDIV_SHIFT
) |
1412 (fll
.fll_fratio
<< WM8994_FLL1_FRATIO_SHIFT
);
1413 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_2
+ reg_offset
,
1414 WM8994_FLL1_OUTDIV_MASK
|
1415 WM8994_FLL1_FRATIO_MASK
, reg
);
1417 snd_soc_write(codec
, WM8994_FLL1_CONTROL_3
+ reg_offset
, fll
.k
);
1419 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_4
+ reg_offset
,
1421 fll
.n
<< WM8994_FLL1_N_SHIFT
);
1423 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_5
+ reg_offset
,
1424 WM8994_FLL1_REFCLK_DIV_MASK
|
1425 WM8994_FLL1_REFCLK_SRC_MASK
,
1426 (fll
.clk_ref_div
<< WM8994_FLL1_REFCLK_DIV_SHIFT
) |
1429 /* Enable (with fractional mode if required) */
1432 reg
= WM8994_FLL1_ENA
| WM8994_FLL1_FRAC
;
1434 reg
= WM8994_FLL1_ENA
;
1435 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
,
1436 WM8994_FLL1_ENA
| WM8994_FLL1_FRAC
,
1440 wm8994
->fll
[id
].in
= freq_in
;
1441 wm8994
->fll
[id
].out
= freq_out
;
1442 wm8994
->fll
[id
].src
= src
;
1444 /* Enable any gated AIF clocks */
1445 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
1446 WM8994_AIF1CLK_ENA
, aif1
);
1447 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
1448 WM8994_AIF2CLK_ENA
, aif2
);
1450 configure_clock(codec
);
1456 static int opclk_divs
[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1458 static int wm8994_set_fll(struct snd_soc_dai
*dai
, int id
, int src
,
1459 unsigned int freq_in
, unsigned int freq_out
)
1461 return _wm8994_set_fll(dai
->codec
, id
, src
, freq_in
, freq_out
);
1464 static int wm8994_set_dai_sysclk(struct snd_soc_dai
*dai
,
1465 int clk_id
, unsigned int freq
, int dir
)
1467 struct snd_soc_codec
*codec
= dai
->codec
;
1468 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1477 /* AIF3 shares clocking with AIF1/2 */
1482 case WM8994_SYSCLK_MCLK1
:
1483 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_MCLK1
;
1484 wm8994
->mclk
[0] = freq
;
1485 dev_dbg(dai
->dev
, "AIF%d using MCLK1 at %uHz\n",
1489 case WM8994_SYSCLK_MCLK2
:
1490 /* TODO: Set GPIO AF */
1491 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_MCLK2
;
1492 wm8994
->mclk
[1] = freq
;
1493 dev_dbg(dai
->dev
, "AIF%d using MCLK2 at %uHz\n",
1497 case WM8994_SYSCLK_FLL1
:
1498 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_FLL1
;
1499 dev_dbg(dai
->dev
, "AIF%d using FLL1\n", dai
->id
);
1502 case WM8994_SYSCLK_FLL2
:
1503 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_FLL2
;
1504 dev_dbg(dai
->dev
, "AIF%d using FLL2\n", dai
->id
);
1507 case WM8994_SYSCLK_OPCLK
:
1508 /* Special case - a division (times 10) is given and
1509 * no effect on main clocking.
1512 for (i
= 0; i
< ARRAY_SIZE(opclk_divs
); i
++)
1513 if (opclk_divs
[i
] == freq
)
1515 if (i
== ARRAY_SIZE(opclk_divs
))
1517 snd_soc_update_bits(codec
, WM8994_CLOCKING_2
,
1518 WM8994_OPCLK_DIV_MASK
, i
);
1519 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_2
,
1520 WM8994_OPCLK_ENA
, WM8994_OPCLK_ENA
);
1522 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_2
,
1523 WM8994_OPCLK_ENA
, 0);
1530 configure_clock(codec
);
1535 static int wm8994_set_bias_level(struct snd_soc_codec
*codec
,
1536 enum snd_soc_bias_level level
)
1538 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1541 case SND_SOC_BIAS_ON
:
1544 case SND_SOC_BIAS_PREPARE
:
1546 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
1547 WM8994_VMID_SEL_MASK
, 0x2);
1550 case SND_SOC_BIAS_STANDBY
:
1551 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
1552 /* Tweak DC servo and DSP configuration for
1553 * improved performance. */
1554 if (wm8994
->revision
< 4) {
1555 /* Tweak DC servo and DSP configuration for
1556 * improved performance. */
1557 snd_soc_write(codec
, 0x102, 0x3);
1558 snd_soc_write(codec
, 0x56, 0x3);
1559 snd_soc_write(codec
, 0x817, 0);
1560 snd_soc_write(codec
, 0x102, 0);
1563 /* Discharge LINEOUT1 & 2 */
1564 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
1565 WM8994_LINEOUT1_DISCH
|
1566 WM8994_LINEOUT2_DISCH
,
1567 WM8994_LINEOUT1_DISCH
|
1568 WM8994_LINEOUT2_DISCH
);
1570 /* Startup bias, VMID ramp & buffer */
1571 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
1572 WM8994_STARTUP_BIAS_ENA
|
1573 WM8994_VMID_BUF_ENA
|
1574 WM8994_VMID_RAMP_MASK
,
1575 WM8994_STARTUP_BIAS_ENA
|
1576 WM8994_VMID_BUF_ENA
|
1577 (0x11 << WM8994_VMID_RAMP_SHIFT
));
1579 /* Main bias enable, VMID=2x40k */
1580 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
1582 WM8994_VMID_SEL_MASK
,
1583 WM8994_BIAS_ENA
| 0x2);
1589 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
1590 WM8994_VMID_SEL_MASK
, 0x4);
1594 case SND_SOC_BIAS_OFF
:
1595 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_STANDBY
) {
1596 /* Switch over to startup biases */
1597 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
1599 WM8994_STARTUP_BIAS_ENA
|
1600 WM8994_VMID_BUF_ENA
|
1601 WM8994_VMID_RAMP_MASK
,
1603 WM8994_STARTUP_BIAS_ENA
|
1604 WM8994_VMID_BUF_ENA
|
1605 (1 << WM8994_VMID_RAMP_SHIFT
));
1607 /* Disable main biases */
1608 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
1610 WM8994_VMID_SEL_MASK
, 0);
1612 /* Discharge line */
1613 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
1614 WM8994_LINEOUT1_DISCH
|
1615 WM8994_LINEOUT2_DISCH
,
1616 WM8994_LINEOUT1_DISCH
|
1617 WM8994_LINEOUT2_DISCH
);
1621 /* Switch off startup biases */
1622 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
1624 WM8994_STARTUP_BIAS_ENA
|
1625 WM8994_VMID_BUF_ENA
|
1626 WM8994_VMID_RAMP_MASK
, 0);
1630 codec
->dapm
.bias_level
= level
;
1634 static int wm8994_set_dai_fmt(struct snd_soc_dai
*dai
, unsigned int fmt
)
1636 struct snd_soc_codec
*codec
= dai
->codec
;
1644 ms_reg
= WM8994_AIF1_MASTER_SLAVE
;
1645 aif1_reg
= WM8994_AIF1_CONTROL_1
;
1648 ms_reg
= WM8994_AIF2_MASTER_SLAVE
;
1649 aif1_reg
= WM8994_AIF2_CONTROL_1
;
1655 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
1656 case SND_SOC_DAIFMT_CBS_CFS
:
1658 case SND_SOC_DAIFMT_CBM_CFM
:
1659 ms
= WM8994_AIF1_MSTR
;
1665 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1666 case SND_SOC_DAIFMT_DSP_B
:
1667 aif1
|= WM8994_AIF1_LRCLK_INV
;
1668 case SND_SOC_DAIFMT_DSP_A
:
1671 case SND_SOC_DAIFMT_I2S
:
1674 case SND_SOC_DAIFMT_RIGHT_J
:
1676 case SND_SOC_DAIFMT_LEFT_J
:
1683 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1684 case SND_SOC_DAIFMT_DSP_A
:
1685 case SND_SOC_DAIFMT_DSP_B
:
1686 /* frame inversion not valid for DSP modes */
1687 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1688 case SND_SOC_DAIFMT_NB_NF
:
1690 case SND_SOC_DAIFMT_IB_NF
:
1691 aif1
|= WM8994_AIF1_BCLK_INV
;
1698 case SND_SOC_DAIFMT_I2S
:
1699 case SND_SOC_DAIFMT_RIGHT_J
:
1700 case SND_SOC_DAIFMT_LEFT_J
:
1701 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1702 case SND_SOC_DAIFMT_NB_NF
:
1704 case SND_SOC_DAIFMT_IB_IF
:
1705 aif1
|= WM8994_AIF1_BCLK_INV
| WM8994_AIF1_LRCLK_INV
;
1707 case SND_SOC_DAIFMT_IB_NF
:
1708 aif1
|= WM8994_AIF1_BCLK_INV
;
1710 case SND_SOC_DAIFMT_NB_IF
:
1711 aif1
|= WM8994_AIF1_LRCLK_INV
;
1721 snd_soc_update_bits(codec
, aif1_reg
,
1722 WM8994_AIF1_BCLK_INV
| WM8994_AIF1_LRCLK_INV
|
1723 WM8994_AIF1_FMT_MASK
,
1725 snd_soc_update_bits(codec
, ms_reg
, WM8994_AIF1_MSTR
,
1747 static int fs_ratios
[] = {
1748 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
1751 static int bclk_divs
[] = {
1752 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
1753 640, 880, 960, 1280, 1760, 1920
1756 static int wm8994_hw_params(struct snd_pcm_substream
*substream
,
1757 struct snd_pcm_hw_params
*params
,
1758 struct snd_soc_dai
*dai
)
1760 struct snd_soc_codec
*codec
= dai
->codec
;
1761 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1770 int id
= dai
->id
- 1;
1772 int i
, cur_val
, best_val
, bclk_rate
, best
;
1776 aif1_reg
= WM8994_AIF1_CONTROL_1
;
1777 bclk_reg
= WM8994_AIF1_BCLK
;
1778 rate_reg
= WM8994_AIF1_RATE
;
1779 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
||
1780 wm8994
->lrclk_shared
[0]) {
1781 lrclk_reg
= WM8994_AIF1DAC_LRCLK
;
1783 lrclk_reg
= WM8994_AIF1ADC_LRCLK
;
1784 dev_dbg(codec
->dev
, "AIF1 using split LRCLK\n");
1788 aif1_reg
= WM8994_AIF2_CONTROL_1
;
1789 bclk_reg
= WM8994_AIF2_BCLK
;
1790 rate_reg
= WM8994_AIF2_RATE
;
1791 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
||
1792 wm8994
->lrclk_shared
[1]) {
1793 lrclk_reg
= WM8994_AIF2DAC_LRCLK
;
1795 lrclk_reg
= WM8994_AIF2ADC_LRCLK
;
1796 dev_dbg(codec
->dev
, "AIF2 using split LRCLK\n");
1803 bclk_rate
= params_rate(params
) * 2;
1804 switch (params_format(params
)) {
1805 case SNDRV_PCM_FORMAT_S16_LE
:
1808 case SNDRV_PCM_FORMAT_S20_3LE
:
1812 case SNDRV_PCM_FORMAT_S24_LE
:
1816 case SNDRV_PCM_FORMAT_S32_LE
:
1824 /* Try to find an appropriate sample rate; look for an exact match. */
1825 for (i
= 0; i
< ARRAY_SIZE(srs
); i
++)
1826 if (srs
[i
].rate
== params_rate(params
))
1828 if (i
== ARRAY_SIZE(srs
))
1830 rate_val
|= srs
[i
].val
<< WM8994_AIF1_SR_SHIFT
;
1832 dev_dbg(dai
->dev
, "Sample rate is %dHz\n", srs
[i
].rate
);
1833 dev_dbg(dai
->dev
, "AIF%dCLK is %dHz, target BCLK %dHz\n",
1834 dai
->id
, wm8994
->aifclk
[id
], bclk_rate
);
1836 if (wm8994
->aifclk
[id
] == 0) {
1837 dev_err(dai
->dev
, "AIF%dCLK not configured\n", dai
->id
);
1841 /* AIFCLK/fs ratio; look for a close match in either direction */
1843 best_val
= abs((fs_ratios
[0] * params_rate(params
))
1844 - wm8994
->aifclk
[id
]);
1845 for (i
= 1; i
< ARRAY_SIZE(fs_ratios
); i
++) {
1846 cur_val
= abs((fs_ratios
[i
] * params_rate(params
))
1847 - wm8994
->aifclk
[id
]);
1848 if (cur_val
>= best_val
)
1853 dev_dbg(dai
->dev
, "Selected AIF%dCLK/fs = %d\n",
1854 dai
->id
, fs_ratios
[best
]);
1857 /* We may not get quite the right frequency if using
1858 * approximate clocks so look for the closest match that is
1859 * higher than the target (we need to ensure that there enough
1860 * BCLKs to clock out the samples).
1863 for (i
= 0; i
< ARRAY_SIZE(bclk_divs
); i
++) {
1864 cur_val
= (wm8994
->aifclk
[id
] * 10 / bclk_divs
[i
]) - bclk_rate
;
1865 if (cur_val
< 0) /* BCLK table is sorted */
1869 bclk_rate
= wm8994
->aifclk
[id
] * 10 / bclk_divs
[best
];
1870 dev_dbg(dai
->dev
, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1871 bclk_divs
[best
], bclk_rate
);
1872 bclk
|= best
<< WM8994_AIF1_BCLK_DIV_SHIFT
;
1874 lrclk
= bclk_rate
/ params_rate(params
);
1875 dev_dbg(dai
->dev
, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1876 lrclk
, bclk_rate
/ lrclk
);
1878 snd_soc_update_bits(codec
, aif1_reg
, WM8994_AIF1_WL_MASK
, aif1
);
1879 snd_soc_update_bits(codec
, bclk_reg
, WM8994_AIF1_BCLK_DIV_MASK
, bclk
);
1880 snd_soc_update_bits(codec
, lrclk_reg
, WM8994_AIF1DAC_RATE_MASK
,
1882 snd_soc_update_bits(codec
, rate_reg
, WM8994_AIF1_SR_MASK
|
1883 WM8994_AIF1CLK_RATE_MASK
, rate_val
);
1885 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
1888 wm8994
->dac_rates
[0] = params_rate(params
);
1889 wm8994_set_retune_mobile(codec
, 0);
1890 wm8994_set_retune_mobile(codec
, 1);
1893 wm8994
->dac_rates
[1] = params_rate(params
);
1894 wm8994_set_retune_mobile(codec
, 2);
1902 static int wm8994_aif_mute(struct snd_soc_dai
*codec_dai
, int mute
)
1904 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1908 switch (codec_dai
->id
) {
1910 mute_reg
= WM8994_AIF1_DAC1_FILTERS_1
;
1913 mute_reg
= WM8994_AIF2_DAC_FILTERS_1
;
1920 reg
= WM8994_AIF1DAC1_MUTE
;
1924 snd_soc_update_bits(codec
, mute_reg
, WM8994_AIF1DAC1_MUTE
, reg
);
1929 static int wm8994_set_tristate(struct snd_soc_dai
*codec_dai
, int tristate
)
1931 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1934 switch (codec_dai
->id
) {
1936 reg
= WM8994_AIF1_MASTER_SLAVE
;
1937 mask
= WM8994_AIF1_TRI
;
1940 reg
= WM8994_AIF2_MASTER_SLAVE
;
1941 mask
= WM8994_AIF2_TRI
;
1944 reg
= WM8994_POWER_MANAGEMENT_6
;
1945 mask
= WM8994_AIF3_TRI
;
1956 return snd_soc_update_bits(codec
, reg
, mask
, reg
);
1959 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
1961 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1962 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1964 static struct snd_soc_dai_ops wm8994_aif1_dai_ops
= {
1965 .set_sysclk
= wm8994_set_dai_sysclk
,
1966 .set_fmt
= wm8994_set_dai_fmt
,
1967 .hw_params
= wm8994_hw_params
,
1968 .digital_mute
= wm8994_aif_mute
,
1969 .set_pll
= wm8994_set_fll
,
1970 .set_tristate
= wm8994_set_tristate
,
1973 static struct snd_soc_dai_ops wm8994_aif2_dai_ops
= {
1974 .set_sysclk
= wm8994_set_dai_sysclk
,
1975 .set_fmt
= wm8994_set_dai_fmt
,
1976 .hw_params
= wm8994_hw_params
,
1977 .digital_mute
= wm8994_aif_mute
,
1978 .set_pll
= wm8994_set_fll
,
1979 .set_tristate
= wm8994_set_tristate
,
1982 static struct snd_soc_dai_ops wm8994_aif3_dai_ops
= {
1983 .set_tristate
= wm8994_set_tristate
,
1986 static struct snd_soc_dai_driver wm8994_dai
[] = {
1988 .name
= "wm8994-aif1",
1991 .stream_name
= "AIF1 Playback",
1994 .rates
= WM8994_RATES
,
1995 .formats
= WM8994_FORMATS
,
1998 .stream_name
= "AIF1 Capture",
2001 .rates
= WM8994_RATES
,
2002 .formats
= WM8994_FORMATS
,
2004 .ops
= &wm8994_aif1_dai_ops
,
2007 .name
= "wm8994-aif2",
2010 .stream_name
= "AIF2 Playback",
2013 .rates
= WM8994_RATES
,
2014 .formats
= WM8994_FORMATS
,
2017 .stream_name
= "AIF2 Capture",
2020 .rates
= WM8994_RATES
,
2021 .formats
= WM8994_FORMATS
,
2023 .ops
= &wm8994_aif2_dai_ops
,
2026 .name
= "wm8994-aif3",
2029 .stream_name
= "AIF3 Playback",
2032 .rates
= WM8994_RATES
,
2033 .formats
= WM8994_FORMATS
,
2036 .stream_name
= "AIF3 Capture",
2039 .rates
= WM8994_RATES
,
2040 .formats
= WM8994_FORMATS
,
2042 .ops
= &wm8994_aif3_dai_ops
,
2047 static int wm8994_suspend(struct snd_soc_codec
*codec
, pm_message_t state
)
2049 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2052 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll
); i
++) {
2053 memcpy(&wm8994
->fll_suspend
[i
], &wm8994
->fll
[i
],
2054 sizeof(struct fll_config
));
2055 ret
= _wm8994_set_fll(codec
, i
+ 1, 0, 0, 0);
2057 dev_warn(codec
->dev
, "Failed to stop FLL%d: %d\n",
2061 wm8994_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
2066 static int wm8994_resume(struct snd_soc_codec
*codec
)
2068 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2069 u16
*reg_cache
= codec
->reg_cache
;
2072 /* Restore the registers */
2073 for (i
= 1; i
< ARRAY_SIZE(wm8994
->reg_cache
); i
++) {
2077 case WM8994_SOFTWARE_RESET
:
2078 /* Handled by other MFD drivers */
2084 if (!wm8994_access_masks
[i
].writable
)
2087 wm8994_reg_write(codec
->control_data
, i
, reg_cache
[i
]);
2090 wm8994_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
2092 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll
); i
++) {
2093 if (!wm8994
->fll_suspend
[i
].out
)
2096 ret
= _wm8994_set_fll(codec
, i
+ 1,
2097 wm8994
->fll_suspend
[i
].src
,
2098 wm8994
->fll_suspend
[i
].in
,
2099 wm8994
->fll_suspend
[i
].out
);
2101 dev_warn(codec
->dev
, "Failed to restore FLL%d: %d\n",
2108 #define wm8994_suspend NULL
2109 #define wm8994_resume NULL
2112 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv
*wm8994
)
2114 struct snd_soc_codec
*codec
= wm8994
->codec
;
2115 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
2116 struct snd_kcontrol_new controls
[] = {
2117 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2118 wm8994
->retune_mobile_enum
,
2119 wm8994_get_retune_mobile_enum
,
2120 wm8994_put_retune_mobile_enum
),
2121 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2122 wm8994
->retune_mobile_enum
,
2123 wm8994_get_retune_mobile_enum
,
2124 wm8994_put_retune_mobile_enum
),
2125 SOC_ENUM_EXT("AIF2 EQ Mode",
2126 wm8994
->retune_mobile_enum
,
2127 wm8994_get_retune_mobile_enum
,
2128 wm8994_put_retune_mobile_enum
),
2133 /* We need an array of texts for the enum API but the number
2134 * of texts is likely to be less than the number of
2135 * configurations due to the sample rate dependency of the
2136 * configurations. */
2137 wm8994
->num_retune_mobile_texts
= 0;
2138 wm8994
->retune_mobile_texts
= NULL
;
2139 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
2140 for (j
= 0; j
< wm8994
->num_retune_mobile_texts
; j
++) {
2141 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
2142 wm8994
->retune_mobile_texts
[j
]) == 0)
2146 if (j
!= wm8994
->num_retune_mobile_texts
)
2149 /* Expand the array... */
2150 t
= krealloc(wm8994
->retune_mobile_texts
,
2152 (wm8994
->num_retune_mobile_texts
+ 1),
2157 /* ...store the new entry... */
2158 t
[wm8994
->num_retune_mobile_texts
] =
2159 pdata
->retune_mobile_cfgs
[i
].name
;
2161 /* ...and remember the new version. */
2162 wm8994
->num_retune_mobile_texts
++;
2163 wm8994
->retune_mobile_texts
= t
;
2166 dev_dbg(codec
->dev
, "Allocated %d unique ReTune Mobile names\n",
2167 wm8994
->num_retune_mobile_texts
);
2169 wm8994
->retune_mobile_enum
.max
= wm8994
->num_retune_mobile_texts
;
2170 wm8994
->retune_mobile_enum
.texts
= wm8994
->retune_mobile_texts
;
2172 ret
= snd_soc_add_controls(wm8994
->codec
, controls
,
2173 ARRAY_SIZE(controls
));
2175 dev_err(wm8994
->codec
->dev
,
2176 "Failed to add ReTune Mobile controls: %d\n", ret
);
2179 static void wm8994_handle_pdata(struct wm8994_priv
*wm8994
)
2181 struct snd_soc_codec
*codec
= wm8994
->codec
;
2182 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
2188 wm_hubs_handle_analogue_pdata(codec
, pdata
->lineout1_diff
,
2189 pdata
->lineout2_diff
,
2194 pdata
->micbias1_lvl
,
2195 pdata
->micbias2_lvl
);
2197 dev_dbg(codec
->dev
, "%d DRC configurations\n", pdata
->num_drc_cfgs
);
2199 if (pdata
->num_drc_cfgs
) {
2200 struct snd_kcontrol_new controls
[] = {
2201 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994
->drc_enum
,
2202 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
2203 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994
->drc_enum
,
2204 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
2205 SOC_ENUM_EXT("AIF2DRC Mode", wm8994
->drc_enum
,
2206 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
2209 /* We need an array of texts for the enum API */
2210 wm8994
->drc_texts
= kmalloc(sizeof(char *)
2211 * pdata
->num_drc_cfgs
, GFP_KERNEL
);
2212 if (!wm8994
->drc_texts
) {
2213 dev_err(wm8994
->codec
->dev
,
2214 "Failed to allocate %d DRC config texts\n",
2215 pdata
->num_drc_cfgs
);
2219 for (i
= 0; i
< pdata
->num_drc_cfgs
; i
++)
2220 wm8994
->drc_texts
[i
] = pdata
->drc_cfgs
[i
].name
;
2222 wm8994
->drc_enum
.max
= pdata
->num_drc_cfgs
;
2223 wm8994
->drc_enum
.texts
= wm8994
->drc_texts
;
2225 ret
= snd_soc_add_controls(wm8994
->codec
, controls
,
2226 ARRAY_SIZE(controls
));
2228 dev_err(wm8994
->codec
->dev
,
2229 "Failed to add DRC mode controls: %d\n", ret
);
2231 for (i
= 0; i
< WM8994_NUM_DRC
; i
++)
2232 wm8994_set_drc(codec
, i
);
2235 dev_dbg(codec
->dev
, "%d ReTune Mobile configurations\n",
2236 pdata
->num_retune_mobile_cfgs
);
2238 if (pdata
->num_retune_mobile_cfgs
)
2239 wm8994_handle_retune_mobile_pdata(wm8994
);
2241 snd_soc_add_controls(wm8994
->codec
, wm8994_eq_controls
,
2242 ARRAY_SIZE(wm8994_eq_controls
));
2246 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2248 * @codec: WM8994 codec
2249 * @jack: jack to report detection events on
2250 * @micbias: microphone bias to detect on
2251 * @det: value to report for presence detection
2252 * @shrt: value to report for short detection
2254 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
2255 * being used to bring out signals to the processor then only platform
2256 * data configuration is needed for WM8994 and processor GPIOs should
2257 * be configured using snd_soc_jack_add_gpios() instead.
2259 * Configuration of detection levels is available via the micbias1_lvl
2260 * and micbias2_lvl platform data members.
2262 int wm8994_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
2263 int micbias
, int det
, int shrt
)
2265 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2266 struct wm8994_micdet
*micdet
;
2271 micdet
= &wm8994
->micdet
[0];
2274 micdet
= &wm8994
->micdet
[1];
2280 dev_dbg(codec
->dev
, "Configuring microphone detection on %d: %x %x\n",
2281 micbias
, det
, shrt
);
2283 /* Store the configuration */
2284 micdet
->jack
= jack
;
2286 micdet
->shrt
= shrt
;
2288 /* If either of the jacks is set up then enable detection */
2289 if (wm8994
->micdet
[0].jack
|| wm8994
->micdet
[1].jack
)
2290 reg
= WM8994_MICD_ENA
;
2294 snd_soc_update_bits(codec
, WM8994_MICBIAS
, WM8994_MICD_ENA
, reg
);
2298 EXPORT_SYMBOL_GPL(wm8994_mic_detect
);
2300 static irqreturn_t
wm8994_mic_irq(int irq
, void *data
)
2302 struct wm8994_priv
*priv
= data
;
2303 struct snd_soc_codec
*codec
= priv
->codec
;
2307 reg
= snd_soc_read(codec
, WM8994_INTERRUPT_RAW_STATUS_2
);
2309 dev_err(codec
->dev
, "Failed to read microphone status: %d\n",
2314 dev_dbg(codec
->dev
, "Microphone status: %x\n", reg
);
2317 if (reg
& WM8994_MIC1_DET_STS
)
2318 report
|= priv
->micdet
[0].det
;
2319 if (reg
& WM8994_MIC1_SHRT_STS
)
2320 report
|= priv
->micdet
[0].shrt
;
2321 snd_soc_jack_report(priv
->micdet
[0].jack
, report
,
2322 priv
->micdet
[0].det
| priv
->micdet
[0].shrt
);
2325 if (reg
& WM8994_MIC2_DET_STS
)
2326 report
|= priv
->micdet
[1].det
;
2327 if (reg
& WM8994_MIC2_SHRT_STS
)
2328 report
|= priv
->micdet
[1].shrt
;
2329 snd_soc_jack_report(priv
->micdet
[1].jack
, report
,
2330 priv
->micdet
[1].det
| priv
->micdet
[1].shrt
);
2335 static int wm8994_codec_probe(struct snd_soc_codec
*codec
)
2337 struct wm8994_priv
*wm8994
;
2338 struct snd_soc_dapm_context
*dapm
= &codec
->dapm
;
2341 codec
->control_data
= dev_get_drvdata(codec
->dev
->parent
);
2343 wm8994
= kzalloc(sizeof(struct wm8994_priv
), GFP_KERNEL
);
2346 snd_soc_codec_set_drvdata(codec
, wm8994
);
2348 codec
->reg_cache
= &wm8994
->reg_cache
;
2350 wm8994
->pdata
= dev_get_platdata(codec
->dev
->parent
);
2351 wm8994
->codec
= codec
;
2353 /* Fill the cache with physical values we inherited; don't reset */
2354 ret
= wm8994_bulk_read(codec
->control_data
, 0,
2355 ARRAY_SIZE(wm8994
->reg_cache
) - 1,
2358 dev_err(codec
->dev
, "Failed to fill register cache: %d\n",
2363 /* Clear the cached values for unreadable/volatile registers to
2364 * avoid potential confusion.
2366 for (i
= 0; i
< ARRAY_SIZE(wm8994
->reg_cache
); i
++)
2367 if (wm8994_volatile(i
) || !wm8994_readable(i
))
2368 wm8994
->reg_cache
[i
] = 0;
2370 /* Set revision-specific configuration */
2371 wm8994
->revision
= snd_soc_read(codec
, WM8994_CHIP_REVISION
);
2372 switch (wm8994
->revision
) {
2375 wm8994
->hubs
.dcs_codes
= -5;
2376 wm8994
->hubs
.hp_startup_mode
= 1;
2377 wm8994
->hubs
.dcs_readback_mode
= 1;
2380 wm8994
->hubs
.dcs_readback_mode
= 1;
2384 ret
= wm8994_request_irq(codec
->control_data
, WM8994_IRQ_MIC1_DET
,
2385 wm8994_mic_irq
, "Mic 1 detect", wm8994
);
2387 dev_warn(codec
->dev
,
2388 "Failed to request Mic1 detect IRQ: %d\n", ret
);
2390 ret
= wm8994_request_irq(codec
->control_data
, WM8994_IRQ_MIC1_SHRT
,
2391 wm8994_mic_irq
, "Mic 1 short", wm8994
);
2393 dev_warn(codec
->dev
,
2394 "Failed to request Mic1 short IRQ: %d\n", ret
);
2396 ret
= wm8994_request_irq(codec
->control_data
, WM8994_IRQ_MIC2_DET
,
2397 wm8994_mic_irq
, "Mic 2 detect", wm8994
);
2399 dev_warn(codec
->dev
,
2400 "Failed to request Mic2 detect IRQ: %d\n", ret
);
2402 ret
= wm8994_request_irq(codec
->control_data
, WM8994_IRQ_MIC2_SHRT
,
2403 wm8994_mic_irq
, "Mic 2 short", wm8994
);
2405 dev_warn(codec
->dev
,
2406 "Failed to request Mic2 short IRQ: %d\n", ret
);
2408 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
2409 * configured on init - if a system wants to do this dynamically
2410 * at runtime we can deal with that then.
2412 ret
= wm8994_reg_read(codec
->control_data
, WM8994_GPIO_1
);
2414 dev_err(codec
->dev
, "Failed to read GPIO1 state: %d\n", ret
);
2417 if ((ret
& WM8994_GPN_FN_MASK
) != WM8994_GP_FN_PIN_SPECIFIC
) {
2418 wm8994
->lrclk_shared
[0] = 1;
2419 wm8994_dai
[0].symmetric_rates
= 1;
2421 wm8994
->lrclk_shared
[0] = 0;
2424 ret
= wm8994_reg_read(codec
->control_data
, WM8994_GPIO_6
);
2426 dev_err(codec
->dev
, "Failed to read GPIO6 state: %d\n", ret
);
2429 if ((ret
& WM8994_GPN_FN_MASK
) != WM8994_GP_FN_PIN_SPECIFIC
) {
2430 wm8994
->lrclk_shared
[1] = 1;
2431 wm8994_dai
[1].symmetric_rates
= 1;
2433 wm8994
->lrclk_shared
[1] = 0;
2436 wm8994_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
2438 /* Latch volume updates (right only; we always do left then right). */
2439 snd_soc_update_bits(codec
, WM8994_AIF1_DAC1_RIGHT_VOLUME
,
2440 WM8994_AIF1DAC1_VU
, WM8994_AIF1DAC1_VU
);
2441 snd_soc_update_bits(codec
, WM8994_AIF1_DAC2_RIGHT_VOLUME
,
2442 WM8994_AIF1DAC2_VU
, WM8994_AIF1DAC2_VU
);
2443 snd_soc_update_bits(codec
, WM8994_AIF2_DAC_RIGHT_VOLUME
,
2444 WM8994_AIF2DAC_VU
, WM8994_AIF2DAC_VU
);
2445 snd_soc_update_bits(codec
, WM8994_AIF1_ADC1_RIGHT_VOLUME
,
2446 WM8994_AIF1ADC1_VU
, WM8994_AIF1ADC1_VU
);
2447 snd_soc_update_bits(codec
, WM8994_AIF1_ADC2_RIGHT_VOLUME
,
2448 WM8994_AIF1ADC2_VU
, WM8994_AIF1ADC2_VU
);
2449 snd_soc_update_bits(codec
, WM8994_AIF2_ADC_RIGHT_VOLUME
,
2450 WM8994_AIF2ADC_VU
, WM8994_AIF1ADC2_VU
);
2451 snd_soc_update_bits(codec
, WM8994_DAC1_RIGHT_VOLUME
,
2452 WM8994_DAC1_VU
, WM8994_DAC1_VU
);
2453 snd_soc_update_bits(codec
, WM8994_DAC2_RIGHT_VOLUME
,
2454 WM8994_DAC2_VU
, WM8994_DAC2_VU
);
2456 /* Set the low bit of the 3D stereo depth so TLV matches */
2457 snd_soc_update_bits(codec
, WM8994_AIF1_DAC1_FILTERS_2
,
2458 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT
,
2459 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT
);
2460 snd_soc_update_bits(codec
, WM8994_AIF1_DAC2_FILTERS_2
,
2461 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT
,
2462 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT
);
2463 snd_soc_update_bits(codec
, WM8994_AIF2_DAC_FILTERS_2
,
2464 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT
,
2465 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT
);
2467 /* Unconditionally enable AIF1 ADC TDM mode; it only affects
2468 * behaviour on idle TDM clock cycles. */
2469 snd_soc_update_bits(codec
, WM8994_AIF1_CONTROL_1
,
2470 WM8994_AIF1ADC_TDM
, WM8994_AIF1ADC_TDM
);
2472 wm8994_update_class_w(codec
);
2474 wm8994_handle_pdata(wm8994
);
2476 wm_hubs_add_analogue_controls(codec
);
2477 snd_soc_add_controls(codec
, wm8994_snd_controls
,
2478 ARRAY_SIZE(wm8994_snd_controls
));
2479 snd_soc_dapm_new_controls(dapm
, wm8994_dapm_widgets
,
2480 ARRAY_SIZE(wm8994_dapm_widgets
));
2481 wm_hubs_add_analogue_routes(codec
, 0, 0);
2482 snd_soc_dapm_add_routes(dapm
, intercon
, ARRAY_SIZE(intercon
));
2487 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC2_SHRT
, wm8994
);
2488 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC2_DET
, wm8994
);
2489 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC1_SHRT
, wm8994
);
2490 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC1_DET
, wm8994
);
2496 static int wm8994_codec_remove(struct snd_soc_codec
*codec
)
2498 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2500 wm8994_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
2502 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC2_SHRT
, wm8994
);
2503 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC2_DET
, wm8994
);
2504 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC1_SHRT
, wm8994
);
2505 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC1_DET
, wm8994
);
2506 kfree(wm8994
->retune_mobile_texts
);
2507 kfree(wm8994
->drc_texts
);
2513 static struct snd_soc_codec_driver soc_codec_dev_wm8994
= {
2514 .probe
= wm8994_codec_probe
,
2515 .remove
= wm8994_codec_remove
,
2516 .suspend
= wm8994_suspend
,
2517 .resume
= wm8994_resume
,
2518 .read
= wm8994_read
,
2519 .write
= wm8994_write
,
2520 .readable_register
= wm8994_readable
,
2521 .volatile_register
= wm8994_volatile
,
2522 .set_bias_level
= wm8994_set_bias_level
,
2525 static int __devinit
wm8994_probe(struct platform_device
*pdev
)
2527 return snd_soc_register_codec(&pdev
->dev
, &soc_codec_dev_wm8994
,
2528 wm8994_dai
, ARRAY_SIZE(wm8994_dai
));
2531 static int __devexit
wm8994_remove(struct platform_device
*pdev
)
2533 snd_soc_unregister_codec(&pdev
->dev
);
2537 static struct platform_driver wm8994_codec_driver
= {
2539 .name
= "wm8994-codec",
2540 .owner
= THIS_MODULE
,
2542 .probe
= wm8994_probe
,
2543 .remove
= __devexit_p(wm8994_remove
),
2546 static __init
int wm8994_init(void)
2548 return platform_driver_register(&wm8994_codec_driver
);
2550 module_init(wm8994_init
);
2552 static __exit
void wm8994_exit(void)
2554 platform_driver_unregister(&wm8994_codec_driver
);
2556 module_exit(wm8994_exit
);
2559 MODULE_DESCRIPTION("ASoC WM8994 driver");
2560 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2561 MODULE_LICENSE("GPL");
2562 MODULE_ALIAS("platform:wm8994-codec");