2 * wm8994.c -- WM8994 ALSA SoC Audio driver
4 * Copyright 2009-12 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/jack.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <trace/events/asoc.h>
33 #include <linux/mfd/wm8994/core.h>
34 #include <linux/mfd/wm8994/registers.h>
35 #include <linux/mfd/wm8994/pdata.h>
36 #include <linux/mfd/wm8994/gpio.h>
41 #define WM1811_JACKDET_MODE_NONE 0x0000
42 #define WM1811_JACKDET_MODE_JACK 0x0100
43 #define WM1811_JACKDET_MODE_MIC 0x0080
44 #define WM1811_JACKDET_MODE_AUDIO 0x0180
46 #define WM8994_NUM_DRC 3
47 #define WM8994_NUM_EQ 3
52 } wm8994_vu_bits
[] = {
53 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME
, WM8994_IN1_VU
},
54 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME
, WM8994_IN1_VU
},
55 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME
, WM8994_IN2_VU
},
56 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME
, WM8994_IN2_VU
},
57 { WM8994_SPEAKER_VOLUME_LEFT
, WM8994_SPKOUT_VU
},
58 { WM8994_SPEAKER_VOLUME_RIGHT
, WM8994_SPKOUT_VU
},
59 { WM8994_LEFT_OUTPUT_VOLUME
, WM8994_HPOUT1_VU
},
60 { WM8994_RIGHT_OUTPUT_VOLUME
, WM8994_HPOUT1_VU
},
61 { WM8994_LEFT_OPGA_VOLUME
, WM8994_MIXOUT_VU
},
62 { WM8994_RIGHT_OPGA_VOLUME
, WM8994_MIXOUT_VU
},
64 { WM8994_AIF1_DAC1_LEFT_VOLUME
, WM8994_AIF1DAC1_VU
},
65 { WM8994_AIF1_DAC1_RIGHT_VOLUME
, WM8994_AIF1DAC1_VU
},
66 { WM8994_AIF1_DAC2_LEFT_VOLUME
, WM8994_AIF1DAC2_VU
},
67 { WM8994_AIF1_DAC2_RIGHT_VOLUME
, WM8994_AIF1DAC2_VU
},
68 { WM8994_AIF2_DAC_LEFT_VOLUME
, WM8994_AIF2DAC_VU
},
69 { WM8994_AIF2_DAC_RIGHT_VOLUME
, WM8994_AIF2DAC_VU
},
70 { WM8994_AIF1_ADC1_LEFT_VOLUME
, WM8994_AIF1ADC1_VU
},
71 { WM8994_AIF1_ADC1_RIGHT_VOLUME
, WM8994_AIF1ADC1_VU
},
72 { WM8994_AIF1_ADC2_LEFT_VOLUME
, WM8994_AIF1ADC2_VU
},
73 { WM8994_AIF1_ADC2_RIGHT_VOLUME
, WM8994_AIF1ADC2_VU
},
74 { WM8994_AIF2_ADC_LEFT_VOLUME
, WM8994_AIF2ADC_VU
},
75 { WM8994_AIF2_ADC_RIGHT_VOLUME
, WM8994_AIF1ADC2_VU
},
76 { WM8994_DAC1_LEFT_VOLUME
, WM8994_DAC1_VU
},
77 { WM8994_DAC1_RIGHT_VOLUME
, WM8994_DAC1_VU
},
78 { WM8994_DAC2_LEFT_VOLUME
, WM8994_DAC2_VU
},
79 { WM8994_DAC2_RIGHT_VOLUME
, WM8994_DAC2_VU
},
82 static int wm8994_drc_base
[] = {
88 static int wm8994_retune_mobile_base
[] = {
89 WM8994_AIF1_DAC1_EQ_GAINS_1
,
90 WM8994_AIF1_DAC2_EQ_GAINS_1
,
91 WM8994_AIF2_EQ_GAINS_1
,
94 static const struct wm8958_micd_rate micdet_rates
[] = {
95 { 32768, true, 1, 4 },
96 { 32768, false, 1, 1 },
97 { 44100 * 256, true, 7, 10 },
98 { 44100 * 256, false, 7, 10 },
101 static const struct wm8958_micd_rate jackdet_rates
[] = {
102 { 32768, true, 0, 1 },
103 { 32768, false, 0, 1 },
104 { 44100 * 256, true, 10, 10 },
105 { 44100 * 256, false, 7, 8 },
108 static void wm8958_micd_set_rate(struct snd_soc_codec
*codec
)
110 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
111 struct wm8994
*control
= wm8994
->wm8994
;
112 int best
, i
, sysclk
, val
;
114 const struct wm8958_micd_rate
*rates
;
117 idle
= !wm8994
->jack_mic
;
119 sysclk
= snd_soc_read(codec
, WM8994_CLOCKING_1
);
120 if (sysclk
& WM8994_SYSCLK_SRC
)
121 sysclk
= wm8994
->aifclk
[1];
123 sysclk
= wm8994
->aifclk
[0];
125 if (control
->pdata
.micd_rates
) {
126 rates
= control
->pdata
.micd_rates
;
127 num_rates
= control
->pdata
.num_micd_rates
;
128 } else if (wm8994
->jackdet
) {
129 rates
= jackdet_rates
;
130 num_rates
= ARRAY_SIZE(jackdet_rates
);
132 rates
= micdet_rates
;
133 num_rates
= ARRAY_SIZE(micdet_rates
);
137 for (i
= 0; i
< num_rates
; i
++) {
138 if (rates
[i
].idle
!= idle
)
140 if (abs(rates
[i
].sysclk
- sysclk
) <
141 abs(rates
[best
].sysclk
- sysclk
))
143 else if (rates
[best
].idle
!= idle
)
147 val
= rates
[best
].start
<< WM8958_MICD_BIAS_STARTTIME_SHIFT
148 | rates
[best
].rate
<< WM8958_MICD_RATE_SHIFT
;
150 dev_dbg(codec
->dev
, "MICD rate %d,%d for %dHz %s\n",
151 rates
[best
].start
, rates
[best
].rate
, sysclk
,
152 idle
? "idle" : "active");
154 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
155 WM8958_MICD_BIAS_STARTTIME_MASK
|
156 WM8958_MICD_RATE_MASK
, val
);
159 static int configure_aif_clock(struct snd_soc_codec
*codec
, int aif
)
161 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
171 switch (wm8994
->sysclk
[aif
]) {
172 case WM8994_SYSCLK_MCLK1
:
173 rate
= wm8994
->mclk
[0];
176 case WM8994_SYSCLK_MCLK2
:
178 rate
= wm8994
->mclk
[1];
181 case WM8994_SYSCLK_FLL1
:
183 rate
= wm8994
->fll
[0].out
;
186 case WM8994_SYSCLK_FLL2
:
188 rate
= wm8994
->fll
[1].out
;
195 if (rate
>= 13500000) {
197 reg1
|= WM8994_AIF1CLK_DIV
;
199 dev_dbg(codec
->dev
, "Dividing AIF%d clock to %dHz\n",
203 wm8994
->aifclk
[aif
] = rate
;
205 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
+ offset
,
206 WM8994_AIF1CLK_SRC_MASK
| WM8994_AIF1CLK_DIV
,
212 static int configure_clock(struct snd_soc_codec
*codec
)
214 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
217 /* Bring up the AIF clocks first */
218 configure_aif_clock(codec
, 0);
219 configure_aif_clock(codec
, 1);
221 /* Then switch CLK_SYS over to the higher of them; a change
222 * can only happen as a result of a clocking change which can
223 * only be made outside of DAPM so we can safely redo the
227 /* If they're equal it doesn't matter which is used */
228 if (wm8994
->aifclk
[0] == wm8994
->aifclk
[1]) {
229 wm8958_micd_set_rate(codec
);
233 if (wm8994
->aifclk
[0] < wm8994
->aifclk
[1])
234 new = WM8994_SYSCLK_SRC
;
238 change
= snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
239 WM8994_SYSCLK_SRC
, new);
241 snd_soc_dapm_sync(&codec
->dapm
);
243 wm8958_micd_set_rate(codec
);
248 static int check_clk_sys(struct snd_soc_dapm_widget
*source
,
249 struct snd_soc_dapm_widget
*sink
)
251 int reg
= snd_soc_read(source
->codec
, WM8994_CLOCKING_1
);
254 /* Check what we're currently using for CLK_SYS */
255 if (reg
& WM8994_SYSCLK_SRC
)
260 return strcmp(source
->name
, clk
) == 0;
263 static const char *sidetone_hpf_text
[] = {
264 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
267 static const struct soc_enum sidetone_hpf
=
268 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 7, 7, sidetone_hpf_text
);
270 static const char *adc_hpf_text
[] = {
271 "HiFi", "Voice 1", "Voice 2", "Voice 3"
274 static const struct soc_enum aif1adc1_hpf
=
275 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS
, 13, 4, adc_hpf_text
);
277 static const struct soc_enum aif1adc2_hpf
=
278 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS
, 13, 4, adc_hpf_text
);
280 static const struct soc_enum aif2adc_hpf
=
281 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS
, 13, 4, adc_hpf_text
);
283 static const DECLARE_TLV_DB_SCALE(aif_tlv
, 0, 600, 0);
284 static const DECLARE_TLV_DB_SCALE(digital_tlv
, -7200, 75, 1);
285 static const DECLARE_TLV_DB_SCALE(st_tlv
, -3600, 300, 0);
286 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv
, -1600, 183, 0);
287 static const DECLARE_TLV_DB_SCALE(eq_tlv
, -1200, 100, 0);
288 static const DECLARE_TLV_DB_SCALE(ng_tlv
, -10200, 600, 0);
289 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv
, 0, 900, 0);
291 #define WM8994_DRC_SWITCH(xname, reg, shift) \
292 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
293 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
294 .put = wm8994_put_drc_sw, \
295 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
297 static int wm8994_put_drc_sw(struct snd_kcontrol
*kcontrol
,
298 struct snd_ctl_elem_value
*ucontrol
)
300 struct soc_mixer_control
*mc
=
301 (struct soc_mixer_control
*)kcontrol
->private_value
;
302 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
305 /* Can't enable both ADC and DAC paths simultaneously */
306 if (mc
->shift
== WM8994_AIF1DAC1_DRC_ENA_SHIFT
)
307 mask
= WM8994_AIF1ADC1L_DRC_ENA_MASK
|
308 WM8994_AIF1ADC1R_DRC_ENA_MASK
;
310 mask
= WM8994_AIF1DAC1_DRC_ENA_MASK
;
312 ret
= snd_soc_read(codec
, mc
->reg
);
318 return snd_soc_put_volsw(kcontrol
, ucontrol
);
321 static void wm8994_set_drc(struct snd_soc_codec
*codec
, int drc
)
323 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
324 struct wm8994
*control
= wm8994
->wm8994
;
325 struct wm8994_pdata
*pdata
= &control
->pdata
;
326 int base
= wm8994_drc_base
[drc
];
327 int cfg
= wm8994
->drc_cfg
[drc
];
330 /* Save any enables; the configuration should clear them. */
331 save
= snd_soc_read(codec
, base
);
332 save
&= WM8994_AIF1DAC1_DRC_ENA
| WM8994_AIF1ADC1L_DRC_ENA
|
333 WM8994_AIF1ADC1R_DRC_ENA
;
335 for (i
= 0; i
< WM8994_DRC_REGS
; i
++)
336 snd_soc_update_bits(codec
, base
+ i
, 0xffff,
337 pdata
->drc_cfgs
[cfg
].regs
[i
]);
339 snd_soc_update_bits(codec
, base
, WM8994_AIF1DAC1_DRC_ENA
|
340 WM8994_AIF1ADC1L_DRC_ENA
|
341 WM8994_AIF1ADC1R_DRC_ENA
, save
);
344 /* Icky as hell but saves code duplication */
345 static int wm8994_get_drc(const char *name
)
347 if (strcmp(name
, "AIF1DRC1 Mode") == 0)
349 if (strcmp(name
, "AIF1DRC2 Mode") == 0)
351 if (strcmp(name
, "AIF2DRC Mode") == 0)
356 static int wm8994_put_drc_enum(struct snd_kcontrol
*kcontrol
,
357 struct snd_ctl_elem_value
*ucontrol
)
359 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
360 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
361 struct wm8994
*control
= wm8994
->wm8994
;
362 struct wm8994_pdata
*pdata
= &control
->pdata
;
363 int drc
= wm8994_get_drc(kcontrol
->id
.name
);
364 int value
= ucontrol
->value
.integer
.value
[0];
369 if (value
>= pdata
->num_drc_cfgs
)
372 wm8994
->drc_cfg
[drc
] = value
;
374 wm8994_set_drc(codec
, drc
);
379 static int wm8994_get_drc_enum(struct snd_kcontrol
*kcontrol
,
380 struct snd_ctl_elem_value
*ucontrol
)
382 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
383 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
384 int drc
= wm8994_get_drc(kcontrol
->id
.name
);
386 ucontrol
->value
.enumerated
.item
[0] = wm8994
->drc_cfg
[drc
];
391 static void wm8994_set_retune_mobile(struct snd_soc_codec
*codec
, int block
)
393 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
394 struct wm8994
*control
= wm8994
->wm8994
;
395 struct wm8994_pdata
*pdata
= &control
->pdata
;
396 int base
= wm8994_retune_mobile_base
[block
];
397 int iface
, best
, best_val
, save
, i
, cfg
;
399 if (!pdata
|| !wm8994
->num_retune_mobile_texts
)
414 /* Find the version of the currently selected configuration
415 * with the nearest sample rate. */
416 cfg
= wm8994
->retune_mobile_cfg
[block
];
419 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
420 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
421 wm8994
->retune_mobile_texts
[cfg
]) == 0 &&
422 abs(pdata
->retune_mobile_cfgs
[i
].rate
423 - wm8994
->dac_rates
[iface
]) < best_val
) {
425 best_val
= abs(pdata
->retune_mobile_cfgs
[i
].rate
426 - wm8994
->dac_rates
[iface
]);
430 dev_dbg(codec
->dev
, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
432 pdata
->retune_mobile_cfgs
[best
].name
,
433 pdata
->retune_mobile_cfgs
[best
].rate
,
434 wm8994
->dac_rates
[iface
]);
436 /* The EQ will be disabled while reconfiguring it, remember the
437 * current configuration.
439 save
= snd_soc_read(codec
, base
);
440 save
&= WM8994_AIF1DAC1_EQ_ENA
;
442 for (i
= 0; i
< WM8994_EQ_REGS
; i
++)
443 snd_soc_update_bits(codec
, base
+ i
, 0xffff,
444 pdata
->retune_mobile_cfgs
[best
].regs
[i
]);
446 snd_soc_update_bits(codec
, base
, WM8994_AIF1DAC1_EQ_ENA
, save
);
449 /* Icky as hell but saves code duplication */
450 static int wm8994_get_retune_mobile_block(const char *name
)
452 if (strcmp(name
, "AIF1.1 EQ Mode") == 0)
454 if (strcmp(name
, "AIF1.2 EQ Mode") == 0)
456 if (strcmp(name
, "AIF2 EQ Mode") == 0)
461 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
462 struct snd_ctl_elem_value
*ucontrol
)
464 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
465 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
466 struct wm8994
*control
= wm8994
->wm8994
;
467 struct wm8994_pdata
*pdata
= &control
->pdata
;
468 int block
= wm8994_get_retune_mobile_block(kcontrol
->id
.name
);
469 int value
= ucontrol
->value
.integer
.value
[0];
474 if (value
>= pdata
->num_retune_mobile_cfgs
)
477 wm8994
->retune_mobile_cfg
[block
] = value
;
479 wm8994_set_retune_mobile(codec
, block
);
484 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
485 struct snd_ctl_elem_value
*ucontrol
)
487 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
488 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
489 int block
= wm8994_get_retune_mobile_block(kcontrol
->id
.name
);
491 ucontrol
->value
.enumerated
.item
[0] = wm8994
->retune_mobile_cfg
[block
];
496 static const char *aif_chan_src_text
[] = {
500 static const struct soc_enum aif1adcl_src
=
501 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1
, 15, 2, aif_chan_src_text
);
503 static const struct soc_enum aif1adcr_src
=
504 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1
, 14, 2, aif_chan_src_text
);
506 static const struct soc_enum aif2adcl_src
=
507 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1
, 15, 2, aif_chan_src_text
);
509 static const struct soc_enum aif2adcr_src
=
510 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1
, 14, 2, aif_chan_src_text
);
512 static const struct soc_enum aif1dacl_src
=
513 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2
, 15, 2, aif_chan_src_text
);
515 static const struct soc_enum aif1dacr_src
=
516 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2
, 14, 2, aif_chan_src_text
);
518 static const struct soc_enum aif2dacl_src
=
519 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2
, 15, 2, aif_chan_src_text
);
521 static const struct soc_enum aif2dacr_src
=
522 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2
, 14, 2, aif_chan_src_text
);
524 static const char *osr_text
[] = {
525 "Low Power", "High Performance",
528 static const struct soc_enum dac_osr
=
529 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING
, 0, 2, osr_text
);
531 static const struct soc_enum adc_osr
=
532 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING
, 1, 2, osr_text
);
534 static const struct snd_kcontrol_new wm8994_snd_controls
[] = {
535 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME
,
536 WM8994_AIF1_ADC1_RIGHT_VOLUME
,
537 1, 119, 0, digital_tlv
),
538 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME
,
539 WM8994_AIF1_ADC2_RIGHT_VOLUME
,
540 1, 119, 0, digital_tlv
),
541 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME
,
542 WM8994_AIF2_ADC_RIGHT_VOLUME
,
543 1, 119, 0, digital_tlv
),
545 SOC_ENUM("AIF1ADCL Source", aif1adcl_src
),
546 SOC_ENUM("AIF1ADCR Source", aif1adcr_src
),
547 SOC_ENUM("AIF2ADCL Source", aif2adcl_src
),
548 SOC_ENUM("AIF2ADCR Source", aif2adcr_src
),
550 SOC_ENUM("AIF1DACL Source", aif1dacl_src
),
551 SOC_ENUM("AIF1DACR Source", aif1dacr_src
),
552 SOC_ENUM("AIF2DACL Source", aif2dacl_src
),
553 SOC_ENUM("AIF2DACR Source", aif2dacr_src
),
555 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME
,
556 WM8994_AIF1_DAC1_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
557 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME
,
558 WM8994_AIF1_DAC2_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
559 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME
,
560 WM8994_AIF2_DAC_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
562 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2
, 10, 3, 0, aif_tlv
),
563 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2
, 10, 3, 0, aif_tlv
),
565 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1
, 0, 1, 0),
566 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1
, 0, 1, 0),
567 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1
, 0, 1, 0),
569 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1
, 2),
570 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1
, 1),
571 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1
, 0),
573 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1
, 2),
574 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1
, 1),
575 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1
, 0),
577 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1
, 2),
578 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1
, 1),
579 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1
, 0),
581 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES
,
583 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES
,
585 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES
,
587 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES
,
589 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf
),
590 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE
, 6, 1, 0),
592 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf
),
593 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS
, 12, 11, 1, 0),
595 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf
),
596 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS
, 12, 11, 1, 0),
598 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf
),
599 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS
, 12, 11, 1, 0),
601 SOC_ENUM("ADC OSR", adc_osr
),
602 SOC_ENUM("DAC OSR", dac_osr
),
604 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME
,
605 WM8994_DAC1_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
606 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME
,
607 WM8994_DAC1_RIGHT_VOLUME
, 9, 1, 1),
609 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME
,
610 WM8994_DAC2_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
611 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME
,
612 WM8994_DAC2_RIGHT_VOLUME
, 9, 1, 1),
614 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION
,
615 6, 1, 1, wm_hubs_spkmix_tlv
),
616 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION
,
617 2, 1, 1, wm_hubs_spkmix_tlv
),
619 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION
,
620 6, 1, 1, wm_hubs_spkmix_tlv
),
621 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION
,
622 2, 1, 1, wm_hubs_spkmix_tlv
),
624 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2
,
625 10, 15, 0, wm8994_3d_tlv
),
626 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2
,
628 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2
,
629 10, 15, 0, wm8994_3d_tlv
),
630 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2
,
632 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2
,
633 10, 15, 0, wm8994_3d_tlv
),
634 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2
,
638 static const struct snd_kcontrol_new wm8994_eq_controls
[] = {
639 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 11, 31, 0,
641 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 6, 31, 0,
643 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 1, 31, 0,
645 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2
, 11, 31, 0,
647 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2
, 6, 31, 0,
650 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 11, 31, 0,
652 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 6, 31, 0,
654 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 1, 31, 0,
656 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2
, 11, 31, 0,
658 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2
, 6, 31, 0,
661 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1
, 11, 31, 0,
663 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1
, 6, 31, 0,
665 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1
, 1, 31, 0,
667 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2
, 11, 31, 0,
669 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2
, 6, 31, 0,
673 static const struct snd_kcontrol_new wm8994_drc_controls
[] = {
674 SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1
, 5,
675 WM8994_AIF1DAC1_DRC_ENA
| WM8994_AIF1ADC1L_DRC_ENA
|
676 WM8994_AIF1ADC1R_DRC_ENA
),
677 SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1
, 5,
678 WM8994_AIF1DAC2_DRC_ENA
| WM8994_AIF1ADC2L_DRC_ENA
|
679 WM8994_AIF1ADC2R_DRC_ENA
),
680 SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1
, 5,
681 WM8994_AIF2DAC_DRC_ENA
| WM8994_AIF2ADCL_DRC_ENA
|
682 WM8994_AIF2ADCR_DRC_ENA
),
685 static const char *wm8958_ng_text
[] = {
686 "30ms", "125ms", "250ms", "500ms",
689 static const struct soc_enum wm8958_aif1dac1_ng_hold
=
690 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE
,
691 WM8958_AIF1DAC1_NG_THR_SHIFT
, 4, wm8958_ng_text
);
693 static const struct soc_enum wm8958_aif1dac2_ng_hold
=
694 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE
,
695 WM8958_AIF1DAC2_NG_THR_SHIFT
, 4, wm8958_ng_text
);
697 static const struct soc_enum wm8958_aif2dac_ng_hold
=
698 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE
,
699 WM8958_AIF2DAC_NG_THR_SHIFT
, 4, wm8958_ng_text
);
701 static const struct snd_kcontrol_new wm8958_snd_controls
[] = {
702 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2
, 10, 3, 0, aif_tlv
),
704 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE
,
705 WM8958_AIF1DAC1_NG_ENA_SHIFT
, 1, 0),
706 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold
),
707 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
708 WM8958_AIF1_DAC1_NOISE_GATE
, WM8958_AIF1DAC1_NG_THR_SHIFT
,
711 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE
,
712 WM8958_AIF1DAC2_NG_ENA_SHIFT
, 1, 0),
713 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold
),
714 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
715 WM8958_AIF1_DAC2_NOISE_GATE
, WM8958_AIF1DAC2_NG_THR_SHIFT
,
718 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE
,
719 WM8958_AIF2DAC_NG_ENA_SHIFT
, 1, 0),
720 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold
),
721 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
722 WM8958_AIF2_DAC_NOISE_GATE
, WM8958_AIF2DAC_NG_THR_SHIFT
,
726 static const struct snd_kcontrol_new wm1811_snd_controls
[] = {
727 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1
, 7, 1, 0,
729 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1
, 8, 1, 0,
733 /* We run all mode setting through a function to enforce audio mode */
734 static void wm1811_jackdet_set_mode(struct snd_soc_codec
*codec
, u16 mode
)
736 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
738 if (!wm8994
->jackdet
|| !wm8994
->micdet
[0].jack
)
741 if (wm8994
->active_refcount
)
742 mode
= WM1811_JACKDET_MODE_AUDIO
;
744 if (mode
== wm8994
->jackdet_mode
)
747 wm8994
->jackdet_mode
= mode
;
749 /* Always use audio mode to detect while the system is active */
750 if (mode
!= WM1811_JACKDET_MODE_NONE
)
751 mode
= WM1811_JACKDET_MODE_AUDIO
;
753 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
754 WM1811_JACKDET_MODE_MASK
, mode
);
757 static void active_reference(struct snd_soc_codec
*codec
)
759 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
761 mutex_lock(&wm8994
->accdet_lock
);
763 wm8994
->active_refcount
++;
765 dev_dbg(codec
->dev
, "Active refcount incremented, now %d\n",
766 wm8994
->active_refcount
);
768 /* If we're using jack detection go into audio mode */
769 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_AUDIO
);
771 mutex_unlock(&wm8994
->accdet_lock
);
774 static void active_dereference(struct snd_soc_codec
*codec
)
776 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
779 mutex_lock(&wm8994
->accdet_lock
);
781 wm8994
->active_refcount
--;
783 dev_dbg(codec
->dev
, "Active refcount decremented, now %d\n",
784 wm8994
->active_refcount
);
786 if (wm8994
->active_refcount
== 0) {
787 /* Go into appropriate detection only mode */
788 if (wm8994
->jack_mic
|| wm8994
->mic_detecting
)
789 mode
= WM1811_JACKDET_MODE_MIC
;
791 mode
= WM1811_JACKDET_MODE_JACK
;
793 wm1811_jackdet_set_mode(codec
, mode
);
796 mutex_unlock(&wm8994
->accdet_lock
);
799 static int clk_sys_event(struct snd_soc_dapm_widget
*w
,
800 struct snd_kcontrol
*kcontrol
, int event
)
802 struct snd_soc_codec
*codec
= w
->codec
;
803 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
806 case SND_SOC_DAPM_PRE_PMU
:
807 return configure_clock(codec
);
809 case SND_SOC_DAPM_POST_PMU
:
811 * JACKDET won't run until we start the clock and it
812 * only reports deltas, make sure we notify the state
813 * up the stack on startup. Use a *very* generous
814 * timeout for paranoia, there's no urgency and we
815 * don't want false reports.
817 if (wm8994
->jackdet
&& !wm8994
->clk_has_run
) {
818 schedule_delayed_work(&wm8994
->jackdet_bootstrap
,
819 msecs_to_jiffies(1000));
820 wm8994
->clk_has_run
= true;
824 case SND_SOC_DAPM_POST_PMD
:
825 configure_clock(codec
);
832 static void vmid_reference(struct snd_soc_codec
*codec
)
834 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
836 pm_runtime_get_sync(codec
->dev
);
838 wm8994
->vmid_refcount
++;
840 dev_dbg(codec
->dev
, "Referencing VMID, refcount is now %d\n",
841 wm8994
->vmid_refcount
);
843 if (wm8994
->vmid_refcount
== 1) {
844 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
845 WM8994_LINEOUT1_DISCH
|
846 WM8994_LINEOUT2_DISCH
, 0);
848 wm_hubs_vmid_ena(codec
);
850 switch (wm8994
->vmid_mode
) {
852 WARN_ON(NULL
== "Invalid VMID mode");
853 case WM8994_VMID_NORMAL
:
854 /* Startup bias, VMID ramp & buffer */
855 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
858 WM8994_STARTUP_BIAS_ENA
|
859 WM8994_VMID_BUF_ENA
|
860 WM8994_VMID_RAMP_MASK
,
862 WM8994_STARTUP_BIAS_ENA
|
863 WM8994_VMID_BUF_ENA
|
864 (0x2 << WM8994_VMID_RAMP_SHIFT
));
866 /* Main bias enable, VMID=2x40k */
867 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
869 WM8994_VMID_SEL_MASK
,
870 WM8994_BIAS_ENA
| 0x2);
874 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
875 WM8994_VMID_RAMP_MASK
|
880 case WM8994_VMID_FORCE
:
881 /* Startup bias, slow VMID ramp & buffer */
882 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
885 WM8994_STARTUP_BIAS_ENA
|
886 WM8994_VMID_BUF_ENA
|
887 WM8994_VMID_RAMP_MASK
,
889 WM8994_STARTUP_BIAS_ENA
|
890 WM8994_VMID_BUF_ENA
|
891 (0x2 << WM8994_VMID_RAMP_SHIFT
));
893 /* Main bias enable, VMID=2x40k */
894 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
896 WM8994_VMID_SEL_MASK
,
897 WM8994_BIAS_ENA
| 0x2);
901 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
902 WM8994_VMID_RAMP_MASK
|
910 static void vmid_dereference(struct snd_soc_codec
*codec
)
912 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
914 wm8994
->vmid_refcount
--;
916 dev_dbg(codec
->dev
, "Dereferencing VMID, refcount is now %d\n",
917 wm8994
->vmid_refcount
);
919 if (wm8994
->vmid_refcount
== 0) {
920 if (wm8994
->hubs
.lineout1_se
)
921 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_3
,
922 WM8994_LINEOUT1N_ENA
|
923 WM8994_LINEOUT1P_ENA
,
924 WM8994_LINEOUT1N_ENA
|
925 WM8994_LINEOUT1P_ENA
);
927 if (wm8994
->hubs
.lineout2_se
)
928 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_3
,
929 WM8994_LINEOUT2N_ENA
|
930 WM8994_LINEOUT2P_ENA
,
931 WM8994_LINEOUT2N_ENA
|
932 WM8994_LINEOUT2P_ENA
);
934 /* Start discharging VMID */
935 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
941 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
942 WM8994_VMID_SEL_MASK
, 0);
946 /* Active discharge */
947 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
948 WM8994_LINEOUT1_DISCH
|
949 WM8994_LINEOUT2_DISCH
,
950 WM8994_LINEOUT1_DISCH
|
951 WM8994_LINEOUT2_DISCH
);
953 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_3
,
954 WM8994_LINEOUT1N_ENA
|
955 WM8994_LINEOUT1P_ENA
|
956 WM8994_LINEOUT2N_ENA
|
957 WM8994_LINEOUT2P_ENA
, 0);
959 /* Switch off startup biases */
960 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
962 WM8994_STARTUP_BIAS_ENA
|
963 WM8994_VMID_BUF_ENA
|
964 WM8994_VMID_RAMP_MASK
, 0);
966 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
967 WM8994_VMID_SEL_MASK
, 0);
970 pm_runtime_put(codec
->dev
);
973 static int vmid_event(struct snd_soc_dapm_widget
*w
,
974 struct snd_kcontrol
*kcontrol
, int event
)
976 struct snd_soc_codec
*codec
= w
->codec
;
979 case SND_SOC_DAPM_PRE_PMU
:
980 vmid_reference(codec
);
983 case SND_SOC_DAPM_POST_PMD
:
984 vmid_dereference(codec
);
991 static bool wm8994_check_class_w_digital(struct snd_soc_codec
*codec
)
993 int source
= 0; /* GCC flow analysis can't track enable */
996 /* We also need the same AIF source for L/R and only one path */
997 reg
= snd_soc_read(codec
, WM8994_DAC1_LEFT_MIXER_ROUTING
);
999 case WM8994_AIF2DACL_TO_DAC1L
:
1000 dev_vdbg(codec
->dev
, "Class W source AIF2DAC\n");
1001 source
= 2 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
1003 case WM8994_AIF1DAC2L_TO_DAC1L
:
1004 dev_vdbg(codec
->dev
, "Class W source AIF1DAC2\n");
1005 source
= 1 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
1007 case WM8994_AIF1DAC1L_TO_DAC1L
:
1008 dev_vdbg(codec
->dev
, "Class W source AIF1DAC1\n");
1009 source
= 0 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
1012 dev_vdbg(codec
->dev
, "DAC mixer setting: %x\n", reg
);
1016 reg_r
= snd_soc_read(codec
, WM8994_DAC1_RIGHT_MIXER_ROUTING
);
1018 dev_vdbg(codec
->dev
, "Left and right DAC mixers different\n");
1022 /* Set the source up */
1023 snd_soc_update_bits(codec
, WM8994_CLASS_W_1
,
1024 WM8994_CP_DYN_SRC_SEL_MASK
, source
);
1029 static int aif1clk_ev(struct snd_soc_dapm_widget
*w
,
1030 struct snd_kcontrol
*kcontrol
, int event
)
1032 struct snd_soc_codec
*codec
= w
->codec
;
1033 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1034 struct wm8994
*control
= codec
->control_data
;
1035 int mask
= WM8994_AIF1DAC1L_ENA
| WM8994_AIF1DAC1R_ENA
;
1041 switch (control
->type
) {
1044 mask
|= WM8994_AIF1DAC2L_ENA
| WM8994_AIF1DAC2R_ENA
;
1051 case SND_SOC_DAPM_PRE_PMU
:
1052 /* Don't enable timeslot 2 if not in use */
1053 if (wm8994
->channels
[0] <= 2)
1054 mask
&= ~(WM8994_AIF1DAC2L_ENA
| WM8994_AIF1DAC2R_ENA
);
1056 val
= snd_soc_read(codec
, WM8994_AIF1_CONTROL_1
);
1057 if ((val
& WM8994_AIF1ADCL_SRC
) &&
1058 (val
& WM8994_AIF1ADCR_SRC
))
1059 adc
= WM8994_AIF1ADC1R_ENA
| WM8994_AIF1ADC2R_ENA
;
1060 else if (!(val
& WM8994_AIF1ADCL_SRC
) &&
1061 !(val
& WM8994_AIF1ADCR_SRC
))
1062 adc
= WM8994_AIF1ADC1L_ENA
| WM8994_AIF1ADC2L_ENA
;
1064 adc
= WM8994_AIF1ADC1R_ENA
| WM8994_AIF1ADC2R_ENA
|
1065 WM8994_AIF1ADC1L_ENA
| WM8994_AIF1ADC2L_ENA
;
1067 val
= snd_soc_read(codec
, WM8994_AIF1_CONTROL_2
);
1068 if ((val
& WM8994_AIF1DACL_SRC
) &&
1069 (val
& WM8994_AIF1DACR_SRC
))
1070 dac
= WM8994_AIF1DAC1R_ENA
| WM8994_AIF1DAC2R_ENA
;
1071 else if (!(val
& WM8994_AIF1DACL_SRC
) &&
1072 !(val
& WM8994_AIF1DACR_SRC
))
1073 dac
= WM8994_AIF1DAC1L_ENA
| WM8994_AIF1DAC2L_ENA
;
1075 dac
= WM8994_AIF1DAC1R_ENA
| WM8994_AIF1DAC2R_ENA
|
1076 WM8994_AIF1DAC1L_ENA
| WM8994_AIF1DAC2L_ENA
;
1078 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
,
1080 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1082 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
1083 WM8994_AIF1DSPCLK_ENA
|
1084 WM8994_SYSDSPCLK_ENA
,
1085 WM8994_AIF1DSPCLK_ENA
|
1086 WM8994_SYSDSPCLK_ENA
);
1087 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
, mask
,
1088 WM8994_AIF1ADC1R_ENA
|
1089 WM8994_AIF1ADC1L_ENA
|
1090 WM8994_AIF1ADC2R_ENA
|
1091 WM8994_AIF1ADC2L_ENA
);
1092 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
, mask
,
1093 WM8994_AIF1DAC1R_ENA
|
1094 WM8994_AIF1DAC1L_ENA
|
1095 WM8994_AIF1DAC2R_ENA
|
1096 WM8994_AIF1DAC2L_ENA
);
1099 case SND_SOC_DAPM_POST_PMU
:
1100 for (i
= 0; i
< ARRAY_SIZE(wm8994_vu_bits
); i
++)
1101 snd_soc_write(codec
, wm8994_vu_bits
[i
].reg
,
1103 wm8994_vu_bits
[i
].reg
));
1106 case SND_SOC_DAPM_PRE_PMD
:
1107 case SND_SOC_DAPM_POST_PMD
:
1108 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1110 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
,
1113 val
= snd_soc_read(codec
, WM8994_CLOCKING_1
);
1114 if (val
& WM8994_AIF2DSPCLK_ENA
)
1115 val
= WM8994_SYSDSPCLK_ENA
;
1118 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
1119 WM8994_SYSDSPCLK_ENA
|
1120 WM8994_AIF1DSPCLK_ENA
, val
);
1127 static int aif2clk_ev(struct snd_soc_dapm_widget
*w
,
1128 struct snd_kcontrol
*kcontrol
, int event
)
1130 struct snd_soc_codec
*codec
= w
->codec
;
1137 case SND_SOC_DAPM_PRE_PMU
:
1138 val
= snd_soc_read(codec
, WM8994_AIF2_CONTROL_1
);
1139 if ((val
& WM8994_AIF2ADCL_SRC
) &&
1140 (val
& WM8994_AIF2ADCR_SRC
))
1141 adc
= WM8994_AIF2ADCR_ENA
;
1142 else if (!(val
& WM8994_AIF2ADCL_SRC
) &&
1143 !(val
& WM8994_AIF2ADCR_SRC
))
1144 adc
= WM8994_AIF2ADCL_ENA
;
1146 adc
= WM8994_AIF2ADCL_ENA
| WM8994_AIF2ADCR_ENA
;
1149 val
= snd_soc_read(codec
, WM8994_AIF2_CONTROL_2
);
1150 if ((val
& WM8994_AIF2DACL_SRC
) &&
1151 (val
& WM8994_AIF2DACR_SRC
))
1152 dac
= WM8994_AIF2DACR_ENA
;
1153 else if (!(val
& WM8994_AIF2DACL_SRC
) &&
1154 !(val
& WM8994_AIF2DACR_SRC
))
1155 dac
= WM8994_AIF2DACL_ENA
;
1157 dac
= WM8994_AIF2DACL_ENA
| WM8994_AIF2DACR_ENA
;
1159 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
,
1160 WM8994_AIF2ADCL_ENA
|
1161 WM8994_AIF2ADCR_ENA
, adc
);
1162 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1163 WM8994_AIF2DACL_ENA
|
1164 WM8994_AIF2DACR_ENA
, dac
);
1165 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
1166 WM8994_AIF2DSPCLK_ENA
|
1167 WM8994_SYSDSPCLK_ENA
,
1168 WM8994_AIF2DSPCLK_ENA
|
1169 WM8994_SYSDSPCLK_ENA
);
1170 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
,
1171 WM8994_AIF2ADCL_ENA
|
1172 WM8994_AIF2ADCR_ENA
,
1173 WM8994_AIF2ADCL_ENA
|
1174 WM8994_AIF2ADCR_ENA
);
1175 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1176 WM8994_AIF2DACL_ENA
|
1177 WM8994_AIF2DACR_ENA
,
1178 WM8994_AIF2DACL_ENA
|
1179 WM8994_AIF2DACR_ENA
);
1182 case SND_SOC_DAPM_POST_PMU
:
1183 for (i
= 0; i
< ARRAY_SIZE(wm8994_vu_bits
); i
++)
1184 snd_soc_write(codec
, wm8994_vu_bits
[i
].reg
,
1186 wm8994_vu_bits
[i
].reg
));
1189 case SND_SOC_DAPM_PRE_PMD
:
1190 case SND_SOC_DAPM_POST_PMD
:
1191 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1192 WM8994_AIF2DACL_ENA
|
1193 WM8994_AIF2DACR_ENA
, 0);
1194 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
,
1195 WM8994_AIF2ADCL_ENA
|
1196 WM8994_AIF2ADCR_ENA
, 0);
1198 val
= snd_soc_read(codec
, WM8994_CLOCKING_1
);
1199 if (val
& WM8994_AIF1DSPCLK_ENA
)
1200 val
= WM8994_SYSDSPCLK_ENA
;
1203 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
1204 WM8994_SYSDSPCLK_ENA
|
1205 WM8994_AIF2DSPCLK_ENA
, val
);
1212 static int aif1clk_late_ev(struct snd_soc_dapm_widget
*w
,
1213 struct snd_kcontrol
*kcontrol
, int event
)
1215 struct snd_soc_codec
*codec
= w
->codec
;
1216 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1219 case SND_SOC_DAPM_PRE_PMU
:
1220 wm8994
->aif1clk_enable
= 1;
1222 case SND_SOC_DAPM_POST_PMD
:
1223 wm8994
->aif1clk_disable
= 1;
1230 static int aif2clk_late_ev(struct snd_soc_dapm_widget
*w
,
1231 struct snd_kcontrol
*kcontrol
, int event
)
1233 struct snd_soc_codec
*codec
= w
->codec
;
1234 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1237 case SND_SOC_DAPM_PRE_PMU
:
1238 wm8994
->aif2clk_enable
= 1;
1240 case SND_SOC_DAPM_POST_PMD
:
1241 wm8994
->aif2clk_disable
= 1;
1248 static int late_enable_ev(struct snd_soc_dapm_widget
*w
,
1249 struct snd_kcontrol
*kcontrol
, int event
)
1251 struct snd_soc_codec
*codec
= w
->codec
;
1252 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1255 case SND_SOC_DAPM_PRE_PMU
:
1256 if (wm8994
->aif1clk_enable
) {
1257 aif1clk_ev(w
, kcontrol
, SND_SOC_DAPM_PRE_PMU
);
1258 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
1259 WM8994_AIF1CLK_ENA_MASK
,
1260 WM8994_AIF1CLK_ENA
);
1261 aif1clk_ev(w
, kcontrol
, SND_SOC_DAPM_POST_PMU
);
1262 wm8994
->aif1clk_enable
= 0;
1264 if (wm8994
->aif2clk_enable
) {
1265 aif2clk_ev(w
, kcontrol
, SND_SOC_DAPM_PRE_PMU
);
1266 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
1267 WM8994_AIF2CLK_ENA_MASK
,
1268 WM8994_AIF2CLK_ENA
);
1269 aif2clk_ev(w
, kcontrol
, SND_SOC_DAPM_POST_PMU
);
1270 wm8994
->aif2clk_enable
= 0;
1275 /* We may also have postponed startup of DSP, handle that. */
1276 wm8958_aif_ev(w
, kcontrol
, event
);
1281 static int late_disable_ev(struct snd_soc_dapm_widget
*w
,
1282 struct snd_kcontrol
*kcontrol
, int event
)
1284 struct snd_soc_codec
*codec
= w
->codec
;
1285 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1288 case SND_SOC_DAPM_POST_PMD
:
1289 if (wm8994
->aif1clk_disable
) {
1290 aif1clk_ev(w
, kcontrol
, SND_SOC_DAPM_PRE_PMD
);
1291 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
1292 WM8994_AIF1CLK_ENA_MASK
, 0);
1293 aif1clk_ev(w
, kcontrol
, SND_SOC_DAPM_POST_PMD
);
1294 wm8994
->aif1clk_disable
= 0;
1296 if (wm8994
->aif2clk_disable
) {
1297 aif2clk_ev(w
, kcontrol
, SND_SOC_DAPM_PRE_PMD
);
1298 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
1299 WM8994_AIF2CLK_ENA_MASK
, 0);
1300 aif2clk_ev(w
, kcontrol
, SND_SOC_DAPM_POST_PMD
);
1301 wm8994
->aif2clk_disable
= 0;
1309 static int adc_mux_ev(struct snd_soc_dapm_widget
*w
,
1310 struct snd_kcontrol
*kcontrol
, int event
)
1312 late_enable_ev(w
, kcontrol
, event
);
1316 static int micbias_ev(struct snd_soc_dapm_widget
*w
,
1317 struct snd_kcontrol
*kcontrol
, int event
)
1319 late_enable_ev(w
, kcontrol
, event
);
1323 static int dac_ev(struct snd_soc_dapm_widget
*w
,
1324 struct snd_kcontrol
*kcontrol
, int event
)
1326 struct snd_soc_codec
*codec
= w
->codec
;
1327 unsigned int mask
= 1 << w
->shift
;
1329 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1334 static const char *adc_mux_text
[] = {
1339 static const struct soc_enum adc_enum
=
1340 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text
);
1342 static const struct snd_kcontrol_new adcl_mux
=
1343 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum
);
1345 static const struct snd_kcontrol_new adcr_mux
=
1346 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum
);
1348 static const struct snd_kcontrol_new left_speaker_mixer
[] = {
1349 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER
, 9, 1, 0),
1350 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER
, 7, 1, 0),
1351 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER
, 5, 1, 0),
1352 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER
, 3, 1, 0),
1353 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER
, 1, 1, 0),
1356 static const struct snd_kcontrol_new right_speaker_mixer
[] = {
1357 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER
, 8, 1, 0),
1358 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER
, 6, 1, 0),
1359 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER
, 4, 1, 0),
1360 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER
, 2, 1, 0),
1361 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER
, 0, 1, 0),
1364 /* Debugging; dump chip status after DAPM transitions */
1365 static int post_ev(struct snd_soc_dapm_widget
*w
,
1366 struct snd_kcontrol
*kcontrol
, int event
)
1368 struct snd_soc_codec
*codec
= w
->codec
;
1369 dev_dbg(codec
->dev
, "SRC status: %x\n",
1371 WM8994_RATE_STATUS
));
1375 static const struct snd_kcontrol_new aif1adc1l_mix
[] = {
1376 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING
,
1378 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING
,
1382 static const struct snd_kcontrol_new aif1adc1r_mix
[] = {
1383 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING
,
1385 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING
,
1389 static const struct snd_kcontrol_new aif1adc2l_mix
[] = {
1390 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING
,
1392 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING
,
1396 static const struct snd_kcontrol_new aif1adc2r_mix
[] = {
1397 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING
,
1399 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING
,
1403 static const struct snd_kcontrol_new aif2dac2l_mix
[] = {
1404 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1406 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1408 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1410 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1412 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1416 static const struct snd_kcontrol_new aif2dac2r_mix
[] = {
1417 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1419 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1421 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1423 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1425 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1429 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1430 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1431 .info = snd_soc_info_volsw, \
1432 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1433 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1435 static int wm8994_put_class_w(struct snd_kcontrol
*kcontrol
,
1436 struct snd_ctl_elem_value
*ucontrol
)
1438 struct snd_soc_dapm_widget_list
*wlist
= snd_kcontrol_chip(kcontrol
);
1439 struct snd_soc_dapm_widget
*w
= wlist
->widgets
[0];
1440 struct snd_soc_codec
*codec
= w
->codec
;
1443 ret
= snd_soc_dapm_put_volsw(kcontrol
, ucontrol
);
1445 wm_hubs_update_class_w(codec
);
1450 static const struct snd_kcontrol_new dac1l_mix
[] = {
1451 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1453 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1455 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1457 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1459 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1463 static const struct snd_kcontrol_new dac1r_mix
[] = {
1464 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1466 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1468 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1470 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1472 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1476 static const char *sidetone_text
[] = {
1477 "ADC/DMIC1", "DMIC2",
1480 static const struct soc_enum sidetone1_enum
=
1481 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 0, 2, sidetone_text
);
1483 static const struct snd_kcontrol_new sidetone1_mux
=
1484 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum
);
1486 static const struct soc_enum sidetone2_enum
=
1487 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 1, 2, sidetone_text
);
1489 static const struct snd_kcontrol_new sidetone2_mux
=
1490 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum
);
1492 static const char *aif1dac_text
[] = {
1493 "AIF1DACDAT", "AIF3DACDAT",
1496 static const struct soc_enum aif1dac_enum
=
1497 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 0, 2, aif1dac_text
);
1499 static const struct snd_kcontrol_new aif1dac_mux
=
1500 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum
);
1502 static const char *aif2dac_text
[] = {
1503 "AIF2DACDAT", "AIF3DACDAT",
1506 static const struct soc_enum aif2dac_enum
=
1507 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 1, 2, aif2dac_text
);
1509 static const struct snd_kcontrol_new aif2dac_mux
=
1510 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum
);
1512 static const char *aif2adc_text
[] = {
1513 "AIF2ADCDAT", "AIF3DACDAT",
1516 static const struct soc_enum aif2adc_enum
=
1517 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 2, 2, aif2adc_text
);
1519 static const struct snd_kcontrol_new aif2adc_mux
=
1520 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum
);
1522 static const char *aif3adc_text
[] = {
1523 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1526 static const struct soc_enum wm8994_aif3adc_enum
=
1527 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 3, 3, aif3adc_text
);
1529 static const struct snd_kcontrol_new wm8994_aif3adc_mux
=
1530 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum
);
1532 static const struct soc_enum wm8958_aif3adc_enum
=
1533 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 3, 4, aif3adc_text
);
1535 static const struct snd_kcontrol_new wm8958_aif3adc_mux
=
1536 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum
);
1538 static const char *mono_pcm_out_text
[] = {
1539 "None", "AIF2ADCL", "AIF2ADCR",
1542 static const struct soc_enum mono_pcm_out_enum
=
1543 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 9, 3, mono_pcm_out_text
);
1545 static const struct snd_kcontrol_new mono_pcm_out_mux
=
1546 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum
);
1548 static const char *aif2dac_src_text
[] = {
1552 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1553 static const struct soc_enum aif2dacl_src_enum
=
1554 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 7, 2, aif2dac_src_text
);
1556 static const struct snd_kcontrol_new aif2dacl_src_mux
=
1557 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum
);
1559 static const struct soc_enum aif2dacr_src_enum
=
1560 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 8, 2, aif2dac_src_text
);
1562 static const struct snd_kcontrol_new aif2dacr_src_mux
=
1563 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum
);
1565 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets
[] = {
1566 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM
, 0, 0, aif1clk_late_ev
,
1567 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1568 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM
, 0, 0, aif2clk_late_ev
,
1569 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1571 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1572 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1573 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1574 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1575 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1576 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1577 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1578 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1579 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1580 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1582 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3
, 8, 0,
1583 left_speaker_mixer
, ARRAY_SIZE(left_speaker_mixer
),
1584 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1585 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3
, 9, 0,
1586 right_speaker_mixer
, ARRAY_SIZE(right_speaker_mixer
),
1587 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1588 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM
, 0, 0, &wm_hubs_hpl_mux
,
1589 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1590 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM
, 0, 0, &wm_hubs_hpr_mux
,
1591 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1593 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev
)
1596 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets
[] = {
1597 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1
, 0, 0, aif1clk_ev
,
1598 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMU
|
1599 SND_SOC_DAPM_PRE_PMD
),
1600 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1
, 0, 0, aif2clk_ev
,
1601 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMU
|
1602 SND_SOC_DAPM_PRE_PMD
),
1603 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM
, 0, 0, NULL
, 0),
1604 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3
, 8, 0,
1605 left_speaker_mixer
, ARRAY_SIZE(left_speaker_mixer
)),
1606 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3
, 9, 0,
1607 right_speaker_mixer
, ARRAY_SIZE(right_speaker_mixer
)),
1608 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM
, 0, 0, &wm_hubs_hpl_mux
),
1609 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM
, 0, 0, &wm_hubs_hpr_mux
),
1612 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets
[] = {
1613 SND_SOC_DAPM_DAC_E("DAC2L", NULL
, SND_SOC_NOPM
, 3, 0,
1614 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1615 SND_SOC_DAPM_DAC_E("DAC2R", NULL
, SND_SOC_NOPM
, 2, 0,
1616 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1617 SND_SOC_DAPM_DAC_E("DAC1L", NULL
, SND_SOC_NOPM
, 1, 0,
1618 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1619 SND_SOC_DAPM_DAC_E("DAC1R", NULL
, SND_SOC_NOPM
, 0, 0,
1620 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1623 static const struct snd_soc_dapm_widget wm8994_dac_widgets
[] = {
1624 SND_SOC_DAPM_DAC("DAC2L", NULL
, WM8994_POWER_MANAGEMENT_5
, 3, 0),
1625 SND_SOC_DAPM_DAC("DAC2R", NULL
, WM8994_POWER_MANAGEMENT_5
, 2, 0),
1626 SND_SOC_DAPM_DAC("DAC1L", NULL
, WM8994_POWER_MANAGEMENT_5
, 1, 0),
1627 SND_SOC_DAPM_DAC("DAC1R", NULL
, WM8994_POWER_MANAGEMENT_5
, 0, 0),
1630 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets
[] = {
1631 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4
, 1, 0, &adcl_mux
,
1632 adc_mux_ev
, SND_SOC_DAPM_PRE_PMU
),
1633 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4
, 0, 0, &adcr_mux
,
1634 adc_mux_ev
, SND_SOC_DAPM_PRE_PMU
),
1637 static const struct snd_soc_dapm_widget wm8994_adc_widgets
[] = {
1638 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4
, 1, 0, &adcl_mux
),
1639 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4
, 0, 0, &adcr_mux
),
1642 static const struct snd_soc_dapm_widget wm8994_dapm_widgets
[] = {
1643 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1644 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1645 SND_SOC_DAPM_INPUT("Clock"),
1647 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM
, 0, 0, micbias_ev
,
1648 SND_SOC_DAPM_PRE_PMU
),
1649 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM
, 0, 0, vmid_event
,
1650 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1652 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM
, 0, 0, clk_sys_event
,
1653 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMU
|
1654 SND_SOC_DAPM_PRE_PMD
),
1656 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM
, 3, 0, NULL
, 0),
1657 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM
, 2, 0, NULL
, 0),
1658 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM
, 1, 0, NULL
, 0),
1660 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL
,
1661 0, SND_SOC_NOPM
, 9, 0),
1662 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL
,
1663 0, SND_SOC_NOPM
, 8, 0),
1664 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL
, 0,
1665 SND_SOC_NOPM
, 9, 0, wm8958_aif_ev
,
1666 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1667 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL
, 0,
1668 SND_SOC_NOPM
, 8, 0, wm8958_aif_ev
,
1669 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1671 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL
,
1672 0, SND_SOC_NOPM
, 11, 0),
1673 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL
,
1674 0, SND_SOC_NOPM
, 10, 0),
1675 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL
, 0,
1676 SND_SOC_NOPM
, 11, 0, wm8958_aif_ev
,
1677 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1678 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL
, 0,
1679 SND_SOC_NOPM
, 10, 0, wm8958_aif_ev
,
1680 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1682 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM
, 0, 0,
1683 aif1adc1l_mix
, ARRAY_SIZE(aif1adc1l_mix
)),
1684 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM
, 0, 0,
1685 aif1adc1r_mix
, ARRAY_SIZE(aif1adc1r_mix
)),
1687 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM
, 0, 0,
1688 aif1adc2l_mix
, ARRAY_SIZE(aif1adc2l_mix
)),
1689 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM
, 0, 0,
1690 aif1adc2r_mix
, ARRAY_SIZE(aif1adc2r_mix
)),
1692 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM
, 0, 0,
1693 aif2dac2l_mix
, ARRAY_SIZE(aif2dac2l_mix
)),
1694 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM
, 0, 0,
1695 aif2dac2r_mix
, ARRAY_SIZE(aif2dac2r_mix
)),
1697 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM
, 0, 0, &sidetone1_mux
),
1698 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM
, 0, 0, &sidetone2_mux
),
1700 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM
, 0, 0,
1701 dac1l_mix
, ARRAY_SIZE(dac1l_mix
)),
1702 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM
, 0, 0,
1703 dac1r_mix
, ARRAY_SIZE(dac1r_mix
)),
1705 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL
, 0,
1706 SND_SOC_NOPM
, 13, 0),
1707 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL
, 0,
1708 SND_SOC_NOPM
, 12, 0),
1709 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL
, 0,
1710 SND_SOC_NOPM
, 13, 0, wm8958_aif_ev
,
1711 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1712 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL
, 0,
1713 SND_SOC_NOPM
, 12, 0, wm8958_aif_ev
,
1714 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1716 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1717 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1718 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1719 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1721 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM
, 0, 0, &aif1dac_mux
),
1722 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM
, 0, 0, &aif2dac_mux
),
1723 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM
, 0, 0, &aif2adc_mux
),
1725 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1726 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1728 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1
, 4, 0, NULL
, 0),
1730 SND_SOC_DAPM_ADC("DMIC2L", NULL
, WM8994_POWER_MANAGEMENT_4
, 5, 0),
1731 SND_SOC_DAPM_ADC("DMIC2R", NULL
, WM8994_POWER_MANAGEMENT_4
, 4, 0),
1732 SND_SOC_DAPM_ADC("DMIC1L", NULL
, WM8994_POWER_MANAGEMENT_4
, 3, 0),
1733 SND_SOC_DAPM_ADC("DMIC1R", NULL
, WM8994_POWER_MANAGEMENT_4
, 2, 0),
1735 /* Power is done with the muxes since the ADC power also controls the
1736 * downsampling chain, the chip will automatically manage the analogue
1737 * specific portions.
1739 SND_SOC_DAPM_ADC("ADCL", NULL
, SND_SOC_NOPM
, 1, 0),
1740 SND_SOC_DAPM_ADC("ADCR", NULL
, SND_SOC_NOPM
, 0, 0),
1742 SND_SOC_DAPM_POST("Debug log", post_ev
),
1745 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets
[] = {
1746 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM
, 0, 0, &wm8994_aif3adc_mux
),
1749 static const struct snd_soc_dapm_widget wm8958_dapm_widgets
[] = {
1750 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6
, 5, 1, NULL
, 0),
1751 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM
, 0, 0, &mono_pcm_out_mux
),
1752 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM
, 0, 0, &aif2dacl_src_mux
),
1753 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM
, 0, 0, &aif2dacr_src_mux
),
1754 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM
, 0, 0, &wm8958_aif3adc_mux
),
1757 static const struct snd_soc_dapm_route intercon
[] = {
1758 { "CLK_SYS", NULL
, "AIF1CLK", check_clk_sys
},
1759 { "CLK_SYS", NULL
, "AIF2CLK", check_clk_sys
},
1761 { "DSP1CLK", NULL
, "CLK_SYS" },
1762 { "DSP2CLK", NULL
, "CLK_SYS" },
1763 { "DSPINTCLK", NULL
, "CLK_SYS" },
1765 { "AIF1ADC1L", NULL
, "AIF1CLK" },
1766 { "AIF1ADC1L", NULL
, "DSP1CLK" },
1767 { "AIF1ADC1R", NULL
, "AIF1CLK" },
1768 { "AIF1ADC1R", NULL
, "DSP1CLK" },
1769 { "AIF1ADC1R", NULL
, "DSPINTCLK" },
1771 { "AIF1DAC1L", NULL
, "AIF1CLK" },
1772 { "AIF1DAC1L", NULL
, "DSP1CLK" },
1773 { "AIF1DAC1R", NULL
, "AIF1CLK" },
1774 { "AIF1DAC1R", NULL
, "DSP1CLK" },
1775 { "AIF1DAC1R", NULL
, "DSPINTCLK" },
1777 { "AIF1ADC2L", NULL
, "AIF1CLK" },
1778 { "AIF1ADC2L", NULL
, "DSP1CLK" },
1779 { "AIF1ADC2R", NULL
, "AIF1CLK" },
1780 { "AIF1ADC2R", NULL
, "DSP1CLK" },
1781 { "AIF1ADC2R", NULL
, "DSPINTCLK" },
1783 { "AIF1DAC2L", NULL
, "AIF1CLK" },
1784 { "AIF1DAC2L", NULL
, "DSP1CLK" },
1785 { "AIF1DAC2R", NULL
, "AIF1CLK" },
1786 { "AIF1DAC2R", NULL
, "DSP1CLK" },
1787 { "AIF1DAC2R", NULL
, "DSPINTCLK" },
1789 { "AIF2ADCL", NULL
, "AIF2CLK" },
1790 { "AIF2ADCL", NULL
, "DSP2CLK" },
1791 { "AIF2ADCR", NULL
, "AIF2CLK" },
1792 { "AIF2ADCR", NULL
, "DSP2CLK" },
1793 { "AIF2ADCR", NULL
, "DSPINTCLK" },
1795 { "AIF2DACL", NULL
, "AIF2CLK" },
1796 { "AIF2DACL", NULL
, "DSP2CLK" },
1797 { "AIF2DACR", NULL
, "AIF2CLK" },
1798 { "AIF2DACR", NULL
, "DSP2CLK" },
1799 { "AIF2DACR", NULL
, "DSPINTCLK" },
1801 { "DMIC1L", NULL
, "DMIC1DAT" },
1802 { "DMIC1L", NULL
, "CLK_SYS" },
1803 { "DMIC1R", NULL
, "DMIC1DAT" },
1804 { "DMIC1R", NULL
, "CLK_SYS" },
1805 { "DMIC2L", NULL
, "DMIC2DAT" },
1806 { "DMIC2L", NULL
, "CLK_SYS" },
1807 { "DMIC2R", NULL
, "DMIC2DAT" },
1808 { "DMIC2R", NULL
, "CLK_SYS" },
1810 { "ADCL", NULL
, "AIF1CLK" },
1811 { "ADCL", NULL
, "DSP1CLK" },
1812 { "ADCL", NULL
, "DSPINTCLK" },
1814 { "ADCR", NULL
, "AIF1CLK" },
1815 { "ADCR", NULL
, "DSP1CLK" },
1816 { "ADCR", NULL
, "DSPINTCLK" },
1818 { "ADCL Mux", "ADC", "ADCL" },
1819 { "ADCL Mux", "DMIC", "DMIC1L" },
1820 { "ADCR Mux", "ADC", "ADCR" },
1821 { "ADCR Mux", "DMIC", "DMIC1R" },
1823 { "DAC1L", NULL
, "AIF1CLK" },
1824 { "DAC1L", NULL
, "DSP1CLK" },
1825 { "DAC1L", NULL
, "DSPINTCLK" },
1827 { "DAC1R", NULL
, "AIF1CLK" },
1828 { "DAC1R", NULL
, "DSP1CLK" },
1829 { "DAC1R", NULL
, "DSPINTCLK" },
1831 { "DAC2L", NULL
, "AIF2CLK" },
1832 { "DAC2L", NULL
, "DSP2CLK" },
1833 { "DAC2L", NULL
, "DSPINTCLK" },
1835 { "DAC2R", NULL
, "AIF2DACR" },
1836 { "DAC2R", NULL
, "AIF2CLK" },
1837 { "DAC2R", NULL
, "DSP2CLK" },
1838 { "DAC2R", NULL
, "DSPINTCLK" },
1840 { "TOCLK", NULL
, "CLK_SYS" },
1842 { "AIF1DACDAT", NULL
, "AIF1 Playback" },
1843 { "AIF2DACDAT", NULL
, "AIF2 Playback" },
1844 { "AIF3DACDAT", NULL
, "AIF3 Playback" },
1846 { "AIF1 Capture", NULL
, "AIF1ADCDAT" },
1847 { "AIF2 Capture", NULL
, "AIF2ADCDAT" },
1848 { "AIF3 Capture", NULL
, "AIF3ADCDAT" },
1851 { "AIF1ADC1L", NULL
, "AIF1ADC1L Mixer" },
1852 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1853 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1855 { "AIF1ADC1R", NULL
, "AIF1ADC1R Mixer" },
1856 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1857 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1859 { "AIF1ADC2L", NULL
, "AIF1ADC2L Mixer" },
1860 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1861 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1863 { "AIF1ADC2R", NULL
, "AIF1ADC2R Mixer" },
1864 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1865 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1867 /* Pin level routing for AIF3 */
1868 { "AIF1DAC1L", NULL
, "AIF1DAC Mux" },
1869 { "AIF1DAC1R", NULL
, "AIF1DAC Mux" },
1870 { "AIF1DAC2L", NULL
, "AIF1DAC Mux" },
1871 { "AIF1DAC2R", NULL
, "AIF1DAC Mux" },
1873 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1874 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1875 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1876 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1877 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1878 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1879 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1882 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1883 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1884 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1885 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1886 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1888 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1889 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1890 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1891 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1892 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1894 /* DAC2/AIF2 outputs */
1895 { "AIF2ADCL", NULL
, "AIF2DAC2L Mixer" },
1896 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1897 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1898 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1899 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1900 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1902 { "AIF2ADCR", NULL
, "AIF2DAC2R Mixer" },
1903 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1904 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1905 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1906 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1907 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1909 { "AIF1ADCDAT", NULL
, "AIF1ADC1L" },
1910 { "AIF1ADCDAT", NULL
, "AIF1ADC1R" },
1911 { "AIF1ADCDAT", NULL
, "AIF1ADC2L" },
1912 { "AIF1ADCDAT", NULL
, "AIF1ADC2R" },
1914 { "AIF2ADCDAT", NULL
, "AIF2ADC Mux" },
1917 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1918 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1919 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1920 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1921 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1922 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1923 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1924 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1927 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1928 { "Left Sidetone", "DMIC2", "DMIC2L" },
1929 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1930 { "Right Sidetone", "DMIC2", "DMIC2R" },
1933 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1934 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1936 { "SPKL", "DAC1 Switch", "DAC1L" },
1937 { "SPKL", "DAC2 Switch", "DAC2L" },
1939 { "SPKR", "DAC1 Switch", "DAC1R" },
1940 { "SPKR", "DAC2 Switch", "DAC2R" },
1942 { "Left Headphone Mux", "DAC", "DAC1L" },
1943 { "Right Headphone Mux", "DAC", "DAC1R" },
1946 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon
[] = {
1947 { "DAC1L", NULL
, "Late DAC1L Enable PGA" },
1948 { "Late DAC1L Enable PGA", NULL
, "DAC1L Mixer" },
1949 { "DAC1R", NULL
, "Late DAC1R Enable PGA" },
1950 { "Late DAC1R Enable PGA", NULL
, "DAC1R Mixer" },
1951 { "DAC2L", NULL
, "Late DAC2L Enable PGA" },
1952 { "Late DAC2L Enable PGA", NULL
, "AIF2DAC2L Mixer" },
1953 { "DAC2R", NULL
, "Late DAC2R Enable PGA" },
1954 { "Late DAC2R Enable PGA", NULL
, "AIF2DAC2R Mixer" }
1957 static const struct snd_soc_dapm_route wm8994_lateclk_intercon
[] = {
1958 { "DAC1L", NULL
, "DAC1L Mixer" },
1959 { "DAC1R", NULL
, "DAC1R Mixer" },
1960 { "DAC2L", NULL
, "AIF2DAC2L Mixer" },
1961 { "DAC2R", NULL
, "AIF2DAC2R Mixer" },
1964 static const struct snd_soc_dapm_route wm8994_revd_intercon
[] = {
1965 { "AIF1DACDAT", NULL
, "AIF2DACDAT" },
1966 { "AIF2DACDAT", NULL
, "AIF1DACDAT" },
1967 { "AIF1ADCDAT", NULL
, "AIF2ADCDAT" },
1968 { "AIF2ADCDAT", NULL
, "AIF1ADCDAT" },
1969 { "MICBIAS1", NULL
, "CLK_SYS" },
1970 { "MICBIAS1", NULL
, "MICBIAS Supply" },
1971 { "MICBIAS2", NULL
, "CLK_SYS" },
1972 { "MICBIAS2", NULL
, "MICBIAS Supply" },
1975 static const struct snd_soc_dapm_route wm8994_intercon
[] = {
1976 { "AIF2DACL", NULL
, "AIF2DAC Mux" },
1977 { "AIF2DACR", NULL
, "AIF2DAC Mux" },
1978 { "MICBIAS1", NULL
, "VMID" },
1979 { "MICBIAS2", NULL
, "VMID" },
1982 static const struct snd_soc_dapm_route wm8958_intercon
[] = {
1983 { "AIF2DACL", NULL
, "AIF2DACL Mux" },
1984 { "AIF2DACR", NULL
, "AIF2DACR Mux" },
1986 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1987 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1988 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1989 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1991 { "AIF3DACDAT", NULL
, "AIF3" },
1992 { "AIF3ADCDAT", NULL
, "AIF3" },
1994 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1995 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1997 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
2000 /* The size in bits of the FLL divide multiplied by 10
2001 * to allow rounding later */
2002 #define FIXED_FLL_SIZE ((1 << 16) * 10)
2012 static int wm8994_get_fll_config(struct fll_div
*fll
,
2013 int freq_in
, int freq_out
)
2016 unsigned int K
, Ndiv
, Nmod
;
2018 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in
, freq_out
);
2020 /* Scale the input frequency down to <= 13.5MHz */
2021 fll
->clk_ref_div
= 0;
2022 while (freq_in
> 13500000) {
2026 if (fll
->clk_ref_div
> 3)
2029 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll
->clk_ref_div
, freq_in
);
2031 /* Scale the output to give 90MHz<=Fvco<=100MHz */
2033 while (freq_out
* (fll
->outdiv
+ 1) < 90000000) {
2035 if (fll
->outdiv
> 63)
2038 freq_out
*= fll
->outdiv
+ 1;
2039 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll
->outdiv
, freq_out
);
2041 if (freq_in
> 1000000) {
2042 fll
->fll_fratio
= 0;
2043 } else if (freq_in
> 256000) {
2044 fll
->fll_fratio
= 1;
2046 } else if (freq_in
> 128000) {
2047 fll
->fll_fratio
= 2;
2049 } else if (freq_in
> 64000) {
2050 fll
->fll_fratio
= 3;
2053 fll
->fll_fratio
= 4;
2056 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll
->fll_fratio
, freq_in
);
2058 /* Now, calculate N.K */
2059 Ndiv
= freq_out
/ freq_in
;
2062 Nmod
= freq_out
% freq_in
;
2063 pr_debug("Nmod=%d\n", Nmod
);
2065 /* Calculate fractional part - scale up so we can round. */
2066 Kpart
= FIXED_FLL_SIZE
* (long long)Nmod
;
2068 do_div(Kpart
, freq_in
);
2070 K
= Kpart
& 0xFFFFFFFF;
2075 /* Move down to proper range now rounding is done */
2078 pr_debug("N=%x K=%x\n", fll
->n
, fll
->k
);
2083 static int _wm8994_set_fll(struct snd_soc_codec
*codec
, int id
, int src
,
2084 unsigned int freq_in
, unsigned int freq_out
)
2086 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2087 struct wm8994
*control
= wm8994
->wm8994
;
2088 int reg_offset
, ret
;
2090 u16 reg
, clk1
, aif_reg
, aif_src
;
2091 unsigned long timeout
;
2109 reg
= snd_soc_read(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
);
2110 was_enabled
= reg
& WM8994_FLL1_ENA
;
2114 /* Allow no source specification when stopping */
2117 src
= wm8994
->fll
[id
].src
;
2119 case WM8994_FLL_SRC_MCLK1
:
2120 case WM8994_FLL_SRC_MCLK2
:
2121 case WM8994_FLL_SRC_LRCLK
:
2122 case WM8994_FLL_SRC_BCLK
:
2124 case WM8994_FLL_SRC_INTERNAL
:
2126 freq_out
= 12000000;
2132 /* Are we changing anything? */
2133 if (wm8994
->fll
[id
].src
== src
&&
2134 wm8994
->fll
[id
].in
== freq_in
&& wm8994
->fll
[id
].out
== freq_out
)
2137 /* If we're stopping the FLL redo the old config - no
2138 * registers will actually be written but we avoid GCC flow
2139 * analysis bugs spewing warnings.
2142 ret
= wm8994_get_fll_config(&fll
, freq_in
, freq_out
);
2144 ret
= wm8994_get_fll_config(&fll
, wm8994
->fll
[id
].in
,
2145 wm8994
->fll
[id
].out
);
2149 /* Make sure that we're not providing SYSCLK right now */
2150 clk1
= snd_soc_read(codec
, WM8994_CLOCKING_1
);
2151 if (clk1
& WM8994_SYSCLK_SRC
)
2152 aif_reg
= WM8994_AIF2_CLOCKING_1
;
2154 aif_reg
= WM8994_AIF1_CLOCKING_1
;
2155 reg
= snd_soc_read(codec
, aif_reg
);
2157 if ((reg
& WM8994_AIF1CLK_ENA
) &&
2158 (reg
& WM8994_AIF1CLK_SRC_MASK
) == aif_src
) {
2159 dev_err(codec
->dev
, "FLL%d is currently providing SYSCLK\n",
2164 /* We always need to disable the FLL while reconfiguring */
2165 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
,
2166 WM8994_FLL1_ENA
, 0);
2168 if (wm8994
->fll_byp
&& src
== WM8994_FLL_SRC_BCLK
&&
2169 freq_in
== freq_out
&& freq_out
) {
2170 dev_dbg(codec
->dev
, "Bypassing FLL%d\n", id
+ 1);
2171 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_5
+ reg_offset
,
2172 WM8958_FLL1_BYP
, WM8958_FLL1_BYP
);
2176 reg
= (fll
.outdiv
<< WM8994_FLL1_OUTDIV_SHIFT
) |
2177 (fll
.fll_fratio
<< WM8994_FLL1_FRATIO_SHIFT
);
2178 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_2
+ reg_offset
,
2179 WM8994_FLL1_OUTDIV_MASK
|
2180 WM8994_FLL1_FRATIO_MASK
, reg
);
2182 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_3
+ reg_offset
,
2183 WM8994_FLL1_K_MASK
, fll
.k
);
2185 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_4
+ reg_offset
,
2187 fll
.n
<< WM8994_FLL1_N_SHIFT
);
2189 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_5
+ reg_offset
,
2190 WM8994_FLL1_FRC_NCO
| WM8958_FLL1_BYP
|
2191 WM8994_FLL1_REFCLK_DIV_MASK
|
2192 WM8994_FLL1_REFCLK_SRC_MASK
,
2193 ((src
== WM8994_FLL_SRC_INTERNAL
)
2194 << WM8994_FLL1_FRC_NCO_SHIFT
) |
2195 (fll
.clk_ref_div
<< WM8994_FLL1_REFCLK_DIV_SHIFT
) |
2198 /* Clear any pending completion from a previous failure */
2199 try_wait_for_completion(&wm8994
->fll_locked
[id
]);
2201 /* Enable (with fractional mode if required) */
2203 /* Enable VMID if we need it */
2205 active_reference(codec
);
2207 switch (control
->type
) {
2209 vmid_reference(codec
);
2212 if (control
->revision
< 1)
2213 vmid_reference(codec
);
2220 reg
= WM8994_FLL1_ENA
;
2223 reg
|= WM8994_FLL1_FRAC
;
2224 if (src
== WM8994_FLL_SRC_INTERNAL
)
2225 reg
|= WM8994_FLL1_OSC_ENA
;
2227 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
,
2228 WM8994_FLL1_ENA
| WM8994_FLL1_OSC_ENA
|
2229 WM8994_FLL1_FRAC
, reg
);
2231 if (wm8994
->fll_locked_irq
) {
2232 timeout
= wait_for_completion_timeout(&wm8994
->fll_locked
[id
],
2233 msecs_to_jiffies(10));
2235 dev_warn(codec
->dev
,
2236 "Timed out waiting for FLL lock\n");
2242 switch (control
->type
) {
2244 vmid_dereference(codec
);
2247 if (control
->revision
< 1)
2248 vmid_dereference(codec
);
2254 active_dereference(codec
);
2259 wm8994
->fll
[id
].in
= freq_in
;
2260 wm8994
->fll
[id
].out
= freq_out
;
2261 wm8994
->fll
[id
].src
= src
;
2263 configure_clock(codec
);
2266 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2269 if (max(wm8994
->aifclk
[0], wm8994
->aifclk
[1]) < 50000) {
2270 dev_dbg(codec
->dev
, "Configuring AIFs for 128fs\n");
2272 wm8994
->aifdiv
[0] = snd_soc_read(codec
, WM8994_AIF1_RATE
)
2273 & WM8994_AIF1CLK_RATE_MASK
;
2274 wm8994
->aifdiv
[1] = snd_soc_read(codec
, WM8994_AIF2_RATE
)
2275 & WM8994_AIF1CLK_RATE_MASK
;
2277 snd_soc_update_bits(codec
, WM8994_AIF1_RATE
,
2278 WM8994_AIF1CLK_RATE_MASK
, 0x1);
2279 snd_soc_update_bits(codec
, WM8994_AIF2_RATE
,
2280 WM8994_AIF2CLK_RATE_MASK
, 0x1);
2281 } else if (wm8994
->aifdiv
[0]) {
2282 snd_soc_update_bits(codec
, WM8994_AIF1_RATE
,
2283 WM8994_AIF1CLK_RATE_MASK
,
2285 snd_soc_update_bits(codec
, WM8994_AIF2_RATE
,
2286 WM8994_AIF2CLK_RATE_MASK
,
2289 wm8994
->aifdiv
[0] = 0;
2290 wm8994
->aifdiv
[1] = 0;
2296 static irqreturn_t
wm8994_fll_locked_irq(int irq
, void *data
)
2298 struct completion
*completion
= data
;
2300 complete(completion
);
2305 static int opclk_divs
[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2307 static int wm8994_set_fll(struct snd_soc_dai
*dai
, int id
, int src
,
2308 unsigned int freq_in
, unsigned int freq_out
)
2310 return _wm8994_set_fll(dai
->codec
, id
, src
, freq_in
, freq_out
);
2313 static int wm8994_set_dai_sysclk(struct snd_soc_dai
*dai
,
2314 int clk_id
, unsigned int freq
, int dir
)
2316 struct snd_soc_codec
*codec
= dai
->codec
;
2317 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2326 /* AIF3 shares clocking with AIF1/2 */
2331 case WM8994_SYSCLK_MCLK1
:
2332 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_MCLK1
;
2333 wm8994
->mclk
[0] = freq
;
2334 dev_dbg(dai
->dev
, "AIF%d using MCLK1 at %uHz\n",
2338 case WM8994_SYSCLK_MCLK2
:
2339 /* TODO: Set GPIO AF */
2340 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_MCLK2
;
2341 wm8994
->mclk
[1] = freq
;
2342 dev_dbg(dai
->dev
, "AIF%d using MCLK2 at %uHz\n",
2346 case WM8994_SYSCLK_FLL1
:
2347 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_FLL1
;
2348 dev_dbg(dai
->dev
, "AIF%d using FLL1\n", dai
->id
);
2351 case WM8994_SYSCLK_FLL2
:
2352 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_FLL2
;
2353 dev_dbg(dai
->dev
, "AIF%d using FLL2\n", dai
->id
);
2356 case WM8994_SYSCLK_OPCLK
:
2357 /* Special case - a division (times 10) is given and
2358 * no effect on main clocking.
2361 for (i
= 0; i
< ARRAY_SIZE(opclk_divs
); i
++)
2362 if (opclk_divs
[i
] == freq
)
2364 if (i
== ARRAY_SIZE(opclk_divs
))
2366 snd_soc_update_bits(codec
, WM8994_CLOCKING_2
,
2367 WM8994_OPCLK_DIV_MASK
, i
);
2368 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_2
,
2369 WM8994_OPCLK_ENA
, WM8994_OPCLK_ENA
);
2371 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_2
,
2372 WM8994_OPCLK_ENA
, 0);
2379 configure_clock(codec
);
2382 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2385 if (max(wm8994
->aifclk
[0], wm8994
->aifclk
[1]) < 50000) {
2386 dev_dbg(codec
->dev
, "Configuring AIFs for 128fs\n");
2388 wm8994
->aifdiv
[0] = snd_soc_read(codec
, WM8994_AIF1_RATE
)
2389 & WM8994_AIF1CLK_RATE_MASK
;
2390 wm8994
->aifdiv
[1] = snd_soc_read(codec
, WM8994_AIF2_RATE
)
2391 & WM8994_AIF1CLK_RATE_MASK
;
2393 snd_soc_update_bits(codec
, WM8994_AIF1_RATE
,
2394 WM8994_AIF1CLK_RATE_MASK
, 0x1);
2395 snd_soc_update_bits(codec
, WM8994_AIF2_RATE
,
2396 WM8994_AIF2CLK_RATE_MASK
, 0x1);
2397 } else if (wm8994
->aifdiv
[0]) {
2398 snd_soc_update_bits(codec
, WM8994_AIF1_RATE
,
2399 WM8994_AIF1CLK_RATE_MASK
,
2401 snd_soc_update_bits(codec
, WM8994_AIF2_RATE
,
2402 WM8994_AIF2CLK_RATE_MASK
,
2405 wm8994
->aifdiv
[0] = 0;
2406 wm8994
->aifdiv
[1] = 0;
2412 static int wm8994_set_bias_level(struct snd_soc_codec
*codec
,
2413 enum snd_soc_bias_level level
)
2415 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2416 struct wm8994
*control
= wm8994
->wm8994
;
2418 wm_hubs_set_bias_level(codec
, level
);
2421 case SND_SOC_BIAS_ON
:
2424 case SND_SOC_BIAS_PREPARE
:
2425 /* MICBIAS into regulating mode */
2426 switch (control
->type
) {
2429 snd_soc_update_bits(codec
, WM8958_MICBIAS1
,
2430 WM8958_MICB1_MODE
, 0);
2431 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
2432 WM8958_MICB2_MODE
, 0);
2438 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_STANDBY
)
2439 active_reference(codec
);
2442 case SND_SOC_BIAS_STANDBY
:
2443 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
2444 switch (control
->type
) {
2446 if (control
->revision
== 0) {
2447 /* Optimise performance for rev A */
2448 snd_soc_update_bits(codec
,
2449 WM8958_CHARGE_PUMP_2
,
2459 /* Discharge LINEOUT1 & 2 */
2460 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
2461 WM8994_LINEOUT1_DISCH
|
2462 WM8994_LINEOUT2_DISCH
,
2463 WM8994_LINEOUT1_DISCH
|
2464 WM8994_LINEOUT2_DISCH
);
2467 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_PREPARE
)
2468 active_dereference(codec
);
2470 /* MICBIAS into bypass mode on newer devices */
2471 switch (control
->type
) {
2474 snd_soc_update_bits(codec
, WM8958_MICBIAS1
,
2477 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
2486 case SND_SOC_BIAS_OFF
:
2487 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_STANDBY
)
2488 wm8994
->cur_fw
= NULL
;
2492 codec
->dapm
.bias_level
= level
;
2497 int wm8994_vmid_mode(struct snd_soc_codec
*codec
, enum wm8994_vmid_mode mode
)
2499 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2502 case WM8994_VMID_NORMAL
:
2503 if (wm8994
->hubs
.lineout1_se
) {
2504 snd_soc_dapm_disable_pin(&codec
->dapm
,
2505 "LINEOUT1N Driver");
2506 snd_soc_dapm_disable_pin(&codec
->dapm
,
2507 "LINEOUT1P Driver");
2509 if (wm8994
->hubs
.lineout2_se
) {
2510 snd_soc_dapm_disable_pin(&codec
->dapm
,
2511 "LINEOUT2N Driver");
2512 snd_soc_dapm_disable_pin(&codec
->dapm
,
2513 "LINEOUT2P Driver");
2516 /* Do the sync with the old mode to allow it to clean up */
2517 snd_soc_dapm_sync(&codec
->dapm
);
2518 wm8994
->vmid_mode
= mode
;
2521 case WM8994_VMID_FORCE
:
2522 if (wm8994
->hubs
.lineout1_se
) {
2523 snd_soc_dapm_force_enable_pin(&codec
->dapm
,
2524 "LINEOUT1N Driver");
2525 snd_soc_dapm_force_enable_pin(&codec
->dapm
,
2526 "LINEOUT1P Driver");
2528 if (wm8994
->hubs
.lineout2_se
) {
2529 snd_soc_dapm_force_enable_pin(&codec
->dapm
,
2530 "LINEOUT2N Driver");
2531 snd_soc_dapm_force_enable_pin(&codec
->dapm
,
2532 "LINEOUT2P Driver");
2535 wm8994
->vmid_mode
= mode
;
2536 snd_soc_dapm_sync(&codec
->dapm
);
2546 static int wm8994_set_dai_fmt(struct snd_soc_dai
*dai
, unsigned int fmt
)
2548 struct snd_soc_codec
*codec
= dai
->codec
;
2549 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2550 struct wm8994
*control
= wm8994
->wm8994
;
2558 ms_reg
= WM8994_AIF1_MASTER_SLAVE
;
2559 aif1_reg
= WM8994_AIF1_CONTROL_1
;
2562 ms_reg
= WM8994_AIF2_MASTER_SLAVE
;
2563 aif1_reg
= WM8994_AIF2_CONTROL_1
;
2569 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
2570 case SND_SOC_DAIFMT_CBS_CFS
:
2572 case SND_SOC_DAIFMT_CBM_CFM
:
2573 ms
= WM8994_AIF1_MSTR
;
2579 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
2580 case SND_SOC_DAIFMT_DSP_B
:
2581 aif1
|= WM8994_AIF1_LRCLK_INV
;
2582 case SND_SOC_DAIFMT_DSP_A
:
2585 case SND_SOC_DAIFMT_I2S
:
2588 case SND_SOC_DAIFMT_RIGHT_J
:
2590 case SND_SOC_DAIFMT_LEFT_J
:
2597 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
2598 case SND_SOC_DAIFMT_DSP_A
:
2599 case SND_SOC_DAIFMT_DSP_B
:
2600 /* frame inversion not valid for DSP modes */
2601 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
2602 case SND_SOC_DAIFMT_NB_NF
:
2604 case SND_SOC_DAIFMT_IB_NF
:
2605 aif1
|= WM8994_AIF1_BCLK_INV
;
2612 case SND_SOC_DAIFMT_I2S
:
2613 case SND_SOC_DAIFMT_RIGHT_J
:
2614 case SND_SOC_DAIFMT_LEFT_J
:
2615 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
2616 case SND_SOC_DAIFMT_NB_NF
:
2618 case SND_SOC_DAIFMT_IB_IF
:
2619 aif1
|= WM8994_AIF1_BCLK_INV
| WM8994_AIF1_LRCLK_INV
;
2621 case SND_SOC_DAIFMT_IB_NF
:
2622 aif1
|= WM8994_AIF1_BCLK_INV
;
2624 case SND_SOC_DAIFMT_NB_IF
:
2625 aif1
|= WM8994_AIF1_LRCLK_INV
;
2635 /* The AIF2 format configuration needs to be mirrored to AIF3
2636 * on WM8958 if it's in use so just do it all the time. */
2637 switch (control
->type
) {
2641 snd_soc_update_bits(codec
, WM8958_AIF3_CONTROL_1
,
2642 WM8994_AIF1_LRCLK_INV
|
2643 WM8958_AIF3_FMT_MASK
, aif1
);
2650 snd_soc_update_bits(codec
, aif1_reg
,
2651 WM8994_AIF1_BCLK_INV
| WM8994_AIF1_LRCLK_INV
|
2652 WM8994_AIF1_FMT_MASK
,
2654 snd_soc_update_bits(codec
, ms_reg
, WM8994_AIF1_MSTR
,
2676 static int fs_ratios
[] = {
2677 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2680 static int bclk_divs
[] = {
2681 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2682 640, 880, 960, 1280, 1760, 1920
2685 static int wm8994_hw_params(struct snd_pcm_substream
*substream
,
2686 struct snd_pcm_hw_params
*params
,
2687 struct snd_soc_dai
*dai
)
2689 struct snd_soc_codec
*codec
= dai
->codec
;
2690 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2691 struct wm8994
*control
= wm8994
->wm8994
;
2692 struct wm8994_pdata
*pdata
= &control
->pdata
;
2703 int id
= dai
->id
- 1;
2705 int i
, cur_val
, best_val
, bclk_rate
, best
;
2709 aif1_reg
= WM8994_AIF1_CONTROL_1
;
2710 aif2_reg
= WM8994_AIF1_CONTROL_2
;
2711 bclk_reg
= WM8994_AIF1_BCLK
;
2712 rate_reg
= WM8994_AIF1_RATE
;
2713 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
||
2714 wm8994
->lrclk_shared
[0]) {
2715 lrclk_reg
= WM8994_AIF1DAC_LRCLK
;
2717 lrclk_reg
= WM8994_AIF1ADC_LRCLK
;
2718 dev_dbg(codec
->dev
, "AIF1 using split LRCLK\n");
2722 aif1_reg
= WM8994_AIF2_CONTROL_1
;
2723 aif2_reg
= WM8994_AIF2_CONTROL_2
;
2724 bclk_reg
= WM8994_AIF2_BCLK
;
2725 rate_reg
= WM8994_AIF2_RATE
;
2726 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
||
2727 wm8994
->lrclk_shared
[1]) {
2728 lrclk_reg
= WM8994_AIF2DAC_LRCLK
;
2730 lrclk_reg
= WM8994_AIF2ADC_LRCLK
;
2731 dev_dbg(codec
->dev
, "AIF2 using split LRCLK\n");
2738 bclk_rate
= params_rate(params
);
2739 switch (params_format(params
)) {
2740 case SNDRV_PCM_FORMAT_S16_LE
:
2743 case SNDRV_PCM_FORMAT_S20_3LE
:
2747 case SNDRV_PCM_FORMAT_S24_LE
:
2751 case SNDRV_PCM_FORMAT_S32_LE
:
2759 wm8994
->channels
[id
] = params_channels(params
);
2760 if (pdata
->max_channels_clocked
[id
] &&
2761 wm8994
->channels
[id
] > pdata
->max_channels_clocked
[id
]) {
2762 dev_dbg(dai
->dev
, "Constraining channels to %d from %d\n",
2763 pdata
->max_channels_clocked
[id
], wm8994
->channels
[id
]);
2764 wm8994
->channels
[id
] = pdata
->max_channels_clocked
[id
];
2767 switch (wm8994
->channels
[id
]) {
2777 /* Try to find an appropriate sample rate; look for an exact match. */
2778 for (i
= 0; i
< ARRAY_SIZE(srs
); i
++)
2779 if (srs
[i
].rate
== params_rate(params
))
2781 if (i
== ARRAY_SIZE(srs
))
2783 rate_val
|= srs
[i
].val
<< WM8994_AIF1_SR_SHIFT
;
2785 dev_dbg(dai
->dev
, "Sample rate is %dHz\n", srs
[i
].rate
);
2786 dev_dbg(dai
->dev
, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2787 dai
->id
, wm8994
->aifclk
[id
], bclk_rate
);
2789 if (wm8994
->channels
[id
] == 1 &&
2790 (snd_soc_read(codec
, aif1_reg
) & 0x18) == 0x18)
2791 aif2
|= WM8994_AIF1_MONO
;
2793 if (wm8994
->aifclk
[id
] == 0) {
2794 dev_err(dai
->dev
, "AIF%dCLK not configured\n", dai
->id
);
2798 /* AIFCLK/fs ratio; look for a close match in either direction */
2800 best_val
= abs((fs_ratios
[0] * params_rate(params
))
2801 - wm8994
->aifclk
[id
]);
2802 for (i
= 1; i
< ARRAY_SIZE(fs_ratios
); i
++) {
2803 cur_val
= abs((fs_ratios
[i
] * params_rate(params
))
2804 - wm8994
->aifclk
[id
]);
2805 if (cur_val
>= best_val
)
2810 dev_dbg(dai
->dev
, "Selected AIF%dCLK/fs = %d\n",
2811 dai
->id
, fs_ratios
[best
]);
2814 /* We may not get quite the right frequency if using
2815 * approximate clocks so look for the closest match that is
2816 * higher than the target (we need to ensure that there enough
2817 * BCLKs to clock out the samples).
2820 for (i
= 0; i
< ARRAY_SIZE(bclk_divs
); i
++) {
2821 cur_val
= (wm8994
->aifclk
[id
] * 10 / bclk_divs
[i
]) - bclk_rate
;
2822 if (cur_val
< 0) /* BCLK table is sorted */
2826 bclk_rate
= wm8994
->aifclk
[id
] * 10 / bclk_divs
[best
];
2827 dev_dbg(dai
->dev
, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2828 bclk_divs
[best
], bclk_rate
);
2829 bclk
|= best
<< WM8994_AIF1_BCLK_DIV_SHIFT
;
2831 lrclk
= bclk_rate
/ params_rate(params
);
2833 dev_err(dai
->dev
, "Unable to generate LRCLK from %dHz BCLK\n",
2837 dev_dbg(dai
->dev
, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2838 lrclk
, bclk_rate
/ lrclk
);
2840 snd_soc_update_bits(codec
, aif1_reg
, WM8994_AIF1_WL_MASK
, aif1
);
2841 snd_soc_update_bits(codec
, aif2_reg
, WM8994_AIF1_MONO
, aif2
);
2842 snd_soc_update_bits(codec
, bclk_reg
, WM8994_AIF1_BCLK_DIV_MASK
, bclk
);
2843 snd_soc_update_bits(codec
, lrclk_reg
, WM8994_AIF1DAC_RATE_MASK
,
2845 snd_soc_update_bits(codec
, rate_reg
, WM8994_AIF1_SR_MASK
|
2846 WM8994_AIF1CLK_RATE_MASK
, rate_val
);
2848 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
2851 wm8994
->dac_rates
[0] = params_rate(params
);
2852 wm8994_set_retune_mobile(codec
, 0);
2853 wm8994_set_retune_mobile(codec
, 1);
2856 wm8994
->dac_rates
[1] = params_rate(params
);
2857 wm8994_set_retune_mobile(codec
, 2);
2865 static int wm8994_aif3_hw_params(struct snd_pcm_substream
*substream
,
2866 struct snd_pcm_hw_params
*params
,
2867 struct snd_soc_dai
*dai
)
2869 struct snd_soc_codec
*codec
= dai
->codec
;
2870 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2871 struct wm8994
*control
= wm8994
->wm8994
;
2877 switch (control
->type
) {
2880 aif1_reg
= WM8958_AIF3_CONTROL_1
;
2889 switch (params_format(params
)) {
2890 case SNDRV_PCM_FORMAT_S16_LE
:
2892 case SNDRV_PCM_FORMAT_S20_3LE
:
2895 case SNDRV_PCM_FORMAT_S24_LE
:
2898 case SNDRV_PCM_FORMAT_S32_LE
:
2905 return snd_soc_update_bits(codec
, aif1_reg
, WM8994_AIF1_WL_MASK
, aif1
);
2908 static int wm8994_aif_mute(struct snd_soc_dai
*codec_dai
, int mute
)
2910 struct snd_soc_codec
*codec
= codec_dai
->codec
;
2914 switch (codec_dai
->id
) {
2916 mute_reg
= WM8994_AIF1_DAC1_FILTERS_1
;
2919 mute_reg
= WM8994_AIF2_DAC_FILTERS_1
;
2926 reg
= WM8994_AIF1DAC1_MUTE
;
2930 snd_soc_update_bits(codec
, mute_reg
, WM8994_AIF1DAC1_MUTE
, reg
);
2935 static int wm8994_set_tristate(struct snd_soc_dai
*codec_dai
, int tristate
)
2937 struct snd_soc_codec
*codec
= codec_dai
->codec
;
2940 switch (codec_dai
->id
) {
2942 reg
= WM8994_AIF1_MASTER_SLAVE
;
2943 mask
= WM8994_AIF1_TRI
;
2946 reg
= WM8994_AIF2_MASTER_SLAVE
;
2947 mask
= WM8994_AIF2_TRI
;
2958 return snd_soc_update_bits(codec
, reg
, mask
, val
);
2961 static int wm8994_aif2_probe(struct snd_soc_dai
*dai
)
2963 struct snd_soc_codec
*codec
= dai
->codec
;
2965 /* Disable the pulls on the AIF if we're using it to save power. */
2966 snd_soc_update_bits(codec
, WM8994_GPIO_3
,
2967 WM8994_GPN_PU
| WM8994_GPN_PD
, 0);
2968 snd_soc_update_bits(codec
, WM8994_GPIO_4
,
2969 WM8994_GPN_PU
| WM8994_GPN_PD
, 0);
2970 snd_soc_update_bits(codec
, WM8994_GPIO_5
,
2971 WM8994_GPN_PU
| WM8994_GPN_PD
, 0);
2976 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2978 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2979 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2981 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops
= {
2982 .set_sysclk
= wm8994_set_dai_sysclk
,
2983 .set_fmt
= wm8994_set_dai_fmt
,
2984 .hw_params
= wm8994_hw_params
,
2985 .digital_mute
= wm8994_aif_mute
,
2986 .set_pll
= wm8994_set_fll
,
2987 .set_tristate
= wm8994_set_tristate
,
2990 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops
= {
2991 .set_sysclk
= wm8994_set_dai_sysclk
,
2992 .set_fmt
= wm8994_set_dai_fmt
,
2993 .hw_params
= wm8994_hw_params
,
2994 .digital_mute
= wm8994_aif_mute
,
2995 .set_pll
= wm8994_set_fll
,
2996 .set_tristate
= wm8994_set_tristate
,
2999 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops
= {
3000 .hw_params
= wm8994_aif3_hw_params
,
3003 static struct snd_soc_dai_driver wm8994_dai
[] = {
3005 .name
= "wm8994-aif1",
3008 .stream_name
= "AIF1 Playback",
3011 .rates
= WM8994_RATES
,
3012 .formats
= WM8994_FORMATS
,
3016 .stream_name
= "AIF1 Capture",
3019 .rates
= WM8994_RATES
,
3020 .formats
= WM8994_FORMATS
,
3023 .ops
= &wm8994_aif1_dai_ops
,
3026 .name
= "wm8994-aif2",
3029 .stream_name
= "AIF2 Playback",
3032 .rates
= WM8994_RATES
,
3033 .formats
= WM8994_FORMATS
,
3037 .stream_name
= "AIF2 Capture",
3040 .rates
= WM8994_RATES
,
3041 .formats
= WM8994_FORMATS
,
3044 .probe
= wm8994_aif2_probe
,
3045 .ops
= &wm8994_aif2_dai_ops
,
3048 .name
= "wm8994-aif3",
3051 .stream_name
= "AIF3 Playback",
3054 .rates
= WM8994_RATES
,
3055 .formats
= WM8994_FORMATS
,
3059 .stream_name
= "AIF3 Capture",
3062 .rates
= WM8994_RATES
,
3063 .formats
= WM8994_FORMATS
,
3066 .ops
= &wm8994_aif3_dai_ops
,
3071 static int wm8994_codec_suspend(struct snd_soc_codec
*codec
)
3073 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3076 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll
); i
++) {
3077 memcpy(&wm8994
->fll_suspend
[i
], &wm8994
->fll
[i
],
3078 sizeof(struct wm8994_fll_config
));
3079 ret
= _wm8994_set_fll(codec
, i
+ 1, 0, 0, 0);
3081 dev_warn(codec
->dev
, "Failed to stop FLL%d: %d\n",
3085 wm8994_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
3090 static int wm8994_codec_resume(struct snd_soc_codec
*codec
)
3092 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3093 struct wm8994
*control
= wm8994
->wm8994
;
3095 unsigned int val
, mask
;
3097 if (control
->revision
< 4) {
3098 /* force a HW read */
3099 ret
= regmap_read(control
->regmap
,
3100 WM8994_POWER_MANAGEMENT_5
, &val
);
3102 /* modify the cache only */
3103 codec
->cache_only
= 1;
3104 mask
= WM8994_DAC1R_ENA
| WM8994_DAC1L_ENA
|
3105 WM8994_DAC2R_ENA
| WM8994_DAC2L_ENA
;
3107 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
3109 codec
->cache_only
= 0;
3112 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll
); i
++) {
3113 if (!wm8994
->fll_suspend
[i
].out
)
3116 ret
= _wm8994_set_fll(codec
, i
+ 1,
3117 wm8994
->fll_suspend
[i
].src
,
3118 wm8994
->fll_suspend
[i
].in
,
3119 wm8994
->fll_suspend
[i
].out
);
3121 dev_warn(codec
->dev
, "Failed to restore FLL%d: %d\n",
3128 #define wm8994_codec_suspend NULL
3129 #define wm8994_codec_resume NULL
3132 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv
*wm8994
)
3134 struct snd_soc_codec
*codec
= wm8994
->hubs
.codec
;
3135 struct wm8994
*control
= wm8994
->wm8994
;
3136 struct wm8994_pdata
*pdata
= &control
->pdata
;
3137 struct snd_kcontrol_new controls
[] = {
3138 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3139 wm8994
->retune_mobile_enum
,
3140 wm8994_get_retune_mobile_enum
,
3141 wm8994_put_retune_mobile_enum
),
3142 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3143 wm8994
->retune_mobile_enum
,
3144 wm8994_get_retune_mobile_enum
,
3145 wm8994_put_retune_mobile_enum
),
3146 SOC_ENUM_EXT("AIF2 EQ Mode",
3147 wm8994
->retune_mobile_enum
,
3148 wm8994_get_retune_mobile_enum
,
3149 wm8994_put_retune_mobile_enum
),
3154 /* We need an array of texts for the enum API but the number
3155 * of texts is likely to be less than the number of
3156 * configurations due to the sample rate dependency of the
3157 * configurations. */
3158 wm8994
->num_retune_mobile_texts
= 0;
3159 wm8994
->retune_mobile_texts
= NULL
;
3160 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
3161 for (j
= 0; j
< wm8994
->num_retune_mobile_texts
; j
++) {
3162 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
3163 wm8994
->retune_mobile_texts
[j
]) == 0)
3167 if (j
!= wm8994
->num_retune_mobile_texts
)
3170 /* Expand the array... */
3171 t
= krealloc(wm8994
->retune_mobile_texts
,
3173 (wm8994
->num_retune_mobile_texts
+ 1),
3178 /* ...store the new entry... */
3179 t
[wm8994
->num_retune_mobile_texts
] =
3180 pdata
->retune_mobile_cfgs
[i
].name
;
3182 /* ...and remember the new version. */
3183 wm8994
->num_retune_mobile_texts
++;
3184 wm8994
->retune_mobile_texts
= t
;
3187 dev_dbg(codec
->dev
, "Allocated %d unique ReTune Mobile names\n",
3188 wm8994
->num_retune_mobile_texts
);
3190 wm8994
->retune_mobile_enum
.max
= wm8994
->num_retune_mobile_texts
;
3191 wm8994
->retune_mobile_enum
.texts
= wm8994
->retune_mobile_texts
;
3193 ret
= snd_soc_add_codec_controls(wm8994
->hubs
.codec
, controls
,
3194 ARRAY_SIZE(controls
));
3196 dev_err(wm8994
->hubs
.codec
->dev
,
3197 "Failed to add ReTune Mobile controls: %d\n", ret
);
3200 static void wm8994_handle_pdata(struct wm8994_priv
*wm8994
)
3202 struct snd_soc_codec
*codec
= wm8994
->hubs
.codec
;
3203 struct wm8994
*control
= wm8994
->wm8994
;
3204 struct wm8994_pdata
*pdata
= &control
->pdata
;
3210 wm_hubs_handle_analogue_pdata(codec
, pdata
->lineout1_diff
,
3211 pdata
->lineout2_diff
,
3218 pdata
->micbias1_lvl
,
3219 pdata
->micbias2_lvl
);
3221 dev_dbg(codec
->dev
, "%d DRC configurations\n", pdata
->num_drc_cfgs
);
3223 if (pdata
->num_drc_cfgs
) {
3224 struct snd_kcontrol_new controls
[] = {
3225 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994
->drc_enum
,
3226 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
3227 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994
->drc_enum
,
3228 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
3229 SOC_ENUM_EXT("AIF2DRC Mode", wm8994
->drc_enum
,
3230 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
3233 /* We need an array of texts for the enum API */
3234 wm8994
->drc_texts
= devm_kzalloc(wm8994
->hubs
.codec
->dev
,
3235 sizeof(char *) * pdata
->num_drc_cfgs
, GFP_KERNEL
);
3236 if (!wm8994
->drc_texts
) {
3237 dev_err(wm8994
->hubs
.codec
->dev
,
3238 "Failed to allocate %d DRC config texts\n",
3239 pdata
->num_drc_cfgs
);
3243 for (i
= 0; i
< pdata
->num_drc_cfgs
; i
++)
3244 wm8994
->drc_texts
[i
] = pdata
->drc_cfgs
[i
].name
;
3246 wm8994
->drc_enum
.max
= pdata
->num_drc_cfgs
;
3247 wm8994
->drc_enum
.texts
= wm8994
->drc_texts
;
3249 ret
= snd_soc_add_codec_controls(wm8994
->hubs
.codec
, controls
,
3250 ARRAY_SIZE(controls
));
3251 for (i
= 0; i
< WM8994_NUM_DRC
; i
++)
3252 wm8994_set_drc(codec
, i
);
3254 ret
= snd_soc_add_codec_controls(wm8994
->hubs
.codec
,
3255 wm8994_drc_controls
,
3256 ARRAY_SIZE(wm8994_drc_controls
));
3260 dev_err(wm8994
->hubs
.codec
->dev
,
3261 "Failed to add DRC mode controls: %d\n", ret
);
3264 dev_dbg(codec
->dev
, "%d ReTune Mobile configurations\n",
3265 pdata
->num_retune_mobile_cfgs
);
3267 if (pdata
->num_retune_mobile_cfgs
)
3268 wm8994_handle_retune_mobile_pdata(wm8994
);
3270 snd_soc_add_codec_controls(wm8994
->hubs
.codec
, wm8994_eq_controls
,
3271 ARRAY_SIZE(wm8994_eq_controls
));
3273 for (i
= 0; i
< ARRAY_SIZE(pdata
->micbias
); i
++) {
3274 if (pdata
->micbias
[i
]) {
3275 snd_soc_write(codec
, WM8958_MICBIAS1
+ i
,
3276 pdata
->micbias
[i
] & 0xffff);
3282 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3284 * @codec: WM8994 codec
3285 * @jack: jack to report detection events on
3286 * @micbias: microphone bias to detect on
3288 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3289 * being used to bring out signals to the processor then only platform
3290 * data configuration is needed for WM8994 and processor GPIOs should
3291 * be configured using snd_soc_jack_add_gpios() instead.
3293 * Configuration of detection levels is available via the micbias1_lvl
3294 * and micbias2_lvl platform data members.
3296 int wm8994_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
3299 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3300 struct wm8994_micdet
*micdet
;
3301 struct wm8994
*control
= wm8994
->wm8994
;
3304 if (control
->type
!= WM8994
) {
3305 dev_warn(codec
->dev
, "Not a WM8994\n");
3311 micdet
= &wm8994
->micdet
[0];
3313 ret
= snd_soc_dapm_force_enable_pin(&codec
->dapm
,
3316 ret
= snd_soc_dapm_disable_pin(&codec
->dapm
,
3320 micdet
= &wm8994
->micdet
[1];
3322 ret
= snd_soc_dapm_force_enable_pin(&codec
->dapm
,
3325 ret
= snd_soc_dapm_disable_pin(&codec
->dapm
,
3329 dev_warn(codec
->dev
, "Invalid MICBIAS %d\n", micbias
);
3334 dev_warn(codec
->dev
, "Failed to configure MICBIAS%d: %d\n",
3337 dev_dbg(codec
->dev
, "Configuring microphone detection on %d %p\n",
3340 /* Store the configuration */
3341 micdet
->jack
= jack
;
3342 micdet
->detecting
= true;
3344 /* If either of the jacks is set up then enable detection */
3345 if (wm8994
->micdet
[0].jack
|| wm8994
->micdet
[1].jack
)
3346 reg
= WM8994_MICD_ENA
;
3350 snd_soc_update_bits(codec
, WM8994_MICBIAS
, WM8994_MICD_ENA
, reg
);
3352 /* enable MICDET and MICSHRT deboune */
3353 snd_soc_update_bits(codec
, WM8994_IRQ_DEBOUNCE
,
3354 WM8994_MIC1_DET_DB_MASK
| WM8994_MIC1_SHRT_DB_MASK
|
3355 WM8994_MIC2_DET_DB_MASK
| WM8994_MIC2_SHRT_DB_MASK
,
3356 WM8994_MIC1_DET_DB
| WM8994_MIC1_SHRT_DB
);
3358 snd_soc_dapm_sync(&codec
->dapm
);
3362 EXPORT_SYMBOL_GPL(wm8994_mic_detect
);
3364 static void wm8994_mic_work(struct work_struct
*work
)
3366 struct wm8994_priv
*priv
= container_of(work
,
3369 struct regmap
*regmap
= priv
->wm8994
->regmap
;
3370 struct device
*dev
= priv
->wm8994
->dev
;
3375 pm_runtime_get_sync(dev
);
3377 ret
= regmap_read(regmap
, WM8994_INTERRUPT_RAW_STATUS_2
, ®
);
3379 dev_err(dev
, "Failed to read microphone status: %d\n",
3381 pm_runtime_put(dev
);
3385 dev_dbg(dev
, "Microphone status: %x\n", reg
);
3388 if (reg
& WM8994_MIC1_DET_STS
) {
3389 if (priv
->micdet
[0].detecting
)
3390 report
= SND_JACK_HEADSET
;
3392 if (reg
& WM8994_MIC1_SHRT_STS
) {
3393 if (priv
->micdet
[0].detecting
)
3394 report
= SND_JACK_HEADPHONE
;
3396 report
|= SND_JACK_BTN_0
;
3399 priv
->micdet
[0].detecting
= false;
3401 priv
->micdet
[0].detecting
= true;
3403 snd_soc_jack_report(priv
->micdet
[0].jack
, report
,
3404 SND_JACK_HEADSET
| SND_JACK_BTN_0
);
3407 if (reg
& WM8994_MIC2_DET_STS
) {
3408 if (priv
->micdet
[1].detecting
)
3409 report
= SND_JACK_HEADSET
;
3411 if (reg
& WM8994_MIC2_SHRT_STS
) {
3412 if (priv
->micdet
[1].detecting
)
3413 report
= SND_JACK_HEADPHONE
;
3415 report
|= SND_JACK_BTN_0
;
3418 priv
->micdet
[1].detecting
= false;
3420 priv
->micdet
[1].detecting
= true;
3422 snd_soc_jack_report(priv
->micdet
[1].jack
, report
,
3423 SND_JACK_HEADSET
| SND_JACK_BTN_0
);
3425 pm_runtime_put(dev
);
3428 static irqreturn_t
wm8994_mic_irq(int irq
, void *data
)
3430 struct wm8994_priv
*priv
= data
;
3431 struct snd_soc_codec
*codec
= priv
->hubs
.codec
;
3433 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3434 trace_snd_soc_jack_irq(dev_name(codec
->dev
));
3437 pm_wakeup_event(codec
->dev
, 300);
3439 schedule_delayed_work(&priv
->mic_work
, msecs_to_jiffies(250));
3444 static void wm1811_micd_stop(struct snd_soc_codec
*codec
)
3446 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3448 if (!wm8994
->jackdet
)
3451 mutex_lock(&wm8994
->accdet_lock
);
3453 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
, WM8958_MICD_ENA
, 0);
3455 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_JACK
);
3457 mutex_unlock(&wm8994
->accdet_lock
);
3459 if (wm8994
->wm8994
->pdata
.jd_ext_cap
)
3460 snd_soc_dapm_disable_pin(&codec
->dapm
,
3464 static void wm8958_button_det(struct snd_soc_codec
*codec
, u16 status
)
3466 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3471 report
|= SND_JACK_BTN_0
;
3474 report
|= SND_JACK_BTN_1
;
3477 report
|= SND_JACK_BTN_2
;
3480 report
|= SND_JACK_BTN_3
;
3483 report
|= SND_JACK_BTN_4
;
3486 report
|= SND_JACK_BTN_5
;
3488 snd_soc_jack_report(wm8994
->micdet
[0].jack
, report
,
3492 static void wm8958_mic_id(void *data
, u16 status
)
3494 struct snd_soc_codec
*codec
= data
;
3495 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3497 /* Either nothing present or just starting detection */
3498 if (!(status
& WM8958_MICD_STS
)) {
3499 /* If nothing present then clear our statuses */
3500 dev_dbg(codec
->dev
, "Detected open circuit\n");
3501 wm8994
->jack_mic
= false;
3502 wm8994
->mic_detecting
= true;
3504 wm1811_micd_stop(codec
);
3506 wm8958_micd_set_rate(codec
);
3508 snd_soc_jack_report(wm8994
->micdet
[0].jack
, 0,
3514 /* If the measurement is showing a high impedence we've got a
3517 if (status
& 0x600) {
3518 dev_dbg(codec
->dev
, "Detected microphone\n");
3520 wm8994
->mic_detecting
= false;
3521 wm8994
->jack_mic
= true;
3523 wm8958_micd_set_rate(codec
);
3525 snd_soc_jack_report(wm8994
->micdet
[0].jack
, SND_JACK_HEADSET
,
3530 if (status
& 0xfc) {
3531 dev_dbg(codec
->dev
, "Detected headphone\n");
3532 wm8994
->mic_detecting
= false;
3534 wm8958_micd_set_rate(codec
);
3536 /* If we have jackdet that will detect removal */
3537 wm1811_micd_stop(codec
);
3539 snd_soc_jack_report(wm8994
->micdet
[0].jack
, SND_JACK_HEADPHONE
,
3544 /* Deferred mic detection to allow for extra settling time */
3545 static void wm1811_mic_work(struct work_struct
*work
)
3547 struct wm8994_priv
*wm8994
= container_of(work
, struct wm8994_priv
,
3549 struct wm8994
*control
= wm8994
->wm8994
;
3550 struct snd_soc_codec
*codec
= wm8994
->hubs
.codec
;
3552 pm_runtime_get_sync(codec
->dev
);
3554 /* If required for an external cap force MICBIAS on */
3555 if (control
->pdata
.jd_ext_cap
) {
3556 snd_soc_dapm_force_enable_pin(&codec
->dapm
,
3558 snd_soc_dapm_sync(&codec
->dapm
);
3561 mutex_lock(&wm8994
->accdet_lock
);
3563 dev_dbg(codec
->dev
, "Starting mic detection\n");
3565 /* Use a user-supplied callback if we have one */
3566 if (wm8994
->micd_cb
) {
3567 wm8994
->micd_cb(wm8994
->micd_cb_data
);
3570 * Start off measument of microphone impedence to find out
3571 * what's actually there.
3573 wm8994
->mic_detecting
= true;
3574 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_MIC
);
3576 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3577 WM8958_MICD_ENA
, WM8958_MICD_ENA
);
3580 mutex_unlock(&wm8994
->accdet_lock
);
3582 pm_runtime_put(codec
->dev
);
3585 static irqreturn_t
wm1811_jackdet_irq(int irq
, void *data
)
3587 struct wm8994_priv
*wm8994
= data
;
3588 struct wm8994
*control
= wm8994
->wm8994
;
3589 struct snd_soc_codec
*codec
= wm8994
->hubs
.codec
;
3593 pm_runtime_get_sync(codec
->dev
);
3595 mutex_lock(&wm8994
->accdet_lock
);
3597 reg
= snd_soc_read(codec
, WM1811_JACKDET_CTRL
);
3599 dev_err(codec
->dev
, "Failed to read jack status: %d\n", reg
);
3600 mutex_unlock(&wm8994
->accdet_lock
);
3601 pm_runtime_put(codec
->dev
);
3605 dev_dbg(codec
->dev
, "JACKDET %x\n", reg
);
3607 present
= reg
& WM1811_JACKDET_LVL
;
3610 dev_dbg(codec
->dev
, "Jack detected\n");
3612 wm8958_micd_set_rate(codec
);
3614 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
3615 WM8958_MICB2_DISCH
, 0);
3617 /* Disable debounce while inserted */
3618 snd_soc_update_bits(codec
, WM1811_JACKDET_CTRL
,
3619 WM1811_JACKDET_DB
, 0);
3621 delay
= control
->pdata
.micdet_delay
;
3622 schedule_delayed_work(&wm8994
->mic_work
,
3623 msecs_to_jiffies(delay
));
3625 dev_dbg(codec
->dev
, "Jack not detected\n");
3627 cancel_delayed_work_sync(&wm8994
->mic_work
);
3629 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
3630 WM8958_MICB2_DISCH
, WM8958_MICB2_DISCH
);
3632 /* Enable debounce while removed */
3633 snd_soc_update_bits(codec
, WM1811_JACKDET_CTRL
,
3634 WM1811_JACKDET_DB
, WM1811_JACKDET_DB
);
3636 wm8994
->mic_detecting
= false;
3637 wm8994
->jack_mic
= false;
3638 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3639 WM8958_MICD_ENA
, 0);
3640 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_JACK
);
3643 mutex_unlock(&wm8994
->accdet_lock
);
3645 /* Turn off MICBIAS if it was on for an external cap */
3646 if (control
->pdata
.jd_ext_cap
&& !present
)
3647 snd_soc_dapm_disable_pin(&codec
->dapm
, "MICBIAS2");
3650 snd_soc_jack_report(wm8994
->micdet
[0].jack
,
3651 SND_JACK_MECHANICAL
, SND_JACK_MECHANICAL
);
3653 snd_soc_jack_report(wm8994
->micdet
[0].jack
, 0,
3654 SND_JACK_MECHANICAL
| SND_JACK_HEADSET
|
3657 /* Since we only report deltas force an update, ensures we
3658 * avoid bootstrapping issues with the core. */
3659 snd_soc_jack_report(wm8994
->micdet
[0].jack
, 0, 0);
3661 pm_runtime_put(codec
->dev
);
3665 static void wm1811_jackdet_bootstrap(struct work_struct
*work
)
3667 struct wm8994_priv
*wm8994
= container_of(work
,
3669 jackdet_bootstrap
.work
);
3670 wm1811_jackdet_irq(0, wm8994
);
3674 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3676 * @codec: WM8958 codec
3677 * @jack: jack to report detection events on
3679 * Enable microphone detection functionality for the WM8958. By
3680 * default simple detection which supports the detection of up to 6
3681 * buttons plus video and microphone functionality is supported.
3683 * The WM8958 has an advanced jack detection facility which is able to
3684 * support complex accessory detection, especially when used in
3685 * conjunction with external circuitry. In order to provide maximum
3686 * flexiblity a callback is provided which allows a completely custom
3687 * detection algorithm.
3689 int wm8958_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
3690 wm1811_micdet_cb det_cb
, void *det_cb_data
,
3691 wm1811_mic_id_cb id_cb
, void *id_cb_data
)
3693 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3694 struct wm8994
*control
= wm8994
->wm8994
;
3697 switch (control
->type
) {
3706 snd_soc_dapm_force_enable_pin(&codec
->dapm
, "CLK_SYS");
3707 snd_soc_dapm_sync(&codec
->dapm
);
3709 wm8994
->micdet
[0].jack
= jack
;
3712 wm8994
->micd_cb
= det_cb
;
3713 wm8994
->micd_cb_data
= det_cb_data
;
3715 wm8994
->mic_detecting
= true;
3716 wm8994
->jack_mic
= false;
3720 wm8994
->mic_id_cb
= id_cb
;
3721 wm8994
->mic_id_cb_data
= id_cb_data
;
3723 wm8994
->mic_id_cb
= wm8958_mic_id
;
3724 wm8994
->mic_id_cb_data
= codec
;
3727 wm8958_micd_set_rate(codec
);
3729 /* Detect microphones and short circuits by default */
3730 if (control
->pdata
.micd_lvl_sel
)
3731 micd_lvl_sel
= control
->pdata
.micd_lvl_sel
;
3733 micd_lvl_sel
= 0x41;
3735 wm8994
->btn_mask
= SND_JACK_BTN_0
| SND_JACK_BTN_1
|
3736 SND_JACK_BTN_2
| SND_JACK_BTN_3
|
3737 SND_JACK_BTN_4
| SND_JACK_BTN_5
;
3739 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_2
,
3740 WM8958_MICD_LVL_SEL_MASK
, micd_lvl_sel
);
3742 WARN_ON(codec
->dapm
.bias_level
> SND_SOC_BIAS_STANDBY
);
3745 * If we can use jack detection start off with that,
3746 * otherwise jump straight to microphone detection.
3748 if (wm8994
->jackdet
) {
3749 /* Disable debounce for the initial detect */
3750 snd_soc_update_bits(codec
, WM1811_JACKDET_CTRL
,
3751 WM1811_JACKDET_DB
, 0);
3753 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
3755 WM8958_MICB2_DISCH
);
3756 snd_soc_update_bits(codec
, WM8994_LDO_1
,
3757 WM8994_LDO1_DISCH
, 0);
3758 wm1811_jackdet_set_mode(codec
,
3759 WM1811_JACKDET_MODE_JACK
);
3761 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3762 WM8958_MICD_ENA
, WM8958_MICD_ENA
);
3766 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3767 WM8958_MICD_ENA
, 0);
3768 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_NONE
);
3769 snd_soc_dapm_disable_pin(&codec
->dapm
, "CLK_SYS");
3770 snd_soc_dapm_sync(&codec
->dapm
);
3775 EXPORT_SYMBOL_GPL(wm8958_mic_detect
);
3777 static irqreturn_t
wm8958_mic_irq(int irq
, void *data
)
3779 struct wm8994_priv
*wm8994
= data
;
3780 struct snd_soc_codec
*codec
= wm8994
->hubs
.codec
;
3781 int reg
, count
, ret
;
3784 * Jack detection may have detected a removal simulataneously
3785 * with an update of the MICDET status; if so it will have
3786 * stopped detection and we can ignore this interrupt.
3788 if (!(snd_soc_read(codec
, WM8958_MIC_DETECT_1
) & WM8958_MICD_ENA
))
3791 pm_runtime_get_sync(codec
->dev
);
3793 /* We may occasionally read a detection without an impedence
3794 * range being provided - if that happens loop again.
3798 reg
= snd_soc_read(codec
, WM8958_MIC_DETECT_3
);
3801 "Failed to read mic detect status: %d\n",
3803 pm_runtime_put(codec
->dev
);
3807 if (!(reg
& WM8958_MICD_VALID
)) {
3808 dev_dbg(codec
->dev
, "Mic detect data not valid\n");
3812 if (!(reg
& WM8958_MICD_STS
) || (reg
& WM8958_MICD_LVL_MASK
))
3819 dev_warn(codec
->dev
, "No impedance range reported for jack\n");
3821 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3822 trace_snd_soc_jack_irq(dev_name(codec
->dev
));
3825 /* Avoid a transient report when the accessory is being removed */
3826 if (wm8994
->jackdet
) {
3827 ret
= snd_soc_read(codec
, WM1811_JACKDET_CTRL
);
3829 dev_err(codec
->dev
, "Failed to read jack status: %d\n",
3831 } else if (!(ret
& WM1811_JACKDET_LVL
)) {
3832 dev_dbg(codec
->dev
, "Ignoring removed jack\n");
3837 if (wm8994
->mic_detecting
)
3838 wm8994
->mic_id_cb(wm8994
->mic_id_cb_data
, reg
);
3840 wm8958_button_det(codec
, reg
);
3843 pm_runtime_put(codec
->dev
);
3847 static irqreturn_t
wm8994_fifo_error(int irq
, void *data
)
3849 struct snd_soc_codec
*codec
= data
;
3851 dev_err(codec
->dev
, "FIFO error\n");
3856 static irqreturn_t
wm8994_temp_warn(int irq
, void *data
)
3858 struct snd_soc_codec
*codec
= data
;
3860 dev_err(codec
->dev
, "Thermal warning\n");
3865 static irqreturn_t
wm8994_temp_shut(int irq
, void *data
)
3867 struct snd_soc_codec
*codec
= data
;
3869 dev_crit(codec
->dev
, "Thermal shutdown\n");
3874 static int wm8994_codec_probe(struct snd_soc_codec
*codec
)
3876 struct wm8994
*control
= dev_get_drvdata(codec
->dev
->parent
);
3877 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3878 struct snd_soc_dapm_context
*dapm
= &codec
->dapm
;
3882 wm8994
->hubs
.codec
= codec
;
3883 codec
->control_data
= control
->regmap
;
3885 snd_soc_codec_set_cache_io(codec
, 16, 16, SND_SOC_REGMAP
);
3887 mutex_init(&wm8994
->accdet_lock
);
3888 INIT_DELAYED_WORK(&wm8994
->jackdet_bootstrap
,
3889 wm1811_jackdet_bootstrap
);
3891 switch (control
->type
) {
3893 INIT_DELAYED_WORK(&wm8994
->mic_work
, wm8994_mic_work
);
3896 INIT_DELAYED_WORK(&wm8994
->mic_work
, wm1811_mic_work
);
3902 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++)
3903 init_completion(&wm8994
->fll_locked
[i
]);
3905 wm8994
->micdet_irq
= control
->pdata
.micdet_irq
;
3907 pm_runtime_enable(codec
->dev
);
3908 pm_runtime_idle(codec
->dev
);
3910 /* By default use idle_bias_off, will override for WM8994 */
3911 codec
->dapm
.idle_bias_off
= 1;
3913 /* Set revision-specific configuration */
3914 switch (control
->type
) {
3916 /* Single ended line outputs should have VMID on. */
3917 if (!control
->pdata
.lineout1_diff
||
3918 !control
->pdata
.lineout2_diff
)
3919 codec
->dapm
.idle_bias_off
= 0;
3921 switch (control
->revision
) {
3924 wm8994
->hubs
.dcs_codes_l
= -5;
3925 wm8994
->hubs
.dcs_codes_r
= -5;
3926 wm8994
->hubs
.hp_startup_mode
= 1;
3927 wm8994
->hubs
.dcs_readback_mode
= 1;
3928 wm8994
->hubs
.series_startup
= 1;
3931 wm8994
->hubs
.dcs_readback_mode
= 2;
3937 wm8994
->hubs
.dcs_readback_mode
= 1;
3938 wm8994
->hubs
.hp_startup_mode
= 1;
3940 switch (control
->revision
) {
3944 wm8994
->fll_byp
= true;
3950 wm8994
->hubs
.dcs_readback_mode
= 2;
3951 wm8994
->hubs
.no_series_update
= 1;
3952 wm8994
->hubs
.hp_startup_mode
= 1;
3953 wm8994
->hubs
.no_cache_dac_hp_direct
= true;
3954 wm8994
->fll_byp
= true;
3956 wm8994
->hubs
.dcs_codes_l
= -9;
3957 wm8994
->hubs
.dcs_codes_r
= -7;
3959 snd_soc_update_bits(codec
, WM8994_ANALOGUE_HP_1
,
3960 WM1811_HPOUT1_ATTN
, WM1811_HPOUT1_ATTN
);
3967 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_FIFOS_ERR
,
3968 wm8994_fifo_error
, "FIFO error", codec
);
3969 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_WARN
,
3970 wm8994_temp_warn
, "Thermal warning", codec
);
3971 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_SHUT
,
3972 wm8994_temp_shut
, "Thermal shutdown", codec
);
3974 ret
= wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_DCS_DONE
,
3975 wm_hubs_dcs_done
, "DC servo done",
3978 wm8994
->hubs
.dcs_done_irq
= true;
3980 switch (control
->type
) {
3982 if (wm8994
->micdet_irq
) {
3983 ret
= request_threaded_irq(wm8994
->micdet_irq
, NULL
,
3985 IRQF_TRIGGER_RISING
,
3989 dev_warn(codec
->dev
,
3990 "Failed to request Mic1 detect IRQ: %d\n",
3994 ret
= wm8994_request_irq(wm8994
->wm8994
,
3995 WM8994_IRQ_MIC1_SHRT
,
3996 wm8994_mic_irq
, "Mic 1 short",
3999 dev_warn(codec
->dev
,
4000 "Failed to request Mic1 short IRQ: %d\n",
4003 ret
= wm8994_request_irq(wm8994
->wm8994
,
4004 WM8994_IRQ_MIC2_DET
,
4005 wm8994_mic_irq
, "Mic 2 detect",
4008 dev_warn(codec
->dev
,
4009 "Failed to request Mic2 detect IRQ: %d\n",
4012 ret
= wm8994_request_irq(wm8994
->wm8994
,
4013 WM8994_IRQ_MIC2_SHRT
,
4014 wm8994_mic_irq
, "Mic 2 short",
4017 dev_warn(codec
->dev
,
4018 "Failed to request Mic2 short IRQ: %d\n",
4024 if (wm8994
->micdet_irq
) {
4025 ret
= request_threaded_irq(wm8994
->micdet_irq
, NULL
,
4027 IRQF_TRIGGER_RISING
,
4031 dev_warn(codec
->dev
,
4032 "Failed to request Mic detect IRQ: %d\n",
4035 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_DET
,
4036 wm8958_mic_irq
, "Mic detect",
4041 switch (control
->type
) {
4043 if (control
->cust_id
> 1 || control
->revision
> 1) {
4044 ret
= wm8994_request_irq(wm8994
->wm8994
,
4046 wm1811_jackdet_irq
, "JACKDET",
4049 wm8994
->jackdet
= true;
4056 wm8994
->fll_locked_irq
= true;
4057 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++) {
4058 ret
= wm8994_request_irq(wm8994
->wm8994
,
4059 WM8994_IRQ_FLL1_LOCK
+ i
,
4060 wm8994_fll_locked_irq
, "FLL lock",
4061 &wm8994
->fll_locked
[i
]);
4063 wm8994
->fll_locked_irq
= false;
4066 /* Make sure we can read from the GPIOs if they're inputs */
4067 pm_runtime_get_sync(codec
->dev
);
4069 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
4070 * configured on init - if a system wants to do this dynamically
4071 * at runtime we can deal with that then.
4073 ret
= regmap_read(control
->regmap
, WM8994_GPIO_1
, ®
);
4075 dev_err(codec
->dev
, "Failed to read GPIO1 state: %d\n", ret
);
4078 if ((reg
& WM8994_GPN_FN_MASK
) != WM8994_GP_FN_PIN_SPECIFIC
) {
4079 wm8994
->lrclk_shared
[0] = 1;
4080 wm8994_dai
[0].symmetric_rates
= 1;
4082 wm8994
->lrclk_shared
[0] = 0;
4085 ret
= regmap_read(control
->regmap
, WM8994_GPIO_6
, ®
);
4087 dev_err(codec
->dev
, "Failed to read GPIO6 state: %d\n", ret
);
4090 if ((reg
& WM8994_GPN_FN_MASK
) != WM8994_GP_FN_PIN_SPECIFIC
) {
4091 wm8994
->lrclk_shared
[1] = 1;
4092 wm8994_dai
[1].symmetric_rates
= 1;
4094 wm8994
->lrclk_shared
[1] = 0;
4097 pm_runtime_put(codec
->dev
);
4099 /* Latch volume update bits */
4100 for (i
= 0; i
< ARRAY_SIZE(wm8994_vu_bits
); i
++)
4101 snd_soc_update_bits(codec
, wm8994_vu_bits
[i
].reg
,
4102 wm8994_vu_bits
[i
].mask
,
4103 wm8994_vu_bits
[i
].mask
);
4105 /* Set the low bit of the 3D stereo depth so TLV matches */
4106 snd_soc_update_bits(codec
, WM8994_AIF1_DAC1_FILTERS_2
,
4107 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT
,
4108 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT
);
4109 snd_soc_update_bits(codec
, WM8994_AIF1_DAC2_FILTERS_2
,
4110 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT
,
4111 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT
);
4112 snd_soc_update_bits(codec
, WM8994_AIF2_DAC_FILTERS_2
,
4113 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT
,
4114 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT
);
4116 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
4117 * use this; it only affects behaviour on idle TDM clock
4119 switch (control
->type
) {
4122 snd_soc_update_bits(codec
, WM8994_AIF1_CONTROL_1
,
4123 WM8994_AIF1ADC_TDM
, WM8994_AIF1ADC_TDM
);
4129 /* Put MICBIAS into bypass mode by default on newer devices */
4130 switch (control
->type
) {
4133 snd_soc_update_bits(codec
, WM8958_MICBIAS1
,
4134 WM8958_MICB1_MODE
, WM8958_MICB1_MODE
);
4135 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
4136 WM8958_MICB2_MODE
, WM8958_MICB2_MODE
);
4142 wm8994
->hubs
.check_class_w_digital
= wm8994_check_class_w_digital
;
4143 wm_hubs_update_class_w(codec
);
4145 wm8994_handle_pdata(wm8994
);
4147 wm_hubs_add_analogue_controls(codec
);
4148 snd_soc_add_codec_controls(codec
, wm8994_snd_controls
,
4149 ARRAY_SIZE(wm8994_snd_controls
));
4150 snd_soc_dapm_new_controls(dapm
, wm8994_dapm_widgets
,
4151 ARRAY_SIZE(wm8994_dapm_widgets
));
4153 switch (control
->type
) {
4155 snd_soc_dapm_new_controls(dapm
, wm8994_specific_dapm_widgets
,
4156 ARRAY_SIZE(wm8994_specific_dapm_widgets
));
4157 if (control
->revision
< 4) {
4158 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_revd_widgets
,
4159 ARRAY_SIZE(wm8994_lateclk_revd_widgets
));
4160 snd_soc_dapm_new_controls(dapm
, wm8994_adc_revd_widgets
,
4161 ARRAY_SIZE(wm8994_adc_revd_widgets
));
4162 snd_soc_dapm_new_controls(dapm
, wm8994_dac_revd_widgets
,
4163 ARRAY_SIZE(wm8994_dac_revd_widgets
));
4165 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_widgets
,
4166 ARRAY_SIZE(wm8994_lateclk_widgets
));
4167 snd_soc_dapm_new_controls(dapm
, wm8994_adc_widgets
,
4168 ARRAY_SIZE(wm8994_adc_widgets
));
4169 snd_soc_dapm_new_controls(dapm
, wm8994_dac_widgets
,
4170 ARRAY_SIZE(wm8994_dac_widgets
));
4174 snd_soc_add_codec_controls(codec
, wm8958_snd_controls
,
4175 ARRAY_SIZE(wm8958_snd_controls
));
4176 snd_soc_dapm_new_controls(dapm
, wm8958_dapm_widgets
,
4177 ARRAY_SIZE(wm8958_dapm_widgets
));
4178 if (control
->revision
< 1) {
4179 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_revd_widgets
,
4180 ARRAY_SIZE(wm8994_lateclk_revd_widgets
));
4181 snd_soc_dapm_new_controls(dapm
, wm8994_adc_revd_widgets
,
4182 ARRAY_SIZE(wm8994_adc_revd_widgets
));
4183 snd_soc_dapm_new_controls(dapm
, wm8994_dac_revd_widgets
,
4184 ARRAY_SIZE(wm8994_dac_revd_widgets
));
4186 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_widgets
,
4187 ARRAY_SIZE(wm8994_lateclk_widgets
));
4188 snd_soc_dapm_new_controls(dapm
, wm8994_adc_widgets
,
4189 ARRAY_SIZE(wm8994_adc_widgets
));
4190 snd_soc_dapm_new_controls(dapm
, wm8994_dac_widgets
,
4191 ARRAY_SIZE(wm8994_dac_widgets
));
4196 snd_soc_add_codec_controls(codec
, wm8958_snd_controls
,
4197 ARRAY_SIZE(wm8958_snd_controls
));
4198 snd_soc_dapm_new_controls(dapm
, wm8958_dapm_widgets
,
4199 ARRAY_SIZE(wm8958_dapm_widgets
));
4200 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_widgets
,
4201 ARRAY_SIZE(wm8994_lateclk_widgets
));
4202 snd_soc_dapm_new_controls(dapm
, wm8994_adc_widgets
,
4203 ARRAY_SIZE(wm8994_adc_widgets
));
4204 snd_soc_dapm_new_controls(dapm
, wm8994_dac_widgets
,
4205 ARRAY_SIZE(wm8994_dac_widgets
));
4209 wm_hubs_add_analogue_routes(codec
, 0, 0);
4210 snd_soc_dapm_add_routes(dapm
, intercon
, ARRAY_SIZE(intercon
));
4212 switch (control
->type
) {
4214 snd_soc_dapm_add_routes(dapm
, wm8994_intercon
,
4215 ARRAY_SIZE(wm8994_intercon
));
4217 if (control
->revision
< 4) {
4218 snd_soc_dapm_add_routes(dapm
, wm8994_revd_intercon
,
4219 ARRAY_SIZE(wm8994_revd_intercon
));
4220 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_revd_intercon
,
4221 ARRAY_SIZE(wm8994_lateclk_revd_intercon
));
4223 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_intercon
,
4224 ARRAY_SIZE(wm8994_lateclk_intercon
));
4228 if (control
->revision
< 1) {
4229 snd_soc_dapm_add_routes(dapm
, wm8994_intercon
,
4230 ARRAY_SIZE(wm8994_intercon
));
4231 snd_soc_dapm_add_routes(dapm
, wm8994_revd_intercon
,
4232 ARRAY_SIZE(wm8994_revd_intercon
));
4233 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_revd_intercon
,
4234 ARRAY_SIZE(wm8994_lateclk_revd_intercon
));
4236 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_intercon
,
4237 ARRAY_SIZE(wm8994_lateclk_intercon
));
4238 snd_soc_dapm_add_routes(dapm
, wm8958_intercon
,
4239 ARRAY_SIZE(wm8958_intercon
));
4242 wm8958_dsp2_init(codec
);
4245 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_intercon
,
4246 ARRAY_SIZE(wm8994_lateclk_intercon
));
4247 snd_soc_dapm_add_routes(dapm
, wm8958_intercon
,
4248 ARRAY_SIZE(wm8958_intercon
));
4255 if (wm8994
->jackdet
)
4256 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_GPIO(6), wm8994
);
4257 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC2_SHRT
, wm8994
);
4258 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC2_DET
, wm8994
);
4259 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_SHRT
, wm8994
);
4260 if (wm8994
->micdet_irq
)
4261 free_irq(wm8994
->micdet_irq
, wm8994
);
4262 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++)
4263 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FLL1_LOCK
+ i
,
4264 &wm8994
->fll_locked
[i
]);
4265 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_DCS_DONE
,
4267 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FIFOS_ERR
, codec
);
4268 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_SHUT
, codec
);
4269 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_WARN
, codec
);
4274 static int wm8994_codec_remove(struct snd_soc_codec
*codec
)
4276 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
4277 struct wm8994
*control
= wm8994
->wm8994
;
4280 wm8994_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
4282 pm_runtime_disable(codec
->dev
);
4284 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++)
4285 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FLL1_LOCK
+ i
,
4286 &wm8994
->fll_locked
[i
]);
4288 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_DCS_DONE
,
4290 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FIFOS_ERR
, codec
);
4291 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_SHUT
, codec
);
4292 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_WARN
, codec
);
4294 if (wm8994
->jackdet
)
4295 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_GPIO(6), wm8994
);
4297 switch (control
->type
) {
4299 if (wm8994
->micdet_irq
)
4300 free_irq(wm8994
->micdet_irq
, wm8994
);
4301 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC2_DET
,
4303 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_SHRT
,
4305 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_DET
,
4311 if (wm8994
->micdet_irq
)
4312 free_irq(wm8994
->micdet_irq
, wm8994
);
4315 release_firmware(wm8994
->mbc
);
4316 release_firmware(wm8994
->mbc_vss
);
4317 release_firmware(wm8994
->enh_eq
);
4318 kfree(wm8994
->retune_mobile_texts
);
4322 static struct snd_soc_codec_driver soc_codec_dev_wm8994
= {
4323 .probe
= wm8994_codec_probe
,
4324 .remove
= wm8994_codec_remove
,
4325 .suspend
= wm8994_codec_suspend
,
4326 .resume
= wm8994_codec_resume
,
4327 .set_bias_level
= wm8994_set_bias_level
,
4330 static int wm8994_probe(struct platform_device
*pdev
)
4332 struct wm8994_priv
*wm8994
;
4334 wm8994
= devm_kzalloc(&pdev
->dev
, sizeof(struct wm8994_priv
),
4338 platform_set_drvdata(pdev
, wm8994
);
4340 wm8994
->wm8994
= dev_get_drvdata(pdev
->dev
.parent
);
4342 return snd_soc_register_codec(&pdev
->dev
, &soc_codec_dev_wm8994
,
4343 wm8994_dai
, ARRAY_SIZE(wm8994_dai
));
4346 static int wm8994_remove(struct platform_device
*pdev
)
4348 snd_soc_unregister_codec(&pdev
->dev
);
4352 #ifdef CONFIG_PM_SLEEP
4353 static int wm8994_suspend(struct device
*dev
)
4355 struct wm8994_priv
*wm8994
= dev_get_drvdata(dev
);
4357 /* Drop down to power saving mode when system is suspended */
4358 if (wm8994
->jackdet
&& !wm8994
->active_refcount
)
4359 regmap_update_bits(wm8994
->wm8994
->regmap
, WM8994_ANTIPOP_2
,
4360 WM1811_JACKDET_MODE_MASK
,
4361 wm8994
->jackdet_mode
);
4366 static int wm8994_resume(struct device
*dev
)
4368 struct wm8994_priv
*wm8994
= dev_get_drvdata(dev
);
4370 if (wm8994
->jackdet
&& wm8994
->jackdet_mode
)
4371 regmap_update_bits(wm8994
->wm8994
->regmap
, WM8994_ANTIPOP_2
,
4372 WM1811_JACKDET_MODE_MASK
,
4373 WM1811_JACKDET_MODE_AUDIO
);
4379 static const struct dev_pm_ops wm8994_pm_ops
= {
4380 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend
, wm8994_resume
)
4383 static struct platform_driver wm8994_codec_driver
= {
4385 .name
= "wm8994-codec",
4386 .owner
= THIS_MODULE
,
4387 .pm
= &wm8994_pm_ops
,
4389 .probe
= wm8994_probe
,
4390 .remove
= wm8994_remove
,
4393 module_platform_driver(wm8994_codec_driver
);
4395 MODULE_DESCRIPTION("ASoC WM8994 driver");
4396 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4397 MODULE_LICENSE("GPL");
4398 MODULE_ALIAS("platform:wm8994-codec");