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ASoC: Remove ASoC-specific WM8994 I/O code
[deliverable/linux.git] / sound / soc / codecs / wm8994.c
1 /*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/jack.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <trace/events/asoc.h>
32
33 #include <linux/mfd/wm8994/core.h>
34 #include <linux/mfd/wm8994/registers.h>
35 #include <linux/mfd/wm8994/pdata.h>
36 #include <linux/mfd/wm8994/gpio.h>
37
38 #include "wm8994.h"
39 #include "wm_hubs.h"
40
41 #define WM1811_JACKDET_MODE_NONE 0x0000
42 #define WM1811_JACKDET_MODE_JACK 0x0100
43 #define WM1811_JACKDET_MODE_MIC 0x0080
44 #define WM1811_JACKDET_MODE_AUDIO 0x0180
45
46 #define WM8994_NUM_DRC 3
47 #define WM8994_NUM_EQ 3
48
49 static int wm8994_drc_base[] = {
50 WM8994_AIF1_DRC1_1,
51 WM8994_AIF1_DRC2_1,
52 WM8994_AIF2_DRC_1,
53 };
54
55 static int wm8994_retune_mobile_base[] = {
56 WM8994_AIF1_DAC1_EQ_GAINS_1,
57 WM8994_AIF1_DAC2_EQ_GAINS_1,
58 WM8994_AIF2_EQ_GAINS_1,
59 };
60
61 static void wm8958_default_micdet(u16 status, void *data);
62
63 static const struct wm8958_micd_rate micdet_rates[] = {
64 { 32768, true, 1, 4 },
65 { 32768, false, 1, 1 },
66 { 44100 * 256, true, 7, 10 },
67 { 44100 * 256, false, 7, 10 },
68 };
69
70 static const struct wm8958_micd_rate jackdet_rates[] = {
71 { 32768, true, 0, 1 },
72 { 32768, false, 0, 1 },
73 { 44100 * 256, true, 7, 10 },
74 { 44100 * 256, false, 7, 10 },
75 };
76
77 static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
78 {
79 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
80 int best, i, sysclk, val;
81 bool idle;
82 const struct wm8958_micd_rate *rates;
83 int num_rates;
84
85 if (wm8994->jack_cb != wm8958_default_micdet)
86 return;
87
88 idle = !wm8994->jack_mic;
89
90 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
91 if (sysclk & WM8994_SYSCLK_SRC)
92 sysclk = wm8994->aifclk[1];
93 else
94 sysclk = wm8994->aifclk[0];
95
96 if (wm8994->pdata && wm8994->pdata->micd_rates) {
97 rates = wm8994->pdata->micd_rates;
98 num_rates = wm8994->pdata->num_micd_rates;
99 } else if (wm8994->jackdet) {
100 rates = jackdet_rates;
101 num_rates = ARRAY_SIZE(jackdet_rates);
102 } else {
103 rates = micdet_rates;
104 num_rates = ARRAY_SIZE(micdet_rates);
105 }
106
107 best = 0;
108 for (i = 0; i < num_rates; i++) {
109 if (rates[i].idle != idle)
110 continue;
111 if (abs(rates[i].sysclk - sysclk) <
112 abs(rates[best].sysclk - sysclk))
113 best = i;
114 else if (rates[best].idle != idle)
115 best = i;
116 }
117
118 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
119 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
120
121 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
122 WM8958_MICD_BIAS_STARTTIME_MASK |
123 WM8958_MICD_RATE_MASK, val);
124 }
125
126 static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg)
127 {
128 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
129 struct wm8994 *control = wm8994->wm8994;
130
131 switch (reg) {
132 case WM8994_GPIO_1:
133 case WM8994_GPIO_2:
134 case WM8994_GPIO_3:
135 case WM8994_GPIO_4:
136 case WM8994_GPIO_5:
137 case WM8994_GPIO_6:
138 case WM8994_GPIO_7:
139 case WM8994_GPIO_8:
140 case WM8994_GPIO_9:
141 case WM8994_GPIO_10:
142 case WM8994_GPIO_11:
143 case WM8994_INTERRUPT_STATUS_1:
144 case WM8994_INTERRUPT_STATUS_2:
145 case WM8994_INTERRUPT_RAW_STATUS_2:
146 return 1;
147
148 case WM8958_DSP2_PROGRAM:
149 case WM8958_DSP2_CONFIG:
150 case WM8958_DSP2_EXECCONTROL:
151 if (control->type == WM8958)
152 return 1;
153 else
154 return 0;
155
156 default:
157 break;
158 }
159
160 if (reg >= WM8994_CACHE_SIZE)
161 return 0;
162 return wm8994_access_masks[reg].readable != 0;
163 }
164
165 static int wm8994_volatile(struct snd_soc_codec *codec, unsigned int reg)
166 {
167 if (reg >= WM8994_CACHE_SIZE)
168 return 1;
169
170 switch (reg) {
171 case WM8994_SOFTWARE_RESET:
172 case WM8994_CHIP_REVISION:
173 case WM8994_DC_SERVO_1:
174 case WM8994_DC_SERVO_READBACK:
175 case WM8994_RATE_STATUS:
176 case WM8994_LDO_1:
177 case WM8994_LDO_2:
178 case WM8958_DSP2_EXECCONTROL:
179 case WM8958_MIC_DETECT_3:
180 case WM8994_DC_SERVO_4E:
181 return 1;
182 default:
183 return 0;
184 }
185 }
186
187 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
188 {
189 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
190 int rate;
191 int reg1 = 0;
192 int offset;
193
194 if (aif)
195 offset = 4;
196 else
197 offset = 0;
198
199 switch (wm8994->sysclk[aif]) {
200 case WM8994_SYSCLK_MCLK1:
201 rate = wm8994->mclk[0];
202 break;
203
204 case WM8994_SYSCLK_MCLK2:
205 reg1 |= 0x8;
206 rate = wm8994->mclk[1];
207 break;
208
209 case WM8994_SYSCLK_FLL1:
210 reg1 |= 0x10;
211 rate = wm8994->fll[0].out;
212 break;
213
214 case WM8994_SYSCLK_FLL2:
215 reg1 |= 0x18;
216 rate = wm8994->fll[1].out;
217 break;
218
219 default:
220 return -EINVAL;
221 }
222
223 if (rate >= 13500000) {
224 rate /= 2;
225 reg1 |= WM8994_AIF1CLK_DIV;
226
227 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
228 aif + 1, rate);
229 }
230
231 wm8994->aifclk[aif] = rate;
232
233 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
234 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
235 reg1);
236
237 return 0;
238 }
239
240 static int configure_clock(struct snd_soc_codec *codec)
241 {
242 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
243 int change, new;
244
245 /* Bring up the AIF clocks first */
246 configure_aif_clock(codec, 0);
247 configure_aif_clock(codec, 1);
248
249 /* Then switch CLK_SYS over to the higher of them; a change
250 * can only happen as a result of a clocking change which can
251 * only be made outside of DAPM so we can safely redo the
252 * clocking.
253 */
254
255 /* If they're equal it doesn't matter which is used */
256 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
257 wm8958_micd_set_rate(codec);
258 return 0;
259 }
260
261 if (wm8994->aifclk[0] < wm8994->aifclk[1])
262 new = WM8994_SYSCLK_SRC;
263 else
264 new = 0;
265
266 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
267 WM8994_SYSCLK_SRC, new);
268 if (change)
269 snd_soc_dapm_sync(&codec->dapm);
270
271 wm8958_micd_set_rate(codec);
272
273 return 0;
274 }
275
276 static int check_clk_sys(struct snd_soc_dapm_widget *source,
277 struct snd_soc_dapm_widget *sink)
278 {
279 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
280 const char *clk;
281
282 /* Check what we're currently using for CLK_SYS */
283 if (reg & WM8994_SYSCLK_SRC)
284 clk = "AIF2CLK";
285 else
286 clk = "AIF1CLK";
287
288 return strcmp(source->name, clk) == 0;
289 }
290
291 static const char *sidetone_hpf_text[] = {
292 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
293 };
294
295 static const struct soc_enum sidetone_hpf =
296 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
297
298 static const char *adc_hpf_text[] = {
299 "HiFi", "Voice 1", "Voice 2", "Voice 3"
300 };
301
302 static const struct soc_enum aif1adc1_hpf =
303 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
304
305 static const struct soc_enum aif1adc2_hpf =
306 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
307
308 static const struct soc_enum aif2adc_hpf =
309 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
310
311 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
312 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
313 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
314 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
315 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
316 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
317 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
318
319 #define WM8994_DRC_SWITCH(xname, reg, shift) \
320 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
321 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
322 .put = wm8994_put_drc_sw, \
323 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
324
325 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
326 struct snd_ctl_elem_value *ucontrol)
327 {
328 struct soc_mixer_control *mc =
329 (struct soc_mixer_control *)kcontrol->private_value;
330 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
331 int mask, ret;
332
333 /* Can't enable both ADC and DAC paths simultaneously */
334 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
335 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
336 WM8994_AIF1ADC1R_DRC_ENA_MASK;
337 else
338 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
339
340 ret = snd_soc_read(codec, mc->reg);
341 if (ret < 0)
342 return ret;
343 if (ret & mask)
344 return -EINVAL;
345
346 return snd_soc_put_volsw(kcontrol, ucontrol);
347 }
348
349 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
350 {
351 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
352 struct wm8994_pdata *pdata = wm8994->pdata;
353 int base = wm8994_drc_base[drc];
354 int cfg = wm8994->drc_cfg[drc];
355 int save, i;
356
357 /* Save any enables; the configuration should clear them. */
358 save = snd_soc_read(codec, base);
359 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
360 WM8994_AIF1ADC1R_DRC_ENA;
361
362 for (i = 0; i < WM8994_DRC_REGS; i++)
363 snd_soc_update_bits(codec, base + i, 0xffff,
364 pdata->drc_cfgs[cfg].regs[i]);
365
366 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
367 WM8994_AIF1ADC1L_DRC_ENA |
368 WM8994_AIF1ADC1R_DRC_ENA, save);
369 }
370
371 /* Icky as hell but saves code duplication */
372 static int wm8994_get_drc(const char *name)
373 {
374 if (strcmp(name, "AIF1DRC1 Mode") == 0)
375 return 0;
376 if (strcmp(name, "AIF1DRC2 Mode") == 0)
377 return 1;
378 if (strcmp(name, "AIF2DRC Mode") == 0)
379 return 2;
380 return -EINVAL;
381 }
382
383 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
384 struct snd_ctl_elem_value *ucontrol)
385 {
386 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
387 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
388 struct wm8994_pdata *pdata = wm8994->pdata;
389 int drc = wm8994_get_drc(kcontrol->id.name);
390 int value = ucontrol->value.integer.value[0];
391
392 if (drc < 0)
393 return drc;
394
395 if (value >= pdata->num_drc_cfgs)
396 return -EINVAL;
397
398 wm8994->drc_cfg[drc] = value;
399
400 wm8994_set_drc(codec, drc);
401
402 return 0;
403 }
404
405 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
406 struct snd_ctl_elem_value *ucontrol)
407 {
408 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
409 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
410 int drc = wm8994_get_drc(kcontrol->id.name);
411
412 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
413
414 return 0;
415 }
416
417 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
418 {
419 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
420 struct wm8994_pdata *pdata = wm8994->pdata;
421 int base = wm8994_retune_mobile_base[block];
422 int iface, best, best_val, save, i, cfg;
423
424 if (!pdata || !wm8994->num_retune_mobile_texts)
425 return;
426
427 switch (block) {
428 case 0:
429 case 1:
430 iface = 0;
431 break;
432 case 2:
433 iface = 1;
434 break;
435 default:
436 return;
437 }
438
439 /* Find the version of the currently selected configuration
440 * with the nearest sample rate. */
441 cfg = wm8994->retune_mobile_cfg[block];
442 best = 0;
443 best_val = INT_MAX;
444 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
445 if (strcmp(pdata->retune_mobile_cfgs[i].name,
446 wm8994->retune_mobile_texts[cfg]) == 0 &&
447 abs(pdata->retune_mobile_cfgs[i].rate
448 - wm8994->dac_rates[iface]) < best_val) {
449 best = i;
450 best_val = abs(pdata->retune_mobile_cfgs[i].rate
451 - wm8994->dac_rates[iface]);
452 }
453 }
454
455 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
456 block,
457 pdata->retune_mobile_cfgs[best].name,
458 pdata->retune_mobile_cfgs[best].rate,
459 wm8994->dac_rates[iface]);
460
461 /* The EQ will be disabled while reconfiguring it, remember the
462 * current configuration.
463 */
464 save = snd_soc_read(codec, base);
465 save &= WM8994_AIF1DAC1_EQ_ENA;
466
467 for (i = 0; i < WM8994_EQ_REGS; i++)
468 snd_soc_update_bits(codec, base + i, 0xffff,
469 pdata->retune_mobile_cfgs[best].regs[i]);
470
471 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
472 }
473
474 /* Icky as hell but saves code duplication */
475 static int wm8994_get_retune_mobile_block(const char *name)
476 {
477 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
478 return 0;
479 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
480 return 1;
481 if (strcmp(name, "AIF2 EQ Mode") == 0)
482 return 2;
483 return -EINVAL;
484 }
485
486 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
487 struct snd_ctl_elem_value *ucontrol)
488 {
489 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
490 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
491 struct wm8994_pdata *pdata = wm8994->pdata;
492 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
493 int value = ucontrol->value.integer.value[0];
494
495 if (block < 0)
496 return block;
497
498 if (value >= pdata->num_retune_mobile_cfgs)
499 return -EINVAL;
500
501 wm8994->retune_mobile_cfg[block] = value;
502
503 wm8994_set_retune_mobile(codec, block);
504
505 return 0;
506 }
507
508 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
509 struct snd_ctl_elem_value *ucontrol)
510 {
511 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
512 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
513 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
514
515 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
516
517 return 0;
518 }
519
520 static const char *aif_chan_src_text[] = {
521 "Left", "Right"
522 };
523
524 static const struct soc_enum aif1adcl_src =
525 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
526
527 static const struct soc_enum aif1adcr_src =
528 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
529
530 static const struct soc_enum aif2adcl_src =
531 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
532
533 static const struct soc_enum aif2adcr_src =
534 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
535
536 static const struct soc_enum aif1dacl_src =
537 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
538
539 static const struct soc_enum aif1dacr_src =
540 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
541
542 static const struct soc_enum aif2dacl_src =
543 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
544
545 static const struct soc_enum aif2dacr_src =
546 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
547
548 static const char *osr_text[] = {
549 "Low Power", "High Performance",
550 };
551
552 static const struct soc_enum dac_osr =
553 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
554
555 static const struct soc_enum adc_osr =
556 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
557
558 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
559 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
560 WM8994_AIF1_ADC1_RIGHT_VOLUME,
561 1, 119, 0, digital_tlv),
562 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
563 WM8994_AIF1_ADC2_RIGHT_VOLUME,
564 1, 119, 0, digital_tlv),
565 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
566 WM8994_AIF2_ADC_RIGHT_VOLUME,
567 1, 119, 0, digital_tlv),
568
569 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
570 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
571 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
572 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
573
574 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
575 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
576 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
577 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
578
579 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
580 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
581 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
582 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
583 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
584 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
585
586 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
587 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
588
589 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
590 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
591 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
592
593 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
594 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
595 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
596
597 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
598 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
599 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
600
601 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
602 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
603 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
604
605 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
606 5, 12, 0, st_tlv),
607 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
608 0, 12, 0, st_tlv),
609 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
610 5, 12, 0, st_tlv),
611 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
612 0, 12, 0, st_tlv),
613 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
614 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
615
616 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
617 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
618
619 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
620 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
621
622 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
623 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
624
625 SOC_ENUM("ADC OSR", adc_osr),
626 SOC_ENUM("DAC OSR", dac_osr),
627
628 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
629 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
630 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
631 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
632
633 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
634 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
635 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
636 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
637
638 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
639 6, 1, 1, wm_hubs_spkmix_tlv),
640 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
641 2, 1, 1, wm_hubs_spkmix_tlv),
642
643 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
644 6, 1, 1, wm_hubs_spkmix_tlv),
645 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
646 2, 1, 1, wm_hubs_spkmix_tlv),
647
648 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
649 10, 15, 0, wm8994_3d_tlv),
650 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
651 8, 1, 0),
652 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
653 10, 15, 0, wm8994_3d_tlv),
654 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
655 8, 1, 0),
656 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
657 10, 15, 0, wm8994_3d_tlv),
658 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
659 8, 1, 0),
660 };
661
662 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
663 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
664 eq_tlv),
665 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
666 eq_tlv),
667 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
668 eq_tlv),
669 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
670 eq_tlv),
671 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
672 eq_tlv),
673
674 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
675 eq_tlv),
676 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
677 eq_tlv),
678 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
679 eq_tlv),
680 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
681 eq_tlv),
682 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
683 eq_tlv),
684
685 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
686 eq_tlv),
687 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
688 eq_tlv),
689 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
690 eq_tlv),
691 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
692 eq_tlv),
693 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
694 eq_tlv),
695 };
696
697 static const char *wm8958_ng_text[] = {
698 "30ms", "125ms", "250ms", "500ms",
699 };
700
701 static const struct soc_enum wm8958_aif1dac1_ng_hold =
702 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
703 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
704
705 static const struct soc_enum wm8958_aif1dac2_ng_hold =
706 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
707 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
708
709 static const struct soc_enum wm8958_aif2dac_ng_hold =
710 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
711 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
712
713 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
714 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
715
716 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
717 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
718 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
719 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
720 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
721 7, 1, ng_tlv),
722
723 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
724 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
725 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
726 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
727 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
728 7, 1, ng_tlv),
729
730 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
731 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
732 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
733 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
734 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
735 7, 1, ng_tlv),
736 };
737
738 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
739 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
740 mixin_boost_tlv),
741 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
742 mixin_boost_tlv),
743 };
744
745 /* We run all mode setting through a function to enforce audio mode */
746 static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
747 {
748 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
749
750 if (wm8994->active_refcount)
751 mode = WM1811_JACKDET_MODE_AUDIO;
752
753 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
754 WM1811_JACKDET_MODE_MASK, mode);
755
756 if (mode == WM1811_JACKDET_MODE_MIC)
757 msleep(2);
758 }
759
760 static void active_reference(struct snd_soc_codec *codec)
761 {
762 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
763
764 mutex_lock(&wm8994->accdet_lock);
765
766 wm8994->active_refcount++;
767
768 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
769 wm8994->active_refcount);
770
771 if (wm8994->active_refcount == 1) {
772 /* If we're using jack detection go into audio mode */
773 if (wm8994->jackdet && wm8994->jack_cb) {
774 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
775 WM1811_JACKDET_MODE_MASK,
776 WM1811_JACKDET_MODE_AUDIO);
777 msleep(2);
778 }
779 }
780
781 mutex_unlock(&wm8994->accdet_lock);
782 }
783
784 static void active_dereference(struct snd_soc_codec *codec)
785 {
786 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
787 u16 mode;
788
789 mutex_lock(&wm8994->accdet_lock);
790
791 wm8994->active_refcount--;
792
793 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
794 wm8994->active_refcount);
795
796 if (wm8994->active_refcount == 0) {
797 /* Go into appropriate detection only mode */
798 if (wm8994->jackdet && wm8994->jack_cb) {
799 if (wm8994->jack_mic || wm8994->mic_detecting)
800 mode = WM1811_JACKDET_MODE_MIC;
801 else
802 mode = WM1811_JACKDET_MODE_JACK;
803
804 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
805 WM1811_JACKDET_MODE_MASK,
806 mode);
807 }
808 }
809
810 mutex_unlock(&wm8994->accdet_lock);
811 }
812
813 static int clk_sys_event(struct snd_soc_dapm_widget *w,
814 struct snd_kcontrol *kcontrol, int event)
815 {
816 struct snd_soc_codec *codec = w->codec;
817
818 switch (event) {
819 case SND_SOC_DAPM_PRE_PMU:
820 return configure_clock(codec);
821
822 case SND_SOC_DAPM_POST_PMD:
823 configure_clock(codec);
824 break;
825 }
826
827 return 0;
828 }
829
830 static void vmid_reference(struct snd_soc_codec *codec)
831 {
832 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
833
834 wm8994->vmid_refcount++;
835
836 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
837 wm8994->vmid_refcount);
838
839 if (wm8994->vmid_refcount == 1) {
840 /* Startup bias, VMID ramp & buffer */
841 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
842 WM8994_STARTUP_BIAS_ENA |
843 WM8994_VMID_BUF_ENA |
844 WM8994_VMID_RAMP_MASK,
845 WM8994_STARTUP_BIAS_ENA |
846 WM8994_VMID_BUF_ENA |
847 (0x11 << WM8994_VMID_RAMP_SHIFT));
848
849 /* Main bias enable, VMID=2x40k */
850 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
851 WM8994_BIAS_ENA |
852 WM8994_VMID_SEL_MASK,
853 WM8994_BIAS_ENA | 0x2);
854
855 msleep(20);
856 }
857 }
858
859 static void vmid_dereference(struct snd_soc_codec *codec)
860 {
861 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
862
863 wm8994->vmid_refcount--;
864
865 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
866 wm8994->vmid_refcount);
867
868 if (wm8994->vmid_refcount == 0) {
869 /* Switch over to startup biases */
870 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
871 WM8994_BIAS_SRC |
872 WM8994_STARTUP_BIAS_ENA |
873 WM8994_VMID_BUF_ENA |
874 WM8994_VMID_RAMP_MASK,
875 WM8994_BIAS_SRC |
876 WM8994_STARTUP_BIAS_ENA |
877 WM8994_VMID_BUF_ENA |
878 (1 << WM8994_VMID_RAMP_SHIFT));
879
880 /* Disable main biases */
881 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
882 WM8994_BIAS_ENA |
883 WM8994_VMID_SEL_MASK, 0);
884
885 /* Discharge line */
886 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
887 WM8994_LINEOUT1_DISCH |
888 WM8994_LINEOUT2_DISCH,
889 WM8994_LINEOUT1_DISCH |
890 WM8994_LINEOUT2_DISCH);
891
892 msleep(5);
893
894 /* Switch off startup biases */
895 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
896 WM8994_BIAS_SRC |
897 WM8994_STARTUP_BIAS_ENA |
898 WM8994_VMID_BUF_ENA |
899 WM8994_VMID_RAMP_MASK, 0);
900 }
901 }
902
903 static int vmid_event(struct snd_soc_dapm_widget *w,
904 struct snd_kcontrol *kcontrol, int event)
905 {
906 struct snd_soc_codec *codec = w->codec;
907
908 switch (event) {
909 case SND_SOC_DAPM_PRE_PMU:
910 vmid_reference(codec);
911 break;
912
913 case SND_SOC_DAPM_POST_PMD:
914 vmid_dereference(codec);
915 break;
916 }
917
918 return 0;
919 }
920
921 static void wm8994_update_class_w(struct snd_soc_codec *codec)
922 {
923 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
924 int enable = 1;
925 int source = 0; /* GCC flow analysis can't track enable */
926 int reg, reg_r;
927
928 /* Only support direct DAC->headphone paths */
929 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
930 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
931 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
932 enable = 0;
933 }
934
935 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
936 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
937 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
938 enable = 0;
939 }
940
941 /* We also need the same setting for L/R and only one path */
942 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
943 switch (reg) {
944 case WM8994_AIF2DACL_TO_DAC1L:
945 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
946 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
947 break;
948 case WM8994_AIF1DAC2L_TO_DAC1L:
949 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
950 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
951 break;
952 case WM8994_AIF1DAC1L_TO_DAC1L:
953 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
954 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
955 break;
956 default:
957 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
958 enable = 0;
959 break;
960 }
961
962 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
963 if (reg_r != reg) {
964 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
965 enable = 0;
966 }
967
968 if (enable) {
969 dev_dbg(codec->dev, "Class W enabled\n");
970 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
971 WM8994_CP_DYN_PWR |
972 WM8994_CP_DYN_SRC_SEL_MASK,
973 source | WM8994_CP_DYN_PWR);
974 wm8994->hubs.class_w = true;
975
976 } else {
977 dev_dbg(codec->dev, "Class W disabled\n");
978 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
979 WM8994_CP_DYN_PWR, 0);
980 wm8994->hubs.class_w = false;
981 }
982 }
983
984 static int late_enable_ev(struct snd_soc_dapm_widget *w,
985 struct snd_kcontrol *kcontrol, int event)
986 {
987 struct snd_soc_codec *codec = w->codec;
988 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
989
990 switch (event) {
991 case SND_SOC_DAPM_PRE_PMU:
992 if (wm8994->aif1clk_enable) {
993 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
994 WM8994_AIF1CLK_ENA_MASK,
995 WM8994_AIF1CLK_ENA);
996 wm8994->aif1clk_enable = 0;
997 }
998 if (wm8994->aif2clk_enable) {
999 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1000 WM8994_AIF2CLK_ENA_MASK,
1001 WM8994_AIF2CLK_ENA);
1002 wm8994->aif2clk_enable = 0;
1003 }
1004 break;
1005 }
1006
1007 /* We may also have postponed startup of DSP, handle that. */
1008 wm8958_aif_ev(w, kcontrol, event);
1009
1010 return 0;
1011 }
1012
1013 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1014 struct snd_kcontrol *kcontrol, int event)
1015 {
1016 struct snd_soc_codec *codec = w->codec;
1017 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1018
1019 switch (event) {
1020 case SND_SOC_DAPM_POST_PMD:
1021 if (wm8994->aif1clk_disable) {
1022 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1023 WM8994_AIF1CLK_ENA_MASK, 0);
1024 wm8994->aif1clk_disable = 0;
1025 }
1026 if (wm8994->aif2clk_disable) {
1027 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1028 WM8994_AIF2CLK_ENA_MASK, 0);
1029 wm8994->aif2clk_disable = 0;
1030 }
1031 break;
1032 }
1033
1034 return 0;
1035 }
1036
1037 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1038 struct snd_kcontrol *kcontrol, int event)
1039 {
1040 struct snd_soc_codec *codec = w->codec;
1041 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1042
1043 switch (event) {
1044 case SND_SOC_DAPM_PRE_PMU:
1045 wm8994->aif1clk_enable = 1;
1046 break;
1047 case SND_SOC_DAPM_POST_PMD:
1048 wm8994->aif1clk_disable = 1;
1049 break;
1050 }
1051
1052 return 0;
1053 }
1054
1055 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1056 struct snd_kcontrol *kcontrol, int event)
1057 {
1058 struct snd_soc_codec *codec = w->codec;
1059 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1060
1061 switch (event) {
1062 case SND_SOC_DAPM_PRE_PMU:
1063 wm8994->aif2clk_enable = 1;
1064 break;
1065 case SND_SOC_DAPM_POST_PMD:
1066 wm8994->aif2clk_disable = 1;
1067 break;
1068 }
1069
1070 return 0;
1071 }
1072
1073 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1074 struct snd_kcontrol *kcontrol, int event)
1075 {
1076 late_enable_ev(w, kcontrol, event);
1077 return 0;
1078 }
1079
1080 static int micbias_ev(struct snd_soc_dapm_widget *w,
1081 struct snd_kcontrol *kcontrol, int event)
1082 {
1083 late_enable_ev(w, kcontrol, event);
1084 return 0;
1085 }
1086
1087 static int dac_ev(struct snd_soc_dapm_widget *w,
1088 struct snd_kcontrol *kcontrol, int event)
1089 {
1090 struct snd_soc_codec *codec = w->codec;
1091 unsigned int mask = 1 << w->shift;
1092
1093 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1094 mask, mask);
1095 return 0;
1096 }
1097
1098 static const char *hp_mux_text[] = {
1099 "Mixer",
1100 "DAC",
1101 };
1102
1103 #define WM8994_HP_ENUM(xname, xenum) \
1104 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1105 .info = snd_soc_info_enum_double, \
1106 .get = snd_soc_dapm_get_enum_double, \
1107 .put = wm8994_put_hp_enum, \
1108 .private_value = (unsigned long)&xenum }
1109
1110 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1111 struct snd_ctl_elem_value *ucontrol)
1112 {
1113 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1114 struct snd_soc_dapm_widget *w = wlist->widgets[0];
1115 struct snd_soc_codec *codec = w->codec;
1116 int ret;
1117
1118 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1119
1120 wm8994_update_class_w(codec);
1121
1122 return ret;
1123 }
1124
1125 static const struct soc_enum hpl_enum =
1126 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1127
1128 static const struct snd_kcontrol_new hpl_mux =
1129 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1130
1131 static const struct soc_enum hpr_enum =
1132 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1133
1134 static const struct snd_kcontrol_new hpr_mux =
1135 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1136
1137 static const char *adc_mux_text[] = {
1138 "ADC",
1139 "DMIC",
1140 };
1141
1142 static const struct soc_enum adc_enum =
1143 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1144
1145 static const struct snd_kcontrol_new adcl_mux =
1146 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1147
1148 static const struct snd_kcontrol_new adcr_mux =
1149 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1150
1151 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1152 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1153 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1154 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1155 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1156 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1157 };
1158
1159 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1160 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1161 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1162 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1163 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1164 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1165 };
1166
1167 /* Debugging; dump chip status after DAPM transitions */
1168 static int post_ev(struct snd_soc_dapm_widget *w,
1169 struct snd_kcontrol *kcontrol, int event)
1170 {
1171 struct snd_soc_codec *codec = w->codec;
1172 dev_dbg(codec->dev, "SRC status: %x\n",
1173 snd_soc_read(codec,
1174 WM8994_RATE_STATUS));
1175 return 0;
1176 }
1177
1178 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1179 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1180 1, 1, 0),
1181 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1182 0, 1, 0),
1183 };
1184
1185 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1186 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1187 1, 1, 0),
1188 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1189 0, 1, 0),
1190 };
1191
1192 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1193 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1194 1, 1, 0),
1195 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1196 0, 1, 0),
1197 };
1198
1199 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1200 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1201 1, 1, 0),
1202 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1203 0, 1, 0),
1204 };
1205
1206 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1207 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1208 5, 1, 0),
1209 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1210 4, 1, 0),
1211 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1212 2, 1, 0),
1213 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1214 1, 1, 0),
1215 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1216 0, 1, 0),
1217 };
1218
1219 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1220 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1221 5, 1, 0),
1222 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1223 4, 1, 0),
1224 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1225 2, 1, 0),
1226 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1227 1, 1, 0),
1228 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1229 0, 1, 0),
1230 };
1231
1232 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1233 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1234 .info = snd_soc_info_volsw, \
1235 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1236 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1237
1238 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1239 struct snd_ctl_elem_value *ucontrol)
1240 {
1241 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1242 struct snd_soc_dapm_widget *w = wlist->widgets[0];
1243 struct snd_soc_codec *codec = w->codec;
1244 int ret;
1245
1246 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1247
1248 wm8994_update_class_w(codec);
1249
1250 return ret;
1251 }
1252
1253 static const struct snd_kcontrol_new dac1l_mix[] = {
1254 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1255 5, 1, 0),
1256 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1257 4, 1, 0),
1258 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1259 2, 1, 0),
1260 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1261 1, 1, 0),
1262 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1263 0, 1, 0),
1264 };
1265
1266 static const struct snd_kcontrol_new dac1r_mix[] = {
1267 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1268 5, 1, 0),
1269 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1270 4, 1, 0),
1271 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1272 2, 1, 0),
1273 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1274 1, 1, 0),
1275 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1276 0, 1, 0),
1277 };
1278
1279 static const char *sidetone_text[] = {
1280 "ADC/DMIC1", "DMIC2",
1281 };
1282
1283 static const struct soc_enum sidetone1_enum =
1284 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1285
1286 static const struct snd_kcontrol_new sidetone1_mux =
1287 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1288
1289 static const struct soc_enum sidetone2_enum =
1290 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1291
1292 static const struct snd_kcontrol_new sidetone2_mux =
1293 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1294
1295 static const char *aif1dac_text[] = {
1296 "AIF1DACDAT", "AIF3DACDAT",
1297 };
1298
1299 static const struct soc_enum aif1dac_enum =
1300 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1301
1302 static const struct snd_kcontrol_new aif1dac_mux =
1303 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1304
1305 static const char *aif2dac_text[] = {
1306 "AIF2DACDAT", "AIF3DACDAT",
1307 };
1308
1309 static const struct soc_enum aif2dac_enum =
1310 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1311
1312 static const struct snd_kcontrol_new aif2dac_mux =
1313 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1314
1315 static const char *aif2adc_text[] = {
1316 "AIF2ADCDAT", "AIF3DACDAT",
1317 };
1318
1319 static const struct soc_enum aif2adc_enum =
1320 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1321
1322 static const struct snd_kcontrol_new aif2adc_mux =
1323 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1324
1325 static const char *aif3adc_text[] = {
1326 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1327 };
1328
1329 static const struct soc_enum wm8994_aif3adc_enum =
1330 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1331
1332 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1333 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1334
1335 static const struct soc_enum wm8958_aif3adc_enum =
1336 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1337
1338 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1339 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1340
1341 static const char *mono_pcm_out_text[] = {
1342 "None", "AIF2ADCL", "AIF2ADCR",
1343 };
1344
1345 static const struct soc_enum mono_pcm_out_enum =
1346 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1347
1348 static const struct snd_kcontrol_new mono_pcm_out_mux =
1349 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1350
1351 static const char *aif2dac_src_text[] = {
1352 "AIF2", "AIF3",
1353 };
1354
1355 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1356 static const struct soc_enum aif2dacl_src_enum =
1357 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1358
1359 static const struct snd_kcontrol_new aif2dacl_src_mux =
1360 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1361
1362 static const struct soc_enum aif2dacr_src_enum =
1363 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1364
1365 static const struct snd_kcontrol_new aif2dacr_src_mux =
1366 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1367
1368 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1369 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1370 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1371 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1372 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1373
1374 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1375 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1376 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1377 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1378 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1379 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1380 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1381 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1382 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1383 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1384
1385 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1386 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1387 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1388 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1389 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1390 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1391 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1392 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1393 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1394 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1395
1396 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1397 };
1398
1399 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1400 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1401 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1402 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1403 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1404 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1405 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1406 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1407 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1408 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1409 };
1410
1411 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1412 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1413 dac_ev, SND_SOC_DAPM_PRE_PMU),
1414 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1415 dac_ev, SND_SOC_DAPM_PRE_PMU),
1416 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1417 dac_ev, SND_SOC_DAPM_PRE_PMU),
1418 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1419 dac_ev, SND_SOC_DAPM_PRE_PMU),
1420 };
1421
1422 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1423 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1424 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1425 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1426 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1427 };
1428
1429 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1430 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1431 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1432 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1433 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1434 };
1435
1436 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1437 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1438 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1439 };
1440
1441 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1442 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1443 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1444 SND_SOC_DAPM_INPUT("Clock"),
1445
1446 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1447 SND_SOC_DAPM_PRE_PMU),
1448 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1449 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1450
1451 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1452 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1453
1454 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1455 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1456 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1457
1458 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1459 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1460 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1461 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
1462 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1463 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1464 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1465 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1466 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1467 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1468
1469 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1470 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1471 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1472 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
1473 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1474 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
1475 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1476 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1477 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1478 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1479
1480 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1481 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1482 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1483 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1484
1485 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1486 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1487 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1488 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1489
1490 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1491 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1492 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1493 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1494
1495 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1496 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1497
1498 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1499 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1500 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1501 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1502
1503 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1504 WM8994_POWER_MANAGEMENT_4, 13, 0),
1505 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1506 WM8994_POWER_MANAGEMENT_4, 12, 0),
1507 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1508 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1509 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1510 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1511 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1512 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1513
1514 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1515 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1516 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1517 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1518
1519 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1520 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1521 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1522
1523 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1524 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1525
1526 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1527
1528 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1529 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1530 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1531 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1532
1533 /* Power is done with the muxes since the ADC power also controls the
1534 * downsampling chain, the chip will automatically manage the analogue
1535 * specific portions.
1536 */
1537 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1538 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1539
1540 SND_SOC_DAPM_POST("Debug log", post_ev),
1541 };
1542
1543 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1544 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1545 };
1546
1547 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1548 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1549 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1550 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1551 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1552 };
1553
1554 static const struct snd_soc_dapm_route intercon[] = {
1555 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1556 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1557
1558 { "DSP1CLK", NULL, "CLK_SYS" },
1559 { "DSP2CLK", NULL, "CLK_SYS" },
1560 { "DSPINTCLK", NULL, "CLK_SYS" },
1561
1562 { "AIF1ADC1L", NULL, "AIF1CLK" },
1563 { "AIF1ADC1L", NULL, "DSP1CLK" },
1564 { "AIF1ADC1R", NULL, "AIF1CLK" },
1565 { "AIF1ADC1R", NULL, "DSP1CLK" },
1566 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1567
1568 { "AIF1DAC1L", NULL, "AIF1CLK" },
1569 { "AIF1DAC1L", NULL, "DSP1CLK" },
1570 { "AIF1DAC1R", NULL, "AIF1CLK" },
1571 { "AIF1DAC1R", NULL, "DSP1CLK" },
1572 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1573
1574 { "AIF1ADC2L", NULL, "AIF1CLK" },
1575 { "AIF1ADC2L", NULL, "DSP1CLK" },
1576 { "AIF1ADC2R", NULL, "AIF1CLK" },
1577 { "AIF1ADC2R", NULL, "DSP1CLK" },
1578 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1579
1580 { "AIF1DAC2L", NULL, "AIF1CLK" },
1581 { "AIF1DAC2L", NULL, "DSP1CLK" },
1582 { "AIF1DAC2R", NULL, "AIF1CLK" },
1583 { "AIF1DAC2R", NULL, "DSP1CLK" },
1584 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1585
1586 { "AIF2ADCL", NULL, "AIF2CLK" },
1587 { "AIF2ADCL", NULL, "DSP2CLK" },
1588 { "AIF2ADCR", NULL, "AIF2CLK" },
1589 { "AIF2ADCR", NULL, "DSP2CLK" },
1590 { "AIF2ADCR", NULL, "DSPINTCLK" },
1591
1592 { "AIF2DACL", NULL, "AIF2CLK" },
1593 { "AIF2DACL", NULL, "DSP2CLK" },
1594 { "AIF2DACR", NULL, "AIF2CLK" },
1595 { "AIF2DACR", NULL, "DSP2CLK" },
1596 { "AIF2DACR", NULL, "DSPINTCLK" },
1597
1598 { "DMIC1L", NULL, "DMIC1DAT" },
1599 { "DMIC1L", NULL, "CLK_SYS" },
1600 { "DMIC1R", NULL, "DMIC1DAT" },
1601 { "DMIC1R", NULL, "CLK_SYS" },
1602 { "DMIC2L", NULL, "DMIC2DAT" },
1603 { "DMIC2L", NULL, "CLK_SYS" },
1604 { "DMIC2R", NULL, "DMIC2DAT" },
1605 { "DMIC2R", NULL, "CLK_SYS" },
1606
1607 { "ADCL", NULL, "AIF1CLK" },
1608 { "ADCL", NULL, "DSP1CLK" },
1609 { "ADCL", NULL, "DSPINTCLK" },
1610
1611 { "ADCR", NULL, "AIF1CLK" },
1612 { "ADCR", NULL, "DSP1CLK" },
1613 { "ADCR", NULL, "DSPINTCLK" },
1614
1615 { "ADCL Mux", "ADC", "ADCL" },
1616 { "ADCL Mux", "DMIC", "DMIC1L" },
1617 { "ADCR Mux", "ADC", "ADCR" },
1618 { "ADCR Mux", "DMIC", "DMIC1R" },
1619
1620 { "DAC1L", NULL, "AIF1CLK" },
1621 { "DAC1L", NULL, "DSP1CLK" },
1622 { "DAC1L", NULL, "DSPINTCLK" },
1623
1624 { "DAC1R", NULL, "AIF1CLK" },
1625 { "DAC1R", NULL, "DSP1CLK" },
1626 { "DAC1R", NULL, "DSPINTCLK" },
1627
1628 { "DAC2L", NULL, "AIF2CLK" },
1629 { "DAC2L", NULL, "DSP2CLK" },
1630 { "DAC2L", NULL, "DSPINTCLK" },
1631
1632 { "DAC2R", NULL, "AIF2DACR" },
1633 { "DAC2R", NULL, "AIF2CLK" },
1634 { "DAC2R", NULL, "DSP2CLK" },
1635 { "DAC2R", NULL, "DSPINTCLK" },
1636
1637 { "TOCLK", NULL, "CLK_SYS" },
1638
1639 /* AIF1 outputs */
1640 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1641 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1642 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1643
1644 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1645 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1646 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1647
1648 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1649 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1650 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1651
1652 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1653 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1654 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1655
1656 /* Pin level routing for AIF3 */
1657 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1658 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1659 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1660 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1661
1662 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1663 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1664 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1665 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1666 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1667 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1668 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1669
1670 /* DAC1 inputs */
1671 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1672 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1673 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1674 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1675 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1676
1677 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1678 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1679 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1680 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1681 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1682
1683 /* DAC2/AIF2 outputs */
1684 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1685 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1686 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1687 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1688 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1689 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1690
1691 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1692 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1693 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1694 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1695 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1696 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1697
1698 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1699 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1700 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1701 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1702
1703 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1704
1705 /* AIF3 output */
1706 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1707 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1708 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1709 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1710 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1711 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1712 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1713 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1714
1715 /* Sidetone */
1716 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1717 { "Left Sidetone", "DMIC2", "DMIC2L" },
1718 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1719 { "Right Sidetone", "DMIC2", "DMIC2R" },
1720
1721 /* Output stages */
1722 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1723 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1724
1725 { "SPKL", "DAC1 Switch", "DAC1L" },
1726 { "SPKL", "DAC2 Switch", "DAC2L" },
1727
1728 { "SPKR", "DAC1 Switch", "DAC1R" },
1729 { "SPKR", "DAC2 Switch", "DAC2R" },
1730
1731 { "Left Headphone Mux", "DAC", "DAC1L" },
1732 { "Right Headphone Mux", "DAC", "DAC1R" },
1733 };
1734
1735 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1736 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1737 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1738 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1739 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1740 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1741 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1742 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1743 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1744 };
1745
1746 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1747 { "DAC1L", NULL, "DAC1L Mixer" },
1748 { "DAC1R", NULL, "DAC1R Mixer" },
1749 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1750 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1751 };
1752
1753 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1754 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1755 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1756 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1757 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1758 { "MICBIAS1", NULL, "CLK_SYS" },
1759 { "MICBIAS1", NULL, "MICBIAS Supply" },
1760 { "MICBIAS2", NULL, "CLK_SYS" },
1761 { "MICBIAS2", NULL, "MICBIAS Supply" },
1762 };
1763
1764 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1765 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1766 { "AIF2DACR", NULL, "AIF2DAC Mux" },
1767 { "MICBIAS1", NULL, "VMID" },
1768 { "MICBIAS2", NULL, "VMID" },
1769 };
1770
1771 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1772 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1773 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1774
1775 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1776 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1777 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1778 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1779
1780 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1781 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1782
1783 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1784 };
1785
1786 /* The size in bits of the FLL divide multiplied by 10
1787 * to allow rounding later */
1788 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1789
1790 struct fll_div {
1791 u16 outdiv;
1792 u16 n;
1793 u16 k;
1794 u16 clk_ref_div;
1795 u16 fll_fratio;
1796 };
1797
1798 static int wm8994_get_fll_config(struct fll_div *fll,
1799 int freq_in, int freq_out)
1800 {
1801 u64 Kpart;
1802 unsigned int K, Ndiv, Nmod;
1803
1804 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1805
1806 /* Scale the input frequency down to <= 13.5MHz */
1807 fll->clk_ref_div = 0;
1808 while (freq_in > 13500000) {
1809 fll->clk_ref_div++;
1810 freq_in /= 2;
1811
1812 if (fll->clk_ref_div > 3)
1813 return -EINVAL;
1814 }
1815 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1816
1817 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1818 fll->outdiv = 3;
1819 while (freq_out * (fll->outdiv + 1) < 90000000) {
1820 fll->outdiv++;
1821 if (fll->outdiv > 63)
1822 return -EINVAL;
1823 }
1824 freq_out *= fll->outdiv + 1;
1825 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1826
1827 if (freq_in > 1000000) {
1828 fll->fll_fratio = 0;
1829 } else if (freq_in > 256000) {
1830 fll->fll_fratio = 1;
1831 freq_in *= 2;
1832 } else if (freq_in > 128000) {
1833 fll->fll_fratio = 2;
1834 freq_in *= 4;
1835 } else if (freq_in > 64000) {
1836 fll->fll_fratio = 3;
1837 freq_in *= 8;
1838 } else {
1839 fll->fll_fratio = 4;
1840 freq_in *= 16;
1841 }
1842 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1843
1844 /* Now, calculate N.K */
1845 Ndiv = freq_out / freq_in;
1846
1847 fll->n = Ndiv;
1848 Nmod = freq_out % freq_in;
1849 pr_debug("Nmod=%d\n", Nmod);
1850
1851 /* Calculate fractional part - scale up so we can round. */
1852 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1853
1854 do_div(Kpart, freq_in);
1855
1856 K = Kpart & 0xFFFFFFFF;
1857
1858 if ((K % 10) >= 5)
1859 K += 5;
1860
1861 /* Move down to proper range now rounding is done */
1862 fll->k = K / 10;
1863
1864 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1865
1866 return 0;
1867 }
1868
1869 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1870 unsigned int freq_in, unsigned int freq_out)
1871 {
1872 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1873 struct wm8994 *control = wm8994->wm8994;
1874 int reg_offset, ret;
1875 struct fll_div fll;
1876 u16 reg, aif1, aif2;
1877 unsigned long timeout;
1878 bool was_enabled;
1879
1880 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1881 & WM8994_AIF1CLK_ENA;
1882
1883 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1884 & WM8994_AIF2CLK_ENA;
1885
1886 switch (id) {
1887 case WM8994_FLL1:
1888 reg_offset = 0;
1889 id = 0;
1890 break;
1891 case WM8994_FLL2:
1892 reg_offset = 0x20;
1893 id = 1;
1894 break;
1895 default:
1896 return -EINVAL;
1897 }
1898
1899 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
1900 was_enabled = reg & WM8994_FLL1_ENA;
1901
1902 switch (src) {
1903 case 0:
1904 /* Allow no source specification when stopping */
1905 if (freq_out)
1906 return -EINVAL;
1907 src = wm8994->fll[id].src;
1908 break;
1909 case WM8994_FLL_SRC_MCLK1:
1910 case WM8994_FLL_SRC_MCLK2:
1911 case WM8994_FLL_SRC_LRCLK:
1912 case WM8994_FLL_SRC_BCLK:
1913 break;
1914 default:
1915 return -EINVAL;
1916 }
1917
1918 /* Are we changing anything? */
1919 if (wm8994->fll[id].src == src &&
1920 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1921 return 0;
1922
1923 /* If we're stopping the FLL redo the old config - no
1924 * registers will actually be written but we avoid GCC flow
1925 * analysis bugs spewing warnings.
1926 */
1927 if (freq_out)
1928 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1929 else
1930 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1931 wm8994->fll[id].out);
1932 if (ret < 0)
1933 return ret;
1934
1935 /* Gate the AIF clocks while we reclock */
1936 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1937 WM8994_AIF1CLK_ENA, 0);
1938 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1939 WM8994_AIF2CLK_ENA, 0);
1940
1941 /* We always need to disable the FLL while reconfiguring */
1942 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1943 WM8994_FLL1_ENA, 0);
1944
1945 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1946 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1947 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1948 WM8994_FLL1_OUTDIV_MASK |
1949 WM8994_FLL1_FRATIO_MASK, reg);
1950
1951 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1952
1953 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1954 WM8994_FLL1_N_MASK,
1955 fll.n << WM8994_FLL1_N_SHIFT);
1956
1957 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1958 WM8994_FLL1_REFCLK_DIV_MASK |
1959 WM8994_FLL1_REFCLK_SRC_MASK,
1960 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1961 (src - 1));
1962
1963 /* Clear any pending completion from a previous failure */
1964 try_wait_for_completion(&wm8994->fll_locked[id]);
1965
1966 /* Enable (with fractional mode if required) */
1967 if (freq_out) {
1968 /* Enable VMID if we need it */
1969 if (!was_enabled) {
1970 active_reference(codec);
1971
1972 switch (control->type) {
1973 case WM8994:
1974 vmid_reference(codec);
1975 break;
1976 case WM8958:
1977 if (wm8994->revision < 1)
1978 vmid_reference(codec);
1979 break;
1980 default:
1981 break;
1982 }
1983 }
1984
1985 if (fll.k)
1986 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1987 else
1988 reg = WM8994_FLL1_ENA;
1989 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1990 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1991 reg);
1992
1993 if (wm8994->fll_locked_irq) {
1994 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
1995 msecs_to_jiffies(10));
1996 if (timeout == 0)
1997 dev_warn(codec->dev,
1998 "Timed out waiting for FLL lock\n");
1999 } else {
2000 msleep(5);
2001 }
2002 } else {
2003 if (was_enabled) {
2004 switch (control->type) {
2005 case WM8994:
2006 vmid_dereference(codec);
2007 break;
2008 case WM8958:
2009 if (wm8994->revision < 1)
2010 vmid_dereference(codec);
2011 break;
2012 default:
2013 break;
2014 }
2015
2016 active_dereference(codec);
2017 }
2018 }
2019
2020 wm8994->fll[id].in = freq_in;
2021 wm8994->fll[id].out = freq_out;
2022 wm8994->fll[id].src = src;
2023
2024 /* Enable any gated AIF clocks */
2025 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
2026 WM8994_AIF1CLK_ENA, aif1);
2027 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
2028 WM8994_AIF2CLK_ENA, aif2);
2029
2030 configure_clock(codec);
2031
2032 return 0;
2033 }
2034
2035 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2036 {
2037 struct completion *completion = data;
2038
2039 complete(completion);
2040
2041 return IRQ_HANDLED;
2042 }
2043
2044 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2045
2046 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2047 unsigned int freq_in, unsigned int freq_out)
2048 {
2049 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2050 }
2051
2052 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2053 int clk_id, unsigned int freq, int dir)
2054 {
2055 struct snd_soc_codec *codec = dai->codec;
2056 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2057 int i;
2058
2059 switch (dai->id) {
2060 case 1:
2061 case 2:
2062 break;
2063
2064 default:
2065 /* AIF3 shares clocking with AIF1/2 */
2066 return -EINVAL;
2067 }
2068
2069 switch (clk_id) {
2070 case WM8994_SYSCLK_MCLK1:
2071 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2072 wm8994->mclk[0] = freq;
2073 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2074 dai->id, freq);
2075 break;
2076
2077 case WM8994_SYSCLK_MCLK2:
2078 /* TODO: Set GPIO AF */
2079 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2080 wm8994->mclk[1] = freq;
2081 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2082 dai->id, freq);
2083 break;
2084
2085 case WM8994_SYSCLK_FLL1:
2086 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2087 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2088 break;
2089
2090 case WM8994_SYSCLK_FLL2:
2091 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2092 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2093 break;
2094
2095 case WM8994_SYSCLK_OPCLK:
2096 /* Special case - a division (times 10) is given and
2097 * no effect on main clocking.
2098 */
2099 if (freq) {
2100 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2101 if (opclk_divs[i] == freq)
2102 break;
2103 if (i == ARRAY_SIZE(opclk_divs))
2104 return -EINVAL;
2105 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2106 WM8994_OPCLK_DIV_MASK, i);
2107 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2108 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2109 } else {
2110 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2111 WM8994_OPCLK_ENA, 0);
2112 }
2113
2114 default:
2115 return -EINVAL;
2116 }
2117
2118 configure_clock(codec);
2119
2120 return 0;
2121 }
2122
2123 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2124 enum snd_soc_bias_level level)
2125 {
2126 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2127 struct wm8994 *control = wm8994->wm8994;
2128
2129 switch (level) {
2130 case SND_SOC_BIAS_ON:
2131 break;
2132
2133 case SND_SOC_BIAS_PREPARE:
2134 /* MICBIAS into regulating mode */
2135 switch (control->type) {
2136 case WM8958:
2137 case WM1811:
2138 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2139 WM8958_MICB1_MODE, 0);
2140 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2141 WM8958_MICB2_MODE, 0);
2142 break;
2143 default:
2144 break;
2145 }
2146
2147 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2148 active_reference(codec);
2149 break;
2150
2151 case SND_SOC_BIAS_STANDBY:
2152 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2153 switch (control->type) {
2154 case WM8994:
2155 if (wm8994->revision < 4) {
2156 /* Tweak DC servo and DSP
2157 * configuration for improved
2158 * performance. */
2159 snd_soc_write(codec, 0x102, 0x3);
2160 snd_soc_write(codec, 0x56, 0x3);
2161 snd_soc_write(codec, 0x817, 0);
2162 snd_soc_write(codec, 0x102, 0);
2163 }
2164 break;
2165
2166 case WM8958:
2167 if (wm8994->revision == 0) {
2168 /* Optimise performance for rev A */
2169 snd_soc_write(codec, 0x102, 0x3);
2170 snd_soc_write(codec, 0xcb, 0x81);
2171 snd_soc_write(codec, 0x817, 0);
2172 snd_soc_write(codec, 0x102, 0);
2173
2174 snd_soc_update_bits(codec,
2175 WM8958_CHARGE_PUMP_2,
2176 WM8958_CP_DISCH,
2177 WM8958_CP_DISCH);
2178 }
2179 break;
2180
2181 case WM1811:
2182 if (wm8994->revision < 2) {
2183 snd_soc_write(codec, 0x102, 0x3);
2184 snd_soc_write(codec, 0x5d, 0x7e);
2185 snd_soc_write(codec, 0x5e, 0x0);
2186 snd_soc_write(codec, 0x102, 0x0);
2187 }
2188 break;
2189 }
2190
2191 /* Discharge LINEOUT1 & 2 */
2192 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2193 WM8994_LINEOUT1_DISCH |
2194 WM8994_LINEOUT2_DISCH,
2195 WM8994_LINEOUT1_DISCH |
2196 WM8994_LINEOUT2_DISCH);
2197 }
2198
2199 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2200 active_dereference(codec);
2201
2202 /* MICBIAS into bypass mode on newer devices */
2203 switch (control->type) {
2204 case WM8958:
2205 case WM1811:
2206 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2207 WM8958_MICB1_MODE,
2208 WM8958_MICB1_MODE);
2209 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2210 WM8958_MICB2_MODE,
2211 WM8958_MICB2_MODE);
2212 break;
2213 default:
2214 break;
2215 }
2216 break;
2217
2218 case SND_SOC_BIAS_OFF:
2219 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2220 wm8994->cur_fw = NULL;
2221 break;
2222 }
2223 codec->dapm.bias_level = level;
2224
2225 return 0;
2226 }
2227
2228 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2229 {
2230 struct snd_soc_codec *codec = dai->codec;
2231 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2232 struct wm8994 *control = wm8994->wm8994;
2233 int ms_reg;
2234 int aif1_reg;
2235 int ms = 0;
2236 int aif1 = 0;
2237
2238 switch (dai->id) {
2239 case 1:
2240 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2241 aif1_reg = WM8994_AIF1_CONTROL_1;
2242 break;
2243 case 2:
2244 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2245 aif1_reg = WM8994_AIF2_CONTROL_1;
2246 break;
2247 default:
2248 return -EINVAL;
2249 }
2250
2251 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2252 case SND_SOC_DAIFMT_CBS_CFS:
2253 break;
2254 case SND_SOC_DAIFMT_CBM_CFM:
2255 ms = WM8994_AIF1_MSTR;
2256 break;
2257 default:
2258 return -EINVAL;
2259 }
2260
2261 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2262 case SND_SOC_DAIFMT_DSP_B:
2263 aif1 |= WM8994_AIF1_LRCLK_INV;
2264 case SND_SOC_DAIFMT_DSP_A:
2265 aif1 |= 0x18;
2266 break;
2267 case SND_SOC_DAIFMT_I2S:
2268 aif1 |= 0x10;
2269 break;
2270 case SND_SOC_DAIFMT_RIGHT_J:
2271 break;
2272 case SND_SOC_DAIFMT_LEFT_J:
2273 aif1 |= 0x8;
2274 break;
2275 default:
2276 return -EINVAL;
2277 }
2278
2279 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2280 case SND_SOC_DAIFMT_DSP_A:
2281 case SND_SOC_DAIFMT_DSP_B:
2282 /* frame inversion not valid for DSP modes */
2283 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2284 case SND_SOC_DAIFMT_NB_NF:
2285 break;
2286 case SND_SOC_DAIFMT_IB_NF:
2287 aif1 |= WM8994_AIF1_BCLK_INV;
2288 break;
2289 default:
2290 return -EINVAL;
2291 }
2292 break;
2293
2294 case SND_SOC_DAIFMT_I2S:
2295 case SND_SOC_DAIFMT_RIGHT_J:
2296 case SND_SOC_DAIFMT_LEFT_J:
2297 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2298 case SND_SOC_DAIFMT_NB_NF:
2299 break;
2300 case SND_SOC_DAIFMT_IB_IF:
2301 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2302 break;
2303 case SND_SOC_DAIFMT_IB_NF:
2304 aif1 |= WM8994_AIF1_BCLK_INV;
2305 break;
2306 case SND_SOC_DAIFMT_NB_IF:
2307 aif1 |= WM8994_AIF1_LRCLK_INV;
2308 break;
2309 default:
2310 return -EINVAL;
2311 }
2312 break;
2313 default:
2314 return -EINVAL;
2315 }
2316
2317 /* The AIF2 format configuration needs to be mirrored to AIF3
2318 * on WM8958 if it's in use so just do it all the time. */
2319 switch (control->type) {
2320 case WM1811:
2321 case WM8958:
2322 if (dai->id == 2)
2323 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2324 WM8994_AIF1_LRCLK_INV |
2325 WM8958_AIF3_FMT_MASK, aif1);
2326 break;
2327
2328 default:
2329 break;
2330 }
2331
2332 snd_soc_update_bits(codec, aif1_reg,
2333 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2334 WM8994_AIF1_FMT_MASK,
2335 aif1);
2336 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2337 ms);
2338
2339 return 0;
2340 }
2341
2342 static struct {
2343 int val, rate;
2344 } srs[] = {
2345 { 0, 8000 },
2346 { 1, 11025 },
2347 { 2, 12000 },
2348 { 3, 16000 },
2349 { 4, 22050 },
2350 { 5, 24000 },
2351 { 6, 32000 },
2352 { 7, 44100 },
2353 { 8, 48000 },
2354 { 9, 88200 },
2355 { 10, 96000 },
2356 };
2357
2358 static int fs_ratios[] = {
2359 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2360 };
2361
2362 static int bclk_divs[] = {
2363 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2364 640, 880, 960, 1280, 1760, 1920
2365 };
2366
2367 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2368 struct snd_pcm_hw_params *params,
2369 struct snd_soc_dai *dai)
2370 {
2371 struct snd_soc_codec *codec = dai->codec;
2372 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2373 int aif1_reg;
2374 int aif2_reg;
2375 int bclk_reg;
2376 int lrclk_reg;
2377 int rate_reg;
2378 int aif1 = 0;
2379 int aif2 = 0;
2380 int bclk = 0;
2381 int lrclk = 0;
2382 int rate_val = 0;
2383 int id = dai->id - 1;
2384
2385 int i, cur_val, best_val, bclk_rate, best;
2386
2387 switch (dai->id) {
2388 case 1:
2389 aif1_reg = WM8994_AIF1_CONTROL_1;
2390 aif2_reg = WM8994_AIF1_CONTROL_2;
2391 bclk_reg = WM8994_AIF1_BCLK;
2392 rate_reg = WM8994_AIF1_RATE;
2393 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2394 wm8994->lrclk_shared[0]) {
2395 lrclk_reg = WM8994_AIF1DAC_LRCLK;
2396 } else {
2397 lrclk_reg = WM8994_AIF1ADC_LRCLK;
2398 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2399 }
2400 break;
2401 case 2:
2402 aif1_reg = WM8994_AIF2_CONTROL_1;
2403 aif2_reg = WM8994_AIF2_CONTROL_2;
2404 bclk_reg = WM8994_AIF2_BCLK;
2405 rate_reg = WM8994_AIF2_RATE;
2406 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2407 wm8994->lrclk_shared[1]) {
2408 lrclk_reg = WM8994_AIF2DAC_LRCLK;
2409 } else {
2410 lrclk_reg = WM8994_AIF2ADC_LRCLK;
2411 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2412 }
2413 break;
2414 default:
2415 return -EINVAL;
2416 }
2417
2418 bclk_rate = params_rate(params) * 2;
2419 switch (params_format(params)) {
2420 case SNDRV_PCM_FORMAT_S16_LE:
2421 bclk_rate *= 16;
2422 break;
2423 case SNDRV_PCM_FORMAT_S20_3LE:
2424 bclk_rate *= 20;
2425 aif1 |= 0x20;
2426 break;
2427 case SNDRV_PCM_FORMAT_S24_LE:
2428 bclk_rate *= 24;
2429 aif1 |= 0x40;
2430 break;
2431 case SNDRV_PCM_FORMAT_S32_LE:
2432 bclk_rate *= 32;
2433 aif1 |= 0x60;
2434 break;
2435 default:
2436 return -EINVAL;
2437 }
2438
2439 /* Try to find an appropriate sample rate; look for an exact match. */
2440 for (i = 0; i < ARRAY_SIZE(srs); i++)
2441 if (srs[i].rate == params_rate(params))
2442 break;
2443 if (i == ARRAY_SIZE(srs))
2444 return -EINVAL;
2445 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2446
2447 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2448 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2449 dai->id, wm8994->aifclk[id], bclk_rate);
2450
2451 if (params_channels(params) == 1 &&
2452 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2453 aif2 |= WM8994_AIF1_MONO;
2454
2455 if (wm8994->aifclk[id] == 0) {
2456 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2457 return -EINVAL;
2458 }
2459
2460 /* AIFCLK/fs ratio; look for a close match in either direction */
2461 best = 0;
2462 best_val = abs((fs_ratios[0] * params_rate(params))
2463 - wm8994->aifclk[id]);
2464 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2465 cur_val = abs((fs_ratios[i] * params_rate(params))
2466 - wm8994->aifclk[id]);
2467 if (cur_val >= best_val)
2468 continue;
2469 best = i;
2470 best_val = cur_val;
2471 }
2472 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2473 dai->id, fs_ratios[best]);
2474 rate_val |= best;
2475
2476 /* We may not get quite the right frequency if using
2477 * approximate clocks so look for the closest match that is
2478 * higher than the target (we need to ensure that there enough
2479 * BCLKs to clock out the samples).
2480 */
2481 best = 0;
2482 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2483 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2484 if (cur_val < 0) /* BCLK table is sorted */
2485 break;
2486 best = i;
2487 }
2488 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2489 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2490 bclk_divs[best], bclk_rate);
2491 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2492
2493 lrclk = bclk_rate / params_rate(params);
2494 if (!lrclk) {
2495 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2496 bclk_rate);
2497 return -EINVAL;
2498 }
2499 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2500 lrclk, bclk_rate / lrclk);
2501
2502 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2503 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2504 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2505 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2506 lrclk);
2507 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2508 WM8994_AIF1CLK_RATE_MASK, rate_val);
2509
2510 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2511 switch (dai->id) {
2512 case 1:
2513 wm8994->dac_rates[0] = params_rate(params);
2514 wm8994_set_retune_mobile(codec, 0);
2515 wm8994_set_retune_mobile(codec, 1);
2516 break;
2517 case 2:
2518 wm8994->dac_rates[1] = params_rate(params);
2519 wm8994_set_retune_mobile(codec, 2);
2520 break;
2521 }
2522 }
2523
2524 return 0;
2525 }
2526
2527 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2528 struct snd_pcm_hw_params *params,
2529 struct snd_soc_dai *dai)
2530 {
2531 struct snd_soc_codec *codec = dai->codec;
2532 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2533 struct wm8994 *control = wm8994->wm8994;
2534 int aif1_reg;
2535 int aif1 = 0;
2536
2537 switch (dai->id) {
2538 case 3:
2539 switch (control->type) {
2540 case WM1811:
2541 case WM8958:
2542 aif1_reg = WM8958_AIF3_CONTROL_1;
2543 break;
2544 default:
2545 return 0;
2546 }
2547 default:
2548 return 0;
2549 }
2550
2551 switch (params_format(params)) {
2552 case SNDRV_PCM_FORMAT_S16_LE:
2553 break;
2554 case SNDRV_PCM_FORMAT_S20_3LE:
2555 aif1 |= 0x20;
2556 break;
2557 case SNDRV_PCM_FORMAT_S24_LE:
2558 aif1 |= 0x40;
2559 break;
2560 case SNDRV_PCM_FORMAT_S32_LE:
2561 aif1 |= 0x60;
2562 break;
2563 default:
2564 return -EINVAL;
2565 }
2566
2567 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2568 }
2569
2570 static void wm8994_aif_shutdown(struct snd_pcm_substream *substream,
2571 struct snd_soc_dai *dai)
2572 {
2573 struct snd_soc_codec *codec = dai->codec;
2574 int rate_reg = 0;
2575
2576 switch (dai->id) {
2577 case 1:
2578 rate_reg = WM8994_AIF1_RATE;
2579 break;
2580 case 2:
2581 rate_reg = WM8994_AIF2_RATE;
2582 break;
2583 default:
2584 break;
2585 }
2586
2587 /* If the DAI is idle then configure the divider tree for the
2588 * lowest output rate to save a little power if the clock is
2589 * still active (eg, because it is system clock).
2590 */
2591 if (rate_reg && !dai->playback_active && !dai->capture_active)
2592 snd_soc_update_bits(codec, rate_reg,
2593 WM8994_AIF1_SR_MASK |
2594 WM8994_AIF1CLK_RATE_MASK, 0x9);
2595 }
2596
2597 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2598 {
2599 struct snd_soc_codec *codec = codec_dai->codec;
2600 int mute_reg;
2601 int reg;
2602
2603 switch (codec_dai->id) {
2604 case 1:
2605 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2606 break;
2607 case 2:
2608 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2609 break;
2610 default:
2611 return -EINVAL;
2612 }
2613
2614 if (mute)
2615 reg = WM8994_AIF1DAC1_MUTE;
2616 else
2617 reg = 0;
2618
2619 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2620
2621 return 0;
2622 }
2623
2624 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2625 {
2626 struct snd_soc_codec *codec = codec_dai->codec;
2627 int reg, val, mask;
2628
2629 switch (codec_dai->id) {
2630 case 1:
2631 reg = WM8994_AIF1_MASTER_SLAVE;
2632 mask = WM8994_AIF1_TRI;
2633 break;
2634 case 2:
2635 reg = WM8994_AIF2_MASTER_SLAVE;
2636 mask = WM8994_AIF2_TRI;
2637 break;
2638 case 3:
2639 reg = WM8994_POWER_MANAGEMENT_6;
2640 mask = WM8994_AIF3_TRI;
2641 break;
2642 default:
2643 return -EINVAL;
2644 }
2645
2646 if (tristate)
2647 val = mask;
2648 else
2649 val = 0;
2650
2651 return snd_soc_update_bits(codec, reg, mask, val);
2652 }
2653
2654 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2655 {
2656 struct snd_soc_codec *codec = dai->codec;
2657
2658 /* Disable the pulls on the AIF if we're using it to save power. */
2659 snd_soc_update_bits(codec, WM8994_GPIO_3,
2660 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2661 snd_soc_update_bits(codec, WM8994_GPIO_4,
2662 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2663 snd_soc_update_bits(codec, WM8994_GPIO_5,
2664 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2665
2666 return 0;
2667 }
2668
2669 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2670
2671 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2672 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2673
2674 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2675 .set_sysclk = wm8994_set_dai_sysclk,
2676 .set_fmt = wm8994_set_dai_fmt,
2677 .hw_params = wm8994_hw_params,
2678 .shutdown = wm8994_aif_shutdown,
2679 .digital_mute = wm8994_aif_mute,
2680 .set_pll = wm8994_set_fll,
2681 .set_tristate = wm8994_set_tristate,
2682 };
2683
2684 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2685 .set_sysclk = wm8994_set_dai_sysclk,
2686 .set_fmt = wm8994_set_dai_fmt,
2687 .hw_params = wm8994_hw_params,
2688 .shutdown = wm8994_aif_shutdown,
2689 .digital_mute = wm8994_aif_mute,
2690 .set_pll = wm8994_set_fll,
2691 .set_tristate = wm8994_set_tristate,
2692 };
2693
2694 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2695 .hw_params = wm8994_aif3_hw_params,
2696 .set_tristate = wm8994_set_tristate,
2697 };
2698
2699 static struct snd_soc_dai_driver wm8994_dai[] = {
2700 {
2701 .name = "wm8994-aif1",
2702 .id = 1,
2703 .playback = {
2704 .stream_name = "AIF1 Playback",
2705 .channels_min = 1,
2706 .channels_max = 2,
2707 .rates = WM8994_RATES,
2708 .formats = WM8994_FORMATS,
2709 },
2710 .capture = {
2711 .stream_name = "AIF1 Capture",
2712 .channels_min = 1,
2713 .channels_max = 2,
2714 .rates = WM8994_RATES,
2715 .formats = WM8994_FORMATS,
2716 },
2717 .ops = &wm8994_aif1_dai_ops,
2718 },
2719 {
2720 .name = "wm8994-aif2",
2721 .id = 2,
2722 .playback = {
2723 .stream_name = "AIF2 Playback",
2724 .channels_min = 1,
2725 .channels_max = 2,
2726 .rates = WM8994_RATES,
2727 .formats = WM8994_FORMATS,
2728 },
2729 .capture = {
2730 .stream_name = "AIF2 Capture",
2731 .channels_min = 1,
2732 .channels_max = 2,
2733 .rates = WM8994_RATES,
2734 .formats = WM8994_FORMATS,
2735 },
2736 .probe = wm8994_aif2_probe,
2737 .ops = &wm8994_aif2_dai_ops,
2738 },
2739 {
2740 .name = "wm8994-aif3",
2741 .id = 3,
2742 .playback = {
2743 .stream_name = "AIF3 Playback",
2744 .channels_min = 1,
2745 .channels_max = 2,
2746 .rates = WM8994_RATES,
2747 .formats = WM8994_FORMATS,
2748 },
2749 .capture = {
2750 .stream_name = "AIF3 Capture",
2751 .channels_min = 1,
2752 .channels_max = 2,
2753 .rates = WM8994_RATES,
2754 .formats = WM8994_FORMATS,
2755 },
2756 .ops = &wm8994_aif3_dai_ops,
2757 }
2758 };
2759
2760 #ifdef CONFIG_PM
2761 static int wm8994_suspend(struct snd_soc_codec *codec)
2762 {
2763 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2764 struct wm8994 *control = wm8994->wm8994;
2765 int i, ret;
2766
2767 switch (control->type) {
2768 case WM8994:
2769 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2770 break;
2771 case WM1811:
2772 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2773 WM1811_JACKDET_MODE_MASK, 0);
2774 /* Fall through */
2775 case WM8958:
2776 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2777 WM8958_MICD_ENA, 0);
2778 break;
2779 }
2780
2781 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2782 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2783 sizeof(struct wm8994_fll_config));
2784 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2785 if (ret < 0)
2786 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2787 i + 1, ret);
2788 }
2789
2790 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2791
2792 return 0;
2793 }
2794
2795 static int wm8994_resume(struct snd_soc_codec *codec)
2796 {
2797 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2798 struct wm8994 *control = wm8994->wm8994;
2799 int i, ret;
2800 unsigned int val, mask;
2801
2802 if (wm8994->revision < 4) {
2803 /* force a HW read */
2804 ret = regmap_read(control->regmap,
2805 WM8994_POWER_MANAGEMENT_5, &val);
2806
2807 /* modify the cache only */
2808 codec->cache_only = 1;
2809 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2810 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2811 val &= mask;
2812 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2813 mask, val);
2814 codec->cache_only = 0;
2815 }
2816
2817 /* Restore the registers */
2818 ret = snd_soc_cache_sync(codec);
2819 if (ret != 0)
2820 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
2821
2822 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2823
2824 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2825 if (!wm8994->fll_suspend[i].out)
2826 continue;
2827
2828 ret = _wm8994_set_fll(codec, i + 1,
2829 wm8994->fll_suspend[i].src,
2830 wm8994->fll_suspend[i].in,
2831 wm8994->fll_suspend[i].out);
2832 if (ret < 0)
2833 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2834 i + 1, ret);
2835 }
2836
2837 switch (control->type) {
2838 case WM8994:
2839 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2840 snd_soc_update_bits(codec, WM8994_MICBIAS,
2841 WM8994_MICD_ENA, WM8994_MICD_ENA);
2842 break;
2843 case WM1811:
2844 if (wm8994->jackdet && wm8994->jack_cb) {
2845 /* Restart from idle */
2846 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2847 WM1811_JACKDET_MODE_MASK,
2848 WM1811_JACKDET_MODE_JACK);
2849 break;
2850 }
2851 case WM8958:
2852 if (wm8994->jack_cb)
2853 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2854 WM8958_MICD_ENA, WM8958_MICD_ENA);
2855 break;
2856 }
2857
2858 return 0;
2859 }
2860 #else
2861 #define wm8994_suspend NULL
2862 #define wm8994_resume NULL
2863 #endif
2864
2865 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2866 {
2867 struct snd_soc_codec *codec = wm8994->codec;
2868 struct wm8994_pdata *pdata = wm8994->pdata;
2869 struct snd_kcontrol_new controls[] = {
2870 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2871 wm8994->retune_mobile_enum,
2872 wm8994_get_retune_mobile_enum,
2873 wm8994_put_retune_mobile_enum),
2874 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2875 wm8994->retune_mobile_enum,
2876 wm8994_get_retune_mobile_enum,
2877 wm8994_put_retune_mobile_enum),
2878 SOC_ENUM_EXT("AIF2 EQ Mode",
2879 wm8994->retune_mobile_enum,
2880 wm8994_get_retune_mobile_enum,
2881 wm8994_put_retune_mobile_enum),
2882 };
2883 int ret, i, j;
2884 const char **t;
2885
2886 /* We need an array of texts for the enum API but the number
2887 * of texts is likely to be less than the number of
2888 * configurations due to the sample rate dependency of the
2889 * configurations. */
2890 wm8994->num_retune_mobile_texts = 0;
2891 wm8994->retune_mobile_texts = NULL;
2892 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2893 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2894 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2895 wm8994->retune_mobile_texts[j]) == 0)
2896 break;
2897 }
2898
2899 if (j != wm8994->num_retune_mobile_texts)
2900 continue;
2901
2902 /* Expand the array... */
2903 t = krealloc(wm8994->retune_mobile_texts,
2904 sizeof(char *) *
2905 (wm8994->num_retune_mobile_texts + 1),
2906 GFP_KERNEL);
2907 if (t == NULL)
2908 continue;
2909
2910 /* ...store the new entry... */
2911 t[wm8994->num_retune_mobile_texts] =
2912 pdata->retune_mobile_cfgs[i].name;
2913
2914 /* ...and remember the new version. */
2915 wm8994->num_retune_mobile_texts++;
2916 wm8994->retune_mobile_texts = t;
2917 }
2918
2919 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2920 wm8994->num_retune_mobile_texts);
2921
2922 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2923 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2924
2925 ret = snd_soc_add_controls(wm8994->codec, controls,
2926 ARRAY_SIZE(controls));
2927 if (ret != 0)
2928 dev_err(wm8994->codec->dev,
2929 "Failed to add ReTune Mobile controls: %d\n", ret);
2930 }
2931
2932 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2933 {
2934 struct snd_soc_codec *codec = wm8994->codec;
2935 struct wm8994_pdata *pdata = wm8994->pdata;
2936 int ret, i;
2937
2938 if (!pdata)
2939 return;
2940
2941 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2942 pdata->lineout2_diff,
2943 pdata->lineout1fb,
2944 pdata->lineout2fb,
2945 pdata->jd_scthr,
2946 pdata->jd_thr,
2947 pdata->micbias1_lvl,
2948 pdata->micbias2_lvl);
2949
2950 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2951
2952 if (pdata->num_drc_cfgs) {
2953 struct snd_kcontrol_new controls[] = {
2954 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2955 wm8994_get_drc_enum, wm8994_put_drc_enum),
2956 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2957 wm8994_get_drc_enum, wm8994_put_drc_enum),
2958 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2959 wm8994_get_drc_enum, wm8994_put_drc_enum),
2960 };
2961
2962 /* We need an array of texts for the enum API */
2963 wm8994->drc_texts = devm_kzalloc(wm8994->codec->dev,
2964 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
2965 if (!wm8994->drc_texts) {
2966 dev_err(wm8994->codec->dev,
2967 "Failed to allocate %d DRC config texts\n",
2968 pdata->num_drc_cfgs);
2969 return;
2970 }
2971
2972 for (i = 0; i < pdata->num_drc_cfgs; i++)
2973 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2974
2975 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2976 wm8994->drc_enum.texts = wm8994->drc_texts;
2977
2978 ret = snd_soc_add_controls(wm8994->codec, controls,
2979 ARRAY_SIZE(controls));
2980 if (ret != 0)
2981 dev_err(wm8994->codec->dev,
2982 "Failed to add DRC mode controls: %d\n", ret);
2983
2984 for (i = 0; i < WM8994_NUM_DRC; i++)
2985 wm8994_set_drc(codec, i);
2986 }
2987
2988 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2989 pdata->num_retune_mobile_cfgs);
2990
2991 if (pdata->num_retune_mobile_cfgs)
2992 wm8994_handle_retune_mobile_pdata(wm8994);
2993 else
2994 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
2995 ARRAY_SIZE(wm8994_eq_controls));
2996
2997 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
2998 if (pdata->micbias[i]) {
2999 snd_soc_write(codec, WM8958_MICBIAS1 + i,
3000 pdata->micbias[i] & 0xffff);
3001 }
3002 }
3003 }
3004
3005 /**
3006 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3007 *
3008 * @codec: WM8994 codec
3009 * @jack: jack to report detection events on
3010 * @micbias: microphone bias to detect on
3011 * @det: value to report for presence detection
3012 * @shrt: value to report for short detection
3013 *
3014 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3015 * being used to bring out signals to the processor then only platform
3016 * data configuration is needed for WM8994 and processor GPIOs should
3017 * be configured using snd_soc_jack_add_gpios() instead.
3018 *
3019 * Configuration of detection levels is available via the micbias1_lvl
3020 * and micbias2_lvl platform data members.
3021 */
3022 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3023 int micbias, int det, int shrt)
3024 {
3025 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3026 struct wm8994_micdet *micdet;
3027 struct wm8994 *control = wm8994->wm8994;
3028 int reg;
3029
3030 if (control->type != WM8994)
3031 return -EINVAL;
3032
3033 switch (micbias) {
3034 case 1:
3035 micdet = &wm8994->micdet[0];
3036 break;
3037 case 2:
3038 micdet = &wm8994->micdet[1];
3039 break;
3040 default:
3041 return -EINVAL;
3042 }
3043
3044 dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
3045 micbias, det, shrt);
3046
3047 /* Store the configuration */
3048 micdet->jack = jack;
3049 micdet->det = det;
3050 micdet->shrt = shrt;
3051
3052 /* If either of the jacks is set up then enable detection */
3053 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3054 reg = WM8994_MICD_ENA;
3055 else
3056 reg = 0;
3057
3058 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3059
3060 return 0;
3061 }
3062 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3063
3064 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3065 {
3066 struct wm8994_priv *priv = data;
3067 struct snd_soc_codec *codec = priv->codec;
3068 int reg;
3069 int report;
3070
3071 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3072 trace_snd_soc_jack_irq(dev_name(codec->dev));
3073 #endif
3074
3075 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
3076 if (reg < 0) {
3077 dev_err(codec->dev, "Failed to read microphone status: %d\n",
3078 reg);
3079 return IRQ_HANDLED;
3080 }
3081
3082 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
3083
3084 report = 0;
3085 if (reg & WM8994_MIC1_DET_STS)
3086 report |= priv->micdet[0].det;
3087 if (reg & WM8994_MIC1_SHRT_STS)
3088 report |= priv->micdet[0].shrt;
3089 snd_soc_jack_report(priv->micdet[0].jack, report,
3090 priv->micdet[0].det | priv->micdet[0].shrt);
3091
3092 report = 0;
3093 if (reg & WM8994_MIC2_DET_STS)
3094 report |= priv->micdet[1].det;
3095 if (reg & WM8994_MIC2_SHRT_STS)
3096 report |= priv->micdet[1].shrt;
3097 snd_soc_jack_report(priv->micdet[1].jack, report,
3098 priv->micdet[1].det | priv->micdet[1].shrt);
3099
3100 return IRQ_HANDLED;
3101 }
3102
3103 /* Default microphone detection handler for WM8958 - the user can
3104 * override this if they wish.
3105 */
3106 static void wm8958_default_micdet(u16 status, void *data)
3107 {
3108 struct snd_soc_codec *codec = data;
3109 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3110 int report;
3111
3112 dev_dbg(codec->dev, "MICDET %x\n", status);
3113
3114 /* Either nothing present or just starting detection */
3115 if (!(status & WM8958_MICD_STS)) {
3116 if (!wm8994->jackdet) {
3117 /* If nothing present then clear our statuses */
3118 dev_dbg(codec->dev, "Detected open circuit\n");
3119 wm8994->jack_mic = false;
3120 wm8994->mic_detecting = true;
3121
3122 wm8958_micd_set_rate(codec);
3123
3124 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3125 wm8994->btn_mask |
3126 SND_JACK_HEADSET);
3127 }
3128 return;
3129 }
3130
3131 /* If the measurement is showing a high impedence we've got a
3132 * microphone.
3133 */
3134 if (wm8994->mic_detecting && (status & 0x600)) {
3135 dev_dbg(codec->dev, "Detected microphone\n");
3136
3137 wm8994->mic_detecting = false;
3138 wm8994->jack_mic = true;
3139
3140 wm8958_micd_set_rate(codec);
3141
3142 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3143 SND_JACK_HEADSET);
3144 }
3145
3146
3147 if (wm8994->mic_detecting && status & 0x4) {
3148 dev_dbg(codec->dev, "Detected headphone\n");
3149 wm8994->mic_detecting = false;
3150
3151 wm8958_micd_set_rate(codec);
3152
3153 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3154 SND_JACK_HEADSET);
3155
3156 /* If we have jackdet that will detect removal */
3157 if (wm8994->jackdet) {
3158 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3159 WM8958_MICD_ENA, 0);
3160
3161 wm1811_jackdet_set_mode(codec,
3162 WM1811_JACKDET_MODE_JACK);
3163 }
3164 }
3165
3166 /* Report short circuit as a button */
3167 if (wm8994->jack_mic) {
3168 report = 0;
3169 if (status & 0x4)
3170 report |= SND_JACK_BTN_0;
3171
3172 if (status & 0x8)
3173 report |= SND_JACK_BTN_1;
3174
3175 if (status & 0x10)
3176 report |= SND_JACK_BTN_2;
3177
3178 if (status & 0x20)
3179 report |= SND_JACK_BTN_3;
3180
3181 if (status & 0x40)
3182 report |= SND_JACK_BTN_4;
3183
3184 if (status & 0x80)
3185 report |= SND_JACK_BTN_5;
3186
3187 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3188 wm8994->btn_mask);
3189 }
3190 }
3191
3192 static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3193 {
3194 struct wm8994_priv *wm8994 = data;
3195 struct snd_soc_codec *codec = wm8994->codec;
3196 int reg;
3197
3198 mutex_lock(&wm8994->accdet_lock);
3199
3200 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3201 if (reg < 0) {
3202 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3203 mutex_unlock(&wm8994->accdet_lock);
3204 return IRQ_NONE;
3205 }
3206
3207 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3208
3209 if (reg & WM1811_JACKDET_LVL) {
3210 dev_dbg(codec->dev, "Jack detected\n");
3211
3212 snd_soc_jack_report(wm8994->micdet[0].jack,
3213 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3214
3215 /*
3216 * Start off measument of microphone impedence to find
3217 * out what's actually there.
3218 */
3219 wm8994->mic_detecting = true;
3220 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3221 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3222 WM8958_MICD_ENA, WM8958_MICD_ENA);
3223 } else {
3224 dev_dbg(codec->dev, "Jack not detected\n");
3225
3226 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3227 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3228 wm8994->btn_mask);
3229
3230 wm8994->mic_detecting = false;
3231 wm8994->jack_mic = false;
3232 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3233 WM8958_MICD_ENA, 0);
3234 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3235 }
3236
3237 mutex_unlock(&wm8994->accdet_lock);
3238
3239 return IRQ_HANDLED;
3240 }
3241
3242 /**
3243 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3244 *
3245 * @codec: WM8958 codec
3246 * @jack: jack to report detection events on
3247 *
3248 * Enable microphone detection functionality for the WM8958. By
3249 * default simple detection which supports the detection of up to 6
3250 * buttons plus video and microphone functionality is supported.
3251 *
3252 * The WM8958 has an advanced jack detection facility which is able to
3253 * support complex accessory detection, especially when used in
3254 * conjunction with external circuitry. In order to provide maximum
3255 * flexiblity a callback is provided which allows a completely custom
3256 * detection algorithm.
3257 */
3258 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3259 wm8958_micdet_cb cb, void *cb_data)
3260 {
3261 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3262 struct wm8994 *control = wm8994->wm8994;
3263 u16 micd_lvl_sel;
3264
3265 switch (control->type) {
3266 case WM1811:
3267 case WM8958:
3268 break;
3269 default:
3270 return -EINVAL;
3271 }
3272
3273 if (jack) {
3274 if (!cb) {
3275 dev_dbg(codec->dev, "Using default micdet callback\n");
3276 cb = wm8958_default_micdet;
3277 cb_data = codec;
3278 }
3279
3280 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3281
3282 wm8994->micdet[0].jack = jack;
3283 wm8994->jack_cb = cb;
3284 wm8994->jack_cb_data = cb_data;
3285
3286 wm8994->mic_detecting = true;
3287 wm8994->jack_mic = false;
3288
3289 wm8958_micd_set_rate(codec);
3290
3291 /* Detect microphones and short circuits by default */
3292 if (wm8994->pdata->micd_lvl_sel)
3293 micd_lvl_sel = wm8994->pdata->micd_lvl_sel;
3294 else
3295 micd_lvl_sel = 0x41;
3296
3297 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3298 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3299 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3300
3301 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
3302 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3303
3304 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3305
3306 /*
3307 * If we can use jack detection start off with that,
3308 * otherwise jump straight to microphone detection.
3309 */
3310 if (wm8994->jackdet) {
3311 snd_soc_update_bits(codec, WM8994_LDO_1,
3312 WM8994_LDO1_DISCH, 0);
3313 wm1811_jackdet_set_mode(codec,
3314 WM1811_JACKDET_MODE_JACK);
3315 } else {
3316 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3317 WM8958_MICD_ENA, WM8958_MICD_ENA);
3318 }
3319
3320 } else {
3321 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3322 WM8958_MICD_ENA, 0);
3323 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
3324 }
3325
3326 return 0;
3327 }
3328 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3329
3330 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3331 {
3332 struct wm8994_priv *wm8994 = data;
3333 struct snd_soc_codec *codec = wm8994->codec;
3334 int reg, count;
3335
3336 mutex_lock(&wm8994->accdet_lock);
3337
3338 /*
3339 * Jack detection may have detected a removal simulataneously
3340 * with an update of the MICDET status; if so it will have
3341 * stopped detection and we can ignore this interrupt.
3342 */
3343 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA)) {
3344 mutex_unlock(&wm8994->accdet_lock);
3345 return IRQ_HANDLED;
3346 }
3347
3348 /* We may occasionally read a detection without an impedence
3349 * range being provided - if that happens loop again.
3350 */
3351 count = 10;
3352 do {
3353 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3354 if (reg < 0) {
3355 mutex_unlock(&wm8994->accdet_lock);
3356 dev_err(codec->dev,
3357 "Failed to read mic detect status: %d\n",
3358 reg);
3359 return IRQ_NONE;
3360 }
3361
3362 if (!(reg & WM8958_MICD_VALID)) {
3363 dev_dbg(codec->dev, "Mic detect data not valid\n");
3364 goto out;
3365 }
3366
3367 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3368 break;
3369
3370 msleep(1);
3371 } while (count--);
3372
3373 if (count == 0)
3374 dev_warn(codec->dev, "No impedence range reported for jack\n");
3375
3376 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3377 trace_snd_soc_jack_irq(dev_name(codec->dev));
3378 #endif
3379
3380 if (wm8994->jack_cb)
3381 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3382 else
3383 dev_warn(codec->dev, "Accessory detection with no callback\n");
3384
3385 out:
3386 mutex_unlock(&wm8994->accdet_lock);
3387
3388 return IRQ_HANDLED;
3389 }
3390
3391 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3392 {
3393 struct snd_soc_codec *codec = data;
3394
3395 dev_err(codec->dev, "FIFO error\n");
3396
3397 return IRQ_HANDLED;
3398 }
3399
3400 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3401 {
3402 struct snd_soc_codec *codec = data;
3403
3404 dev_err(codec->dev, "Thermal warning\n");
3405
3406 return IRQ_HANDLED;
3407 }
3408
3409 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3410 {
3411 struct snd_soc_codec *codec = data;
3412
3413 dev_crit(codec->dev, "Thermal shutdown\n");
3414
3415 return IRQ_HANDLED;
3416 }
3417
3418 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3419 {
3420 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
3421 struct wm8994_priv *wm8994;
3422 struct snd_soc_dapm_context *dapm = &codec->dapm;
3423 unsigned int reg;
3424 int ret, i;
3425
3426 codec->control_data = control->regmap;
3427
3428 wm8994 = devm_kzalloc(codec->dev, sizeof(struct wm8994_priv),
3429 GFP_KERNEL);
3430 if (wm8994 == NULL)
3431 return -ENOMEM;
3432 snd_soc_codec_set_drvdata(codec, wm8994);
3433
3434 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
3435
3436 wm8994->wm8994 = dev_get_drvdata(codec->dev->parent);
3437 wm8994->pdata = dev_get_platdata(codec->dev->parent);
3438 wm8994->codec = codec;
3439
3440 mutex_init(&wm8994->accdet_lock);
3441
3442 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3443 init_completion(&wm8994->fll_locked[i]);
3444
3445 if (wm8994->pdata && wm8994->pdata->micdet_irq)
3446 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3447 else if (wm8994->pdata && wm8994->pdata->irq_base)
3448 wm8994->micdet_irq = wm8994->pdata->irq_base +
3449 WM8994_IRQ_MIC1_DET;
3450
3451 pm_runtime_enable(codec->dev);
3452 pm_runtime_resume(codec->dev);
3453
3454 /* Read our current status back from the chip - we don't want to
3455 * reset as this may interfere with the GPIO or LDO operation. */
3456 for (i = 0; i < WM8994_CACHE_SIZE; i++) {
3457 if (!wm8994_readable(codec, i) || wm8994_volatile(codec, i))
3458 continue;
3459
3460 ret = regmap_read(control->regmap, i, &reg);
3461 if (ret <= 0)
3462 continue;
3463
3464 ret = snd_soc_cache_write(codec, i, reg);
3465 if (ret != 0) {
3466 dev_err(codec->dev,
3467 "Failed to initialise cache for 0x%x: %d\n",
3468 i, ret);
3469 goto err;
3470 }
3471 }
3472
3473 /* Set revision-specific configuration */
3474 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3475 switch (control->type) {
3476 case WM8994:
3477 switch (wm8994->revision) {
3478 case 2:
3479 case 3:
3480 wm8994->hubs.dcs_codes_l = -5;
3481 wm8994->hubs.dcs_codes_r = -5;
3482 wm8994->hubs.hp_startup_mode = 1;
3483 wm8994->hubs.dcs_readback_mode = 1;
3484 wm8994->hubs.series_startup = 1;
3485 break;
3486 default:
3487 wm8994->hubs.dcs_readback_mode = 2;
3488 break;
3489 }
3490 break;
3491
3492 case WM8958:
3493 wm8994->hubs.dcs_readback_mode = 1;
3494 break;
3495
3496 case WM1811:
3497 wm8994->hubs.dcs_readback_mode = 2;
3498 wm8994->hubs.no_series_update = 1;
3499
3500 switch (wm8994->revision) {
3501 case 0:
3502 case 1:
3503 case 2:
3504 case 3:
3505 wm8994->hubs.dcs_codes_l = -9;
3506 wm8994->hubs.dcs_codes_r = -5;
3507 break;
3508 default:
3509 break;
3510 }
3511
3512 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3513 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3514 break;
3515
3516 default:
3517 break;
3518 }
3519
3520 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3521 wm8994_fifo_error, "FIFO error", codec);
3522 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
3523 wm8994_temp_warn, "Thermal warning", codec);
3524 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
3525 wm8994_temp_shut, "Thermal shutdown", codec);
3526
3527 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3528 wm_hubs_dcs_done, "DC servo done",
3529 &wm8994->hubs);
3530 if (ret == 0)
3531 wm8994->hubs.dcs_done_irq = true;
3532
3533 switch (control->type) {
3534 case WM8994:
3535 if (wm8994->micdet_irq) {
3536 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3537 wm8994_mic_irq,
3538 IRQF_TRIGGER_RISING,
3539 "Mic1 detect",
3540 wm8994);
3541 if (ret != 0)
3542 dev_warn(codec->dev,
3543 "Failed to request Mic1 detect IRQ: %d\n",
3544 ret);
3545 }
3546
3547 ret = wm8994_request_irq(wm8994->wm8994,
3548 WM8994_IRQ_MIC1_SHRT,
3549 wm8994_mic_irq, "Mic 1 short",
3550 wm8994);
3551 if (ret != 0)
3552 dev_warn(codec->dev,
3553 "Failed to request Mic1 short IRQ: %d\n",
3554 ret);
3555
3556 ret = wm8994_request_irq(wm8994->wm8994,
3557 WM8994_IRQ_MIC2_DET,
3558 wm8994_mic_irq, "Mic 2 detect",
3559 wm8994);
3560 if (ret != 0)
3561 dev_warn(codec->dev,
3562 "Failed to request Mic2 detect IRQ: %d\n",
3563 ret);
3564
3565 ret = wm8994_request_irq(wm8994->wm8994,
3566 WM8994_IRQ_MIC2_SHRT,
3567 wm8994_mic_irq, "Mic 2 short",
3568 wm8994);
3569 if (ret != 0)
3570 dev_warn(codec->dev,
3571 "Failed to request Mic2 short IRQ: %d\n",
3572 ret);
3573 break;
3574
3575 case WM8958:
3576 case WM1811:
3577 if (wm8994->micdet_irq) {
3578 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3579 wm8958_mic_irq,
3580 IRQF_TRIGGER_RISING,
3581 "Mic detect",
3582 wm8994);
3583 if (ret != 0)
3584 dev_warn(codec->dev,
3585 "Failed to request Mic detect IRQ: %d\n",
3586 ret);
3587 }
3588 }
3589
3590 switch (control->type) {
3591 case WM1811:
3592 if (wm8994->revision > 1) {
3593 ret = wm8994_request_irq(wm8994->wm8994,
3594 WM8994_IRQ_GPIO(6),
3595 wm1811_jackdet_irq, "JACKDET",
3596 wm8994);
3597 if (ret == 0)
3598 wm8994->jackdet = true;
3599 }
3600 break;
3601 default:
3602 break;
3603 }
3604
3605 wm8994->fll_locked_irq = true;
3606 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
3607 ret = wm8994_request_irq(wm8994->wm8994,
3608 WM8994_IRQ_FLL1_LOCK + i,
3609 wm8994_fll_locked_irq, "FLL lock",
3610 &wm8994->fll_locked[i]);
3611 if (ret != 0)
3612 wm8994->fll_locked_irq = false;
3613 }
3614
3615 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3616 * configured on init - if a system wants to do this dynamically
3617 * at runtime we can deal with that then.
3618 */
3619 ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
3620 if (ret < 0) {
3621 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3622 goto err_irq;
3623 }
3624 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3625 wm8994->lrclk_shared[0] = 1;
3626 wm8994_dai[0].symmetric_rates = 1;
3627 } else {
3628 wm8994->lrclk_shared[0] = 0;
3629 }
3630
3631 ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
3632 if (ret < 0) {
3633 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3634 goto err_irq;
3635 }
3636 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3637 wm8994->lrclk_shared[1] = 1;
3638 wm8994_dai[1].symmetric_rates = 1;
3639 } else {
3640 wm8994->lrclk_shared[1] = 0;
3641 }
3642
3643 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3644
3645 /* Latch volume updates (right only; we always do left then right). */
3646 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3647 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3648 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3649 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3650 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3651 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3652 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3653 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3654 snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3655 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3656 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3657 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3658 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3659 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3660 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3661 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3662 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3663 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3664 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3665 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3666 snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3667 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3668 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3669 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3670 snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3671 WM8994_DAC1_VU, WM8994_DAC1_VU);
3672 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3673 WM8994_DAC1_VU, WM8994_DAC1_VU);
3674 snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3675 WM8994_DAC2_VU, WM8994_DAC2_VU);
3676 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3677 WM8994_DAC2_VU, WM8994_DAC2_VU);
3678
3679 /* Set the low bit of the 3D stereo depth so TLV matches */
3680 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3681 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3682 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3683 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3684 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3685 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3686 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3687 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3688 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3689
3690 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3691 * use this; it only affects behaviour on idle TDM clock
3692 * cycles. */
3693 switch (control->type) {
3694 case WM8994:
3695 case WM8958:
3696 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3697 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3698 break;
3699 default:
3700 break;
3701 }
3702
3703 /* Put MICBIAS into bypass mode by default on newer devices */
3704 switch (control->type) {
3705 case WM8958:
3706 case WM1811:
3707 snd_soc_update_bits(codec, WM8958_MICBIAS1,
3708 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
3709 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3710 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
3711 break;
3712 default:
3713 break;
3714 }
3715
3716 wm8994_update_class_w(codec);
3717
3718 wm8994_handle_pdata(wm8994);
3719
3720 wm_hubs_add_analogue_controls(codec);
3721 snd_soc_add_controls(codec, wm8994_snd_controls,
3722 ARRAY_SIZE(wm8994_snd_controls));
3723 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3724 ARRAY_SIZE(wm8994_dapm_widgets));
3725
3726 switch (control->type) {
3727 case WM8994:
3728 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3729 ARRAY_SIZE(wm8994_specific_dapm_widgets));
3730 if (wm8994->revision < 4) {
3731 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3732 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3733 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3734 ARRAY_SIZE(wm8994_adc_revd_widgets));
3735 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3736 ARRAY_SIZE(wm8994_dac_revd_widgets));
3737 } else {
3738 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3739 ARRAY_SIZE(wm8994_lateclk_widgets));
3740 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3741 ARRAY_SIZE(wm8994_adc_widgets));
3742 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3743 ARRAY_SIZE(wm8994_dac_widgets));
3744 }
3745 break;
3746 case WM8958:
3747 snd_soc_add_controls(codec, wm8958_snd_controls,
3748 ARRAY_SIZE(wm8958_snd_controls));
3749 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3750 ARRAY_SIZE(wm8958_dapm_widgets));
3751 if (wm8994->revision < 1) {
3752 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3753 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3754 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3755 ARRAY_SIZE(wm8994_adc_revd_widgets));
3756 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3757 ARRAY_SIZE(wm8994_dac_revd_widgets));
3758 } else {
3759 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3760 ARRAY_SIZE(wm8994_lateclk_widgets));
3761 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3762 ARRAY_SIZE(wm8994_adc_widgets));
3763 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3764 ARRAY_SIZE(wm8994_dac_widgets));
3765 }
3766 break;
3767
3768 case WM1811:
3769 snd_soc_add_controls(codec, wm8958_snd_controls,
3770 ARRAY_SIZE(wm8958_snd_controls));
3771 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3772 ARRAY_SIZE(wm8958_dapm_widgets));
3773 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3774 ARRAY_SIZE(wm8994_lateclk_widgets));
3775 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3776 ARRAY_SIZE(wm8994_adc_widgets));
3777 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3778 ARRAY_SIZE(wm8994_dac_widgets));
3779 break;
3780 }
3781
3782
3783 wm_hubs_add_analogue_routes(codec, 0, 0);
3784 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3785
3786 switch (control->type) {
3787 case WM8994:
3788 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3789 ARRAY_SIZE(wm8994_intercon));
3790
3791 if (wm8994->revision < 4) {
3792 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3793 ARRAY_SIZE(wm8994_revd_intercon));
3794 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3795 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3796 } else {
3797 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3798 ARRAY_SIZE(wm8994_lateclk_intercon));
3799 }
3800 break;
3801 case WM8958:
3802 if (wm8994->revision < 1) {
3803 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3804 ARRAY_SIZE(wm8994_revd_intercon));
3805 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3806 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3807 } else {
3808 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3809 ARRAY_SIZE(wm8994_lateclk_intercon));
3810 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3811 ARRAY_SIZE(wm8958_intercon));
3812 }
3813
3814 wm8958_dsp2_init(codec);
3815 break;
3816 case WM1811:
3817 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3818 ARRAY_SIZE(wm8994_lateclk_intercon));
3819 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3820 ARRAY_SIZE(wm8958_intercon));
3821 break;
3822 }
3823
3824 return 0;
3825
3826 err_irq:
3827 if (wm8994->jackdet)
3828 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
3829 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
3830 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
3831 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
3832 if (wm8994->micdet_irq)
3833 free_irq(wm8994->micdet_irq, wm8994);
3834 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3835 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
3836 &wm8994->fll_locked[i]);
3837 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3838 &wm8994->hubs);
3839 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3840 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3841 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
3842 err:
3843 return ret;
3844 }
3845
3846 static int wm8994_codec_remove(struct snd_soc_codec *codec)
3847 {
3848 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3849 struct wm8994 *control = wm8994->wm8994;
3850 int i;
3851
3852 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3853
3854 pm_runtime_disable(codec->dev);
3855
3856 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3857 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
3858 &wm8994->fll_locked[i]);
3859
3860 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3861 &wm8994->hubs);
3862 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3863 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3864 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
3865
3866 if (wm8994->jackdet)
3867 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
3868
3869 switch (control->type) {
3870 case WM8994:
3871 if (wm8994->micdet_irq)
3872 free_irq(wm8994->micdet_irq, wm8994);
3873 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
3874 wm8994);
3875 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
3876 wm8994);
3877 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3878 wm8994);
3879 break;
3880
3881 case WM1811:
3882 case WM8958:
3883 if (wm8994->micdet_irq)
3884 free_irq(wm8994->micdet_irq, wm8994);
3885 break;
3886 }
3887 if (wm8994->mbc)
3888 release_firmware(wm8994->mbc);
3889 if (wm8994->mbc_vss)
3890 release_firmware(wm8994->mbc_vss);
3891 if (wm8994->enh_eq)
3892 release_firmware(wm8994->enh_eq);
3893 kfree(wm8994->retune_mobile_texts);
3894
3895 return 0;
3896 }
3897
3898 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3899 .probe = wm8994_codec_probe,
3900 .remove = wm8994_codec_remove,
3901 .suspend = wm8994_suspend,
3902 .resume = wm8994_resume,
3903 .readable_register = wm8994_readable,
3904 .volatile_register = wm8994_volatile,
3905 .set_bias_level = wm8994_set_bias_level,
3906
3907 .reg_cache_size = WM8994_CACHE_SIZE,
3908 .reg_cache_default = wm8994_reg_defaults,
3909 .reg_word_size = 2,
3910 .compress_type = SND_SOC_RBTREE_COMPRESSION,
3911 };
3912
3913 static int __devinit wm8994_probe(struct platform_device *pdev)
3914 {
3915 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3916 wm8994_dai, ARRAY_SIZE(wm8994_dai));
3917 }
3918
3919 static int __devexit wm8994_remove(struct platform_device *pdev)
3920 {
3921 snd_soc_unregister_codec(&pdev->dev);
3922 return 0;
3923 }
3924
3925 static struct platform_driver wm8994_codec_driver = {
3926 .driver = {
3927 .name = "wm8994-codec",
3928 .owner = THIS_MODULE,
3929 },
3930 .probe = wm8994_probe,
3931 .remove = __devexit_p(wm8994_remove),
3932 };
3933
3934 module_platform_driver(wm8994_codec_driver);
3935
3936 MODULE_DESCRIPTION("ASoC WM8994 driver");
3937 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3938 MODULE_LICENSE("GPL");
3939 MODULE_ALIAS("platform:wm8994-codec");
Linux kernel - Deliverables
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