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ASoC: wm8994: Tune VMID power down sequence
[deliverable/linux.git] / sound / soc / codecs / wm8994.c
1 /*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009-12 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/jack.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <trace/events/asoc.h>
32
33 #include <linux/mfd/wm8994/core.h>
34 #include <linux/mfd/wm8994/registers.h>
35 #include <linux/mfd/wm8994/pdata.h>
36 #include <linux/mfd/wm8994/gpio.h>
37
38 #include "wm8994.h"
39 #include "wm_hubs.h"
40
41 #define WM1811_JACKDET_MODE_NONE 0x0000
42 #define WM1811_JACKDET_MODE_JACK 0x0100
43 #define WM1811_JACKDET_MODE_MIC 0x0080
44 #define WM1811_JACKDET_MODE_AUDIO 0x0180
45
46 #define WM8994_NUM_DRC 3
47 #define WM8994_NUM_EQ 3
48
49 static struct {
50 unsigned int reg;
51 unsigned int mask;
52 } wm8994_vu_bits[] = {
53 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
54 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
55 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
56 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
57 { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
58 { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
59 { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
60 { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
61 { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
62 { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
63
64 { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
65 { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
66 { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
67 { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
68 { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
69 { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
70 { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
71 { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
72 { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
73 { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
74 { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
75 { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
76 { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
77 { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
78 { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
79 { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
80 };
81
82 static int wm8994_drc_base[] = {
83 WM8994_AIF1_DRC1_1,
84 WM8994_AIF1_DRC2_1,
85 WM8994_AIF2_DRC_1,
86 };
87
88 static int wm8994_retune_mobile_base[] = {
89 WM8994_AIF1_DAC1_EQ_GAINS_1,
90 WM8994_AIF1_DAC2_EQ_GAINS_1,
91 WM8994_AIF2_EQ_GAINS_1,
92 };
93
94 static void wm8958_default_micdet(u16 status, void *data);
95
96 static const struct wm8958_micd_rate micdet_rates[] = {
97 { 32768, true, 1, 4 },
98 { 32768, false, 1, 1 },
99 { 44100 * 256, true, 7, 10 },
100 { 44100 * 256, false, 7, 10 },
101 };
102
103 static const struct wm8958_micd_rate jackdet_rates[] = {
104 { 32768, true, 0, 1 },
105 { 32768, false, 0, 1 },
106 { 44100 * 256, true, 10, 10 },
107 { 44100 * 256, false, 7, 8 },
108 };
109
110 static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
111 {
112 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
113 int best, i, sysclk, val;
114 bool idle;
115 const struct wm8958_micd_rate *rates;
116 int num_rates;
117
118 if (!(wm8994->pdata && wm8994->pdata->micd_rates) &&
119 wm8994->jack_cb != wm8958_default_micdet)
120 return;
121
122 idle = !wm8994->jack_mic;
123
124 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
125 if (sysclk & WM8994_SYSCLK_SRC)
126 sysclk = wm8994->aifclk[1];
127 else
128 sysclk = wm8994->aifclk[0];
129
130 if (wm8994->pdata && wm8994->pdata->micd_rates) {
131 rates = wm8994->pdata->micd_rates;
132 num_rates = wm8994->pdata->num_micd_rates;
133 } else if (wm8994->jackdet) {
134 rates = jackdet_rates;
135 num_rates = ARRAY_SIZE(jackdet_rates);
136 } else {
137 rates = micdet_rates;
138 num_rates = ARRAY_SIZE(micdet_rates);
139 }
140
141 best = 0;
142 for (i = 0; i < num_rates; i++) {
143 if (rates[i].idle != idle)
144 continue;
145 if (abs(rates[i].sysclk - sysclk) <
146 abs(rates[best].sysclk - sysclk))
147 best = i;
148 else if (rates[best].idle != idle)
149 best = i;
150 }
151
152 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
153 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
154
155 dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n",
156 rates[best].start, rates[best].rate, sysclk,
157 idle ? "idle" : "active");
158
159 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
160 WM8958_MICD_BIAS_STARTTIME_MASK |
161 WM8958_MICD_RATE_MASK, val);
162 }
163
164 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
165 {
166 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
167 int rate;
168 int reg1 = 0;
169 int offset;
170
171 if (aif)
172 offset = 4;
173 else
174 offset = 0;
175
176 switch (wm8994->sysclk[aif]) {
177 case WM8994_SYSCLK_MCLK1:
178 rate = wm8994->mclk[0];
179 break;
180
181 case WM8994_SYSCLK_MCLK2:
182 reg1 |= 0x8;
183 rate = wm8994->mclk[1];
184 break;
185
186 case WM8994_SYSCLK_FLL1:
187 reg1 |= 0x10;
188 rate = wm8994->fll[0].out;
189 break;
190
191 case WM8994_SYSCLK_FLL2:
192 reg1 |= 0x18;
193 rate = wm8994->fll[1].out;
194 break;
195
196 default:
197 return -EINVAL;
198 }
199
200 if (rate >= 13500000) {
201 rate /= 2;
202 reg1 |= WM8994_AIF1CLK_DIV;
203
204 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
205 aif + 1, rate);
206 }
207
208 wm8994->aifclk[aif] = rate;
209
210 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
211 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
212 reg1);
213
214 return 0;
215 }
216
217 static int configure_clock(struct snd_soc_codec *codec)
218 {
219 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
220 int change, new;
221
222 /* Bring up the AIF clocks first */
223 configure_aif_clock(codec, 0);
224 configure_aif_clock(codec, 1);
225
226 /* Then switch CLK_SYS over to the higher of them; a change
227 * can only happen as a result of a clocking change which can
228 * only be made outside of DAPM so we can safely redo the
229 * clocking.
230 */
231
232 /* If they're equal it doesn't matter which is used */
233 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
234 wm8958_micd_set_rate(codec);
235 return 0;
236 }
237
238 if (wm8994->aifclk[0] < wm8994->aifclk[1])
239 new = WM8994_SYSCLK_SRC;
240 else
241 new = 0;
242
243 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
244 WM8994_SYSCLK_SRC, new);
245 if (change)
246 snd_soc_dapm_sync(&codec->dapm);
247
248 wm8958_micd_set_rate(codec);
249
250 return 0;
251 }
252
253 static int check_clk_sys(struct snd_soc_dapm_widget *source,
254 struct snd_soc_dapm_widget *sink)
255 {
256 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
257 const char *clk;
258
259 /* Check what we're currently using for CLK_SYS */
260 if (reg & WM8994_SYSCLK_SRC)
261 clk = "AIF2CLK";
262 else
263 clk = "AIF1CLK";
264
265 return strcmp(source->name, clk) == 0;
266 }
267
268 static const char *sidetone_hpf_text[] = {
269 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
270 };
271
272 static const struct soc_enum sidetone_hpf =
273 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
274
275 static const char *adc_hpf_text[] = {
276 "HiFi", "Voice 1", "Voice 2", "Voice 3"
277 };
278
279 static const struct soc_enum aif1adc1_hpf =
280 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
281
282 static const struct soc_enum aif1adc2_hpf =
283 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
284
285 static const struct soc_enum aif2adc_hpf =
286 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
287
288 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
289 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
290 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
291 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
292 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
293 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
294 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
295
296 #define WM8994_DRC_SWITCH(xname, reg, shift) \
297 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
298 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
299 .put = wm8994_put_drc_sw, \
300 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
301
302 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
303 struct snd_ctl_elem_value *ucontrol)
304 {
305 struct soc_mixer_control *mc =
306 (struct soc_mixer_control *)kcontrol->private_value;
307 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
308 int mask, ret;
309
310 /* Can't enable both ADC and DAC paths simultaneously */
311 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
312 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
313 WM8994_AIF1ADC1R_DRC_ENA_MASK;
314 else
315 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
316
317 ret = snd_soc_read(codec, mc->reg);
318 if (ret < 0)
319 return ret;
320 if (ret & mask)
321 return -EINVAL;
322
323 return snd_soc_put_volsw(kcontrol, ucontrol);
324 }
325
326 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
327 {
328 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
329 struct wm8994_pdata *pdata = wm8994->pdata;
330 int base = wm8994_drc_base[drc];
331 int cfg = wm8994->drc_cfg[drc];
332 int save, i;
333
334 /* Save any enables; the configuration should clear them. */
335 save = snd_soc_read(codec, base);
336 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
337 WM8994_AIF1ADC1R_DRC_ENA;
338
339 for (i = 0; i < WM8994_DRC_REGS; i++)
340 snd_soc_update_bits(codec, base + i, 0xffff,
341 pdata->drc_cfgs[cfg].regs[i]);
342
343 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
344 WM8994_AIF1ADC1L_DRC_ENA |
345 WM8994_AIF1ADC1R_DRC_ENA, save);
346 }
347
348 /* Icky as hell but saves code duplication */
349 static int wm8994_get_drc(const char *name)
350 {
351 if (strcmp(name, "AIF1DRC1 Mode") == 0)
352 return 0;
353 if (strcmp(name, "AIF1DRC2 Mode") == 0)
354 return 1;
355 if (strcmp(name, "AIF2DRC Mode") == 0)
356 return 2;
357 return -EINVAL;
358 }
359
360 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
361 struct snd_ctl_elem_value *ucontrol)
362 {
363 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
364 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
365 struct wm8994_pdata *pdata = wm8994->pdata;
366 int drc = wm8994_get_drc(kcontrol->id.name);
367 int value = ucontrol->value.integer.value[0];
368
369 if (drc < 0)
370 return drc;
371
372 if (value >= pdata->num_drc_cfgs)
373 return -EINVAL;
374
375 wm8994->drc_cfg[drc] = value;
376
377 wm8994_set_drc(codec, drc);
378
379 return 0;
380 }
381
382 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
383 struct snd_ctl_elem_value *ucontrol)
384 {
385 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
386 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
387 int drc = wm8994_get_drc(kcontrol->id.name);
388
389 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
390
391 return 0;
392 }
393
394 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
395 {
396 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
397 struct wm8994_pdata *pdata = wm8994->pdata;
398 int base = wm8994_retune_mobile_base[block];
399 int iface, best, best_val, save, i, cfg;
400
401 if (!pdata || !wm8994->num_retune_mobile_texts)
402 return;
403
404 switch (block) {
405 case 0:
406 case 1:
407 iface = 0;
408 break;
409 case 2:
410 iface = 1;
411 break;
412 default:
413 return;
414 }
415
416 /* Find the version of the currently selected configuration
417 * with the nearest sample rate. */
418 cfg = wm8994->retune_mobile_cfg[block];
419 best = 0;
420 best_val = INT_MAX;
421 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
422 if (strcmp(pdata->retune_mobile_cfgs[i].name,
423 wm8994->retune_mobile_texts[cfg]) == 0 &&
424 abs(pdata->retune_mobile_cfgs[i].rate
425 - wm8994->dac_rates[iface]) < best_val) {
426 best = i;
427 best_val = abs(pdata->retune_mobile_cfgs[i].rate
428 - wm8994->dac_rates[iface]);
429 }
430 }
431
432 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
433 block,
434 pdata->retune_mobile_cfgs[best].name,
435 pdata->retune_mobile_cfgs[best].rate,
436 wm8994->dac_rates[iface]);
437
438 /* The EQ will be disabled while reconfiguring it, remember the
439 * current configuration.
440 */
441 save = snd_soc_read(codec, base);
442 save &= WM8994_AIF1DAC1_EQ_ENA;
443
444 for (i = 0; i < WM8994_EQ_REGS; i++)
445 snd_soc_update_bits(codec, base + i, 0xffff,
446 pdata->retune_mobile_cfgs[best].regs[i]);
447
448 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
449 }
450
451 /* Icky as hell but saves code duplication */
452 static int wm8994_get_retune_mobile_block(const char *name)
453 {
454 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
455 return 0;
456 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
457 return 1;
458 if (strcmp(name, "AIF2 EQ Mode") == 0)
459 return 2;
460 return -EINVAL;
461 }
462
463 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
464 struct snd_ctl_elem_value *ucontrol)
465 {
466 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
467 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
468 struct wm8994_pdata *pdata = wm8994->pdata;
469 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
470 int value = ucontrol->value.integer.value[0];
471
472 if (block < 0)
473 return block;
474
475 if (value >= pdata->num_retune_mobile_cfgs)
476 return -EINVAL;
477
478 wm8994->retune_mobile_cfg[block] = value;
479
480 wm8994_set_retune_mobile(codec, block);
481
482 return 0;
483 }
484
485 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
486 struct snd_ctl_elem_value *ucontrol)
487 {
488 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
489 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
490 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
491
492 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
493
494 return 0;
495 }
496
497 static const char *aif_chan_src_text[] = {
498 "Left", "Right"
499 };
500
501 static const struct soc_enum aif1adcl_src =
502 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
503
504 static const struct soc_enum aif1adcr_src =
505 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
506
507 static const struct soc_enum aif2adcl_src =
508 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
509
510 static const struct soc_enum aif2adcr_src =
511 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
512
513 static const struct soc_enum aif1dacl_src =
514 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
515
516 static const struct soc_enum aif1dacr_src =
517 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
518
519 static const struct soc_enum aif2dacl_src =
520 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
521
522 static const struct soc_enum aif2dacr_src =
523 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
524
525 static const char *osr_text[] = {
526 "Low Power", "High Performance",
527 };
528
529 static const struct soc_enum dac_osr =
530 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
531
532 static const struct soc_enum adc_osr =
533 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
534
535 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
536 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
537 WM8994_AIF1_ADC1_RIGHT_VOLUME,
538 1, 119, 0, digital_tlv),
539 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
540 WM8994_AIF1_ADC2_RIGHT_VOLUME,
541 1, 119, 0, digital_tlv),
542 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
543 WM8994_AIF2_ADC_RIGHT_VOLUME,
544 1, 119, 0, digital_tlv),
545
546 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
547 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
548 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
549 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
550
551 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
552 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
553 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
554 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
555
556 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
557 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
558 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
559 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
560 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
561 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
562
563 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
564 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
565
566 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
567 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
568 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
569
570 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
571 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
572 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
573
574 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
575 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
576 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
577
578 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
579 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
580 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
581
582 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
583 5, 12, 0, st_tlv),
584 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
585 0, 12, 0, st_tlv),
586 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
587 5, 12, 0, st_tlv),
588 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
589 0, 12, 0, st_tlv),
590 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
591 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
592
593 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
594 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
595
596 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
597 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
598
599 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
600 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
601
602 SOC_ENUM("ADC OSR", adc_osr),
603 SOC_ENUM("DAC OSR", dac_osr),
604
605 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
606 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
607 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
608 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
609
610 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
611 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
612 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
613 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
614
615 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
616 6, 1, 1, wm_hubs_spkmix_tlv),
617 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
618 2, 1, 1, wm_hubs_spkmix_tlv),
619
620 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
621 6, 1, 1, wm_hubs_spkmix_tlv),
622 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
623 2, 1, 1, wm_hubs_spkmix_tlv),
624
625 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
626 10, 15, 0, wm8994_3d_tlv),
627 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
628 8, 1, 0),
629 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
630 10, 15, 0, wm8994_3d_tlv),
631 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
632 8, 1, 0),
633 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
634 10, 15, 0, wm8994_3d_tlv),
635 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
636 8, 1, 0),
637 };
638
639 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
640 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
641 eq_tlv),
642 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
643 eq_tlv),
644 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
645 eq_tlv),
646 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
647 eq_tlv),
648 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
649 eq_tlv),
650
651 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
652 eq_tlv),
653 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
654 eq_tlv),
655 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
656 eq_tlv),
657 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
658 eq_tlv),
659 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
660 eq_tlv),
661
662 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
663 eq_tlv),
664 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
665 eq_tlv),
666 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
667 eq_tlv),
668 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
669 eq_tlv),
670 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
671 eq_tlv),
672 };
673
674 static const struct snd_kcontrol_new wm8994_drc_controls[] = {
675 SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5,
676 WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
677 WM8994_AIF1ADC1R_DRC_ENA),
678 SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5,
679 WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA |
680 WM8994_AIF1ADC2R_DRC_ENA),
681 SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5,
682 WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA |
683 WM8994_AIF2ADCR_DRC_ENA),
684 };
685
686 static const char *wm8958_ng_text[] = {
687 "30ms", "125ms", "250ms", "500ms",
688 };
689
690 static const struct soc_enum wm8958_aif1dac1_ng_hold =
691 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
692 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
693
694 static const struct soc_enum wm8958_aif1dac2_ng_hold =
695 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
696 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
697
698 static const struct soc_enum wm8958_aif2dac_ng_hold =
699 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
700 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
701
702 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
703 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
704
705 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
706 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
707 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
708 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
709 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
710 7, 1, ng_tlv),
711
712 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
713 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
714 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
715 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
716 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
717 7, 1, ng_tlv),
718
719 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
720 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
721 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
722 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
723 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
724 7, 1, ng_tlv),
725 };
726
727 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
728 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
729 mixin_boost_tlv),
730 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
731 mixin_boost_tlv),
732 };
733
734 /* We run all mode setting through a function to enforce audio mode */
735 static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
736 {
737 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
738
739 if (!wm8994->jackdet || !wm8994->jack_cb)
740 return;
741
742 if (wm8994->active_refcount)
743 mode = WM1811_JACKDET_MODE_AUDIO;
744
745 if (mode == wm8994->jackdet_mode)
746 return;
747
748 wm8994->jackdet_mode = mode;
749
750 /* Always use audio mode to detect while the system is active */
751 if (mode != WM1811_JACKDET_MODE_NONE)
752 mode = WM1811_JACKDET_MODE_AUDIO;
753
754 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
755 WM1811_JACKDET_MODE_MASK, mode);
756 }
757
758 static void active_reference(struct snd_soc_codec *codec)
759 {
760 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
761
762 mutex_lock(&wm8994->accdet_lock);
763
764 wm8994->active_refcount++;
765
766 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
767 wm8994->active_refcount);
768
769 /* If we're using jack detection go into audio mode */
770 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
771
772 mutex_unlock(&wm8994->accdet_lock);
773 }
774
775 static void active_dereference(struct snd_soc_codec *codec)
776 {
777 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
778 u16 mode;
779
780 mutex_lock(&wm8994->accdet_lock);
781
782 wm8994->active_refcount--;
783
784 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
785 wm8994->active_refcount);
786
787 if (wm8994->active_refcount == 0) {
788 /* Go into appropriate detection only mode */
789 if (wm8994->jack_mic || wm8994->mic_detecting)
790 mode = WM1811_JACKDET_MODE_MIC;
791 else
792 mode = WM1811_JACKDET_MODE_JACK;
793
794 wm1811_jackdet_set_mode(codec, mode);
795 }
796
797 mutex_unlock(&wm8994->accdet_lock);
798 }
799
800 static int clk_sys_event(struct snd_soc_dapm_widget *w,
801 struct snd_kcontrol *kcontrol, int event)
802 {
803 struct snd_soc_codec *codec = w->codec;
804 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
805
806 switch (event) {
807 case SND_SOC_DAPM_PRE_PMU:
808 return configure_clock(codec);
809
810 case SND_SOC_DAPM_POST_PMU:
811 /*
812 * JACKDET won't run until we start the clock and it
813 * only reports deltas, make sure we notify the state
814 * up the stack on startup. Use a *very* generous
815 * timeout for paranoia, there's no urgency and we
816 * don't want false reports.
817 */
818 if (wm8994->jackdet && !wm8994->clk_has_run) {
819 schedule_delayed_work(&wm8994->jackdet_bootstrap,
820 msecs_to_jiffies(1000));
821 wm8994->clk_has_run = true;
822 }
823 break;
824
825 case SND_SOC_DAPM_POST_PMD:
826 configure_clock(codec);
827 break;
828 }
829
830 return 0;
831 }
832
833 static void vmid_reference(struct snd_soc_codec *codec)
834 {
835 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
836
837 pm_runtime_get_sync(codec->dev);
838
839 wm8994->vmid_refcount++;
840
841 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
842 wm8994->vmid_refcount);
843
844 if (wm8994->vmid_refcount == 1) {
845 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
846 WM8994_LINEOUT1_DISCH |
847 WM8994_LINEOUT2_DISCH, 0);
848
849 wm_hubs_vmid_ena(codec);
850
851 switch (wm8994->vmid_mode) {
852 default:
853 WARN_ON(NULL == "Invalid VMID mode");
854 case WM8994_VMID_NORMAL:
855 /* Startup bias, VMID ramp & buffer */
856 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
857 WM8994_BIAS_SRC |
858 WM8994_VMID_DISCH |
859 WM8994_STARTUP_BIAS_ENA |
860 WM8994_VMID_BUF_ENA |
861 WM8994_VMID_RAMP_MASK,
862 WM8994_BIAS_SRC |
863 WM8994_STARTUP_BIAS_ENA |
864 WM8994_VMID_BUF_ENA |
865 (0x2 << WM8994_VMID_RAMP_SHIFT));
866
867 /* Main bias enable, VMID=2x40k */
868 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
869 WM8994_BIAS_ENA |
870 WM8994_VMID_SEL_MASK,
871 WM8994_BIAS_ENA | 0x2);
872
873 msleep(300);
874
875 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
876 WM8994_VMID_RAMP_MASK |
877 WM8994_BIAS_SRC,
878 0);
879 break;
880
881 case WM8994_VMID_FORCE:
882 /* Startup bias, slow VMID ramp & buffer */
883 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
884 WM8994_BIAS_SRC |
885 WM8994_VMID_DISCH |
886 WM8994_STARTUP_BIAS_ENA |
887 WM8994_VMID_BUF_ENA |
888 WM8994_VMID_RAMP_MASK,
889 WM8994_BIAS_SRC |
890 WM8994_STARTUP_BIAS_ENA |
891 WM8994_VMID_BUF_ENA |
892 (0x2 << WM8994_VMID_RAMP_SHIFT));
893
894 /* Main bias enable, VMID=2x40k */
895 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
896 WM8994_BIAS_ENA |
897 WM8994_VMID_SEL_MASK,
898 WM8994_BIAS_ENA | 0x2);
899
900 msleep(400);
901
902 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
903 WM8994_VMID_RAMP_MASK |
904 WM8994_BIAS_SRC,
905 0);
906 break;
907 }
908 }
909 }
910
911 static void vmid_dereference(struct snd_soc_codec *codec)
912 {
913 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
914
915 wm8994->vmid_refcount--;
916
917 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
918 wm8994->vmid_refcount);
919
920 if (wm8994->vmid_refcount == 0) {
921 if (wm8994->hubs.lineout1_se)
922 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
923 WM8994_LINEOUT1N_ENA |
924 WM8994_LINEOUT1P_ENA,
925 WM8994_LINEOUT1N_ENA |
926 WM8994_LINEOUT1P_ENA);
927
928 if (wm8994->hubs.lineout2_se)
929 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
930 WM8994_LINEOUT2N_ENA |
931 WM8994_LINEOUT2P_ENA,
932 WM8994_LINEOUT2N_ENA |
933 WM8994_LINEOUT2P_ENA);
934
935 /* Start discharging VMID */
936 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
937 WM8994_BIAS_SRC |
938 WM8994_VMID_DISCH,
939 WM8994_BIAS_SRC |
940 WM8994_VMID_DISCH);
941
942 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
943 WM8994_VMID_SEL_MASK, 0);
944
945 msleep(400);
946
947 /* Active discharge */
948 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
949 WM8994_LINEOUT1_DISCH |
950 WM8994_LINEOUT2_DISCH,
951 WM8994_LINEOUT1_DISCH |
952 WM8994_LINEOUT2_DISCH);
953
954 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
955 WM8994_LINEOUT1N_ENA |
956 WM8994_LINEOUT1P_ENA |
957 WM8994_LINEOUT2N_ENA |
958 WM8994_LINEOUT2P_ENA, 0);
959
960 /* Switch off startup biases */
961 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
962 WM8994_BIAS_SRC |
963 WM8994_STARTUP_BIAS_ENA |
964 WM8994_VMID_BUF_ENA |
965 WM8994_VMID_RAMP_MASK, 0);
966
967 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
968 WM8994_VMID_SEL_MASK, 0);
969 }
970
971 pm_runtime_put(codec->dev);
972 }
973
974 static int vmid_event(struct snd_soc_dapm_widget *w,
975 struct snd_kcontrol *kcontrol, int event)
976 {
977 struct snd_soc_codec *codec = w->codec;
978
979 switch (event) {
980 case SND_SOC_DAPM_PRE_PMU:
981 vmid_reference(codec);
982 break;
983
984 case SND_SOC_DAPM_POST_PMD:
985 vmid_dereference(codec);
986 break;
987 }
988
989 return 0;
990 }
991
992 static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec)
993 {
994 int source = 0; /* GCC flow analysis can't track enable */
995 int reg, reg_r;
996
997 /* We also need the same AIF source for L/R and only one path */
998 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
999 switch (reg) {
1000 case WM8994_AIF2DACL_TO_DAC1L:
1001 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
1002 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1003 break;
1004 case WM8994_AIF1DAC2L_TO_DAC1L:
1005 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
1006 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1007 break;
1008 case WM8994_AIF1DAC1L_TO_DAC1L:
1009 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
1010 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1011 break;
1012 default:
1013 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
1014 return false;
1015 }
1016
1017 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1018 if (reg_r != reg) {
1019 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
1020 return false;
1021 }
1022
1023 /* Set the source up */
1024 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1025 WM8994_CP_DYN_SRC_SEL_MASK, source);
1026
1027 return true;
1028 }
1029
1030 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1031 struct snd_kcontrol *kcontrol, int event)
1032 {
1033 struct snd_soc_codec *codec = w->codec;
1034 struct wm8994 *control = codec->control_data;
1035 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
1036 int i;
1037 int dac;
1038 int adc;
1039 int val;
1040
1041 switch (control->type) {
1042 case WM8994:
1043 case WM8958:
1044 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1045 break;
1046 default:
1047 break;
1048 }
1049
1050 switch (event) {
1051 case SND_SOC_DAPM_PRE_PMU:
1052 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
1053 if ((val & WM8994_AIF1ADCL_SRC) &&
1054 (val & WM8994_AIF1ADCR_SRC))
1055 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1056 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1057 !(val & WM8994_AIF1ADCR_SRC))
1058 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1059 else
1060 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1061 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1062
1063 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
1064 if ((val & WM8994_AIF1DACL_SRC) &&
1065 (val & WM8994_AIF1DACR_SRC))
1066 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1067 else if (!(val & WM8994_AIF1DACL_SRC) &&
1068 !(val & WM8994_AIF1DACR_SRC))
1069 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1070 else
1071 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1072 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1073
1074 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1075 mask, adc);
1076 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1077 mask, dac);
1078 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1079 WM8994_AIF1DSPCLK_ENA |
1080 WM8994_SYSDSPCLK_ENA,
1081 WM8994_AIF1DSPCLK_ENA |
1082 WM8994_SYSDSPCLK_ENA);
1083 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
1084 WM8994_AIF1ADC1R_ENA |
1085 WM8994_AIF1ADC1L_ENA |
1086 WM8994_AIF1ADC2R_ENA |
1087 WM8994_AIF1ADC2L_ENA);
1088 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
1089 WM8994_AIF1DAC1R_ENA |
1090 WM8994_AIF1DAC1L_ENA |
1091 WM8994_AIF1DAC2R_ENA |
1092 WM8994_AIF1DAC2L_ENA);
1093 break;
1094
1095 case SND_SOC_DAPM_POST_PMU:
1096 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1097 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1098 snd_soc_read(codec,
1099 wm8994_vu_bits[i].reg));
1100 break;
1101
1102 case SND_SOC_DAPM_PRE_PMD:
1103 case SND_SOC_DAPM_POST_PMD:
1104 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1105 mask, 0);
1106 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1107 mask, 0);
1108
1109 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1110 if (val & WM8994_AIF2DSPCLK_ENA)
1111 val = WM8994_SYSDSPCLK_ENA;
1112 else
1113 val = 0;
1114 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1115 WM8994_SYSDSPCLK_ENA |
1116 WM8994_AIF1DSPCLK_ENA, val);
1117 break;
1118 }
1119
1120 return 0;
1121 }
1122
1123 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1124 struct snd_kcontrol *kcontrol, int event)
1125 {
1126 struct snd_soc_codec *codec = w->codec;
1127 int i;
1128 int dac;
1129 int adc;
1130 int val;
1131
1132 switch (event) {
1133 case SND_SOC_DAPM_PRE_PMU:
1134 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1135 if ((val & WM8994_AIF2ADCL_SRC) &&
1136 (val & WM8994_AIF2ADCR_SRC))
1137 adc = WM8994_AIF2ADCR_ENA;
1138 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1139 !(val & WM8994_AIF2ADCR_SRC))
1140 adc = WM8994_AIF2ADCL_ENA;
1141 else
1142 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1143
1144
1145 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1146 if ((val & WM8994_AIF2DACL_SRC) &&
1147 (val & WM8994_AIF2DACR_SRC))
1148 dac = WM8994_AIF2DACR_ENA;
1149 else if (!(val & WM8994_AIF2DACL_SRC) &&
1150 !(val & WM8994_AIF2DACR_SRC))
1151 dac = WM8994_AIF2DACL_ENA;
1152 else
1153 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1154
1155 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1156 WM8994_AIF2ADCL_ENA |
1157 WM8994_AIF2ADCR_ENA, adc);
1158 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1159 WM8994_AIF2DACL_ENA |
1160 WM8994_AIF2DACR_ENA, dac);
1161 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1162 WM8994_AIF2DSPCLK_ENA |
1163 WM8994_SYSDSPCLK_ENA,
1164 WM8994_AIF2DSPCLK_ENA |
1165 WM8994_SYSDSPCLK_ENA);
1166 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1167 WM8994_AIF2ADCL_ENA |
1168 WM8994_AIF2ADCR_ENA,
1169 WM8994_AIF2ADCL_ENA |
1170 WM8994_AIF2ADCR_ENA);
1171 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1172 WM8994_AIF2DACL_ENA |
1173 WM8994_AIF2DACR_ENA,
1174 WM8994_AIF2DACL_ENA |
1175 WM8994_AIF2DACR_ENA);
1176 break;
1177
1178 case SND_SOC_DAPM_POST_PMU:
1179 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1180 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1181 snd_soc_read(codec,
1182 wm8994_vu_bits[i].reg));
1183 break;
1184
1185 case SND_SOC_DAPM_PRE_PMD:
1186 case SND_SOC_DAPM_POST_PMD:
1187 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1188 WM8994_AIF2DACL_ENA |
1189 WM8994_AIF2DACR_ENA, 0);
1190 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1191 WM8994_AIF2ADCL_ENA |
1192 WM8994_AIF2ADCR_ENA, 0);
1193
1194 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1195 if (val & WM8994_AIF1DSPCLK_ENA)
1196 val = WM8994_SYSDSPCLK_ENA;
1197 else
1198 val = 0;
1199 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1200 WM8994_SYSDSPCLK_ENA |
1201 WM8994_AIF2DSPCLK_ENA, val);
1202 break;
1203 }
1204
1205 return 0;
1206 }
1207
1208 static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1209 struct snd_kcontrol *kcontrol, int event)
1210 {
1211 struct snd_soc_codec *codec = w->codec;
1212 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1213
1214 switch (event) {
1215 case SND_SOC_DAPM_PRE_PMU:
1216 wm8994->aif1clk_enable = 1;
1217 break;
1218 case SND_SOC_DAPM_POST_PMD:
1219 wm8994->aif1clk_disable = 1;
1220 break;
1221 }
1222
1223 return 0;
1224 }
1225
1226 static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1227 struct snd_kcontrol *kcontrol, int event)
1228 {
1229 struct snd_soc_codec *codec = w->codec;
1230 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1231
1232 switch (event) {
1233 case SND_SOC_DAPM_PRE_PMU:
1234 wm8994->aif2clk_enable = 1;
1235 break;
1236 case SND_SOC_DAPM_POST_PMD:
1237 wm8994->aif2clk_disable = 1;
1238 break;
1239 }
1240
1241 return 0;
1242 }
1243
1244 static int late_enable_ev(struct snd_soc_dapm_widget *w,
1245 struct snd_kcontrol *kcontrol, int event)
1246 {
1247 struct snd_soc_codec *codec = w->codec;
1248 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1249
1250 switch (event) {
1251 case SND_SOC_DAPM_PRE_PMU:
1252 if (wm8994->aif1clk_enable) {
1253 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1254 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1255 WM8994_AIF1CLK_ENA_MASK,
1256 WM8994_AIF1CLK_ENA);
1257 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1258 wm8994->aif1clk_enable = 0;
1259 }
1260 if (wm8994->aif2clk_enable) {
1261 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1262 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1263 WM8994_AIF2CLK_ENA_MASK,
1264 WM8994_AIF2CLK_ENA);
1265 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1266 wm8994->aif2clk_enable = 0;
1267 }
1268 break;
1269 }
1270
1271 /* We may also have postponed startup of DSP, handle that. */
1272 wm8958_aif_ev(w, kcontrol, event);
1273
1274 return 0;
1275 }
1276
1277 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1278 struct snd_kcontrol *kcontrol, int event)
1279 {
1280 struct snd_soc_codec *codec = w->codec;
1281 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1282
1283 switch (event) {
1284 case SND_SOC_DAPM_POST_PMD:
1285 if (wm8994->aif1clk_disable) {
1286 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1287 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1288 WM8994_AIF1CLK_ENA_MASK, 0);
1289 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1290 wm8994->aif1clk_disable = 0;
1291 }
1292 if (wm8994->aif2clk_disable) {
1293 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1294 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1295 WM8994_AIF2CLK_ENA_MASK, 0);
1296 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1297 wm8994->aif2clk_disable = 0;
1298 }
1299 break;
1300 }
1301
1302 return 0;
1303 }
1304
1305 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1306 struct snd_kcontrol *kcontrol, int event)
1307 {
1308 late_enable_ev(w, kcontrol, event);
1309 return 0;
1310 }
1311
1312 static int micbias_ev(struct snd_soc_dapm_widget *w,
1313 struct snd_kcontrol *kcontrol, int event)
1314 {
1315 late_enable_ev(w, kcontrol, event);
1316 return 0;
1317 }
1318
1319 static int dac_ev(struct snd_soc_dapm_widget *w,
1320 struct snd_kcontrol *kcontrol, int event)
1321 {
1322 struct snd_soc_codec *codec = w->codec;
1323 unsigned int mask = 1 << w->shift;
1324
1325 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1326 mask, mask);
1327 return 0;
1328 }
1329
1330 static const char *adc_mux_text[] = {
1331 "ADC",
1332 "DMIC",
1333 };
1334
1335 static const struct soc_enum adc_enum =
1336 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1337
1338 static const struct snd_kcontrol_new adcl_mux =
1339 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1340
1341 static const struct snd_kcontrol_new adcr_mux =
1342 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1343
1344 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1345 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1346 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1347 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1348 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1349 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1350 };
1351
1352 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1353 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1354 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1355 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1356 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1357 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1358 };
1359
1360 /* Debugging; dump chip status after DAPM transitions */
1361 static int post_ev(struct snd_soc_dapm_widget *w,
1362 struct snd_kcontrol *kcontrol, int event)
1363 {
1364 struct snd_soc_codec *codec = w->codec;
1365 dev_dbg(codec->dev, "SRC status: %x\n",
1366 snd_soc_read(codec,
1367 WM8994_RATE_STATUS));
1368 return 0;
1369 }
1370
1371 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1372 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1373 1, 1, 0),
1374 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1375 0, 1, 0),
1376 };
1377
1378 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1379 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1380 1, 1, 0),
1381 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1382 0, 1, 0),
1383 };
1384
1385 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1386 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1387 1, 1, 0),
1388 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1389 0, 1, 0),
1390 };
1391
1392 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1393 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1394 1, 1, 0),
1395 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1396 0, 1, 0),
1397 };
1398
1399 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1400 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1401 5, 1, 0),
1402 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1403 4, 1, 0),
1404 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1405 2, 1, 0),
1406 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1407 1, 1, 0),
1408 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1409 0, 1, 0),
1410 };
1411
1412 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1413 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1414 5, 1, 0),
1415 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1416 4, 1, 0),
1417 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1418 2, 1, 0),
1419 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1420 1, 1, 0),
1421 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1422 0, 1, 0),
1423 };
1424
1425 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1426 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1427 .info = snd_soc_info_volsw, \
1428 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1429 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1430
1431 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1432 struct snd_ctl_elem_value *ucontrol)
1433 {
1434 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1435 struct snd_soc_dapm_widget *w = wlist->widgets[0];
1436 struct snd_soc_codec *codec = w->codec;
1437 int ret;
1438
1439 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1440
1441 wm_hubs_update_class_w(codec);
1442
1443 return ret;
1444 }
1445
1446 static const struct snd_kcontrol_new dac1l_mix[] = {
1447 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1448 5, 1, 0),
1449 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1450 4, 1, 0),
1451 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1452 2, 1, 0),
1453 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1454 1, 1, 0),
1455 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1456 0, 1, 0),
1457 };
1458
1459 static const struct snd_kcontrol_new dac1r_mix[] = {
1460 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1461 5, 1, 0),
1462 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1463 4, 1, 0),
1464 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1465 2, 1, 0),
1466 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1467 1, 1, 0),
1468 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1469 0, 1, 0),
1470 };
1471
1472 static const char *sidetone_text[] = {
1473 "ADC/DMIC1", "DMIC2",
1474 };
1475
1476 static const struct soc_enum sidetone1_enum =
1477 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1478
1479 static const struct snd_kcontrol_new sidetone1_mux =
1480 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1481
1482 static const struct soc_enum sidetone2_enum =
1483 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1484
1485 static const struct snd_kcontrol_new sidetone2_mux =
1486 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1487
1488 static const char *aif1dac_text[] = {
1489 "AIF1DACDAT", "AIF3DACDAT",
1490 };
1491
1492 static const struct soc_enum aif1dac_enum =
1493 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1494
1495 static const struct snd_kcontrol_new aif1dac_mux =
1496 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1497
1498 static const char *aif2dac_text[] = {
1499 "AIF2DACDAT", "AIF3DACDAT",
1500 };
1501
1502 static const struct soc_enum aif2dac_enum =
1503 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1504
1505 static const struct snd_kcontrol_new aif2dac_mux =
1506 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1507
1508 static const char *aif2adc_text[] = {
1509 "AIF2ADCDAT", "AIF3DACDAT",
1510 };
1511
1512 static const struct soc_enum aif2adc_enum =
1513 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1514
1515 static const struct snd_kcontrol_new aif2adc_mux =
1516 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1517
1518 static const char *aif3adc_text[] = {
1519 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1520 };
1521
1522 static const struct soc_enum wm8994_aif3adc_enum =
1523 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1524
1525 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1526 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1527
1528 static const struct soc_enum wm8958_aif3adc_enum =
1529 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1530
1531 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1532 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1533
1534 static const char *mono_pcm_out_text[] = {
1535 "None", "AIF2ADCL", "AIF2ADCR",
1536 };
1537
1538 static const struct soc_enum mono_pcm_out_enum =
1539 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1540
1541 static const struct snd_kcontrol_new mono_pcm_out_mux =
1542 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1543
1544 static const char *aif2dac_src_text[] = {
1545 "AIF2", "AIF3",
1546 };
1547
1548 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1549 static const struct soc_enum aif2dacl_src_enum =
1550 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1551
1552 static const struct snd_kcontrol_new aif2dacl_src_mux =
1553 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1554
1555 static const struct soc_enum aif2dacr_src_enum =
1556 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1557
1558 static const struct snd_kcontrol_new aif2dacr_src_mux =
1559 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1560
1561 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1562 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
1563 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1564 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
1565 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1566
1567 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1568 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1569 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1570 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1571 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1572 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1573 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1574 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1575 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1576 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1577
1578 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1579 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1580 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1581 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1582 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1583 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1584 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
1585 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1586 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
1587 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1588
1589 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1590 };
1591
1592 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1593 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
1594 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1595 SND_SOC_DAPM_PRE_PMD),
1596 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
1597 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1598 SND_SOC_DAPM_PRE_PMD),
1599 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1600 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1601 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1602 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1603 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1604 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1605 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
1606 };
1607
1608 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1609 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1610 dac_ev, SND_SOC_DAPM_PRE_PMU),
1611 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1612 dac_ev, SND_SOC_DAPM_PRE_PMU),
1613 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1614 dac_ev, SND_SOC_DAPM_PRE_PMU),
1615 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1616 dac_ev, SND_SOC_DAPM_PRE_PMU),
1617 };
1618
1619 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1620 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1621 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1622 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1623 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1624 };
1625
1626 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1627 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1628 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1629 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1630 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1631 };
1632
1633 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1634 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1635 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1636 };
1637
1638 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1639 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1640 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1641 SND_SOC_DAPM_INPUT("Clock"),
1642
1643 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1644 SND_SOC_DAPM_PRE_PMU),
1645 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1646 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1647
1648 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1649 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1650 SND_SOC_DAPM_PRE_PMD),
1651
1652 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1653 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1654 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
1655
1656 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1657 0, SND_SOC_NOPM, 9, 0),
1658 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1659 0, SND_SOC_NOPM, 8, 0),
1660 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1661 SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
1662 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1663 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1664 SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
1665 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1666
1667 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1668 0, SND_SOC_NOPM, 11, 0),
1669 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1670 0, SND_SOC_NOPM, 10, 0),
1671 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1672 SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
1673 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1674 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1675 SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
1676 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1677
1678 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1679 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1680 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1681 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1682
1683 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1684 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1685 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1686 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1687
1688 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1689 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1690 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1691 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1692
1693 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1694 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1695
1696 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1697 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1698 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1699 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1700
1701 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1702 SND_SOC_NOPM, 13, 0),
1703 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1704 SND_SOC_NOPM, 12, 0),
1705 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1706 SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
1707 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1708 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1709 SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
1710 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1711
1712 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1713 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1714 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1715 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1716
1717 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1718 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1719 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1720
1721 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1722 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1723
1724 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1725
1726 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1727 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1728 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1729 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1730
1731 /* Power is done with the muxes since the ADC power also controls the
1732 * downsampling chain, the chip will automatically manage the analogue
1733 * specific portions.
1734 */
1735 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1736 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1737
1738 SND_SOC_DAPM_POST("Debug log", post_ev),
1739 };
1740
1741 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1742 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1743 };
1744
1745 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1746 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
1747 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1748 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1749 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1750 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1751 };
1752
1753 static const struct snd_soc_dapm_route intercon[] = {
1754 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1755 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1756
1757 { "DSP1CLK", NULL, "CLK_SYS" },
1758 { "DSP2CLK", NULL, "CLK_SYS" },
1759 { "DSPINTCLK", NULL, "CLK_SYS" },
1760
1761 { "AIF1ADC1L", NULL, "AIF1CLK" },
1762 { "AIF1ADC1L", NULL, "DSP1CLK" },
1763 { "AIF1ADC1R", NULL, "AIF1CLK" },
1764 { "AIF1ADC1R", NULL, "DSP1CLK" },
1765 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1766
1767 { "AIF1DAC1L", NULL, "AIF1CLK" },
1768 { "AIF1DAC1L", NULL, "DSP1CLK" },
1769 { "AIF1DAC1R", NULL, "AIF1CLK" },
1770 { "AIF1DAC1R", NULL, "DSP1CLK" },
1771 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1772
1773 { "AIF1ADC2L", NULL, "AIF1CLK" },
1774 { "AIF1ADC2L", NULL, "DSP1CLK" },
1775 { "AIF1ADC2R", NULL, "AIF1CLK" },
1776 { "AIF1ADC2R", NULL, "DSP1CLK" },
1777 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1778
1779 { "AIF1DAC2L", NULL, "AIF1CLK" },
1780 { "AIF1DAC2L", NULL, "DSP1CLK" },
1781 { "AIF1DAC2R", NULL, "AIF1CLK" },
1782 { "AIF1DAC2R", NULL, "DSP1CLK" },
1783 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1784
1785 { "AIF2ADCL", NULL, "AIF2CLK" },
1786 { "AIF2ADCL", NULL, "DSP2CLK" },
1787 { "AIF2ADCR", NULL, "AIF2CLK" },
1788 { "AIF2ADCR", NULL, "DSP2CLK" },
1789 { "AIF2ADCR", NULL, "DSPINTCLK" },
1790
1791 { "AIF2DACL", NULL, "AIF2CLK" },
1792 { "AIF2DACL", NULL, "DSP2CLK" },
1793 { "AIF2DACR", NULL, "AIF2CLK" },
1794 { "AIF2DACR", NULL, "DSP2CLK" },
1795 { "AIF2DACR", NULL, "DSPINTCLK" },
1796
1797 { "DMIC1L", NULL, "DMIC1DAT" },
1798 { "DMIC1L", NULL, "CLK_SYS" },
1799 { "DMIC1R", NULL, "DMIC1DAT" },
1800 { "DMIC1R", NULL, "CLK_SYS" },
1801 { "DMIC2L", NULL, "DMIC2DAT" },
1802 { "DMIC2L", NULL, "CLK_SYS" },
1803 { "DMIC2R", NULL, "DMIC2DAT" },
1804 { "DMIC2R", NULL, "CLK_SYS" },
1805
1806 { "ADCL", NULL, "AIF1CLK" },
1807 { "ADCL", NULL, "DSP1CLK" },
1808 { "ADCL", NULL, "DSPINTCLK" },
1809
1810 { "ADCR", NULL, "AIF1CLK" },
1811 { "ADCR", NULL, "DSP1CLK" },
1812 { "ADCR", NULL, "DSPINTCLK" },
1813
1814 { "ADCL Mux", "ADC", "ADCL" },
1815 { "ADCL Mux", "DMIC", "DMIC1L" },
1816 { "ADCR Mux", "ADC", "ADCR" },
1817 { "ADCR Mux", "DMIC", "DMIC1R" },
1818
1819 { "DAC1L", NULL, "AIF1CLK" },
1820 { "DAC1L", NULL, "DSP1CLK" },
1821 { "DAC1L", NULL, "DSPINTCLK" },
1822
1823 { "DAC1R", NULL, "AIF1CLK" },
1824 { "DAC1R", NULL, "DSP1CLK" },
1825 { "DAC1R", NULL, "DSPINTCLK" },
1826
1827 { "DAC2L", NULL, "AIF2CLK" },
1828 { "DAC2L", NULL, "DSP2CLK" },
1829 { "DAC2L", NULL, "DSPINTCLK" },
1830
1831 { "DAC2R", NULL, "AIF2DACR" },
1832 { "DAC2R", NULL, "AIF2CLK" },
1833 { "DAC2R", NULL, "DSP2CLK" },
1834 { "DAC2R", NULL, "DSPINTCLK" },
1835
1836 { "TOCLK", NULL, "CLK_SYS" },
1837
1838 { "AIF1DACDAT", NULL, "AIF1 Playback" },
1839 { "AIF2DACDAT", NULL, "AIF2 Playback" },
1840 { "AIF3DACDAT", NULL, "AIF3 Playback" },
1841
1842 { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1843 { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1844 { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1845
1846 /* AIF1 outputs */
1847 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1848 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1849 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1850
1851 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1852 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1853 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1854
1855 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1856 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1857 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1858
1859 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1860 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1861 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1862
1863 /* Pin level routing for AIF3 */
1864 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1865 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1866 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1867 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1868
1869 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1870 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1871 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1872 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1873 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1874 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1875 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1876
1877 /* DAC1 inputs */
1878 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1879 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1880 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1881 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1882 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1883
1884 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1885 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1886 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1887 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1888 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1889
1890 /* DAC2/AIF2 outputs */
1891 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1892 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1893 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1894 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1895 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1896 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1897
1898 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1899 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1900 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1901 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1902 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1903 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1904
1905 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1906 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1907 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1908 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1909
1910 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1911
1912 /* AIF3 output */
1913 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1914 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1915 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1916 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1917 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1918 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1919 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1920 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1921
1922 /* Sidetone */
1923 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1924 { "Left Sidetone", "DMIC2", "DMIC2L" },
1925 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1926 { "Right Sidetone", "DMIC2", "DMIC2R" },
1927
1928 /* Output stages */
1929 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1930 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1931
1932 { "SPKL", "DAC1 Switch", "DAC1L" },
1933 { "SPKL", "DAC2 Switch", "DAC2L" },
1934
1935 { "SPKR", "DAC1 Switch", "DAC1R" },
1936 { "SPKR", "DAC2 Switch", "DAC2R" },
1937
1938 { "Left Headphone Mux", "DAC", "DAC1L" },
1939 { "Right Headphone Mux", "DAC", "DAC1R" },
1940 };
1941
1942 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1943 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1944 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1945 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1946 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1947 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1948 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1949 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1950 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1951 };
1952
1953 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1954 { "DAC1L", NULL, "DAC1L Mixer" },
1955 { "DAC1R", NULL, "DAC1R Mixer" },
1956 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1957 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1958 };
1959
1960 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1961 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1962 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1963 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1964 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1965 { "MICBIAS1", NULL, "CLK_SYS" },
1966 { "MICBIAS1", NULL, "MICBIAS Supply" },
1967 { "MICBIAS2", NULL, "CLK_SYS" },
1968 { "MICBIAS2", NULL, "MICBIAS Supply" },
1969 };
1970
1971 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1972 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1973 { "AIF2DACR", NULL, "AIF2DAC Mux" },
1974 { "MICBIAS1", NULL, "VMID" },
1975 { "MICBIAS2", NULL, "VMID" },
1976 };
1977
1978 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1979 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1980 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1981
1982 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1983 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1984 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1985 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1986
1987 { "AIF3DACDAT", NULL, "AIF3" },
1988 { "AIF3ADCDAT", NULL, "AIF3" },
1989
1990 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1991 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1992
1993 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1994 };
1995
1996 /* The size in bits of the FLL divide multiplied by 10
1997 * to allow rounding later */
1998 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1999
2000 struct fll_div {
2001 u16 outdiv;
2002 u16 n;
2003 u16 k;
2004 u16 clk_ref_div;
2005 u16 fll_fratio;
2006 };
2007
2008 static int wm8994_get_fll_config(struct fll_div *fll,
2009 int freq_in, int freq_out)
2010 {
2011 u64 Kpart;
2012 unsigned int K, Ndiv, Nmod;
2013
2014 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2015
2016 /* Scale the input frequency down to <= 13.5MHz */
2017 fll->clk_ref_div = 0;
2018 while (freq_in > 13500000) {
2019 fll->clk_ref_div++;
2020 freq_in /= 2;
2021
2022 if (fll->clk_ref_div > 3)
2023 return -EINVAL;
2024 }
2025 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2026
2027 /* Scale the output to give 90MHz<=Fvco<=100MHz */
2028 fll->outdiv = 3;
2029 while (freq_out * (fll->outdiv + 1) < 90000000) {
2030 fll->outdiv++;
2031 if (fll->outdiv > 63)
2032 return -EINVAL;
2033 }
2034 freq_out *= fll->outdiv + 1;
2035 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2036
2037 if (freq_in > 1000000) {
2038 fll->fll_fratio = 0;
2039 } else if (freq_in > 256000) {
2040 fll->fll_fratio = 1;
2041 freq_in *= 2;
2042 } else if (freq_in > 128000) {
2043 fll->fll_fratio = 2;
2044 freq_in *= 4;
2045 } else if (freq_in > 64000) {
2046 fll->fll_fratio = 3;
2047 freq_in *= 8;
2048 } else {
2049 fll->fll_fratio = 4;
2050 freq_in *= 16;
2051 }
2052 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2053
2054 /* Now, calculate N.K */
2055 Ndiv = freq_out / freq_in;
2056
2057 fll->n = Ndiv;
2058 Nmod = freq_out % freq_in;
2059 pr_debug("Nmod=%d\n", Nmod);
2060
2061 /* Calculate fractional part - scale up so we can round. */
2062 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
2063
2064 do_div(Kpart, freq_in);
2065
2066 K = Kpart & 0xFFFFFFFF;
2067
2068 if ((K % 10) >= 5)
2069 K += 5;
2070
2071 /* Move down to proper range now rounding is done */
2072 fll->k = K / 10;
2073
2074 pr_debug("N=%x K=%x\n", fll->n, fll->k);
2075
2076 return 0;
2077 }
2078
2079 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
2080 unsigned int freq_in, unsigned int freq_out)
2081 {
2082 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2083 struct wm8994 *control = wm8994->wm8994;
2084 int reg_offset, ret;
2085 struct fll_div fll;
2086 u16 reg, clk1, aif_reg, aif_src;
2087 unsigned long timeout;
2088 bool was_enabled;
2089
2090 switch (id) {
2091 case WM8994_FLL1:
2092 reg_offset = 0;
2093 id = 0;
2094 aif_src = 0x10;
2095 break;
2096 case WM8994_FLL2:
2097 reg_offset = 0x20;
2098 id = 1;
2099 aif_src = 0x18;
2100 break;
2101 default:
2102 return -EINVAL;
2103 }
2104
2105 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2106 was_enabled = reg & WM8994_FLL1_ENA;
2107
2108 switch (src) {
2109 case 0:
2110 /* Allow no source specification when stopping */
2111 if (freq_out)
2112 return -EINVAL;
2113 src = wm8994->fll[id].src;
2114 break;
2115 case WM8994_FLL_SRC_MCLK1:
2116 case WM8994_FLL_SRC_MCLK2:
2117 case WM8994_FLL_SRC_LRCLK:
2118 case WM8994_FLL_SRC_BCLK:
2119 break;
2120 case WM8994_FLL_SRC_INTERNAL:
2121 freq_in = 12000000;
2122 freq_out = 12000000;
2123 break;
2124 default:
2125 return -EINVAL;
2126 }
2127
2128 /* Are we changing anything? */
2129 if (wm8994->fll[id].src == src &&
2130 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2131 return 0;
2132
2133 /* If we're stopping the FLL redo the old config - no
2134 * registers will actually be written but we avoid GCC flow
2135 * analysis bugs spewing warnings.
2136 */
2137 if (freq_out)
2138 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
2139 else
2140 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
2141 wm8994->fll[id].out);
2142 if (ret < 0)
2143 return ret;
2144
2145 /* Make sure that we're not providing SYSCLK right now */
2146 clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
2147 if (clk1 & WM8994_SYSCLK_SRC)
2148 aif_reg = WM8994_AIF2_CLOCKING_1;
2149 else
2150 aif_reg = WM8994_AIF1_CLOCKING_1;
2151 reg = snd_soc_read(codec, aif_reg);
2152
2153 if ((reg & WM8994_AIF1CLK_ENA) &&
2154 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2155 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
2156 id + 1);
2157 return -EBUSY;
2158 }
2159
2160 /* We always need to disable the FLL while reconfiguring */
2161 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2162 WM8994_FLL1_ENA, 0);
2163
2164 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
2165 freq_in == freq_out && freq_out) {
2166 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
2167 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2168 WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2169 goto out;
2170 }
2171
2172 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2173 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2174 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2175 WM8994_FLL1_OUTDIV_MASK |
2176 WM8994_FLL1_FRATIO_MASK, reg);
2177
2178 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
2179 WM8994_FLL1_K_MASK, fll.k);
2180
2181 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2182 WM8994_FLL1_N_MASK,
2183 fll.n << WM8994_FLL1_N_SHIFT);
2184
2185 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2186 WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
2187 WM8994_FLL1_REFCLK_DIV_MASK |
2188 WM8994_FLL1_REFCLK_SRC_MASK,
2189 ((src == WM8994_FLL_SRC_INTERNAL)
2190 << WM8994_FLL1_FRC_NCO_SHIFT) |
2191 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2192 (src - 1));
2193
2194 /* Clear any pending completion from a previous failure */
2195 try_wait_for_completion(&wm8994->fll_locked[id]);
2196
2197 /* Enable (with fractional mode if required) */
2198 if (freq_out) {
2199 /* Enable VMID if we need it */
2200 if (!was_enabled) {
2201 active_reference(codec);
2202
2203 switch (control->type) {
2204 case WM8994:
2205 vmid_reference(codec);
2206 break;
2207 case WM8958:
2208 if (wm8994->revision < 1)
2209 vmid_reference(codec);
2210 break;
2211 default:
2212 break;
2213 }
2214 }
2215
2216 reg = WM8994_FLL1_ENA;
2217
2218 if (fll.k)
2219 reg |= WM8994_FLL1_FRAC;
2220 if (src == WM8994_FLL_SRC_INTERNAL)
2221 reg |= WM8994_FLL1_OSC_ENA;
2222
2223 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2224 WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
2225 WM8994_FLL1_FRAC, reg);
2226
2227 if (wm8994->fll_locked_irq) {
2228 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2229 msecs_to_jiffies(10));
2230 if (timeout == 0)
2231 dev_warn(codec->dev,
2232 "Timed out waiting for FLL lock\n");
2233 } else {
2234 msleep(5);
2235 }
2236 } else {
2237 if (was_enabled) {
2238 switch (control->type) {
2239 case WM8994:
2240 vmid_dereference(codec);
2241 break;
2242 case WM8958:
2243 if (wm8994->revision < 1)
2244 vmid_dereference(codec);
2245 break;
2246 default:
2247 break;
2248 }
2249
2250 active_dereference(codec);
2251 }
2252 }
2253
2254 out:
2255 wm8994->fll[id].in = freq_in;
2256 wm8994->fll[id].out = freq_out;
2257 wm8994->fll[id].src = src;
2258
2259 configure_clock(codec);
2260
2261 return 0;
2262 }
2263
2264 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2265 {
2266 struct completion *completion = data;
2267
2268 complete(completion);
2269
2270 return IRQ_HANDLED;
2271 }
2272
2273 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2274
2275 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2276 unsigned int freq_in, unsigned int freq_out)
2277 {
2278 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2279 }
2280
2281 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2282 int clk_id, unsigned int freq, int dir)
2283 {
2284 struct snd_soc_codec *codec = dai->codec;
2285 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2286 int i;
2287
2288 switch (dai->id) {
2289 case 1:
2290 case 2:
2291 break;
2292
2293 default:
2294 /* AIF3 shares clocking with AIF1/2 */
2295 return -EINVAL;
2296 }
2297
2298 switch (clk_id) {
2299 case WM8994_SYSCLK_MCLK1:
2300 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2301 wm8994->mclk[0] = freq;
2302 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2303 dai->id, freq);
2304 break;
2305
2306 case WM8994_SYSCLK_MCLK2:
2307 /* TODO: Set GPIO AF */
2308 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2309 wm8994->mclk[1] = freq;
2310 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2311 dai->id, freq);
2312 break;
2313
2314 case WM8994_SYSCLK_FLL1:
2315 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2316 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2317 break;
2318
2319 case WM8994_SYSCLK_FLL2:
2320 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2321 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2322 break;
2323
2324 case WM8994_SYSCLK_OPCLK:
2325 /* Special case - a division (times 10) is given and
2326 * no effect on main clocking.
2327 */
2328 if (freq) {
2329 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2330 if (opclk_divs[i] == freq)
2331 break;
2332 if (i == ARRAY_SIZE(opclk_divs))
2333 return -EINVAL;
2334 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2335 WM8994_OPCLK_DIV_MASK, i);
2336 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2337 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2338 } else {
2339 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2340 WM8994_OPCLK_ENA, 0);
2341 }
2342
2343 default:
2344 return -EINVAL;
2345 }
2346
2347 configure_clock(codec);
2348
2349 return 0;
2350 }
2351
2352 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2353 enum snd_soc_bias_level level)
2354 {
2355 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2356 struct wm8994 *control = wm8994->wm8994;
2357
2358 wm_hubs_set_bias_level(codec, level);
2359
2360 switch (level) {
2361 case SND_SOC_BIAS_ON:
2362 break;
2363
2364 case SND_SOC_BIAS_PREPARE:
2365 /* MICBIAS into regulating mode */
2366 switch (control->type) {
2367 case WM8958:
2368 case WM1811:
2369 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2370 WM8958_MICB1_MODE, 0);
2371 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2372 WM8958_MICB2_MODE, 0);
2373 break;
2374 default:
2375 break;
2376 }
2377
2378 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2379 active_reference(codec);
2380 break;
2381
2382 case SND_SOC_BIAS_STANDBY:
2383 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2384 switch (control->type) {
2385 case WM8958:
2386 if (wm8994->revision == 0) {
2387 /* Optimise performance for rev A */
2388 snd_soc_update_bits(codec,
2389 WM8958_CHARGE_PUMP_2,
2390 WM8958_CP_DISCH,
2391 WM8958_CP_DISCH);
2392 }
2393 break;
2394
2395 default:
2396 break;
2397 }
2398
2399 /* Discharge LINEOUT1 & 2 */
2400 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2401 WM8994_LINEOUT1_DISCH |
2402 WM8994_LINEOUT2_DISCH,
2403 WM8994_LINEOUT1_DISCH |
2404 WM8994_LINEOUT2_DISCH);
2405 }
2406
2407 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2408 active_dereference(codec);
2409
2410 /* MICBIAS into bypass mode on newer devices */
2411 switch (control->type) {
2412 case WM8958:
2413 case WM1811:
2414 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2415 WM8958_MICB1_MODE,
2416 WM8958_MICB1_MODE);
2417 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2418 WM8958_MICB2_MODE,
2419 WM8958_MICB2_MODE);
2420 break;
2421 default:
2422 break;
2423 }
2424 break;
2425
2426 case SND_SOC_BIAS_OFF:
2427 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2428 wm8994->cur_fw = NULL;
2429 break;
2430 }
2431
2432 codec->dapm.bias_level = level;
2433
2434 return 0;
2435 }
2436
2437 int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2438 {
2439 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2440
2441 switch (mode) {
2442 case WM8994_VMID_NORMAL:
2443 if (wm8994->hubs.lineout1_se) {
2444 snd_soc_dapm_disable_pin(&codec->dapm,
2445 "LINEOUT1N Driver");
2446 snd_soc_dapm_disable_pin(&codec->dapm,
2447 "LINEOUT1P Driver");
2448 }
2449 if (wm8994->hubs.lineout2_se) {
2450 snd_soc_dapm_disable_pin(&codec->dapm,
2451 "LINEOUT2N Driver");
2452 snd_soc_dapm_disable_pin(&codec->dapm,
2453 "LINEOUT2P Driver");
2454 }
2455
2456 /* Do the sync with the old mode to allow it to clean up */
2457 snd_soc_dapm_sync(&codec->dapm);
2458 wm8994->vmid_mode = mode;
2459 break;
2460
2461 case WM8994_VMID_FORCE:
2462 if (wm8994->hubs.lineout1_se) {
2463 snd_soc_dapm_force_enable_pin(&codec->dapm,
2464 "LINEOUT1N Driver");
2465 snd_soc_dapm_force_enable_pin(&codec->dapm,
2466 "LINEOUT1P Driver");
2467 }
2468 if (wm8994->hubs.lineout2_se) {
2469 snd_soc_dapm_force_enable_pin(&codec->dapm,
2470 "LINEOUT2N Driver");
2471 snd_soc_dapm_force_enable_pin(&codec->dapm,
2472 "LINEOUT2P Driver");
2473 }
2474
2475 wm8994->vmid_mode = mode;
2476 snd_soc_dapm_sync(&codec->dapm);
2477 break;
2478
2479 default:
2480 return -EINVAL;
2481 }
2482
2483 return 0;
2484 }
2485
2486 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2487 {
2488 struct snd_soc_codec *codec = dai->codec;
2489 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2490 struct wm8994 *control = wm8994->wm8994;
2491 int ms_reg;
2492 int aif1_reg;
2493 int ms = 0;
2494 int aif1 = 0;
2495
2496 switch (dai->id) {
2497 case 1:
2498 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2499 aif1_reg = WM8994_AIF1_CONTROL_1;
2500 break;
2501 case 2:
2502 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2503 aif1_reg = WM8994_AIF2_CONTROL_1;
2504 break;
2505 default:
2506 return -EINVAL;
2507 }
2508
2509 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2510 case SND_SOC_DAIFMT_CBS_CFS:
2511 break;
2512 case SND_SOC_DAIFMT_CBM_CFM:
2513 ms = WM8994_AIF1_MSTR;
2514 break;
2515 default:
2516 return -EINVAL;
2517 }
2518
2519 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2520 case SND_SOC_DAIFMT_DSP_B:
2521 aif1 |= WM8994_AIF1_LRCLK_INV;
2522 case SND_SOC_DAIFMT_DSP_A:
2523 aif1 |= 0x18;
2524 break;
2525 case SND_SOC_DAIFMT_I2S:
2526 aif1 |= 0x10;
2527 break;
2528 case SND_SOC_DAIFMT_RIGHT_J:
2529 break;
2530 case SND_SOC_DAIFMT_LEFT_J:
2531 aif1 |= 0x8;
2532 break;
2533 default:
2534 return -EINVAL;
2535 }
2536
2537 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2538 case SND_SOC_DAIFMT_DSP_A:
2539 case SND_SOC_DAIFMT_DSP_B:
2540 /* frame inversion not valid for DSP modes */
2541 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2542 case SND_SOC_DAIFMT_NB_NF:
2543 break;
2544 case SND_SOC_DAIFMT_IB_NF:
2545 aif1 |= WM8994_AIF1_BCLK_INV;
2546 break;
2547 default:
2548 return -EINVAL;
2549 }
2550 break;
2551
2552 case SND_SOC_DAIFMT_I2S:
2553 case SND_SOC_DAIFMT_RIGHT_J:
2554 case SND_SOC_DAIFMT_LEFT_J:
2555 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2556 case SND_SOC_DAIFMT_NB_NF:
2557 break;
2558 case SND_SOC_DAIFMT_IB_IF:
2559 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2560 break;
2561 case SND_SOC_DAIFMT_IB_NF:
2562 aif1 |= WM8994_AIF1_BCLK_INV;
2563 break;
2564 case SND_SOC_DAIFMT_NB_IF:
2565 aif1 |= WM8994_AIF1_LRCLK_INV;
2566 break;
2567 default:
2568 return -EINVAL;
2569 }
2570 break;
2571 default:
2572 return -EINVAL;
2573 }
2574
2575 /* The AIF2 format configuration needs to be mirrored to AIF3
2576 * on WM8958 if it's in use so just do it all the time. */
2577 switch (control->type) {
2578 case WM1811:
2579 case WM8958:
2580 if (dai->id == 2)
2581 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2582 WM8994_AIF1_LRCLK_INV |
2583 WM8958_AIF3_FMT_MASK, aif1);
2584 break;
2585
2586 default:
2587 break;
2588 }
2589
2590 snd_soc_update_bits(codec, aif1_reg,
2591 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2592 WM8994_AIF1_FMT_MASK,
2593 aif1);
2594 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2595 ms);
2596
2597 return 0;
2598 }
2599
2600 static struct {
2601 int val, rate;
2602 } srs[] = {
2603 { 0, 8000 },
2604 { 1, 11025 },
2605 { 2, 12000 },
2606 { 3, 16000 },
2607 { 4, 22050 },
2608 { 5, 24000 },
2609 { 6, 32000 },
2610 { 7, 44100 },
2611 { 8, 48000 },
2612 { 9, 88200 },
2613 { 10, 96000 },
2614 };
2615
2616 static int fs_ratios[] = {
2617 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2618 };
2619
2620 static int bclk_divs[] = {
2621 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2622 640, 880, 960, 1280, 1760, 1920
2623 };
2624
2625 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2626 struct snd_pcm_hw_params *params,
2627 struct snd_soc_dai *dai)
2628 {
2629 struct snd_soc_codec *codec = dai->codec;
2630 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2631 int aif1_reg;
2632 int aif2_reg;
2633 int bclk_reg;
2634 int lrclk_reg;
2635 int rate_reg;
2636 int aif1 = 0;
2637 int aif2 = 0;
2638 int bclk = 0;
2639 int lrclk = 0;
2640 int rate_val = 0;
2641 int id = dai->id - 1;
2642
2643 int i, cur_val, best_val, bclk_rate, best;
2644
2645 switch (dai->id) {
2646 case 1:
2647 aif1_reg = WM8994_AIF1_CONTROL_1;
2648 aif2_reg = WM8994_AIF1_CONTROL_2;
2649 bclk_reg = WM8994_AIF1_BCLK;
2650 rate_reg = WM8994_AIF1_RATE;
2651 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2652 wm8994->lrclk_shared[0]) {
2653 lrclk_reg = WM8994_AIF1DAC_LRCLK;
2654 } else {
2655 lrclk_reg = WM8994_AIF1ADC_LRCLK;
2656 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2657 }
2658 break;
2659 case 2:
2660 aif1_reg = WM8994_AIF2_CONTROL_1;
2661 aif2_reg = WM8994_AIF2_CONTROL_2;
2662 bclk_reg = WM8994_AIF2_BCLK;
2663 rate_reg = WM8994_AIF2_RATE;
2664 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2665 wm8994->lrclk_shared[1]) {
2666 lrclk_reg = WM8994_AIF2DAC_LRCLK;
2667 } else {
2668 lrclk_reg = WM8994_AIF2ADC_LRCLK;
2669 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2670 }
2671 break;
2672 default:
2673 return -EINVAL;
2674 }
2675
2676 bclk_rate = params_rate(params) * 4;
2677 switch (params_format(params)) {
2678 case SNDRV_PCM_FORMAT_S16_LE:
2679 bclk_rate *= 16;
2680 break;
2681 case SNDRV_PCM_FORMAT_S20_3LE:
2682 bclk_rate *= 20;
2683 aif1 |= 0x20;
2684 break;
2685 case SNDRV_PCM_FORMAT_S24_LE:
2686 bclk_rate *= 24;
2687 aif1 |= 0x40;
2688 break;
2689 case SNDRV_PCM_FORMAT_S32_LE:
2690 bclk_rate *= 32;
2691 aif1 |= 0x60;
2692 break;
2693 default:
2694 return -EINVAL;
2695 }
2696
2697 /* Try to find an appropriate sample rate; look for an exact match. */
2698 for (i = 0; i < ARRAY_SIZE(srs); i++)
2699 if (srs[i].rate == params_rate(params))
2700 break;
2701 if (i == ARRAY_SIZE(srs))
2702 return -EINVAL;
2703 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2704
2705 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2706 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2707 dai->id, wm8994->aifclk[id], bclk_rate);
2708
2709 if (params_channels(params) == 1 &&
2710 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2711 aif2 |= WM8994_AIF1_MONO;
2712
2713 if (wm8994->aifclk[id] == 0) {
2714 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2715 return -EINVAL;
2716 }
2717
2718 /* AIFCLK/fs ratio; look for a close match in either direction */
2719 best = 0;
2720 best_val = abs((fs_ratios[0] * params_rate(params))
2721 - wm8994->aifclk[id]);
2722 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2723 cur_val = abs((fs_ratios[i] * params_rate(params))
2724 - wm8994->aifclk[id]);
2725 if (cur_val >= best_val)
2726 continue;
2727 best = i;
2728 best_val = cur_val;
2729 }
2730 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2731 dai->id, fs_ratios[best]);
2732 rate_val |= best;
2733
2734 /* We may not get quite the right frequency if using
2735 * approximate clocks so look for the closest match that is
2736 * higher than the target (we need to ensure that there enough
2737 * BCLKs to clock out the samples).
2738 */
2739 best = 0;
2740 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2741 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2742 if (cur_val < 0) /* BCLK table is sorted */
2743 break;
2744 best = i;
2745 }
2746 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2747 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2748 bclk_divs[best], bclk_rate);
2749 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2750
2751 lrclk = bclk_rate / params_rate(params);
2752 if (!lrclk) {
2753 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2754 bclk_rate);
2755 return -EINVAL;
2756 }
2757 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2758 lrclk, bclk_rate / lrclk);
2759
2760 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2761 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2762 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2763 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2764 lrclk);
2765 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2766 WM8994_AIF1CLK_RATE_MASK, rate_val);
2767
2768 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2769 switch (dai->id) {
2770 case 1:
2771 wm8994->dac_rates[0] = params_rate(params);
2772 wm8994_set_retune_mobile(codec, 0);
2773 wm8994_set_retune_mobile(codec, 1);
2774 break;
2775 case 2:
2776 wm8994->dac_rates[1] = params_rate(params);
2777 wm8994_set_retune_mobile(codec, 2);
2778 break;
2779 }
2780 }
2781
2782 return 0;
2783 }
2784
2785 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2786 struct snd_pcm_hw_params *params,
2787 struct snd_soc_dai *dai)
2788 {
2789 struct snd_soc_codec *codec = dai->codec;
2790 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2791 struct wm8994 *control = wm8994->wm8994;
2792 int aif1_reg;
2793 int aif1 = 0;
2794
2795 switch (dai->id) {
2796 case 3:
2797 switch (control->type) {
2798 case WM1811:
2799 case WM8958:
2800 aif1_reg = WM8958_AIF3_CONTROL_1;
2801 break;
2802 default:
2803 return 0;
2804 }
2805 default:
2806 return 0;
2807 }
2808
2809 switch (params_format(params)) {
2810 case SNDRV_PCM_FORMAT_S16_LE:
2811 break;
2812 case SNDRV_PCM_FORMAT_S20_3LE:
2813 aif1 |= 0x20;
2814 break;
2815 case SNDRV_PCM_FORMAT_S24_LE:
2816 aif1 |= 0x40;
2817 break;
2818 case SNDRV_PCM_FORMAT_S32_LE:
2819 aif1 |= 0x60;
2820 break;
2821 default:
2822 return -EINVAL;
2823 }
2824
2825 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2826 }
2827
2828 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2829 {
2830 struct snd_soc_codec *codec = codec_dai->codec;
2831 int mute_reg;
2832 int reg;
2833
2834 switch (codec_dai->id) {
2835 case 1:
2836 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2837 break;
2838 case 2:
2839 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2840 break;
2841 default:
2842 return -EINVAL;
2843 }
2844
2845 if (mute)
2846 reg = WM8994_AIF1DAC1_MUTE;
2847 else
2848 reg = 0;
2849
2850 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2851
2852 return 0;
2853 }
2854
2855 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2856 {
2857 struct snd_soc_codec *codec = codec_dai->codec;
2858 int reg, val, mask;
2859
2860 switch (codec_dai->id) {
2861 case 1:
2862 reg = WM8994_AIF1_MASTER_SLAVE;
2863 mask = WM8994_AIF1_TRI;
2864 break;
2865 case 2:
2866 reg = WM8994_AIF2_MASTER_SLAVE;
2867 mask = WM8994_AIF2_TRI;
2868 break;
2869 default:
2870 return -EINVAL;
2871 }
2872
2873 if (tristate)
2874 val = mask;
2875 else
2876 val = 0;
2877
2878 return snd_soc_update_bits(codec, reg, mask, val);
2879 }
2880
2881 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2882 {
2883 struct snd_soc_codec *codec = dai->codec;
2884
2885 /* Disable the pulls on the AIF if we're using it to save power. */
2886 snd_soc_update_bits(codec, WM8994_GPIO_3,
2887 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2888 snd_soc_update_bits(codec, WM8994_GPIO_4,
2889 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2890 snd_soc_update_bits(codec, WM8994_GPIO_5,
2891 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2892
2893 return 0;
2894 }
2895
2896 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2897
2898 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2899 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2900
2901 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2902 .set_sysclk = wm8994_set_dai_sysclk,
2903 .set_fmt = wm8994_set_dai_fmt,
2904 .hw_params = wm8994_hw_params,
2905 .digital_mute = wm8994_aif_mute,
2906 .set_pll = wm8994_set_fll,
2907 .set_tristate = wm8994_set_tristate,
2908 };
2909
2910 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2911 .set_sysclk = wm8994_set_dai_sysclk,
2912 .set_fmt = wm8994_set_dai_fmt,
2913 .hw_params = wm8994_hw_params,
2914 .digital_mute = wm8994_aif_mute,
2915 .set_pll = wm8994_set_fll,
2916 .set_tristate = wm8994_set_tristate,
2917 };
2918
2919 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2920 .hw_params = wm8994_aif3_hw_params,
2921 };
2922
2923 static struct snd_soc_dai_driver wm8994_dai[] = {
2924 {
2925 .name = "wm8994-aif1",
2926 .id = 1,
2927 .playback = {
2928 .stream_name = "AIF1 Playback",
2929 .channels_min = 1,
2930 .channels_max = 2,
2931 .rates = WM8994_RATES,
2932 .formats = WM8994_FORMATS,
2933 .sig_bits = 24,
2934 },
2935 .capture = {
2936 .stream_name = "AIF1 Capture",
2937 .channels_min = 1,
2938 .channels_max = 2,
2939 .rates = WM8994_RATES,
2940 .formats = WM8994_FORMATS,
2941 .sig_bits = 24,
2942 },
2943 .ops = &wm8994_aif1_dai_ops,
2944 },
2945 {
2946 .name = "wm8994-aif2",
2947 .id = 2,
2948 .playback = {
2949 .stream_name = "AIF2 Playback",
2950 .channels_min = 1,
2951 .channels_max = 2,
2952 .rates = WM8994_RATES,
2953 .formats = WM8994_FORMATS,
2954 .sig_bits = 24,
2955 },
2956 .capture = {
2957 .stream_name = "AIF2 Capture",
2958 .channels_min = 1,
2959 .channels_max = 2,
2960 .rates = WM8994_RATES,
2961 .formats = WM8994_FORMATS,
2962 .sig_bits = 24,
2963 },
2964 .probe = wm8994_aif2_probe,
2965 .ops = &wm8994_aif2_dai_ops,
2966 },
2967 {
2968 .name = "wm8994-aif3",
2969 .id = 3,
2970 .playback = {
2971 .stream_name = "AIF3 Playback",
2972 .channels_min = 1,
2973 .channels_max = 2,
2974 .rates = WM8994_RATES,
2975 .formats = WM8994_FORMATS,
2976 .sig_bits = 24,
2977 },
2978 .capture = {
2979 .stream_name = "AIF3 Capture",
2980 .channels_min = 1,
2981 .channels_max = 2,
2982 .rates = WM8994_RATES,
2983 .formats = WM8994_FORMATS,
2984 .sig_bits = 24,
2985 },
2986 .ops = &wm8994_aif3_dai_ops,
2987 }
2988 };
2989
2990 #ifdef CONFIG_PM
2991 static int wm8994_codec_suspend(struct snd_soc_codec *codec)
2992 {
2993 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2994 int i, ret;
2995
2996 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2997 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2998 sizeof(struct wm8994_fll_config));
2999 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
3000 if (ret < 0)
3001 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
3002 i + 1, ret);
3003 }
3004
3005 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3006
3007 return 0;
3008 }
3009
3010 static int wm8994_codec_resume(struct snd_soc_codec *codec)
3011 {
3012 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3013 struct wm8994 *control = wm8994->wm8994;
3014 int i, ret;
3015 unsigned int val, mask;
3016
3017 if (wm8994->revision < 4) {
3018 /* force a HW read */
3019 ret = regmap_read(control->regmap,
3020 WM8994_POWER_MANAGEMENT_5, &val);
3021
3022 /* modify the cache only */
3023 codec->cache_only = 1;
3024 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
3025 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
3026 val &= mask;
3027 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
3028 mask, val);
3029 codec->cache_only = 0;
3030 }
3031
3032 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3033 if (!wm8994->fll_suspend[i].out)
3034 continue;
3035
3036 ret = _wm8994_set_fll(codec, i + 1,
3037 wm8994->fll_suspend[i].src,
3038 wm8994->fll_suspend[i].in,
3039 wm8994->fll_suspend[i].out);
3040 if (ret < 0)
3041 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
3042 i + 1, ret);
3043 }
3044
3045 return 0;
3046 }
3047 #else
3048 #define wm8994_codec_suspend NULL
3049 #define wm8994_codec_resume NULL
3050 #endif
3051
3052 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3053 {
3054 struct snd_soc_codec *codec = wm8994->hubs.codec;
3055 struct wm8994_pdata *pdata = wm8994->pdata;
3056 struct snd_kcontrol_new controls[] = {
3057 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3058 wm8994->retune_mobile_enum,
3059 wm8994_get_retune_mobile_enum,
3060 wm8994_put_retune_mobile_enum),
3061 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3062 wm8994->retune_mobile_enum,
3063 wm8994_get_retune_mobile_enum,
3064 wm8994_put_retune_mobile_enum),
3065 SOC_ENUM_EXT("AIF2 EQ Mode",
3066 wm8994->retune_mobile_enum,
3067 wm8994_get_retune_mobile_enum,
3068 wm8994_put_retune_mobile_enum),
3069 };
3070 int ret, i, j;
3071 const char **t;
3072
3073 /* We need an array of texts for the enum API but the number
3074 * of texts is likely to be less than the number of
3075 * configurations due to the sample rate dependency of the
3076 * configurations. */
3077 wm8994->num_retune_mobile_texts = 0;
3078 wm8994->retune_mobile_texts = NULL;
3079 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3080 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3081 if (strcmp(pdata->retune_mobile_cfgs[i].name,
3082 wm8994->retune_mobile_texts[j]) == 0)
3083 break;
3084 }
3085
3086 if (j != wm8994->num_retune_mobile_texts)
3087 continue;
3088
3089 /* Expand the array... */
3090 t = krealloc(wm8994->retune_mobile_texts,
3091 sizeof(char *) *
3092 (wm8994->num_retune_mobile_texts + 1),
3093 GFP_KERNEL);
3094 if (t == NULL)
3095 continue;
3096
3097 /* ...store the new entry... */
3098 t[wm8994->num_retune_mobile_texts] =
3099 pdata->retune_mobile_cfgs[i].name;
3100
3101 /* ...and remember the new version. */
3102 wm8994->num_retune_mobile_texts++;
3103 wm8994->retune_mobile_texts = t;
3104 }
3105
3106 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3107 wm8994->num_retune_mobile_texts);
3108
3109 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
3110 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3111
3112 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3113 ARRAY_SIZE(controls));
3114 if (ret != 0)
3115 dev_err(wm8994->hubs.codec->dev,
3116 "Failed to add ReTune Mobile controls: %d\n", ret);
3117 }
3118
3119 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3120 {
3121 struct snd_soc_codec *codec = wm8994->hubs.codec;
3122 struct wm8994_pdata *pdata = wm8994->pdata;
3123 int ret, i;
3124
3125 if (!pdata)
3126 return;
3127
3128 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3129 pdata->lineout2_diff,
3130 pdata->lineout1fb,
3131 pdata->lineout2fb,
3132 pdata->jd_scthr,
3133 pdata->jd_thr,
3134 pdata->micb1_delay,
3135 pdata->micb2_delay,
3136 pdata->micbias1_lvl,
3137 pdata->micbias2_lvl);
3138
3139 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3140
3141 if (pdata->num_drc_cfgs) {
3142 struct snd_kcontrol_new controls[] = {
3143 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3144 wm8994_get_drc_enum, wm8994_put_drc_enum),
3145 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3146 wm8994_get_drc_enum, wm8994_put_drc_enum),
3147 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3148 wm8994_get_drc_enum, wm8994_put_drc_enum),
3149 };
3150
3151 /* We need an array of texts for the enum API */
3152 wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev,
3153 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
3154 if (!wm8994->drc_texts) {
3155 dev_err(wm8994->hubs.codec->dev,
3156 "Failed to allocate %d DRC config texts\n",
3157 pdata->num_drc_cfgs);
3158 return;
3159 }
3160
3161 for (i = 0; i < pdata->num_drc_cfgs; i++)
3162 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3163
3164 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3165 wm8994->drc_enum.texts = wm8994->drc_texts;
3166
3167 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3168 ARRAY_SIZE(controls));
3169 for (i = 0; i < WM8994_NUM_DRC; i++)
3170 wm8994_set_drc(codec, i);
3171 } else {
3172 ret = snd_soc_add_codec_controls(wm8994->hubs.codec,
3173 wm8994_drc_controls,
3174 ARRAY_SIZE(wm8994_drc_controls));
3175 }
3176
3177 if (ret != 0)
3178 dev_err(wm8994->hubs.codec->dev,
3179 "Failed to add DRC mode controls: %d\n", ret);
3180
3181
3182 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3183 pdata->num_retune_mobile_cfgs);
3184
3185 if (pdata->num_retune_mobile_cfgs)
3186 wm8994_handle_retune_mobile_pdata(wm8994);
3187 else
3188 snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls,
3189 ARRAY_SIZE(wm8994_eq_controls));
3190
3191 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3192 if (pdata->micbias[i]) {
3193 snd_soc_write(codec, WM8958_MICBIAS1 + i,
3194 pdata->micbias[i] & 0xffff);
3195 }
3196 }
3197 }
3198
3199 /**
3200 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3201 *
3202 * @codec: WM8994 codec
3203 * @jack: jack to report detection events on
3204 * @micbias: microphone bias to detect on
3205 *
3206 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3207 * being used to bring out signals to the processor then only platform
3208 * data configuration is needed for WM8994 and processor GPIOs should
3209 * be configured using snd_soc_jack_add_gpios() instead.
3210 *
3211 * Configuration of detection levels is available via the micbias1_lvl
3212 * and micbias2_lvl platform data members.
3213 */
3214 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3215 int micbias)
3216 {
3217 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3218 struct wm8994_micdet *micdet;
3219 struct wm8994 *control = wm8994->wm8994;
3220 int reg, ret;
3221
3222 if (control->type != WM8994) {
3223 dev_warn(codec->dev, "Not a WM8994\n");
3224 return -EINVAL;
3225 }
3226
3227 switch (micbias) {
3228 case 1:
3229 micdet = &wm8994->micdet[0];
3230 if (jack)
3231 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3232 "MICBIAS1");
3233 else
3234 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3235 "MICBIAS1");
3236 break;
3237 case 2:
3238 micdet = &wm8994->micdet[1];
3239 if (jack)
3240 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3241 "MICBIAS1");
3242 else
3243 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3244 "MICBIAS1");
3245 break;
3246 default:
3247 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
3248 return -EINVAL;
3249 }
3250
3251 if (ret != 0)
3252 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3253 micbias, ret);
3254
3255 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3256 micbias, jack);
3257
3258 /* Store the configuration */
3259 micdet->jack = jack;
3260 micdet->detecting = true;
3261
3262 /* If either of the jacks is set up then enable detection */
3263 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3264 reg = WM8994_MICD_ENA;
3265 else
3266 reg = 0;
3267
3268 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3269
3270 /* enable MICDET and MICSHRT deboune */
3271 snd_soc_update_bits(codec, WM8994_IRQ_DEBOUNCE,
3272 WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK |
3273 WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK,
3274 WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB);
3275
3276 snd_soc_dapm_sync(&codec->dapm);
3277
3278 return 0;
3279 }
3280 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3281
3282 static void wm8994_mic_work(struct work_struct *work)
3283 {
3284 struct wm8994_priv *priv = container_of(work,
3285 struct wm8994_priv,
3286 mic_work.work);
3287 struct regmap *regmap = priv->wm8994->regmap;
3288 struct device *dev = priv->wm8994->dev;
3289 unsigned int reg;
3290 int ret;
3291 int report;
3292
3293 pm_runtime_get_sync(dev);
3294
3295 ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, &reg);
3296 if (ret < 0) {
3297 dev_err(dev, "Failed to read microphone status: %d\n",
3298 ret);
3299 pm_runtime_put(dev);
3300 return;
3301 }
3302
3303 dev_dbg(dev, "Microphone status: %x\n", reg);
3304
3305 report = 0;
3306 if (reg & WM8994_MIC1_DET_STS) {
3307 if (priv->micdet[0].detecting)
3308 report = SND_JACK_HEADSET;
3309 }
3310 if (reg & WM8994_MIC1_SHRT_STS) {
3311 if (priv->micdet[0].detecting)
3312 report = SND_JACK_HEADPHONE;
3313 else
3314 report |= SND_JACK_BTN_0;
3315 }
3316 if (report)
3317 priv->micdet[0].detecting = false;
3318 else
3319 priv->micdet[0].detecting = true;
3320
3321 snd_soc_jack_report(priv->micdet[0].jack, report,
3322 SND_JACK_HEADSET | SND_JACK_BTN_0);
3323
3324 report = 0;
3325 if (reg & WM8994_MIC2_DET_STS) {
3326 if (priv->micdet[1].detecting)
3327 report = SND_JACK_HEADSET;
3328 }
3329 if (reg & WM8994_MIC2_SHRT_STS) {
3330 if (priv->micdet[1].detecting)
3331 report = SND_JACK_HEADPHONE;
3332 else
3333 report |= SND_JACK_BTN_0;
3334 }
3335 if (report)
3336 priv->micdet[1].detecting = false;
3337 else
3338 priv->micdet[1].detecting = true;
3339
3340 snd_soc_jack_report(priv->micdet[1].jack, report,
3341 SND_JACK_HEADSET | SND_JACK_BTN_0);
3342
3343 pm_runtime_put(dev);
3344 }
3345
3346 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3347 {
3348 struct wm8994_priv *priv = data;
3349 struct snd_soc_codec *codec = priv->hubs.codec;
3350
3351 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3352 trace_snd_soc_jack_irq(dev_name(codec->dev));
3353 #endif
3354
3355 pm_wakeup_event(codec->dev, 300);
3356
3357 schedule_delayed_work(&priv->mic_work, msecs_to_jiffies(250));
3358
3359 return IRQ_HANDLED;
3360 }
3361
3362 /* Default microphone detection handler for WM8958 - the user can
3363 * override this if they wish.
3364 */
3365 static void wm8958_default_micdet(u16 status, void *data)
3366 {
3367 struct snd_soc_codec *codec = data;
3368 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3369 int report;
3370
3371 dev_dbg(codec->dev, "MICDET %x\n", status);
3372
3373 /* Either nothing present or just starting detection */
3374 if (!(status & WM8958_MICD_STS)) {
3375 if (!wm8994->jackdet) {
3376 /* If nothing present then clear our statuses */
3377 dev_dbg(codec->dev, "Detected open circuit\n");
3378 wm8994->jack_mic = false;
3379 wm8994->mic_detecting = true;
3380
3381 wm8958_micd_set_rate(codec);
3382
3383 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3384 wm8994->btn_mask |
3385 SND_JACK_HEADSET);
3386 }
3387 return;
3388 }
3389
3390 /* If the measurement is showing a high impedence we've got a
3391 * microphone.
3392 */
3393 if (wm8994->mic_detecting && (status & 0x600)) {
3394 dev_dbg(codec->dev, "Detected microphone\n");
3395
3396 wm8994->mic_detecting = false;
3397 wm8994->jack_mic = true;
3398
3399 wm8958_micd_set_rate(codec);
3400
3401 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3402 SND_JACK_HEADSET);
3403 }
3404
3405
3406 if (wm8994->mic_detecting && status & 0xfc) {
3407 dev_dbg(codec->dev, "Detected headphone\n");
3408 wm8994->mic_detecting = false;
3409
3410 wm8958_micd_set_rate(codec);
3411
3412 /* If we have jackdet that will detect removal */
3413 if (wm8994->jackdet) {
3414 mutex_lock(&wm8994->accdet_lock);
3415
3416 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3417 WM8958_MICD_ENA, 0);
3418
3419 wm1811_jackdet_set_mode(codec,
3420 WM1811_JACKDET_MODE_JACK);
3421
3422 mutex_unlock(&wm8994->accdet_lock);
3423
3424 if (wm8994->pdata->jd_ext_cap)
3425 snd_soc_dapm_disable_pin(&codec->dapm,
3426 "MICBIAS2");
3427 }
3428
3429 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3430 SND_JACK_HEADSET);
3431 }
3432
3433 /* Report short circuit as a button */
3434 if (wm8994->jack_mic) {
3435 report = 0;
3436 if (status & 0x4)
3437 report |= SND_JACK_BTN_0;
3438
3439 if (status & 0x8)
3440 report |= SND_JACK_BTN_1;
3441
3442 if (status & 0x10)
3443 report |= SND_JACK_BTN_2;
3444
3445 if (status & 0x20)
3446 report |= SND_JACK_BTN_3;
3447
3448 if (status & 0x40)
3449 report |= SND_JACK_BTN_4;
3450
3451 if (status & 0x80)
3452 report |= SND_JACK_BTN_5;
3453
3454 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3455 wm8994->btn_mask);
3456 }
3457 }
3458
3459 /* Deferred mic detection to allow for extra settling time */
3460 static void wm1811_mic_work(struct work_struct *work)
3461 {
3462 struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv,
3463 mic_work.work);
3464 struct snd_soc_codec *codec = wm8994->hubs.codec;
3465
3466 pm_runtime_get_sync(codec->dev);
3467
3468 /* If required for an external cap force MICBIAS on */
3469 if (wm8994->pdata->jd_ext_cap) {
3470 snd_soc_dapm_force_enable_pin(&codec->dapm,
3471 "MICBIAS2");
3472 snd_soc_dapm_sync(&codec->dapm);
3473 }
3474
3475 mutex_lock(&wm8994->accdet_lock);
3476
3477 dev_dbg(codec->dev, "Starting mic detection\n");
3478
3479 /*
3480 * Start off measument of microphone impedence to find out
3481 * what's actually there.
3482 */
3483 wm8994->mic_detecting = true;
3484 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3485
3486 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3487 WM8958_MICD_ENA, WM8958_MICD_ENA);
3488
3489 mutex_unlock(&wm8994->accdet_lock);
3490
3491 pm_runtime_put(codec->dev);
3492 }
3493
3494 static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3495 {
3496 struct wm8994_priv *wm8994 = data;
3497 struct snd_soc_codec *codec = wm8994->hubs.codec;
3498 int reg, delay;
3499 bool present;
3500
3501 pm_runtime_get_sync(codec->dev);
3502
3503 mutex_lock(&wm8994->accdet_lock);
3504
3505 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3506 if (reg < 0) {
3507 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3508 mutex_unlock(&wm8994->accdet_lock);
3509 pm_runtime_put(codec->dev);
3510 return IRQ_NONE;
3511 }
3512
3513 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3514
3515 present = reg & WM1811_JACKDET_LVL;
3516
3517 if (present) {
3518 dev_dbg(codec->dev, "Jack detected\n");
3519
3520 wm8958_micd_set_rate(codec);
3521
3522 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3523 WM8958_MICB2_DISCH, 0);
3524
3525 /* Disable debounce while inserted */
3526 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3527 WM1811_JACKDET_DB, 0);
3528
3529 delay = wm8994->pdata->micdet_delay;
3530 schedule_delayed_work(&wm8994->mic_work,
3531 msecs_to_jiffies(delay));
3532 } else {
3533 dev_dbg(codec->dev, "Jack not detected\n");
3534
3535 cancel_delayed_work_sync(&wm8994->mic_work);
3536
3537 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3538 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3539
3540 /* Enable debounce while removed */
3541 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3542 WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3543
3544 wm8994->mic_detecting = false;
3545 wm8994->jack_mic = false;
3546 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3547 WM8958_MICD_ENA, 0);
3548 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3549 }
3550
3551 mutex_unlock(&wm8994->accdet_lock);
3552
3553 /* Turn off MICBIAS if it was on for an external cap */
3554 if (wm8994->pdata->jd_ext_cap && !present)
3555 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
3556
3557 if (present)
3558 snd_soc_jack_report(wm8994->micdet[0].jack,
3559 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3560 else
3561 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3562 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3563 wm8994->btn_mask);
3564
3565 /* Since we only report deltas force an update, ensures we
3566 * avoid bootstrapping issues with the core. */
3567 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0);
3568
3569 pm_runtime_put(codec->dev);
3570 return IRQ_HANDLED;
3571 }
3572
3573 static void wm1811_jackdet_bootstrap(struct work_struct *work)
3574 {
3575 struct wm8994_priv *wm8994 = container_of(work,
3576 struct wm8994_priv,
3577 jackdet_bootstrap.work);
3578 wm1811_jackdet_irq(0, wm8994);
3579 }
3580
3581 /**
3582 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3583 *
3584 * @codec: WM8958 codec
3585 * @jack: jack to report detection events on
3586 *
3587 * Enable microphone detection functionality for the WM8958. By
3588 * default simple detection which supports the detection of up to 6
3589 * buttons plus video and microphone functionality is supported.
3590 *
3591 * The WM8958 has an advanced jack detection facility which is able to
3592 * support complex accessory detection, especially when used in
3593 * conjunction with external circuitry. In order to provide maximum
3594 * flexiblity a callback is provided which allows a completely custom
3595 * detection algorithm.
3596 */
3597 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3598 wm8958_micdet_cb cb, void *cb_data)
3599 {
3600 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3601 struct wm8994 *control = wm8994->wm8994;
3602 u16 micd_lvl_sel;
3603
3604 switch (control->type) {
3605 case WM1811:
3606 case WM8958:
3607 break;
3608 default:
3609 return -EINVAL;
3610 }
3611
3612 if (jack) {
3613 if (!cb) {
3614 dev_dbg(codec->dev, "Using default micdet callback\n");
3615 cb = wm8958_default_micdet;
3616 cb_data = codec;
3617 }
3618
3619 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3620 snd_soc_dapm_sync(&codec->dapm);
3621
3622 wm8994->micdet[0].jack = jack;
3623 wm8994->jack_cb = cb;
3624 wm8994->jack_cb_data = cb_data;
3625
3626 wm8994->mic_detecting = true;
3627 wm8994->jack_mic = false;
3628
3629 wm8958_micd_set_rate(codec);
3630
3631 /* Detect microphones and short circuits by default */
3632 if (wm8994->pdata->micd_lvl_sel)
3633 micd_lvl_sel = wm8994->pdata->micd_lvl_sel;
3634 else
3635 micd_lvl_sel = 0x41;
3636
3637 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3638 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3639 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3640
3641 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
3642 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3643
3644 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3645
3646 /*
3647 * If we can use jack detection start off with that,
3648 * otherwise jump straight to microphone detection.
3649 */
3650 if (wm8994->jackdet) {
3651 /* Disable debounce for the initial detect */
3652 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3653 WM1811_JACKDET_DB, 0);
3654
3655 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3656 WM8958_MICB2_DISCH,
3657 WM8958_MICB2_DISCH);
3658 snd_soc_update_bits(codec, WM8994_LDO_1,
3659 WM8994_LDO1_DISCH, 0);
3660 wm1811_jackdet_set_mode(codec,
3661 WM1811_JACKDET_MODE_JACK);
3662 } else {
3663 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3664 WM8958_MICD_ENA, WM8958_MICD_ENA);
3665 }
3666
3667 } else {
3668 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3669 WM8958_MICD_ENA, 0);
3670 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
3671 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
3672 snd_soc_dapm_sync(&codec->dapm);
3673 }
3674
3675 return 0;
3676 }
3677 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3678
3679 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3680 {
3681 struct wm8994_priv *wm8994 = data;
3682 struct snd_soc_codec *codec = wm8994->hubs.codec;
3683 int reg, count;
3684
3685 /*
3686 * Jack detection may have detected a removal simulataneously
3687 * with an update of the MICDET status; if so it will have
3688 * stopped detection and we can ignore this interrupt.
3689 */
3690 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
3691 return IRQ_HANDLED;
3692
3693 pm_runtime_get_sync(codec->dev);
3694
3695 /* We may occasionally read a detection without an impedence
3696 * range being provided - if that happens loop again.
3697 */
3698 count = 10;
3699 do {
3700 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3701 if (reg < 0) {
3702 dev_err(codec->dev,
3703 "Failed to read mic detect status: %d\n",
3704 reg);
3705 pm_runtime_put(codec->dev);
3706 return IRQ_NONE;
3707 }
3708
3709 if (!(reg & WM8958_MICD_VALID)) {
3710 dev_dbg(codec->dev, "Mic detect data not valid\n");
3711 goto out;
3712 }
3713
3714 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3715 break;
3716
3717 msleep(1);
3718 } while (count--);
3719
3720 if (count == 0)
3721 dev_warn(codec->dev, "No impedence range reported for jack\n");
3722
3723 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3724 trace_snd_soc_jack_irq(dev_name(codec->dev));
3725 #endif
3726
3727 if (wm8994->jack_cb)
3728 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3729 else
3730 dev_warn(codec->dev, "Accessory detection with no callback\n");
3731
3732 out:
3733 pm_runtime_put(codec->dev);
3734 return IRQ_HANDLED;
3735 }
3736
3737 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3738 {
3739 struct snd_soc_codec *codec = data;
3740
3741 dev_err(codec->dev, "FIFO error\n");
3742
3743 return IRQ_HANDLED;
3744 }
3745
3746 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3747 {
3748 struct snd_soc_codec *codec = data;
3749
3750 dev_err(codec->dev, "Thermal warning\n");
3751
3752 return IRQ_HANDLED;
3753 }
3754
3755 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3756 {
3757 struct snd_soc_codec *codec = data;
3758
3759 dev_crit(codec->dev, "Thermal shutdown\n");
3760
3761 return IRQ_HANDLED;
3762 }
3763
3764 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3765 {
3766 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
3767 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3768 struct snd_soc_dapm_context *dapm = &codec->dapm;
3769 unsigned int reg;
3770 int ret, i;
3771
3772 wm8994->hubs.codec = codec;
3773 codec->control_data = control->regmap;
3774
3775 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
3776
3777 mutex_init(&wm8994->accdet_lock);
3778 INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
3779 wm1811_jackdet_bootstrap);
3780
3781 switch (control->type) {
3782 case WM8994:
3783 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
3784 break;
3785 case WM1811:
3786 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work);
3787 break;
3788 default:
3789 break;
3790 }
3791
3792 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3793 init_completion(&wm8994->fll_locked[i]);
3794
3795 if (wm8994->pdata && wm8994->pdata->micdet_irq)
3796 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3797
3798 pm_runtime_enable(codec->dev);
3799 pm_runtime_idle(codec->dev);
3800
3801 /* By default use idle_bias_off, will override for WM8994 */
3802 codec->dapm.idle_bias_off = 1;
3803
3804 /* Set revision-specific configuration */
3805 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3806 switch (control->type) {
3807 case WM8994:
3808 /* Single ended line outputs should have VMID on. */
3809 if (!wm8994->pdata->lineout1_diff ||
3810 !wm8994->pdata->lineout2_diff)
3811 codec->dapm.idle_bias_off = 0;
3812
3813 switch (wm8994->revision) {
3814 case 2:
3815 case 3:
3816 wm8994->hubs.dcs_codes_l = -5;
3817 wm8994->hubs.dcs_codes_r = -5;
3818 wm8994->hubs.hp_startup_mode = 1;
3819 wm8994->hubs.dcs_readback_mode = 1;
3820 wm8994->hubs.series_startup = 1;
3821 break;
3822 default:
3823 wm8994->hubs.dcs_readback_mode = 2;
3824 break;
3825 }
3826 break;
3827
3828 case WM8958:
3829 wm8994->hubs.dcs_readback_mode = 1;
3830 wm8994->hubs.hp_startup_mode = 1;
3831
3832 switch (wm8994->revision) {
3833 case 0:
3834 break;
3835 default:
3836 wm8994->fll_byp = true;
3837 break;
3838 }
3839 break;
3840
3841 case WM1811:
3842 wm8994->hubs.dcs_readback_mode = 2;
3843 wm8994->hubs.no_series_update = 1;
3844 wm8994->hubs.hp_startup_mode = 1;
3845 wm8994->hubs.no_cache_dac_hp_direct = true;
3846 wm8994->fll_byp = true;
3847
3848 switch (control->cust_id) {
3849 case 0:
3850 case 2:
3851 wm8994->hubs.dcs_codes_l = -9;
3852 wm8994->hubs.dcs_codes_r = -7;
3853 break;
3854 case 1:
3855 case 3:
3856 wm8994->hubs.dcs_codes_l = -8;
3857 wm8994->hubs.dcs_codes_r = -7;
3858 break;
3859 default:
3860 break;
3861 }
3862
3863 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3864 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3865 break;
3866
3867 default:
3868 break;
3869 }
3870
3871 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3872 wm8994_fifo_error, "FIFO error", codec);
3873 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
3874 wm8994_temp_warn, "Thermal warning", codec);
3875 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
3876 wm8994_temp_shut, "Thermal shutdown", codec);
3877
3878 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3879 wm_hubs_dcs_done, "DC servo done",
3880 &wm8994->hubs);
3881 if (ret == 0)
3882 wm8994->hubs.dcs_done_irq = true;
3883
3884 switch (control->type) {
3885 case WM8994:
3886 if (wm8994->micdet_irq) {
3887 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3888 wm8994_mic_irq,
3889 IRQF_TRIGGER_RISING,
3890 "Mic1 detect",
3891 wm8994);
3892 if (ret != 0)
3893 dev_warn(codec->dev,
3894 "Failed to request Mic1 detect IRQ: %d\n",
3895 ret);
3896 }
3897
3898 ret = wm8994_request_irq(wm8994->wm8994,
3899 WM8994_IRQ_MIC1_SHRT,
3900 wm8994_mic_irq, "Mic 1 short",
3901 wm8994);
3902 if (ret != 0)
3903 dev_warn(codec->dev,
3904 "Failed to request Mic1 short IRQ: %d\n",
3905 ret);
3906
3907 ret = wm8994_request_irq(wm8994->wm8994,
3908 WM8994_IRQ_MIC2_DET,
3909 wm8994_mic_irq, "Mic 2 detect",
3910 wm8994);
3911 if (ret != 0)
3912 dev_warn(codec->dev,
3913 "Failed to request Mic2 detect IRQ: %d\n",
3914 ret);
3915
3916 ret = wm8994_request_irq(wm8994->wm8994,
3917 WM8994_IRQ_MIC2_SHRT,
3918 wm8994_mic_irq, "Mic 2 short",
3919 wm8994);
3920 if (ret != 0)
3921 dev_warn(codec->dev,
3922 "Failed to request Mic2 short IRQ: %d\n",
3923 ret);
3924 break;
3925
3926 case WM8958:
3927 case WM1811:
3928 if (wm8994->micdet_irq) {
3929 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3930 wm8958_mic_irq,
3931 IRQF_TRIGGER_RISING,
3932 "Mic detect",
3933 wm8994);
3934 if (ret != 0)
3935 dev_warn(codec->dev,
3936 "Failed to request Mic detect IRQ: %d\n",
3937 ret);
3938 } else {
3939 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3940 wm8958_mic_irq, "Mic detect",
3941 wm8994);
3942 }
3943 }
3944
3945 switch (control->type) {
3946 case WM1811:
3947 if (control->cust_id > 1 || wm8994->revision > 1) {
3948 ret = wm8994_request_irq(wm8994->wm8994,
3949 WM8994_IRQ_GPIO(6),
3950 wm1811_jackdet_irq, "JACKDET",
3951 wm8994);
3952 if (ret == 0)
3953 wm8994->jackdet = true;
3954 }
3955 break;
3956 default:
3957 break;
3958 }
3959
3960 wm8994->fll_locked_irq = true;
3961 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
3962 ret = wm8994_request_irq(wm8994->wm8994,
3963 WM8994_IRQ_FLL1_LOCK + i,
3964 wm8994_fll_locked_irq, "FLL lock",
3965 &wm8994->fll_locked[i]);
3966 if (ret != 0)
3967 wm8994->fll_locked_irq = false;
3968 }
3969
3970 /* Make sure we can read from the GPIOs if they're inputs */
3971 pm_runtime_get_sync(codec->dev);
3972
3973 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3974 * configured on init - if a system wants to do this dynamically
3975 * at runtime we can deal with that then.
3976 */
3977 ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
3978 if (ret < 0) {
3979 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3980 goto err_irq;
3981 }
3982 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3983 wm8994->lrclk_shared[0] = 1;
3984 wm8994_dai[0].symmetric_rates = 1;
3985 } else {
3986 wm8994->lrclk_shared[0] = 0;
3987 }
3988
3989 ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
3990 if (ret < 0) {
3991 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3992 goto err_irq;
3993 }
3994 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3995 wm8994->lrclk_shared[1] = 1;
3996 wm8994_dai[1].symmetric_rates = 1;
3997 } else {
3998 wm8994->lrclk_shared[1] = 0;
3999 }
4000
4001 pm_runtime_put(codec->dev);
4002
4003 /* Latch volume update bits */
4004 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
4005 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg,
4006 wm8994_vu_bits[i].mask,
4007 wm8994_vu_bits[i].mask);
4008
4009 /* Set the low bit of the 3D stereo depth so TLV matches */
4010 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
4011 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
4012 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
4013 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
4014 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
4015 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
4016 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
4017 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
4018 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
4019
4020 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
4021 * use this; it only affects behaviour on idle TDM clock
4022 * cycles. */
4023 switch (control->type) {
4024 case WM8994:
4025 case WM8958:
4026 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
4027 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
4028 break;
4029 default:
4030 break;
4031 }
4032
4033 /* Put MICBIAS into bypass mode by default on newer devices */
4034 switch (control->type) {
4035 case WM8958:
4036 case WM1811:
4037 snd_soc_update_bits(codec, WM8958_MICBIAS1,
4038 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
4039 snd_soc_update_bits(codec, WM8958_MICBIAS2,
4040 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
4041 break;
4042 default:
4043 break;
4044 }
4045
4046 wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
4047 wm_hubs_update_class_w(codec);
4048
4049 wm8994_handle_pdata(wm8994);
4050
4051 wm_hubs_add_analogue_controls(codec);
4052 snd_soc_add_codec_controls(codec, wm8994_snd_controls,
4053 ARRAY_SIZE(wm8994_snd_controls));
4054 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
4055 ARRAY_SIZE(wm8994_dapm_widgets));
4056
4057 switch (control->type) {
4058 case WM8994:
4059 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
4060 ARRAY_SIZE(wm8994_specific_dapm_widgets));
4061 if (wm8994->revision < 4) {
4062 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4063 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4064 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4065 ARRAY_SIZE(wm8994_adc_revd_widgets));
4066 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4067 ARRAY_SIZE(wm8994_dac_revd_widgets));
4068 } else {
4069 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4070 ARRAY_SIZE(wm8994_lateclk_widgets));
4071 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4072 ARRAY_SIZE(wm8994_adc_widgets));
4073 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4074 ARRAY_SIZE(wm8994_dac_widgets));
4075 }
4076 break;
4077 case WM8958:
4078 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4079 ARRAY_SIZE(wm8958_snd_controls));
4080 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4081 ARRAY_SIZE(wm8958_dapm_widgets));
4082 if (wm8994->revision < 1) {
4083 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4084 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4085 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4086 ARRAY_SIZE(wm8994_adc_revd_widgets));
4087 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4088 ARRAY_SIZE(wm8994_dac_revd_widgets));
4089 } else {
4090 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4091 ARRAY_SIZE(wm8994_lateclk_widgets));
4092 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4093 ARRAY_SIZE(wm8994_adc_widgets));
4094 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4095 ARRAY_SIZE(wm8994_dac_widgets));
4096 }
4097 break;
4098
4099 case WM1811:
4100 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4101 ARRAY_SIZE(wm8958_snd_controls));
4102 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4103 ARRAY_SIZE(wm8958_dapm_widgets));
4104 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4105 ARRAY_SIZE(wm8994_lateclk_widgets));
4106 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4107 ARRAY_SIZE(wm8994_adc_widgets));
4108 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4109 ARRAY_SIZE(wm8994_dac_widgets));
4110 break;
4111 }
4112
4113 wm_hubs_add_analogue_routes(codec, 0, 0);
4114 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
4115
4116 switch (control->type) {
4117 case WM8994:
4118 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4119 ARRAY_SIZE(wm8994_intercon));
4120
4121 if (wm8994->revision < 4) {
4122 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4123 ARRAY_SIZE(wm8994_revd_intercon));
4124 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4125 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4126 } else {
4127 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4128 ARRAY_SIZE(wm8994_lateclk_intercon));
4129 }
4130 break;
4131 case WM8958:
4132 if (wm8994->revision < 1) {
4133 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4134 ARRAY_SIZE(wm8994_intercon));
4135 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4136 ARRAY_SIZE(wm8994_revd_intercon));
4137 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4138 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4139 } else {
4140 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4141 ARRAY_SIZE(wm8994_lateclk_intercon));
4142 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4143 ARRAY_SIZE(wm8958_intercon));
4144 }
4145
4146 wm8958_dsp2_init(codec);
4147 break;
4148 case WM1811:
4149 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4150 ARRAY_SIZE(wm8994_lateclk_intercon));
4151 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4152 ARRAY_SIZE(wm8958_intercon));
4153 break;
4154 }
4155
4156 return 0;
4157
4158 err_irq:
4159 if (wm8994->jackdet)
4160 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4161 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4162 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4163 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
4164 if (wm8994->micdet_irq)
4165 free_irq(wm8994->micdet_irq, wm8994);
4166 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4167 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4168 &wm8994->fll_locked[i]);
4169 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4170 &wm8994->hubs);
4171 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4172 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4173 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4174
4175 return ret;
4176 }
4177
4178 static int wm8994_codec_remove(struct snd_soc_codec *codec)
4179 {
4180 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4181 struct wm8994 *control = wm8994->wm8994;
4182 int i;
4183
4184 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
4185
4186 pm_runtime_disable(codec->dev);
4187
4188 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4189 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4190 &wm8994->fll_locked[i]);
4191
4192 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4193 &wm8994->hubs);
4194 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4195 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4196 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4197
4198 if (wm8994->jackdet)
4199 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4200
4201 switch (control->type) {
4202 case WM8994:
4203 if (wm8994->micdet_irq)
4204 free_irq(wm8994->micdet_irq, wm8994);
4205 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
4206 wm8994);
4207 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
4208 wm8994);
4209 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4210 wm8994);
4211 break;
4212
4213 case WM1811:
4214 case WM8958:
4215 if (wm8994->micdet_irq)
4216 free_irq(wm8994->micdet_irq, wm8994);
4217 break;
4218 }
4219 release_firmware(wm8994->mbc);
4220 release_firmware(wm8994->mbc_vss);
4221 release_firmware(wm8994->enh_eq);
4222 kfree(wm8994->retune_mobile_texts);
4223 return 0;
4224 }
4225
4226 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4227 .probe = wm8994_codec_probe,
4228 .remove = wm8994_codec_remove,
4229 .suspend = wm8994_codec_suspend,
4230 .resume = wm8994_codec_resume,
4231 .set_bias_level = wm8994_set_bias_level,
4232 };
4233
4234 static int __devinit wm8994_probe(struct platform_device *pdev)
4235 {
4236 struct wm8994_priv *wm8994;
4237
4238 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4239 GFP_KERNEL);
4240 if (wm8994 == NULL)
4241 return -ENOMEM;
4242 platform_set_drvdata(pdev, wm8994);
4243
4244 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
4245 wm8994->pdata = dev_get_platdata(pdev->dev.parent);
4246
4247 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4248 wm8994_dai, ARRAY_SIZE(wm8994_dai));
4249 }
4250
4251 static int __devexit wm8994_remove(struct platform_device *pdev)
4252 {
4253 snd_soc_unregister_codec(&pdev->dev);
4254 return 0;
4255 }
4256
4257 #ifdef CONFIG_PM_SLEEP
4258 static int wm8994_suspend(struct device *dev)
4259 {
4260 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4261
4262 /* Drop down to power saving mode when system is suspended */
4263 if (wm8994->jackdet && !wm8994->active_refcount)
4264 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4265 WM1811_JACKDET_MODE_MASK,
4266 wm8994->jackdet_mode);
4267
4268 return 0;
4269 }
4270
4271 static int wm8994_resume(struct device *dev)
4272 {
4273 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4274
4275 if (wm8994->jackdet && wm8994->jack_cb)
4276 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4277 WM1811_JACKDET_MODE_MASK,
4278 WM1811_JACKDET_MODE_AUDIO);
4279
4280 return 0;
4281 }
4282 #endif
4283
4284 static const struct dev_pm_ops wm8994_pm_ops = {
4285 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4286 };
4287
4288 static struct platform_driver wm8994_codec_driver = {
4289 .driver = {
4290 .name = "wm8994-codec",
4291 .owner = THIS_MODULE,
4292 .pm = &wm8994_pm_ops,
4293 },
4294 .probe = wm8994_probe,
4295 .remove = __devexit_p(wm8994_remove),
4296 };
4297
4298 module_platform_driver(wm8994_codec_driver);
4299
4300 MODULE_DESCRIPTION("ASoC WM8994 driver");
4301 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4302 MODULE_LICENSE("GPL");
4303 MODULE_ALIAS("platform:wm8994-codec");
Linux kernel - Deliverables
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