2 * wm9081.c -- WM9081 ALSA SoC Audio driver
6 * Copyright 2009 Wolfson Microelectronics plc
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/soc.h>
25 #include <sound/soc-dapm.h>
26 #include <sound/initval.h>
27 #include <sound/tlv.h>
29 #include <sound/wm9081.h>
32 static u16 wm9081_reg_defaults
[] = {
33 0x0000, /* R0 - Software Reset */
35 0x00B9, /* R2 - Analogue Lineout */
36 0x00B9, /* R3 - Analogue Speaker PGA */
37 0x0001, /* R4 - VMID Control */
38 0x0068, /* R5 - Bias Control 1 */
40 0x0000, /* R7 - Analogue Mixer */
41 0x0000, /* R8 - Anti Pop Control */
42 0x01DB, /* R9 - Analogue Speaker 1 */
43 0x0018, /* R10 - Analogue Speaker 2 */
44 0x0180, /* R11 - Power Management */
45 0x0000, /* R12 - Clock Control 1 */
46 0x0038, /* R13 - Clock Control 2 */
47 0x4000, /* R14 - Clock Control 3 */
49 0x0000, /* R16 - FLL Control 1 */
50 0x0200, /* R17 - FLL Control 2 */
51 0x0000, /* R18 - FLL Control 3 */
52 0x0204, /* R19 - FLL Control 4 */
53 0x0000, /* R20 - FLL Control 5 */
55 0x0000, /* R22 - Audio Interface 1 */
56 0x0002, /* R23 - Audio Interface 2 */
57 0x0008, /* R24 - Audio Interface 3 */
58 0x0022, /* R25 - Audio Interface 4 */
59 0x0000, /* R26 - Interrupt Status */
60 0x0006, /* R27 - Interrupt Status Mask */
61 0x0000, /* R28 - Interrupt Polarity */
62 0x0000, /* R29 - Interrupt Control */
63 0x00C0, /* R30 - DAC Digital 1 */
64 0x0008, /* R31 - DAC Digital 2 */
65 0x09AF, /* R32 - DRC 1 */
66 0x4201, /* R33 - DRC 2 */
67 0x0000, /* R34 - DRC 3 */
68 0x0000, /* R35 - DRC 4 */
71 0x0000, /* R38 - Write Sequencer 1 */
72 0x0000, /* R39 - Write Sequencer 2 */
73 0x0002, /* R40 - MW Slave 1 */
75 0x0000, /* R42 - EQ 1 */
76 0x0000, /* R43 - EQ 2 */
77 0x0FCA, /* R44 - EQ 3 */
78 0x0400, /* R45 - EQ 4 */
79 0x00B8, /* R46 - EQ 5 */
80 0x1EB5, /* R47 - EQ 6 */
81 0xF145, /* R48 - EQ 7 */
82 0x0B75, /* R49 - EQ 8 */
83 0x01C5, /* R50 - EQ 9 */
84 0x169E, /* R51 - EQ 10 */
85 0xF829, /* R52 - EQ 11 */
86 0x07AD, /* R53 - EQ 12 */
87 0x1103, /* R54 - EQ 13 */
88 0x1C58, /* R55 - EQ 14 */
89 0xF373, /* R56 - EQ 15 */
90 0x0A54, /* R57 - EQ 16 */
91 0x0558, /* R58 - EQ 17 */
92 0x0564, /* R59 - EQ 18 */
93 0x0559, /* R60 - EQ 19 */
94 0x4000, /* R61 - EQ 20 */
100 } clk_sys_rates
[] = {
131 int div
; /* *10 due to .5s */
158 struct snd_soc_codec codec
;
159 u16 reg_cache
[WM9081_MAX_REGISTER
+ 1];
168 struct wm9081_retune_mobile_config
*retune
;
171 static int wm9081_reg_is_volatile(int reg
)
179 static unsigned int wm9081_read_reg_cache(struct snd_soc_codec
*codec
,
182 u16
*cache
= codec
->reg_cache
;
183 BUG_ON(reg
> WM9081_MAX_REGISTER
);
187 static unsigned int wm9081_read_hw(struct snd_soc_codec
*codec
, u8 reg
)
189 struct i2c_msg xfer
[2];
192 struct i2c_client
*client
= codec
->control_data
;
194 BUG_ON(reg
> WM9081_MAX_REGISTER
);
197 xfer
[0].addr
= client
->addr
;
203 xfer
[1].addr
= client
->addr
;
204 xfer
[1].flags
= I2C_M_RD
;
206 xfer
[1].buf
= (u8
*)&data
;
208 ret
= i2c_transfer(client
->adapter
, xfer
, 2);
210 dev_err(&client
->dev
, "i2c_transfer() returned %d\n", ret
);
214 return (data
>> 8) | ((data
& 0xff) << 8);
217 static unsigned int wm9081_read(struct snd_soc_codec
*codec
, unsigned int reg
)
219 if (wm9081_reg_is_volatile(reg
))
220 return wm9081_read_hw(codec
, reg
);
222 return wm9081_read_reg_cache(codec
, reg
);
225 static int wm9081_write(struct snd_soc_codec
*codec
, unsigned int reg
,
228 u16
*cache
= codec
->reg_cache
;
231 BUG_ON(reg
> WM9081_MAX_REGISTER
);
233 if (!wm9081_reg_is_volatile(reg
))
237 data
[1] = value
>> 8;
238 data
[2] = value
& 0x00ff;
240 if (codec
->hw_write(codec
->control_data
, data
, 3) == 3)
246 static int wm9081_reset(struct snd_soc_codec
*codec
)
248 return wm9081_write(codec
, WM9081_SOFTWARE_RESET
, 0);
251 static const DECLARE_TLV_DB_SCALE(drc_in_tlv
, -4500, 75, 0);
252 static const DECLARE_TLV_DB_SCALE(drc_out_tlv
, -2250, 75, 0);
253 static const DECLARE_TLV_DB_SCALE(drc_min_tlv
, -1800, 600, 0);
254 static unsigned int drc_max_tlv
[] = {
255 TLV_DB_RANGE_HEAD(4),
256 0, 0, TLV_DB_SCALE_ITEM(1200, 0, 0),
257 1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0),
258 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
259 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
261 static const DECLARE_TLV_DB_SCALE(drc_qr_tlv
, 1200, 600, 0);
262 static const DECLARE_TLV_DB_SCALE(drc_startup_tlv
, -300, 50, 0);
264 static const DECLARE_TLV_DB_SCALE(eq_tlv
, -1200, 100, 0);
266 static const DECLARE_TLV_DB_SCALE(in_tlv
, -600, 600, 0);
267 static const DECLARE_TLV_DB_SCALE(dac_tlv
, -7200, 75, 1);
268 static const DECLARE_TLV_DB_SCALE(out_tlv
, -5700, 100, 0);
270 static const char *drc_high_text
[] = {
279 static const struct soc_enum drc_high
=
280 SOC_ENUM_SINGLE(WM9081_DRC_3
, 3, 6, drc_high_text
);
282 static const char *drc_low_text
[] = {
290 static const struct soc_enum drc_low
=
291 SOC_ENUM_SINGLE(WM9081_DRC_3
, 0, 5, drc_low_text
);
293 static const char *drc_atk_text
[] = {
308 static const struct soc_enum drc_atk
=
309 SOC_ENUM_SINGLE(WM9081_DRC_2
, 12, 12, drc_atk_text
);
311 static const char *drc_dcy_text
[] = {
323 static const struct soc_enum drc_dcy
=
324 SOC_ENUM_SINGLE(WM9081_DRC_2
, 8, 9, drc_dcy_text
);
326 static const char *drc_qr_dcy_text
[] = {
332 static const struct soc_enum drc_qr_dcy
=
333 SOC_ENUM_SINGLE(WM9081_DRC_2
, 4, 3, drc_qr_dcy_text
);
335 static const char *dac_deemph_text
[] = {
342 static const struct soc_enum dac_deemph
=
343 SOC_ENUM_SINGLE(WM9081_DAC_DIGITAL_2
, 1, 4, dac_deemph_text
);
345 static const char *speaker_mode_text
[] = {
350 static const struct soc_enum speaker_mode
=
351 SOC_ENUM_SINGLE(WM9081_ANALOGUE_SPEAKER_2
, 6, 2, speaker_mode_text
);
353 static int speaker_mode_get(struct snd_kcontrol
*kcontrol
,
354 struct snd_ctl_elem_value
*ucontrol
)
356 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
359 reg
= wm9081_read(codec
, WM9081_ANALOGUE_SPEAKER_2
);
360 if (reg
& WM9081_SPK_MODE
)
361 ucontrol
->value
.integer
.value
[0] = 1;
363 ucontrol
->value
.integer
.value
[0] = 0;
369 * Stop any attempts to change speaker mode while the speaker is enabled.
371 * We also have some special anti-pop controls dependant on speaker
372 * mode which must be changed along with the mode.
374 static int speaker_mode_put(struct snd_kcontrol
*kcontrol
,
375 struct snd_ctl_elem_value
*ucontrol
)
377 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
378 unsigned int reg_pwr
= wm9081_read(codec
, WM9081_POWER_MANAGEMENT
);
379 unsigned int reg2
= wm9081_read(codec
, WM9081_ANALOGUE_SPEAKER_2
);
381 /* Are we changing anything? */
382 if (ucontrol
->value
.integer
.value
[0] ==
383 ((reg2
& WM9081_SPK_MODE
) != 0))
386 /* Don't try to change modes while enabled */
387 if (reg_pwr
& WM9081_SPK_ENA
)
390 if (ucontrol
->value
.integer
.value
[0]) {
392 reg2
&= ~(WM9081_SPK_INV_MUTE
| WM9081_OUT_SPK_CTRL
);
393 reg2
|= WM9081_SPK_MODE
;
396 reg2
|= WM9081_SPK_INV_MUTE
| WM9081_OUT_SPK_CTRL
;
397 reg2
&= ~WM9081_SPK_MODE
;
400 wm9081_write(codec
, WM9081_ANALOGUE_SPEAKER_2
, reg2
);
405 static const struct snd_kcontrol_new wm9081_snd_controls
[] = {
406 SOC_SINGLE_TLV("IN1 Volume", WM9081_ANALOGUE_MIXER
, 1, 1, 1, in_tlv
),
407 SOC_SINGLE_TLV("IN2 Volume", WM9081_ANALOGUE_MIXER
, 3, 1, 1, in_tlv
),
409 SOC_SINGLE_TLV("Playback Volume", WM9081_DAC_DIGITAL_1
, 1, 96, 0, dac_tlv
),
411 SOC_SINGLE("LINEOUT Switch", WM9081_ANALOGUE_LINEOUT
, 7, 1, 1),
412 SOC_SINGLE("LINEOUT ZC Switch", WM9081_ANALOGUE_LINEOUT
, 6, 1, 0),
413 SOC_SINGLE_TLV("LINEOUT Volume", WM9081_ANALOGUE_LINEOUT
, 0, 63, 0, out_tlv
),
415 SOC_SINGLE("DRC Switch", WM9081_DRC_1
, 15, 1, 0),
416 SOC_ENUM("DRC High Slope", drc_high
),
417 SOC_ENUM("DRC Low Slope", drc_low
),
418 SOC_SINGLE_TLV("DRC Input Volume", WM9081_DRC_4
, 5, 60, 1, drc_in_tlv
),
419 SOC_SINGLE_TLV("DRC Output Volume", WM9081_DRC_4
, 0, 30, 1, drc_out_tlv
),
420 SOC_SINGLE_TLV("DRC Minimum Volume", WM9081_DRC_2
, 2, 3, 1, drc_min_tlv
),
421 SOC_SINGLE_TLV("DRC Maximum Volume", WM9081_DRC_2
, 0, 3, 0, drc_max_tlv
),
422 SOC_ENUM("DRC Attack", drc_atk
),
423 SOC_ENUM("DRC Decay", drc_dcy
),
424 SOC_SINGLE("DRC Quick Release Switch", WM9081_DRC_1
, 2, 1, 0),
425 SOC_SINGLE_TLV("DRC Quick Release Volume", WM9081_DRC_2
, 6, 3, 0, drc_qr_tlv
),
426 SOC_ENUM("DRC Quick Release Decay", drc_qr_dcy
),
427 SOC_SINGLE_TLV("DRC Startup Volume", WM9081_DRC_1
, 6, 18, 0, drc_startup_tlv
),
429 SOC_SINGLE("EQ Switch", WM9081_EQ_1
, 0, 1, 0),
431 SOC_SINGLE("Speaker DC Volume", WM9081_ANALOGUE_SPEAKER_1
, 3, 5, 0),
432 SOC_SINGLE("Speaker AC Volume", WM9081_ANALOGUE_SPEAKER_1
, 0, 5, 0),
433 SOC_SINGLE("Speaker Switch", WM9081_ANALOGUE_SPEAKER_PGA
, 7, 1, 1),
434 SOC_SINGLE("Speaker ZC Switch", WM9081_ANALOGUE_SPEAKER_PGA
, 6, 1, 0),
435 SOC_SINGLE_TLV("Speaker Volume", WM9081_ANALOGUE_SPEAKER_PGA
, 0, 63, 0,
437 SOC_ENUM("DAC Deemphasis", dac_deemph
),
438 SOC_ENUM_EXT("Speaker Mode", speaker_mode
, speaker_mode_get
, speaker_mode_put
),
441 static const struct snd_kcontrol_new wm9081_eq_controls
[] = {
442 SOC_SINGLE_TLV("EQ1 Volume", WM9081_EQ_1
, 11, 24, 0, eq_tlv
),
443 SOC_SINGLE_TLV("EQ2 Volume", WM9081_EQ_1
, 6, 24, 0, eq_tlv
),
444 SOC_SINGLE_TLV("EQ3 Volume", WM9081_EQ_1
, 1, 24, 0, eq_tlv
),
445 SOC_SINGLE_TLV("EQ4 Volume", WM9081_EQ_2
, 11, 24, 0, eq_tlv
),
446 SOC_SINGLE_TLV("EQ5 Volume", WM9081_EQ_2
, 6, 24, 0, eq_tlv
),
449 static const struct snd_kcontrol_new mixer
[] = {
450 SOC_DAPM_SINGLE("IN1 Switch", WM9081_ANALOGUE_MIXER
, 0, 1, 0),
451 SOC_DAPM_SINGLE("IN2 Switch", WM9081_ANALOGUE_MIXER
, 2, 1, 0),
452 SOC_DAPM_SINGLE("Playback Switch", WM9081_ANALOGUE_MIXER
, 4, 1, 0),
455 static int speaker_event(struct snd_soc_dapm_widget
*w
,
456 struct snd_kcontrol
*kcontrol
, int event
)
458 struct snd_soc_codec
*codec
= w
->codec
;
459 unsigned int reg
= wm9081_read(codec
, WM9081_POWER_MANAGEMENT
);
462 case SND_SOC_DAPM_POST_PMU
:
463 reg
|= WM9081_SPK_ENA
;
466 case SND_SOC_DAPM_PRE_PMD
:
467 reg
&= ~WM9081_SPK_ENA
;
471 wm9081_write(codec
, WM9081_POWER_MANAGEMENT
, reg
);
484 /* The size in bits of the FLL divide multiplied by 10
485 * to allow rounding later */
486 #define FIXED_FLL_SIZE ((1 << 16) * 10)
495 { 64000, 128000, 3, 8 },
496 { 128000, 256000, 2, 4 },
497 { 256000, 1000000, 1, 2 },
498 { 1000000, 13500000, 0, 1 },
501 static int fll_factors(struct _fll_div
*fll_div
, unsigned int Fref
,
505 unsigned int K
, Ndiv
, Nmod
, target
;
509 /* Fref must be <=13.5MHz */
511 while ((Fref
/ div
) > 13500000) {
515 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
520 fll_div
->fll_clk_ref_div
= div
/ 2;
522 pr_debug("Fref=%u Fout=%u\n", Fref
, Fout
);
524 /* Apply the division for our remaining calculations */
527 /* Fvco should be 90-100MHz; don't check the upper bound */
530 while (target
< 90000000) {
534 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
539 fll_div
->fll_outdiv
= div
;
541 pr_debug("Fvco=%dHz\n", target
);
543 /* Find an appropraite FLL_FRATIO and factor it out of the target */
544 for (i
= 0; i
< ARRAY_SIZE(fll_fratios
); i
++) {
545 if (fll_fratios
[i
].min
<= Fref
&& Fref
<= fll_fratios
[i
].max
) {
546 fll_div
->fll_fratio
= fll_fratios
[i
].fll_fratio
;
547 target
/= fll_fratios
[i
].ratio
;
551 if (i
== ARRAY_SIZE(fll_fratios
)) {
552 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref
);
556 /* Now, calculate N.K */
557 Ndiv
= target
/ Fref
;
560 Nmod
= target
% Fref
;
561 pr_debug("Nmod=%d\n", Nmod
);
563 /* Calculate fractional part - scale up so we can round. */
564 Kpart
= FIXED_FLL_SIZE
* (long long)Nmod
;
568 K
= Kpart
& 0xFFFFFFFF;
573 /* Move down to proper range now rounding is done */
576 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
577 fll_div
->n
, fll_div
->k
,
578 fll_div
->fll_fratio
, fll_div
->fll_outdiv
,
579 fll_div
->fll_clk_ref_div
);
584 static int wm9081_set_fll(struct snd_soc_codec
*codec
, int fll_id
,
585 unsigned int Fref
, unsigned int Fout
)
587 struct wm9081_priv
*wm9081
= codec
->private_data
;
588 u16 reg1
, reg4
, reg5
;
589 struct _fll_div fll_div
;
594 if (Fref
== wm9081
->fll_fref
&& Fout
== wm9081
->fll_fout
)
597 /* Disable the FLL */
599 dev_dbg(codec
->dev
, "FLL disabled\n");
600 wm9081
->fll_fref
= 0;
601 wm9081
->fll_fout
= 0;
606 ret
= fll_factors(&fll_div
, Fref
, Fout
);
610 reg5
= wm9081_read(codec
, WM9081_FLL_CONTROL_5
);
611 reg5
&= ~WM9081_FLL_CLK_SRC_MASK
;
614 case WM9081_SYSCLK_FLL_MCLK
:
619 dev_err(codec
->dev
, "Unknown FLL ID %d\n", fll_id
);
623 /* Disable CLK_SYS while we reconfigure */
624 clk_sys_reg
= wm9081_read(codec
, WM9081_CLOCK_CONTROL_3
);
625 if (clk_sys_reg
& WM9081_CLK_SYS_ENA
)
626 wm9081_write(codec
, WM9081_CLOCK_CONTROL_3
,
627 clk_sys_reg
& ~WM9081_CLK_SYS_ENA
);
629 /* Any FLL configuration change requires that the FLL be
631 reg1
= wm9081_read(codec
, WM9081_FLL_CONTROL_1
);
632 reg1
&= ~WM9081_FLL_ENA
;
633 wm9081_write(codec
, WM9081_FLL_CONTROL_1
, reg1
);
635 /* Apply the configuration */
637 reg1
|= WM9081_FLL_FRAC_MASK
;
639 reg1
&= ~WM9081_FLL_FRAC_MASK
;
640 wm9081_write(codec
, WM9081_FLL_CONTROL_1
, reg1
);
642 wm9081_write(codec
, WM9081_FLL_CONTROL_2
,
643 (fll_div
.fll_outdiv
<< WM9081_FLL_OUTDIV_SHIFT
) |
644 (fll_div
.fll_fratio
<< WM9081_FLL_FRATIO_SHIFT
));
645 wm9081_write(codec
, WM9081_FLL_CONTROL_3
, fll_div
.k
);
647 reg4
= wm9081_read(codec
, WM9081_FLL_CONTROL_4
);
648 reg4
&= ~WM9081_FLL_N_MASK
;
649 reg4
|= fll_div
.n
<< WM9081_FLL_N_SHIFT
;
650 wm9081_write(codec
, WM9081_FLL_CONTROL_4
, reg4
);
652 reg5
&= ~WM9081_FLL_CLK_REF_DIV_MASK
;
653 reg5
|= fll_div
.fll_clk_ref_div
<< WM9081_FLL_CLK_REF_DIV_SHIFT
;
654 wm9081_write(codec
, WM9081_FLL_CONTROL_5
, reg5
);
657 wm9081_write(codec
, WM9081_FLL_CONTROL_1
, reg1
| WM9081_FLL_ENA
);
659 /* Then bring CLK_SYS up again if it was disabled */
660 if (clk_sys_reg
& WM9081_CLK_SYS_ENA
)
661 wm9081_write(codec
, WM9081_CLOCK_CONTROL_3
, clk_sys_reg
);
663 dev_dbg(codec
->dev
, "FLL enabled at %dHz->%dHz\n", Fref
, Fout
);
665 wm9081
->fll_fref
= Fref
;
666 wm9081
->fll_fout
= Fout
;
671 static int configure_clock(struct snd_soc_codec
*codec
)
673 struct wm9081_priv
*wm9081
= codec
->private_data
;
674 int new_sysclk
, i
, target
;
680 switch (wm9081
->sysclk_source
) {
681 case WM9081_SYSCLK_MCLK
:
682 if (wm9081
->mclk_rate
> 12225000) {
684 wm9081
->sysclk_rate
= wm9081
->mclk_rate
/ 2;
686 wm9081
->sysclk_rate
= wm9081
->mclk_rate
;
688 wm9081_set_fll(codec
, WM9081_SYSCLK_FLL_MCLK
, 0, 0);
691 case WM9081_SYSCLK_FLL_MCLK
:
692 /* If we have a sample rate calculate a CLK_SYS that
693 * gives us a suitable DAC configuration, plus BCLK.
694 * Ideally we would check to see if we can clock
695 * directly from MCLK and only use the FLL if this is
696 * not the case, though care must be taken with free
699 if (wm9081
->master
&& wm9081
->bclk
) {
700 /* Make sure we can generate CLK_SYS and BCLK
701 * and that we've got 3MHz for optimal
703 for (i
= 0; i
< ARRAY_SIZE(clk_sys_rates
); i
++) {
704 target
= wm9081
->fs
* clk_sys_rates
[i
].ratio
;
706 if (target
>= wm9081
->bclk
&&
710 } else if (wm9081
->fs
) {
711 for (i
= 0; i
< ARRAY_SIZE(clk_sys_rates
); i
++) {
712 new_sysclk
= clk_sys_rates
[i
].ratio
714 if (new_sysclk
> 3000000)
718 new_sysclk
= 12288000;
721 ret
= wm9081_set_fll(codec
, WM9081_SYSCLK_FLL_MCLK
,
722 wm9081
->mclk_rate
, new_sysclk
);
724 wm9081
->sysclk_rate
= new_sysclk
;
726 /* Switch SYSCLK over to FLL */
729 wm9081
->sysclk_rate
= wm9081
->mclk_rate
;
737 reg
= wm9081_read(codec
, WM9081_CLOCK_CONTROL_1
);
739 reg
|= WM9081_MCLKDIV2
;
741 reg
&= ~WM9081_MCLKDIV2
;
742 wm9081_write(codec
, WM9081_CLOCK_CONTROL_1
, reg
);
744 reg
= wm9081_read(codec
, WM9081_CLOCK_CONTROL_3
);
746 reg
|= WM9081_CLK_SRC_SEL
;
748 reg
&= ~WM9081_CLK_SRC_SEL
;
749 wm9081_write(codec
, WM9081_CLOCK_CONTROL_3
, reg
);
751 dev_dbg(codec
->dev
, "CLK_SYS is %dHz\n", wm9081
->sysclk_rate
);
756 static int clk_sys_event(struct snd_soc_dapm_widget
*w
,
757 struct snd_kcontrol
*kcontrol
, int event
)
759 struct snd_soc_codec
*codec
= w
->codec
;
760 struct wm9081_priv
*wm9081
= codec
->private_data
;
762 /* This should be done on init() for bypass paths */
763 switch (wm9081
->sysclk_source
) {
764 case WM9081_SYSCLK_MCLK
:
765 dev_dbg(codec
->dev
, "Using %dHz MCLK\n", wm9081
->mclk_rate
);
767 case WM9081_SYSCLK_FLL_MCLK
:
768 dev_dbg(codec
->dev
, "Using %dHz MCLK with FLL\n",
772 dev_err(codec
->dev
, "System clock not configured\n");
777 case SND_SOC_DAPM_PRE_PMU
:
778 configure_clock(codec
);
781 case SND_SOC_DAPM_POST_PMD
:
782 /* Disable the FLL if it's running */
783 wm9081_set_fll(codec
, 0, 0, 0);
790 static const struct snd_soc_dapm_widget wm9081_dapm_widgets
[] = {
791 SND_SOC_DAPM_INPUT("IN1"),
792 SND_SOC_DAPM_INPUT("IN2"),
794 SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM9081_POWER_MANAGEMENT
, 0, 0),
796 SND_SOC_DAPM_MIXER_NAMED_CTL("Mixer", SND_SOC_NOPM
, 0, 0,
797 mixer
, ARRAY_SIZE(mixer
)),
799 SND_SOC_DAPM_PGA("LINEOUT PGA", WM9081_POWER_MANAGEMENT
, 4, 0, NULL
, 0),
801 SND_SOC_DAPM_PGA_E("Speaker PGA", WM9081_POWER_MANAGEMENT
, 2, 0, NULL
, 0,
803 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
805 SND_SOC_DAPM_OUTPUT("LINEOUT"),
806 SND_SOC_DAPM_OUTPUT("SPKN"),
807 SND_SOC_DAPM_OUTPUT("SPKP"),
809 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM9081_CLOCK_CONTROL_3
, 0, 0, clk_sys_event
,
810 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
811 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM9081_CLOCK_CONTROL_3
, 1, 0, NULL
, 0),
812 SND_SOC_DAPM_SUPPLY("TOCLK", WM9081_CLOCK_CONTROL_3
, 2, 0, NULL
, 0),
816 static const struct snd_soc_dapm_route audio_paths
[] = {
817 { "DAC", NULL
, "CLK_SYS" },
818 { "DAC", NULL
, "CLK_DSP" },
820 { "Mixer", "IN1 Switch", "IN1" },
821 { "Mixer", "IN2 Switch", "IN2" },
822 { "Mixer", "Playback Switch", "DAC" },
824 { "LINEOUT PGA", NULL
, "Mixer" },
825 { "LINEOUT PGA", NULL
, "TOCLK" },
826 { "LINEOUT PGA", NULL
, "CLK_SYS" },
828 { "LINEOUT", NULL
, "LINEOUT PGA" },
830 { "Speaker PGA", NULL
, "Mixer" },
831 { "Speaker PGA", NULL
, "TOCLK" },
832 { "Speaker PGA", NULL
, "CLK_SYS" },
834 { "SPKN", NULL
, "Speaker PGA" },
835 { "SPKP", NULL
, "Speaker PGA" },
838 static int wm9081_set_bias_level(struct snd_soc_codec
*codec
,
839 enum snd_soc_bias_level level
)
844 case SND_SOC_BIAS_ON
:
847 case SND_SOC_BIAS_PREPARE
:
849 reg
= wm9081_read(codec
, WM9081_VMID_CONTROL
);
850 reg
&= ~WM9081_VMID_SEL_MASK
;
852 wm9081_write(codec
, WM9081_VMID_CONTROL
, reg
);
854 /* Normal bias current */
855 reg
= wm9081_read(codec
, WM9081_BIAS_CONTROL_1
);
856 reg
&= ~WM9081_STBY_BIAS_ENA
;
857 wm9081_write(codec
, WM9081_BIAS_CONTROL_1
, reg
);
860 case SND_SOC_BIAS_STANDBY
:
861 /* Initial cold start */
862 if (codec
->bias_level
== SND_SOC_BIAS_OFF
) {
863 /* Disable LINEOUT discharge */
864 reg
= wm9081_read(codec
, WM9081_ANTI_POP_CONTROL
);
865 reg
&= ~WM9081_LINEOUT_DISCH
;
866 wm9081_write(codec
, WM9081_ANTI_POP_CONTROL
, reg
);
868 /* Select startup bias source */
869 reg
= wm9081_read(codec
, WM9081_BIAS_CONTROL_1
);
870 reg
|= WM9081_BIAS_SRC
| WM9081_BIAS_ENA
;
871 wm9081_write(codec
, WM9081_BIAS_CONTROL_1
, reg
);
873 /* VMID 2*4k; Soft VMID ramp enable */
874 reg
= wm9081_read(codec
, WM9081_VMID_CONTROL
);
875 reg
|= WM9081_VMID_RAMP
| 0x6;
876 wm9081_write(codec
, WM9081_VMID_CONTROL
, reg
);
880 /* Normal bias enable & soft start off */
881 reg
|= WM9081_BIAS_ENA
;
882 reg
&= ~WM9081_VMID_RAMP
;
883 wm9081_write(codec
, WM9081_VMID_CONTROL
, reg
);
885 /* Standard bias source */
886 reg
= wm9081_read(codec
, WM9081_BIAS_CONTROL_1
);
887 reg
&= ~WM9081_BIAS_SRC
;
888 wm9081_write(codec
, WM9081_BIAS_CONTROL_1
, reg
);
892 reg
= wm9081_read(codec
, WM9081_BIAS_CONTROL_1
);
893 reg
&= ~WM9081_VMID_SEL_MASK
;
895 wm9081_write(codec
, WM9081_VMID_CONTROL
, reg
);
897 /* Standby bias current on */
898 reg
= wm9081_read(codec
, WM9081_BIAS_CONTROL_1
);
899 reg
|= WM9081_STBY_BIAS_ENA
;
900 wm9081_write(codec
, WM9081_BIAS_CONTROL_1
, reg
);
903 case SND_SOC_BIAS_OFF
:
904 /* Startup bias source */
905 reg
= wm9081_read(codec
, WM9081_BIAS_CONTROL_1
);
906 reg
|= WM9081_BIAS_SRC
;
907 wm9081_write(codec
, WM9081_BIAS_CONTROL_1
, reg
);
909 /* Disable VMID and biases with soft ramping */
910 reg
= wm9081_read(codec
, WM9081_VMID_CONTROL
);
911 reg
&= ~(WM9081_VMID_SEL_MASK
| WM9081_BIAS_ENA
);
912 reg
|= WM9081_VMID_RAMP
;
913 wm9081_write(codec
, WM9081_VMID_CONTROL
, reg
);
915 /* Actively discharge LINEOUT */
916 reg
= wm9081_read(codec
, WM9081_ANTI_POP_CONTROL
);
917 reg
|= WM9081_LINEOUT_DISCH
;
918 wm9081_write(codec
, WM9081_ANTI_POP_CONTROL
, reg
);
922 codec
->bias_level
= level
;
927 static int wm9081_set_dai_fmt(struct snd_soc_dai
*dai
,
930 struct snd_soc_codec
*codec
= dai
->codec
;
931 struct wm9081_priv
*wm9081
= codec
->private_data
;
932 unsigned int aif2
= wm9081_read(codec
, WM9081_AUDIO_INTERFACE_2
);
934 aif2
&= ~(WM9081_AIF_BCLK_INV
| WM9081_AIF_LRCLK_INV
|
935 WM9081_BCLK_DIR
| WM9081_LRCLK_DIR
| WM9081_AIF_FMT_MASK
);
937 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
938 case SND_SOC_DAIFMT_CBS_CFS
:
941 case SND_SOC_DAIFMT_CBS_CFM
:
942 aif2
|= WM9081_LRCLK_DIR
;
945 case SND_SOC_DAIFMT_CBM_CFS
:
946 aif2
|= WM9081_BCLK_DIR
;
949 case SND_SOC_DAIFMT_CBM_CFM
:
950 aif2
|= WM9081_LRCLK_DIR
| WM9081_BCLK_DIR
;
957 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
958 case SND_SOC_DAIFMT_DSP_B
:
959 aif2
|= WM9081_AIF_LRCLK_INV
;
960 case SND_SOC_DAIFMT_DSP_A
:
963 case SND_SOC_DAIFMT_I2S
:
966 case SND_SOC_DAIFMT_RIGHT_J
:
968 case SND_SOC_DAIFMT_LEFT_J
:
975 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
976 case SND_SOC_DAIFMT_DSP_A
:
977 case SND_SOC_DAIFMT_DSP_B
:
978 /* frame inversion not valid for DSP modes */
979 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
980 case SND_SOC_DAIFMT_NB_NF
:
982 case SND_SOC_DAIFMT_IB_NF
:
983 aif2
|= WM9081_AIF_BCLK_INV
;
990 case SND_SOC_DAIFMT_I2S
:
991 case SND_SOC_DAIFMT_RIGHT_J
:
992 case SND_SOC_DAIFMT_LEFT_J
:
993 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
994 case SND_SOC_DAIFMT_NB_NF
:
996 case SND_SOC_DAIFMT_IB_IF
:
997 aif2
|= WM9081_AIF_BCLK_INV
| WM9081_AIF_LRCLK_INV
;
999 case SND_SOC_DAIFMT_IB_NF
:
1000 aif2
|= WM9081_AIF_BCLK_INV
;
1002 case SND_SOC_DAIFMT_NB_IF
:
1003 aif2
|= WM9081_AIF_LRCLK_INV
;
1013 wm9081_write(codec
, WM9081_AUDIO_INTERFACE_2
, aif2
);
1018 static int wm9081_hw_params(struct snd_pcm_substream
*substream
,
1019 struct snd_pcm_hw_params
*params
,
1020 struct snd_soc_dai
*dai
)
1022 struct snd_soc_codec
*codec
= dai
->codec
;
1023 struct wm9081_priv
*wm9081
= codec
->private_data
;
1024 int ret
, i
, best
, best_val
, cur_val
;
1025 unsigned int clk_ctrl2
, aif1
, aif2
, aif3
, aif4
;
1027 clk_ctrl2
= wm9081_read(codec
, WM9081_CLOCK_CONTROL_2
);
1028 clk_ctrl2
&= ~(WM9081_CLK_SYS_RATE_MASK
| WM9081_SAMPLE_RATE_MASK
);
1030 aif1
= wm9081_read(codec
, WM9081_AUDIO_INTERFACE_1
);
1032 aif2
= wm9081_read(codec
, WM9081_AUDIO_INTERFACE_2
);
1033 aif2
&= ~WM9081_AIF_WL_MASK
;
1035 aif3
= wm9081_read(codec
, WM9081_AUDIO_INTERFACE_3
);
1036 aif3
&= ~WM9081_BCLK_DIV_MASK
;
1038 aif4
= wm9081_read(codec
, WM9081_AUDIO_INTERFACE_4
);
1039 aif4
&= ~WM9081_LRCLK_RATE_MASK
;
1041 /* What BCLK do we need? */
1042 wm9081
->fs
= params_rate(params
);
1043 wm9081
->bclk
= 2 * wm9081
->fs
;
1044 switch (params_format(params
)) {
1045 case SNDRV_PCM_FORMAT_S16_LE
:
1048 case SNDRV_PCM_FORMAT_S20_3LE
:
1052 case SNDRV_PCM_FORMAT_S24_LE
:
1056 case SNDRV_PCM_FORMAT_S32_LE
:
1064 if (aif1
& WM9081_AIFDAC_TDM_MODE_MASK
) {
1065 int slots
= ((aif1
& WM9081_AIFDAC_TDM_MODE_MASK
) >>
1066 WM9081_AIFDAC_TDM_MODE_SHIFT
) + 1;
1067 wm9081
->bclk
*= slots
;
1070 dev_dbg(codec
->dev
, "Target BCLK is %dHz\n", wm9081
->bclk
);
1072 ret
= configure_clock(codec
);
1076 /* Select nearest CLK_SYS_RATE */
1078 best_val
= abs((wm9081
->sysclk_rate
/ clk_sys_rates
[0].ratio
)
1080 for (i
= 1; i
< ARRAY_SIZE(clk_sys_rates
); i
++) {
1081 cur_val
= abs((wm9081
->sysclk_rate
/
1082 clk_sys_rates
[i
].ratio
) - wm9081
->fs
);;
1083 if (cur_val
< best_val
) {
1088 dev_dbg(codec
->dev
, "Selected CLK_SYS_RATIO of %d\n",
1089 clk_sys_rates
[best
].ratio
);
1090 clk_ctrl2
|= (clk_sys_rates
[best
].clk_sys_rate
1091 << WM9081_CLK_SYS_RATE_SHIFT
);
1095 best_val
= abs(wm9081
->fs
- sample_rates
[0].rate
);
1096 for (i
= 1; i
< ARRAY_SIZE(sample_rates
); i
++) {
1098 cur_val
= abs(wm9081
->fs
- sample_rates
[i
].rate
);
1099 if (cur_val
< best_val
) {
1104 dev_dbg(codec
->dev
, "Selected SAMPLE_RATE of %dHz\n",
1105 sample_rates
[best
].rate
);
1106 clk_ctrl2
|= (sample_rates
[best
].sample_rate
1107 << WM9081_SAMPLE_RATE_SHIFT
);
1112 for (i
= 0; i
< ARRAY_SIZE(bclk_divs
); i
++) {
1113 cur_val
= ((wm9081
->sysclk_rate
* 10) / bclk_divs
[i
].div
)
1115 if (cur_val
< 0) /* Table is sorted */
1117 if (cur_val
< best_val
) {
1122 wm9081
->bclk
= (wm9081
->sysclk_rate
* 10) / bclk_divs
[best
].div
;
1123 dev_dbg(codec
->dev
, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1124 bclk_divs
[best
].div
, wm9081
->bclk
);
1125 aif3
|= bclk_divs
[best
].bclk_div
;
1127 /* LRCLK is a simple fraction of BCLK */
1128 dev_dbg(codec
->dev
, "LRCLK_RATE is %d\n", wm9081
->bclk
/ wm9081
->fs
);
1129 aif4
|= wm9081
->bclk
/ wm9081
->fs
;
1131 /* Apply a ReTune Mobile configuration if it's in use */
1132 if (wm9081
->retune
) {
1133 struct wm9081_retune_mobile_config
*retune
= wm9081
->retune
;
1134 struct wm9081_retune_mobile_setting
*s
;
1138 best_val
= abs(retune
->configs
[0].rate
- wm9081
->fs
);
1139 for (i
= 0; i
< retune
->num_configs
; i
++) {
1140 cur_val
= abs(retune
->configs
[i
].rate
- wm9081
->fs
);
1141 if (cur_val
< best_val
) {
1146 s
= &retune
->configs
[best
];
1148 dev_dbg(codec
->dev
, "ReTune Mobile %s tuned for %dHz\n",
1151 /* If the EQ is enabled then disable it while we write out */
1152 eq1
= wm9081_read(codec
, WM9081_EQ_1
) & WM9081_EQ_ENA
;
1153 if (eq1
& WM9081_EQ_ENA
)
1154 wm9081_write(codec
, WM9081_EQ_1
, 0);
1156 /* Write out the other values */
1157 for (i
= 1; i
< ARRAY_SIZE(s
->config
); i
++)
1158 wm9081_write(codec
, WM9081_EQ_1
+ i
, s
->config
[i
]);
1160 eq1
|= (s
->config
[0] & ~WM9081_EQ_ENA
);
1161 wm9081_write(codec
, WM9081_EQ_1
, eq1
);
1164 wm9081_write(codec
, WM9081_CLOCK_CONTROL_2
, clk_ctrl2
);
1165 wm9081_write(codec
, WM9081_AUDIO_INTERFACE_2
, aif2
);
1166 wm9081_write(codec
, WM9081_AUDIO_INTERFACE_3
, aif3
);
1167 wm9081_write(codec
, WM9081_AUDIO_INTERFACE_4
, aif4
);
1172 static int wm9081_digital_mute(struct snd_soc_dai
*codec_dai
, int mute
)
1174 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1177 reg
= wm9081_read(codec
, WM9081_DAC_DIGITAL_2
);
1180 reg
|= WM9081_DAC_MUTE
;
1182 reg
&= ~WM9081_DAC_MUTE
;
1184 wm9081_write(codec
, WM9081_DAC_DIGITAL_2
, reg
);
1189 static int wm9081_set_sysclk(struct snd_soc_dai
*codec_dai
,
1190 int clk_id
, unsigned int freq
, int dir
)
1192 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1193 struct wm9081_priv
*wm9081
= codec
->private_data
;
1196 case WM9081_SYSCLK_MCLK
:
1197 case WM9081_SYSCLK_FLL_MCLK
:
1198 wm9081
->sysclk_source
= clk_id
;
1199 wm9081
->mclk_rate
= freq
;
1209 static int wm9081_set_tdm_slot(struct snd_soc_dai
*dai
,
1210 unsigned int mask
, int slots
)
1212 struct snd_soc_codec
*codec
= dai
->codec
;
1213 unsigned int aif1
= wm9081_read(codec
, WM9081_AUDIO_INTERFACE_1
);
1215 aif1
&= ~(WM9081_AIFDAC_TDM_SLOT_MASK
| WM9081_AIFDAC_TDM_MODE_MASK
);
1217 if (slots
< 1 || slots
> 4)
1220 aif1
|= (slots
- 1) << WM9081_AIFDAC_TDM_MODE_SHIFT
;
1238 wm9081_write(codec
, WM9081_AUDIO_INTERFACE_1
, aif1
);
1243 #define WM9081_RATES SNDRV_PCM_RATE_8000_96000
1245 #define WM9081_FORMATS \
1246 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1247 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1249 static struct snd_soc_dai_ops wm9081_dai_ops
= {
1250 .hw_params
= wm9081_hw_params
,
1251 .set_sysclk
= wm9081_set_sysclk
,
1252 .set_fmt
= wm9081_set_dai_fmt
,
1253 .digital_mute
= wm9081_digital_mute
,
1254 .set_tdm_slot
= wm9081_set_tdm_slot
,
1257 /* We report two channels because the CODEC processes a stereo signal, even
1258 * though it is only capable of handling a mono output.
1260 struct snd_soc_dai wm9081_dai
= {
1263 .stream_name
= "HiFi Playback",
1266 .rates
= WM9081_RATES
,
1267 .formats
= WM9081_FORMATS
,
1269 .ops
= &wm9081_dai_ops
,
1271 EXPORT_SYMBOL_GPL(wm9081_dai
);
1274 static struct snd_soc_codec
*wm9081_codec
;
1276 static int wm9081_probe(struct platform_device
*pdev
)
1278 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1279 struct snd_soc_codec
*codec
;
1280 struct wm9081_priv
*wm9081
;
1283 if (wm9081_codec
== NULL
) {
1284 dev_err(&pdev
->dev
, "Codec device not registered\n");
1288 socdev
->card
->codec
= wm9081_codec
;
1289 codec
= wm9081_codec
;
1290 wm9081
= codec
->private_data
;
1293 ret
= snd_soc_new_pcms(socdev
, SNDRV_DEFAULT_IDX1
, SNDRV_DEFAULT_STR1
);
1295 dev_err(codec
->dev
, "failed to create pcms: %d\n", ret
);
1299 snd_soc_add_controls(codec
, wm9081_snd_controls
,
1300 ARRAY_SIZE(wm9081_snd_controls
));
1301 if (!wm9081
->retune
) {
1303 "No ReTune Mobile data, using normal EQ\n");
1304 snd_soc_add_controls(codec
, wm9081_eq_controls
,
1305 ARRAY_SIZE(wm9081_eq_controls
));
1308 snd_soc_dapm_new_controls(codec
, wm9081_dapm_widgets
,
1309 ARRAY_SIZE(wm9081_dapm_widgets
));
1310 snd_soc_dapm_add_routes(codec
, audio_paths
, ARRAY_SIZE(audio_paths
));
1311 snd_soc_dapm_new_widgets(codec
);
1313 ret
= snd_soc_init_card(socdev
);
1315 dev_err(codec
->dev
, "failed to register card: %d\n", ret
);
1322 snd_soc_free_pcms(socdev
);
1323 snd_soc_dapm_free(socdev
);
1328 static int wm9081_remove(struct platform_device
*pdev
)
1330 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1332 snd_soc_free_pcms(socdev
);
1333 snd_soc_dapm_free(socdev
);
1339 static int wm9081_suspend(struct platform_device
*pdev
, pm_message_t state
)
1341 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1342 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
1344 wm9081_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1349 static int wm9081_resume(struct platform_device
*pdev
)
1351 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1352 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
1353 u16
*reg_cache
= codec
->reg_cache
;
1356 for (i
= 0; i
< codec
->reg_cache_size
; i
++) {
1357 if (i
== WM9081_SOFTWARE_RESET
)
1360 wm9081_write(codec
, i
, reg_cache
[i
]);
1363 wm9081_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1368 #define wm9081_suspend NULL
1369 #define wm9081_resume NULL
1372 struct snd_soc_codec_device soc_codec_dev_wm9081
= {
1373 .probe
= wm9081_probe
,
1374 .remove
= wm9081_remove
,
1375 .suspend
= wm9081_suspend
,
1376 .resume
= wm9081_resume
,
1378 EXPORT_SYMBOL_GPL(soc_codec_dev_wm9081
);
1380 static int wm9081_register(struct wm9081_priv
*wm9081
)
1382 struct snd_soc_codec
*codec
= &wm9081
->codec
;
1387 dev_err(codec
->dev
, "Another WM9081 is registered\n");
1392 mutex_init(&codec
->mutex
);
1393 INIT_LIST_HEAD(&codec
->dapm_widgets
);
1394 INIT_LIST_HEAD(&codec
->dapm_paths
);
1396 codec
->private_data
= wm9081
;
1397 codec
->name
= "WM9081";
1398 codec
->owner
= THIS_MODULE
;
1399 codec
->read
= wm9081_read
;
1400 codec
->write
= wm9081_write
;
1401 codec
->dai
= &wm9081_dai
;
1403 codec
->reg_cache_size
= ARRAY_SIZE(wm9081
->reg_cache
);
1404 codec
->reg_cache
= &wm9081
->reg_cache
;
1405 codec
->bias_level
= SND_SOC_BIAS_OFF
;
1406 codec
->set_bias_level
= wm9081_set_bias_level
;
1408 memcpy(codec
->reg_cache
, wm9081_reg_defaults
,
1409 sizeof(wm9081_reg_defaults
));
1411 reg
= wm9081_read_hw(codec
, WM9081_SOFTWARE_RESET
);
1412 if (reg
!= 0x9081) {
1413 dev_err(codec
->dev
, "Device is not a WM9081: ID=0x%x\n", reg
);
1418 ret
= wm9081_reset(codec
);
1420 dev_err(codec
->dev
, "Failed to issue reset\n");
1424 wm9081_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1426 /* Enable zero cross by default */
1427 reg
= wm9081_read(codec
, WM9081_ANALOGUE_LINEOUT
);
1428 wm9081_write(codec
, WM9081_ANALOGUE_LINEOUT
, reg
| WM9081_LINEOUTZC
);
1429 reg
= wm9081_read(codec
, WM9081_ANALOGUE_SPEAKER_PGA
);
1430 wm9081_write(codec
, WM9081_ANALOGUE_SPEAKER_PGA
,
1431 reg
| WM9081_SPKPGAZC
);
1433 wm9081_dai
.dev
= codec
->dev
;
1435 wm9081_codec
= codec
;
1437 ret
= snd_soc_register_codec(codec
);
1439 dev_err(codec
->dev
, "Failed to register codec: %d\n", ret
);
1443 ret
= snd_soc_register_dai(&wm9081_dai
);
1445 dev_err(codec
->dev
, "Failed to register DAI: %d\n", ret
);
1446 snd_soc_unregister_codec(codec
);
1457 static void wm9081_unregister(struct wm9081_priv
*wm9081
)
1459 wm9081_set_bias_level(&wm9081
->codec
, SND_SOC_BIAS_OFF
);
1460 snd_soc_unregister_dai(&wm9081_dai
);
1461 snd_soc_unregister_codec(&wm9081
->codec
);
1463 wm9081_codec
= NULL
;
1466 static __devinit
int wm9081_i2c_probe(struct i2c_client
*i2c
,
1467 const struct i2c_device_id
*id
)
1469 struct wm9081_priv
*wm9081
;
1470 struct snd_soc_codec
*codec
;
1472 wm9081
= kzalloc(sizeof(struct wm9081_priv
), GFP_KERNEL
);
1476 codec
= &wm9081
->codec
;
1477 codec
->hw_write
= (hw_write_t
)i2c_master_send
;
1478 wm9081
->retune
= i2c
->dev
.platform_data
;
1480 i2c_set_clientdata(i2c
, wm9081
);
1481 codec
->control_data
= i2c
;
1483 codec
->dev
= &i2c
->dev
;
1485 return wm9081_register(wm9081
);
1488 static __devexit
int wm9081_i2c_remove(struct i2c_client
*client
)
1490 struct wm9081_priv
*wm9081
= i2c_get_clientdata(client
);
1491 wm9081_unregister(wm9081
);
1496 static int wm9081_i2c_suspend(struct i2c_client
*client
, pm_message_t msg
)
1498 return snd_soc_suspend_device(&client
->dev
);
1501 static int wm9081_i2c_resume(struct i2c_client
*client
)
1503 return snd_soc_resume_device(&client
->dev
);
1506 #define wm9081_i2c_suspend NULL
1507 #define wm9081_i2c_resume NULL
1510 static const struct i2c_device_id wm9081_i2c_id
[] = {
1514 MODULE_DEVICE_TABLE(i2c
, wm9081_i2c_id
);
1516 static struct i2c_driver wm9081_i2c_driver
= {
1519 .owner
= THIS_MODULE
,
1521 .probe
= wm9081_i2c_probe
,
1522 .remove
= __devexit_p(wm9081_i2c_remove
),
1523 .suspend
= wm9081_i2c_suspend
,
1524 .resume
= wm9081_i2c_resume
,
1525 .id_table
= wm9081_i2c_id
,
1528 static int __init
wm9081_modinit(void)
1532 ret
= i2c_add_driver(&wm9081_i2c_driver
);
1534 printk(KERN_ERR
"Failed to register WM9081 I2C driver: %d\n",
1540 module_init(wm9081_modinit
);
1542 static void __exit
wm9081_exit(void)
1544 i2c_del_driver(&wm9081_i2c_driver
);
1546 module_exit(wm9081_exit
);
1549 MODULE_DESCRIPTION("ASoC WM9081 driver");
1550 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1551 MODULE_LICENSE("GPL");