2 * wm9081.c -- WM9081 ALSA SoC Audio driver
6 * Copyright 2009 Wolfson Microelectronics plc
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
30 #include <sound/wm9081.h>
33 static u16 wm9081_reg_defaults
[] = {
34 0x0000, /* R0 - Software Reset */
36 0x00B9, /* R2 - Analogue Lineout */
37 0x00B9, /* R3 - Analogue Speaker PGA */
38 0x0001, /* R4 - VMID Control */
39 0x0068, /* R5 - Bias Control 1 */
41 0x0000, /* R7 - Analogue Mixer */
42 0x0000, /* R8 - Anti Pop Control */
43 0x01DB, /* R9 - Analogue Speaker 1 */
44 0x0018, /* R10 - Analogue Speaker 2 */
45 0x0180, /* R11 - Power Management */
46 0x0000, /* R12 - Clock Control 1 */
47 0x0038, /* R13 - Clock Control 2 */
48 0x4000, /* R14 - Clock Control 3 */
50 0x0000, /* R16 - FLL Control 1 */
51 0x0200, /* R17 - FLL Control 2 */
52 0x0000, /* R18 - FLL Control 3 */
53 0x0204, /* R19 - FLL Control 4 */
54 0x0000, /* R20 - FLL Control 5 */
56 0x0000, /* R22 - Audio Interface 1 */
57 0x0002, /* R23 - Audio Interface 2 */
58 0x0008, /* R24 - Audio Interface 3 */
59 0x0022, /* R25 - Audio Interface 4 */
60 0x0000, /* R26 - Interrupt Status */
61 0x0006, /* R27 - Interrupt Status Mask */
62 0x0000, /* R28 - Interrupt Polarity */
63 0x0000, /* R29 - Interrupt Control */
64 0x00C0, /* R30 - DAC Digital 1 */
65 0x0008, /* R31 - DAC Digital 2 */
66 0x09AF, /* R32 - DRC 1 */
67 0x4201, /* R33 - DRC 2 */
68 0x0000, /* R34 - DRC 3 */
69 0x0000, /* R35 - DRC 4 */
72 0x0000, /* R38 - Write Sequencer 1 */
73 0x0000, /* R39 - Write Sequencer 2 */
74 0x0002, /* R40 - MW Slave 1 */
76 0x0000, /* R42 - EQ 1 */
77 0x0000, /* R43 - EQ 2 */
78 0x0FCA, /* R44 - EQ 3 */
79 0x0400, /* R45 - EQ 4 */
80 0x00B8, /* R46 - EQ 5 */
81 0x1EB5, /* R47 - EQ 6 */
82 0xF145, /* R48 - EQ 7 */
83 0x0B75, /* R49 - EQ 8 */
84 0x01C5, /* R50 - EQ 9 */
85 0x169E, /* R51 - EQ 10 */
86 0xF829, /* R52 - EQ 11 */
87 0x07AD, /* R53 - EQ 12 */
88 0x1103, /* R54 - EQ 13 */
89 0x1C58, /* R55 - EQ 14 */
90 0xF373, /* R56 - EQ 15 */
91 0x0A54, /* R57 - EQ 16 */
92 0x0558, /* R58 - EQ 17 */
93 0x0564, /* R59 - EQ 18 */
94 0x0559, /* R60 - EQ 19 */
95 0x4000, /* R61 - EQ 20 */
101 } clk_sys_rates
[] = {
132 int div
; /* *10 due to .5s */
159 enum snd_soc_control_type control_type
;
170 struct wm9081_retune_mobile_config
*retune
;
173 static int wm9081_volatile_register(unsigned int reg
)
176 case WM9081_SOFTWARE_RESET
:
183 static int wm9081_reset(struct snd_soc_codec
*codec
)
185 return snd_soc_write(codec
, WM9081_SOFTWARE_RESET
, 0);
188 static const DECLARE_TLV_DB_SCALE(drc_in_tlv
, -4500, 75, 0);
189 static const DECLARE_TLV_DB_SCALE(drc_out_tlv
, -2250, 75, 0);
190 static const DECLARE_TLV_DB_SCALE(drc_min_tlv
, -1800, 600, 0);
191 static unsigned int drc_max_tlv
[] = {
192 TLV_DB_RANGE_HEAD(4),
193 0, 0, TLV_DB_SCALE_ITEM(1200, 0, 0),
194 1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0),
195 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
196 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
198 static const DECLARE_TLV_DB_SCALE(drc_qr_tlv
, 1200, 600, 0);
199 static const DECLARE_TLV_DB_SCALE(drc_startup_tlv
, -300, 50, 0);
201 static const DECLARE_TLV_DB_SCALE(eq_tlv
, -1200, 100, 0);
203 static const DECLARE_TLV_DB_SCALE(in_tlv
, -600, 600, 0);
204 static const DECLARE_TLV_DB_SCALE(dac_tlv
, -7200, 75, 1);
205 static const DECLARE_TLV_DB_SCALE(out_tlv
, -5700, 100, 0);
207 static const char *drc_high_text
[] = {
216 static const struct soc_enum drc_high
=
217 SOC_ENUM_SINGLE(WM9081_DRC_3
, 3, 6, drc_high_text
);
219 static const char *drc_low_text
[] = {
227 static const struct soc_enum drc_low
=
228 SOC_ENUM_SINGLE(WM9081_DRC_3
, 0, 5, drc_low_text
);
230 static const char *drc_atk_text
[] = {
245 static const struct soc_enum drc_atk
=
246 SOC_ENUM_SINGLE(WM9081_DRC_2
, 12, 12, drc_atk_text
);
248 static const char *drc_dcy_text
[] = {
260 static const struct soc_enum drc_dcy
=
261 SOC_ENUM_SINGLE(WM9081_DRC_2
, 8, 9, drc_dcy_text
);
263 static const char *drc_qr_dcy_text
[] = {
269 static const struct soc_enum drc_qr_dcy
=
270 SOC_ENUM_SINGLE(WM9081_DRC_2
, 4, 3, drc_qr_dcy_text
);
272 static const char *dac_deemph_text
[] = {
279 static const struct soc_enum dac_deemph
=
280 SOC_ENUM_SINGLE(WM9081_DAC_DIGITAL_2
, 1, 4, dac_deemph_text
);
282 static const char *speaker_mode_text
[] = {
287 static const struct soc_enum speaker_mode
=
288 SOC_ENUM_SINGLE(WM9081_ANALOGUE_SPEAKER_2
, 6, 2, speaker_mode_text
);
290 static int speaker_mode_get(struct snd_kcontrol
*kcontrol
,
291 struct snd_ctl_elem_value
*ucontrol
)
293 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
296 reg
= snd_soc_read(codec
, WM9081_ANALOGUE_SPEAKER_2
);
297 if (reg
& WM9081_SPK_MODE
)
298 ucontrol
->value
.integer
.value
[0] = 1;
300 ucontrol
->value
.integer
.value
[0] = 0;
306 * Stop any attempts to change speaker mode while the speaker is enabled.
308 * We also have some special anti-pop controls dependant on speaker
309 * mode which must be changed along with the mode.
311 static int speaker_mode_put(struct snd_kcontrol
*kcontrol
,
312 struct snd_ctl_elem_value
*ucontrol
)
314 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
315 unsigned int reg_pwr
= snd_soc_read(codec
, WM9081_POWER_MANAGEMENT
);
316 unsigned int reg2
= snd_soc_read(codec
, WM9081_ANALOGUE_SPEAKER_2
);
318 /* Are we changing anything? */
319 if (ucontrol
->value
.integer
.value
[0] ==
320 ((reg2
& WM9081_SPK_MODE
) != 0))
323 /* Don't try to change modes while enabled */
324 if (reg_pwr
& WM9081_SPK_ENA
)
327 if (ucontrol
->value
.integer
.value
[0]) {
329 reg2
&= ~(WM9081_SPK_INV_MUTE
| WM9081_OUT_SPK_CTRL
);
330 reg2
|= WM9081_SPK_MODE
;
333 reg2
|= WM9081_SPK_INV_MUTE
| WM9081_OUT_SPK_CTRL
;
334 reg2
&= ~WM9081_SPK_MODE
;
337 snd_soc_write(codec
, WM9081_ANALOGUE_SPEAKER_2
, reg2
);
342 static const struct snd_kcontrol_new wm9081_snd_controls
[] = {
343 SOC_SINGLE_TLV("IN1 Volume", WM9081_ANALOGUE_MIXER
, 1, 1, 1, in_tlv
),
344 SOC_SINGLE_TLV("IN2 Volume", WM9081_ANALOGUE_MIXER
, 3, 1, 1, in_tlv
),
346 SOC_SINGLE_TLV("Playback Volume", WM9081_DAC_DIGITAL_1
, 1, 96, 0, dac_tlv
),
348 SOC_SINGLE("LINEOUT Switch", WM9081_ANALOGUE_LINEOUT
, 7, 1, 1),
349 SOC_SINGLE("LINEOUT ZC Switch", WM9081_ANALOGUE_LINEOUT
, 6, 1, 0),
350 SOC_SINGLE_TLV("LINEOUT Volume", WM9081_ANALOGUE_LINEOUT
, 0, 63, 0, out_tlv
),
352 SOC_SINGLE("DRC Switch", WM9081_DRC_1
, 15, 1, 0),
353 SOC_ENUM("DRC High Slope", drc_high
),
354 SOC_ENUM("DRC Low Slope", drc_low
),
355 SOC_SINGLE_TLV("DRC Input Volume", WM9081_DRC_4
, 5, 60, 1, drc_in_tlv
),
356 SOC_SINGLE_TLV("DRC Output Volume", WM9081_DRC_4
, 0, 30, 1, drc_out_tlv
),
357 SOC_SINGLE_TLV("DRC Minimum Volume", WM9081_DRC_2
, 2, 3, 1, drc_min_tlv
),
358 SOC_SINGLE_TLV("DRC Maximum Volume", WM9081_DRC_2
, 0, 3, 0, drc_max_tlv
),
359 SOC_ENUM("DRC Attack", drc_atk
),
360 SOC_ENUM("DRC Decay", drc_dcy
),
361 SOC_SINGLE("DRC Quick Release Switch", WM9081_DRC_1
, 2, 1, 0),
362 SOC_SINGLE_TLV("DRC Quick Release Volume", WM9081_DRC_2
, 6, 3, 0, drc_qr_tlv
),
363 SOC_ENUM("DRC Quick Release Decay", drc_qr_dcy
),
364 SOC_SINGLE_TLV("DRC Startup Volume", WM9081_DRC_1
, 6, 18, 0, drc_startup_tlv
),
366 SOC_SINGLE("EQ Switch", WM9081_EQ_1
, 0, 1, 0),
368 SOC_SINGLE("Speaker DC Volume", WM9081_ANALOGUE_SPEAKER_1
, 3, 5, 0),
369 SOC_SINGLE("Speaker AC Volume", WM9081_ANALOGUE_SPEAKER_1
, 0, 5, 0),
370 SOC_SINGLE("Speaker Switch", WM9081_ANALOGUE_SPEAKER_PGA
, 7, 1, 1),
371 SOC_SINGLE("Speaker ZC Switch", WM9081_ANALOGUE_SPEAKER_PGA
, 6, 1, 0),
372 SOC_SINGLE_TLV("Speaker Volume", WM9081_ANALOGUE_SPEAKER_PGA
, 0, 63, 0,
374 SOC_ENUM("DAC Deemphasis", dac_deemph
),
375 SOC_ENUM_EXT("Speaker Mode", speaker_mode
, speaker_mode_get
, speaker_mode_put
),
378 static const struct snd_kcontrol_new wm9081_eq_controls
[] = {
379 SOC_SINGLE_TLV("EQ1 Volume", WM9081_EQ_1
, 11, 24, 0, eq_tlv
),
380 SOC_SINGLE_TLV("EQ2 Volume", WM9081_EQ_1
, 6, 24, 0, eq_tlv
),
381 SOC_SINGLE_TLV("EQ3 Volume", WM9081_EQ_1
, 1, 24, 0, eq_tlv
),
382 SOC_SINGLE_TLV("EQ4 Volume", WM9081_EQ_2
, 11, 24, 0, eq_tlv
),
383 SOC_SINGLE_TLV("EQ5 Volume", WM9081_EQ_2
, 6, 24, 0, eq_tlv
),
386 static const struct snd_kcontrol_new mixer
[] = {
387 SOC_DAPM_SINGLE("IN1 Switch", WM9081_ANALOGUE_MIXER
, 0, 1, 0),
388 SOC_DAPM_SINGLE("IN2 Switch", WM9081_ANALOGUE_MIXER
, 2, 1, 0),
389 SOC_DAPM_SINGLE("Playback Switch", WM9081_ANALOGUE_MIXER
, 4, 1, 0),
392 static int speaker_event(struct snd_soc_dapm_widget
*w
,
393 struct snd_kcontrol
*kcontrol
, int event
)
395 struct snd_soc_codec
*codec
= w
->codec
;
396 unsigned int reg
= snd_soc_read(codec
, WM9081_POWER_MANAGEMENT
);
399 case SND_SOC_DAPM_POST_PMU
:
400 reg
|= WM9081_SPK_ENA
;
403 case SND_SOC_DAPM_PRE_PMD
:
404 reg
&= ~WM9081_SPK_ENA
;
408 snd_soc_write(codec
, WM9081_POWER_MANAGEMENT
, reg
);
421 /* The size in bits of the FLL divide multiplied by 10
422 * to allow rounding later */
423 #define FIXED_FLL_SIZE ((1 << 16) * 10)
432 { 64000, 128000, 3, 8 },
433 { 128000, 256000, 2, 4 },
434 { 256000, 1000000, 1, 2 },
435 { 1000000, 13500000, 0, 1 },
438 static int fll_factors(struct _fll_div
*fll_div
, unsigned int Fref
,
442 unsigned int K
, Ndiv
, Nmod
, target
;
446 /* Fref must be <=13.5MHz */
448 while ((Fref
/ div
) > 13500000) {
452 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
457 fll_div
->fll_clk_ref_div
= div
/ 2;
459 pr_debug("Fref=%u Fout=%u\n", Fref
, Fout
);
461 /* Apply the division for our remaining calculations */
464 /* Fvco should be 90-100MHz; don't check the upper bound */
467 while (target
< 90000000) {
471 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
476 fll_div
->fll_outdiv
= div
;
478 pr_debug("Fvco=%dHz\n", target
);
480 /* Find an appropraite FLL_FRATIO and factor it out of the target */
481 for (i
= 0; i
< ARRAY_SIZE(fll_fratios
); i
++) {
482 if (fll_fratios
[i
].min
<= Fref
&& Fref
<= fll_fratios
[i
].max
) {
483 fll_div
->fll_fratio
= fll_fratios
[i
].fll_fratio
;
484 target
/= fll_fratios
[i
].ratio
;
488 if (i
== ARRAY_SIZE(fll_fratios
)) {
489 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref
);
493 /* Now, calculate N.K */
494 Ndiv
= target
/ Fref
;
497 Nmod
= target
% Fref
;
498 pr_debug("Nmod=%d\n", Nmod
);
500 /* Calculate fractional part - scale up so we can round. */
501 Kpart
= FIXED_FLL_SIZE
* (long long)Nmod
;
505 K
= Kpart
& 0xFFFFFFFF;
510 /* Move down to proper range now rounding is done */
513 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
514 fll_div
->n
, fll_div
->k
,
515 fll_div
->fll_fratio
, fll_div
->fll_outdiv
,
516 fll_div
->fll_clk_ref_div
);
521 static int wm9081_set_fll(struct snd_soc_codec
*codec
, int fll_id
,
522 unsigned int Fref
, unsigned int Fout
)
524 struct wm9081_priv
*wm9081
= snd_soc_codec_get_drvdata(codec
);
525 u16 reg1
, reg4
, reg5
;
526 struct _fll_div fll_div
;
531 if (Fref
== wm9081
->fll_fref
&& Fout
== wm9081
->fll_fout
)
534 /* Disable the FLL */
536 dev_dbg(codec
->dev
, "FLL disabled\n");
537 wm9081
->fll_fref
= 0;
538 wm9081
->fll_fout
= 0;
543 ret
= fll_factors(&fll_div
, Fref
, Fout
);
547 reg5
= snd_soc_read(codec
, WM9081_FLL_CONTROL_5
);
548 reg5
&= ~WM9081_FLL_CLK_SRC_MASK
;
551 case WM9081_SYSCLK_FLL_MCLK
:
556 dev_err(codec
->dev
, "Unknown FLL ID %d\n", fll_id
);
560 /* Disable CLK_SYS while we reconfigure */
561 clk_sys_reg
= snd_soc_read(codec
, WM9081_CLOCK_CONTROL_3
);
562 if (clk_sys_reg
& WM9081_CLK_SYS_ENA
)
563 snd_soc_write(codec
, WM9081_CLOCK_CONTROL_3
,
564 clk_sys_reg
& ~WM9081_CLK_SYS_ENA
);
566 /* Any FLL configuration change requires that the FLL be
568 reg1
= snd_soc_read(codec
, WM9081_FLL_CONTROL_1
);
569 reg1
&= ~WM9081_FLL_ENA
;
570 snd_soc_write(codec
, WM9081_FLL_CONTROL_1
, reg1
);
572 /* Apply the configuration */
574 reg1
|= WM9081_FLL_FRAC_MASK
;
576 reg1
&= ~WM9081_FLL_FRAC_MASK
;
577 snd_soc_write(codec
, WM9081_FLL_CONTROL_1
, reg1
);
579 snd_soc_write(codec
, WM9081_FLL_CONTROL_2
,
580 (fll_div
.fll_outdiv
<< WM9081_FLL_OUTDIV_SHIFT
) |
581 (fll_div
.fll_fratio
<< WM9081_FLL_FRATIO_SHIFT
));
582 snd_soc_write(codec
, WM9081_FLL_CONTROL_3
, fll_div
.k
);
584 reg4
= snd_soc_read(codec
, WM9081_FLL_CONTROL_4
);
585 reg4
&= ~WM9081_FLL_N_MASK
;
586 reg4
|= fll_div
.n
<< WM9081_FLL_N_SHIFT
;
587 snd_soc_write(codec
, WM9081_FLL_CONTROL_4
, reg4
);
589 reg5
&= ~WM9081_FLL_CLK_REF_DIV_MASK
;
590 reg5
|= fll_div
.fll_clk_ref_div
<< WM9081_FLL_CLK_REF_DIV_SHIFT
;
591 snd_soc_write(codec
, WM9081_FLL_CONTROL_5
, reg5
);
593 /* Set gain to the recommended value */
594 snd_soc_update_bits(codec
, WM9081_FLL_CONTROL_4
,
595 WM9081_FLL_GAIN_MASK
, 0);
598 snd_soc_write(codec
, WM9081_FLL_CONTROL_1
, reg1
| WM9081_FLL_ENA
);
600 /* Then bring CLK_SYS up again if it was disabled */
601 if (clk_sys_reg
& WM9081_CLK_SYS_ENA
)
602 snd_soc_write(codec
, WM9081_CLOCK_CONTROL_3
, clk_sys_reg
);
604 dev_dbg(codec
->dev
, "FLL enabled at %dHz->%dHz\n", Fref
, Fout
);
606 wm9081
->fll_fref
= Fref
;
607 wm9081
->fll_fout
= Fout
;
612 static int configure_clock(struct snd_soc_codec
*codec
)
614 struct wm9081_priv
*wm9081
= snd_soc_codec_get_drvdata(codec
);
615 int new_sysclk
, i
, target
;
621 switch (wm9081
->sysclk_source
) {
622 case WM9081_SYSCLK_MCLK
:
623 if (wm9081
->mclk_rate
> 12225000) {
625 wm9081
->sysclk_rate
= wm9081
->mclk_rate
/ 2;
627 wm9081
->sysclk_rate
= wm9081
->mclk_rate
;
629 wm9081_set_fll(codec
, WM9081_SYSCLK_FLL_MCLK
, 0, 0);
632 case WM9081_SYSCLK_FLL_MCLK
:
633 /* If we have a sample rate calculate a CLK_SYS that
634 * gives us a suitable DAC configuration, plus BCLK.
635 * Ideally we would check to see if we can clock
636 * directly from MCLK and only use the FLL if this is
637 * not the case, though care must be taken with free
640 if (wm9081
->master
&& wm9081
->bclk
) {
641 /* Make sure we can generate CLK_SYS and BCLK
642 * and that we've got 3MHz for optimal
644 for (i
= 0; i
< ARRAY_SIZE(clk_sys_rates
); i
++) {
645 target
= wm9081
->fs
* clk_sys_rates
[i
].ratio
;
647 if (target
>= wm9081
->bclk
&&
652 if (i
== ARRAY_SIZE(clk_sys_rates
))
655 } else if (wm9081
->fs
) {
656 for (i
= 0; i
< ARRAY_SIZE(clk_sys_rates
); i
++) {
657 new_sysclk
= clk_sys_rates
[i
].ratio
659 if (new_sysclk
> 3000000)
663 if (i
== ARRAY_SIZE(clk_sys_rates
))
667 new_sysclk
= 12288000;
670 ret
= wm9081_set_fll(codec
, WM9081_SYSCLK_FLL_MCLK
,
671 wm9081
->mclk_rate
, new_sysclk
);
673 wm9081
->sysclk_rate
= new_sysclk
;
675 /* Switch SYSCLK over to FLL */
678 wm9081
->sysclk_rate
= wm9081
->mclk_rate
;
686 reg
= snd_soc_read(codec
, WM9081_CLOCK_CONTROL_1
);
688 reg
|= WM9081_MCLKDIV2
;
690 reg
&= ~WM9081_MCLKDIV2
;
691 snd_soc_write(codec
, WM9081_CLOCK_CONTROL_1
, reg
);
693 reg
= snd_soc_read(codec
, WM9081_CLOCK_CONTROL_3
);
695 reg
|= WM9081_CLK_SRC_SEL
;
697 reg
&= ~WM9081_CLK_SRC_SEL
;
698 snd_soc_write(codec
, WM9081_CLOCK_CONTROL_3
, reg
);
700 dev_dbg(codec
->dev
, "CLK_SYS is %dHz\n", wm9081
->sysclk_rate
);
705 static int clk_sys_event(struct snd_soc_dapm_widget
*w
,
706 struct snd_kcontrol
*kcontrol
, int event
)
708 struct snd_soc_codec
*codec
= w
->codec
;
709 struct wm9081_priv
*wm9081
= snd_soc_codec_get_drvdata(codec
);
711 /* This should be done on init() for bypass paths */
712 switch (wm9081
->sysclk_source
) {
713 case WM9081_SYSCLK_MCLK
:
714 dev_dbg(codec
->dev
, "Using %dHz MCLK\n", wm9081
->mclk_rate
);
716 case WM9081_SYSCLK_FLL_MCLK
:
717 dev_dbg(codec
->dev
, "Using %dHz MCLK with FLL\n",
721 dev_err(codec
->dev
, "System clock not configured\n");
726 case SND_SOC_DAPM_PRE_PMU
:
727 configure_clock(codec
);
730 case SND_SOC_DAPM_POST_PMD
:
731 /* Disable the FLL if it's running */
732 wm9081_set_fll(codec
, 0, 0, 0);
739 static const struct snd_soc_dapm_widget wm9081_dapm_widgets
[] = {
740 SND_SOC_DAPM_INPUT("IN1"),
741 SND_SOC_DAPM_INPUT("IN2"),
743 SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM9081_POWER_MANAGEMENT
, 0, 0),
745 SND_SOC_DAPM_MIXER_NAMED_CTL("Mixer", SND_SOC_NOPM
, 0, 0,
746 mixer
, ARRAY_SIZE(mixer
)),
748 SND_SOC_DAPM_PGA("LINEOUT PGA", WM9081_POWER_MANAGEMENT
, 4, 0, NULL
, 0),
750 SND_SOC_DAPM_PGA_E("Speaker PGA", WM9081_POWER_MANAGEMENT
, 2, 0, NULL
, 0,
752 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
754 SND_SOC_DAPM_OUTPUT("LINEOUT"),
755 SND_SOC_DAPM_OUTPUT("SPKN"),
756 SND_SOC_DAPM_OUTPUT("SPKP"),
758 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM9081_CLOCK_CONTROL_3
, 0, 0, clk_sys_event
,
759 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
760 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM9081_CLOCK_CONTROL_3
, 1, 0, NULL
, 0),
761 SND_SOC_DAPM_SUPPLY("TOCLK", WM9081_CLOCK_CONTROL_3
, 2, 0, NULL
, 0),
765 static const struct snd_soc_dapm_route audio_paths
[] = {
766 { "DAC", NULL
, "CLK_SYS" },
767 { "DAC", NULL
, "CLK_DSP" },
769 { "Mixer", "IN1 Switch", "IN1" },
770 { "Mixer", "IN2 Switch", "IN2" },
771 { "Mixer", "Playback Switch", "DAC" },
773 { "LINEOUT PGA", NULL
, "Mixer" },
774 { "LINEOUT PGA", NULL
, "TOCLK" },
775 { "LINEOUT PGA", NULL
, "CLK_SYS" },
777 { "LINEOUT", NULL
, "LINEOUT PGA" },
779 { "Speaker PGA", NULL
, "Mixer" },
780 { "Speaker PGA", NULL
, "TOCLK" },
781 { "Speaker PGA", NULL
, "CLK_SYS" },
783 { "SPKN", NULL
, "Speaker PGA" },
784 { "SPKP", NULL
, "Speaker PGA" },
787 static int wm9081_set_bias_level(struct snd_soc_codec
*codec
,
788 enum snd_soc_bias_level level
)
793 case SND_SOC_BIAS_ON
:
796 case SND_SOC_BIAS_PREPARE
:
798 reg
= snd_soc_read(codec
, WM9081_VMID_CONTROL
);
799 reg
&= ~WM9081_VMID_SEL_MASK
;
801 snd_soc_write(codec
, WM9081_VMID_CONTROL
, reg
);
803 /* Normal bias current */
804 reg
= snd_soc_read(codec
, WM9081_BIAS_CONTROL_1
);
805 reg
&= ~WM9081_STBY_BIAS_ENA
;
806 snd_soc_write(codec
, WM9081_BIAS_CONTROL_1
, reg
);
809 case SND_SOC_BIAS_STANDBY
:
810 /* Initial cold start */
811 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
812 /* Disable LINEOUT discharge */
813 reg
= snd_soc_read(codec
, WM9081_ANTI_POP_CONTROL
);
814 reg
&= ~WM9081_LINEOUT_DISCH
;
815 snd_soc_write(codec
, WM9081_ANTI_POP_CONTROL
, reg
);
817 /* Select startup bias source */
818 reg
= snd_soc_read(codec
, WM9081_BIAS_CONTROL_1
);
819 reg
|= WM9081_BIAS_SRC
| WM9081_BIAS_ENA
;
820 snd_soc_write(codec
, WM9081_BIAS_CONTROL_1
, reg
);
822 /* VMID 2*4k; Soft VMID ramp enable */
823 reg
= snd_soc_read(codec
, WM9081_VMID_CONTROL
);
824 reg
|= WM9081_VMID_RAMP
| 0x6;
825 snd_soc_write(codec
, WM9081_VMID_CONTROL
, reg
);
829 /* Normal bias enable & soft start off */
830 reg
|= WM9081_BIAS_ENA
;
831 reg
&= ~WM9081_VMID_RAMP
;
832 snd_soc_write(codec
, WM9081_VMID_CONTROL
, reg
);
834 /* Standard bias source */
835 reg
= snd_soc_read(codec
, WM9081_BIAS_CONTROL_1
);
836 reg
&= ~WM9081_BIAS_SRC
;
837 snd_soc_write(codec
, WM9081_BIAS_CONTROL_1
, reg
);
841 reg
= snd_soc_read(codec
, WM9081_BIAS_CONTROL_1
);
842 reg
&= ~WM9081_VMID_SEL_MASK
;
844 snd_soc_write(codec
, WM9081_VMID_CONTROL
, reg
);
846 /* Standby bias current on */
847 reg
= snd_soc_read(codec
, WM9081_BIAS_CONTROL_1
);
848 reg
|= WM9081_STBY_BIAS_ENA
;
849 snd_soc_write(codec
, WM9081_BIAS_CONTROL_1
, reg
);
852 case SND_SOC_BIAS_OFF
:
853 /* Startup bias source */
854 reg
= snd_soc_read(codec
, WM9081_BIAS_CONTROL_1
);
855 reg
|= WM9081_BIAS_SRC
;
856 snd_soc_write(codec
, WM9081_BIAS_CONTROL_1
, reg
);
858 /* Disable VMID and biases with soft ramping */
859 reg
= snd_soc_read(codec
, WM9081_VMID_CONTROL
);
860 reg
&= ~(WM9081_VMID_SEL_MASK
| WM9081_BIAS_ENA
);
861 reg
|= WM9081_VMID_RAMP
;
862 snd_soc_write(codec
, WM9081_VMID_CONTROL
, reg
);
864 /* Actively discharge LINEOUT */
865 reg
= snd_soc_read(codec
, WM9081_ANTI_POP_CONTROL
);
866 reg
|= WM9081_LINEOUT_DISCH
;
867 snd_soc_write(codec
, WM9081_ANTI_POP_CONTROL
, reg
);
871 codec
->dapm
.bias_level
= level
;
876 static int wm9081_set_dai_fmt(struct snd_soc_dai
*dai
,
879 struct snd_soc_codec
*codec
= dai
->codec
;
880 struct wm9081_priv
*wm9081
= snd_soc_codec_get_drvdata(codec
);
881 unsigned int aif2
= snd_soc_read(codec
, WM9081_AUDIO_INTERFACE_2
);
883 aif2
&= ~(WM9081_AIF_BCLK_INV
| WM9081_AIF_LRCLK_INV
|
884 WM9081_BCLK_DIR
| WM9081_LRCLK_DIR
| WM9081_AIF_FMT_MASK
);
886 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
887 case SND_SOC_DAIFMT_CBS_CFS
:
890 case SND_SOC_DAIFMT_CBS_CFM
:
891 aif2
|= WM9081_LRCLK_DIR
;
894 case SND_SOC_DAIFMT_CBM_CFS
:
895 aif2
|= WM9081_BCLK_DIR
;
898 case SND_SOC_DAIFMT_CBM_CFM
:
899 aif2
|= WM9081_LRCLK_DIR
| WM9081_BCLK_DIR
;
906 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
907 case SND_SOC_DAIFMT_DSP_B
:
908 aif2
|= WM9081_AIF_LRCLK_INV
;
909 case SND_SOC_DAIFMT_DSP_A
:
912 case SND_SOC_DAIFMT_I2S
:
915 case SND_SOC_DAIFMT_RIGHT_J
:
917 case SND_SOC_DAIFMT_LEFT_J
:
924 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
925 case SND_SOC_DAIFMT_DSP_A
:
926 case SND_SOC_DAIFMT_DSP_B
:
927 /* frame inversion not valid for DSP modes */
928 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
929 case SND_SOC_DAIFMT_NB_NF
:
931 case SND_SOC_DAIFMT_IB_NF
:
932 aif2
|= WM9081_AIF_BCLK_INV
;
939 case SND_SOC_DAIFMT_I2S
:
940 case SND_SOC_DAIFMT_RIGHT_J
:
941 case SND_SOC_DAIFMT_LEFT_J
:
942 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
943 case SND_SOC_DAIFMT_NB_NF
:
945 case SND_SOC_DAIFMT_IB_IF
:
946 aif2
|= WM9081_AIF_BCLK_INV
| WM9081_AIF_LRCLK_INV
;
948 case SND_SOC_DAIFMT_IB_NF
:
949 aif2
|= WM9081_AIF_BCLK_INV
;
951 case SND_SOC_DAIFMT_NB_IF
:
952 aif2
|= WM9081_AIF_LRCLK_INV
;
962 snd_soc_write(codec
, WM9081_AUDIO_INTERFACE_2
, aif2
);
967 static int wm9081_hw_params(struct snd_pcm_substream
*substream
,
968 struct snd_pcm_hw_params
*params
,
969 struct snd_soc_dai
*dai
)
971 struct snd_soc_codec
*codec
= dai
->codec
;
972 struct wm9081_priv
*wm9081
= snd_soc_codec_get_drvdata(codec
);
973 int ret
, i
, best
, best_val
, cur_val
;
974 unsigned int clk_ctrl2
, aif1
, aif2
, aif3
, aif4
;
976 clk_ctrl2
= snd_soc_read(codec
, WM9081_CLOCK_CONTROL_2
);
977 clk_ctrl2
&= ~(WM9081_CLK_SYS_RATE_MASK
| WM9081_SAMPLE_RATE_MASK
);
979 aif1
= snd_soc_read(codec
, WM9081_AUDIO_INTERFACE_1
);
981 aif2
= snd_soc_read(codec
, WM9081_AUDIO_INTERFACE_2
);
982 aif2
&= ~WM9081_AIF_WL_MASK
;
984 aif3
= snd_soc_read(codec
, WM9081_AUDIO_INTERFACE_3
);
985 aif3
&= ~WM9081_BCLK_DIV_MASK
;
987 aif4
= snd_soc_read(codec
, WM9081_AUDIO_INTERFACE_4
);
988 aif4
&= ~WM9081_LRCLK_RATE_MASK
;
990 wm9081
->fs
= params_rate(params
);
992 if (wm9081
->tdm_width
) {
993 /* If TDM is set up then that fixes our BCLK. */
994 int slots
= ((aif1
& WM9081_AIFDAC_TDM_MODE_MASK
) >>
995 WM9081_AIFDAC_TDM_MODE_SHIFT
) + 1;
997 wm9081
->bclk
= wm9081
->fs
* wm9081
->tdm_width
* slots
;
999 /* Otherwise work out a BCLK from the sample size */
1000 wm9081
->bclk
= 2 * wm9081
->fs
;
1002 switch (params_format(params
)) {
1003 case SNDRV_PCM_FORMAT_S16_LE
:
1006 case SNDRV_PCM_FORMAT_S20_3LE
:
1010 case SNDRV_PCM_FORMAT_S24_LE
:
1014 case SNDRV_PCM_FORMAT_S32_LE
:
1023 dev_dbg(codec
->dev
, "Target BCLK is %dHz\n", wm9081
->bclk
);
1025 ret
= configure_clock(codec
);
1029 /* Select nearest CLK_SYS_RATE */
1031 best_val
= abs((wm9081
->sysclk_rate
/ clk_sys_rates
[0].ratio
)
1033 for (i
= 1; i
< ARRAY_SIZE(clk_sys_rates
); i
++) {
1034 cur_val
= abs((wm9081
->sysclk_rate
/
1035 clk_sys_rates
[i
].ratio
) - wm9081
->fs
);
1036 if (cur_val
< best_val
) {
1041 dev_dbg(codec
->dev
, "Selected CLK_SYS_RATIO of %d\n",
1042 clk_sys_rates
[best
].ratio
);
1043 clk_ctrl2
|= (clk_sys_rates
[best
].clk_sys_rate
1044 << WM9081_CLK_SYS_RATE_SHIFT
);
1048 best_val
= abs(wm9081
->fs
- sample_rates
[0].rate
);
1049 for (i
= 1; i
< ARRAY_SIZE(sample_rates
); i
++) {
1051 cur_val
= abs(wm9081
->fs
- sample_rates
[i
].rate
);
1052 if (cur_val
< best_val
) {
1057 dev_dbg(codec
->dev
, "Selected SAMPLE_RATE of %dHz\n",
1058 sample_rates
[best
].rate
);
1059 clk_ctrl2
|= (sample_rates
[best
].sample_rate
1060 << WM9081_SAMPLE_RATE_SHIFT
);
1065 for (i
= 0; i
< ARRAY_SIZE(bclk_divs
); i
++) {
1066 cur_val
= ((wm9081
->sysclk_rate
* 10) / bclk_divs
[i
].div
)
1068 if (cur_val
< 0) /* Table is sorted */
1070 if (cur_val
< best_val
) {
1075 wm9081
->bclk
= (wm9081
->sysclk_rate
* 10) / bclk_divs
[best
].div
;
1076 dev_dbg(codec
->dev
, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1077 bclk_divs
[best
].div
, wm9081
->bclk
);
1078 aif3
|= bclk_divs
[best
].bclk_div
;
1080 /* LRCLK is a simple fraction of BCLK */
1081 dev_dbg(codec
->dev
, "LRCLK_RATE is %d\n", wm9081
->bclk
/ wm9081
->fs
);
1082 aif4
|= wm9081
->bclk
/ wm9081
->fs
;
1084 /* Apply a ReTune Mobile configuration if it's in use */
1085 if (wm9081
->retune
) {
1086 struct wm9081_retune_mobile_config
*retune
= wm9081
->retune
;
1087 struct wm9081_retune_mobile_setting
*s
;
1091 best_val
= abs(retune
->configs
[0].rate
- wm9081
->fs
);
1092 for (i
= 0; i
< retune
->num_configs
; i
++) {
1093 cur_val
= abs(retune
->configs
[i
].rate
- wm9081
->fs
);
1094 if (cur_val
< best_val
) {
1099 s
= &retune
->configs
[best
];
1101 dev_dbg(codec
->dev
, "ReTune Mobile %s tuned for %dHz\n",
1104 /* If the EQ is enabled then disable it while we write out */
1105 eq1
= snd_soc_read(codec
, WM9081_EQ_1
) & WM9081_EQ_ENA
;
1106 if (eq1
& WM9081_EQ_ENA
)
1107 snd_soc_write(codec
, WM9081_EQ_1
, 0);
1109 /* Write out the other values */
1110 for (i
= 1; i
< ARRAY_SIZE(s
->config
); i
++)
1111 snd_soc_write(codec
, WM9081_EQ_1
+ i
, s
->config
[i
]);
1113 eq1
|= (s
->config
[0] & ~WM9081_EQ_ENA
);
1114 snd_soc_write(codec
, WM9081_EQ_1
, eq1
);
1117 snd_soc_write(codec
, WM9081_CLOCK_CONTROL_2
, clk_ctrl2
);
1118 snd_soc_write(codec
, WM9081_AUDIO_INTERFACE_2
, aif2
);
1119 snd_soc_write(codec
, WM9081_AUDIO_INTERFACE_3
, aif3
);
1120 snd_soc_write(codec
, WM9081_AUDIO_INTERFACE_4
, aif4
);
1125 static int wm9081_digital_mute(struct snd_soc_dai
*codec_dai
, int mute
)
1127 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1130 reg
= snd_soc_read(codec
, WM9081_DAC_DIGITAL_2
);
1133 reg
|= WM9081_DAC_MUTE
;
1135 reg
&= ~WM9081_DAC_MUTE
;
1137 snd_soc_write(codec
, WM9081_DAC_DIGITAL_2
, reg
);
1142 static int wm9081_set_sysclk(struct snd_soc_dai
*codec_dai
,
1143 int clk_id
, unsigned int freq
, int dir
)
1145 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1146 struct wm9081_priv
*wm9081
= snd_soc_codec_get_drvdata(codec
);
1149 case WM9081_SYSCLK_MCLK
:
1150 case WM9081_SYSCLK_FLL_MCLK
:
1151 wm9081
->sysclk_source
= clk_id
;
1152 wm9081
->mclk_rate
= freq
;
1162 static int wm9081_set_tdm_slot(struct snd_soc_dai
*dai
,
1163 unsigned int tx_mask
, unsigned int rx_mask
, int slots
, int slot_width
)
1165 struct snd_soc_codec
*codec
= dai
->codec
;
1166 struct wm9081_priv
*wm9081
= snd_soc_codec_get_drvdata(codec
);
1167 unsigned int aif1
= snd_soc_read(codec
, WM9081_AUDIO_INTERFACE_1
);
1169 aif1
&= ~(WM9081_AIFDAC_TDM_SLOT_MASK
| WM9081_AIFDAC_TDM_MODE_MASK
);
1171 if (slots
< 0 || slots
> 4)
1174 wm9081
->tdm_width
= slot_width
;
1179 aif1
|= (slots
- 1) << WM9081_AIFDAC_TDM_MODE_SHIFT
;
1197 snd_soc_write(codec
, WM9081_AUDIO_INTERFACE_1
, aif1
);
1202 #define WM9081_RATES SNDRV_PCM_RATE_8000_96000
1204 #define WM9081_FORMATS \
1205 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1206 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1208 static struct snd_soc_dai_ops wm9081_dai_ops
= {
1209 .hw_params
= wm9081_hw_params
,
1210 .set_sysclk
= wm9081_set_sysclk
,
1211 .set_fmt
= wm9081_set_dai_fmt
,
1212 .digital_mute
= wm9081_digital_mute
,
1213 .set_tdm_slot
= wm9081_set_tdm_slot
,
1216 /* We report two channels because the CODEC processes a stereo signal, even
1217 * though it is only capable of handling a mono output.
1219 static struct snd_soc_dai_driver wm9081_dai
= {
1220 .name
= "wm9081-hifi",
1222 .stream_name
= "HiFi Playback",
1225 .rates
= WM9081_RATES
,
1226 .formats
= WM9081_FORMATS
,
1228 .ops
= &wm9081_dai_ops
,
1231 static int wm9081_probe(struct snd_soc_codec
*codec
)
1233 struct wm9081_priv
*wm9081
= snd_soc_codec_get_drvdata(codec
);
1234 struct snd_soc_dapm_context
*dapm
= &codec
->dapm
;
1238 codec
->control_data
= wm9081
->control_data
;
1239 ret
= snd_soc_codec_set_cache_io(codec
, 8, 16, wm9081
->control_type
);
1241 dev_err(codec
->dev
, "Failed to set cache I/O: %d\n", ret
);
1245 reg
= snd_soc_read(codec
, WM9081_SOFTWARE_RESET
);
1246 if (reg
!= 0x9081) {
1247 dev_err(codec
->dev
, "Device is not a WM9081: ID=0x%x\n", reg
);
1252 ret
= wm9081_reset(codec
);
1254 dev_err(codec
->dev
, "Failed to issue reset\n");
1258 wm9081_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1260 /* Enable zero cross by default */
1261 reg
= snd_soc_read(codec
, WM9081_ANALOGUE_LINEOUT
);
1262 snd_soc_write(codec
, WM9081_ANALOGUE_LINEOUT
, reg
| WM9081_LINEOUTZC
);
1263 reg
= snd_soc_read(codec
, WM9081_ANALOGUE_SPEAKER_PGA
);
1264 snd_soc_write(codec
, WM9081_ANALOGUE_SPEAKER_PGA
,
1265 reg
| WM9081_SPKPGAZC
);
1267 snd_soc_add_controls(codec
, wm9081_snd_controls
,
1268 ARRAY_SIZE(wm9081_snd_controls
));
1269 if (!wm9081
->retune
) {
1271 "No ReTune Mobile data, using normal EQ\n");
1272 snd_soc_add_controls(codec
, wm9081_eq_controls
,
1273 ARRAY_SIZE(wm9081_eq_controls
));
1276 snd_soc_dapm_new_controls(dapm
, wm9081_dapm_widgets
,
1277 ARRAY_SIZE(wm9081_dapm_widgets
));
1278 snd_soc_dapm_add_routes(dapm
, audio_paths
, ARRAY_SIZE(audio_paths
));
1283 static int wm9081_remove(struct snd_soc_codec
*codec
)
1285 wm9081_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1290 static int wm9081_suspend(struct snd_soc_codec
*codec
, pm_message_t state
)
1292 wm9081_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1297 static int wm9081_resume(struct snd_soc_codec
*codec
)
1299 u16
*reg_cache
= codec
->reg_cache
;
1302 for (i
= 0; i
< codec
->driver
->reg_cache_size
; i
++) {
1303 if (i
== WM9081_SOFTWARE_RESET
)
1306 snd_soc_write(codec
, i
, reg_cache
[i
]);
1309 wm9081_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1314 #define wm9081_suspend NULL
1315 #define wm9081_resume NULL
1318 static struct snd_soc_codec_driver soc_codec_dev_wm9081
= {
1319 .probe
= wm9081_probe
,
1320 .remove
= wm9081_remove
,
1321 .suspend
= wm9081_suspend
,
1322 .resume
= wm9081_resume
,
1323 .set_bias_level
= wm9081_set_bias_level
,
1324 .reg_cache_size
= ARRAY_SIZE(wm9081_reg_defaults
),
1325 .reg_word_size
= sizeof(u16
),
1326 .reg_cache_default
= wm9081_reg_defaults
,
1327 .volatile_register
= wm9081_volatile_register
,
1330 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1331 static __devinit
int wm9081_i2c_probe(struct i2c_client
*i2c
,
1332 const struct i2c_device_id
*id
)
1334 struct wm9081_priv
*wm9081
;
1337 wm9081
= kzalloc(sizeof(struct wm9081_priv
), GFP_KERNEL
);
1341 i2c_set_clientdata(i2c
, wm9081
);
1342 wm9081
->control_type
= SND_SOC_I2C
;
1343 wm9081
->control_data
= i2c
;
1345 if (dev_get_platdata(&i2c
->dev
))
1346 memcpy(&wm9081
->retune
, dev_get_platdata(&i2c
->dev
),
1347 sizeof(wm9081
->retune
));
1349 ret
= snd_soc_register_codec(&i2c
->dev
,
1350 &soc_codec_dev_wm9081
, &wm9081_dai
, 1);
1356 static __devexit
int wm9081_i2c_remove(struct i2c_client
*client
)
1358 snd_soc_unregister_codec(&client
->dev
);
1359 kfree(i2c_get_clientdata(client
));
1363 static const struct i2c_device_id wm9081_i2c_id
[] = {
1367 MODULE_DEVICE_TABLE(i2c
, wm9081_i2c_id
);
1369 static struct i2c_driver wm9081_i2c_driver
= {
1371 .name
= "wm9081-codec",
1372 .owner
= THIS_MODULE
,
1374 .probe
= wm9081_i2c_probe
,
1375 .remove
= __devexit_p(wm9081_i2c_remove
),
1376 .id_table
= wm9081_i2c_id
,
1380 static int __init
wm9081_modinit(void)
1383 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1384 ret
= i2c_add_driver(&wm9081_i2c_driver
);
1386 printk(KERN_ERR
"Failed to register WM9081 I2C driver: %d\n",
1392 module_init(wm9081_modinit
);
1394 static void __exit
wm9081_exit(void)
1396 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1397 i2c_del_driver(&wm9081_i2c_driver
);
1400 module_exit(wm9081_exit
);
1403 MODULE_DESCRIPTION("ASoC WM9081 driver");
1404 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1405 MODULE_LICENSE("GPL");