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Merge branch 'for-3.2' into for-3.3
[deliverable/linux.git] / sound / soc / codecs / wm9081.c
1 /*
2 * wm9081.c -- WM9081 ALSA SoC Audio driver
3 *
4 * Author: Mark Brown
5 *
6 * Copyright 2009 Wolfson Microelectronics plc
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/pm.h>
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 #include <linux/regmap.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/soc.h>
28 #include <sound/initval.h>
29 #include <sound/tlv.h>
30
31 #include <sound/wm9081.h>
32 #include "wm9081.h"
33
34 static struct reg_default wm9081_reg[] = {
35 { 0, 0x9081 }, /* R0 - Software Reset */
36 { 2, 0x00B9 }, /* R2 - Analogue Lineout */
37 { 3, 0x00B9 }, /* R3 - Analogue Speaker PGA */
38 { 4, 0x0001 }, /* R4 - VMID Control */
39 { 5, 0x0068 }, /* R5 - Bias Control 1 */
40 { 7, 0x0000 }, /* R7 - Analogue Mixer */
41 { 8, 0x0000 }, /* R8 - Anti Pop Control */
42 { 9, 0x01DB }, /* R9 - Analogue Speaker 1 */
43 { 10, 0x0018 }, /* R10 - Analogue Speaker 2 */
44 { 11, 0x0180 }, /* R11 - Power Management */
45 { 12, 0x0000 }, /* R12 - Clock Control 1 */
46 { 13, 0x0038 }, /* R13 - Clock Control 2 */
47 { 14, 0x4000 }, /* R14 - Clock Control 3 */
48 { 16, 0x0000 }, /* R16 - FLL Control 1 */
49 { 17, 0x0200 }, /* R17 - FLL Control 2 */
50 { 18, 0x0000 }, /* R18 - FLL Control 3 */
51 { 19, 0x0204 }, /* R19 - FLL Control 4 */
52 { 20, 0x0000 }, /* R20 - FLL Control 5 */
53 { 22, 0x0000 }, /* R22 - Audio Interface 1 */
54 { 23, 0x0002 }, /* R23 - Audio Interface 2 */
55 { 24, 0x0008 }, /* R24 - Audio Interface 3 */
56 { 25, 0x0022 }, /* R25 - Audio Interface 4 */
57 { 27, 0x0006 }, /* R27 - Interrupt Status Mask */
58 { 28, 0x0000 }, /* R28 - Interrupt Polarity */
59 { 29, 0x0000 }, /* R29 - Interrupt Control */
60 { 30, 0x00C0 }, /* R30 - DAC Digital 1 */
61 { 31, 0x0008 }, /* R31 - DAC Digital 2 */
62 { 32, 0x09AF }, /* R32 - DRC 1 */
63 { 33, 0x4201 }, /* R33 - DRC 2 */
64 { 34, 0x0000 }, /* R34 - DRC 3 */
65 { 35, 0x0000 }, /* R35 - DRC 4 */
66 { 38, 0x0000 }, /* R38 - Write Sequencer 1 */
67 { 39, 0x0000 }, /* R39 - Write Sequencer 2 */
68 { 40, 0x0002 }, /* R40 - MW Slave 1 */
69 { 42, 0x0000 }, /* R42 - EQ 1 */
70 { 43, 0x0000 }, /* R43 - EQ 2 */
71 { 44, 0x0FCA }, /* R44 - EQ 3 */
72 { 45, 0x0400 }, /* R45 - EQ 4 */
73 { 46, 0x00B8 }, /* R46 - EQ 5 */
74 { 47, 0x1EB5 }, /* R47 - EQ 6 */
75 { 48, 0xF145 }, /* R48 - EQ 7 */
76 { 49, 0x0B75 }, /* R49 - EQ 8 */
77 { 50, 0x01C5 }, /* R50 - EQ 9 */
78 { 51, 0x169E }, /* R51 - EQ 10 */
79 { 52, 0xF829 }, /* R52 - EQ 11 */
80 { 53, 0x07AD }, /* R53 - EQ 12 */
81 { 54, 0x1103 }, /* R54 - EQ 13 */
82 { 55, 0x1C58 }, /* R55 - EQ 14 */
83 { 56, 0xF373 }, /* R56 - EQ 15 */
84 { 57, 0x0A54 }, /* R57 - EQ 16 */
85 { 58, 0x0558 }, /* R58 - EQ 17 */
86 { 59, 0x0564 }, /* R59 - EQ 18 */
87 { 60, 0x0559 }, /* R60 - EQ 19 */
88 { 61, 0x4000 }, /* R61 - EQ 20 */
89 };
90
91 static struct {
92 int ratio;
93 int clk_sys_rate;
94 } clk_sys_rates[] = {
95 { 64, 0 },
96 { 128, 1 },
97 { 192, 2 },
98 { 256, 3 },
99 { 384, 4 },
100 { 512, 5 },
101 { 768, 6 },
102 { 1024, 7 },
103 { 1408, 8 },
104 { 1536, 9 },
105 };
106
107 static struct {
108 int rate;
109 int sample_rate;
110 } sample_rates[] = {
111 { 8000, 0 },
112 { 11025, 1 },
113 { 12000, 2 },
114 { 16000, 3 },
115 { 22050, 4 },
116 { 24000, 5 },
117 { 32000, 6 },
118 { 44100, 7 },
119 { 48000, 8 },
120 { 88200, 9 },
121 { 96000, 10 },
122 };
123
124 static struct {
125 int div; /* *10 due to .5s */
126 int bclk_div;
127 } bclk_divs[] = {
128 { 10, 0 },
129 { 15, 1 },
130 { 20, 2 },
131 { 30, 3 },
132 { 40, 4 },
133 { 50, 5 },
134 { 55, 6 },
135 { 60, 7 },
136 { 80, 8 },
137 { 100, 9 },
138 { 110, 10 },
139 { 120, 11 },
140 { 160, 12 },
141 { 200, 13 },
142 { 220, 14 },
143 { 240, 15 },
144 { 250, 16 },
145 { 300, 17 },
146 { 320, 18 },
147 { 440, 19 },
148 { 480, 20 },
149 };
150
151 struct wm9081_priv {
152 struct regmap *regmap;
153 int sysclk_source;
154 int mclk_rate;
155 int sysclk_rate;
156 int fs;
157 int bclk;
158 int master;
159 int fll_fref;
160 int fll_fout;
161 int tdm_width;
162 struct wm9081_pdata pdata;
163 };
164
165 static bool wm9081_volatile_register(struct device *dev, unsigned int reg)
166 {
167 switch (reg) {
168 case WM9081_SOFTWARE_RESET:
169 case WM9081_INTERRUPT_STATUS:
170 return true;
171 default:
172 return false;
173 }
174 }
175
176 static bool wm9081_readable_register(struct device *dev, unsigned int reg)
177 {
178 switch (reg) {
179 case WM9081_SOFTWARE_RESET:
180 case WM9081_ANALOGUE_LINEOUT:
181 case WM9081_ANALOGUE_SPEAKER_PGA:
182 case WM9081_VMID_CONTROL:
183 case WM9081_BIAS_CONTROL_1:
184 case WM9081_ANALOGUE_MIXER:
185 case WM9081_ANTI_POP_CONTROL:
186 case WM9081_ANALOGUE_SPEAKER_1:
187 case WM9081_ANALOGUE_SPEAKER_2:
188 case WM9081_POWER_MANAGEMENT:
189 case WM9081_CLOCK_CONTROL_1:
190 case WM9081_CLOCK_CONTROL_2:
191 case WM9081_CLOCK_CONTROL_3:
192 case WM9081_FLL_CONTROL_1:
193 case WM9081_FLL_CONTROL_2:
194 case WM9081_FLL_CONTROL_3:
195 case WM9081_FLL_CONTROL_4:
196 case WM9081_FLL_CONTROL_5:
197 case WM9081_AUDIO_INTERFACE_1:
198 case WM9081_AUDIO_INTERFACE_2:
199 case WM9081_AUDIO_INTERFACE_3:
200 case WM9081_AUDIO_INTERFACE_4:
201 case WM9081_INTERRUPT_STATUS:
202 case WM9081_INTERRUPT_STATUS_MASK:
203 case WM9081_INTERRUPT_POLARITY:
204 case WM9081_INTERRUPT_CONTROL:
205 case WM9081_DAC_DIGITAL_1:
206 case WM9081_DAC_DIGITAL_2:
207 case WM9081_DRC_1:
208 case WM9081_DRC_2:
209 case WM9081_DRC_3:
210 case WM9081_DRC_4:
211 case WM9081_WRITE_SEQUENCER_1:
212 case WM9081_WRITE_SEQUENCER_2:
213 case WM9081_MW_SLAVE_1:
214 case WM9081_EQ_1:
215 case WM9081_EQ_2:
216 case WM9081_EQ_3:
217 case WM9081_EQ_4:
218 case WM9081_EQ_5:
219 case WM9081_EQ_6:
220 case WM9081_EQ_7:
221 case WM9081_EQ_8:
222 case WM9081_EQ_9:
223 case WM9081_EQ_10:
224 case WM9081_EQ_11:
225 case WM9081_EQ_12:
226 case WM9081_EQ_13:
227 case WM9081_EQ_14:
228 case WM9081_EQ_15:
229 case WM9081_EQ_16:
230 case WM9081_EQ_17:
231 case WM9081_EQ_18:
232 case WM9081_EQ_19:
233 case WM9081_EQ_20:
234 return true;
235 default:
236 return false;
237 }
238 }
239
240 static int wm9081_reset(struct regmap *map)
241 {
242 return regmap_write(map, WM9081_SOFTWARE_RESET, 0x9081);
243 }
244
245 static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0);
246 static const DECLARE_TLV_DB_SCALE(drc_out_tlv, -2250, 75, 0);
247 static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
248 static unsigned int drc_max_tlv[] = {
249 TLV_DB_RANGE_HEAD(4),
250 0, 0, TLV_DB_SCALE_ITEM(1200, 0, 0),
251 1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0),
252 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
253 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
254 };
255 static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
256 static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -300, 50, 0);
257
258 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
259
260 static const DECLARE_TLV_DB_SCALE(in_tlv, -600, 600, 0);
261 static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
262 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
263
264 static const char *drc_high_text[] = {
265 "1",
266 "1/2",
267 "1/4",
268 "1/8",
269 "1/16",
270 "0",
271 };
272
273 static const struct soc_enum drc_high =
274 SOC_ENUM_SINGLE(WM9081_DRC_3, 3, 6, drc_high_text);
275
276 static const char *drc_low_text[] = {
277 "1",
278 "1/2",
279 "1/4",
280 "1/8",
281 "0",
282 };
283
284 static const struct soc_enum drc_low =
285 SOC_ENUM_SINGLE(WM9081_DRC_3, 0, 5, drc_low_text);
286
287 static const char *drc_atk_text[] = {
288 "181us",
289 "181us",
290 "363us",
291 "726us",
292 "1.45ms",
293 "2.9ms",
294 "5.8ms",
295 "11.6ms",
296 "23.2ms",
297 "46.4ms",
298 "92.8ms",
299 "185.6ms",
300 };
301
302 static const struct soc_enum drc_atk =
303 SOC_ENUM_SINGLE(WM9081_DRC_2, 12, 12, drc_atk_text);
304
305 static const char *drc_dcy_text[] = {
306 "186ms",
307 "372ms",
308 "743ms",
309 "1.49s",
310 "2.97s",
311 "5.94s",
312 "11.89s",
313 "23.78s",
314 "47.56s",
315 };
316
317 static const struct soc_enum drc_dcy =
318 SOC_ENUM_SINGLE(WM9081_DRC_2, 8, 9, drc_dcy_text);
319
320 static const char *drc_qr_dcy_text[] = {
321 "0.725ms",
322 "1.45ms",
323 "5.8ms",
324 };
325
326 static const struct soc_enum drc_qr_dcy =
327 SOC_ENUM_SINGLE(WM9081_DRC_2, 4, 3, drc_qr_dcy_text);
328
329 static const char *dac_deemph_text[] = {
330 "None",
331 "32kHz",
332 "44.1kHz",
333 "48kHz",
334 };
335
336 static const struct soc_enum dac_deemph =
337 SOC_ENUM_SINGLE(WM9081_DAC_DIGITAL_2, 1, 4, dac_deemph_text);
338
339 static const char *speaker_mode_text[] = {
340 "Class D",
341 "Class AB",
342 };
343
344 static const struct soc_enum speaker_mode =
345 SOC_ENUM_SINGLE(WM9081_ANALOGUE_SPEAKER_2, 6, 2, speaker_mode_text);
346
347 static int speaker_mode_get(struct snd_kcontrol *kcontrol,
348 struct snd_ctl_elem_value *ucontrol)
349 {
350 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
351 unsigned int reg;
352
353 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
354 if (reg & WM9081_SPK_MODE)
355 ucontrol->value.integer.value[0] = 1;
356 else
357 ucontrol->value.integer.value[0] = 0;
358
359 return 0;
360 }
361
362 /*
363 * Stop any attempts to change speaker mode while the speaker is enabled.
364 *
365 * We also have some special anti-pop controls dependent on speaker
366 * mode which must be changed along with the mode.
367 */
368 static int speaker_mode_put(struct snd_kcontrol *kcontrol,
369 struct snd_ctl_elem_value *ucontrol)
370 {
371 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
372 unsigned int reg_pwr = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
373 unsigned int reg2 = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
374
375 /* Are we changing anything? */
376 if (ucontrol->value.integer.value[0] ==
377 ((reg2 & WM9081_SPK_MODE) != 0))
378 return 0;
379
380 /* Don't try to change modes while enabled */
381 if (reg_pwr & WM9081_SPK_ENA)
382 return -EINVAL;
383
384 if (ucontrol->value.integer.value[0]) {
385 /* Class AB */
386 reg2 &= ~(WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL);
387 reg2 |= WM9081_SPK_MODE;
388 } else {
389 /* Class D */
390 reg2 |= WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL;
391 reg2 &= ~WM9081_SPK_MODE;
392 }
393
394 snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_2, reg2);
395
396 return 0;
397 }
398
399 static const struct snd_kcontrol_new wm9081_snd_controls[] = {
400 SOC_SINGLE_TLV("IN1 Volume", WM9081_ANALOGUE_MIXER, 1, 1, 1, in_tlv),
401 SOC_SINGLE_TLV("IN2 Volume", WM9081_ANALOGUE_MIXER, 3, 1, 1, in_tlv),
402
403 SOC_SINGLE_TLV("Playback Volume", WM9081_DAC_DIGITAL_1, 1, 96, 0, dac_tlv),
404
405 SOC_SINGLE("LINEOUT Switch", WM9081_ANALOGUE_LINEOUT, 7, 1, 1),
406 SOC_SINGLE("LINEOUT ZC Switch", WM9081_ANALOGUE_LINEOUT, 6, 1, 0),
407 SOC_SINGLE_TLV("LINEOUT Volume", WM9081_ANALOGUE_LINEOUT, 0, 63, 0, out_tlv),
408
409 SOC_SINGLE("DRC Switch", WM9081_DRC_1, 15, 1, 0),
410 SOC_ENUM("DRC High Slope", drc_high),
411 SOC_ENUM("DRC Low Slope", drc_low),
412 SOC_SINGLE_TLV("DRC Input Volume", WM9081_DRC_4, 5, 60, 1, drc_in_tlv),
413 SOC_SINGLE_TLV("DRC Output Volume", WM9081_DRC_4, 0, 30, 1, drc_out_tlv),
414 SOC_SINGLE_TLV("DRC Minimum Volume", WM9081_DRC_2, 2, 3, 1, drc_min_tlv),
415 SOC_SINGLE_TLV("DRC Maximum Volume", WM9081_DRC_2, 0, 3, 0, drc_max_tlv),
416 SOC_ENUM("DRC Attack", drc_atk),
417 SOC_ENUM("DRC Decay", drc_dcy),
418 SOC_SINGLE("DRC Quick Release Switch", WM9081_DRC_1, 2, 1, 0),
419 SOC_SINGLE_TLV("DRC Quick Release Volume", WM9081_DRC_2, 6, 3, 0, drc_qr_tlv),
420 SOC_ENUM("DRC Quick Release Decay", drc_qr_dcy),
421 SOC_SINGLE_TLV("DRC Startup Volume", WM9081_DRC_1, 6, 18, 0, drc_startup_tlv),
422
423 SOC_SINGLE("EQ Switch", WM9081_EQ_1, 0, 1, 0),
424
425 SOC_SINGLE("Speaker DC Volume", WM9081_ANALOGUE_SPEAKER_1, 3, 5, 0),
426 SOC_SINGLE("Speaker AC Volume", WM9081_ANALOGUE_SPEAKER_1, 0, 5, 0),
427 SOC_SINGLE("Speaker Switch", WM9081_ANALOGUE_SPEAKER_PGA, 7, 1, 1),
428 SOC_SINGLE("Speaker ZC Switch", WM9081_ANALOGUE_SPEAKER_PGA, 6, 1, 0),
429 SOC_SINGLE_TLV("Speaker Volume", WM9081_ANALOGUE_SPEAKER_PGA, 0, 63, 0,
430 out_tlv),
431 SOC_ENUM("DAC Deemphasis", dac_deemph),
432 SOC_ENUM_EXT("Speaker Mode", speaker_mode, speaker_mode_get, speaker_mode_put),
433 };
434
435 static const struct snd_kcontrol_new wm9081_eq_controls[] = {
436 SOC_SINGLE_TLV("EQ1 Volume", WM9081_EQ_1, 11, 24, 0, eq_tlv),
437 SOC_SINGLE_TLV("EQ2 Volume", WM9081_EQ_1, 6, 24, 0, eq_tlv),
438 SOC_SINGLE_TLV("EQ3 Volume", WM9081_EQ_1, 1, 24, 0, eq_tlv),
439 SOC_SINGLE_TLV("EQ4 Volume", WM9081_EQ_2, 11, 24, 0, eq_tlv),
440 SOC_SINGLE_TLV("EQ5 Volume", WM9081_EQ_2, 6, 24, 0, eq_tlv),
441 };
442
443 static const struct snd_kcontrol_new mixer[] = {
444 SOC_DAPM_SINGLE("IN1 Switch", WM9081_ANALOGUE_MIXER, 0, 1, 0),
445 SOC_DAPM_SINGLE("IN2 Switch", WM9081_ANALOGUE_MIXER, 2, 1, 0),
446 SOC_DAPM_SINGLE("Playback Switch", WM9081_ANALOGUE_MIXER, 4, 1, 0),
447 };
448
449 struct _fll_div {
450 u16 fll_fratio;
451 u16 fll_outdiv;
452 u16 fll_clk_ref_div;
453 u16 n;
454 u16 k;
455 };
456
457 /* The size in bits of the FLL divide multiplied by 10
458 * to allow rounding later */
459 #define FIXED_FLL_SIZE ((1 << 16) * 10)
460
461 static struct {
462 unsigned int min;
463 unsigned int max;
464 u16 fll_fratio;
465 int ratio;
466 } fll_fratios[] = {
467 { 0, 64000, 4, 16 },
468 { 64000, 128000, 3, 8 },
469 { 128000, 256000, 2, 4 },
470 { 256000, 1000000, 1, 2 },
471 { 1000000, 13500000, 0, 1 },
472 };
473
474 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
475 unsigned int Fout)
476 {
477 u64 Kpart;
478 unsigned int K, Ndiv, Nmod, target;
479 unsigned int div;
480 int i;
481
482 /* Fref must be <=13.5MHz */
483 div = 1;
484 while ((Fref / div) > 13500000) {
485 div *= 2;
486
487 if (div > 8) {
488 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
489 Fref);
490 return -EINVAL;
491 }
492 }
493 fll_div->fll_clk_ref_div = div / 2;
494
495 pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
496
497 /* Apply the division for our remaining calculations */
498 Fref /= div;
499
500 /* Fvco should be 90-100MHz; don't check the upper bound */
501 div = 0;
502 target = Fout * 2;
503 while (target < 90000000) {
504 div++;
505 target *= 2;
506 if (div > 7) {
507 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
508 Fout);
509 return -EINVAL;
510 }
511 }
512 fll_div->fll_outdiv = div;
513
514 pr_debug("Fvco=%dHz\n", target);
515
516 /* Find an appropriate FLL_FRATIO and factor it out of the target */
517 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
518 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
519 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
520 target /= fll_fratios[i].ratio;
521 break;
522 }
523 }
524 if (i == ARRAY_SIZE(fll_fratios)) {
525 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
526 return -EINVAL;
527 }
528
529 /* Now, calculate N.K */
530 Ndiv = target / Fref;
531
532 fll_div->n = Ndiv;
533 Nmod = target % Fref;
534 pr_debug("Nmod=%d\n", Nmod);
535
536 /* Calculate fractional part - scale up so we can round. */
537 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
538
539 do_div(Kpart, Fref);
540
541 K = Kpart & 0xFFFFFFFF;
542
543 if ((K % 10) >= 5)
544 K += 5;
545
546 /* Move down to proper range now rounding is done */
547 fll_div->k = K / 10;
548
549 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
550 fll_div->n, fll_div->k,
551 fll_div->fll_fratio, fll_div->fll_outdiv,
552 fll_div->fll_clk_ref_div);
553
554 return 0;
555 }
556
557 static int wm9081_set_fll(struct snd_soc_codec *codec, int fll_id,
558 unsigned int Fref, unsigned int Fout)
559 {
560 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
561 u16 reg1, reg4, reg5;
562 struct _fll_div fll_div;
563 int ret;
564 int clk_sys_reg;
565
566 /* Any change? */
567 if (Fref == wm9081->fll_fref && Fout == wm9081->fll_fout)
568 return 0;
569
570 /* Disable the FLL */
571 if (Fout == 0) {
572 dev_dbg(codec->dev, "FLL disabled\n");
573 wm9081->fll_fref = 0;
574 wm9081->fll_fout = 0;
575
576 return 0;
577 }
578
579 ret = fll_factors(&fll_div, Fref, Fout);
580 if (ret != 0)
581 return ret;
582
583 reg5 = snd_soc_read(codec, WM9081_FLL_CONTROL_5);
584 reg5 &= ~WM9081_FLL_CLK_SRC_MASK;
585
586 switch (fll_id) {
587 case WM9081_SYSCLK_FLL_MCLK:
588 reg5 |= 0x1;
589 break;
590
591 default:
592 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
593 return -EINVAL;
594 }
595
596 /* Disable CLK_SYS while we reconfigure */
597 clk_sys_reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
598 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
599 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3,
600 clk_sys_reg & ~WM9081_CLK_SYS_ENA);
601
602 /* Any FLL configuration change requires that the FLL be
603 * disabled first. */
604 reg1 = snd_soc_read(codec, WM9081_FLL_CONTROL_1);
605 reg1 &= ~WM9081_FLL_ENA;
606 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
607
608 /* Apply the configuration */
609 if (fll_div.k)
610 reg1 |= WM9081_FLL_FRAC_MASK;
611 else
612 reg1 &= ~WM9081_FLL_FRAC_MASK;
613 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
614
615 snd_soc_write(codec, WM9081_FLL_CONTROL_2,
616 (fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) |
617 (fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT));
618 snd_soc_write(codec, WM9081_FLL_CONTROL_3, fll_div.k);
619
620 reg4 = snd_soc_read(codec, WM9081_FLL_CONTROL_4);
621 reg4 &= ~WM9081_FLL_N_MASK;
622 reg4 |= fll_div.n << WM9081_FLL_N_SHIFT;
623 snd_soc_write(codec, WM9081_FLL_CONTROL_4, reg4);
624
625 reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK;
626 reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT;
627 snd_soc_write(codec, WM9081_FLL_CONTROL_5, reg5);
628
629 /* Set gain to the recommended value */
630 snd_soc_update_bits(codec, WM9081_FLL_CONTROL_4,
631 WM9081_FLL_GAIN_MASK, 0);
632
633 /* Enable the FLL */
634 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA);
635
636 /* Then bring CLK_SYS up again if it was disabled */
637 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
638 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, clk_sys_reg);
639
640 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
641
642 wm9081->fll_fref = Fref;
643 wm9081->fll_fout = Fout;
644
645 return 0;
646 }
647
648 static int configure_clock(struct snd_soc_codec *codec)
649 {
650 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
651 int new_sysclk, i, target;
652 unsigned int reg;
653 int ret = 0;
654 int mclkdiv = 0;
655 int fll = 0;
656
657 switch (wm9081->sysclk_source) {
658 case WM9081_SYSCLK_MCLK:
659 if (wm9081->mclk_rate > 12225000) {
660 mclkdiv = 1;
661 wm9081->sysclk_rate = wm9081->mclk_rate / 2;
662 } else {
663 wm9081->sysclk_rate = wm9081->mclk_rate;
664 }
665 wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK, 0, 0);
666 break;
667
668 case WM9081_SYSCLK_FLL_MCLK:
669 /* If we have a sample rate calculate a CLK_SYS that
670 * gives us a suitable DAC configuration, plus BCLK.
671 * Ideally we would check to see if we can clock
672 * directly from MCLK and only use the FLL if this is
673 * not the case, though care must be taken with free
674 * running mode.
675 */
676 if (wm9081->master && wm9081->bclk) {
677 /* Make sure we can generate CLK_SYS and BCLK
678 * and that we've got 3MHz for optimal
679 * performance. */
680 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
681 target = wm9081->fs * clk_sys_rates[i].ratio;
682 new_sysclk = target;
683 if (target >= wm9081->bclk &&
684 target > 3000000)
685 break;
686 }
687
688 if (i == ARRAY_SIZE(clk_sys_rates))
689 return -EINVAL;
690
691 } else if (wm9081->fs) {
692 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
693 new_sysclk = clk_sys_rates[i].ratio
694 * wm9081->fs;
695 if (new_sysclk > 3000000)
696 break;
697 }
698
699 if (i == ARRAY_SIZE(clk_sys_rates))
700 return -EINVAL;
701
702 } else {
703 new_sysclk = 12288000;
704 }
705
706 ret = wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK,
707 wm9081->mclk_rate, new_sysclk);
708 if (ret == 0) {
709 wm9081->sysclk_rate = new_sysclk;
710
711 /* Switch SYSCLK over to FLL */
712 fll = 1;
713 } else {
714 wm9081->sysclk_rate = wm9081->mclk_rate;
715 }
716 break;
717
718 default:
719 return -EINVAL;
720 }
721
722 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_1);
723 if (mclkdiv)
724 reg |= WM9081_MCLKDIV2;
725 else
726 reg &= ~WM9081_MCLKDIV2;
727 snd_soc_write(codec, WM9081_CLOCK_CONTROL_1, reg);
728
729 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
730 if (fll)
731 reg |= WM9081_CLK_SRC_SEL;
732 else
733 reg &= ~WM9081_CLK_SRC_SEL;
734 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, reg);
735
736 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate);
737
738 return ret;
739 }
740
741 static int clk_sys_event(struct snd_soc_dapm_widget *w,
742 struct snd_kcontrol *kcontrol, int event)
743 {
744 struct snd_soc_codec *codec = w->codec;
745 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
746
747 /* This should be done on init() for bypass paths */
748 switch (wm9081->sysclk_source) {
749 case WM9081_SYSCLK_MCLK:
750 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm9081->mclk_rate);
751 break;
752 case WM9081_SYSCLK_FLL_MCLK:
753 dev_dbg(codec->dev, "Using %dHz MCLK with FLL\n",
754 wm9081->mclk_rate);
755 break;
756 default:
757 dev_err(codec->dev, "System clock not configured\n");
758 return -EINVAL;
759 }
760
761 switch (event) {
762 case SND_SOC_DAPM_PRE_PMU:
763 configure_clock(codec);
764 break;
765
766 case SND_SOC_DAPM_POST_PMD:
767 /* Disable the FLL if it's running */
768 wm9081_set_fll(codec, 0, 0, 0);
769 break;
770 }
771
772 return 0;
773 }
774
775 static const struct snd_soc_dapm_widget wm9081_dapm_widgets[] = {
776 SND_SOC_DAPM_INPUT("IN1"),
777 SND_SOC_DAPM_INPUT("IN2"),
778
779 SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM9081_POWER_MANAGEMENT, 0, 0),
780
781 SND_SOC_DAPM_MIXER_NAMED_CTL("Mixer", SND_SOC_NOPM, 0, 0,
782 mixer, ARRAY_SIZE(mixer)),
783
784 SND_SOC_DAPM_PGA("LINEOUT PGA", WM9081_POWER_MANAGEMENT, 4, 0, NULL, 0),
785
786 SND_SOC_DAPM_PGA("Speaker PGA", WM9081_POWER_MANAGEMENT, 2, 0, NULL, 0),
787 SND_SOC_DAPM_OUT_DRV("Speaker", WM9081_POWER_MANAGEMENT, 1, 0, NULL, 0),
788
789 SND_SOC_DAPM_OUTPUT("LINEOUT"),
790 SND_SOC_DAPM_OUTPUT("SPKN"),
791 SND_SOC_DAPM_OUTPUT("SPKP"),
792
793 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM9081_CLOCK_CONTROL_3, 0, 0, clk_sys_event,
794 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
795 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM9081_CLOCK_CONTROL_3, 1, 0, NULL, 0),
796 SND_SOC_DAPM_SUPPLY("TOCLK", WM9081_CLOCK_CONTROL_3, 2, 0, NULL, 0),
797 SND_SOC_DAPM_SUPPLY("TSENSE", WM9081_POWER_MANAGEMENT, 7, 0, NULL, 0),
798 };
799
800
801 static const struct snd_soc_dapm_route wm9081_audio_paths[] = {
802 { "DAC", NULL, "CLK_SYS" },
803 { "DAC", NULL, "CLK_DSP" },
804
805 { "Mixer", "IN1 Switch", "IN1" },
806 { "Mixer", "IN2 Switch", "IN2" },
807 { "Mixer", "Playback Switch", "DAC" },
808
809 { "LINEOUT PGA", NULL, "Mixer" },
810 { "LINEOUT PGA", NULL, "TOCLK" },
811 { "LINEOUT PGA", NULL, "CLK_SYS" },
812
813 { "LINEOUT", NULL, "LINEOUT PGA" },
814
815 { "Speaker PGA", NULL, "Mixer" },
816 { "Speaker PGA", NULL, "TOCLK" },
817 { "Speaker PGA", NULL, "CLK_SYS" },
818
819 { "Speaker", NULL, "Speaker PGA" },
820 { "Speaker", NULL, "TSENSE" },
821
822 { "SPKN", NULL, "Speaker" },
823 { "SPKP", NULL, "Speaker" },
824 };
825
826 static int wm9081_set_bias_level(struct snd_soc_codec *codec,
827 enum snd_soc_bias_level level)
828 {
829 switch (level) {
830 case SND_SOC_BIAS_ON:
831 break;
832
833 case SND_SOC_BIAS_PREPARE:
834 /* VMID=2*40k */
835 snd_soc_update_bits(codec, WM9081_VMID_CONTROL,
836 WM9081_VMID_SEL_MASK, 0x2);
837
838 /* Normal bias current */
839 snd_soc_update_bits(codec, WM9081_BIAS_CONTROL_1,
840 WM9081_STBY_BIAS_ENA, 0);
841 break;
842
843 case SND_SOC_BIAS_STANDBY:
844 /* Initial cold start */
845 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
846 /* Disable LINEOUT discharge */
847 snd_soc_update_bits(codec, WM9081_ANTI_POP_CONTROL,
848 WM9081_LINEOUT_DISCH, 0);
849
850 /* Select startup bias source */
851 snd_soc_update_bits(codec, WM9081_BIAS_CONTROL_1,
852 WM9081_BIAS_SRC | WM9081_BIAS_ENA,
853 WM9081_BIAS_SRC | WM9081_BIAS_ENA);
854
855 /* VMID 2*4k; Soft VMID ramp enable */
856 snd_soc_update_bits(codec, WM9081_VMID_CONTROL,
857 WM9081_VMID_RAMP |
858 WM9081_VMID_SEL_MASK,
859 WM9081_VMID_RAMP | 0x6);
860
861 mdelay(100);
862
863 /* Normal bias enable & soft start off */
864 snd_soc_update_bits(codec, WM9081_VMID_CONTROL,
865 WM9081_VMID_RAMP, 0);
866
867 /* Standard bias source */
868 snd_soc_update_bits(codec, WM9081_BIAS_CONTROL_1,
869 WM9081_BIAS_SRC, 0);
870 }
871
872 /* VMID 2*240k */
873 snd_soc_update_bits(codec, WM9081_VMID_CONTROL,
874 WM9081_VMID_SEL_MASK, 0x04);
875
876 /* Standby bias current on */
877 snd_soc_update_bits(codec, WM9081_BIAS_CONTROL_1,
878 WM9081_STBY_BIAS_ENA,
879 WM9081_STBY_BIAS_ENA);
880 break;
881
882 case SND_SOC_BIAS_OFF:
883 /* Startup bias source and disable bias */
884 snd_soc_update_bits(codec, WM9081_BIAS_CONTROL_1,
885 WM9081_BIAS_SRC | WM9081_BIAS_ENA,
886 WM9081_BIAS_SRC);
887
888 /* Disable VMID with soft ramping */
889 snd_soc_update_bits(codec, WM9081_VMID_CONTROL,
890 WM9081_VMID_RAMP | WM9081_VMID_SEL_MASK,
891 WM9081_VMID_RAMP);
892
893 /* Actively discharge LINEOUT */
894 snd_soc_update_bits(codec, WM9081_ANTI_POP_CONTROL,
895 WM9081_LINEOUT_DISCH,
896 WM9081_LINEOUT_DISCH);
897 break;
898 }
899
900 codec->dapm.bias_level = level;
901
902 return 0;
903 }
904
905 static int wm9081_set_dai_fmt(struct snd_soc_dai *dai,
906 unsigned int fmt)
907 {
908 struct snd_soc_codec *codec = dai->codec;
909 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
910 unsigned int aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
911
912 aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV |
913 WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK);
914
915 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
916 case SND_SOC_DAIFMT_CBS_CFS:
917 wm9081->master = 0;
918 break;
919 case SND_SOC_DAIFMT_CBS_CFM:
920 aif2 |= WM9081_LRCLK_DIR;
921 wm9081->master = 1;
922 break;
923 case SND_SOC_DAIFMT_CBM_CFS:
924 aif2 |= WM9081_BCLK_DIR;
925 wm9081->master = 1;
926 break;
927 case SND_SOC_DAIFMT_CBM_CFM:
928 aif2 |= WM9081_LRCLK_DIR | WM9081_BCLK_DIR;
929 wm9081->master = 1;
930 break;
931 default:
932 return -EINVAL;
933 }
934
935 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
936 case SND_SOC_DAIFMT_DSP_B:
937 aif2 |= WM9081_AIF_LRCLK_INV;
938 case SND_SOC_DAIFMT_DSP_A:
939 aif2 |= 0x3;
940 break;
941 case SND_SOC_DAIFMT_I2S:
942 aif2 |= 0x2;
943 break;
944 case SND_SOC_DAIFMT_RIGHT_J:
945 break;
946 case SND_SOC_DAIFMT_LEFT_J:
947 aif2 |= 0x1;
948 break;
949 default:
950 return -EINVAL;
951 }
952
953 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
954 case SND_SOC_DAIFMT_DSP_A:
955 case SND_SOC_DAIFMT_DSP_B:
956 /* frame inversion not valid for DSP modes */
957 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
958 case SND_SOC_DAIFMT_NB_NF:
959 break;
960 case SND_SOC_DAIFMT_IB_NF:
961 aif2 |= WM9081_AIF_BCLK_INV;
962 break;
963 default:
964 return -EINVAL;
965 }
966 break;
967
968 case SND_SOC_DAIFMT_I2S:
969 case SND_SOC_DAIFMT_RIGHT_J:
970 case SND_SOC_DAIFMT_LEFT_J:
971 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
972 case SND_SOC_DAIFMT_NB_NF:
973 break;
974 case SND_SOC_DAIFMT_IB_IF:
975 aif2 |= WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV;
976 break;
977 case SND_SOC_DAIFMT_IB_NF:
978 aif2 |= WM9081_AIF_BCLK_INV;
979 break;
980 case SND_SOC_DAIFMT_NB_IF:
981 aif2 |= WM9081_AIF_LRCLK_INV;
982 break;
983 default:
984 return -EINVAL;
985 }
986 break;
987 default:
988 return -EINVAL;
989 }
990
991 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
992
993 return 0;
994 }
995
996 static int wm9081_hw_params(struct snd_pcm_substream *substream,
997 struct snd_pcm_hw_params *params,
998 struct snd_soc_dai *dai)
999 {
1000 struct snd_soc_codec *codec = dai->codec;
1001 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
1002 int ret, i, best, best_val, cur_val;
1003 unsigned int clk_ctrl2, aif1, aif2, aif3, aif4;
1004
1005 clk_ctrl2 = snd_soc_read(codec, WM9081_CLOCK_CONTROL_2);
1006 clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK);
1007
1008 aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
1009
1010 aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
1011 aif2 &= ~WM9081_AIF_WL_MASK;
1012
1013 aif3 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_3);
1014 aif3 &= ~WM9081_BCLK_DIV_MASK;
1015
1016 aif4 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_4);
1017 aif4 &= ~WM9081_LRCLK_RATE_MASK;
1018
1019 wm9081->fs = params_rate(params);
1020
1021 if (wm9081->tdm_width) {
1022 /* If TDM is set up then that fixes our BCLK. */
1023 int slots = ((aif1 & WM9081_AIFDAC_TDM_MODE_MASK) >>
1024 WM9081_AIFDAC_TDM_MODE_SHIFT) + 1;
1025
1026 wm9081->bclk = wm9081->fs * wm9081->tdm_width * slots;
1027 } else {
1028 /* Otherwise work out a BCLK from the sample size */
1029 wm9081->bclk = 2 * wm9081->fs;
1030
1031 switch (params_format(params)) {
1032 case SNDRV_PCM_FORMAT_S16_LE:
1033 wm9081->bclk *= 16;
1034 break;
1035 case SNDRV_PCM_FORMAT_S20_3LE:
1036 wm9081->bclk *= 20;
1037 aif2 |= 0x4;
1038 break;
1039 case SNDRV_PCM_FORMAT_S24_LE:
1040 wm9081->bclk *= 24;
1041 aif2 |= 0x8;
1042 break;
1043 case SNDRV_PCM_FORMAT_S32_LE:
1044 wm9081->bclk *= 32;
1045 aif2 |= 0xc;
1046 break;
1047 default:
1048 return -EINVAL;
1049 }
1050 }
1051
1052 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm9081->bclk);
1053
1054 ret = configure_clock(codec);
1055 if (ret != 0)
1056 return ret;
1057
1058 /* Select nearest CLK_SYS_RATE */
1059 best = 0;
1060 best_val = abs((wm9081->sysclk_rate / clk_sys_rates[0].ratio)
1061 - wm9081->fs);
1062 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1063 cur_val = abs((wm9081->sysclk_rate /
1064 clk_sys_rates[i].ratio) - wm9081->fs);
1065 if (cur_val < best_val) {
1066 best = i;
1067 best_val = cur_val;
1068 }
1069 }
1070 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1071 clk_sys_rates[best].ratio);
1072 clk_ctrl2 |= (clk_sys_rates[best].clk_sys_rate
1073 << WM9081_CLK_SYS_RATE_SHIFT);
1074
1075 /* SAMPLE_RATE */
1076 best = 0;
1077 best_val = abs(wm9081->fs - sample_rates[0].rate);
1078 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1079 /* Closest match */
1080 cur_val = abs(wm9081->fs - sample_rates[i].rate);
1081 if (cur_val < best_val) {
1082 best = i;
1083 best_val = cur_val;
1084 }
1085 }
1086 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1087 sample_rates[best].rate);
1088 clk_ctrl2 |= (sample_rates[best].sample_rate
1089 << WM9081_SAMPLE_RATE_SHIFT);
1090
1091 /* BCLK_DIV */
1092 best = 0;
1093 best_val = INT_MAX;
1094 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1095 cur_val = ((wm9081->sysclk_rate * 10) / bclk_divs[i].div)
1096 - wm9081->bclk;
1097 if (cur_val < 0) /* Table is sorted */
1098 break;
1099 if (cur_val < best_val) {
1100 best = i;
1101 best_val = cur_val;
1102 }
1103 }
1104 wm9081->bclk = (wm9081->sysclk_rate * 10) / bclk_divs[best].div;
1105 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1106 bclk_divs[best].div, wm9081->bclk);
1107 aif3 |= bclk_divs[best].bclk_div;
1108
1109 /* LRCLK is a simple fraction of BCLK */
1110 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm9081->bclk / wm9081->fs);
1111 aif4 |= wm9081->bclk / wm9081->fs;
1112
1113 /* Apply a ReTune Mobile configuration if it's in use */
1114 if (wm9081->pdata.num_retune_configs) {
1115 struct wm9081_pdata *pdata = &wm9081->pdata;
1116 struct wm9081_retune_mobile_setting *s;
1117 int eq1;
1118
1119 best = 0;
1120 best_val = abs(pdata->retune_configs[0].rate - wm9081->fs);
1121 for (i = 0; i < pdata->num_retune_configs; i++) {
1122 cur_val = abs(pdata->retune_configs[i].rate -
1123 wm9081->fs);
1124 if (cur_val < best_val) {
1125 best_val = cur_val;
1126 best = i;
1127 }
1128 }
1129 s = &pdata->retune_configs[best];
1130
1131 dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
1132 s->name, s->rate);
1133
1134 /* If the EQ is enabled then disable it while we write out */
1135 eq1 = snd_soc_read(codec, WM9081_EQ_1) & WM9081_EQ_ENA;
1136 if (eq1 & WM9081_EQ_ENA)
1137 snd_soc_write(codec, WM9081_EQ_1, 0);
1138
1139 /* Write out the other values */
1140 for (i = 1; i < ARRAY_SIZE(s->config); i++)
1141 snd_soc_write(codec, WM9081_EQ_1 + i, s->config[i]);
1142
1143 eq1 |= (s->config[0] & ~WM9081_EQ_ENA);
1144 snd_soc_write(codec, WM9081_EQ_1, eq1);
1145 }
1146
1147 snd_soc_write(codec, WM9081_CLOCK_CONTROL_2, clk_ctrl2);
1148 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
1149 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_3, aif3);
1150 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_4, aif4);
1151
1152 return 0;
1153 }
1154
1155 static int wm9081_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1156 {
1157 struct snd_soc_codec *codec = codec_dai->codec;
1158 unsigned int reg;
1159
1160 reg = snd_soc_read(codec, WM9081_DAC_DIGITAL_2);
1161
1162 if (mute)
1163 reg |= WM9081_DAC_MUTE;
1164 else
1165 reg &= ~WM9081_DAC_MUTE;
1166
1167 snd_soc_write(codec, WM9081_DAC_DIGITAL_2, reg);
1168
1169 return 0;
1170 }
1171
1172 static int wm9081_set_sysclk(struct snd_soc_codec *codec, int clk_id,
1173 int source, unsigned int freq, int dir)
1174 {
1175 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
1176
1177 switch (clk_id) {
1178 case WM9081_SYSCLK_MCLK:
1179 case WM9081_SYSCLK_FLL_MCLK:
1180 wm9081->sysclk_source = clk_id;
1181 wm9081->mclk_rate = freq;
1182 break;
1183
1184 default:
1185 return -EINVAL;
1186 }
1187
1188 return 0;
1189 }
1190
1191 static int wm9081_set_tdm_slot(struct snd_soc_dai *dai,
1192 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1193 {
1194 struct snd_soc_codec *codec = dai->codec;
1195 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
1196 unsigned int aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
1197
1198 aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK);
1199
1200 if (slots < 0 || slots > 4)
1201 return -EINVAL;
1202
1203 wm9081->tdm_width = slot_width;
1204
1205 if (slots == 0)
1206 slots = 1;
1207
1208 aif1 |= (slots - 1) << WM9081_AIFDAC_TDM_MODE_SHIFT;
1209
1210 switch (rx_mask) {
1211 case 1:
1212 break;
1213 case 2:
1214 aif1 |= 0x10;
1215 break;
1216 case 4:
1217 aif1 |= 0x20;
1218 break;
1219 case 8:
1220 aif1 |= 0x30;
1221 break;
1222 default:
1223 return -EINVAL;
1224 }
1225
1226 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_1, aif1);
1227
1228 return 0;
1229 }
1230
1231 #define WM9081_RATES SNDRV_PCM_RATE_8000_96000
1232
1233 #define WM9081_FORMATS \
1234 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1235 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1236
1237 static const struct snd_soc_dai_ops wm9081_dai_ops = {
1238 .hw_params = wm9081_hw_params,
1239 .set_fmt = wm9081_set_dai_fmt,
1240 .digital_mute = wm9081_digital_mute,
1241 .set_tdm_slot = wm9081_set_tdm_slot,
1242 };
1243
1244 /* We report two channels because the CODEC processes a stereo signal, even
1245 * though it is only capable of handling a mono output.
1246 */
1247 static struct snd_soc_dai_driver wm9081_dai = {
1248 .name = "wm9081-hifi",
1249 .playback = {
1250 .stream_name = "HiFi Playback",
1251 .channels_min = 1,
1252 .channels_max = 2,
1253 .rates = WM9081_RATES,
1254 .formats = WM9081_FORMATS,
1255 },
1256 .ops = &wm9081_dai_ops,
1257 };
1258
1259 static int wm9081_probe(struct snd_soc_codec *codec)
1260 {
1261 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
1262 int ret;
1263 u16 reg;
1264
1265 codec->control_data = wm9081->regmap;
1266
1267 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP);
1268 if (ret != 0) {
1269 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1270 return ret;
1271 }
1272
1273 reg = 0;
1274 if (wm9081->pdata.irq_high)
1275 reg |= WM9081_IRQ_POL;
1276 if (!wm9081->pdata.irq_cmos)
1277 reg |= WM9081_IRQ_OP_CTRL;
1278 snd_soc_update_bits(codec, WM9081_INTERRUPT_CONTROL,
1279 WM9081_IRQ_POL | WM9081_IRQ_OP_CTRL, reg);
1280
1281 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1282
1283 /* Enable zero cross by default */
1284 snd_soc_update_bits(codec, WM9081_ANALOGUE_LINEOUT,
1285 WM9081_LINEOUTZC, WM9081_LINEOUTZC);
1286 snd_soc_update_bits(codec, WM9081_ANALOGUE_SPEAKER_PGA,
1287 WM9081_SPKPGAZC, WM9081_SPKPGAZC);
1288
1289 if (!wm9081->pdata.num_retune_configs) {
1290 dev_dbg(codec->dev,
1291 "No ReTune Mobile data, using normal EQ\n");
1292 snd_soc_add_controls(codec, wm9081_eq_controls,
1293 ARRAY_SIZE(wm9081_eq_controls));
1294 }
1295
1296 return ret;
1297 }
1298
1299 static int wm9081_remove(struct snd_soc_codec *codec)
1300 {
1301 wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF);
1302 return 0;
1303 }
1304
1305 #ifdef CONFIG_PM
1306 static int wm9081_suspend(struct snd_soc_codec *codec, pm_message_t state)
1307 {
1308 wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF);
1309
1310 return 0;
1311 }
1312
1313 static int wm9081_resume(struct snd_soc_codec *codec)
1314 {
1315 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
1316
1317 regcache_sync(wm9081->regmap);
1318
1319 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1320
1321 return 0;
1322 }
1323 #else
1324 #define wm9081_suspend NULL
1325 #define wm9081_resume NULL
1326 #endif
1327
1328 static struct snd_soc_codec_driver soc_codec_dev_wm9081 = {
1329 .probe = wm9081_probe,
1330 .remove = wm9081_remove,
1331 .suspend = wm9081_suspend,
1332 .resume = wm9081_resume,
1333
1334 .set_sysclk = wm9081_set_sysclk,
1335 .set_bias_level = wm9081_set_bias_level,
1336
1337 .controls = wm9081_snd_controls,
1338 .num_controls = ARRAY_SIZE(wm9081_snd_controls),
1339 .dapm_widgets = wm9081_dapm_widgets,
1340 .num_dapm_widgets = ARRAY_SIZE(wm9081_dapm_widgets),
1341 .dapm_routes = wm9081_audio_paths,
1342 .num_dapm_routes = ARRAY_SIZE(wm9081_audio_paths),
1343 };
1344
1345 static const struct regmap_config wm9081_regmap = {
1346 .reg_bits = 8,
1347 .val_bits = 16,
1348
1349 .max_register = WM9081_MAX_REGISTER,
1350 .reg_defaults = wm9081_reg,
1351 .num_reg_defaults = ARRAY_SIZE(wm9081_reg),
1352 .volatile_reg = wm9081_volatile_register,
1353 .readable_reg = wm9081_readable_register,
1354 .cache_type = REGCACHE_RBTREE,
1355 };
1356
1357 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1358 static __devinit int wm9081_i2c_probe(struct i2c_client *i2c,
1359 const struct i2c_device_id *id)
1360 {
1361 struct wm9081_priv *wm9081;
1362 unsigned int reg;
1363 int ret;
1364
1365 wm9081 = kzalloc(sizeof(struct wm9081_priv), GFP_KERNEL);
1366 if (wm9081 == NULL)
1367 return -ENOMEM;
1368
1369 i2c_set_clientdata(i2c, wm9081);
1370
1371 wm9081->regmap = regmap_init_i2c(i2c, &wm9081_regmap);
1372 if (IS_ERR(wm9081->regmap)) {
1373 ret = PTR_ERR(wm9081->regmap);
1374 dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
1375 goto err;
1376 }
1377
1378 ret = regmap_read(wm9081->regmap, WM9081_SOFTWARE_RESET, &reg);
1379 if (ret != 0) {
1380 dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
1381 goto err_regmap;
1382 }
1383 if (reg != 0x9081) {
1384 dev_err(&i2c->dev, "Device is not a WM9081: ID=0x%x\n", reg);
1385 ret = -EINVAL;
1386 goto err_regmap;
1387 }
1388
1389 ret = wm9081_reset(wm9081->regmap);
1390 if (ret < 0) {
1391 dev_err(&i2c->dev, "Failed to issue reset\n");
1392 goto err_regmap;
1393 }
1394
1395 if (dev_get_platdata(&i2c->dev))
1396 memcpy(&wm9081->pdata, dev_get_platdata(&i2c->dev),
1397 sizeof(wm9081->pdata));
1398
1399 ret = snd_soc_register_codec(&i2c->dev,
1400 &soc_codec_dev_wm9081, &wm9081_dai, 1);
1401 if (ret < 0)
1402 goto err_regmap;
1403
1404 return 0;
1405
1406 err_regmap:
1407 regmap_exit(wm9081->regmap);
1408 err:
1409 kfree(wm9081);
1410
1411 return ret;
1412 }
1413
1414 static __devexit int wm9081_i2c_remove(struct i2c_client *client)
1415 {
1416 struct wm9081_priv *wm9081 = i2c_get_clientdata(client);
1417
1418 snd_soc_unregister_codec(&client->dev);
1419 regmap_exit(wm9081->regmap);
1420 kfree(i2c_get_clientdata(client));
1421 return 0;
1422 }
1423
1424 static const struct i2c_device_id wm9081_i2c_id[] = {
1425 { "wm9081", 0 },
1426 { }
1427 };
1428 MODULE_DEVICE_TABLE(i2c, wm9081_i2c_id);
1429
1430 static struct i2c_driver wm9081_i2c_driver = {
1431 .driver = {
1432 .name = "wm9081",
1433 .owner = THIS_MODULE,
1434 },
1435 .probe = wm9081_i2c_probe,
1436 .remove = __devexit_p(wm9081_i2c_remove),
1437 .id_table = wm9081_i2c_id,
1438 };
1439 #endif
1440
1441 static int __init wm9081_modinit(void)
1442 {
1443 int ret = 0;
1444 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1445 ret = i2c_add_driver(&wm9081_i2c_driver);
1446 if (ret != 0) {
1447 printk(KERN_ERR "Failed to register WM9081 I2C driver: %d\n",
1448 ret);
1449 }
1450 #endif
1451 return ret;
1452 }
1453 module_init(wm9081_modinit);
1454
1455 static void __exit wm9081_exit(void)
1456 {
1457 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1458 i2c_del_driver(&wm9081_i2c_driver);
1459 #endif
1460 }
1461 module_exit(wm9081_exit);
1462
1463
1464 MODULE_DESCRIPTION("ASoC WM9081 driver");
1465 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1466 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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