2 * wm9081.c -- WM9081 ALSA SoC Audio driver
6 * Copyright 2009 Wolfson Microelectronics plc
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 #include <linux/regmap.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/soc.h>
28 #include <sound/initval.h>
29 #include <sound/tlv.h>
31 #include <sound/wm9081.h>
34 static struct reg_default wm9081_reg
[] = {
35 { 0, 0x9081 }, /* R0 - Software Reset */
36 { 2, 0x00B9 }, /* R2 - Analogue Lineout */
37 { 3, 0x00B9 }, /* R3 - Analogue Speaker PGA */
38 { 4, 0x0001 }, /* R4 - VMID Control */
39 { 5, 0x0068 }, /* R5 - Bias Control 1 */
40 { 7, 0x0000 }, /* R7 - Analogue Mixer */
41 { 8, 0x0000 }, /* R8 - Anti Pop Control */
42 { 9, 0x01DB }, /* R9 - Analogue Speaker 1 */
43 { 10, 0x0018 }, /* R10 - Analogue Speaker 2 */
44 { 11, 0x0180 }, /* R11 - Power Management */
45 { 12, 0x0000 }, /* R12 - Clock Control 1 */
46 { 13, 0x0038 }, /* R13 - Clock Control 2 */
47 { 14, 0x4000 }, /* R14 - Clock Control 3 */
48 { 16, 0x0000 }, /* R16 - FLL Control 1 */
49 { 17, 0x0200 }, /* R17 - FLL Control 2 */
50 { 18, 0x0000 }, /* R18 - FLL Control 3 */
51 { 19, 0x0204 }, /* R19 - FLL Control 4 */
52 { 20, 0x0000 }, /* R20 - FLL Control 5 */
53 { 22, 0x0000 }, /* R22 - Audio Interface 1 */
54 { 23, 0x0002 }, /* R23 - Audio Interface 2 */
55 { 24, 0x0008 }, /* R24 - Audio Interface 3 */
56 { 25, 0x0022 }, /* R25 - Audio Interface 4 */
57 { 27, 0x0006 }, /* R27 - Interrupt Status Mask */
58 { 28, 0x0000 }, /* R28 - Interrupt Polarity */
59 { 29, 0x0000 }, /* R29 - Interrupt Control */
60 { 30, 0x00C0 }, /* R30 - DAC Digital 1 */
61 { 31, 0x0008 }, /* R31 - DAC Digital 2 */
62 { 32, 0x09AF }, /* R32 - DRC 1 */
63 { 33, 0x4201 }, /* R33 - DRC 2 */
64 { 34, 0x0000 }, /* R34 - DRC 3 */
65 { 35, 0x0000 }, /* R35 - DRC 4 */
66 { 38, 0x0000 }, /* R38 - Write Sequencer 1 */
67 { 39, 0x0000 }, /* R39 - Write Sequencer 2 */
68 { 40, 0x0002 }, /* R40 - MW Slave 1 */
69 { 42, 0x0000 }, /* R42 - EQ 1 */
70 { 43, 0x0000 }, /* R43 - EQ 2 */
71 { 44, 0x0FCA }, /* R44 - EQ 3 */
72 { 45, 0x0400 }, /* R45 - EQ 4 */
73 { 46, 0x00B8 }, /* R46 - EQ 5 */
74 { 47, 0x1EB5 }, /* R47 - EQ 6 */
75 { 48, 0xF145 }, /* R48 - EQ 7 */
76 { 49, 0x0B75 }, /* R49 - EQ 8 */
77 { 50, 0x01C5 }, /* R50 - EQ 9 */
78 { 51, 0x169E }, /* R51 - EQ 10 */
79 { 52, 0xF829 }, /* R52 - EQ 11 */
80 { 53, 0x07AD }, /* R53 - EQ 12 */
81 { 54, 0x1103 }, /* R54 - EQ 13 */
82 { 55, 0x1C58 }, /* R55 - EQ 14 */
83 { 56, 0xF373 }, /* R56 - EQ 15 */
84 { 57, 0x0A54 }, /* R57 - EQ 16 */
85 { 58, 0x0558 }, /* R58 - EQ 17 */
86 { 59, 0x0564 }, /* R59 - EQ 18 */
87 { 60, 0x0559 }, /* R60 - EQ 19 */
88 { 61, 0x4000 }, /* R61 - EQ 20 */
125 int div
; /* *10 due to .5s */
152 struct regmap
*regmap
;
162 struct wm9081_pdata pdata
;
165 static bool wm9081_volatile_register(struct device
*dev
, unsigned int reg
)
168 case WM9081_SOFTWARE_RESET
:
169 case WM9081_INTERRUPT_STATUS
:
176 static bool wm9081_readable_register(struct device
*dev
, unsigned int reg
)
179 case WM9081_SOFTWARE_RESET
:
180 case WM9081_ANALOGUE_LINEOUT
:
181 case WM9081_ANALOGUE_SPEAKER_PGA
:
182 case WM9081_VMID_CONTROL
:
183 case WM9081_BIAS_CONTROL_1
:
184 case WM9081_ANALOGUE_MIXER
:
185 case WM9081_ANTI_POP_CONTROL
:
186 case WM9081_ANALOGUE_SPEAKER_1
:
187 case WM9081_ANALOGUE_SPEAKER_2
:
188 case WM9081_POWER_MANAGEMENT
:
189 case WM9081_CLOCK_CONTROL_1
:
190 case WM9081_CLOCK_CONTROL_2
:
191 case WM9081_CLOCK_CONTROL_3
:
192 case WM9081_FLL_CONTROL_1
:
193 case WM9081_FLL_CONTROL_2
:
194 case WM9081_FLL_CONTROL_3
:
195 case WM9081_FLL_CONTROL_4
:
196 case WM9081_FLL_CONTROL_5
:
197 case WM9081_AUDIO_INTERFACE_1
:
198 case WM9081_AUDIO_INTERFACE_2
:
199 case WM9081_AUDIO_INTERFACE_3
:
200 case WM9081_AUDIO_INTERFACE_4
:
201 case WM9081_INTERRUPT_STATUS
:
202 case WM9081_INTERRUPT_STATUS_MASK
:
203 case WM9081_INTERRUPT_POLARITY
:
204 case WM9081_INTERRUPT_CONTROL
:
205 case WM9081_DAC_DIGITAL_1
:
206 case WM9081_DAC_DIGITAL_2
:
211 case WM9081_WRITE_SEQUENCER_1
:
212 case WM9081_WRITE_SEQUENCER_2
:
213 case WM9081_MW_SLAVE_1
:
240 static int wm9081_reset(struct regmap
*map
)
242 return regmap_write(map
, WM9081_SOFTWARE_RESET
, 0x9081);
245 static const DECLARE_TLV_DB_SCALE(drc_in_tlv
, -4500, 75, 0);
246 static const DECLARE_TLV_DB_SCALE(drc_out_tlv
, -2250, 75, 0);
247 static const DECLARE_TLV_DB_SCALE(drc_min_tlv
, -1800, 600, 0);
248 static unsigned int drc_max_tlv
[] = {
249 TLV_DB_RANGE_HEAD(4),
250 0, 0, TLV_DB_SCALE_ITEM(1200, 0, 0),
251 1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0),
252 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
253 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
255 static const DECLARE_TLV_DB_SCALE(drc_qr_tlv
, 1200, 600, 0);
256 static const DECLARE_TLV_DB_SCALE(drc_startup_tlv
, -300, 50, 0);
258 static const DECLARE_TLV_DB_SCALE(eq_tlv
, -1200, 100, 0);
260 static const DECLARE_TLV_DB_SCALE(in_tlv
, -600, 600, 0);
261 static const DECLARE_TLV_DB_SCALE(dac_tlv
, -7200, 75, 1);
262 static const DECLARE_TLV_DB_SCALE(out_tlv
, -5700, 100, 0);
264 static const char *drc_high_text
[] = {
273 static const struct soc_enum drc_high
=
274 SOC_ENUM_SINGLE(WM9081_DRC_3
, 3, 6, drc_high_text
);
276 static const char *drc_low_text
[] = {
284 static const struct soc_enum drc_low
=
285 SOC_ENUM_SINGLE(WM9081_DRC_3
, 0, 5, drc_low_text
);
287 static const char *drc_atk_text
[] = {
302 static const struct soc_enum drc_atk
=
303 SOC_ENUM_SINGLE(WM9081_DRC_2
, 12, 12, drc_atk_text
);
305 static const char *drc_dcy_text
[] = {
317 static const struct soc_enum drc_dcy
=
318 SOC_ENUM_SINGLE(WM9081_DRC_2
, 8, 9, drc_dcy_text
);
320 static const char *drc_qr_dcy_text
[] = {
326 static const struct soc_enum drc_qr_dcy
=
327 SOC_ENUM_SINGLE(WM9081_DRC_2
, 4, 3, drc_qr_dcy_text
);
329 static const char *dac_deemph_text
[] = {
336 static const struct soc_enum dac_deemph
=
337 SOC_ENUM_SINGLE(WM9081_DAC_DIGITAL_2
, 1, 4, dac_deemph_text
);
339 static const char *speaker_mode_text
[] = {
344 static const struct soc_enum speaker_mode
=
345 SOC_ENUM_SINGLE(WM9081_ANALOGUE_SPEAKER_2
, 6, 2, speaker_mode_text
);
347 static int speaker_mode_get(struct snd_kcontrol
*kcontrol
,
348 struct snd_ctl_elem_value
*ucontrol
)
350 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
353 reg
= snd_soc_read(codec
, WM9081_ANALOGUE_SPEAKER_2
);
354 if (reg
& WM9081_SPK_MODE
)
355 ucontrol
->value
.integer
.value
[0] = 1;
357 ucontrol
->value
.integer
.value
[0] = 0;
363 * Stop any attempts to change speaker mode while the speaker is enabled.
365 * We also have some special anti-pop controls dependent on speaker
366 * mode which must be changed along with the mode.
368 static int speaker_mode_put(struct snd_kcontrol
*kcontrol
,
369 struct snd_ctl_elem_value
*ucontrol
)
371 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
372 unsigned int reg_pwr
= snd_soc_read(codec
, WM9081_POWER_MANAGEMENT
);
373 unsigned int reg2
= snd_soc_read(codec
, WM9081_ANALOGUE_SPEAKER_2
);
375 /* Are we changing anything? */
376 if (ucontrol
->value
.integer
.value
[0] ==
377 ((reg2
& WM9081_SPK_MODE
) != 0))
380 /* Don't try to change modes while enabled */
381 if (reg_pwr
& WM9081_SPK_ENA
)
384 if (ucontrol
->value
.integer
.value
[0]) {
386 reg2
&= ~(WM9081_SPK_INV_MUTE
| WM9081_OUT_SPK_CTRL
);
387 reg2
|= WM9081_SPK_MODE
;
390 reg2
|= WM9081_SPK_INV_MUTE
| WM9081_OUT_SPK_CTRL
;
391 reg2
&= ~WM9081_SPK_MODE
;
394 snd_soc_write(codec
, WM9081_ANALOGUE_SPEAKER_2
, reg2
);
399 static const struct snd_kcontrol_new wm9081_snd_controls
[] = {
400 SOC_SINGLE_TLV("IN1 Volume", WM9081_ANALOGUE_MIXER
, 1, 1, 1, in_tlv
),
401 SOC_SINGLE_TLV("IN2 Volume", WM9081_ANALOGUE_MIXER
, 3, 1, 1, in_tlv
),
403 SOC_SINGLE_TLV("Playback Volume", WM9081_DAC_DIGITAL_1
, 1, 96, 0, dac_tlv
),
405 SOC_SINGLE("LINEOUT Switch", WM9081_ANALOGUE_LINEOUT
, 7, 1, 1),
406 SOC_SINGLE("LINEOUT ZC Switch", WM9081_ANALOGUE_LINEOUT
, 6, 1, 0),
407 SOC_SINGLE_TLV("LINEOUT Volume", WM9081_ANALOGUE_LINEOUT
, 0, 63, 0, out_tlv
),
409 SOC_SINGLE("DRC Switch", WM9081_DRC_1
, 15, 1, 0),
410 SOC_ENUM("DRC High Slope", drc_high
),
411 SOC_ENUM("DRC Low Slope", drc_low
),
412 SOC_SINGLE_TLV("DRC Input Volume", WM9081_DRC_4
, 5, 60, 1, drc_in_tlv
),
413 SOC_SINGLE_TLV("DRC Output Volume", WM9081_DRC_4
, 0, 30, 1, drc_out_tlv
),
414 SOC_SINGLE_TLV("DRC Minimum Volume", WM9081_DRC_2
, 2, 3, 1, drc_min_tlv
),
415 SOC_SINGLE_TLV("DRC Maximum Volume", WM9081_DRC_2
, 0, 3, 0, drc_max_tlv
),
416 SOC_ENUM("DRC Attack", drc_atk
),
417 SOC_ENUM("DRC Decay", drc_dcy
),
418 SOC_SINGLE("DRC Quick Release Switch", WM9081_DRC_1
, 2, 1, 0),
419 SOC_SINGLE_TLV("DRC Quick Release Volume", WM9081_DRC_2
, 6, 3, 0, drc_qr_tlv
),
420 SOC_ENUM("DRC Quick Release Decay", drc_qr_dcy
),
421 SOC_SINGLE_TLV("DRC Startup Volume", WM9081_DRC_1
, 6, 18, 0, drc_startup_tlv
),
423 SOC_SINGLE("EQ Switch", WM9081_EQ_1
, 0, 1, 0),
425 SOC_SINGLE("Speaker DC Volume", WM9081_ANALOGUE_SPEAKER_1
, 3, 5, 0),
426 SOC_SINGLE("Speaker AC Volume", WM9081_ANALOGUE_SPEAKER_1
, 0, 5, 0),
427 SOC_SINGLE("Speaker Switch", WM9081_ANALOGUE_SPEAKER_PGA
, 7, 1, 1),
428 SOC_SINGLE("Speaker ZC Switch", WM9081_ANALOGUE_SPEAKER_PGA
, 6, 1, 0),
429 SOC_SINGLE_TLV("Speaker Volume", WM9081_ANALOGUE_SPEAKER_PGA
, 0, 63, 0,
431 SOC_ENUM("DAC Deemphasis", dac_deemph
),
432 SOC_ENUM_EXT("Speaker Mode", speaker_mode
, speaker_mode_get
, speaker_mode_put
),
435 static const struct snd_kcontrol_new wm9081_eq_controls
[] = {
436 SOC_SINGLE_TLV("EQ1 Volume", WM9081_EQ_1
, 11, 24, 0, eq_tlv
),
437 SOC_SINGLE_TLV("EQ2 Volume", WM9081_EQ_1
, 6, 24, 0, eq_tlv
),
438 SOC_SINGLE_TLV("EQ3 Volume", WM9081_EQ_1
, 1, 24, 0, eq_tlv
),
439 SOC_SINGLE_TLV("EQ4 Volume", WM9081_EQ_2
, 11, 24, 0, eq_tlv
),
440 SOC_SINGLE_TLV("EQ5 Volume", WM9081_EQ_2
, 6, 24, 0, eq_tlv
),
443 static const struct snd_kcontrol_new mixer
[] = {
444 SOC_DAPM_SINGLE("IN1 Switch", WM9081_ANALOGUE_MIXER
, 0, 1, 0),
445 SOC_DAPM_SINGLE("IN2 Switch", WM9081_ANALOGUE_MIXER
, 2, 1, 0),
446 SOC_DAPM_SINGLE("Playback Switch", WM9081_ANALOGUE_MIXER
, 4, 1, 0),
457 /* The size in bits of the FLL divide multiplied by 10
458 * to allow rounding later */
459 #define FIXED_FLL_SIZE ((1 << 16) * 10)
468 { 64000, 128000, 3, 8 },
469 { 128000, 256000, 2, 4 },
470 { 256000, 1000000, 1, 2 },
471 { 1000000, 13500000, 0, 1 },
474 static int fll_factors(struct _fll_div
*fll_div
, unsigned int Fref
,
478 unsigned int K
, Ndiv
, Nmod
, target
;
482 /* Fref must be <=13.5MHz */
484 while ((Fref
/ div
) > 13500000) {
488 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
493 fll_div
->fll_clk_ref_div
= div
/ 2;
495 pr_debug("Fref=%u Fout=%u\n", Fref
, Fout
);
497 /* Apply the division for our remaining calculations */
500 /* Fvco should be 90-100MHz; don't check the upper bound */
503 while (target
< 90000000) {
507 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
512 fll_div
->fll_outdiv
= div
;
514 pr_debug("Fvco=%dHz\n", target
);
516 /* Find an appropriate FLL_FRATIO and factor it out of the target */
517 for (i
= 0; i
< ARRAY_SIZE(fll_fratios
); i
++) {
518 if (fll_fratios
[i
].min
<= Fref
&& Fref
<= fll_fratios
[i
].max
) {
519 fll_div
->fll_fratio
= fll_fratios
[i
].fll_fratio
;
520 target
/= fll_fratios
[i
].ratio
;
524 if (i
== ARRAY_SIZE(fll_fratios
)) {
525 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref
);
529 /* Now, calculate N.K */
530 Ndiv
= target
/ Fref
;
533 Nmod
= target
% Fref
;
534 pr_debug("Nmod=%d\n", Nmod
);
536 /* Calculate fractional part - scale up so we can round. */
537 Kpart
= FIXED_FLL_SIZE
* (long long)Nmod
;
541 K
= Kpart
& 0xFFFFFFFF;
546 /* Move down to proper range now rounding is done */
549 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
550 fll_div
->n
, fll_div
->k
,
551 fll_div
->fll_fratio
, fll_div
->fll_outdiv
,
552 fll_div
->fll_clk_ref_div
);
557 static int wm9081_set_fll(struct snd_soc_codec
*codec
, int fll_id
,
558 unsigned int Fref
, unsigned int Fout
)
560 struct wm9081_priv
*wm9081
= snd_soc_codec_get_drvdata(codec
);
561 u16 reg1
, reg4
, reg5
;
562 struct _fll_div fll_div
;
567 if (Fref
== wm9081
->fll_fref
&& Fout
== wm9081
->fll_fout
)
570 /* Disable the FLL */
572 dev_dbg(codec
->dev
, "FLL disabled\n");
573 wm9081
->fll_fref
= 0;
574 wm9081
->fll_fout
= 0;
579 ret
= fll_factors(&fll_div
, Fref
, Fout
);
583 reg5
= snd_soc_read(codec
, WM9081_FLL_CONTROL_5
);
584 reg5
&= ~WM9081_FLL_CLK_SRC_MASK
;
587 case WM9081_SYSCLK_FLL_MCLK
:
592 dev_err(codec
->dev
, "Unknown FLL ID %d\n", fll_id
);
596 /* Disable CLK_SYS while we reconfigure */
597 clk_sys_reg
= snd_soc_read(codec
, WM9081_CLOCK_CONTROL_3
);
598 if (clk_sys_reg
& WM9081_CLK_SYS_ENA
)
599 snd_soc_write(codec
, WM9081_CLOCK_CONTROL_3
,
600 clk_sys_reg
& ~WM9081_CLK_SYS_ENA
);
602 /* Any FLL configuration change requires that the FLL be
604 reg1
= snd_soc_read(codec
, WM9081_FLL_CONTROL_1
);
605 reg1
&= ~WM9081_FLL_ENA
;
606 snd_soc_write(codec
, WM9081_FLL_CONTROL_1
, reg1
);
608 /* Apply the configuration */
610 reg1
|= WM9081_FLL_FRAC_MASK
;
612 reg1
&= ~WM9081_FLL_FRAC_MASK
;
613 snd_soc_write(codec
, WM9081_FLL_CONTROL_1
, reg1
);
615 snd_soc_write(codec
, WM9081_FLL_CONTROL_2
,
616 (fll_div
.fll_outdiv
<< WM9081_FLL_OUTDIV_SHIFT
) |
617 (fll_div
.fll_fratio
<< WM9081_FLL_FRATIO_SHIFT
));
618 snd_soc_write(codec
, WM9081_FLL_CONTROL_3
, fll_div
.k
);
620 reg4
= snd_soc_read(codec
, WM9081_FLL_CONTROL_4
);
621 reg4
&= ~WM9081_FLL_N_MASK
;
622 reg4
|= fll_div
.n
<< WM9081_FLL_N_SHIFT
;
623 snd_soc_write(codec
, WM9081_FLL_CONTROL_4
, reg4
);
625 reg5
&= ~WM9081_FLL_CLK_REF_DIV_MASK
;
626 reg5
|= fll_div
.fll_clk_ref_div
<< WM9081_FLL_CLK_REF_DIV_SHIFT
;
627 snd_soc_write(codec
, WM9081_FLL_CONTROL_5
, reg5
);
629 /* Set gain to the recommended value */
630 snd_soc_update_bits(codec
, WM9081_FLL_CONTROL_4
,
631 WM9081_FLL_GAIN_MASK
, 0);
634 snd_soc_write(codec
, WM9081_FLL_CONTROL_1
, reg1
| WM9081_FLL_ENA
);
636 /* Then bring CLK_SYS up again if it was disabled */
637 if (clk_sys_reg
& WM9081_CLK_SYS_ENA
)
638 snd_soc_write(codec
, WM9081_CLOCK_CONTROL_3
, clk_sys_reg
);
640 dev_dbg(codec
->dev
, "FLL enabled at %dHz->%dHz\n", Fref
, Fout
);
642 wm9081
->fll_fref
= Fref
;
643 wm9081
->fll_fout
= Fout
;
648 static int configure_clock(struct snd_soc_codec
*codec
)
650 struct wm9081_priv
*wm9081
= snd_soc_codec_get_drvdata(codec
);
651 int new_sysclk
, i
, target
;
657 switch (wm9081
->sysclk_source
) {
658 case WM9081_SYSCLK_MCLK
:
659 if (wm9081
->mclk_rate
> 12225000) {
661 wm9081
->sysclk_rate
= wm9081
->mclk_rate
/ 2;
663 wm9081
->sysclk_rate
= wm9081
->mclk_rate
;
665 wm9081_set_fll(codec
, WM9081_SYSCLK_FLL_MCLK
, 0, 0);
668 case WM9081_SYSCLK_FLL_MCLK
:
669 /* If we have a sample rate calculate a CLK_SYS that
670 * gives us a suitable DAC configuration, plus BCLK.
671 * Ideally we would check to see if we can clock
672 * directly from MCLK and only use the FLL if this is
673 * not the case, though care must be taken with free
676 if (wm9081
->master
&& wm9081
->bclk
) {
677 /* Make sure we can generate CLK_SYS and BCLK
678 * and that we've got 3MHz for optimal
680 for (i
= 0; i
< ARRAY_SIZE(clk_sys_rates
); i
++) {
681 target
= wm9081
->fs
* clk_sys_rates
[i
].ratio
;
683 if (target
>= wm9081
->bclk
&&
688 if (i
== ARRAY_SIZE(clk_sys_rates
))
691 } else if (wm9081
->fs
) {
692 for (i
= 0; i
< ARRAY_SIZE(clk_sys_rates
); i
++) {
693 new_sysclk
= clk_sys_rates
[i
].ratio
695 if (new_sysclk
> 3000000)
699 if (i
== ARRAY_SIZE(clk_sys_rates
))
703 new_sysclk
= 12288000;
706 ret
= wm9081_set_fll(codec
, WM9081_SYSCLK_FLL_MCLK
,
707 wm9081
->mclk_rate
, new_sysclk
);
709 wm9081
->sysclk_rate
= new_sysclk
;
711 /* Switch SYSCLK over to FLL */
714 wm9081
->sysclk_rate
= wm9081
->mclk_rate
;
722 reg
= snd_soc_read(codec
, WM9081_CLOCK_CONTROL_1
);
724 reg
|= WM9081_MCLKDIV2
;
726 reg
&= ~WM9081_MCLKDIV2
;
727 snd_soc_write(codec
, WM9081_CLOCK_CONTROL_1
, reg
);
729 reg
= snd_soc_read(codec
, WM9081_CLOCK_CONTROL_3
);
731 reg
|= WM9081_CLK_SRC_SEL
;
733 reg
&= ~WM9081_CLK_SRC_SEL
;
734 snd_soc_write(codec
, WM9081_CLOCK_CONTROL_3
, reg
);
736 dev_dbg(codec
->dev
, "CLK_SYS is %dHz\n", wm9081
->sysclk_rate
);
741 static int clk_sys_event(struct snd_soc_dapm_widget
*w
,
742 struct snd_kcontrol
*kcontrol
, int event
)
744 struct snd_soc_codec
*codec
= w
->codec
;
745 struct wm9081_priv
*wm9081
= snd_soc_codec_get_drvdata(codec
);
747 /* This should be done on init() for bypass paths */
748 switch (wm9081
->sysclk_source
) {
749 case WM9081_SYSCLK_MCLK
:
750 dev_dbg(codec
->dev
, "Using %dHz MCLK\n", wm9081
->mclk_rate
);
752 case WM9081_SYSCLK_FLL_MCLK
:
753 dev_dbg(codec
->dev
, "Using %dHz MCLK with FLL\n",
757 dev_err(codec
->dev
, "System clock not configured\n");
762 case SND_SOC_DAPM_PRE_PMU
:
763 configure_clock(codec
);
766 case SND_SOC_DAPM_POST_PMD
:
767 /* Disable the FLL if it's running */
768 wm9081_set_fll(codec
, 0, 0, 0);
775 static const struct snd_soc_dapm_widget wm9081_dapm_widgets
[] = {
776 SND_SOC_DAPM_INPUT("IN1"),
777 SND_SOC_DAPM_INPUT("IN2"),
779 SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM9081_POWER_MANAGEMENT
, 0, 0),
781 SND_SOC_DAPM_MIXER_NAMED_CTL("Mixer", SND_SOC_NOPM
, 0, 0,
782 mixer
, ARRAY_SIZE(mixer
)),
784 SND_SOC_DAPM_PGA("LINEOUT PGA", WM9081_POWER_MANAGEMENT
, 4, 0, NULL
, 0),
786 SND_SOC_DAPM_PGA("Speaker PGA", WM9081_POWER_MANAGEMENT
, 2, 0, NULL
, 0),
787 SND_SOC_DAPM_OUT_DRV("Speaker", WM9081_POWER_MANAGEMENT
, 1, 0, NULL
, 0),
789 SND_SOC_DAPM_OUTPUT("LINEOUT"),
790 SND_SOC_DAPM_OUTPUT("SPKN"),
791 SND_SOC_DAPM_OUTPUT("SPKP"),
793 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM9081_CLOCK_CONTROL_3
, 0, 0, clk_sys_event
,
794 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
795 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM9081_CLOCK_CONTROL_3
, 1, 0, NULL
, 0),
796 SND_SOC_DAPM_SUPPLY("TOCLK", WM9081_CLOCK_CONTROL_3
, 2, 0, NULL
, 0),
797 SND_SOC_DAPM_SUPPLY("TSENSE", WM9081_POWER_MANAGEMENT
, 7, 0, NULL
, 0),
801 static const struct snd_soc_dapm_route wm9081_audio_paths
[] = {
802 { "DAC", NULL
, "CLK_SYS" },
803 { "DAC", NULL
, "CLK_DSP" },
805 { "Mixer", "IN1 Switch", "IN1" },
806 { "Mixer", "IN2 Switch", "IN2" },
807 { "Mixer", "Playback Switch", "DAC" },
809 { "LINEOUT PGA", NULL
, "Mixer" },
810 { "LINEOUT PGA", NULL
, "TOCLK" },
811 { "LINEOUT PGA", NULL
, "CLK_SYS" },
813 { "LINEOUT", NULL
, "LINEOUT PGA" },
815 { "Speaker PGA", NULL
, "Mixer" },
816 { "Speaker PGA", NULL
, "TOCLK" },
817 { "Speaker PGA", NULL
, "CLK_SYS" },
819 { "Speaker", NULL
, "Speaker PGA" },
820 { "Speaker", NULL
, "TSENSE" },
822 { "SPKN", NULL
, "Speaker" },
823 { "SPKP", NULL
, "Speaker" },
826 static int wm9081_set_bias_level(struct snd_soc_codec
*codec
,
827 enum snd_soc_bias_level level
)
830 case SND_SOC_BIAS_ON
:
833 case SND_SOC_BIAS_PREPARE
:
835 snd_soc_update_bits(codec
, WM9081_VMID_CONTROL
,
836 WM9081_VMID_SEL_MASK
, 0x2);
838 /* Normal bias current */
839 snd_soc_update_bits(codec
, WM9081_BIAS_CONTROL_1
,
840 WM9081_STBY_BIAS_ENA
, 0);
843 case SND_SOC_BIAS_STANDBY
:
844 /* Initial cold start */
845 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
846 /* Disable LINEOUT discharge */
847 snd_soc_update_bits(codec
, WM9081_ANTI_POP_CONTROL
,
848 WM9081_LINEOUT_DISCH
, 0);
850 /* Select startup bias source */
851 snd_soc_update_bits(codec
, WM9081_BIAS_CONTROL_1
,
852 WM9081_BIAS_SRC
| WM9081_BIAS_ENA
,
853 WM9081_BIAS_SRC
| WM9081_BIAS_ENA
);
855 /* VMID 2*4k; Soft VMID ramp enable */
856 snd_soc_update_bits(codec
, WM9081_VMID_CONTROL
,
858 WM9081_VMID_SEL_MASK
,
859 WM9081_VMID_RAMP
| 0x6);
863 /* Normal bias enable & soft start off */
864 snd_soc_update_bits(codec
, WM9081_VMID_CONTROL
,
865 WM9081_VMID_RAMP
, 0);
867 /* Standard bias source */
868 snd_soc_update_bits(codec
, WM9081_BIAS_CONTROL_1
,
873 snd_soc_update_bits(codec
, WM9081_VMID_CONTROL
,
874 WM9081_VMID_SEL_MASK
, 0x04);
876 /* Standby bias current on */
877 snd_soc_update_bits(codec
, WM9081_BIAS_CONTROL_1
,
878 WM9081_STBY_BIAS_ENA
,
879 WM9081_STBY_BIAS_ENA
);
882 case SND_SOC_BIAS_OFF
:
883 /* Startup bias source and disable bias */
884 snd_soc_update_bits(codec
, WM9081_BIAS_CONTROL_1
,
885 WM9081_BIAS_SRC
| WM9081_BIAS_ENA
,
888 /* Disable VMID with soft ramping */
889 snd_soc_update_bits(codec
, WM9081_VMID_CONTROL
,
890 WM9081_VMID_RAMP
| WM9081_VMID_SEL_MASK
,
893 /* Actively discharge LINEOUT */
894 snd_soc_update_bits(codec
, WM9081_ANTI_POP_CONTROL
,
895 WM9081_LINEOUT_DISCH
,
896 WM9081_LINEOUT_DISCH
);
900 codec
->dapm
.bias_level
= level
;
905 static int wm9081_set_dai_fmt(struct snd_soc_dai
*dai
,
908 struct snd_soc_codec
*codec
= dai
->codec
;
909 struct wm9081_priv
*wm9081
= snd_soc_codec_get_drvdata(codec
);
910 unsigned int aif2
= snd_soc_read(codec
, WM9081_AUDIO_INTERFACE_2
);
912 aif2
&= ~(WM9081_AIF_BCLK_INV
| WM9081_AIF_LRCLK_INV
|
913 WM9081_BCLK_DIR
| WM9081_LRCLK_DIR
| WM9081_AIF_FMT_MASK
);
915 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
916 case SND_SOC_DAIFMT_CBS_CFS
:
919 case SND_SOC_DAIFMT_CBS_CFM
:
920 aif2
|= WM9081_LRCLK_DIR
;
923 case SND_SOC_DAIFMT_CBM_CFS
:
924 aif2
|= WM9081_BCLK_DIR
;
927 case SND_SOC_DAIFMT_CBM_CFM
:
928 aif2
|= WM9081_LRCLK_DIR
| WM9081_BCLK_DIR
;
935 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
936 case SND_SOC_DAIFMT_DSP_B
:
937 aif2
|= WM9081_AIF_LRCLK_INV
;
938 case SND_SOC_DAIFMT_DSP_A
:
941 case SND_SOC_DAIFMT_I2S
:
944 case SND_SOC_DAIFMT_RIGHT_J
:
946 case SND_SOC_DAIFMT_LEFT_J
:
953 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
954 case SND_SOC_DAIFMT_DSP_A
:
955 case SND_SOC_DAIFMT_DSP_B
:
956 /* frame inversion not valid for DSP modes */
957 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
958 case SND_SOC_DAIFMT_NB_NF
:
960 case SND_SOC_DAIFMT_IB_NF
:
961 aif2
|= WM9081_AIF_BCLK_INV
;
968 case SND_SOC_DAIFMT_I2S
:
969 case SND_SOC_DAIFMT_RIGHT_J
:
970 case SND_SOC_DAIFMT_LEFT_J
:
971 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
972 case SND_SOC_DAIFMT_NB_NF
:
974 case SND_SOC_DAIFMT_IB_IF
:
975 aif2
|= WM9081_AIF_BCLK_INV
| WM9081_AIF_LRCLK_INV
;
977 case SND_SOC_DAIFMT_IB_NF
:
978 aif2
|= WM9081_AIF_BCLK_INV
;
980 case SND_SOC_DAIFMT_NB_IF
:
981 aif2
|= WM9081_AIF_LRCLK_INV
;
991 snd_soc_write(codec
, WM9081_AUDIO_INTERFACE_2
, aif2
);
996 static int wm9081_hw_params(struct snd_pcm_substream
*substream
,
997 struct snd_pcm_hw_params
*params
,
998 struct snd_soc_dai
*dai
)
1000 struct snd_soc_codec
*codec
= dai
->codec
;
1001 struct wm9081_priv
*wm9081
= snd_soc_codec_get_drvdata(codec
);
1002 int ret
, i
, best
, best_val
, cur_val
;
1003 unsigned int clk_ctrl2
, aif1
, aif2
, aif3
, aif4
;
1005 clk_ctrl2
= snd_soc_read(codec
, WM9081_CLOCK_CONTROL_2
);
1006 clk_ctrl2
&= ~(WM9081_CLK_SYS_RATE_MASK
| WM9081_SAMPLE_RATE_MASK
);
1008 aif1
= snd_soc_read(codec
, WM9081_AUDIO_INTERFACE_1
);
1010 aif2
= snd_soc_read(codec
, WM9081_AUDIO_INTERFACE_2
);
1011 aif2
&= ~WM9081_AIF_WL_MASK
;
1013 aif3
= snd_soc_read(codec
, WM9081_AUDIO_INTERFACE_3
);
1014 aif3
&= ~WM9081_BCLK_DIV_MASK
;
1016 aif4
= snd_soc_read(codec
, WM9081_AUDIO_INTERFACE_4
);
1017 aif4
&= ~WM9081_LRCLK_RATE_MASK
;
1019 wm9081
->fs
= params_rate(params
);
1021 if (wm9081
->tdm_width
) {
1022 /* If TDM is set up then that fixes our BCLK. */
1023 int slots
= ((aif1
& WM9081_AIFDAC_TDM_MODE_MASK
) >>
1024 WM9081_AIFDAC_TDM_MODE_SHIFT
) + 1;
1026 wm9081
->bclk
= wm9081
->fs
* wm9081
->tdm_width
* slots
;
1028 /* Otherwise work out a BCLK from the sample size */
1029 wm9081
->bclk
= 2 * wm9081
->fs
;
1031 switch (params_format(params
)) {
1032 case SNDRV_PCM_FORMAT_S16_LE
:
1035 case SNDRV_PCM_FORMAT_S20_3LE
:
1039 case SNDRV_PCM_FORMAT_S24_LE
:
1043 case SNDRV_PCM_FORMAT_S32_LE
:
1052 dev_dbg(codec
->dev
, "Target BCLK is %dHz\n", wm9081
->bclk
);
1054 ret
= configure_clock(codec
);
1058 /* Select nearest CLK_SYS_RATE */
1060 best_val
= abs((wm9081
->sysclk_rate
/ clk_sys_rates
[0].ratio
)
1062 for (i
= 1; i
< ARRAY_SIZE(clk_sys_rates
); i
++) {
1063 cur_val
= abs((wm9081
->sysclk_rate
/
1064 clk_sys_rates
[i
].ratio
) - wm9081
->fs
);
1065 if (cur_val
< best_val
) {
1070 dev_dbg(codec
->dev
, "Selected CLK_SYS_RATIO of %d\n",
1071 clk_sys_rates
[best
].ratio
);
1072 clk_ctrl2
|= (clk_sys_rates
[best
].clk_sys_rate
1073 << WM9081_CLK_SYS_RATE_SHIFT
);
1077 best_val
= abs(wm9081
->fs
- sample_rates
[0].rate
);
1078 for (i
= 1; i
< ARRAY_SIZE(sample_rates
); i
++) {
1080 cur_val
= abs(wm9081
->fs
- sample_rates
[i
].rate
);
1081 if (cur_val
< best_val
) {
1086 dev_dbg(codec
->dev
, "Selected SAMPLE_RATE of %dHz\n",
1087 sample_rates
[best
].rate
);
1088 clk_ctrl2
|= (sample_rates
[best
].sample_rate
1089 << WM9081_SAMPLE_RATE_SHIFT
);
1094 for (i
= 0; i
< ARRAY_SIZE(bclk_divs
); i
++) {
1095 cur_val
= ((wm9081
->sysclk_rate
* 10) / bclk_divs
[i
].div
)
1097 if (cur_val
< 0) /* Table is sorted */
1099 if (cur_val
< best_val
) {
1104 wm9081
->bclk
= (wm9081
->sysclk_rate
* 10) / bclk_divs
[best
].div
;
1105 dev_dbg(codec
->dev
, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1106 bclk_divs
[best
].div
, wm9081
->bclk
);
1107 aif3
|= bclk_divs
[best
].bclk_div
;
1109 /* LRCLK is a simple fraction of BCLK */
1110 dev_dbg(codec
->dev
, "LRCLK_RATE is %d\n", wm9081
->bclk
/ wm9081
->fs
);
1111 aif4
|= wm9081
->bclk
/ wm9081
->fs
;
1113 /* Apply a ReTune Mobile configuration if it's in use */
1114 if (wm9081
->pdata
.num_retune_configs
) {
1115 struct wm9081_pdata
*pdata
= &wm9081
->pdata
;
1116 struct wm9081_retune_mobile_setting
*s
;
1120 best_val
= abs(pdata
->retune_configs
[0].rate
- wm9081
->fs
);
1121 for (i
= 0; i
< pdata
->num_retune_configs
; i
++) {
1122 cur_val
= abs(pdata
->retune_configs
[i
].rate
-
1124 if (cur_val
< best_val
) {
1129 s
= &pdata
->retune_configs
[best
];
1131 dev_dbg(codec
->dev
, "ReTune Mobile %s tuned for %dHz\n",
1134 /* If the EQ is enabled then disable it while we write out */
1135 eq1
= snd_soc_read(codec
, WM9081_EQ_1
) & WM9081_EQ_ENA
;
1136 if (eq1
& WM9081_EQ_ENA
)
1137 snd_soc_write(codec
, WM9081_EQ_1
, 0);
1139 /* Write out the other values */
1140 for (i
= 1; i
< ARRAY_SIZE(s
->config
); i
++)
1141 snd_soc_write(codec
, WM9081_EQ_1
+ i
, s
->config
[i
]);
1143 eq1
|= (s
->config
[0] & ~WM9081_EQ_ENA
);
1144 snd_soc_write(codec
, WM9081_EQ_1
, eq1
);
1147 snd_soc_write(codec
, WM9081_CLOCK_CONTROL_2
, clk_ctrl2
);
1148 snd_soc_write(codec
, WM9081_AUDIO_INTERFACE_2
, aif2
);
1149 snd_soc_write(codec
, WM9081_AUDIO_INTERFACE_3
, aif3
);
1150 snd_soc_write(codec
, WM9081_AUDIO_INTERFACE_4
, aif4
);
1155 static int wm9081_digital_mute(struct snd_soc_dai
*codec_dai
, int mute
)
1157 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1160 reg
= snd_soc_read(codec
, WM9081_DAC_DIGITAL_2
);
1163 reg
|= WM9081_DAC_MUTE
;
1165 reg
&= ~WM9081_DAC_MUTE
;
1167 snd_soc_write(codec
, WM9081_DAC_DIGITAL_2
, reg
);
1172 static int wm9081_set_sysclk(struct snd_soc_codec
*codec
, int clk_id
,
1173 int source
, unsigned int freq
, int dir
)
1175 struct wm9081_priv
*wm9081
= snd_soc_codec_get_drvdata(codec
);
1178 case WM9081_SYSCLK_MCLK
:
1179 case WM9081_SYSCLK_FLL_MCLK
:
1180 wm9081
->sysclk_source
= clk_id
;
1181 wm9081
->mclk_rate
= freq
;
1191 static int wm9081_set_tdm_slot(struct snd_soc_dai
*dai
,
1192 unsigned int tx_mask
, unsigned int rx_mask
, int slots
, int slot_width
)
1194 struct snd_soc_codec
*codec
= dai
->codec
;
1195 struct wm9081_priv
*wm9081
= snd_soc_codec_get_drvdata(codec
);
1196 unsigned int aif1
= snd_soc_read(codec
, WM9081_AUDIO_INTERFACE_1
);
1198 aif1
&= ~(WM9081_AIFDAC_TDM_SLOT_MASK
| WM9081_AIFDAC_TDM_MODE_MASK
);
1200 if (slots
< 0 || slots
> 4)
1203 wm9081
->tdm_width
= slot_width
;
1208 aif1
|= (slots
- 1) << WM9081_AIFDAC_TDM_MODE_SHIFT
;
1226 snd_soc_write(codec
, WM9081_AUDIO_INTERFACE_1
, aif1
);
1231 #define WM9081_RATES SNDRV_PCM_RATE_8000_96000
1233 #define WM9081_FORMATS \
1234 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1235 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1237 static struct snd_soc_dai_ops wm9081_dai_ops
= {
1238 .hw_params
= wm9081_hw_params
,
1239 .set_fmt
= wm9081_set_dai_fmt
,
1240 .digital_mute
= wm9081_digital_mute
,
1241 .set_tdm_slot
= wm9081_set_tdm_slot
,
1244 /* We report two channels because the CODEC processes a stereo signal, even
1245 * though it is only capable of handling a mono output.
1247 static struct snd_soc_dai_driver wm9081_dai
= {
1248 .name
= "wm9081-hifi",
1250 .stream_name
= "HiFi Playback",
1253 .rates
= WM9081_RATES
,
1254 .formats
= WM9081_FORMATS
,
1256 .ops
= &wm9081_dai_ops
,
1259 static int wm9081_probe(struct snd_soc_codec
*codec
)
1261 struct wm9081_priv
*wm9081
= snd_soc_codec_get_drvdata(codec
);
1265 codec
->control_data
= wm9081
->regmap
;
1267 ret
= snd_soc_codec_set_cache_io(codec
, 8, 16, SND_SOC_REGMAP
);
1269 dev_err(codec
->dev
, "Failed to set cache I/O: %d\n", ret
);
1274 if (wm9081
->pdata
.irq_high
)
1275 reg
|= WM9081_IRQ_POL
;
1276 if (!wm9081
->pdata
.irq_cmos
)
1277 reg
|= WM9081_IRQ_OP_CTRL
;
1278 snd_soc_update_bits(codec
, WM9081_INTERRUPT_CONTROL
,
1279 WM9081_IRQ_POL
| WM9081_IRQ_OP_CTRL
, reg
);
1281 wm9081_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1283 /* Enable zero cross by default */
1284 snd_soc_update_bits(codec
, WM9081_ANALOGUE_LINEOUT
,
1285 WM9081_LINEOUTZC
, WM9081_LINEOUTZC
);
1286 snd_soc_update_bits(codec
, WM9081_ANALOGUE_SPEAKER_PGA
,
1287 WM9081_SPKPGAZC
, WM9081_SPKPGAZC
);
1289 if (!wm9081
->pdata
.num_retune_configs
) {
1291 "No ReTune Mobile data, using normal EQ\n");
1292 snd_soc_add_controls(codec
, wm9081_eq_controls
,
1293 ARRAY_SIZE(wm9081_eq_controls
));
1299 static int wm9081_remove(struct snd_soc_codec
*codec
)
1301 wm9081_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1306 static int wm9081_suspend(struct snd_soc_codec
*codec
, pm_message_t state
)
1308 wm9081_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1313 static int wm9081_resume(struct snd_soc_codec
*codec
)
1315 struct wm9081_priv
*wm9081
= snd_soc_codec_get_drvdata(codec
);
1317 regcache_sync(wm9081
->regmap
);
1319 wm9081_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1324 #define wm9081_suspend NULL
1325 #define wm9081_resume NULL
1328 static struct snd_soc_codec_driver soc_codec_dev_wm9081
= {
1329 .probe
= wm9081_probe
,
1330 .remove
= wm9081_remove
,
1331 .suspend
= wm9081_suspend
,
1332 .resume
= wm9081_resume
,
1334 .set_sysclk
= wm9081_set_sysclk
,
1335 .set_bias_level
= wm9081_set_bias_level
,
1337 .controls
= wm9081_snd_controls
,
1338 .num_controls
= ARRAY_SIZE(wm9081_snd_controls
),
1339 .dapm_widgets
= wm9081_dapm_widgets
,
1340 .num_dapm_widgets
= ARRAY_SIZE(wm9081_dapm_widgets
),
1341 .dapm_routes
= wm9081_audio_paths
,
1342 .num_dapm_routes
= ARRAY_SIZE(wm9081_audio_paths
),
1345 static const struct regmap_config wm9081_regmap
= {
1349 .max_register
= WM9081_MAX_REGISTER
,
1350 .reg_defaults
= wm9081_reg
,
1351 .num_reg_defaults
= ARRAY_SIZE(wm9081_reg
),
1352 .volatile_reg
= wm9081_volatile_register
,
1353 .readable_reg
= wm9081_readable_register
,
1354 .cache_type
= REGCACHE_RBTREE
,
1357 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1358 static __devinit
int wm9081_i2c_probe(struct i2c_client
*i2c
,
1359 const struct i2c_device_id
*id
)
1361 struct wm9081_priv
*wm9081
;
1365 wm9081
= kzalloc(sizeof(struct wm9081_priv
), GFP_KERNEL
);
1369 i2c_set_clientdata(i2c
, wm9081
);
1371 wm9081
->regmap
= regmap_init_i2c(i2c
, &wm9081_regmap
);
1372 if (IS_ERR(wm9081
->regmap
)) {
1373 ret
= PTR_ERR(wm9081
->regmap
);
1374 dev_err(&i2c
->dev
, "regmap_init() failed: %d\n", ret
);
1378 ret
= regmap_read(wm9081
->regmap
, WM9081_SOFTWARE_RESET
, ®
);
1380 dev_err(&i2c
->dev
, "Failed to read chip ID: %d\n", ret
);
1383 if (reg
!= 0x9081) {
1384 dev_err(&i2c
->dev
, "Device is not a WM9081: ID=0x%x\n", reg
);
1389 ret
= wm9081_reset(wm9081
->regmap
);
1391 dev_err(&i2c
->dev
, "Failed to issue reset\n");
1395 if (dev_get_platdata(&i2c
->dev
))
1396 memcpy(&wm9081
->pdata
, dev_get_platdata(&i2c
->dev
),
1397 sizeof(wm9081
->pdata
));
1399 ret
= snd_soc_register_codec(&i2c
->dev
,
1400 &soc_codec_dev_wm9081
, &wm9081_dai
, 1);
1407 regmap_exit(wm9081
->regmap
);
1414 static __devexit
int wm9081_i2c_remove(struct i2c_client
*client
)
1416 struct wm9081_priv
*wm9081
= i2c_get_clientdata(client
);
1418 snd_soc_unregister_codec(&client
->dev
);
1419 regmap_exit(wm9081
->regmap
);
1420 kfree(i2c_get_clientdata(client
));
1424 static const struct i2c_device_id wm9081_i2c_id
[] = {
1428 MODULE_DEVICE_TABLE(i2c
, wm9081_i2c_id
);
1430 static struct i2c_driver wm9081_i2c_driver
= {
1433 .owner
= THIS_MODULE
,
1435 .probe
= wm9081_i2c_probe
,
1436 .remove
= __devexit_p(wm9081_i2c_remove
),
1437 .id_table
= wm9081_i2c_id
,
1441 static int __init
wm9081_modinit(void)
1444 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1445 ret
= i2c_add_driver(&wm9081_i2c_driver
);
1447 printk(KERN_ERR
"Failed to register WM9081 I2C driver: %d\n",
1453 module_init(wm9081_modinit
);
1455 static void __exit
wm9081_exit(void)
1457 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1458 i2c_del_driver(&wm9081_i2c_driver
);
1461 module_exit(wm9081_exit
);
1464 MODULE_DESCRIPTION("ASoC WM9081 driver");
1465 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1466 MODULE_LICENSE("GPL");