2 * wm_adsp.c -- Wolfson ADSP support
4 * Copyright 2012 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/firmware.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/regmap.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/slab.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
27 #include <sound/jack.h>
28 #include <sound/initval.h>
29 #include <sound/tlv.h>
31 #include <linux/mfd/arizona/registers.h>
35 #define adsp_crit(_dsp, fmt, ...) \
36 dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
37 #define adsp_err(_dsp, fmt, ...) \
38 dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
39 #define adsp_warn(_dsp, fmt, ...) \
40 dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
41 #define adsp_info(_dsp, fmt, ...) \
42 dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
43 #define adsp_dbg(_dsp, fmt, ...) \
44 dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
46 #define ADSP1_CONTROL_1 0x00
47 #define ADSP1_CONTROL_2 0x02
48 #define ADSP1_CONTROL_3 0x03
49 #define ADSP1_CONTROL_4 0x04
50 #define ADSP1_CONTROL_5 0x06
51 #define ADSP1_CONTROL_6 0x07
52 #define ADSP1_CONTROL_7 0x08
53 #define ADSP1_CONTROL_8 0x09
54 #define ADSP1_CONTROL_9 0x0A
55 #define ADSP1_CONTROL_10 0x0B
56 #define ADSP1_CONTROL_11 0x0C
57 #define ADSP1_CONTROL_12 0x0D
58 #define ADSP1_CONTROL_13 0x0F
59 #define ADSP1_CONTROL_14 0x10
60 #define ADSP1_CONTROL_15 0x11
61 #define ADSP1_CONTROL_16 0x12
62 #define ADSP1_CONTROL_17 0x13
63 #define ADSP1_CONTROL_18 0x14
64 #define ADSP1_CONTROL_19 0x16
65 #define ADSP1_CONTROL_20 0x17
66 #define ADSP1_CONTROL_21 0x18
67 #define ADSP1_CONTROL_22 0x1A
68 #define ADSP1_CONTROL_23 0x1B
69 #define ADSP1_CONTROL_24 0x1C
70 #define ADSP1_CONTROL_25 0x1E
71 #define ADSP1_CONTROL_26 0x20
72 #define ADSP1_CONTROL_27 0x21
73 #define ADSP1_CONTROL_28 0x22
74 #define ADSP1_CONTROL_29 0x23
75 #define ADSP1_CONTROL_30 0x24
76 #define ADSP1_CONTROL_31 0x26
81 #define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
82 #define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
83 #define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
89 #define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
90 #define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
91 #define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
92 #define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
93 #define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
94 #define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
95 #define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
96 #define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
97 #define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
98 #define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
99 #define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
100 #define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
101 #define ADSP1_START 0x0001 /* DSP1_START */
102 #define ADSP1_START_MASK 0x0001 /* DSP1_START */
103 #define ADSP1_START_SHIFT 0 /* DSP1_START */
104 #define ADSP1_START_WIDTH 1 /* DSP1_START */
106 #define ADSP2_CONTROL 0
107 #define ADSP2_CLOCKING 1
108 #define ADSP2_STATUS1 4
114 #define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
115 #define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
116 #define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
117 #define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
118 #define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
119 #define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
120 #define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
121 #define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
122 #define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
123 #define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
124 #define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
125 #define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
126 #define ADSP2_START 0x0001 /* DSP1_START */
127 #define ADSP2_START_MASK 0x0001 /* DSP1_START */
128 #define ADSP2_START_SHIFT 0 /* DSP1_START */
129 #define ADSP2_START_WIDTH 1 /* DSP1_START */
134 #define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
135 #define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
136 #define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
141 #define ADSP2_RAM_RDY 0x0001
142 #define ADSP2_RAM_RDY_MASK 0x0001
143 #define ADSP2_RAM_RDY_SHIFT 0
144 #define ADSP2_RAM_RDY_WIDTH 1
146 #define WM_ADSP_NUM_FW 3
148 static const char *wm_adsp_fw_text
[WM_ADSP_NUM_FW
] = {
149 "MBC/VSS", "Tx", "Rx ANC"
154 } wm_adsp_fw
[WM_ADSP_NUM_FW
] = {
155 { .file
= "mbc-vss" },
157 { .file
= "rx-anc" },
160 static int wm_adsp_fw_get(struct snd_kcontrol
*kcontrol
,
161 struct snd_ctl_elem_value
*ucontrol
)
163 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
164 struct soc_enum
*e
= (struct soc_enum
*)kcontrol
->private_value
;
165 struct wm_adsp
*adsp
= snd_soc_codec_get_drvdata(codec
);
167 ucontrol
->value
.integer
.value
[0] = adsp
[e
->shift_l
].fw
;
172 static int wm_adsp_fw_put(struct snd_kcontrol
*kcontrol
,
173 struct snd_ctl_elem_value
*ucontrol
)
175 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
176 struct soc_enum
*e
= (struct soc_enum
*)kcontrol
->private_value
;
177 struct wm_adsp
*adsp
= snd_soc_codec_get_drvdata(codec
);
179 if (ucontrol
->value
.integer
.value
[0] == adsp
[e
->shift_l
].fw
)
182 if (ucontrol
->value
.integer
.value
[0] >= WM_ADSP_NUM_FW
)
185 if (adsp
[e
->shift_l
].running
)
188 adsp
->fw
= ucontrol
->value
.integer
.value
[0];
193 static const struct soc_enum wm_adsp_fw_enum
[] = {
194 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text
), wm_adsp_fw_text
),
195 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text
), wm_adsp_fw_text
),
196 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text
), wm_adsp_fw_text
),
197 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text
), wm_adsp_fw_text
),
200 const struct snd_kcontrol_new wm_adsp_fw_controls
[] = {
201 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum
[0],
202 wm_adsp_fw_get
, wm_adsp_fw_put
),
203 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum
[1],
204 wm_adsp_fw_get
, wm_adsp_fw_put
),
205 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum
[2],
206 wm_adsp_fw_get
, wm_adsp_fw_put
),
207 SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum
[3],
208 wm_adsp_fw_get
, wm_adsp_fw_put
),
210 EXPORT_SYMBOL_GPL(wm_adsp_fw_controls
);
212 static struct wm_adsp_region
const *wm_adsp_find_region(struct wm_adsp
*dsp
,
217 for (i
= 0; i
< dsp
->num_mems
; i
++)
218 if (dsp
->mem
[i
].type
== type
)
224 static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region
const *region
,
227 switch (region
->type
) {
229 return region
->base
+ (offset
* 3);
231 return region
->base
+ (offset
* 2);
233 return region
->base
+ (offset
* 2);
235 return region
->base
+ (offset
* 2);
237 return region
->base
+ (offset
* 2);
239 WARN_ON(NULL
!= "Unknown memory region type");
244 static int wm_adsp_load(struct wm_adsp
*dsp
)
246 const struct firmware
*firmware
;
247 struct regmap
*regmap
= dsp
->regmap
;
248 unsigned int pos
= 0;
249 const struct wmfw_header
*header
;
250 const struct wmfw_adsp1_sizes
*adsp1_sizes
;
251 const struct wmfw_adsp2_sizes
*adsp2_sizes
;
252 const struct wmfw_footer
*footer
;
253 const struct wmfw_region
*region
;
254 const struct wm_adsp_region
*mem
;
255 const char *region_name
;
259 int ret
, offset
, type
, sizes
;
261 file
= kzalloc(PAGE_SIZE
, GFP_KERNEL
);
265 snprintf(file
, PAGE_SIZE
, "%s-dsp%d-%s.wmfw", dsp
->part
, dsp
->num
,
266 wm_adsp_fw
[dsp
->fw
].file
);
267 file
[PAGE_SIZE
- 1] = '\0';
269 ret
= request_firmware(&firmware
, file
, dsp
->dev
);
271 adsp_err(dsp
, "Failed to request '%s'\n", file
);
276 pos
= sizeof(*header
) + sizeof(*adsp1_sizes
) + sizeof(*footer
);
277 if (pos
>= firmware
->size
) {
278 adsp_err(dsp
, "%s: file too short, %zu bytes\n",
279 file
, firmware
->size
);
283 header
= (void*)&firmware
->data
[0];
285 if (memcmp(&header
->magic
[0], "WMFW", 4) != 0) {
286 adsp_err(dsp
, "%s: invalid magic\n", file
);
290 if (header
->ver
!= 0) {
291 adsp_err(dsp
, "%s: unknown file format %d\n",
296 if (header
->core
!= dsp
->type
) {
297 adsp_err(dsp
, "%s: invalid core %d != %d\n",
298 file
, header
->core
, dsp
->type
);
304 pos
= sizeof(*header
) + sizeof(*adsp1_sizes
) + sizeof(*footer
);
305 adsp1_sizes
= (void *)&(header
[1]);
306 footer
= (void *)&(adsp1_sizes
[1]);
307 sizes
= sizeof(*adsp1_sizes
);
309 adsp_dbg(dsp
, "%s: %d DM, %d PM, %d ZM\n",
310 file
, le32_to_cpu(adsp1_sizes
->dm
),
311 le32_to_cpu(adsp1_sizes
->pm
),
312 le32_to_cpu(adsp1_sizes
->zm
));
316 pos
= sizeof(*header
) + sizeof(*adsp2_sizes
) + sizeof(*footer
);
317 adsp2_sizes
= (void *)&(header
[1]);
318 footer
= (void *)&(adsp2_sizes
[1]);
319 sizes
= sizeof(*adsp2_sizes
);
321 adsp_dbg(dsp
, "%s: %d XM, %d YM %d PM, %d ZM\n",
322 file
, le32_to_cpu(adsp2_sizes
->xm
),
323 le32_to_cpu(adsp2_sizes
->ym
),
324 le32_to_cpu(adsp2_sizes
->pm
),
325 le32_to_cpu(adsp2_sizes
->zm
));
329 BUG_ON(NULL
== "Unknown DSP type");
333 if (le32_to_cpu(header
->len
) != sizeof(*header
) +
334 sizes
+ sizeof(*footer
)) {
335 adsp_err(dsp
, "%s: unexpected header length %d\n",
336 file
, le32_to_cpu(header
->len
));
340 adsp_dbg(dsp
, "%s: timestamp %llu\n", file
,
341 le64_to_cpu(footer
->timestamp
));
343 while (pos
< firmware
->size
&&
344 pos
- firmware
->size
> sizeof(*region
)) {
345 region
= (void *)&(firmware
->data
[pos
]);
346 region_name
= "Unknown";
349 offset
= le32_to_cpu(region
->offset
) & 0xffffff;
350 type
= be32_to_cpu(region
->type
) & 0xff;
351 mem
= wm_adsp_find_region(dsp
, type
);
355 region_name
= "Firmware name";
356 text
= kzalloc(le32_to_cpu(region
->len
) + 1,
360 region_name
= "Information";
361 text
= kzalloc(le32_to_cpu(region
->len
) + 1,
365 region_name
= "Absolute";
371 reg
= wm_adsp_region_to_reg(mem
, offset
);
376 reg
= wm_adsp_region_to_reg(mem
, offset
);
381 reg
= wm_adsp_region_to_reg(mem
, offset
);
386 reg
= wm_adsp_region_to_reg(mem
, offset
);
391 reg
= wm_adsp_region_to_reg(mem
, offset
);
395 "%s.%d: Unknown region type %x at %d(%x)\n",
396 file
, regions
, type
, pos
, pos
);
400 adsp_dbg(dsp
, "%s.%d: %d bytes at %d in %s\n", file
,
401 regions
, le32_to_cpu(region
->len
), offset
,
405 memcpy(text
, region
->data
, le32_to_cpu(region
->len
));
406 adsp_info(dsp
, "%s: %s\n", file
, text
);
411 ret
= regmap_raw_write(regmap
, reg
, region
->data
,
412 le32_to_cpu(region
->len
));
415 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
417 le32_to_cpu(region
->len
), offset
,
423 pos
+= le32_to_cpu(region
->len
) + sizeof(*region
);
427 if (pos
> firmware
->size
)
428 adsp_warn(dsp
, "%s.%d: %zu bytes at end of file\n",
429 file
, regions
, pos
- firmware
->size
);
432 release_firmware(firmware
);
439 static int wm_adsp_setup_algs(struct wm_adsp
*dsp
)
441 struct regmap
*regmap
= dsp
->regmap
;
442 struct wmfw_adsp1_id_hdr adsp1_id
;
443 struct wmfw_adsp2_id_hdr adsp2_id
;
444 struct wmfw_adsp1_alg_hdr
*adsp1_alg
;
445 struct wmfw_adsp2_alg_hdr
*adsp2_alg
;
447 struct wm_adsp_alg_region
*region
;
448 const struct wm_adsp_region
*mem
;
449 unsigned int pos
, term
;
450 size_t algs
, buf_size
;
456 mem
= wm_adsp_find_region(dsp
, WMFW_ADSP1_DM
);
459 mem
= wm_adsp_find_region(dsp
, WMFW_ADSP2_XM
);
473 ret
= regmap_raw_read(regmap
, mem
->base
, &adsp1_id
,
476 adsp_err(dsp
, "Failed to read algorithm info: %d\n",
482 buf_size
= sizeof(adsp1_id
);
484 algs
= be32_to_cpu(adsp1_id
.algs
);
485 adsp_info(dsp
, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
486 be32_to_cpu(adsp1_id
.fw
.id
),
487 (be32_to_cpu(adsp1_id
.fw
.ver
) & 0xff0000) >> 16,
488 (be32_to_cpu(adsp1_id
.fw
.ver
) & 0xff00) >> 8,
489 be32_to_cpu(adsp1_id
.fw
.ver
) & 0xff,
492 pos
= sizeof(adsp1_id
) / 2;
493 term
= pos
+ ((sizeof(*adsp1_alg
) * algs
) / 2);
497 ret
= regmap_raw_read(regmap
, mem
->base
, &adsp2_id
,
500 adsp_err(dsp
, "Failed to read algorithm info: %d\n",
506 buf_size
= sizeof(adsp2_id
);
508 algs
= be32_to_cpu(adsp2_id
.algs
);
509 adsp_info(dsp
, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
510 be32_to_cpu(adsp2_id
.fw
.id
),
511 (be32_to_cpu(adsp2_id
.fw
.ver
) & 0xff0000) >> 16,
512 (be32_to_cpu(adsp2_id
.fw
.ver
) & 0xff00) >> 8,
513 be32_to_cpu(adsp2_id
.fw
.ver
) & 0xff,
516 pos
= sizeof(adsp2_id
) / 2;
517 term
= pos
+ ((sizeof(*adsp2_alg
) * algs
) / 2);
521 BUG_ON(NULL
== "Unknown DSP type");
526 adsp_err(dsp
, "No algorithms\n");
531 adsp_err(dsp
, "Algorithm count %zx excessive\n", algs
);
532 print_hex_dump_bytes(dev_name(dsp
->dev
), DUMP_PREFIX_OFFSET
,
537 /* Read the terminator first to validate the length */
538 ret
= regmap_raw_read(regmap
, mem
->base
+ term
, &val
, sizeof(val
));
540 adsp_err(dsp
, "Failed to read algorithm list end: %d\n",
545 if (be32_to_cpu(val
) != 0xbedead)
546 adsp_warn(dsp
, "Algorithm list end %x 0x%x != 0xbeadead\n",
547 term
, be32_to_cpu(val
));
549 alg
= kzalloc((term
- pos
) * 2, GFP_KERNEL
);
553 ret
= regmap_raw_read(regmap
, mem
->base
+ pos
, alg
, (term
- pos
) * 2);
555 adsp_err(dsp
, "Failed to read algorithm list: %d\n",
563 for (i
= 0; i
< algs
; i
++) {
566 adsp_info(dsp
, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
567 i
, be32_to_cpu(adsp1_alg
[i
].alg
.id
),
568 (be32_to_cpu(adsp1_alg
[i
].alg
.ver
) & 0xff0000) >> 16,
569 (be32_to_cpu(adsp1_alg
[i
].alg
.ver
) & 0xff00) >> 8,
570 be32_to_cpu(adsp1_alg
[i
].alg
.ver
) & 0xff,
571 be32_to_cpu(adsp1_alg
[i
].dm
),
572 be32_to_cpu(adsp1_alg
[i
].zm
));
574 if (adsp1_alg
[i
].dm
) {
575 region
= kzalloc(sizeof(*region
), GFP_KERNEL
);
578 region
->type
= WMFW_ADSP1_DM
;
579 region
->alg
= be32_to_cpu(adsp1_alg
[i
].alg
.id
);
580 region
->base
= be32_to_cpu(adsp1_alg
[i
].dm
);
581 list_add_tail(®ion
->list
,
585 if (adsp1_alg
[i
].zm
) {
586 region
= kzalloc(sizeof(*region
), GFP_KERNEL
);
589 region
->type
= WMFW_ADSP1_ZM
;
590 region
->alg
= be32_to_cpu(adsp1_alg
[i
].alg
.id
);
591 region
->base
= be32_to_cpu(adsp1_alg
[i
].zm
);
592 list_add_tail(®ion
->list
,
599 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
600 i
, be32_to_cpu(adsp2_alg
[i
].alg
.id
),
601 (be32_to_cpu(adsp2_alg
[i
].alg
.ver
) & 0xff0000) >> 16,
602 (be32_to_cpu(adsp2_alg
[i
].alg
.ver
) & 0xff00) >> 8,
603 be32_to_cpu(adsp2_alg
[i
].alg
.ver
) & 0xff,
604 be32_to_cpu(adsp2_alg
[i
].xm
),
605 be32_to_cpu(adsp2_alg
[i
].ym
),
606 be32_to_cpu(adsp2_alg
[i
].zm
));
608 if (adsp2_alg
[i
].xm
) {
609 region
= kzalloc(sizeof(*region
), GFP_KERNEL
);
612 region
->type
= WMFW_ADSP2_XM
;
613 region
->alg
= be32_to_cpu(adsp2_alg
[i
].alg
.id
);
614 region
->base
= be32_to_cpu(adsp2_alg
[i
].xm
);
615 list_add_tail(®ion
->list
,
619 if (adsp2_alg
[i
].ym
) {
620 region
= kzalloc(sizeof(*region
), GFP_KERNEL
);
623 region
->type
= WMFW_ADSP2_YM
;
624 region
->alg
= be32_to_cpu(adsp2_alg
[i
].alg
.id
);
625 region
->base
= be32_to_cpu(adsp2_alg
[i
].ym
);
626 list_add_tail(®ion
->list
,
630 if (adsp2_alg
[i
].zm
) {
631 region
= kzalloc(sizeof(*region
), GFP_KERNEL
);
634 region
->type
= WMFW_ADSP2_ZM
;
635 region
->alg
= be32_to_cpu(adsp2_alg
[i
].alg
.id
);
636 region
->base
= be32_to_cpu(adsp2_alg
[i
].zm
);
637 list_add_tail(®ion
->list
,
649 static int wm_adsp_load_coeff(struct wm_adsp
*dsp
)
651 struct regmap
*regmap
= dsp
->regmap
;
652 struct wmfw_coeff_hdr
*hdr
;
653 struct wmfw_coeff_item
*blk
;
654 const struct firmware
*firmware
;
655 const struct wm_adsp_region
*mem
;
656 struct wm_adsp_alg_region
*alg_region
;
657 const char *region_name
;
658 int ret
, pos
, blocks
, type
, offset
, reg
;
661 file
= kzalloc(PAGE_SIZE
, GFP_KERNEL
);
665 snprintf(file
, PAGE_SIZE
, "%s-dsp%d-%s.bin", dsp
->part
, dsp
->num
,
666 wm_adsp_fw
[dsp
->fw
].file
);
667 file
[PAGE_SIZE
- 1] = '\0';
669 ret
= request_firmware(&firmware
, file
, dsp
->dev
);
671 adsp_warn(dsp
, "Failed to request '%s'\n", file
);
677 if (sizeof(*hdr
) >= firmware
->size
) {
678 adsp_err(dsp
, "%s: file too short, %zu bytes\n",
679 file
, firmware
->size
);
683 hdr
= (void*)&firmware
->data
[0];
684 if (memcmp(hdr
->magic
, "WMDR", 4) != 0) {
685 adsp_err(dsp
, "%s: invalid magic\n", file
);
689 adsp_dbg(dsp
, "%s: v%d.%d.%d\n", file
,
690 (le32_to_cpu(hdr
->ver
) >> 16) & 0xff,
691 (le32_to_cpu(hdr
->ver
) >> 8) & 0xff,
692 le32_to_cpu(hdr
->ver
) & 0xff);
694 pos
= le32_to_cpu(hdr
->len
);
697 while (pos
< firmware
->size
&&
698 pos
- firmware
->size
> sizeof(*blk
)) {
699 blk
= (void*)(&firmware
->data
[pos
]);
701 type
= be32_to_cpu(blk
->type
) & 0xff;
702 offset
= le32_to_cpu(blk
->offset
) & 0xffffff;
704 adsp_dbg(dsp
, "%s.%d: %x v%d.%d.%d\n",
705 file
, blocks
, le32_to_cpu(blk
->id
),
706 (le32_to_cpu(blk
->ver
) >> 16) & 0xff,
707 (le32_to_cpu(blk
->ver
) >> 8) & 0xff,
708 le32_to_cpu(blk
->ver
) & 0xff);
709 adsp_dbg(dsp
, "%s.%d: %d bytes at 0x%x in %x\n",
710 file
, blocks
, le32_to_cpu(blk
->len
), offset
, type
);
713 region_name
= "Unknown";
719 region_name
= "register";
727 adsp_dbg(dsp
, "%s.%d: %d bytes in %x for %x\n",
728 file
, blocks
, le32_to_cpu(blk
->len
),
729 type
, le32_to_cpu(blk
->id
));
731 mem
= wm_adsp_find_region(dsp
, type
);
733 adsp_err(dsp
, "No base for region %x\n", type
);
738 list_for_each_entry(alg_region
,
739 &dsp
->alg_regions
, list
) {
740 if (le32_to_cpu(blk
->id
) == alg_region
->alg
&&
741 type
== alg_region
->type
) {
742 reg
= alg_region
->base
+ offset
;
743 reg
= wm_adsp_region_to_reg(mem
,
749 adsp_err(dsp
, "No %x for algorithm %x\n",
750 type
, le32_to_cpu(blk
->id
));
754 adsp_err(dsp
, "Unknown region type %x\n", type
);
759 ret
= regmap_raw_write(regmap
, reg
, blk
->data
,
760 le32_to_cpu(blk
->len
));
763 "%s.%d: Failed to write to %x in %s\n",
764 file
, blocks
, reg
, region_name
);
768 pos
+= le32_to_cpu(blk
->len
) + sizeof(*blk
);
772 if (pos
> firmware
->size
)
773 adsp_warn(dsp
, "%s.%d: %zu bytes at end of file\n",
774 file
, blocks
, pos
- firmware
->size
);
777 release_firmware(firmware
);
783 int wm_adsp1_event(struct snd_soc_dapm_widget
*w
,
784 struct snd_kcontrol
*kcontrol
,
787 struct snd_soc_codec
*codec
= w
->codec
;
788 struct wm_adsp
*dsps
= snd_soc_codec_get_drvdata(codec
);
789 struct wm_adsp
*dsp
= &dsps
[w
->shift
];
793 case SND_SOC_DAPM_POST_PMU
:
794 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP1_CONTROL_30
,
795 ADSP1_SYS_ENA
, ADSP1_SYS_ENA
);
797 ret
= wm_adsp_load(dsp
);
801 ret
= wm_adsp_setup_algs(dsp
);
805 ret
= wm_adsp_load_coeff(dsp
);
809 /* Start the core running */
810 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP1_CONTROL_30
,
811 ADSP1_CORE_ENA
| ADSP1_START
,
812 ADSP1_CORE_ENA
| ADSP1_START
);
815 case SND_SOC_DAPM_PRE_PMD
:
817 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP1_CONTROL_30
,
818 ADSP1_CORE_ENA
| ADSP1_START
, 0);
820 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP1_CONTROL_19
,
821 ADSP1_WDMA_BUFFER_LENGTH_MASK
, 0);
823 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP1_CONTROL_30
,
834 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP1_CONTROL_30
,
838 EXPORT_SYMBOL_GPL(wm_adsp1_event
);
840 static int wm_adsp2_ena(struct wm_adsp
*dsp
)
845 ret
= regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP2_CONTROL
,
846 ADSP2_SYS_ENA
, ADSP2_SYS_ENA
);
850 /* Wait for the RAM to start, should be near instantaneous */
853 ret
= regmap_read(dsp
->regmap
, dsp
->base
+ ADSP2_STATUS1
,
857 } while (!(val
& ADSP2_RAM_RDY
) && ++count
< 10);
859 if (!(val
& ADSP2_RAM_RDY
)) {
860 adsp_err(dsp
, "Failed to start DSP RAM\n");
864 adsp_dbg(dsp
, "RAM ready after %d polls\n", count
);
865 adsp_info(dsp
, "RAM ready after %d polls\n", count
);
870 int wm_adsp2_event(struct snd_soc_dapm_widget
*w
,
871 struct snd_kcontrol
*kcontrol
, int event
)
873 struct snd_soc_codec
*codec
= w
->codec
;
874 struct wm_adsp
*dsps
= snd_soc_codec_get_drvdata(codec
);
875 struct wm_adsp
*dsp
= &dsps
[w
->shift
];
876 struct wm_adsp_alg_region
*alg_region
;
881 case SND_SOC_DAPM_POST_PMU
:
883 * For simplicity set the DSP clock rate to be the
884 * SYSCLK rate rather than making it configurable.
886 ret
= regmap_read(dsp
->regmap
, ARIZONA_SYSTEM_CLOCK_1
, &val
);
888 adsp_err(dsp
, "Failed to read SYSCLK state: %d\n",
892 val
= (val
& ARIZONA_SYSCLK_FREQ_MASK
)
893 >> ARIZONA_SYSCLK_FREQ_SHIFT
;
895 ret
= regmap_update_bits(dsp
->regmap
,
896 dsp
->base
+ ADSP2_CLOCKING
,
897 ADSP2_CLK_SEL_MASK
, val
);
899 adsp_err(dsp
, "Failed to set clock rate: %d\n",
905 ret
= regmap_read(dsp
->regmap
,
906 dsp
->base
+ ADSP2_CLOCKING
, &val
);
909 "Failed to read clocking: %d\n", ret
);
913 if ((val
& ADSP2_CLK_SEL_MASK
) >= 3) {
914 ret
= regulator_enable(dsp
->dvfs
);
917 "Failed to enable supply: %d\n",
922 ret
= regulator_set_voltage(dsp
->dvfs
,
927 "Failed to raise supply: %d\n",
934 ret
= wm_adsp2_ena(dsp
);
938 ret
= wm_adsp_load(dsp
);
942 ret
= wm_adsp_setup_algs(dsp
);
946 ret
= wm_adsp_load_coeff(dsp
);
950 ret
= regmap_update_bits(dsp
->regmap
,
951 dsp
->base
+ ADSP2_CONTROL
,
952 ADSP2_CORE_ENA
| ADSP2_START
,
953 ADSP2_CORE_ENA
| ADSP2_START
);
960 case SND_SOC_DAPM_PRE_PMD
:
961 dsp
->running
= false;
963 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP2_CONTROL
,
964 ADSP2_SYS_ENA
| ADSP2_CORE_ENA
|
968 ret
= regulator_set_voltage(dsp
->dvfs
, 1200000,
972 "Failed to lower supply: %d\n",
975 ret
= regulator_disable(dsp
->dvfs
);
978 "Failed to enable supply: %d\n",
982 while (!list_empty(&dsp
->alg_regions
)) {
983 alg_region
= list_first_entry(&dsp
->alg_regions
,
984 struct wm_adsp_alg_region
,
986 list_del(&alg_region
->list
);
997 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP2_CONTROL
,
998 ADSP2_SYS_ENA
| ADSP2_CORE_ENA
| ADSP2_START
, 0);
1001 EXPORT_SYMBOL_GPL(wm_adsp2_event
);
1003 int wm_adsp2_init(struct wm_adsp
*adsp
, bool dvfs
)
1008 * Disable the DSP memory by default when in reset for a small
1011 ret
= regmap_update_bits(adsp
->regmap
, adsp
->base
+ ADSP2_CONTROL
,
1014 adsp_err(adsp
, "Failed to clear memory retention: %d\n", ret
);
1018 INIT_LIST_HEAD(&adsp
->alg_regions
);
1021 adsp
->dvfs
= devm_regulator_get(adsp
->dev
, "DCVDD");
1022 if (IS_ERR(adsp
->dvfs
)) {
1023 ret
= PTR_ERR(adsp
->dvfs
);
1024 dev_err(adsp
->dev
, "Failed to get DCVDD: %d\n", ret
);
1028 ret
= regulator_enable(adsp
->dvfs
);
1030 dev_err(adsp
->dev
, "Failed to enable DCVDD: %d\n",
1035 ret
= regulator_set_voltage(adsp
->dvfs
, 1200000, 1800000);
1037 dev_err(adsp
->dev
, "Failed to initialise DVFS: %d\n",
1042 ret
= regulator_disable(adsp
->dvfs
);
1044 dev_err(adsp
->dev
, "Failed to disable DCVDD: %d\n",
1052 EXPORT_SYMBOL_GPL(wm_adsp2_init
);