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[deliverable/linux.git] / sound / soc / codecs / wm_adsp.c
1 /*
2 * wm_adsp.c -- Wolfson ADSP support
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/firmware.h>
18 #include <linux/pm.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/regmap.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/slab.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
27 #include <sound/jack.h>
28 #include <sound/initval.h>
29 #include <sound/tlv.h>
30
31 #include <linux/mfd/arizona/registers.h>
32
33 #include "wm_adsp.h"
34
35 #define adsp_crit(_dsp, fmt, ...) \
36 dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
37 #define adsp_err(_dsp, fmt, ...) \
38 dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
39 #define adsp_warn(_dsp, fmt, ...) \
40 dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
41 #define adsp_info(_dsp, fmt, ...) \
42 dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
43 #define adsp_dbg(_dsp, fmt, ...) \
44 dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
45
46 #define ADSP1_CONTROL_1 0x00
47 #define ADSP1_CONTROL_2 0x02
48 #define ADSP1_CONTROL_3 0x03
49 #define ADSP1_CONTROL_4 0x04
50 #define ADSP1_CONTROL_5 0x06
51 #define ADSP1_CONTROL_6 0x07
52 #define ADSP1_CONTROL_7 0x08
53 #define ADSP1_CONTROL_8 0x09
54 #define ADSP1_CONTROL_9 0x0A
55 #define ADSP1_CONTROL_10 0x0B
56 #define ADSP1_CONTROL_11 0x0C
57 #define ADSP1_CONTROL_12 0x0D
58 #define ADSP1_CONTROL_13 0x0F
59 #define ADSP1_CONTROL_14 0x10
60 #define ADSP1_CONTROL_15 0x11
61 #define ADSP1_CONTROL_16 0x12
62 #define ADSP1_CONTROL_17 0x13
63 #define ADSP1_CONTROL_18 0x14
64 #define ADSP1_CONTROL_19 0x16
65 #define ADSP1_CONTROL_20 0x17
66 #define ADSP1_CONTROL_21 0x18
67 #define ADSP1_CONTROL_22 0x1A
68 #define ADSP1_CONTROL_23 0x1B
69 #define ADSP1_CONTROL_24 0x1C
70 #define ADSP1_CONTROL_25 0x1E
71 #define ADSP1_CONTROL_26 0x20
72 #define ADSP1_CONTROL_27 0x21
73 #define ADSP1_CONTROL_28 0x22
74 #define ADSP1_CONTROL_29 0x23
75 #define ADSP1_CONTROL_30 0x24
76 #define ADSP1_CONTROL_31 0x26
77
78 /*
79 * ADSP1 Control 19
80 */
81 #define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
82 #define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
83 #define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
84
85
86 /*
87 * ADSP1 Control 30
88 */
89 #define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
90 #define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
91 #define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
92 #define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
93 #define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
94 #define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
95 #define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
96 #define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
97 #define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
98 #define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
99 #define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
100 #define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
101 #define ADSP1_START 0x0001 /* DSP1_START */
102 #define ADSP1_START_MASK 0x0001 /* DSP1_START */
103 #define ADSP1_START_SHIFT 0 /* DSP1_START */
104 #define ADSP1_START_WIDTH 1 /* DSP1_START */
105
106 #define ADSP2_CONTROL 0
107 #define ADSP2_CLOCKING 1
108 #define ADSP2_STATUS1 4
109
110 /*
111 * ADSP2 Control
112 */
113
114 #define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
115 #define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
116 #define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
117 #define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
118 #define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
119 #define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
120 #define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
121 #define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
122 #define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
123 #define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
124 #define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
125 #define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
126 #define ADSP2_START 0x0001 /* DSP1_START */
127 #define ADSP2_START_MASK 0x0001 /* DSP1_START */
128 #define ADSP2_START_SHIFT 0 /* DSP1_START */
129 #define ADSP2_START_WIDTH 1 /* DSP1_START */
130
131 /*
132 * ADSP2 clocking
133 */
134 #define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
135 #define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
136 #define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
137
138 /*
139 * ADSP2 Status 1
140 */
141 #define ADSP2_RAM_RDY 0x0001
142 #define ADSP2_RAM_RDY_MASK 0x0001
143 #define ADSP2_RAM_RDY_SHIFT 0
144 #define ADSP2_RAM_RDY_WIDTH 1
145
146
147 static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
148 int type)
149 {
150 int i;
151
152 for (i = 0; i < dsp->num_mems; i++)
153 if (dsp->mem[i].type == type)
154 return &dsp->mem[i];
155
156 return NULL;
157 }
158
159 static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *region,
160 unsigned int offset)
161 {
162 switch (region->type) {
163 case WMFW_ADSP1_PM:
164 return region->base + (offset * 3);
165 case WMFW_ADSP1_DM:
166 return region->base + (offset * 2);
167 case WMFW_ADSP2_XM:
168 return region->base + (offset * 2);
169 case WMFW_ADSP2_YM:
170 return region->base + (offset * 2);
171 case WMFW_ADSP1_ZM:
172 return region->base + (offset * 2);
173 default:
174 WARN_ON(NULL != "Unknown memory region type");
175 return offset;
176 }
177 }
178
179 static int wm_adsp_load(struct wm_adsp *dsp)
180 {
181 const struct firmware *firmware;
182 struct regmap *regmap = dsp->regmap;
183 unsigned int pos = 0;
184 const struct wmfw_header *header;
185 const struct wmfw_adsp1_sizes *adsp1_sizes;
186 const struct wmfw_adsp2_sizes *adsp2_sizes;
187 const struct wmfw_footer *footer;
188 const struct wmfw_region *region;
189 const struct wm_adsp_region *mem;
190 const char *region_name;
191 char *file, *text;
192 unsigned int reg;
193 int regions = 0;
194 int ret, offset, type, sizes;
195
196 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
197 if (file == NULL)
198 return -ENOMEM;
199
200 snprintf(file, PAGE_SIZE, "%s-dsp%d.wmfw", dsp->part, dsp->num);
201 file[PAGE_SIZE - 1] = '\0';
202
203 ret = request_firmware(&firmware, file, dsp->dev);
204 if (ret != 0) {
205 adsp_err(dsp, "Failed to request '%s'\n", file);
206 goto out;
207 }
208 ret = -EINVAL;
209
210 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
211 if (pos >= firmware->size) {
212 adsp_err(dsp, "%s: file too short, %zu bytes\n",
213 file, firmware->size);
214 goto out_fw;
215 }
216
217 header = (void*)&firmware->data[0];
218
219 if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
220 adsp_err(dsp, "%s: invalid magic\n", file);
221 goto out_fw;
222 }
223
224 if (header->ver != 0) {
225 adsp_err(dsp, "%s: unknown file format %d\n",
226 file, header->ver);
227 goto out_fw;
228 }
229
230 if (header->core != dsp->type) {
231 adsp_err(dsp, "%s: invalid core %d != %d\n",
232 file, header->core, dsp->type);
233 goto out_fw;
234 }
235
236 switch (dsp->type) {
237 case WMFW_ADSP1:
238 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
239 adsp1_sizes = (void *)&(header[1]);
240 footer = (void *)&(adsp1_sizes[1]);
241 sizes = sizeof(*adsp1_sizes);
242
243 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n",
244 file, le32_to_cpu(adsp1_sizes->dm),
245 le32_to_cpu(adsp1_sizes->pm),
246 le32_to_cpu(adsp1_sizes->zm));
247 break;
248
249 case WMFW_ADSP2:
250 pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer);
251 adsp2_sizes = (void *)&(header[1]);
252 footer = (void *)&(adsp2_sizes[1]);
253 sizes = sizeof(*adsp2_sizes);
254
255 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n",
256 file, le32_to_cpu(adsp2_sizes->xm),
257 le32_to_cpu(adsp2_sizes->ym),
258 le32_to_cpu(adsp2_sizes->pm),
259 le32_to_cpu(adsp2_sizes->zm));
260 break;
261
262 default:
263 BUG_ON(NULL == "Unknown DSP type");
264 goto out_fw;
265 }
266
267 if (le32_to_cpu(header->len) != sizeof(*header) +
268 sizes + sizeof(*footer)) {
269 adsp_err(dsp, "%s: unexpected header length %d\n",
270 file, le32_to_cpu(header->len));
271 goto out_fw;
272 }
273
274 adsp_dbg(dsp, "%s: timestamp %llu\n", file,
275 le64_to_cpu(footer->timestamp));
276
277 while (pos < firmware->size &&
278 pos - firmware->size > sizeof(*region)) {
279 region = (void *)&(firmware->data[pos]);
280 region_name = "Unknown";
281 reg = 0;
282 text = NULL;
283 offset = le32_to_cpu(region->offset) & 0xffffff;
284 type = be32_to_cpu(region->type) & 0xff;
285 mem = wm_adsp_find_region(dsp, type);
286
287 switch (type) {
288 case WMFW_NAME_TEXT:
289 region_name = "Firmware name";
290 text = kzalloc(le32_to_cpu(region->len) + 1,
291 GFP_KERNEL);
292 break;
293 case WMFW_INFO_TEXT:
294 region_name = "Information";
295 text = kzalloc(le32_to_cpu(region->len) + 1,
296 GFP_KERNEL);
297 break;
298 case WMFW_ABSOLUTE:
299 region_name = "Absolute";
300 reg = offset;
301 break;
302 case WMFW_ADSP1_PM:
303 BUG_ON(!mem);
304 region_name = "PM";
305 reg = wm_adsp_region_to_reg(mem, offset);
306 break;
307 case WMFW_ADSP1_DM:
308 BUG_ON(!mem);
309 region_name = "DM";
310 reg = wm_adsp_region_to_reg(mem, offset);
311 break;
312 case WMFW_ADSP2_XM:
313 BUG_ON(!mem);
314 region_name = "XM";
315 reg = wm_adsp_region_to_reg(mem, offset);
316 break;
317 case WMFW_ADSP2_YM:
318 BUG_ON(!mem);
319 region_name = "YM";
320 reg = wm_adsp_region_to_reg(mem, offset);
321 break;
322 case WMFW_ADSP1_ZM:
323 BUG_ON(!mem);
324 region_name = "ZM";
325 reg = wm_adsp_region_to_reg(mem, offset);
326 break;
327 default:
328 adsp_warn(dsp,
329 "%s.%d: Unknown region type %x at %d(%x)\n",
330 file, regions, type, pos, pos);
331 break;
332 }
333
334 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
335 regions, le32_to_cpu(region->len), offset,
336 region_name);
337
338 if (text) {
339 memcpy(text, region->data, le32_to_cpu(region->len));
340 adsp_info(dsp, "%s: %s\n", file, text);
341 kfree(text);
342 }
343
344 if (reg) {
345 ret = regmap_raw_write(regmap, reg, region->data,
346 le32_to_cpu(region->len));
347 if (ret != 0) {
348 adsp_err(dsp,
349 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
350 file, regions,
351 le32_to_cpu(region->len), offset,
352 region_name, ret);
353 goto out_fw;
354 }
355 }
356
357 pos += le32_to_cpu(region->len) + sizeof(*region);
358 regions++;
359 }
360
361 if (pos > firmware->size)
362 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
363 file, regions, pos - firmware->size);
364
365 out_fw:
366 release_firmware(firmware);
367 out:
368 kfree(file);
369
370 return ret;
371 }
372
373 static int wm_adsp_setup_algs(struct wm_adsp *dsp)
374 {
375 struct regmap *regmap = dsp->regmap;
376 struct wmfw_adsp1_id_hdr adsp1_id;
377 struct wmfw_adsp2_id_hdr adsp2_id;
378 struct wmfw_adsp1_alg_hdr *adsp1_alg;
379 struct wmfw_adsp2_alg_hdr *adsp2_alg;
380 void *alg;
381 const struct wm_adsp_region *mem;
382 unsigned int pos, term;
383 size_t algs;
384 __be32 val;
385 int i, ret;
386
387 switch (dsp->type) {
388 case WMFW_ADSP1:
389 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
390 break;
391 case WMFW_ADSP2:
392 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
393 break;
394 default:
395 mem = NULL;
396 break;
397 }
398
399 if (mem == NULL) {
400 BUG_ON(mem != NULL);
401 return -EINVAL;
402 }
403
404 switch (dsp->type) {
405 case WMFW_ADSP1:
406 ret = regmap_raw_read(regmap, mem->base, &adsp1_id,
407 sizeof(adsp1_id));
408 if (ret != 0) {
409 adsp_err(dsp, "Failed to read algorithm info: %d\n",
410 ret);
411 return ret;
412 }
413
414 algs = be32_to_cpu(adsp1_id.algs);
415 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
416 be32_to_cpu(adsp1_id.fw.id),
417 (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16,
418 (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8,
419 be32_to_cpu(adsp1_id.fw.ver) & 0xff,
420 algs);
421
422 pos = sizeof(adsp1_id) / 2;
423 term = pos + ((sizeof(*adsp1_alg) * algs) / 2);
424 break;
425
426 case WMFW_ADSP2:
427 ret = regmap_raw_read(regmap, mem->base, &adsp2_id,
428 sizeof(adsp2_id));
429 if (ret != 0) {
430 adsp_err(dsp, "Failed to read algorithm info: %d\n",
431 ret);
432 return ret;
433 }
434
435 algs = be32_to_cpu(adsp2_id.algs);
436 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
437 be32_to_cpu(adsp2_id.fw.id),
438 (be32_to_cpu(adsp2_id.fw.ver) & 0xff0000) >> 16,
439 (be32_to_cpu(adsp2_id.fw.ver) & 0xff00) >> 8,
440 be32_to_cpu(adsp2_id.fw.ver) & 0xff,
441 algs);
442
443 pos = sizeof(adsp2_id) / 2;
444 term = pos + ((sizeof(*adsp2_alg) * algs) / 2);
445 break;
446
447 default:
448 BUG_ON(NULL == "Unknown DSP type");
449 return -EINVAL;
450 }
451
452 if (algs == 0) {
453 adsp_err(dsp, "No algorithms\n");
454 return -EINVAL;
455 }
456
457 /* Read the terminator first to validate the length */
458 ret = regmap_raw_read(regmap, mem->base + term, &val, sizeof(val));
459 if (ret != 0) {
460 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
461 ret);
462 return ret;
463 }
464
465 if (be32_to_cpu(val) != 0xbedead)
466 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbeadead\n",
467 term, be32_to_cpu(val));
468
469 alg = kzalloc((term - pos) * 2, GFP_KERNEL);
470 if (!alg)
471 return -ENOMEM;
472
473 ret = regmap_raw_read(regmap, mem->base + pos, alg, (term - pos) * 2);
474 if (ret != 0) {
475 adsp_err(dsp, "Failed to read algorithm list: %d\n",
476 ret);
477 goto out;
478 }
479
480 adsp1_alg = alg;
481 adsp2_alg = alg;
482
483 for (i = 0; i < algs; i++) {
484 switch (dsp->type) {
485 case WMFW_ADSP1:
486 adsp_info(dsp, "%d: ID %x v%d.%d.%d\n",
487 i, be32_to_cpu(adsp1_alg[i].alg.id),
488 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
489 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
490 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff);
491 break;
492
493 case WMFW_ADSP2:
494 adsp_info(dsp, "%d: ID %x v%d.%d.%d\n",
495 i, be32_to_cpu(adsp2_alg[i].alg.id),
496 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
497 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
498 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff);
499 break;
500 }
501 }
502
503 out:
504 kfree(alg);
505 return ret;
506 }
507
508 static int wm_adsp_load_coeff(struct wm_adsp *dsp)
509 {
510 struct regmap *regmap = dsp->regmap;
511 struct wmfw_coeff_hdr *hdr;
512 struct wmfw_coeff_item *blk;
513 const struct firmware *firmware;
514 const char *region_name;
515 int ret, pos, blocks, type, offset, reg;
516 char *file;
517
518 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
519 if (file == NULL)
520 return -ENOMEM;
521
522 snprintf(file, PAGE_SIZE, "%s-dsp%d.bin", dsp->part, dsp->num);
523 file[PAGE_SIZE - 1] = '\0';
524
525 ret = request_firmware(&firmware, file, dsp->dev);
526 if (ret != 0) {
527 adsp_warn(dsp, "Failed to request '%s'\n", file);
528 ret = 0;
529 goto out;
530 }
531 ret = -EINVAL;
532
533 if (sizeof(*hdr) >= firmware->size) {
534 adsp_err(dsp, "%s: file too short, %zu bytes\n",
535 file, firmware->size);
536 goto out_fw;
537 }
538
539 hdr = (void*)&firmware->data[0];
540 if (memcmp(hdr->magic, "WMDR", 4) != 0) {
541 adsp_err(dsp, "%s: invalid magic\n", file);
542 return -EINVAL;
543 }
544
545 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
546 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
547 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
548 le32_to_cpu(hdr->ver) & 0xff);
549
550 pos = le32_to_cpu(hdr->len);
551
552 blocks = 0;
553 while (pos < firmware->size &&
554 pos - firmware->size > sizeof(*blk)) {
555 blk = (void*)(&firmware->data[pos]);
556
557 type = be32_to_cpu(blk->type) & 0xff;
558 offset = le32_to_cpu(blk->offset) & 0xffffff;
559
560 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
561 file, blocks, le32_to_cpu(blk->id),
562 (le32_to_cpu(blk->ver) >> 16) & 0xff,
563 (le32_to_cpu(blk->ver) >> 8) & 0xff,
564 le32_to_cpu(blk->ver) & 0xff);
565 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
566 file, blocks, le32_to_cpu(blk->len), offset, type);
567
568 reg = 0;
569 region_name = "Unknown";
570 switch (type) {
571 case WMFW_NAME_TEXT:
572 case WMFW_INFO_TEXT:
573 break;
574 case WMFW_ABSOLUTE:
575 region_name = "register";
576 reg = offset;
577 break;
578 default:
579 adsp_err(dsp, "Unknown region type %x\n", type);
580 break;
581 }
582
583 if (reg) {
584 ret = regmap_raw_write(regmap, reg, blk->data,
585 le32_to_cpu(blk->len));
586 if (ret != 0) {
587 adsp_err(dsp,
588 "%s.%d: Failed to write to %x in %s\n",
589 file, blocks, reg, region_name);
590 }
591 }
592
593 pos += le32_to_cpu(blk->len) + sizeof(*blk);
594 blocks++;
595 }
596
597 if (pos > firmware->size)
598 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
599 file, blocks, pos - firmware->size);
600
601 out_fw:
602 release_firmware(firmware);
603 out:
604 kfree(file);
605 return 0;
606 }
607
608 int wm_adsp1_event(struct snd_soc_dapm_widget *w,
609 struct snd_kcontrol *kcontrol,
610 int event)
611 {
612 struct snd_soc_codec *codec = w->codec;
613 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
614 struct wm_adsp *dsp = &dsps[w->shift];
615 int ret;
616
617 switch (event) {
618 case SND_SOC_DAPM_POST_PMU:
619 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
620 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
621
622 ret = wm_adsp_load(dsp);
623 if (ret != 0)
624 goto err;
625
626 ret = wm_adsp_setup_algs(dsp);
627 if (ret != 0)
628 goto err;
629
630 ret = wm_adsp_load_coeff(dsp);
631 if (ret != 0)
632 goto err;
633
634 /* Start the core running */
635 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
636 ADSP1_CORE_ENA | ADSP1_START,
637 ADSP1_CORE_ENA | ADSP1_START);
638 break;
639
640 case SND_SOC_DAPM_PRE_PMD:
641 /* Halt the core */
642 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
643 ADSP1_CORE_ENA | ADSP1_START, 0);
644
645 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
646 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
647
648 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
649 ADSP1_SYS_ENA, 0);
650 break;
651
652 default:
653 break;
654 }
655
656 return 0;
657
658 err:
659 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
660 ADSP1_SYS_ENA, 0);
661 return ret;
662 }
663 EXPORT_SYMBOL_GPL(wm_adsp1_event);
664
665 static int wm_adsp2_ena(struct wm_adsp *dsp)
666 {
667 unsigned int val;
668 int ret, count;
669
670 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
671 ADSP2_SYS_ENA, ADSP2_SYS_ENA);
672 if (ret != 0)
673 return ret;
674
675 /* Wait for the RAM to start, should be near instantaneous */
676 count = 0;
677 do {
678 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1,
679 &val);
680 if (ret != 0)
681 return ret;
682 } while (!(val & ADSP2_RAM_RDY) && ++count < 10);
683
684 if (!(val & ADSP2_RAM_RDY)) {
685 adsp_err(dsp, "Failed to start DSP RAM\n");
686 return -EBUSY;
687 }
688
689 adsp_dbg(dsp, "RAM ready after %d polls\n", count);
690 adsp_info(dsp, "RAM ready after %d polls\n", count);
691
692 return 0;
693 }
694
695 int wm_adsp2_event(struct snd_soc_dapm_widget *w,
696 struct snd_kcontrol *kcontrol, int event)
697 {
698 struct snd_soc_codec *codec = w->codec;
699 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
700 struct wm_adsp *dsp = &dsps[w->shift];
701 unsigned int val;
702 int ret;
703
704 switch (event) {
705 case SND_SOC_DAPM_POST_PMU:
706 /*
707 * For simplicity set the DSP clock rate to be the
708 * SYSCLK rate rather than making it configurable.
709 */
710 ret = regmap_read(dsp->regmap, ARIZONA_SYSTEM_CLOCK_1, &val);
711 if (ret != 0) {
712 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
713 ret);
714 return ret;
715 }
716 val = (val & ARIZONA_SYSCLK_FREQ_MASK)
717 >> ARIZONA_SYSCLK_FREQ_SHIFT;
718
719 ret = regmap_update_bits(dsp->regmap,
720 dsp->base + ADSP2_CLOCKING,
721 ADSP2_CLK_SEL_MASK, val);
722 if (ret != 0) {
723 adsp_err(dsp, "Failed to set clock rate: %d\n",
724 ret);
725 return ret;
726 }
727
728 if (dsp->dvfs) {
729 ret = regmap_read(dsp->regmap,
730 dsp->base + ADSP2_CLOCKING, &val);
731 if (ret != 0) {
732 dev_err(dsp->dev,
733 "Failed to read clocking: %d\n", ret);
734 return ret;
735 }
736
737 if ((val & ADSP2_CLK_SEL_MASK) >= 3) {
738 ret = regulator_enable(dsp->dvfs);
739 if (ret != 0) {
740 dev_err(dsp->dev,
741 "Failed to enable supply: %d\n",
742 ret);
743 return ret;
744 }
745
746 ret = regulator_set_voltage(dsp->dvfs,
747 1800000,
748 1800000);
749 if (ret != 0) {
750 dev_err(dsp->dev,
751 "Failed to raise supply: %d\n",
752 ret);
753 return ret;
754 }
755 }
756 }
757
758 ret = wm_adsp2_ena(dsp);
759 if (ret != 0)
760 return ret;
761
762 ret = wm_adsp_load(dsp);
763 if (ret != 0)
764 goto err;
765
766 ret = wm_adsp_setup_algs(dsp);
767 if (ret != 0)
768 goto err;
769
770 ret = wm_adsp_load_coeff(dsp);
771 if (ret != 0)
772 goto err;
773
774 ret = regmap_update_bits(dsp->regmap,
775 dsp->base + ADSP2_CONTROL,
776 ADSP2_CORE_ENA | ADSP2_START,
777 ADSP2_CORE_ENA | ADSP2_START);
778 if (ret != 0)
779 goto err;
780 break;
781
782 case SND_SOC_DAPM_PRE_PMD:
783 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
784 ADSP2_SYS_ENA | ADSP2_CORE_ENA |
785 ADSP2_START, 0);
786
787 if (dsp->dvfs) {
788 ret = regulator_set_voltage(dsp->dvfs, 1200000,
789 1800000);
790 if (ret != 0)
791 dev_warn(dsp->dev,
792 "Failed to lower supply: %d\n",
793 ret);
794
795 ret = regulator_disable(dsp->dvfs);
796 if (ret != 0)
797 dev_err(dsp->dev,
798 "Failed to enable supply: %d\n",
799 ret);
800 }
801 break;
802
803 default:
804 break;
805 }
806
807 return 0;
808 err:
809 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
810 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
811 return ret;
812 }
813 EXPORT_SYMBOL_GPL(wm_adsp2_event);
814
815 int wm_adsp2_init(struct wm_adsp *adsp, bool dvfs)
816 {
817 int ret;
818
819 /*
820 * Disable the DSP memory by default when in reset for a small
821 * power saving.
822 */
823 ret = regmap_update_bits(adsp->regmap, adsp->base + ADSP2_CONTROL,
824 ADSP2_MEM_ENA, 0);
825 if (ret != 0) {
826 adsp_err(adsp, "Failed to clear memory retention: %d\n", ret);
827 return ret;
828 }
829
830 if (dvfs) {
831 adsp->dvfs = devm_regulator_get(adsp->dev, "DCVDD");
832 if (IS_ERR(adsp->dvfs)) {
833 ret = PTR_ERR(adsp->dvfs);
834 dev_err(adsp->dev, "Failed to get DCVDD: %d\n", ret);
835 return ret;
836 }
837
838 ret = regulator_enable(adsp->dvfs);
839 if (ret != 0) {
840 dev_err(adsp->dev, "Failed to enable DCVDD: %d\n",
841 ret);
842 return ret;
843 }
844
845 ret = regulator_set_voltage(adsp->dvfs, 1200000, 1800000);
846 if (ret != 0) {
847 dev_err(adsp->dev, "Failed to initialise DVFS: %d\n",
848 ret);
849 return ret;
850 }
851
852 ret = regulator_disable(adsp->dvfs);
853 if (ret != 0) {
854 dev_err(adsp->dev, "Failed to disable DCVDD: %d\n",
855 ret);
856 return ret;
857 }
858 }
859
860 return 0;
861 }
862 EXPORT_SYMBOL_GPL(wm_adsp2_init);
Linux kernel - Deliverables
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