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ASoC: wm_adsp: Dump scratch registers on DSP shutdown
[deliverable/linux.git] / sound / soc / codecs / wm_adsp.c
1 /*
2 * wm_adsp.c -- Wolfson ADSP support
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/firmware.h>
18 #include <linux/list.h>
19 #include <linux/pm.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <linux/vmalloc.h>
25 #include <linux/workqueue.h>
26 #include <sound/core.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/jack.h>
31 #include <sound/initval.h>
32 #include <sound/tlv.h>
33
34 #include <linux/mfd/arizona/registers.h>
35
36 #include "arizona.h"
37 #include "wm_adsp.h"
38
39 #define adsp_crit(_dsp, fmt, ...) \
40 dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
41 #define adsp_err(_dsp, fmt, ...) \
42 dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
43 #define adsp_warn(_dsp, fmt, ...) \
44 dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
45 #define adsp_info(_dsp, fmt, ...) \
46 dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
47 #define adsp_dbg(_dsp, fmt, ...) \
48 dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
49
50 #define ADSP1_CONTROL_1 0x00
51 #define ADSP1_CONTROL_2 0x02
52 #define ADSP1_CONTROL_3 0x03
53 #define ADSP1_CONTROL_4 0x04
54 #define ADSP1_CONTROL_5 0x06
55 #define ADSP1_CONTROL_6 0x07
56 #define ADSP1_CONTROL_7 0x08
57 #define ADSP1_CONTROL_8 0x09
58 #define ADSP1_CONTROL_9 0x0A
59 #define ADSP1_CONTROL_10 0x0B
60 #define ADSP1_CONTROL_11 0x0C
61 #define ADSP1_CONTROL_12 0x0D
62 #define ADSP1_CONTROL_13 0x0F
63 #define ADSP1_CONTROL_14 0x10
64 #define ADSP1_CONTROL_15 0x11
65 #define ADSP1_CONTROL_16 0x12
66 #define ADSP1_CONTROL_17 0x13
67 #define ADSP1_CONTROL_18 0x14
68 #define ADSP1_CONTROL_19 0x16
69 #define ADSP1_CONTROL_20 0x17
70 #define ADSP1_CONTROL_21 0x18
71 #define ADSP1_CONTROL_22 0x1A
72 #define ADSP1_CONTROL_23 0x1B
73 #define ADSP1_CONTROL_24 0x1C
74 #define ADSP1_CONTROL_25 0x1E
75 #define ADSP1_CONTROL_26 0x20
76 #define ADSP1_CONTROL_27 0x21
77 #define ADSP1_CONTROL_28 0x22
78 #define ADSP1_CONTROL_29 0x23
79 #define ADSP1_CONTROL_30 0x24
80 #define ADSP1_CONTROL_31 0x26
81
82 /*
83 * ADSP1 Control 19
84 */
85 #define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
86 #define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
87 #define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
88
89
90 /*
91 * ADSP1 Control 30
92 */
93 #define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
94 #define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
95 #define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
96 #define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
97 #define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
98 #define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
99 #define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
100 #define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
101 #define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
102 #define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
103 #define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
104 #define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
105 #define ADSP1_START 0x0001 /* DSP1_START */
106 #define ADSP1_START_MASK 0x0001 /* DSP1_START */
107 #define ADSP1_START_SHIFT 0 /* DSP1_START */
108 #define ADSP1_START_WIDTH 1 /* DSP1_START */
109
110 /*
111 * ADSP1 Control 31
112 */
113 #define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
114 #define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
115 #define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
116
117 #define ADSP2_CONTROL 0x0
118 #define ADSP2_CLOCKING 0x1
119 #define ADSP2_STATUS1 0x4
120 #define ADSP2_WDMA_CONFIG_1 0x30
121 #define ADSP2_WDMA_CONFIG_2 0x31
122 #define ADSP2_RDMA_CONFIG_1 0x34
123
124 #define ADSP2_SCRATCH0 0x40
125 #define ADSP2_SCRATCH1 0x41
126 #define ADSP2_SCRATCH2 0x42
127 #define ADSP2_SCRATCH3 0x43
128
129 /*
130 * ADSP2 Control
131 */
132
133 #define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
134 #define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
135 #define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
136 #define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
137 #define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
138 #define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
139 #define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
140 #define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
141 #define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
142 #define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
143 #define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
144 #define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
145 #define ADSP2_START 0x0001 /* DSP1_START */
146 #define ADSP2_START_MASK 0x0001 /* DSP1_START */
147 #define ADSP2_START_SHIFT 0 /* DSP1_START */
148 #define ADSP2_START_WIDTH 1 /* DSP1_START */
149
150 /*
151 * ADSP2 clocking
152 */
153 #define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
154 #define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
155 #define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
156
157 /*
158 * ADSP2 Status 1
159 */
160 #define ADSP2_RAM_RDY 0x0001
161 #define ADSP2_RAM_RDY_MASK 0x0001
162 #define ADSP2_RAM_RDY_SHIFT 0
163 #define ADSP2_RAM_RDY_WIDTH 1
164
165 struct wm_adsp_buf {
166 struct list_head list;
167 void *buf;
168 };
169
170 static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len,
171 struct list_head *list)
172 {
173 struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
174
175 if (buf == NULL)
176 return NULL;
177
178 buf->buf = vmalloc(len);
179 if (!buf->buf) {
180 vfree(buf);
181 return NULL;
182 }
183 memcpy(buf->buf, src, len);
184
185 if (list)
186 list_add_tail(&buf->list, list);
187
188 return buf;
189 }
190
191 static void wm_adsp_buf_free(struct list_head *list)
192 {
193 while (!list_empty(list)) {
194 struct wm_adsp_buf *buf = list_first_entry(list,
195 struct wm_adsp_buf,
196 list);
197 list_del(&buf->list);
198 vfree(buf->buf);
199 kfree(buf);
200 }
201 }
202
203 #define WM_ADSP_NUM_FW 4
204
205 #define WM_ADSP_FW_MBC_VSS 0
206 #define WM_ADSP_FW_TX 1
207 #define WM_ADSP_FW_TX_SPK 2
208 #define WM_ADSP_FW_RX_ANC 3
209
210 static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
211 [WM_ADSP_FW_MBC_VSS] = "MBC/VSS",
212 [WM_ADSP_FW_TX] = "Tx",
213 [WM_ADSP_FW_TX_SPK] = "Tx Speaker",
214 [WM_ADSP_FW_RX_ANC] = "Rx ANC",
215 };
216
217 static struct {
218 const char *file;
219 } wm_adsp_fw[WM_ADSP_NUM_FW] = {
220 [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" },
221 [WM_ADSP_FW_TX] = { .file = "tx" },
222 [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" },
223 [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" },
224 };
225
226 struct wm_coeff_ctl_ops {
227 int (*xget)(struct snd_kcontrol *kcontrol,
228 struct snd_ctl_elem_value *ucontrol);
229 int (*xput)(struct snd_kcontrol *kcontrol,
230 struct snd_ctl_elem_value *ucontrol);
231 int (*xinfo)(struct snd_kcontrol *kcontrol,
232 struct snd_ctl_elem_info *uinfo);
233 };
234
235 struct wm_coeff_ctl {
236 const char *name;
237 const char *fw_name;
238 struct wm_adsp_alg_region alg_region;
239 struct wm_coeff_ctl_ops ops;
240 struct wm_adsp *dsp;
241 unsigned int enabled:1;
242 struct list_head list;
243 void *cache;
244 unsigned int offset;
245 size_t len;
246 unsigned int set:1;
247 struct snd_kcontrol *kcontrol;
248 unsigned int flags;
249 };
250
251 static int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
252 struct snd_ctl_elem_value *ucontrol)
253 {
254 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
255 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
256 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
257
258 ucontrol->value.integer.value[0] = dsp[e->shift_l].fw;
259
260 return 0;
261 }
262
263 static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
264 struct snd_ctl_elem_value *ucontrol)
265 {
266 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
267 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
268 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
269
270 if (ucontrol->value.integer.value[0] == dsp[e->shift_l].fw)
271 return 0;
272
273 if (ucontrol->value.integer.value[0] >= WM_ADSP_NUM_FW)
274 return -EINVAL;
275
276 if (dsp[e->shift_l].running)
277 return -EBUSY;
278
279 dsp[e->shift_l].fw = ucontrol->value.integer.value[0];
280
281 return 0;
282 }
283
284 static const struct soc_enum wm_adsp_fw_enum[] = {
285 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
286 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
287 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
288 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
289 };
290
291 const struct snd_kcontrol_new wm_adsp1_fw_controls[] = {
292 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
293 wm_adsp_fw_get, wm_adsp_fw_put),
294 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
295 wm_adsp_fw_get, wm_adsp_fw_put),
296 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
297 wm_adsp_fw_get, wm_adsp_fw_put),
298 };
299 EXPORT_SYMBOL_GPL(wm_adsp1_fw_controls);
300
301 #if IS_ENABLED(CONFIG_SND_SOC_ARIZONA)
302 static const struct soc_enum wm_adsp2_rate_enum[] = {
303 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP1_CONTROL_1,
304 ARIZONA_DSP1_RATE_SHIFT, 0xf,
305 ARIZONA_RATE_ENUM_SIZE,
306 arizona_rate_text, arizona_rate_val),
307 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP2_CONTROL_1,
308 ARIZONA_DSP1_RATE_SHIFT, 0xf,
309 ARIZONA_RATE_ENUM_SIZE,
310 arizona_rate_text, arizona_rate_val),
311 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP3_CONTROL_1,
312 ARIZONA_DSP1_RATE_SHIFT, 0xf,
313 ARIZONA_RATE_ENUM_SIZE,
314 arizona_rate_text, arizona_rate_val),
315 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP4_CONTROL_1,
316 ARIZONA_DSP1_RATE_SHIFT, 0xf,
317 ARIZONA_RATE_ENUM_SIZE,
318 arizona_rate_text, arizona_rate_val),
319 };
320
321 const struct snd_kcontrol_new wm_adsp2_fw_controls[] = {
322 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
323 wm_adsp_fw_get, wm_adsp_fw_put),
324 SOC_ENUM("DSP1 Rate", wm_adsp2_rate_enum[0]),
325 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
326 wm_adsp_fw_get, wm_adsp_fw_put),
327 SOC_ENUM("DSP2 Rate", wm_adsp2_rate_enum[1]),
328 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
329 wm_adsp_fw_get, wm_adsp_fw_put),
330 SOC_ENUM("DSP3 Rate", wm_adsp2_rate_enum[2]),
331 SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum[3],
332 wm_adsp_fw_get, wm_adsp_fw_put),
333 SOC_ENUM("DSP4 Rate", wm_adsp2_rate_enum[3]),
334 };
335 EXPORT_SYMBOL_GPL(wm_adsp2_fw_controls);
336 #endif
337
338 static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
339 int type)
340 {
341 int i;
342
343 for (i = 0; i < dsp->num_mems; i++)
344 if (dsp->mem[i].type == type)
345 return &dsp->mem[i];
346
347 return NULL;
348 }
349
350 static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *mem,
351 unsigned int offset)
352 {
353 if (WARN_ON(!mem))
354 return offset;
355 switch (mem->type) {
356 case WMFW_ADSP1_PM:
357 return mem->base + (offset * 3);
358 case WMFW_ADSP1_DM:
359 return mem->base + (offset * 2);
360 case WMFW_ADSP2_XM:
361 return mem->base + (offset * 2);
362 case WMFW_ADSP2_YM:
363 return mem->base + (offset * 2);
364 case WMFW_ADSP1_ZM:
365 return mem->base + (offset * 2);
366 default:
367 WARN(1, "Unknown memory region type");
368 return offset;
369 }
370 }
371
372 static void wm_adsp2_show_fw_status(struct wm_adsp *dsp)
373 {
374 u16 scratch[4];
375 int ret;
376
377 ret = regmap_raw_read(dsp->regmap, dsp->base + ADSP2_SCRATCH0,
378 scratch, sizeof(scratch));
379 if (ret) {
380 adsp_err(dsp, "Failed to read SCRATCH regs: %d\n", ret);
381 return;
382 }
383
384 adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
385 be16_to_cpu(scratch[0]),
386 be16_to_cpu(scratch[1]),
387 be16_to_cpu(scratch[2]),
388 be16_to_cpu(scratch[3]));
389 }
390
391 static int wm_coeff_info(struct snd_kcontrol *kcontrol,
392 struct snd_ctl_elem_info *uinfo)
393 {
394 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
395
396 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
397 uinfo->count = ctl->len;
398 return 0;
399 }
400
401 static int wm_coeff_write_control(struct wm_coeff_ctl *ctl,
402 const void *buf, size_t len)
403 {
404 struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
405 const struct wm_adsp_region *mem;
406 struct wm_adsp *dsp = ctl->dsp;
407 void *scratch;
408 int ret;
409 unsigned int reg;
410
411 mem = wm_adsp_find_region(dsp, alg_region->type);
412 if (!mem) {
413 adsp_err(dsp, "No base for region %x\n",
414 alg_region->type);
415 return -EINVAL;
416 }
417
418 reg = ctl->alg_region.base + ctl->offset;
419 reg = wm_adsp_region_to_reg(mem, reg);
420
421 scratch = kmemdup(buf, ctl->len, GFP_KERNEL | GFP_DMA);
422 if (!scratch)
423 return -ENOMEM;
424
425 ret = regmap_raw_write(dsp->regmap, reg, scratch,
426 ctl->len);
427 if (ret) {
428 adsp_err(dsp, "Failed to write %zu bytes to %x: %d\n",
429 ctl->len, reg, ret);
430 kfree(scratch);
431 return ret;
432 }
433 adsp_dbg(dsp, "Wrote %zu bytes to %x\n", ctl->len, reg);
434
435 kfree(scratch);
436
437 return 0;
438 }
439
440 static int wm_coeff_put(struct snd_kcontrol *kcontrol,
441 struct snd_ctl_elem_value *ucontrol)
442 {
443 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
444 char *p = ucontrol->value.bytes.data;
445
446 memcpy(ctl->cache, p, ctl->len);
447
448 ctl->set = 1;
449 if (!ctl->enabled)
450 return 0;
451
452 return wm_coeff_write_control(ctl, p, ctl->len);
453 }
454
455 static int wm_coeff_read_control(struct wm_coeff_ctl *ctl,
456 void *buf, size_t len)
457 {
458 struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
459 const struct wm_adsp_region *mem;
460 struct wm_adsp *dsp = ctl->dsp;
461 void *scratch;
462 int ret;
463 unsigned int reg;
464
465 mem = wm_adsp_find_region(dsp, alg_region->type);
466 if (!mem) {
467 adsp_err(dsp, "No base for region %x\n",
468 alg_region->type);
469 return -EINVAL;
470 }
471
472 reg = ctl->alg_region.base + ctl->offset;
473 reg = wm_adsp_region_to_reg(mem, reg);
474
475 scratch = kmalloc(ctl->len, GFP_KERNEL | GFP_DMA);
476 if (!scratch)
477 return -ENOMEM;
478
479 ret = regmap_raw_read(dsp->regmap, reg, scratch, ctl->len);
480 if (ret) {
481 adsp_err(dsp, "Failed to read %zu bytes from %x: %d\n",
482 ctl->len, reg, ret);
483 kfree(scratch);
484 return ret;
485 }
486 adsp_dbg(dsp, "Read %zu bytes from %x\n", ctl->len, reg);
487
488 memcpy(buf, scratch, ctl->len);
489 kfree(scratch);
490
491 return 0;
492 }
493
494 static int wm_coeff_get(struct snd_kcontrol *kcontrol,
495 struct snd_ctl_elem_value *ucontrol)
496 {
497 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
498 char *p = ucontrol->value.bytes.data;
499
500 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
501 if (ctl->enabled)
502 return wm_coeff_read_control(ctl, p, ctl->len);
503 else
504 return -EPERM;
505 }
506
507 memcpy(p, ctl->cache, ctl->len);
508
509 return 0;
510 }
511
512 struct wmfw_ctl_work {
513 struct wm_adsp *dsp;
514 struct wm_coeff_ctl *ctl;
515 struct work_struct work;
516 };
517
518 static int wmfw_add_ctl(struct wm_adsp *dsp, struct wm_coeff_ctl *ctl)
519 {
520 struct snd_kcontrol_new *kcontrol;
521 int ret;
522
523 if (!ctl || !ctl->name)
524 return -EINVAL;
525
526 kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL);
527 if (!kcontrol)
528 return -ENOMEM;
529 kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
530
531 kcontrol->name = ctl->name;
532 kcontrol->info = wm_coeff_info;
533 kcontrol->get = wm_coeff_get;
534 kcontrol->put = wm_coeff_put;
535 kcontrol->private_value = (unsigned long)ctl;
536
537 if (ctl->flags) {
538 if (ctl->flags & WMFW_CTL_FLAG_WRITEABLE)
539 kcontrol->access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
540 if (ctl->flags & WMFW_CTL_FLAG_READABLE)
541 kcontrol->access |= SNDRV_CTL_ELEM_ACCESS_READ;
542 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
543 kcontrol->access |= SNDRV_CTL_ELEM_ACCESS_VOLATILE;
544 }
545
546 ret = snd_soc_add_card_controls(dsp->card,
547 kcontrol, 1);
548 if (ret < 0)
549 goto err_kcontrol;
550
551 kfree(kcontrol);
552
553 ctl->kcontrol = snd_soc_card_get_kcontrol(dsp->card,
554 ctl->name);
555
556 return 0;
557
558 err_kcontrol:
559 kfree(kcontrol);
560 return ret;
561 }
562
563 static int wm_coeff_init_control_caches(struct wm_adsp *dsp)
564 {
565 struct wm_coeff_ctl *ctl;
566 int ret;
567
568 list_for_each_entry(ctl, &dsp->ctl_list, list) {
569 if (!ctl->enabled || ctl->set)
570 continue;
571 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
572 continue;
573
574 ret = wm_coeff_read_control(ctl,
575 ctl->cache,
576 ctl->len);
577 if (ret < 0)
578 return ret;
579 }
580
581 return 0;
582 }
583
584 static int wm_coeff_sync_controls(struct wm_adsp *dsp)
585 {
586 struct wm_coeff_ctl *ctl;
587 int ret;
588
589 list_for_each_entry(ctl, &dsp->ctl_list, list) {
590 if (!ctl->enabled)
591 continue;
592 if (ctl->set && !(ctl->flags & WMFW_CTL_FLAG_VOLATILE)) {
593 ret = wm_coeff_write_control(ctl,
594 ctl->cache,
595 ctl->len);
596 if (ret < 0)
597 return ret;
598 }
599 }
600
601 return 0;
602 }
603
604 static void wm_adsp_ctl_work(struct work_struct *work)
605 {
606 struct wmfw_ctl_work *ctl_work = container_of(work,
607 struct wmfw_ctl_work,
608 work);
609
610 wmfw_add_ctl(ctl_work->dsp, ctl_work->ctl);
611 kfree(ctl_work);
612 }
613
614 static int wm_adsp_create_control(struct wm_adsp *dsp,
615 const struct wm_adsp_alg_region *alg_region,
616 unsigned int offset, unsigned int len,
617 const char *subname, unsigned int subname_len,
618 unsigned int flags)
619 {
620 struct wm_coeff_ctl *ctl;
621 struct wmfw_ctl_work *ctl_work;
622 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
623 char *region_name;
624 int ret;
625
626 if (flags & WMFW_CTL_FLAG_SYS)
627 return 0;
628
629 switch (alg_region->type) {
630 case WMFW_ADSP1_PM:
631 region_name = "PM";
632 break;
633 case WMFW_ADSP1_DM:
634 region_name = "DM";
635 break;
636 case WMFW_ADSP2_XM:
637 region_name = "XM";
638 break;
639 case WMFW_ADSP2_YM:
640 region_name = "YM";
641 break;
642 case WMFW_ADSP1_ZM:
643 region_name = "ZM";
644 break;
645 default:
646 adsp_err(dsp, "Unknown region type: %d\n", alg_region->type);
647 return -EINVAL;
648 }
649
650 switch (dsp->fw_ver) {
651 case 0:
652 case 1:
653 snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "DSP%d %s %x",
654 dsp->num, region_name, alg_region->alg);
655 break;
656 default:
657 ret = snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
658 "DSP%d%c %.12s %x", dsp->num, *region_name,
659 wm_adsp_fw_text[dsp->fw], alg_region->alg);
660
661 /* Truncate the subname from the start if it is too long */
662 if (subname) {
663 int avail = SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret - 2;
664 int skip = 0;
665
666 if (subname_len > avail)
667 skip = subname_len - avail;
668
669 snprintf(name + ret,
670 SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret, " %.*s",
671 subname_len - skip, subname + skip);
672 }
673 break;
674 }
675
676 list_for_each_entry(ctl, &dsp->ctl_list,
677 list) {
678 if (!strcmp(ctl->name, name)) {
679 if (!ctl->enabled)
680 ctl->enabled = 1;
681 return 0;
682 }
683 }
684
685 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
686 if (!ctl)
687 return -ENOMEM;
688 ctl->fw_name = wm_adsp_fw_text[dsp->fw];
689 ctl->alg_region = *alg_region;
690 ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL);
691 if (!ctl->name) {
692 ret = -ENOMEM;
693 goto err_ctl;
694 }
695 ctl->enabled = 1;
696 ctl->set = 0;
697 ctl->ops.xget = wm_coeff_get;
698 ctl->ops.xput = wm_coeff_put;
699 ctl->dsp = dsp;
700
701 ctl->flags = flags;
702 ctl->offset = offset;
703 if (len > 512) {
704 adsp_warn(dsp, "Truncating control %s from %d\n",
705 ctl->name, len);
706 len = 512;
707 }
708 ctl->len = len;
709 ctl->cache = kzalloc(ctl->len, GFP_KERNEL);
710 if (!ctl->cache) {
711 ret = -ENOMEM;
712 goto err_ctl_name;
713 }
714
715 list_add(&ctl->list, &dsp->ctl_list);
716
717 ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL);
718 if (!ctl_work) {
719 ret = -ENOMEM;
720 goto err_ctl_cache;
721 }
722
723 ctl_work->dsp = dsp;
724 ctl_work->ctl = ctl;
725 INIT_WORK(&ctl_work->work, wm_adsp_ctl_work);
726 schedule_work(&ctl_work->work);
727
728 return 0;
729
730 err_ctl_cache:
731 kfree(ctl->cache);
732 err_ctl_name:
733 kfree(ctl->name);
734 err_ctl:
735 kfree(ctl);
736
737 return ret;
738 }
739
740 struct wm_coeff_parsed_alg {
741 int id;
742 const u8 *name;
743 int name_len;
744 int ncoeff;
745 };
746
747 struct wm_coeff_parsed_coeff {
748 int offset;
749 int mem_type;
750 const u8 *name;
751 int name_len;
752 int ctl_type;
753 int flags;
754 int len;
755 };
756
757 static int wm_coeff_parse_string(int bytes, const u8 **pos, const u8 **str)
758 {
759 int length;
760
761 switch (bytes) {
762 case 1:
763 length = **pos;
764 break;
765 case 2:
766 length = le16_to_cpu(*((__le16 *)*pos));
767 break;
768 default:
769 return 0;
770 }
771
772 if (str)
773 *str = *pos + bytes;
774
775 *pos += ((length + bytes) + 3) & ~0x03;
776
777 return length;
778 }
779
780 static int wm_coeff_parse_int(int bytes, const u8 **pos)
781 {
782 int val = 0;
783
784 switch (bytes) {
785 case 2:
786 val = le16_to_cpu(*((__le16 *)*pos));
787 break;
788 case 4:
789 val = le32_to_cpu(*((__le32 *)*pos));
790 break;
791 default:
792 break;
793 }
794
795 *pos += bytes;
796
797 return val;
798 }
799
800 static inline void wm_coeff_parse_alg(struct wm_adsp *dsp, const u8 **data,
801 struct wm_coeff_parsed_alg *blk)
802 {
803 const struct wmfw_adsp_alg_data *raw;
804
805 switch (dsp->fw_ver) {
806 case 0:
807 case 1:
808 raw = (const struct wmfw_adsp_alg_data *)*data;
809 *data = raw->data;
810
811 blk->id = le32_to_cpu(raw->id);
812 blk->name = raw->name;
813 blk->name_len = strlen(raw->name);
814 blk->ncoeff = le32_to_cpu(raw->ncoeff);
815 break;
816 default:
817 blk->id = wm_coeff_parse_int(sizeof(raw->id), data);
818 blk->name_len = wm_coeff_parse_string(sizeof(u8), data,
819 &blk->name);
820 wm_coeff_parse_string(sizeof(u16), data, NULL);
821 blk->ncoeff = wm_coeff_parse_int(sizeof(raw->ncoeff), data);
822 break;
823 }
824
825 adsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id);
826 adsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name);
827 adsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff);
828 }
829
830 static inline void wm_coeff_parse_coeff(struct wm_adsp *dsp, const u8 **data,
831 struct wm_coeff_parsed_coeff *blk)
832 {
833 const struct wmfw_adsp_coeff_data *raw;
834 const u8 *tmp;
835 int length;
836
837 switch (dsp->fw_ver) {
838 case 0:
839 case 1:
840 raw = (const struct wmfw_adsp_coeff_data *)*data;
841 *data = *data + sizeof(raw->hdr) + le32_to_cpu(raw->hdr.size);
842
843 blk->offset = le16_to_cpu(raw->hdr.offset);
844 blk->mem_type = le16_to_cpu(raw->hdr.type);
845 blk->name = raw->name;
846 blk->name_len = strlen(raw->name);
847 blk->ctl_type = le16_to_cpu(raw->ctl_type);
848 blk->flags = le16_to_cpu(raw->flags);
849 blk->len = le32_to_cpu(raw->len);
850 break;
851 default:
852 tmp = *data;
853 blk->offset = wm_coeff_parse_int(sizeof(raw->hdr.offset), &tmp);
854 blk->mem_type = wm_coeff_parse_int(sizeof(raw->hdr.type), &tmp);
855 length = wm_coeff_parse_int(sizeof(raw->hdr.size), &tmp);
856 blk->name_len = wm_coeff_parse_string(sizeof(u8), &tmp,
857 &blk->name);
858 wm_coeff_parse_string(sizeof(u8), &tmp, NULL);
859 wm_coeff_parse_string(sizeof(u16), &tmp, NULL);
860 blk->ctl_type = wm_coeff_parse_int(sizeof(raw->ctl_type), &tmp);
861 blk->flags = wm_coeff_parse_int(sizeof(raw->flags), &tmp);
862 blk->len = wm_coeff_parse_int(sizeof(raw->len), &tmp);
863
864 *data = *data + sizeof(raw->hdr) + length;
865 break;
866 }
867
868 adsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type);
869 adsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset);
870 adsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name);
871 adsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags);
872 adsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type);
873 adsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len);
874 }
875
876 static int wm_adsp_parse_coeff(struct wm_adsp *dsp,
877 const struct wmfw_region *region)
878 {
879 struct wm_adsp_alg_region alg_region = {};
880 struct wm_coeff_parsed_alg alg_blk;
881 struct wm_coeff_parsed_coeff coeff_blk;
882 const u8 *data = region->data;
883 int i, ret;
884
885 wm_coeff_parse_alg(dsp, &data, &alg_blk);
886 for (i = 0; i < alg_blk.ncoeff; i++) {
887 wm_coeff_parse_coeff(dsp, &data, &coeff_blk);
888
889 switch (coeff_blk.ctl_type) {
890 case SNDRV_CTL_ELEM_TYPE_BYTES:
891 break;
892 default:
893 adsp_err(dsp, "Unknown control type: %d\n",
894 coeff_blk.ctl_type);
895 return -EINVAL;
896 }
897
898 alg_region.type = coeff_blk.mem_type;
899 alg_region.alg = alg_blk.id;
900
901 ret = wm_adsp_create_control(dsp, &alg_region,
902 coeff_blk.offset,
903 coeff_blk.len,
904 coeff_blk.name,
905 coeff_blk.name_len,
906 coeff_blk.flags);
907 if (ret < 0)
908 adsp_err(dsp, "Failed to create control: %.*s, %d\n",
909 coeff_blk.name_len, coeff_blk.name, ret);
910 }
911
912 return 0;
913 }
914
915 static int wm_adsp_load(struct wm_adsp *dsp)
916 {
917 LIST_HEAD(buf_list);
918 const struct firmware *firmware;
919 struct regmap *regmap = dsp->regmap;
920 unsigned int pos = 0;
921 const struct wmfw_header *header;
922 const struct wmfw_adsp1_sizes *adsp1_sizes;
923 const struct wmfw_adsp2_sizes *adsp2_sizes;
924 const struct wmfw_footer *footer;
925 const struct wmfw_region *region;
926 const struct wm_adsp_region *mem;
927 const char *region_name;
928 char *file, *text;
929 struct wm_adsp_buf *buf;
930 unsigned int reg;
931 int regions = 0;
932 int ret, offset, type, sizes;
933
934 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
935 if (file == NULL)
936 return -ENOMEM;
937
938 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.wmfw", dsp->part, dsp->num,
939 wm_adsp_fw[dsp->fw].file);
940 file[PAGE_SIZE - 1] = '\0';
941
942 ret = request_firmware(&firmware, file, dsp->dev);
943 if (ret != 0) {
944 adsp_err(dsp, "Failed to request '%s'\n", file);
945 goto out;
946 }
947 ret = -EINVAL;
948
949 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
950 if (pos >= firmware->size) {
951 adsp_err(dsp, "%s: file too short, %zu bytes\n",
952 file, firmware->size);
953 goto out_fw;
954 }
955
956 header = (void*)&firmware->data[0];
957
958 if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
959 adsp_err(dsp, "%s: invalid magic\n", file);
960 goto out_fw;
961 }
962
963 switch (header->ver) {
964 case 0:
965 adsp_warn(dsp, "%s: Depreciated file format %d\n",
966 file, header->ver);
967 break;
968 case 1:
969 case 2:
970 break;
971 default:
972 adsp_err(dsp, "%s: unknown file format %d\n",
973 file, header->ver);
974 goto out_fw;
975 }
976
977 adsp_info(dsp, "Firmware version: %d\n", header->ver);
978 dsp->fw_ver = header->ver;
979
980 if (header->core != dsp->type) {
981 adsp_err(dsp, "%s: invalid core %d != %d\n",
982 file, header->core, dsp->type);
983 goto out_fw;
984 }
985
986 switch (dsp->type) {
987 case WMFW_ADSP1:
988 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
989 adsp1_sizes = (void *)&(header[1]);
990 footer = (void *)&(adsp1_sizes[1]);
991 sizes = sizeof(*adsp1_sizes);
992
993 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n",
994 file, le32_to_cpu(adsp1_sizes->dm),
995 le32_to_cpu(adsp1_sizes->pm),
996 le32_to_cpu(adsp1_sizes->zm));
997 break;
998
999 case WMFW_ADSP2:
1000 pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer);
1001 adsp2_sizes = (void *)&(header[1]);
1002 footer = (void *)&(adsp2_sizes[1]);
1003 sizes = sizeof(*adsp2_sizes);
1004
1005 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n",
1006 file, le32_to_cpu(adsp2_sizes->xm),
1007 le32_to_cpu(adsp2_sizes->ym),
1008 le32_to_cpu(adsp2_sizes->pm),
1009 le32_to_cpu(adsp2_sizes->zm));
1010 break;
1011
1012 default:
1013 WARN(1, "Unknown DSP type");
1014 goto out_fw;
1015 }
1016
1017 if (le32_to_cpu(header->len) != sizeof(*header) +
1018 sizes + sizeof(*footer)) {
1019 adsp_err(dsp, "%s: unexpected header length %d\n",
1020 file, le32_to_cpu(header->len));
1021 goto out_fw;
1022 }
1023
1024 adsp_dbg(dsp, "%s: timestamp %llu\n", file,
1025 le64_to_cpu(footer->timestamp));
1026
1027 while (pos < firmware->size &&
1028 pos - firmware->size > sizeof(*region)) {
1029 region = (void *)&(firmware->data[pos]);
1030 region_name = "Unknown";
1031 reg = 0;
1032 text = NULL;
1033 offset = le32_to_cpu(region->offset) & 0xffffff;
1034 type = be32_to_cpu(region->type) & 0xff;
1035 mem = wm_adsp_find_region(dsp, type);
1036
1037 switch (type) {
1038 case WMFW_NAME_TEXT:
1039 region_name = "Firmware name";
1040 text = kzalloc(le32_to_cpu(region->len) + 1,
1041 GFP_KERNEL);
1042 break;
1043 case WMFW_ALGORITHM_DATA:
1044 region_name = "Algorithm";
1045 ret = wm_adsp_parse_coeff(dsp, region);
1046 if (ret != 0)
1047 goto out_fw;
1048 break;
1049 case WMFW_INFO_TEXT:
1050 region_name = "Information";
1051 text = kzalloc(le32_to_cpu(region->len) + 1,
1052 GFP_KERNEL);
1053 break;
1054 case WMFW_ABSOLUTE:
1055 region_name = "Absolute";
1056 reg = offset;
1057 break;
1058 case WMFW_ADSP1_PM:
1059 region_name = "PM";
1060 reg = wm_adsp_region_to_reg(mem, offset);
1061 break;
1062 case WMFW_ADSP1_DM:
1063 region_name = "DM";
1064 reg = wm_adsp_region_to_reg(mem, offset);
1065 break;
1066 case WMFW_ADSP2_XM:
1067 region_name = "XM";
1068 reg = wm_adsp_region_to_reg(mem, offset);
1069 break;
1070 case WMFW_ADSP2_YM:
1071 region_name = "YM";
1072 reg = wm_adsp_region_to_reg(mem, offset);
1073 break;
1074 case WMFW_ADSP1_ZM:
1075 region_name = "ZM";
1076 reg = wm_adsp_region_to_reg(mem, offset);
1077 break;
1078 default:
1079 adsp_warn(dsp,
1080 "%s.%d: Unknown region type %x at %d(%x)\n",
1081 file, regions, type, pos, pos);
1082 break;
1083 }
1084
1085 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
1086 regions, le32_to_cpu(region->len), offset,
1087 region_name);
1088
1089 if (text) {
1090 memcpy(text, region->data, le32_to_cpu(region->len));
1091 adsp_info(dsp, "%s: %s\n", file, text);
1092 kfree(text);
1093 }
1094
1095 if (reg) {
1096 buf = wm_adsp_buf_alloc(region->data,
1097 le32_to_cpu(region->len),
1098 &buf_list);
1099 if (!buf) {
1100 adsp_err(dsp, "Out of memory\n");
1101 ret = -ENOMEM;
1102 goto out_fw;
1103 }
1104
1105 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1106 le32_to_cpu(region->len));
1107 if (ret != 0) {
1108 adsp_err(dsp,
1109 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
1110 file, regions,
1111 le32_to_cpu(region->len), offset,
1112 region_name, ret);
1113 goto out_fw;
1114 }
1115 }
1116
1117 pos += le32_to_cpu(region->len) + sizeof(*region);
1118 regions++;
1119 }
1120
1121 ret = regmap_async_complete(regmap);
1122 if (ret != 0) {
1123 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
1124 goto out_fw;
1125 }
1126
1127 if (pos > firmware->size)
1128 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1129 file, regions, pos - firmware->size);
1130
1131 out_fw:
1132 regmap_async_complete(regmap);
1133 wm_adsp_buf_free(&buf_list);
1134 release_firmware(firmware);
1135 out:
1136 kfree(file);
1137
1138 return ret;
1139 }
1140
1141 static void wm_adsp_ctl_fixup_base(struct wm_adsp *dsp,
1142 const struct wm_adsp_alg_region *alg_region)
1143 {
1144 struct wm_coeff_ctl *ctl;
1145
1146 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1147 if (ctl->fw_name == wm_adsp_fw_text[dsp->fw] &&
1148 alg_region->alg == ctl->alg_region.alg &&
1149 alg_region->type == ctl->alg_region.type) {
1150 ctl->alg_region.base = alg_region->base;
1151 }
1152 }
1153 }
1154
1155 static void *wm_adsp_read_algs(struct wm_adsp *dsp, size_t n_algs,
1156 unsigned int pos, unsigned int len)
1157 {
1158 void *alg;
1159 int ret;
1160 __be32 val;
1161
1162 if (n_algs == 0) {
1163 adsp_err(dsp, "No algorithms\n");
1164 return ERR_PTR(-EINVAL);
1165 }
1166
1167 if (n_algs > 1024) {
1168 adsp_err(dsp, "Algorithm count %zx excessive\n", n_algs);
1169 return ERR_PTR(-EINVAL);
1170 }
1171
1172 /* Read the terminator first to validate the length */
1173 ret = regmap_raw_read(dsp->regmap, pos + len, &val, sizeof(val));
1174 if (ret != 0) {
1175 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
1176 ret);
1177 return ERR_PTR(ret);
1178 }
1179
1180 if (be32_to_cpu(val) != 0xbedead)
1181 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbeadead\n",
1182 pos + len, be32_to_cpu(val));
1183
1184 alg = kzalloc(len * 2, GFP_KERNEL | GFP_DMA);
1185 if (!alg)
1186 return ERR_PTR(-ENOMEM);
1187
1188 ret = regmap_raw_read(dsp->regmap, pos, alg, len * 2);
1189 if (ret != 0) {
1190 adsp_err(dsp, "Failed to read algorithm list: %d\n",
1191 ret);
1192 kfree(alg);
1193 return ERR_PTR(ret);
1194 }
1195
1196 return alg;
1197 }
1198
1199 static struct wm_adsp_alg_region *wm_adsp_create_region(struct wm_adsp *dsp,
1200 int type, __be32 id,
1201 __be32 base)
1202 {
1203 struct wm_adsp_alg_region *alg_region;
1204
1205 alg_region = kzalloc(sizeof(*alg_region), GFP_KERNEL);
1206 if (!alg_region)
1207 return ERR_PTR(-ENOMEM);
1208
1209 alg_region->type = type;
1210 alg_region->alg = be32_to_cpu(id);
1211 alg_region->base = be32_to_cpu(base);
1212
1213 list_add_tail(&alg_region->list, &dsp->alg_regions);
1214
1215 if (dsp->fw_ver > 0)
1216 wm_adsp_ctl_fixup_base(dsp, alg_region);
1217
1218 return alg_region;
1219 }
1220
1221 static int wm_adsp1_setup_algs(struct wm_adsp *dsp)
1222 {
1223 struct wmfw_adsp1_id_hdr adsp1_id;
1224 struct wmfw_adsp1_alg_hdr *adsp1_alg;
1225 struct wm_adsp_alg_region *alg_region;
1226 const struct wm_adsp_region *mem;
1227 unsigned int pos, len;
1228 size_t n_algs;
1229 int i, ret;
1230
1231 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
1232 if (WARN_ON(!mem))
1233 return -EINVAL;
1234
1235 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id,
1236 sizeof(adsp1_id));
1237 if (ret != 0) {
1238 adsp_err(dsp, "Failed to read algorithm info: %d\n",
1239 ret);
1240 return ret;
1241 }
1242
1243 n_algs = be32_to_cpu(adsp1_id.n_algs);
1244 dsp->fw_id = be32_to_cpu(adsp1_id.fw.id);
1245 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
1246 dsp->fw_id,
1247 (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16,
1248 (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8,
1249 be32_to_cpu(adsp1_id.fw.ver) & 0xff,
1250 n_algs);
1251
1252 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
1253 adsp1_id.fw.id, adsp1_id.zm);
1254 if (IS_ERR(alg_region))
1255 return PTR_ERR(alg_region);
1256
1257 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
1258 adsp1_id.fw.id, adsp1_id.dm);
1259 if (IS_ERR(alg_region))
1260 return PTR_ERR(alg_region);
1261
1262 pos = sizeof(adsp1_id) / 2;
1263 len = (sizeof(*adsp1_alg) * n_algs) / 2;
1264
1265 adsp1_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len);
1266 if (IS_ERR(adsp1_alg))
1267 return PTR_ERR(adsp1_alg);
1268
1269 for (i = 0; i < n_algs; i++) {
1270 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
1271 i, be32_to_cpu(adsp1_alg[i].alg.id),
1272 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
1273 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
1274 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
1275 be32_to_cpu(adsp1_alg[i].dm),
1276 be32_to_cpu(adsp1_alg[i].zm));
1277
1278 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
1279 adsp1_alg[i].alg.id,
1280 adsp1_alg[i].dm);
1281 if (IS_ERR(alg_region)) {
1282 ret = PTR_ERR(alg_region);
1283 goto out;
1284 }
1285 if (dsp->fw_ver == 0) {
1286 if (i + 1 < n_algs) {
1287 len = be32_to_cpu(adsp1_alg[i + 1].dm);
1288 len -= be32_to_cpu(adsp1_alg[i].dm);
1289 len *= 4;
1290 wm_adsp_create_control(dsp, alg_region, 0,
1291 len, NULL, 0, 0);
1292 } else {
1293 adsp_warn(dsp, "Missing length info for region DM with ID %x\n",
1294 be32_to_cpu(adsp1_alg[i].alg.id));
1295 }
1296 }
1297
1298 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
1299 adsp1_alg[i].alg.id,
1300 adsp1_alg[i].zm);
1301 if (IS_ERR(alg_region)) {
1302 ret = PTR_ERR(alg_region);
1303 goto out;
1304 }
1305 if (dsp->fw_ver == 0) {
1306 if (i + 1 < n_algs) {
1307 len = be32_to_cpu(adsp1_alg[i + 1].zm);
1308 len -= be32_to_cpu(adsp1_alg[i].zm);
1309 len *= 4;
1310 wm_adsp_create_control(dsp, alg_region, 0,
1311 len, NULL, 0, 0);
1312 } else {
1313 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
1314 be32_to_cpu(adsp1_alg[i].alg.id));
1315 }
1316 }
1317 }
1318
1319 out:
1320 kfree(adsp1_alg);
1321 return ret;
1322 }
1323
1324 static int wm_adsp2_setup_algs(struct wm_adsp *dsp)
1325 {
1326 struct wmfw_adsp2_id_hdr adsp2_id;
1327 struct wmfw_adsp2_alg_hdr *adsp2_alg;
1328 struct wm_adsp_alg_region *alg_region;
1329 const struct wm_adsp_region *mem;
1330 unsigned int pos, len;
1331 size_t n_algs;
1332 int i, ret;
1333
1334 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
1335 if (WARN_ON(!mem))
1336 return -EINVAL;
1337
1338 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id,
1339 sizeof(adsp2_id));
1340 if (ret != 0) {
1341 adsp_err(dsp, "Failed to read algorithm info: %d\n",
1342 ret);
1343 return ret;
1344 }
1345
1346 n_algs = be32_to_cpu(adsp2_id.n_algs);
1347 dsp->fw_id = be32_to_cpu(adsp2_id.fw.id);
1348 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
1349 dsp->fw_id,
1350 (be32_to_cpu(adsp2_id.fw.ver) & 0xff0000) >> 16,
1351 (be32_to_cpu(adsp2_id.fw.ver) & 0xff00) >> 8,
1352 be32_to_cpu(adsp2_id.fw.ver) & 0xff,
1353 n_algs);
1354
1355 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
1356 adsp2_id.fw.id, adsp2_id.xm);
1357 if (IS_ERR(alg_region))
1358 return PTR_ERR(alg_region);
1359
1360 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
1361 adsp2_id.fw.id, adsp2_id.ym);
1362 if (IS_ERR(alg_region))
1363 return PTR_ERR(alg_region);
1364
1365 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
1366 adsp2_id.fw.id, adsp2_id.zm);
1367 if (IS_ERR(alg_region))
1368 return PTR_ERR(alg_region);
1369
1370 pos = sizeof(adsp2_id) / 2;
1371 len = (sizeof(*adsp2_alg) * n_algs) / 2;
1372
1373 adsp2_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len);
1374 if (IS_ERR(adsp2_alg))
1375 return PTR_ERR(adsp2_alg);
1376
1377 for (i = 0; i < n_algs; i++) {
1378 adsp_info(dsp,
1379 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
1380 i, be32_to_cpu(adsp2_alg[i].alg.id),
1381 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
1382 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
1383 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
1384 be32_to_cpu(adsp2_alg[i].xm),
1385 be32_to_cpu(adsp2_alg[i].ym),
1386 be32_to_cpu(adsp2_alg[i].zm));
1387
1388 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
1389 adsp2_alg[i].alg.id,
1390 adsp2_alg[i].xm);
1391 if (IS_ERR(alg_region)) {
1392 ret = PTR_ERR(alg_region);
1393 goto out;
1394 }
1395 if (dsp->fw_ver == 0) {
1396 if (i + 1 < n_algs) {
1397 len = be32_to_cpu(adsp2_alg[i + 1].xm);
1398 len -= be32_to_cpu(adsp2_alg[i].xm);
1399 len *= 4;
1400 wm_adsp_create_control(dsp, alg_region, 0,
1401 len, NULL, 0, 0);
1402 } else {
1403 adsp_warn(dsp, "Missing length info for region XM with ID %x\n",
1404 be32_to_cpu(adsp2_alg[i].alg.id));
1405 }
1406 }
1407
1408 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
1409 adsp2_alg[i].alg.id,
1410 adsp2_alg[i].ym);
1411 if (IS_ERR(alg_region)) {
1412 ret = PTR_ERR(alg_region);
1413 goto out;
1414 }
1415 if (dsp->fw_ver == 0) {
1416 if (i + 1 < n_algs) {
1417 len = be32_to_cpu(adsp2_alg[i + 1].ym);
1418 len -= be32_to_cpu(adsp2_alg[i].ym);
1419 len *= 4;
1420 wm_adsp_create_control(dsp, alg_region, 0,
1421 len, NULL, 0, 0);
1422 } else {
1423 adsp_warn(dsp, "Missing length info for region YM with ID %x\n",
1424 be32_to_cpu(adsp2_alg[i].alg.id));
1425 }
1426 }
1427
1428 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
1429 adsp2_alg[i].alg.id,
1430 adsp2_alg[i].zm);
1431 if (IS_ERR(alg_region)) {
1432 ret = PTR_ERR(alg_region);
1433 goto out;
1434 }
1435 if (dsp->fw_ver == 0) {
1436 if (i + 1 < n_algs) {
1437 len = be32_to_cpu(adsp2_alg[i + 1].zm);
1438 len -= be32_to_cpu(adsp2_alg[i].zm);
1439 len *= 4;
1440 wm_adsp_create_control(dsp, alg_region, 0,
1441 len, NULL, 0, 0);
1442 } else {
1443 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
1444 be32_to_cpu(adsp2_alg[i].alg.id));
1445 }
1446 }
1447 }
1448
1449 out:
1450 kfree(adsp2_alg);
1451 return ret;
1452 }
1453
1454 static int wm_adsp_load_coeff(struct wm_adsp *dsp)
1455 {
1456 LIST_HEAD(buf_list);
1457 struct regmap *regmap = dsp->regmap;
1458 struct wmfw_coeff_hdr *hdr;
1459 struct wmfw_coeff_item *blk;
1460 const struct firmware *firmware;
1461 const struct wm_adsp_region *mem;
1462 struct wm_adsp_alg_region *alg_region;
1463 const char *region_name;
1464 int ret, pos, blocks, type, offset, reg;
1465 char *file;
1466 struct wm_adsp_buf *buf;
1467
1468 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1469 if (file == NULL)
1470 return -ENOMEM;
1471
1472 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, dsp->num,
1473 wm_adsp_fw[dsp->fw].file);
1474 file[PAGE_SIZE - 1] = '\0';
1475
1476 ret = request_firmware(&firmware, file, dsp->dev);
1477 if (ret != 0) {
1478 adsp_warn(dsp, "Failed to request '%s'\n", file);
1479 ret = 0;
1480 goto out;
1481 }
1482 ret = -EINVAL;
1483
1484 if (sizeof(*hdr) >= firmware->size) {
1485 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1486 file, firmware->size);
1487 goto out_fw;
1488 }
1489
1490 hdr = (void*)&firmware->data[0];
1491 if (memcmp(hdr->magic, "WMDR", 4) != 0) {
1492 adsp_err(dsp, "%s: invalid magic\n", file);
1493 goto out_fw;
1494 }
1495
1496 switch (be32_to_cpu(hdr->rev) & 0xff) {
1497 case 1:
1498 break;
1499 default:
1500 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
1501 file, be32_to_cpu(hdr->rev) & 0xff);
1502 ret = -EINVAL;
1503 goto out_fw;
1504 }
1505
1506 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
1507 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
1508 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
1509 le32_to_cpu(hdr->ver) & 0xff);
1510
1511 pos = le32_to_cpu(hdr->len);
1512
1513 blocks = 0;
1514 while (pos < firmware->size &&
1515 pos - firmware->size > sizeof(*blk)) {
1516 blk = (void*)(&firmware->data[pos]);
1517
1518 type = le16_to_cpu(blk->type);
1519 offset = le16_to_cpu(blk->offset);
1520
1521 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
1522 file, blocks, le32_to_cpu(blk->id),
1523 (le32_to_cpu(blk->ver) >> 16) & 0xff,
1524 (le32_to_cpu(blk->ver) >> 8) & 0xff,
1525 le32_to_cpu(blk->ver) & 0xff);
1526 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
1527 file, blocks, le32_to_cpu(blk->len), offset, type);
1528
1529 reg = 0;
1530 region_name = "Unknown";
1531 switch (type) {
1532 case (WMFW_NAME_TEXT << 8):
1533 case (WMFW_INFO_TEXT << 8):
1534 break;
1535 case (WMFW_ABSOLUTE << 8):
1536 /*
1537 * Old files may use this for global
1538 * coefficients.
1539 */
1540 if (le32_to_cpu(blk->id) == dsp->fw_id &&
1541 offset == 0) {
1542 region_name = "global coefficients";
1543 mem = wm_adsp_find_region(dsp, type);
1544 if (!mem) {
1545 adsp_err(dsp, "No ZM\n");
1546 break;
1547 }
1548 reg = wm_adsp_region_to_reg(mem, 0);
1549
1550 } else {
1551 region_name = "register";
1552 reg = offset;
1553 }
1554 break;
1555
1556 case WMFW_ADSP1_DM:
1557 case WMFW_ADSP1_ZM:
1558 case WMFW_ADSP2_XM:
1559 case WMFW_ADSP2_YM:
1560 adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
1561 file, blocks, le32_to_cpu(blk->len),
1562 type, le32_to_cpu(blk->id));
1563
1564 mem = wm_adsp_find_region(dsp, type);
1565 if (!mem) {
1566 adsp_err(dsp, "No base for region %x\n", type);
1567 break;
1568 }
1569
1570 reg = 0;
1571 list_for_each_entry(alg_region,
1572 &dsp->alg_regions, list) {
1573 if (le32_to_cpu(blk->id) == alg_region->alg &&
1574 type == alg_region->type) {
1575 reg = alg_region->base;
1576 reg = wm_adsp_region_to_reg(mem,
1577 reg);
1578 reg += offset;
1579 break;
1580 }
1581 }
1582
1583 if (reg == 0)
1584 adsp_err(dsp, "No %x for algorithm %x\n",
1585 type, le32_to_cpu(blk->id));
1586 break;
1587
1588 default:
1589 adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
1590 file, blocks, type, pos);
1591 break;
1592 }
1593
1594 if (reg) {
1595 buf = wm_adsp_buf_alloc(blk->data,
1596 le32_to_cpu(blk->len),
1597 &buf_list);
1598 if (!buf) {
1599 adsp_err(dsp, "Out of memory\n");
1600 ret = -ENOMEM;
1601 goto out_fw;
1602 }
1603
1604 adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
1605 file, blocks, le32_to_cpu(blk->len),
1606 reg);
1607 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1608 le32_to_cpu(blk->len));
1609 if (ret != 0) {
1610 adsp_err(dsp,
1611 "%s.%d: Failed to write to %x in %s: %d\n",
1612 file, blocks, reg, region_name, ret);
1613 }
1614 }
1615
1616 pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03;
1617 blocks++;
1618 }
1619
1620 ret = regmap_async_complete(regmap);
1621 if (ret != 0)
1622 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
1623
1624 if (pos > firmware->size)
1625 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1626 file, blocks, pos - firmware->size);
1627
1628 out_fw:
1629 regmap_async_complete(regmap);
1630 release_firmware(firmware);
1631 wm_adsp_buf_free(&buf_list);
1632 out:
1633 kfree(file);
1634 return ret;
1635 }
1636
1637 int wm_adsp1_init(struct wm_adsp *dsp)
1638 {
1639 INIT_LIST_HEAD(&dsp->alg_regions);
1640
1641 return 0;
1642 }
1643 EXPORT_SYMBOL_GPL(wm_adsp1_init);
1644
1645 int wm_adsp1_event(struct snd_soc_dapm_widget *w,
1646 struct snd_kcontrol *kcontrol,
1647 int event)
1648 {
1649 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1650 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
1651 struct wm_adsp *dsp = &dsps[w->shift];
1652 struct wm_adsp_alg_region *alg_region;
1653 struct wm_coeff_ctl *ctl;
1654 int ret;
1655 int val;
1656
1657 dsp->card = codec->component.card;
1658
1659 switch (event) {
1660 case SND_SOC_DAPM_POST_PMU:
1661 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1662 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
1663
1664 /*
1665 * For simplicity set the DSP clock rate to be the
1666 * SYSCLK rate rather than making it configurable.
1667 */
1668 if(dsp->sysclk_reg) {
1669 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
1670 if (ret != 0) {
1671 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
1672 ret);
1673 return ret;
1674 }
1675
1676 val = (val & dsp->sysclk_mask)
1677 >> dsp->sysclk_shift;
1678
1679 ret = regmap_update_bits(dsp->regmap,
1680 dsp->base + ADSP1_CONTROL_31,
1681 ADSP1_CLK_SEL_MASK, val);
1682 if (ret != 0) {
1683 adsp_err(dsp, "Failed to set clock rate: %d\n",
1684 ret);
1685 return ret;
1686 }
1687 }
1688
1689 ret = wm_adsp_load(dsp);
1690 if (ret != 0)
1691 goto err;
1692
1693 ret = wm_adsp1_setup_algs(dsp);
1694 if (ret != 0)
1695 goto err;
1696
1697 ret = wm_adsp_load_coeff(dsp);
1698 if (ret != 0)
1699 goto err;
1700
1701 /* Initialize caches for enabled and unset controls */
1702 ret = wm_coeff_init_control_caches(dsp);
1703 if (ret != 0)
1704 goto err;
1705
1706 /* Sync set controls */
1707 ret = wm_coeff_sync_controls(dsp);
1708 if (ret != 0)
1709 goto err;
1710
1711 /* Start the core running */
1712 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1713 ADSP1_CORE_ENA | ADSP1_START,
1714 ADSP1_CORE_ENA | ADSP1_START);
1715 break;
1716
1717 case SND_SOC_DAPM_PRE_PMD:
1718 /* Halt the core */
1719 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1720 ADSP1_CORE_ENA | ADSP1_START, 0);
1721
1722 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
1723 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
1724
1725 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1726 ADSP1_SYS_ENA, 0);
1727
1728 list_for_each_entry(ctl, &dsp->ctl_list, list)
1729 ctl->enabled = 0;
1730
1731 while (!list_empty(&dsp->alg_regions)) {
1732 alg_region = list_first_entry(&dsp->alg_regions,
1733 struct wm_adsp_alg_region,
1734 list);
1735 list_del(&alg_region->list);
1736 kfree(alg_region);
1737 }
1738 break;
1739
1740 default:
1741 break;
1742 }
1743
1744 return 0;
1745
1746 err:
1747 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1748 ADSP1_SYS_ENA, 0);
1749 return ret;
1750 }
1751 EXPORT_SYMBOL_GPL(wm_adsp1_event);
1752
1753 static int wm_adsp2_ena(struct wm_adsp *dsp)
1754 {
1755 unsigned int val;
1756 int ret, count;
1757
1758 ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL,
1759 ADSP2_SYS_ENA, ADSP2_SYS_ENA);
1760 if (ret != 0)
1761 return ret;
1762
1763 /* Wait for the RAM to start, should be near instantaneous */
1764 for (count = 0; count < 10; ++count) {
1765 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1,
1766 &val);
1767 if (ret != 0)
1768 return ret;
1769
1770 if (val & ADSP2_RAM_RDY)
1771 break;
1772
1773 msleep(1);
1774 }
1775
1776 if (!(val & ADSP2_RAM_RDY)) {
1777 adsp_err(dsp, "Failed to start DSP RAM\n");
1778 return -EBUSY;
1779 }
1780
1781 adsp_dbg(dsp, "RAM ready after %d polls\n", count);
1782
1783 return 0;
1784 }
1785
1786 static void wm_adsp2_boot_work(struct work_struct *work)
1787 {
1788 struct wm_adsp *dsp = container_of(work,
1789 struct wm_adsp,
1790 boot_work);
1791 int ret;
1792 unsigned int val;
1793
1794 /*
1795 * For simplicity set the DSP clock rate to be the
1796 * SYSCLK rate rather than making it configurable.
1797 */
1798 ret = regmap_read(dsp->regmap, ARIZONA_SYSTEM_CLOCK_1, &val);
1799 if (ret != 0) {
1800 adsp_err(dsp, "Failed to read SYSCLK state: %d\n", ret);
1801 return;
1802 }
1803 val = (val & ARIZONA_SYSCLK_FREQ_MASK)
1804 >> ARIZONA_SYSCLK_FREQ_SHIFT;
1805
1806 ret = regmap_update_bits_async(dsp->regmap,
1807 dsp->base + ADSP2_CLOCKING,
1808 ADSP2_CLK_SEL_MASK, val);
1809 if (ret != 0) {
1810 adsp_err(dsp, "Failed to set clock rate: %d\n", ret);
1811 return;
1812 }
1813
1814 if (dsp->dvfs) {
1815 ret = regmap_read(dsp->regmap,
1816 dsp->base + ADSP2_CLOCKING, &val);
1817 if (ret != 0) {
1818 adsp_err(dsp, "Failed to read clocking: %d\n", ret);
1819 return;
1820 }
1821
1822 if ((val & ADSP2_CLK_SEL_MASK) >= 3) {
1823 ret = regulator_enable(dsp->dvfs);
1824 if (ret != 0) {
1825 adsp_err(dsp,
1826 "Failed to enable supply: %d\n",
1827 ret);
1828 return;
1829 }
1830
1831 ret = regulator_set_voltage(dsp->dvfs,
1832 1800000,
1833 1800000);
1834 if (ret != 0) {
1835 adsp_err(dsp,
1836 "Failed to raise supply: %d\n",
1837 ret);
1838 return;
1839 }
1840 }
1841 }
1842
1843 ret = wm_adsp2_ena(dsp);
1844 if (ret != 0)
1845 return;
1846
1847 ret = wm_adsp_load(dsp);
1848 if (ret != 0)
1849 goto err;
1850
1851 ret = wm_adsp2_setup_algs(dsp);
1852 if (ret != 0)
1853 goto err;
1854
1855 ret = wm_adsp_load_coeff(dsp);
1856 if (ret != 0)
1857 goto err;
1858
1859 /* Initialize caches for enabled and unset controls */
1860 ret = wm_coeff_init_control_caches(dsp);
1861 if (ret != 0)
1862 goto err;
1863
1864 /* Sync set controls */
1865 ret = wm_coeff_sync_controls(dsp);
1866 if (ret != 0)
1867 goto err;
1868
1869 dsp->running = true;
1870
1871 return;
1872
1873 err:
1874 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
1875 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
1876 }
1877
1878 int wm_adsp2_early_event(struct snd_soc_dapm_widget *w,
1879 struct snd_kcontrol *kcontrol, int event)
1880 {
1881 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1882 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
1883 struct wm_adsp *dsp = &dsps[w->shift];
1884
1885 dsp->card = codec->component.card;
1886
1887 switch (event) {
1888 case SND_SOC_DAPM_PRE_PMU:
1889 queue_work(system_unbound_wq, &dsp->boot_work);
1890 break;
1891 default:
1892 break;
1893 }
1894
1895 return 0;
1896 }
1897 EXPORT_SYMBOL_GPL(wm_adsp2_early_event);
1898
1899 int wm_adsp2_event(struct snd_soc_dapm_widget *w,
1900 struct snd_kcontrol *kcontrol, int event)
1901 {
1902 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1903 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
1904 struct wm_adsp *dsp = &dsps[w->shift];
1905 struct wm_adsp_alg_region *alg_region;
1906 struct wm_coeff_ctl *ctl;
1907 int ret;
1908
1909 switch (event) {
1910 case SND_SOC_DAPM_POST_PMU:
1911 flush_work(&dsp->boot_work);
1912
1913 if (!dsp->running)
1914 return -EIO;
1915
1916 ret = regmap_update_bits(dsp->regmap,
1917 dsp->base + ADSP2_CONTROL,
1918 ADSP2_CORE_ENA | ADSP2_START,
1919 ADSP2_CORE_ENA | ADSP2_START);
1920 if (ret != 0)
1921 goto err;
1922 break;
1923
1924 case SND_SOC_DAPM_PRE_PMD:
1925 /* Log firmware state, it can be useful for analysis */
1926 wm_adsp2_show_fw_status(dsp);
1927
1928 dsp->running = false;
1929
1930 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
1931 ADSP2_SYS_ENA | ADSP2_CORE_ENA |
1932 ADSP2_START, 0);
1933
1934 /* Make sure DMAs are quiesced */
1935 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
1936 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0);
1937 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
1938
1939 if (dsp->dvfs) {
1940 ret = regulator_set_voltage(dsp->dvfs, 1200000,
1941 1800000);
1942 if (ret != 0)
1943 adsp_warn(dsp,
1944 "Failed to lower supply: %d\n",
1945 ret);
1946
1947 ret = regulator_disable(dsp->dvfs);
1948 if (ret != 0)
1949 adsp_err(dsp,
1950 "Failed to enable supply: %d\n",
1951 ret);
1952 }
1953
1954 list_for_each_entry(ctl, &dsp->ctl_list, list)
1955 ctl->enabled = 0;
1956
1957 while (!list_empty(&dsp->alg_regions)) {
1958 alg_region = list_first_entry(&dsp->alg_regions,
1959 struct wm_adsp_alg_region,
1960 list);
1961 list_del(&alg_region->list);
1962 kfree(alg_region);
1963 }
1964
1965 adsp_dbg(dsp, "Shutdown complete\n");
1966 break;
1967
1968 default:
1969 break;
1970 }
1971
1972 return 0;
1973 err:
1974 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
1975 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
1976 return ret;
1977 }
1978 EXPORT_SYMBOL_GPL(wm_adsp2_event);
1979
1980 int wm_adsp2_init(struct wm_adsp *dsp, bool dvfs)
1981 {
1982 int ret;
1983
1984 /*
1985 * Disable the DSP memory by default when in reset for a small
1986 * power saving.
1987 */
1988 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
1989 ADSP2_MEM_ENA, 0);
1990 if (ret != 0) {
1991 adsp_err(dsp, "Failed to clear memory retention: %d\n", ret);
1992 return ret;
1993 }
1994
1995 INIT_LIST_HEAD(&dsp->alg_regions);
1996 INIT_LIST_HEAD(&dsp->ctl_list);
1997 INIT_WORK(&dsp->boot_work, wm_adsp2_boot_work);
1998
1999 if (dvfs) {
2000 dsp->dvfs = devm_regulator_get(dsp->dev, "DCVDD");
2001 if (IS_ERR(dsp->dvfs)) {
2002 ret = PTR_ERR(dsp->dvfs);
2003 adsp_err(dsp, "Failed to get DCVDD: %d\n", ret);
2004 return ret;
2005 }
2006
2007 ret = regulator_enable(dsp->dvfs);
2008 if (ret != 0) {
2009 adsp_err(dsp, "Failed to enable DCVDD: %d\n", ret);
2010 return ret;
2011 }
2012
2013 ret = regulator_set_voltage(dsp->dvfs, 1200000, 1800000);
2014 if (ret != 0) {
2015 adsp_err(dsp, "Failed to initialise DVFS: %d\n", ret);
2016 return ret;
2017 }
2018
2019 ret = regulator_disable(dsp->dvfs);
2020 if (ret != 0) {
2021 adsp_err(dsp, "Failed to disable DCVDD: %d\n", ret);
2022 return ret;
2023 }
2024 }
2025
2026 return 0;
2027 }
2028 EXPORT_SYMBOL_GPL(wm_adsp2_init);
2029
2030 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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