2 * wm_adsp.c -- Wolfson ADSP support
4 * Copyright 2012 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/firmware.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/regmap.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/slab.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
27 #include <sound/jack.h>
28 #include <sound/initval.h>
29 #include <sound/tlv.h>
31 #include <linux/mfd/arizona/registers.h>
35 #define adsp_crit(_dsp, fmt, ...) \
36 dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
37 #define adsp_err(_dsp, fmt, ...) \
38 dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
39 #define adsp_warn(_dsp, fmt, ...) \
40 dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
41 #define adsp_info(_dsp, fmt, ...) \
42 dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
43 #define adsp_dbg(_dsp, fmt, ...) \
44 dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
46 #define ADSP1_CONTROL_1 0x00
47 #define ADSP1_CONTROL_2 0x02
48 #define ADSP1_CONTROL_3 0x03
49 #define ADSP1_CONTROL_4 0x04
50 #define ADSP1_CONTROL_5 0x06
51 #define ADSP1_CONTROL_6 0x07
52 #define ADSP1_CONTROL_7 0x08
53 #define ADSP1_CONTROL_8 0x09
54 #define ADSP1_CONTROL_9 0x0A
55 #define ADSP1_CONTROL_10 0x0B
56 #define ADSP1_CONTROL_11 0x0C
57 #define ADSP1_CONTROL_12 0x0D
58 #define ADSP1_CONTROL_13 0x0F
59 #define ADSP1_CONTROL_14 0x10
60 #define ADSP1_CONTROL_15 0x11
61 #define ADSP1_CONTROL_16 0x12
62 #define ADSP1_CONTROL_17 0x13
63 #define ADSP1_CONTROL_18 0x14
64 #define ADSP1_CONTROL_19 0x16
65 #define ADSP1_CONTROL_20 0x17
66 #define ADSP1_CONTROL_21 0x18
67 #define ADSP1_CONTROL_22 0x1A
68 #define ADSP1_CONTROL_23 0x1B
69 #define ADSP1_CONTROL_24 0x1C
70 #define ADSP1_CONTROL_25 0x1E
71 #define ADSP1_CONTROL_26 0x20
72 #define ADSP1_CONTROL_27 0x21
73 #define ADSP1_CONTROL_28 0x22
74 #define ADSP1_CONTROL_29 0x23
75 #define ADSP1_CONTROL_30 0x24
76 #define ADSP1_CONTROL_31 0x26
81 #define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
82 #define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
83 #define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
89 #define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
90 #define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
91 #define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
92 #define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
93 #define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
94 #define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
95 #define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
96 #define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
97 #define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
98 #define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
99 #define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
100 #define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
101 #define ADSP1_START 0x0001 /* DSP1_START */
102 #define ADSP1_START_MASK 0x0001 /* DSP1_START */
103 #define ADSP1_START_SHIFT 0 /* DSP1_START */
104 #define ADSP1_START_WIDTH 1 /* DSP1_START */
109 #define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
110 #define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
111 #define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
113 #define ADSP2_CONTROL 0
114 #define ADSP2_CLOCKING 1
115 #define ADSP2_STATUS1 4
121 #define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
122 #define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
123 #define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
124 #define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
125 #define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
126 #define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
127 #define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
128 #define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
129 #define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
130 #define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
131 #define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
132 #define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
133 #define ADSP2_START 0x0001 /* DSP1_START */
134 #define ADSP2_START_MASK 0x0001 /* DSP1_START */
135 #define ADSP2_START_SHIFT 0 /* DSP1_START */
136 #define ADSP2_START_WIDTH 1 /* DSP1_START */
141 #define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
142 #define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
143 #define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
148 #define ADSP2_RAM_RDY 0x0001
149 #define ADSP2_RAM_RDY_MASK 0x0001
150 #define ADSP2_RAM_RDY_SHIFT 0
151 #define ADSP2_RAM_RDY_WIDTH 1
153 #define WM_ADSP_NUM_FW 3
155 static const char *wm_adsp_fw_text
[WM_ADSP_NUM_FW
] = {
156 "MBC/VSS", "Tx", "Rx ANC"
161 } wm_adsp_fw
[WM_ADSP_NUM_FW
] = {
162 { .file
= "mbc-vss" },
164 { .file
= "rx-anc" },
167 static int wm_adsp_fw_get(struct snd_kcontrol
*kcontrol
,
168 struct snd_ctl_elem_value
*ucontrol
)
170 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
171 struct soc_enum
*e
= (struct soc_enum
*)kcontrol
->private_value
;
172 struct wm_adsp
*adsp
= snd_soc_codec_get_drvdata(codec
);
174 ucontrol
->value
.integer
.value
[0] = adsp
[e
->shift_l
].fw
;
179 static int wm_adsp_fw_put(struct snd_kcontrol
*kcontrol
,
180 struct snd_ctl_elem_value
*ucontrol
)
182 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
183 struct soc_enum
*e
= (struct soc_enum
*)kcontrol
->private_value
;
184 struct wm_adsp
*adsp
= snd_soc_codec_get_drvdata(codec
);
186 if (ucontrol
->value
.integer
.value
[0] == adsp
[e
->shift_l
].fw
)
189 if (ucontrol
->value
.integer
.value
[0] >= WM_ADSP_NUM_FW
)
192 if (adsp
[e
->shift_l
].running
)
195 adsp
->fw
= ucontrol
->value
.integer
.value
[0];
200 static const struct soc_enum wm_adsp_fw_enum
[] = {
201 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text
), wm_adsp_fw_text
),
202 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text
), wm_adsp_fw_text
),
203 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text
), wm_adsp_fw_text
),
204 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text
), wm_adsp_fw_text
),
207 const struct snd_kcontrol_new wm_adsp_fw_controls
[] = {
208 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum
[0],
209 wm_adsp_fw_get
, wm_adsp_fw_put
),
210 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum
[1],
211 wm_adsp_fw_get
, wm_adsp_fw_put
),
212 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum
[2],
213 wm_adsp_fw_get
, wm_adsp_fw_put
),
214 SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum
[3],
215 wm_adsp_fw_get
, wm_adsp_fw_put
),
217 EXPORT_SYMBOL_GPL(wm_adsp_fw_controls
);
219 static struct wm_adsp_region
const *wm_adsp_find_region(struct wm_adsp
*dsp
,
224 for (i
= 0; i
< dsp
->num_mems
; i
++)
225 if (dsp
->mem
[i
].type
== type
)
231 static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region
const *region
,
234 switch (region
->type
) {
236 return region
->base
+ (offset
* 3);
238 return region
->base
+ (offset
* 2);
240 return region
->base
+ (offset
* 2);
242 return region
->base
+ (offset
* 2);
244 return region
->base
+ (offset
* 2);
246 WARN_ON(NULL
!= "Unknown memory region type");
251 static int wm_adsp_load(struct wm_adsp
*dsp
)
253 const struct firmware
*firmware
;
254 struct regmap
*regmap
= dsp
->regmap
;
255 unsigned int pos
= 0;
256 const struct wmfw_header
*header
;
257 const struct wmfw_adsp1_sizes
*adsp1_sizes
;
258 const struct wmfw_adsp2_sizes
*adsp2_sizes
;
259 const struct wmfw_footer
*footer
;
260 const struct wmfw_region
*region
;
261 const struct wm_adsp_region
*mem
;
262 const char *region_name
;
267 int ret
, offset
, type
, sizes
;
269 file
= kzalloc(PAGE_SIZE
, GFP_KERNEL
);
273 snprintf(file
, PAGE_SIZE
, "%s-dsp%d-%s.wmfw", dsp
->part
, dsp
->num
,
274 wm_adsp_fw
[dsp
->fw
].file
);
275 file
[PAGE_SIZE
- 1] = '\0';
277 ret
= request_firmware(&firmware
, file
, dsp
->dev
);
279 adsp_err(dsp
, "Failed to request '%s'\n", file
);
284 pos
= sizeof(*header
) + sizeof(*adsp1_sizes
) + sizeof(*footer
);
285 if (pos
>= firmware
->size
) {
286 adsp_err(dsp
, "%s: file too short, %zu bytes\n",
287 file
, firmware
->size
);
291 header
= (void*)&firmware
->data
[0];
293 if (memcmp(&header
->magic
[0], "WMFW", 4) != 0) {
294 adsp_err(dsp
, "%s: invalid magic\n", file
);
298 if (header
->ver
!= 0) {
299 adsp_err(dsp
, "%s: unknown file format %d\n",
304 if (header
->core
!= dsp
->type
) {
305 adsp_err(dsp
, "%s: invalid core %d != %d\n",
306 file
, header
->core
, dsp
->type
);
312 pos
= sizeof(*header
) + sizeof(*adsp1_sizes
) + sizeof(*footer
);
313 adsp1_sizes
= (void *)&(header
[1]);
314 footer
= (void *)&(adsp1_sizes
[1]);
315 sizes
= sizeof(*adsp1_sizes
);
317 adsp_dbg(dsp
, "%s: %d DM, %d PM, %d ZM\n",
318 file
, le32_to_cpu(adsp1_sizes
->dm
),
319 le32_to_cpu(adsp1_sizes
->pm
),
320 le32_to_cpu(adsp1_sizes
->zm
));
324 pos
= sizeof(*header
) + sizeof(*adsp2_sizes
) + sizeof(*footer
);
325 adsp2_sizes
= (void *)&(header
[1]);
326 footer
= (void *)&(adsp2_sizes
[1]);
327 sizes
= sizeof(*adsp2_sizes
);
329 adsp_dbg(dsp
, "%s: %d XM, %d YM %d PM, %d ZM\n",
330 file
, le32_to_cpu(adsp2_sizes
->xm
),
331 le32_to_cpu(adsp2_sizes
->ym
),
332 le32_to_cpu(adsp2_sizes
->pm
),
333 le32_to_cpu(adsp2_sizes
->zm
));
337 BUG_ON(NULL
== "Unknown DSP type");
341 if (le32_to_cpu(header
->len
) != sizeof(*header
) +
342 sizes
+ sizeof(*footer
)) {
343 adsp_err(dsp
, "%s: unexpected header length %d\n",
344 file
, le32_to_cpu(header
->len
));
348 adsp_dbg(dsp
, "%s: timestamp %llu\n", file
,
349 le64_to_cpu(footer
->timestamp
));
351 while (pos
< firmware
->size
&&
352 pos
- firmware
->size
> sizeof(*region
)) {
353 region
= (void *)&(firmware
->data
[pos
]);
354 region_name
= "Unknown";
357 offset
= le32_to_cpu(region
->offset
) & 0xffffff;
358 type
= be32_to_cpu(region
->type
) & 0xff;
359 mem
= wm_adsp_find_region(dsp
, type
);
363 region_name
= "Firmware name";
364 text
= kzalloc(le32_to_cpu(region
->len
) + 1,
368 region_name
= "Information";
369 text
= kzalloc(le32_to_cpu(region
->len
) + 1,
373 region_name
= "Absolute";
379 reg
= wm_adsp_region_to_reg(mem
, offset
);
384 reg
= wm_adsp_region_to_reg(mem
, offset
);
389 reg
= wm_adsp_region_to_reg(mem
, offset
);
394 reg
= wm_adsp_region_to_reg(mem
, offset
);
399 reg
= wm_adsp_region_to_reg(mem
, offset
);
403 "%s.%d: Unknown region type %x at %d(%x)\n",
404 file
, regions
, type
, pos
, pos
);
408 adsp_dbg(dsp
, "%s.%d: %d bytes at %d in %s\n", file
,
409 regions
, le32_to_cpu(region
->len
), offset
,
413 memcpy(text
, region
->data
, le32_to_cpu(region
->len
));
414 adsp_info(dsp
, "%s: %s\n", file
, text
);
419 buf
= kmemdup(region
->data
, le32_to_cpu(region
->len
),
420 GFP_KERNEL
| GFP_DMA
);
422 adsp_err(dsp
, "Out of memory\n");
426 ret
= regmap_raw_write(regmap
, reg
, buf
,
427 le32_to_cpu(region
->len
));
433 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
435 le32_to_cpu(region
->len
), offset
,
441 pos
+= le32_to_cpu(region
->len
) + sizeof(*region
);
445 if (pos
> firmware
->size
)
446 adsp_warn(dsp
, "%s.%d: %zu bytes at end of file\n",
447 file
, regions
, pos
- firmware
->size
);
450 release_firmware(firmware
);
457 static int wm_adsp_setup_algs(struct wm_adsp
*dsp
)
459 struct regmap
*regmap
= dsp
->regmap
;
460 struct wmfw_adsp1_id_hdr adsp1_id
;
461 struct wmfw_adsp2_id_hdr adsp2_id
;
462 struct wmfw_adsp1_alg_hdr
*adsp1_alg
;
463 struct wmfw_adsp2_alg_hdr
*adsp2_alg
;
465 struct wm_adsp_alg_region
*region
;
466 const struct wm_adsp_region
*mem
;
467 unsigned int pos
, term
;
468 size_t algs
, buf_size
;
474 mem
= wm_adsp_find_region(dsp
, WMFW_ADSP1_DM
);
477 mem
= wm_adsp_find_region(dsp
, WMFW_ADSP2_XM
);
491 ret
= regmap_raw_read(regmap
, mem
->base
, &adsp1_id
,
494 adsp_err(dsp
, "Failed to read algorithm info: %d\n",
500 buf_size
= sizeof(adsp1_id
);
502 algs
= be32_to_cpu(adsp1_id
.algs
);
503 adsp_info(dsp
, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
504 be32_to_cpu(adsp1_id
.fw
.id
),
505 (be32_to_cpu(adsp1_id
.fw
.ver
) & 0xff0000) >> 16,
506 (be32_to_cpu(adsp1_id
.fw
.ver
) & 0xff00) >> 8,
507 be32_to_cpu(adsp1_id
.fw
.ver
) & 0xff,
510 pos
= sizeof(adsp1_id
) / 2;
511 term
= pos
+ ((sizeof(*adsp1_alg
) * algs
) / 2);
515 ret
= regmap_raw_read(regmap
, mem
->base
, &adsp2_id
,
518 adsp_err(dsp
, "Failed to read algorithm info: %d\n",
524 buf_size
= sizeof(adsp2_id
);
526 algs
= be32_to_cpu(adsp2_id
.algs
);
527 adsp_info(dsp
, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
528 be32_to_cpu(adsp2_id
.fw
.id
),
529 (be32_to_cpu(adsp2_id
.fw
.ver
) & 0xff0000) >> 16,
530 (be32_to_cpu(adsp2_id
.fw
.ver
) & 0xff00) >> 8,
531 be32_to_cpu(adsp2_id
.fw
.ver
) & 0xff,
534 pos
= sizeof(adsp2_id
) / 2;
535 term
= pos
+ ((sizeof(*adsp2_alg
) * algs
) / 2);
539 BUG_ON(NULL
== "Unknown DSP type");
544 adsp_err(dsp
, "No algorithms\n");
549 adsp_err(dsp
, "Algorithm count %zx excessive\n", algs
);
550 print_hex_dump_bytes(dev_name(dsp
->dev
), DUMP_PREFIX_OFFSET
,
555 /* Read the terminator first to validate the length */
556 ret
= regmap_raw_read(regmap
, mem
->base
+ term
, &val
, sizeof(val
));
558 adsp_err(dsp
, "Failed to read algorithm list end: %d\n",
563 if (be32_to_cpu(val
) != 0xbedead)
564 adsp_warn(dsp
, "Algorithm list end %x 0x%x != 0xbeadead\n",
565 term
, be32_to_cpu(val
));
567 alg
= kzalloc((term
- pos
) * 2, GFP_KERNEL
| GFP_DMA
);
571 ret
= regmap_raw_read(regmap
, mem
->base
+ pos
, alg
, (term
- pos
) * 2);
573 adsp_err(dsp
, "Failed to read algorithm list: %d\n",
581 for (i
= 0; i
< algs
; i
++) {
584 adsp_info(dsp
, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
585 i
, be32_to_cpu(adsp1_alg
[i
].alg
.id
),
586 (be32_to_cpu(adsp1_alg
[i
].alg
.ver
) & 0xff0000) >> 16,
587 (be32_to_cpu(adsp1_alg
[i
].alg
.ver
) & 0xff00) >> 8,
588 be32_to_cpu(adsp1_alg
[i
].alg
.ver
) & 0xff,
589 be32_to_cpu(adsp1_alg
[i
].dm
),
590 be32_to_cpu(adsp1_alg
[i
].zm
));
592 if (adsp1_alg
[i
].dm
) {
593 region
= kzalloc(sizeof(*region
), GFP_KERNEL
);
596 region
->type
= WMFW_ADSP1_DM
;
597 region
->alg
= be32_to_cpu(adsp1_alg
[i
].alg
.id
);
598 region
->base
= be32_to_cpu(adsp1_alg
[i
].dm
);
599 list_add_tail(®ion
->list
,
603 if (adsp1_alg
[i
].zm
) {
604 region
= kzalloc(sizeof(*region
), GFP_KERNEL
);
607 region
->type
= WMFW_ADSP1_ZM
;
608 region
->alg
= be32_to_cpu(adsp1_alg
[i
].alg
.id
);
609 region
->base
= be32_to_cpu(adsp1_alg
[i
].zm
);
610 list_add_tail(®ion
->list
,
617 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
618 i
, be32_to_cpu(adsp2_alg
[i
].alg
.id
),
619 (be32_to_cpu(adsp2_alg
[i
].alg
.ver
) & 0xff0000) >> 16,
620 (be32_to_cpu(adsp2_alg
[i
].alg
.ver
) & 0xff00) >> 8,
621 be32_to_cpu(adsp2_alg
[i
].alg
.ver
) & 0xff,
622 be32_to_cpu(adsp2_alg
[i
].xm
),
623 be32_to_cpu(adsp2_alg
[i
].ym
),
624 be32_to_cpu(adsp2_alg
[i
].zm
));
626 if (adsp2_alg
[i
].xm
) {
627 region
= kzalloc(sizeof(*region
), GFP_KERNEL
);
630 region
->type
= WMFW_ADSP2_XM
;
631 region
->alg
= be32_to_cpu(adsp2_alg
[i
].alg
.id
);
632 region
->base
= be32_to_cpu(adsp2_alg
[i
].xm
);
633 list_add_tail(®ion
->list
,
637 if (adsp2_alg
[i
].ym
) {
638 region
= kzalloc(sizeof(*region
), GFP_KERNEL
);
641 region
->type
= WMFW_ADSP2_YM
;
642 region
->alg
= be32_to_cpu(adsp2_alg
[i
].alg
.id
);
643 region
->base
= be32_to_cpu(adsp2_alg
[i
].ym
);
644 list_add_tail(®ion
->list
,
648 if (adsp2_alg
[i
].zm
) {
649 region
= kzalloc(sizeof(*region
), GFP_KERNEL
);
652 region
->type
= WMFW_ADSP2_ZM
;
653 region
->alg
= be32_to_cpu(adsp2_alg
[i
].alg
.id
);
654 region
->base
= be32_to_cpu(adsp2_alg
[i
].zm
);
655 list_add_tail(®ion
->list
,
667 static int wm_adsp_load_coeff(struct wm_adsp
*dsp
)
669 struct regmap
*regmap
= dsp
->regmap
;
670 struct wmfw_coeff_hdr
*hdr
;
671 struct wmfw_coeff_item
*blk
;
672 const struct firmware
*firmware
;
673 const struct wm_adsp_region
*mem
;
674 struct wm_adsp_alg_region
*alg_region
;
675 const char *region_name
;
676 int ret
, pos
, blocks
, type
, offset
, reg
;
680 file
= kzalloc(PAGE_SIZE
, GFP_KERNEL
);
684 snprintf(file
, PAGE_SIZE
, "%s-dsp%d-%s.bin", dsp
->part
, dsp
->num
,
685 wm_adsp_fw
[dsp
->fw
].file
);
686 file
[PAGE_SIZE
- 1] = '\0';
688 ret
= request_firmware(&firmware
, file
, dsp
->dev
);
690 adsp_warn(dsp
, "Failed to request '%s'\n", file
);
696 if (sizeof(*hdr
) >= firmware
->size
) {
697 adsp_err(dsp
, "%s: file too short, %zu bytes\n",
698 file
, firmware
->size
);
702 hdr
= (void*)&firmware
->data
[0];
703 if (memcmp(hdr
->magic
, "WMDR", 4) != 0) {
704 adsp_err(dsp
, "%s: invalid magic\n", file
);
708 switch (be32_to_cpu(hdr
->rev
) & 0xff) {
712 adsp_err(dsp
, "%s: Unsupported coefficient file format %d\n",
713 file
, be32_to_cpu(hdr
->rev
) & 0xff);
718 adsp_dbg(dsp
, "%s: v%d.%d.%d\n", file
,
719 (le32_to_cpu(hdr
->ver
) >> 16) & 0xff,
720 (le32_to_cpu(hdr
->ver
) >> 8) & 0xff,
721 le32_to_cpu(hdr
->ver
) & 0xff);
723 pos
= le32_to_cpu(hdr
->len
);
726 while (pos
< firmware
->size
&&
727 pos
- firmware
->size
> sizeof(*blk
)) {
728 blk
= (void*)(&firmware
->data
[pos
]);
730 type
= le16_to_cpu(blk
->type
);
731 offset
= le16_to_cpu(blk
->offset
);
733 adsp_dbg(dsp
, "%s.%d: %x v%d.%d.%d\n",
734 file
, blocks
, le32_to_cpu(blk
->id
),
735 (le32_to_cpu(blk
->ver
) >> 16) & 0xff,
736 (le32_to_cpu(blk
->ver
) >> 8) & 0xff,
737 le32_to_cpu(blk
->ver
) & 0xff);
738 adsp_dbg(dsp
, "%s.%d: %d bytes at 0x%x in %x\n",
739 file
, blocks
, le32_to_cpu(blk
->len
), offset
, type
);
742 region_name
= "Unknown";
744 case (WMFW_NAME_TEXT
<< 8):
745 case (WMFW_INFO_TEXT
<< 8):
747 case (WMFW_ABSOLUTE
<< 8):
748 region_name
= "register";
756 adsp_dbg(dsp
, "%s.%d: %d bytes in %x for %x\n",
757 file
, blocks
, le32_to_cpu(blk
->len
),
758 type
, le32_to_cpu(blk
->id
));
760 mem
= wm_adsp_find_region(dsp
, type
);
762 adsp_err(dsp
, "No base for region %x\n", type
);
767 list_for_each_entry(alg_region
,
768 &dsp
->alg_regions
, list
) {
769 if (le32_to_cpu(blk
->id
) == alg_region
->alg
&&
770 type
== alg_region
->type
) {
771 reg
= alg_region
->base
+ offset
;
772 reg
= wm_adsp_region_to_reg(mem
,
778 adsp_err(dsp
, "No %x for algorithm %x\n",
779 type
, le32_to_cpu(blk
->id
));
783 adsp_err(dsp
, "%s.%d: Unknown region type %x at %d\n",
784 file
, blocks
, type
, pos
);
789 buf
= kmemdup(blk
->data
, le32_to_cpu(blk
->len
),
790 GFP_KERNEL
| GFP_DMA
);
792 adsp_err(dsp
, "Out of memory\n");
796 ret
= regmap_raw_write(regmap
, reg
, blk
->data
,
797 le32_to_cpu(blk
->len
));
800 "%s.%d: Failed to write to %x in %s\n",
801 file
, blocks
, reg
, region_name
);
807 pos
+= le32_to_cpu(blk
->len
) + sizeof(*blk
);
811 if (pos
> firmware
->size
)
812 adsp_warn(dsp
, "%s.%d: %zu bytes at end of file\n",
813 file
, blocks
, pos
- firmware
->size
);
816 release_firmware(firmware
);
822 int wm_adsp1_init(struct wm_adsp
*adsp
)
824 INIT_LIST_HEAD(&adsp
->alg_regions
);
828 EXPORT_SYMBOL_GPL(wm_adsp1_init
);
830 int wm_adsp1_event(struct snd_soc_dapm_widget
*w
,
831 struct snd_kcontrol
*kcontrol
,
834 struct snd_soc_codec
*codec
= w
->codec
;
835 struct wm_adsp
*dsps
= snd_soc_codec_get_drvdata(codec
);
836 struct wm_adsp
*dsp
= &dsps
[w
->shift
];
841 case SND_SOC_DAPM_POST_PMU
:
842 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP1_CONTROL_30
,
843 ADSP1_SYS_ENA
, ADSP1_SYS_ENA
);
846 * For simplicity set the DSP clock rate to be the
847 * SYSCLK rate rather than making it configurable.
849 if(dsp
->sysclk_reg
) {
850 ret
= regmap_read(dsp
->regmap
, dsp
->sysclk_reg
, &val
);
852 adsp_err(dsp
, "Failed to read SYSCLK state: %d\n",
857 val
= (val
& dsp
->sysclk_mask
)
858 >> dsp
->sysclk_shift
;
860 ret
= regmap_update_bits(dsp
->regmap
,
861 dsp
->base
+ ADSP1_CONTROL_31
,
862 ADSP1_CLK_SEL_MASK
, val
);
864 adsp_err(dsp
, "Failed to set clock rate: %d\n",
870 ret
= wm_adsp_load(dsp
);
874 ret
= wm_adsp_setup_algs(dsp
);
878 ret
= wm_adsp_load_coeff(dsp
);
882 /* Start the core running */
883 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP1_CONTROL_30
,
884 ADSP1_CORE_ENA
| ADSP1_START
,
885 ADSP1_CORE_ENA
| ADSP1_START
);
888 case SND_SOC_DAPM_PRE_PMD
:
890 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP1_CONTROL_30
,
891 ADSP1_CORE_ENA
| ADSP1_START
, 0);
893 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP1_CONTROL_19
,
894 ADSP1_WDMA_BUFFER_LENGTH_MASK
, 0);
896 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP1_CONTROL_30
,
907 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP1_CONTROL_30
,
911 EXPORT_SYMBOL_GPL(wm_adsp1_event
);
913 static int wm_adsp2_ena(struct wm_adsp
*dsp
)
918 ret
= regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP2_CONTROL
,
919 ADSP2_SYS_ENA
, ADSP2_SYS_ENA
);
923 /* Wait for the RAM to start, should be near instantaneous */
926 ret
= regmap_read(dsp
->regmap
, dsp
->base
+ ADSP2_STATUS1
,
930 } while (!(val
& ADSP2_RAM_RDY
) && ++count
< 10);
932 if (!(val
& ADSP2_RAM_RDY
)) {
933 adsp_err(dsp
, "Failed to start DSP RAM\n");
937 adsp_dbg(dsp
, "RAM ready after %d polls\n", count
);
938 adsp_info(dsp
, "RAM ready after %d polls\n", count
);
943 int wm_adsp2_event(struct snd_soc_dapm_widget
*w
,
944 struct snd_kcontrol
*kcontrol
, int event
)
946 struct snd_soc_codec
*codec
= w
->codec
;
947 struct wm_adsp
*dsps
= snd_soc_codec_get_drvdata(codec
);
948 struct wm_adsp
*dsp
= &dsps
[w
->shift
];
949 struct wm_adsp_alg_region
*alg_region
;
954 case SND_SOC_DAPM_POST_PMU
:
956 * For simplicity set the DSP clock rate to be the
957 * SYSCLK rate rather than making it configurable.
959 ret
= regmap_read(dsp
->regmap
, ARIZONA_SYSTEM_CLOCK_1
, &val
);
961 adsp_err(dsp
, "Failed to read SYSCLK state: %d\n",
965 val
= (val
& ARIZONA_SYSCLK_FREQ_MASK
)
966 >> ARIZONA_SYSCLK_FREQ_SHIFT
;
968 ret
= regmap_update_bits(dsp
->regmap
,
969 dsp
->base
+ ADSP2_CLOCKING
,
970 ADSP2_CLK_SEL_MASK
, val
);
972 adsp_err(dsp
, "Failed to set clock rate: %d\n",
978 ret
= regmap_read(dsp
->regmap
,
979 dsp
->base
+ ADSP2_CLOCKING
, &val
);
982 "Failed to read clocking: %d\n", ret
);
986 if ((val
& ADSP2_CLK_SEL_MASK
) >= 3) {
987 ret
= regulator_enable(dsp
->dvfs
);
990 "Failed to enable supply: %d\n",
995 ret
= regulator_set_voltage(dsp
->dvfs
,
1000 "Failed to raise supply: %d\n",
1007 ret
= wm_adsp2_ena(dsp
);
1011 ret
= wm_adsp_load(dsp
);
1015 ret
= wm_adsp_setup_algs(dsp
);
1019 ret
= wm_adsp_load_coeff(dsp
);
1023 ret
= regmap_update_bits(dsp
->regmap
,
1024 dsp
->base
+ ADSP2_CONTROL
,
1025 ADSP2_CORE_ENA
| ADSP2_START
,
1026 ADSP2_CORE_ENA
| ADSP2_START
);
1030 dsp
->running
= true;
1033 case SND_SOC_DAPM_PRE_PMD
:
1034 dsp
->running
= false;
1036 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP2_CONTROL
,
1037 ADSP2_SYS_ENA
| ADSP2_CORE_ENA
|
1041 ret
= regulator_set_voltage(dsp
->dvfs
, 1200000,
1045 "Failed to lower supply: %d\n",
1048 ret
= regulator_disable(dsp
->dvfs
);
1051 "Failed to enable supply: %d\n",
1055 while (!list_empty(&dsp
->alg_regions
)) {
1056 alg_region
= list_first_entry(&dsp
->alg_regions
,
1057 struct wm_adsp_alg_region
,
1059 list_del(&alg_region
->list
);
1070 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP2_CONTROL
,
1071 ADSP2_SYS_ENA
| ADSP2_CORE_ENA
| ADSP2_START
, 0);
1074 EXPORT_SYMBOL_GPL(wm_adsp2_event
);
1076 int wm_adsp2_init(struct wm_adsp
*adsp
, bool dvfs
)
1081 * Disable the DSP memory by default when in reset for a small
1084 ret
= regmap_update_bits(adsp
->regmap
, adsp
->base
+ ADSP2_CONTROL
,
1087 adsp_err(adsp
, "Failed to clear memory retention: %d\n", ret
);
1091 INIT_LIST_HEAD(&adsp
->alg_regions
);
1094 adsp
->dvfs
= devm_regulator_get(adsp
->dev
, "DCVDD");
1095 if (IS_ERR(adsp
->dvfs
)) {
1096 ret
= PTR_ERR(adsp
->dvfs
);
1097 dev_err(adsp
->dev
, "Failed to get DCVDD: %d\n", ret
);
1101 ret
= regulator_enable(adsp
->dvfs
);
1103 dev_err(adsp
->dev
, "Failed to enable DCVDD: %d\n",
1108 ret
= regulator_set_voltage(adsp
->dvfs
, 1200000, 1800000);
1110 dev_err(adsp
->dev
, "Failed to initialise DVFS: %d\n",
1115 ret
= regulator_disable(adsp
->dvfs
);
1117 dev_err(adsp
->dev
, "Failed to disable DCVDD: %d\n",
1125 EXPORT_SYMBOL_GPL(wm_adsp2_init
);