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ASoC: wm_adsp: Group all the ALSA control functions together
[deliverable/linux.git] / sound / soc / codecs / wm_adsp.c
1 /*
2 * wm_adsp.c -- Wolfson ADSP support
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/firmware.h>
18 #include <linux/list.h>
19 #include <linux/pm.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <linux/vmalloc.h>
25 #include <linux/workqueue.h>
26 #include <sound/core.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/jack.h>
31 #include <sound/initval.h>
32 #include <sound/tlv.h>
33
34 #include <linux/mfd/arizona/registers.h>
35
36 #include "arizona.h"
37 #include "wm_adsp.h"
38
39 #define adsp_crit(_dsp, fmt, ...) \
40 dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
41 #define adsp_err(_dsp, fmt, ...) \
42 dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
43 #define adsp_warn(_dsp, fmt, ...) \
44 dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
45 #define adsp_info(_dsp, fmt, ...) \
46 dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
47 #define adsp_dbg(_dsp, fmt, ...) \
48 dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
49
50 #define ADSP1_CONTROL_1 0x00
51 #define ADSP1_CONTROL_2 0x02
52 #define ADSP1_CONTROL_3 0x03
53 #define ADSP1_CONTROL_4 0x04
54 #define ADSP1_CONTROL_5 0x06
55 #define ADSP1_CONTROL_6 0x07
56 #define ADSP1_CONTROL_7 0x08
57 #define ADSP1_CONTROL_8 0x09
58 #define ADSP1_CONTROL_9 0x0A
59 #define ADSP1_CONTROL_10 0x0B
60 #define ADSP1_CONTROL_11 0x0C
61 #define ADSP1_CONTROL_12 0x0D
62 #define ADSP1_CONTROL_13 0x0F
63 #define ADSP1_CONTROL_14 0x10
64 #define ADSP1_CONTROL_15 0x11
65 #define ADSP1_CONTROL_16 0x12
66 #define ADSP1_CONTROL_17 0x13
67 #define ADSP1_CONTROL_18 0x14
68 #define ADSP1_CONTROL_19 0x16
69 #define ADSP1_CONTROL_20 0x17
70 #define ADSP1_CONTROL_21 0x18
71 #define ADSP1_CONTROL_22 0x1A
72 #define ADSP1_CONTROL_23 0x1B
73 #define ADSP1_CONTROL_24 0x1C
74 #define ADSP1_CONTROL_25 0x1E
75 #define ADSP1_CONTROL_26 0x20
76 #define ADSP1_CONTROL_27 0x21
77 #define ADSP1_CONTROL_28 0x22
78 #define ADSP1_CONTROL_29 0x23
79 #define ADSP1_CONTROL_30 0x24
80 #define ADSP1_CONTROL_31 0x26
81
82 /*
83 * ADSP1 Control 19
84 */
85 #define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
86 #define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
87 #define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
88
89
90 /*
91 * ADSP1 Control 30
92 */
93 #define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
94 #define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
95 #define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
96 #define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
97 #define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
98 #define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
99 #define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
100 #define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
101 #define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
102 #define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
103 #define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
104 #define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
105 #define ADSP1_START 0x0001 /* DSP1_START */
106 #define ADSP1_START_MASK 0x0001 /* DSP1_START */
107 #define ADSP1_START_SHIFT 0 /* DSP1_START */
108 #define ADSP1_START_WIDTH 1 /* DSP1_START */
109
110 /*
111 * ADSP1 Control 31
112 */
113 #define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
114 #define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
115 #define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
116
117 #define ADSP2_CONTROL 0x0
118 #define ADSP2_CLOCKING 0x1
119 #define ADSP2_STATUS1 0x4
120 #define ADSP2_WDMA_CONFIG_1 0x30
121 #define ADSP2_WDMA_CONFIG_2 0x31
122 #define ADSP2_RDMA_CONFIG_1 0x34
123
124 /*
125 * ADSP2 Control
126 */
127
128 #define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
129 #define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
130 #define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
131 #define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
132 #define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
133 #define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
134 #define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
135 #define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
136 #define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
137 #define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
138 #define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
139 #define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
140 #define ADSP2_START 0x0001 /* DSP1_START */
141 #define ADSP2_START_MASK 0x0001 /* DSP1_START */
142 #define ADSP2_START_SHIFT 0 /* DSP1_START */
143 #define ADSP2_START_WIDTH 1 /* DSP1_START */
144
145 /*
146 * ADSP2 clocking
147 */
148 #define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
149 #define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
150 #define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
151
152 /*
153 * ADSP2 Status 1
154 */
155 #define ADSP2_RAM_RDY 0x0001
156 #define ADSP2_RAM_RDY_MASK 0x0001
157 #define ADSP2_RAM_RDY_SHIFT 0
158 #define ADSP2_RAM_RDY_WIDTH 1
159
160 struct wm_adsp_buf {
161 struct list_head list;
162 void *buf;
163 };
164
165 static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len,
166 struct list_head *list)
167 {
168 struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
169
170 if (buf == NULL)
171 return NULL;
172
173 buf->buf = vmalloc(len);
174 if (!buf->buf) {
175 vfree(buf);
176 return NULL;
177 }
178 memcpy(buf->buf, src, len);
179
180 if (list)
181 list_add_tail(&buf->list, list);
182
183 return buf;
184 }
185
186 static void wm_adsp_buf_free(struct list_head *list)
187 {
188 while (!list_empty(list)) {
189 struct wm_adsp_buf *buf = list_first_entry(list,
190 struct wm_adsp_buf,
191 list);
192 list_del(&buf->list);
193 vfree(buf->buf);
194 kfree(buf);
195 }
196 }
197
198 #define WM_ADSP_NUM_FW 4
199
200 #define WM_ADSP_FW_MBC_VSS 0
201 #define WM_ADSP_FW_TX 1
202 #define WM_ADSP_FW_TX_SPK 2
203 #define WM_ADSP_FW_RX_ANC 3
204
205 static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
206 [WM_ADSP_FW_MBC_VSS] = "MBC/VSS",
207 [WM_ADSP_FW_TX] = "Tx",
208 [WM_ADSP_FW_TX_SPK] = "Tx Speaker",
209 [WM_ADSP_FW_RX_ANC] = "Rx ANC",
210 };
211
212 static struct {
213 const char *file;
214 } wm_adsp_fw[WM_ADSP_NUM_FW] = {
215 [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" },
216 [WM_ADSP_FW_TX] = { .file = "tx" },
217 [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" },
218 [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" },
219 };
220
221 struct wm_coeff_ctl_ops {
222 int (*xget)(struct snd_kcontrol *kcontrol,
223 struct snd_ctl_elem_value *ucontrol);
224 int (*xput)(struct snd_kcontrol *kcontrol,
225 struct snd_ctl_elem_value *ucontrol);
226 int (*xinfo)(struct snd_kcontrol *kcontrol,
227 struct snd_ctl_elem_info *uinfo);
228 };
229
230 struct wm_coeff_ctl {
231 const char *name;
232 struct wm_adsp_alg_region alg_region;
233 struct wm_coeff_ctl_ops ops;
234 struct wm_adsp *dsp;
235 unsigned int enabled:1;
236 struct list_head list;
237 void *cache;
238 size_t len;
239 unsigned int set:1;
240 struct snd_kcontrol *kcontrol;
241 };
242
243 static int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
244 struct snd_ctl_elem_value *ucontrol)
245 {
246 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
247 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
248 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
249
250 ucontrol->value.integer.value[0] = dsp[e->shift_l].fw;
251
252 return 0;
253 }
254
255 static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
256 struct snd_ctl_elem_value *ucontrol)
257 {
258 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
259 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
260 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
261
262 if (ucontrol->value.integer.value[0] == dsp[e->shift_l].fw)
263 return 0;
264
265 if (ucontrol->value.integer.value[0] >= WM_ADSP_NUM_FW)
266 return -EINVAL;
267
268 if (dsp[e->shift_l].running)
269 return -EBUSY;
270
271 dsp[e->shift_l].fw = ucontrol->value.integer.value[0];
272
273 return 0;
274 }
275
276 static const struct soc_enum wm_adsp_fw_enum[] = {
277 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
278 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
279 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
280 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
281 };
282
283 const struct snd_kcontrol_new wm_adsp1_fw_controls[] = {
284 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
285 wm_adsp_fw_get, wm_adsp_fw_put),
286 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
287 wm_adsp_fw_get, wm_adsp_fw_put),
288 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
289 wm_adsp_fw_get, wm_adsp_fw_put),
290 };
291 EXPORT_SYMBOL_GPL(wm_adsp1_fw_controls);
292
293 #if IS_ENABLED(CONFIG_SND_SOC_ARIZONA)
294 static const struct soc_enum wm_adsp2_rate_enum[] = {
295 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP1_CONTROL_1,
296 ARIZONA_DSP1_RATE_SHIFT, 0xf,
297 ARIZONA_RATE_ENUM_SIZE,
298 arizona_rate_text, arizona_rate_val),
299 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP2_CONTROL_1,
300 ARIZONA_DSP1_RATE_SHIFT, 0xf,
301 ARIZONA_RATE_ENUM_SIZE,
302 arizona_rate_text, arizona_rate_val),
303 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP3_CONTROL_1,
304 ARIZONA_DSP1_RATE_SHIFT, 0xf,
305 ARIZONA_RATE_ENUM_SIZE,
306 arizona_rate_text, arizona_rate_val),
307 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP4_CONTROL_1,
308 ARIZONA_DSP1_RATE_SHIFT, 0xf,
309 ARIZONA_RATE_ENUM_SIZE,
310 arizona_rate_text, arizona_rate_val),
311 };
312
313 const struct snd_kcontrol_new wm_adsp2_fw_controls[] = {
314 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
315 wm_adsp_fw_get, wm_adsp_fw_put),
316 SOC_ENUM("DSP1 Rate", wm_adsp2_rate_enum[0]),
317 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
318 wm_adsp_fw_get, wm_adsp_fw_put),
319 SOC_ENUM("DSP2 Rate", wm_adsp2_rate_enum[1]),
320 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
321 wm_adsp_fw_get, wm_adsp_fw_put),
322 SOC_ENUM("DSP3 Rate", wm_adsp2_rate_enum[2]),
323 SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum[3],
324 wm_adsp_fw_get, wm_adsp_fw_put),
325 SOC_ENUM("DSP4 Rate", wm_adsp2_rate_enum[3]),
326 };
327 EXPORT_SYMBOL_GPL(wm_adsp2_fw_controls);
328 #endif
329
330 static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
331 int type)
332 {
333 int i;
334
335 for (i = 0; i < dsp->num_mems; i++)
336 if (dsp->mem[i].type == type)
337 return &dsp->mem[i];
338
339 return NULL;
340 }
341
342 static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *mem,
343 unsigned int offset)
344 {
345 if (WARN_ON(!mem))
346 return offset;
347 switch (mem->type) {
348 case WMFW_ADSP1_PM:
349 return mem->base + (offset * 3);
350 case WMFW_ADSP1_DM:
351 return mem->base + (offset * 2);
352 case WMFW_ADSP2_XM:
353 return mem->base + (offset * 2);
354 case WMFW_ADSP2_YM:
355 return mem->base + (offset * 2);
356 case WMFW_ADSP1_ZM:
357 return mem->base + (offset * 2);
358 default:
359 WARN(1, "Unknown memory region type");
360 return offset;
361 }
362 }
363
364 static int wm_coeff_info(struct snd_kcontrol *kcontrol,
365 struct snd_ctl_elem_info *uinfo)
366 {
367 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
368
369 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
370 uinfo->count = ctl->len;
371 return 0;
372 }
373
374 static int wm_coeff_write_control(struct wm_coeff_ctl *ctl,
375 const void *buf, size_t len)
376 {
377 struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
378 const struct wm_adsp_region *mem;
379 struct wm_adsp *dsp = ctl->dsp;
380 void *scratch;
381 int ret;
382 unsigned int reg;
383
384 mem = wm_adsp_find_region(dsp, alg_region->type);
385 if (!mem) {
386 adsp_err(dsp, "No base for region %x\n",
387 alg_region->type);
388 return -EINVAL;
389 }
390
391 reg = ctl->alg_region.base;
392 reg = wm_adsp_region_to_reg(mem, reg);
393
394 scratch = kmemdup(buf, ctl->len, GFP_KERNEL | GFP_DMA);
395 if (!scratch)
396 return -ENOMEM;
397
398 ret = regmap_raw_write(dsp->regmap, reg, scratch,
399 ctl->len);
400 if (ret) {
401 adsp_err(dsp, "Failed to write %zu bytes to %x: %d\n",
402 ctl->len, reg, ret);
403 kfree(scratch);
404 return ret;
405 }
406 adsp_dbg(dsp, "Wrote %zu bytes to %x\n", ctl->len, reg);
407
408 kfree(scratch);
409
410 return 0;
411 }
412
413 static int wm_coeff_put(struct snd_kcontrol *kcontrol,
414 struct snd_ctl_elem_value *ucontrol)
415 {
416 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
417 char *p = ucontrol->value.bytes.data;
418
419 memcpy(ctl->cache, p, ctl->len);
420
421 ctl->set = 1;
422 if (!ctl->enabled)
423 return 0;
424
425 return wm_coeff_write_control(ctl, p, ctl->len);
426 }
427
428 static int wm_coeff_read_control(struct wm_coeff_ctl *ctl,
429 void *buf, size_t len)
430 {
431 struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
432 const struct wm_adsp_region *mem;
433 struct wm_adsp *dsp = ctl->dsp;
434 void *scratch;
435 int ret;
436 unsigned int reg;
437
438 mem = wm_adsp_find_region(dsp, alg_region->type);
439 if (!mem) {
440 adsp_err(dsp, "No base for region %x\n",
441 alg_region->type);
442 return -EINVAL;
443 }
444
445 reg = ctl->alg_region.base;
446 reg = wm_adsp_region_to_reg(mem, reg);
447
448 scratch = kmalloc(ctl->len, GFP_KERNEL | GFP_DMA);
449 if (!scratch)
450 return -ENOMEM;
451
452 ret = regmap_raw_read(dsp->regmap, reg, scratch, ctl->len);
453 if (ret) {
454 adsp_err(dsp, "Failed to read %zu bytes from %x: %d\n",
455 ctl->len, reg, ret);
456 kfree(scratch);
457 return ret;
458 }
459 adsp_dbg(dsp, "Read %zu bytes from %x\n", ctl->len, reg);
460
461 memcpy(buf, scratch, ctl->len);
462 kfree(scratch);
463
464 return 0;
465 }
466
467 static int wm_coeff_get(struct snd_kcontrol *kcontrol,
468 struct snd_ctl_elem_value *ucontrol)
469 {
470 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
471 char *p = ucontrol->value.bytes.data;
472
473 memcpy(p, ctl->cache, ctl->len);
474 return 0;
475 }
476
477 struct wmfw_ctl_work {
478 struct wm_adsp *dsp;
479 struct wm_coeff_ctl *ctl;
480 struct work_struct work;
481 };
482
483 static int wmfw_add_ctl(struct wm_adsp *dsp, struct wm_coeff_ctl *ctl)
484 {
485 struct snd_kcontrol_new *kcontrol;
486 int ret;
487
488 if (!ctl || !ctl->name)
489 return -EINVAL;
490
491 kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL);
492 if (!kcontrol)
493 return -ENOMEM;
494 kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
495
496 kcontrol->name = ctl->name;
497 kcontrol->info = wm_coeff_info;
498 kcontrol->get = wm_coeff_get;
499 kcontrol->put = wm_coeff_put;
500 kcontrol->private_value = (unsigned long)ctl;
501
502 ret = snd_soc_add_card_controls(dsp->card,
503 kcontrol, 1);
504 if (ret < 0)
505 goto err_kcontrol;
506
507 kfree(kcontrol);
508
509 ctl->kcontrol = snd_soc_card_get_kcontrol(dsp->card,
510 ctl->name);
511
512 list_add(&ctl->list, &dsp->ctl_list);
513
514 return 0;
515
516 err_kcontrol:
517 kfree(kcontrol);
518 return ret;
519 }
520
521 static int wm_coeff_init_control_caches(struct wm_adsp *dsp)
522 {
523 struct wm_coeff_ctl *ctl;
524 int ret;
525
526 list_for_each_entry(ctl, &dsp->ctl_list, list) {
527 if (!ctl->enabled || ctl->set)
528 continue;
529 ret = wm_coeff_read_control(ctl,
530 ctl->cache,
531 ctl->len);
532 if (ret < 0)
533 return ret;
534 }
535
536 return 0;
537 }
538
539 static int wm_coeff_sync_controls(struct wm_adsp *dsp)
540 {
541 struct wm_coeff_ctl *ctl;
542 int ret;
543
544 list_for_each_entry(ctl, &dsp->ctl_list, list) {
545 if (!ctl->enabled)
546 continue;
547 if (ctl->set) {
548 ret = wm_coeff_write_control(ctl,
549 ctl->cache,
550 ctl->len);
551 if (ret < 0)
552 return ret;
553 }
554 }
555
556 return 0;
557 }
558
559 static void wm_adsp_ctl_work(struct work_struct *work)
560 {
561 struct wmfw_ctl_work *ctl_work = container_of(work,
562 struct wmfw_ctl_work,
563 work);
564
565 wmfw_add_ctl(ctl_work->dsp, ctl_work->ctl);
566 kfree(ctl_work);
567 }
568
569 static int wm_adsp_create_control(struct wm_adsp *dsp,
570 const struct wm_adsp_alg_region *alg_region,
571 unsigned int len)
572 {
573 struct wm_coeff_ctl *ctl;
574 struct wmfw_ctl_work *ctl_work;
575 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
576 char *region_name;
577 int ret;
578
579 switch (alg_region->type) {
580 case WMFW_ADSP1_PM:
581 region_name = "PM";
582 break;
583 case WMFW_ADSP1_DM:
584 region_name = "DM";
585 break;
586 case WMFW_ADSP2_XM:
587 region_name = "XM";
588 break;
589 case WMFW_ADSP2_YM:
590 region_name = "YM";
591 break;
592 case WMFW_ADSP1_ZM:
593 region_name = "ZM";
594 break;
595 default:
596 return -EINVAL;
597 }
598
599 snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "DSP%d %s %x",
600 dsp->num, region_name, alg_region->alg);
601
602 list_for_each_entry(ctl, &dsp->ctl_list,
603 list) {
604 if (!strcmp(ctl->name, name)) {
605 if (!ctl->enabled)
606 ctl->enabled = 1;
607 return 0;
608 }
609 }
610
611 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
612 if (!ctl)
613 return -ENOMEM;
614 ctl->alg_region = *alg_region;
615 ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL);
616 if (!ctl->name) {
617 ret = -ENOMEM;
618 goto err_ctl;
619 }
620 ctl->enabled = 1;
621 ctl->set = 0;
622 ctl->ops.xget = wm_coeff_get;
623 ctl->ops.xput = wm_coeff_put;
624 ctl->dsp = dsp;
625
626 if (len > 512) {
627 adsp_warn(dsp, "Truncating control %s from %d\n",
628 ctl->name, len);
629 len = 512;
630 }
631 ctl->len = len;
632 ctl->cache = kzalloc(ctl->len, GFP_KERNEL);
633 if (!ctl->cache) {
634 ret = -ENOMEM;
635 goto err_ctl_name;
636 }
637
638 ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL);
639 if (!ctl_work) {
640 ret = -ENOMEM;
641 goto err_ctl_cache;
642 }
643
644 ctl_work->dsp = dsp;
645 ctl_work->ctl = ctl;
646 INIT_WORK(&ctl_work->work, wm_adsp_ctl_work);
647 schedule_work(&ctl_work->work);
648
649 return 0;
650
651 err_ctl_cache:
652 kfree(ctl->cache);
653 err_ctl_name:
654 kfree(ctl->name);
655 err_ctl:
656 kfree(ctl);
657
658 return ret;
659 }
660
661 static int wm_adsp_load(struct wm_adsp *dsp)
662 {
663 LIST_HEAD(buf_list);
664 const struct firmware *firmware;
665 struct regmap *regmap = dsp->regmap;
666 unsigned int pos = 0;
667 const struct wmfw_header *header;
668 const struct wmfw_adsp1_sizes *adsp1_sizes;
669 const struct wmfw_adsp2_sizes *adsp2_sizes;
670 const struct wmfw_footer *footer;
671 const struct wmfw_region *region;
672 const struct wm_adsp_region *mem;
673 const char *region_name;
674 char *file, *text;
675 struct wm_adsp_buf *buf;
676 unsigned int reg;
677 int regions = 0;
678 int ret, offset, type, sizes;
679
680 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
681 if (file == NULL)
682 return -ENOMEM;
683
684 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.wmfw", dsp->part, dsp->num,
685 wm_adsp_fw[dsp->fw].file);
686 file[PAGE_SIZE - 1] = '\0';
687
688 ret = request_firmware(&firmware, file, dsp->dev);
689 if (ret != 0) {
690 adsp_err(dsp, "Failed to request '%s'\n", file);
691 goto out;
692 }
693 ret = -EINVAL;
694
695 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
696 if (pos >= firmware->size) {
697 adsp_err(dsp, "%s: file too short, %zu bytes\n",
698 file, firmware->size);
699 goto out_fw;
700 }
701
702 header = (void*)&firmware->data[0];
703
704 if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
705 adsp_err(dsp, "%s: invalid magic\n", file);
706 goto out_fw;
707 }
708
709 if (header->ver != 0) {
710 adsp_err(dsp, "%s: unknown file format %d\n",
711 file, header->ver);
712 goto out_fw;
713 }
714 adsp_info(dsp, "Firmware version: %d\n", header->ver);
715
716 if (header->core != dsp->type) {
717 adsp_err(dsp, "%s: invalid core %d != %d\n",
718 file, header->core, dsp->type);
719 goto out_fw;
720 }
721
722 switch (dsp->type) {
723 case WMFW_ADSP1:
724 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
725 adsp1_sizes = (void *)&(header[1]);
726 footer = (void *)&(adsp1_sizes[1]);
727 sizes = sizeof(*adsp1_sizes);
728
729 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n",
730 file, le32_to_cpu(adsp1_sizes->dm),
731 le32_to_cpu(adsp1_sizes->pm),
732 le32_to_cpu(adsp1_sizes->zm));
733 break;
734
735 case WMFW_ADSP2:
736 pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer);
737 adsp2_sizes = (void *)&(header[1]);
738 footer = (void *)&(adsp2_sizes[1]);
739 sizes = sizeof(*adsp2_sizes);
740
741 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n",
742 file, le32_to_cpu(adsp2_sizes->xm),
743 le32_to_cpu(adsp2_sizes->ym),
744 le32_to_cpu(adsp2_sizes->pm),
745 le32_to_cpu(adsp2_sizes->zm));
746 break;
747
748 default:
749 WARN(1, "Unknown DSP type");
750 goto out_fw;
751 }
752
753 if (le32_to_cpu(header->len) != sizeof(*header) +
754 sizes + sizeof(*footer)) {
755 adsp_err(dsp, "%s: unexpected header length %d\n",
756 file, le32_to_cpu(header->len));
757 goto out_fw;
758 }
759
760 adsp_dbg(dsp, "%s: timestamp %llu\n", file,
761 le64_to_cpu(footer->timestamp));
762
763 while (pos < firmware->size &&
764 pos - firmware->size > sizeof(*region)) {
765 region = (void *)&(firmware->data[pos]);
766 region_name = "Unknown";
767 reg = 0;
768 text = NULL;
769 offset = le32_to_cpu(region->offset) & 0xffffff;
770 type = be32_to_cpu(region->type) & 0xff;
771 mem = wm_adsp_find_region(dsp, type);
772
773 switch (type) {
774 case WMFW_NAME_TEXT:
775 region_name = "Firmware name";
776 text = kzalloc(le32_to_cpu(region->len) + 1,
777 GFP_KERNEL);
778 break;
779 case WMFW_INFO_TEXT:
780 region_name = "Information";
781 text = kzalloc(le32_to_cpu(region->len) + 1,
782 GFP_KERNEL);
783 break;
784 case WMFW_ABSOLUTE:
785 region_name = "Absolute";
786 reg = offset;
787 break;
788 case WMFW_ADSP1_PM:
789 region_name = "PM";
790 reg = wm_adsp_region_to_reg(mem, offset);
791 break;
792 case WMFW_ADSP1_DM:
793 region_name = "DM";
794 reg = wm_adsp_region_to_reg(mem, offset);
795 break;
796 case WMFW_ADSP2_XM:
797 region_name = "XM";
798 reg = wm_adsp_region_to_reg(mem, offset);
799 break;
800 case WMFW_ADSP2_YM:
801 region_name = "YM";
802 reg = wm_adsp_region_to_reg(mem, offset);
803 break;
804 case WMFW_ADSP1_ZM:
805 region_name = "ZM";
806 reg = wm_adsp_region_to_reg(mem, offset);
807 break;
808 default:
809 adsp_warn(dsp,
810 "%s.%d: Unknown region type %x at %d(%x)\n",
811 file, regions, type, pos, pos);
812 break;
813 }
814
815 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
816 regions, le32_to_cpu(region->len), offset,
817 region_name);
818
819 if (text) {
820 memcpy(text, region->data, le32_to_cpu(region->len));
821 adsp_info(dsp, "%s: %s\n", file, text);
822 kfree(text);
823 }
824
825 if (reg) {
826 buf = wm_adsp_buf_alloc(region->data,
827 le32_to_cpu(region->len),
828 &buf_list);
829 if (!buf) {
830 adsp_err(dsp, "Out of memory\n");
831 ret = -ENOMEM;
832 goto out_fw;
833 }
834
835 ret = regmap_raw_write_async(regmap, reg, buf->buf,
836 le32_to_cpu(region->len));
837 if (ret != 0) {
838 adsp_err(dsp,
839 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
840 file, regions,
841 le32_to_cpu(region->len), offset,
842 region_name, ret);
843 goto out_fw;
844 }
845 }
846
847 pos += le32_to_cpu(region->len) + sizeof(*region);
848 regions++;
849 }
850
851 ret = regmap_async_complete(regmap);
852 if (ret != 0) {
853 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
854 goto out_fw;
855 }
856
857 if (pos > firmware->size)
858 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
859 file, regions, pos - firmware->size);
860
861 out_fw:
862 regmap_async_complete(regmap);
863 wm_adsp_buf_free(&buf_list);
864 release_firmware(firmware);
865 out:
866 kfree(file);
867
868 return ret;
869 }
870
871 static void *wm_adsp_read_algs(struct wm_adsp *dsp, size_t n_algs,
872 unsigned int pos, unsigned int len)
873 {
874 void *alg;
875 int ret;
876 __be32 val;
877
878 if (n_algs == 0) {
879 adsp_err(dsp, "No algorithms\n");
880 return ERR_PTR(-EINVAL);
881 }
882
883 if (n_algs > 1024) {
884 adsp_err(dsp, "Algorithm count %zx excessive\n", n_algs);
885 return ERR_PTR(-EINVAL);
886 }
887
888 /* Read the terminator first to validate the length */
889 ret = regmap_raw_read(dsp->regmap, pos + len, &val, sizeof(val));
890 if (ret != 0) {
891 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
892 ret);
893 return ERR_PTR(ret);
894 }
895
896 if (be32_to_cpu(val) != 0xbedead)
897 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbeadead\n",
898 pos + len, be32_to_cpu(val));
899
900 alg = kzalloc(len * 2, GFP_KERNEL | GFP_DMA);
901 if (!alg)
902 return ERR_PTR(-ENOMEM);
903
904 ret = regmap_raw_read(dsp->regmap, pos, alg, len * 2);
905 if (ret != 0) {
906 adsp_err(dsp, "Failed to read algorithm list: %d\n",
907 ret);
908 kfree(alg);
909 return ERR_PTR(ret);
910 }
911
912 return alg;
913 }
914
915 static struct wm_adsp_alg_region *wm_adsp_create_region(struct wm_adsp *dsp,
916 int type, __be32 id,
917 __be32 base)
918 {
919 struct wm_adsp_alg_region *alg_region;
920
921 alg_region = kzalloc(sizeof(*alg_region), GFP_KERNEL);
922 if (!alg_region)
923 return ERR_PTR(-ENOMEM);
924
925 alg_region->type = type;
926 alg_region->alg = be32_to_cpu(id);
927 alg_region->base = be32_to_cpu(base);
928
929 list_add_tail(&alg_region->list, &dsp->alg_regions);
930
931 return alg_region;
932 }
933
934 static int wm_adsp1_setup_algs(struct wm_adsp *dsp)
935 {
936 struct wmfw_adsp1_id_hdr adsp1_id;
937 struct wmfw_adsp1_alg_hdr *adsp1_alg;
938 struct wm_adsp_alg_region *alg_region;
939 const struct wm_adsp_region *mem;
940 unsigned int pos, len;
941 size_t n_algs;
942 int i, ret;
943
944 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
945 if (WARN_ON(!mem))
946 return -EINVAL;
947
948 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id,
949 sizeof(adsp1_id));
950 if (ret != 0) {
951 adsp_err(dsp, "Failed to read algorithm info: %d\n",
952 ret);
953 return ret;
954 }
955
956 n_algs = be32_to_cpu(adsp1_id.n_algs);
957 dsp->fw_id = be32_to_cpu(adsp1_id.fw.id);
958 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
959 dsp->fw_id,
960 (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16,
961 (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8,
962 be32_to_cpu(adsp1_id.fw.ver) & 0xff,
963 n_algs);
964
965 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
966 adsp1_id.fw.id, adsp1_id.zm);
967 if (IS_ERR(alg_region))
968 return PTR_ERR(alg_region);
969
970 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
971 adsp1_id.fw.id, adsp1_id.dm);
972 if (IS_ERR(alg_region))
973 return PTR_ERR(alg_region);
974
975 pos = sizeof(adsp1_id) / 2;
976 len = (sizeof(*adsp1_alg) * n_algs) / 2;
977
978 adsp1_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len);
979 if (IS_ERR(adsp1_alg))
980 return PTR_ERR(adsp1_alg);
981
982 for (i = 0; i < n_algs; i++) {
983 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
984 i, be32_to_cpu(adsp1_alg[i].alg.id),
985 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
986 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
987 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
988 be32_to_cpu(adsp1_alg[i].dm),
989 be32_to_cpu(adsp1_alg[i].zm));
990
991 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
992 adsp1_alg[i].alg.id,
993 adsp1_alg[i].dm);
994 if (IS_ERR(alg_region)) {
995 ret = PTR_ERR(alg_region);
996 goto out;
997 }
998 if (i + 1 < n_algs) {
999 len = be32_to_cpu(adsp1_alg[i + 1].dm);
1000 len -= be32_to_cpu(adsp1_alg[i].dm);
1001 len *= 4;
1002 wm_adsp_create_control(dsp, alg_region, len);
1003 } else {
1004 adsp_warn(dsp, "Missing length info for region DM with ID %x\n",
1005 be32_to_cpu(adsp1_alg[i].alg.id));
1006 }
1007
1008 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
1009 adsp1_alg[i].alg.id,
1010 adsp1_alg[i].zm);
1011 if (IS_ERR(alg_region)) {
1012 ret = PTR_ERR(alg_region);
1013 goto out;
1014 }
1015 if (i + 1 < n_algs) {
1016 len = be32_to_cpu(adsp1_alg[i + 1].zm);
1017 len -= be32_to_cpu(adsp1_alg[i].zm);
1018 len *= 4;
1019 wm_adsp_create_control(dsp, alg_region, len);
1020 } else {
1021 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
1022 be32_to_cpu(adsp1_alg[i].alg.id));
1023 }
1024 }
1025
1026 out:
1027 kfree(adsp1_alg);
1028 return ret;
1029 }
1030
1031 static int wm_adsp2_setup_algs(struct wm_adsp *dsp)
1032 {
1033 struct wmfw_adsp2_id_hdr adsp2_id;
1034 struct wmfw_adsp2_alg_hdr *adsp2_alg;
1035 struct wm_adsp_alg_region *alg_region;
1036 const struct wm_adsp_region *mem;
1037 unsigned int pos, len;
1038 size_t n_algs;
1039 int i, ret;
1040
1041 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
1042 if (WARN_ON(!mem))
1043 return -EINVAL;
1044
1045 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id,
1046 sizeof(adsp2_id));
1047 if (ret != 0) {
1048 adsp_err(dsp, "Failed to read algorithm info: %d\n",
1049 ret);
1050 return ret;
1051 }
1052
1053 n_algs = be32_to_cpu(adsp2_id.n_algs);
1054 dsp->fw_id = be32_to_cpu(adsp2_id.fw.id);
1055 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
1056 dsp->fw_id,
1057 (be32_to_cpu(adsp2_id.fw.ver) & 0xff0000) >> 16,
1058 (be32_to_cpu(adsp2_id.fw.ver) & 0xff00) >> 8,
1059 be32_to_cpu(adsp2_id.fw.ver) & 0xff,
1060 n_algs);
1061
1062 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
1063 adsp2_id.fw.id, adsp2_id.xm);
1064 if (IS_ERR(alg_region))
1065 return PTR_ERR(alg_region);
1066
1067 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
1068 adsp2_id.fw.id, adsp2_id.ym);
1069 if (IS_ERR(alg_region))
1070 return PTR_ERR(alg_region);
1071
1072 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
1073 adsp2_id.fw.id, adsp2_id.zm);
1074 if (IS_ERR(alg_region))
1075 return PTR_ERR(alg_region);
1076
1077 pos = sizeof(adsp2_id) / 2;
1078 len = (sizeof(*adsp2_alg) * n_algs) / 2;
1079
1080 adsp2_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len);
1081 if (IS_ERR(adsp2_alg))
1082 return PTR_ERR(adsp2_alg);
1083
1084 for (i = 0; i < n_algs; i++) {
1085 adsp_info(dsp,
1086 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
1087 i, be32_to_cpu(adsp2_alg[i].alg.id),
1088 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
1089 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
1090 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
1091 be32_to_cpu(adsp2_alg[i].xm),
1092 be32_to_cpu(adsp2_alg[i].ym),
1093 be32_to_cpu(adsp2_alg[i].zm));
1094
1095 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
1096 adsp2_alg[i].alg.id,
1097 adsp2_alg[i].xm);
1098 if (IS_ERR(alg_region)) {
1099 ret = PTR_ERR(alg_region);
1100 goto out;
1101 }
1102 if (i + 1 < n_algs) {
1103 len = be32_to_cpu(adsp2_alg[i + 1].xm);
1104 len -= be32_to_cpu(adsp2_alg[i].xm);
1105 len *= 4;
1106 wm_adsp_create_control(dsp, alg_region, len);
1107 } else {
1108 adsp_warn(dsp, "Missing length info for region XM with ID %x\n",
1109 be32_to_cpu(adsp2_alg[i].alg.id));
1110 }
1111
1112 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
1113 adsp2_alg[i].alg.id,
1114 adsp2_alg[i].ym);
1115 if (IS_ERR(alg_region)) {
1116 ret = PTR_ERR(alg_region);
1117 goto out;
1118 }
1119 if (i + 1 < n_algs) {
1120 len = be32_to_cpu(adsp2_alg[i + 1].ym);
1121 len -= be32_to_cpu(adsp2_alg[i].ym);
1122 len *= 4;
1123 wm_adsp_create_control(dsp, alg_region, len);
1124 } else {
1125 adsp_warn(dsp, "Missing length info for region YM with ID %x\n",
1126 be32_to_cpu(adsp2_alg[i].alg.id));
1127 }
1128
1129 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
1130 adsp2_alg[i].alg.id,
1131 adsp2_alg[i].zm);
1132 if (IS_ERR(alg_region)) {
1133 ret = PTR_ERR(alg_region);
1134 goto out;
1135 }
1136 if (i + 1 < n_algs) {
1137 len = be32_to_cpu(adsp2_alg[i + 1].zm);
1138 len -= be32_to_cpu(adsp2_alg[i].zm);
1139 len *= 4;
1140 wm_adsp_create_control(dsp, alg_region, len);
1141 } else {
1142 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
1143 be32_to_cpu(adsp2_alg[i].alg.id));
1144 }
1145 }
1146
1147 out:
1148 kfree(adsp2_alg);
1149 return ret;
1150 }
1151
1152 static int wm_adsp_load_coeff(struct wm_adsp *dsp)
1153 {
1154 LIST_HEAD(buf_list);
1155 struct regmap *regmap = dsp->regmap;
1156 struct wmfw_coeff_hdr *hdr;
1157 struct wmfw_coeff_item *blk;
1158 const struct firmware *firmware;
1159 const struct wm_adsp_region *mem;
1160 struct wm_adsp_alg_region *alg_region;
1161 const char *region_name;
1162 int ret, pos, blocks, type, offset, reg;
1163 char *file;
1164 struct wm_adsp_buf *buf;
1165
1166 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1167 if (file == NULL)
1168 return -ENOMEM;
1169
1170 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, dsp->num,
1171 wm_adsp_fw[dsp->fw].file);
1172 file[PAGE_SIZE - 1] = '\0';
1173
1174 ret = request_firmware(&firmware, file, dsp->dev);
1175 if (ret != 0) {
1176 adsp_warn(dsp, "Failed to request '%s'\n", file);
1177 ret = 0;
1178 goto out;
1179 }
1180 ret = -EINVAL;
1181
1182 if (sizeof(*hdr) >= firmware->size) {
1183 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1184 file, firmware->size);
1185 goto out_fw;
1186 }
1187
1188 hdr = (void*)&firmware->data[0];
1189 if (memcmp(hdr->magic, "WMDR", 4) != 0) {
1190 adsp_err(dsp, "%s: invalid magic\n", file);
1191 goto out_fw;
1192 }
1193
1194 switch (be32_to_cpu(hdr->rev) & 0xff) {
1195 case 1:
1196 break;
1197 default:
1198 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
1199 file, be32_to_cpu(hdr->rev) & 0xff);
1200 ret = -EINVAL;
1201 goto out_fw;
1202 }
1203
1204 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
1205 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
1206 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
1207 le32_to_cpu(hdr->ver) & 0xff);
1208
1209 pos = le32_to_cpu(hdr->len);
1210
1211 blocks = 0;
1212 while (pos < firmware->size &&
1213 pos - firmware->size > sizeof(*blk)) {
1214 blk = (void*)(&firmware->data[pos]);
1215
1216 type = le16_to_cpu(blk->type);
1217 offset = le16_to_cpu(blk->offset);
1218
1219 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
1220 file, blocks, le32_to_cpu(blk->id),
1221 (le32_to_cpu(blk->ver) >> 16) & 0xff,
1222 (le32_to_cpu(blk->ver) >> 8) & 0xff,
1223 le32_to_cpu(blk->ver) & 0xff);
1224 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
1225 file, blocks, le32_to_cpu(blk->len), offset, type);
1226
1227 reg = 0;
1228 region_name = "Unknown";
1229 switch (type) {
1230 case (WMFW_NAME_TEXT << 8):
1231 case (WMFW_INFO_TEXT << 8):
1232 break;
1233 case (WMFW_ABSOLUTE << 8):
1234 /*
1235 * Old files may use this for global
1236 * coefficients.
1237 */
1238 if (le32_to_cpu(blk->id) == dsp->fw_id &&
1239 offset == 0) {
1240 region_name = "global coefficients";
1241 mem = wm_adsp_find_region(dsp, type);
1242 if (!mem) {
1243 adsp_err(dsp, "No ZM\n");
1244 break;
1245 }
1246 reg = wm_adsp_region_to_reg(mem, 0);
1247
1248 } else {
1249 region_name = "register";
1250 reg = offset;
1251 }
1252 break;
1253
1254 case WMFW_ADSP1_DM:
1255 case WMFW_ADSP1_ZM:
1256 case WMFW_ADSP2_XM:
1257 case WMFW_ADSP2_YM:
1258 adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
1259 file, blocks, le32_to_cpu(blk->len),
1260 type, le32_to_cpu(blk->id));
1261
1262 mem = wm_adsp_find_region(dsp, type);
1263 if (!mem) {
1264 adsp_err(dsp, "No base for region %x\n", type);
1265 break;
1266 }
1267
1268 reg = 0;
1269 list_for_each_entry(alg_region,
1270 &dsp->alg_regions, list) {
1271 if (le32_to_cpu(blk->id) == alg_region->alg &&
1272 type == alg_region->type) {
1273 reg = alg_region->base;
1274 reg = wm_adsp_region_to_reg(mem,
1275 reg);
1276 reg += offset;
1277 break;
1278 }
1279 }
1280
1281 if (reg == 0)
1282 adsp_err(dsp, "No %x for algorithm %x\n",
1283 type, le32_to_cpu(blk->id));
1284 break;
1285
1286 default:
1287 adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
1288 file, blocks, type, pos);
1289 break;
1290 }
1291
1292 if (reg) {
1293 buf = wm_adsp_buf_alloc(blk->data,
1294 le32_to_cpu(blk->len),
1295 &buf_list);
1296 if (!buf) {
1297 adsp_err(dsp, "Out of memory\n");
1298 ret = -ENOMEM;
1299 goto out_fw;
1300 }
1301
1302 adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
1303 file, blocks, le32_to_cpu(blk->len),
1304 reg);
1305 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1306 le32_to_cpu(blk->len));
1307 if (ret != 0) {
1308 adsp_err(dsp,
1309 "%s.%d: Failed to write to %x in %s: %d\n",
1310 file, blocks, reg, region_name, ret);
1311 }
1312 }
1313
1314 pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03;
1315 blocks++;
1316 }
1317
1318 ret = regmap_async_complete(regmap);
1319 if (ret != 0)
1320 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
1321
1322 if (pos > firmware->size)
1323 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1324 file, blocks, pos - firmware->size);
1325
1326 out_fw:
1327 regmap_async_complete(regmap);
1328 release_firmware(firmware);
1329 wm_adsp_buf_free(&buf_list);
1330 out:
1331 kfree(file);
1332 return ret;
1333 }
1334
1335 int wm_adsp1_init(struct wm_adsp *dsp)
1336 {
1337 INIT_LIST_HEAD(&dsp->alg_regions);
1338
1339 return 0;
1340 }
1341 EXPORT_SYMBOL_GPL(wm_adsp1_init);
1342
1343 int wm_adsp1_event(struct snd_soc_dapm_widget *w,
1344 struct snd_kcontrol *kcontrol,
1345 int event)
1346 {
1347 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1348 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
1349 struct wm_adsp *dsp = &dsps[w->shift];
1350 struct wm_adsp_alg_region *alg_region;
1351 struct wm_coeff_ctl *ctl;
1352 int ret;
1353 int val;
1354
1355 dsp->card = codec->component.card;
1356
1357 switch (event) {
1358 case SND_SOC_DAPM_POST_PMU:
1359 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1360 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
1361
1362 /*
1363 * For simplicity set the DSP clock rate to be the
1364 * SYSCLK rate rather than making it configurable.
1365 */
1366 if(dsp->sysclk_reg) {
1367 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
1368 if (ret != 0) {
1369 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
1370 ret);
1371 return ret;
1372 }
1373
1374 val = (val & dsp->sysclk_mask)
1375 >> dsp->sysclk_shift;
1376
1377 ret = regmap_update_bits(dsp->regmap,
1378 dsp->base + ADSP1_CONTROL_31,
1379 ADSP1_CLK_SEL_MASK, val);
1380 if (ret != 0) {
1381 adsp_err(dsp, "Failed to set clock rate: %d\n",
1382 ret);
1383 return ret;
1384 }
1385 }
1386
1387 ret = wm_adsp_load(dsp);
1388 if (ret != 0)
1389 goto err;
1390
1391 ret = wm_adsp1_setup_algs(dsp);
1392 if (ret != 0)
1393 goto err;
1394
1395 ret = wm_adsp_load_coeff(dsp);
1396 if (ret != 0)
1397 goto err;
1398
1399 /* Initialize caches for enabled and unset controls */
1400 ret = wm_coeff_init_control_caches(dsp);
1401 if (ret != 0)
1402 goto err;
1403
1404 /* Sync set controls */
1405 ret = wm_coeff_sync_controls(dsp);
1406 if (ret != 0)
1407 goto err;
1408
1409 /* Start the core running */
1410 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1411 ADSP1_CORE_ENA | ADSP1_START,
1412 ADSP1_CORE_ENA | ADSP1_START);
1413 break;
1414
1415 case SND_SOC_DAPM_PRE_PMD:
1416 /* Halt the core */
1417 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1418 ADSP1_CORE_ENA | ADSP1_START, 0);
1419
1420 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
1421 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
1422
1423 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1424 ADSP1_SYS_ENA, 0);
1425
1426 list_for_each_entry(ctl, &dsp->ctl_list, list)
1427 ctl->enabled = 0;
1428
1429 while (!list_empty(&dsp->alg_regions)) {
1430 alg_region = list_first_entry(&dsp->alg_regions,
1431 struct wm_adsp_alg_region,
1432 list);
1433 list_del(&alg_region->list);
1434 kfree(alg_region);
1435 }
1436 break;
1437
1438 default:
1439 break;
1440 }
1441
1442 return 0;
1443
1444 err:
1445 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1446 ADSP1_SYS_ENA, 0);
1447 return ret;
1448 }
1449 EXPORT_SYMBOL_GPL(wm_adsp1_event);
1450
1451 static int wm_adsp2_ena(struct wm_adsp *dsp)
1452 {
1453 unsigned int val;
1454 int ret, count;
1455
1456 ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL,
1457 ADSP2_SYS_ENA, ADSP2_SYS_ENA);
1458 if (ret != 0)
1459 return ret;
1460
1461 /* Wait for the RAM to start, should be near instantaneous */
1462 for (count = 0; count < 10; ++count) {
1463 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1,
1464 &val);
1465 if (ret != 0)
1466 return ret;
1467
1468 if (val & ADSP2_RAM_RDY)
1469 break;
1470
1471 msleep(1);
1472 }
1473
1474 if (!(val & ADSP2_RAM_RDY)) {
1475 adsp_err(dsp, "Failed to start DSP RAM\n");
1476 return -EBUSY;
1477 }
1478
1479 adsp_dbg(dsp, "RAM ready after %d polls\n", count);
1480
1481 return 0;
1482 }
1483
1484 static void wm_adsp2_boot_work(struct work_struct *work)
1485 {
1486 struct wm_adsp *dsp = container_of(work,
1487 struct wm_adsp,
1488 boot_work);
1489 int ret;
1490 unsigned int val;
1491
1492 /*
1493 * For simplicity set the DSP clock rate to be the
1494 * SYSCLK rate rather than making it configurable.
1495 */
1496 ret = regmap_read(dsp->regmap, ARIZONA_SYSTEM_CLOCK_1, &val);
1497 if (ret != 0) {
1498 adsp_err(dsp, "Failed to read SYSCLK state: %d\n", ret);
1499 return;
1500 }
1501 val = (val & ARIZONA_SYSCLK_FREQ_MASK)
1502 >> ARIZONA_SYSCLK_FREQ_SHIFT;
1503
1504 ret = regmap_update_bits_async(dsp->regmap,
1505 dsp->base + ADSP2_CLOCKING,
1506 ADSP2_CLK_SEL_MASK, val);
1507 if (ret != 0) {
1508 adsp_err(dsp, "Failed to set clock rate: %d\n", ret);
1509 return;
1510 }
1511
1512 if (dsp->dvfs) {
1513 ret = regmap_read(dsp->regmap,
1514 dsp->base + ADSP2_CLOCKING, &val);
1515 if (ret != 0) {
1516 adsp_err(dsp, "Failed to read clocking: %d\n", ret);
1517 return;
1518 }
1519
1520 if ((val & ADSP2_CLK_SEL_MASK) >= 3) {
1521 ret = regulator_enable(dsp->dvfs);
1522 if (ret != 0) {
1523 adsp_err(dsp,
1524 "Failed to enable supply: %d\n",
1525 ret);
1526 return;
1527 }
1528
1529 ret = regulator_set_voltage(dsp->dvfs,
1530 1800000,
1531 1800000);
1532 if (ret != 0) {
1533 adsp_err(dsp,
1534 "Failed to raise supply: %d\n",
1535 ret);
1536 return;
1537 }
1538 }
1539 }
1540
1541 ret = wm_adsp2_ena(dsp);
1542 if (ret != 0)
1543 return;
1544
1545 ret = wm_adsp_load(dsp);
1546 if (ret != 0)
1547 goto err;
1548
1549 ret = wm_adsp2_setup_algs(dsp);
1550 if (ret != 0)
1551 goto err;
1552
1553 ret = wm_adsp_load_coeff(dsp);
1554 if (ret != 0)
1555 goto err;
1556
1557 /* Initialize caches for enabled and unset controls */
1558 ret = wm_coeff_init_control_caches(dsp);
1559 if (ret != 0)
1560 goto err;
1561
1562 /* Sync set controls */
1563 ret = wm_coeff_sync_controls(dsp);
1564 if (ret != 0)
1565 goto err;
1566
1567 dsp->running = true;
1568
1569 return;
1570
1571 err:
1572 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
1573 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
1574 }
1575
1576 int wm_adsp2_early_event(struct snd_soc_dapm_widget *w,
1577 struct snd_kcontrol *kcontrol, int event)
1578 {
1579 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1580 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
1581 struct wm_adsp *dsp = &dsps[w->shift];
1582
1583 dsp->card = codec->component.card;
1584
1585 switch (event) {
1586 case SND_SOC_DAPM_PRE_PMU:
1587 queue_work(system_unbound_wq, &dsp->boot_work);
1588 break;
1589 default:
1590 break;
1591 }
1592
1593 return 0;
1594 }
1595 EXPORT_SYMBOL_GPL(wm_adsp2_early_event);
1596
1597 int wm_adsp2_event(struct snd_soc_dapm_widget *w,
1598 struct snd_kcontrol *kcontrol, int event)
1599 {
1600 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1601 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
1602 struct wm_adsp *dsp = &dsps[w->shift];
1603 struct wm_adsp_alg_region *alg_region;
1604 struct wm_coeff_ctl *ctl;
1605 int ret;
1606
1607 switch (event) {
1608 case SND_SOC_DAPM_POST_PMU:
1609 flush_work(&dsp->boot_work);
1610
1611 if (!dsp->running)
1612 return -EIO;
1613
1614 ret = regmap_update_bits(dsp->regmap,
1615 dsp->base + ADSP2_CONTROL,
1616 ADSP2_CORE_ENA | ADSP2_START,
1617 ADSP2_CORE_ENA | ADSP2_START);
1618 if (ret != 0)
1619 goto err;
1620 break;
1621
1622 case SND_SOC_DAPM_PRE_PMD:
1623 dsp->running = false;
1624
1625 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
1626 ADSP2_SYS_ENA | ADSP2_CORE_ENA |
1627 ADSP2_START, 0);
1628
1629 /* Make sure DMAs are quiesced */
1630 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
1631 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0);
1632 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
1633
1634 if (dsp->dvfs) {
1635 ret = regulator_set_voltage(dsp->dvfs, 1200000,
1636 1800000);
1637 if (ret != 0)
1638 adsp_warn(dsp,
1639 "Failed to lower supply: %d\n",
1640 ret);
1641
1642 ret = regulator_disable(dsp->dvfs);
1643 if (ret != 0)
1644 adsp_err(dsp,
1645 "Failed to enable supply: %d\n",
1646 ret);
1647 }
1648
1649 list_for_each_entry(ctl, &dsp->ctl_list, list)
1650 ctl->enabled = 0;
1651
1652 while (!list_empty(&dsp->alg_regions)) {
1653 alg_region = list_first_entry(&dsp->alg_regions,
1654 struct wm_adsp_alg_region,
1655 list);
1656 list_del(&alg_region->list);
1657 kfree(alg_region);
1658 }
1659
1660 adsp_dbg(dsp, "Shutdown complete\n");
1661 break;
1662
1663 default:
1664 break;
1665 }
1666
1667 return 0;
1668 err:
1669 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
1670 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
1671 return ret;
1672 }
1673 EXPORT_SYMBOL_GPL(wm_adsp2_event);
1674
1675 int wm_adsp2_init(struct wm_adsp *dsp, bool dvfs)
1676 {
1677 int ret;
1678
1679 /*
1680 * Disable the DSP memory by default when in reset for a small
1681 * power saving.
1682 */
1683 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
1684 ADSP2_MEM_ENA, 0);
1685 if (ret != 0) {
1686 adsp_err(dsp, "Failed to clear memory retention: %d\n", ret);
1687 return ret;
1688 }
1689
1690 INIT_LIST_HEAD(&dsp->alg_regions);
1691 INIT_LIST_HEAD(&dsp->ctl_list);
1692 INIT_WORK(&dsp->boot_work, wm_adsp2_boot_work);
1693
1694 if (dvfs) {
1695 dsp->dvfs = devm_regulator_get(dsp->dev, "DCVDD");
1696 if (IS_ERR(dsp->dvfs)) {
1697 ret = PTR_ERR(dsp->dvfs);
1698 adsp_err(dsp, "Failed to get DCVDD: %d\n", ret);
1699 return ret;
1700 }
1701
1702 ret = regulator_enable(dsp->dvfs);
1703 if (ret != 0) {
1704 adsp_err(dsp, "Failed to enable DCVDD: %d\n", ret);
1705 return ret;
1706 }
1707
1708 ret = regulator_set_voltage(dsp->dvfs, 1200000, 1800000);
1709 if (ret != 0) {
1710 adsp_err(dsp, "Failed to initialise DVFS: %d\n", ret);
1711 return ret;
1712 }
1713
1714 ret = regulator_disable(dsp->dvfs);
1715 if (ret != 0) {
1716 adsp_err(dsp, "Failed to disable DCVDD: %d\n", ret);
1717 return ret;
1718 }
1719 }
1720
1721 return 0;
1722 }
1723 EXPORT_SYMBOL_GPL(wm_adsp2_init);
1724
1725 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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