2 * wm_adsp.c -- Wolfson ADSP support
4 * Copyright 2012 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/firmware.h>
18 #include <linux/list.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <linux/vmalloc.h>
25 #include <linux/workqueue.h>
26 #include <sound/core.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/jack.h>
31 #include <sound/initval.h>
32 #include <sound/tlv.h>
34 #include <linux/mfd/arizona/registers.h>
39 #define adsp_crit(_dsp, fmt, ...) \
40 dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
41 #define adsp_err(_dsp, fmt, ...) \
42 dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
43 #define adsp_warn(_dsp, fmt, ...) \
44 dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
45 #define adsp_info(_dsp, fmt, ...) \
46 dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
47 #define adsp_dbg(_dsp, fmt, ...) \
48 dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
50 #define ADSP1_CONTROL_1 0x00
51 #define ADSP1_CONTROL_2 0x02
52 #define ADSP1_CONTROL_3 0x03
53 #define ADSP1_CONTROL_4 0x04
54 #define ADSP1_CONTROL_5 0x06
55 #define ADSP1_CONTROL_6 0x07
56 #define ADSP1_CONTROL_7 0x08
57 #define ADSP1_CONTROL_8 0x09
58 #define ADSP1_CONTROL_9 0x0A
59 #define ADSP1_CONTROL_10 0x0B
60 #define ADSP1_CONTROL_11 0x0C
61 #define ADSP1_CONTROL_12 0x0D
62 #define ADSP1_CONTROL_13 0x0F
63 #define ADSP1_CONTROL_14 0x10
64 #define ADSP1_CONTROL_15 0x11
65 #define ADSP1_CONTROL_16 0x12
66 #define ADSP1_CONTROL_17 0x13
67 #define ADSP1_CONTROL_18 0x14
68 #define ADSP1_CONTROL_19 0x16
69 #define ADSP1_CONTROL_20 0x17
70 #define ADSP1_CONTROL_21 0x18
71 #define ADSP1_CONTROL_22 0x1A
72 #define ADSP1_CONTROL_23 0x1B
73 #define ADSP1_CONTROL_24 0x1C
74 #define ADSP1_CONTROL_25 0x1E
75 #define ADSP1_CONTROL_26 0x20
76 #define ADSP1_CONTROL_27 0x21
77 #define ADSP1_CONTROL_28 0x22
78 #define ADSP1_CONTROL_29 0x23
79 #define ADSP1_CONTROL_30 0x24
80 #define ADSP1_CONTROL_31 0x26
85 #define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
86 #define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
87 #define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
93 #define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
94 #define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
95 #define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
96 #define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
97 #define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
98 #define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
99 #define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
100 #define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
101 #define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
102 #define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
103 #define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
104 #define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
105 #define ADSP1_START 0x0001 /* DSP1_START */
106 #define ADSP1_START_MASK 0x0001 /* DSP1_START */
107 #define ADSP1_START_SHIFT 0 /* DSP1_START */
108 #define ADSP1_START_WIDTH 1 /* DSP1_START */
113 #define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
114 #define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
115 #define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
117 #define ADSP2_CONTROL 0x0
118 #define ADSP2_CLOCKING 0x1
119 #define ADSP2_STATUS1 0x4
120 #define ADSP2_WDMA_CONFIG_1 0x30
121 #define ADSP2_WDMA_CONFIG_2 0x31
122 #define ADSP2_RDMA_CONFIG_1 0x34
124 #define ADSP2_SCRATCH0 0x40
125 #define ADSP2_SCRATCH1 0x41
126 #define ADSP2_SCRATCH2 0x42
127 #define ADSP2_SCRATCH3 0x43
133 #define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
134 #define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
135 #define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
136 #define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
137 #define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
138 #define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
139 #define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
140 #define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
141 #define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
142 #define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
143 #define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
144 #define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
145 #define ADSP2_START 0x0001 /* DSP1_START */
146 #define ADSP2_START_MASK 0x0001 /* DSP1_START */
147 #define ADSP2_START_SHIFT 0 /* DSP1_START */
148 #define ADSP2_START_WIDTH 1 /* DSP1_START */
153 #define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
154 #define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
155 #define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
160 #define ADSP2_RAM_RDY 0x0001
161 #define ADSP2_RAM_RDY_MASK 0x0001
162 #define ADSP2_RAM_RDY_SHIFT 0
163 #define ADSP2_RAM_RDY_WIDTH 1
166 struct list_head list
;
170 static struct wm_adsp_buf
*wm_adsp_buf_alloc(const void *src
, size_t len
,
171 struct list_head
*list
)
173 struct wm_adsp_buf
*buf
= kzalloc(sizeof(*buf
), GFP_KERNEL
);
178 buf
->buf
= vmalloc(len
);
183 memcpy(buf
->buf
, src
, len
);
186 list_add_tail(&buf
->list
, list
);
191 static void wm_adsp_buf_free(struct list_head
*list
)
193 while (!list_empty(list
)) {
194 struct wm_adsp_buf
*buf
= list_first_entry(list
,
197 list_del(&buf
->list
);
203 #define WM_ADSP_NUM_FW 4
205 #define WM_ADSP_FW_MBC_VSS 0
206 #define WM_ADSP_FW_TX 1
207 #define WM_ADSP_FW_TX_SPK 2
208 #define WM_ADSP_FW_RX_ANC 3
210 static const char *wm_adsp_fw_text
[WM_ADSP_NUM_FW
] = {
211 [WM_ADSP_FW_MBC_VSS
] = "MBC/VSS",
212 [WM_ADSP_FW_TX
] = "Tx",
213 [WM_ADSP_FW_TX_SPK
] = "Tx Speaker",
214 [WM_ADSP_FW_RX_ANC
] = "Rx ANC",
219 } wm_adsp_fw
[WM_ADSP_NUM_FW
] = {
220 [WM_ADSP_FW_MBC_VSS
] = { .file
= "mbc-vss" },
221 [WM_ADSP_FW_TX
] = { .file
= "tx" },
222 [WM_ADSP_FW_TX_SPK
] = { .file
= "tx-spk" },
223 [WM_ADSP_FW_RX_ANC
] = { .file
= "rx-anc" },
226 struct wm_coeff_ctl_ops
{
227 int (*xget
)(struct snd_kcontrol
*kcontrol
,
228 struct snd_ctl_elem_value
*ucontrol
);
229 int (*xput
)(struct snd_kcontrol
*kcontrol
,
230 struct snd_ctl_elem_value
*ucontrol
);
231 int (*xinfo
)(struct snd_kcontrol
*kcontrol
,
232 struct snd_ctl_elem_info
*uinfo
);
235 struct wm_coeff_ctl
{
238 struct wm_adsp_alg_region alg_region
;
239 struct wm_coeff_ctl_ops ops
;
241 unsigned int enabled
:1;
242 struct list_head list
;
247 struct snd_kcontrol
*kcontrol
;
251 static int wm_adsp_fw_get(struct snd_kcontrol
*kcontrol
,
252 struct snd_ctl_elem_value
*ucontrol
)
254 struct snd_soc_codec
*codec
= snd_soc_kcontrol_codec(kcontrol
);
255 struct soc_enum
*e
= (struct soc_enum
*)kcontrol
->private_value
;
256 struct wm_adsp
*dsp
= snd_soc_codec_get_drvdata(codec
);
258 ucontrol
->value
.integer
.value
[0] = dsp
[e
->shift_l
].fw
;
263 static int wm_adsp_fw_put(struct snd_kcontrol
*kcontrol
,
264 struct snd_ctl_elem_value
*ucontrol
)
266 struct snd_soc_codec
*codec
= snd_soc_kcontrol_codec(kcontrol
);
267 struct soc_enum
*e
= (struct soc_enum
*)kcontrol
->private_value
;
268 struct wm_adsp
*dsp
= snd_soc_codec_get_drvdata(codec
);
270 if (ucontrol
->value
.integer
.value
[0] == dsp
[e
->shift_l
].fw
)
273 if (ucontrol
->value
.integer
.value
[0] >= WM_ADSP_NUM_FW
)
276 if (dsp
[e
->shift_l
].running
)
279 dsp
[e
->shift_l
].fw
= ucontrol
->value
.integer
.value
[0];
284 static const struct soc_enum wm_adsp_fw_enum
[] = {
285 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text
), wm_adsp_fw_text
),
286 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text
), wm_adsp_fw_text
),
287 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text
), wm_adsp_fw_text
),
288 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text
), wm_adsp_fw_text
),
291 const struct snd_kcontrol_new wm_adsp1_fw_controls
[] = {
292 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum
[0],
293 wm_adsp_fw_get
, wm_adsp_fw_put
),
294 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum
[1],
295 wm_adsp_fw_get
, wm_adsp_fw_put
),
296 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum
[2],
297 wm_adsp_fw_get
, wm_adsp_fw_put
),
299 EXPORT_SYMBOL_GPL(wm_adsp1_fw_controls
);
301 #if IS_ENABLED(CONFIG_SND_SOC_ARIZONA)
302 static const struct soc_enum wm_adsp2_rate_enum
[] = {
303 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP1_CONTROL_1
,
304 ARIZONA_DSP1_RATE_SHIFT
, 0xf,
305 ARIZONA_RATE_ENUM_SIZE
,
306 arizona_rate_text
, arizona_rate_val
),
307 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP2_CONTROL_1
,
308 ARIZONA_DSP1_RATE_SHIFT
, 0xf,
309 ARIZONA_RATE_ENUM_SIZE
,
310 arizona_rate_text
, arizona_rate_val
),
311 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP3_CONTROL_1
,
312 ARIZONA_DSP1_RATE_SHIFT
, 0xf,
313 ARIZONA_RATE_ENUM_SIZE
,
314 arizona_rate_text
, arizona_rate_val
),
315 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP4_CONTROL_1
,
316 ARIZONA_DSP1_RATE_SHIFT
, 0xf,
317 ARIZONA_RATE_ENUM_SIZE
,
318 arizona_rate_text
, arizona_rate_val
),
321 const struct snd_kcontrol_new wm_adsp2_fw_controls
[] = {
322 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum
[0],
323 wm_adsp_fw_get
, wm_adsp_fw_put
),
324 SOC_ENUM("DSP1 Rate", wm_adsp2_rate_enum
[0]),
325 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum
[1],
326 wm_adsp_fw_get
, wm_adsp_fw_put
),
327 SOC_ENUM("DSP2 Rate", wm_adsp2_rate_enum
[1]),
328 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum
[2],
329 wm_adsp_fw_get
, wm_adsp_fw_put
),
330 SOC_ENUM("DSP3 Rate", wm_adsp2_rate_enum
[2]),
331 SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum
[3],
332 wm_adsp_fw_get
, wm_adsp_fw_put
),
333 SOC_ENUM("DSP4 Rate", wm_adsp2_rate_enum
[3]),
335 EXPORT_SYMBOL_GPL(wm_adsp2_fw_controls
);
338 static struct wm_adsp_region
const *wm_adsp_find_region(struct wm_adsp
*dsp
,
343 for (i
= 0; i
< dsp
->num_mems
; i
++)
344 if (dsp
->mem
[i
].type
== type
)
350 static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region
const *mem
,
357 return mem
->base
+ (offset
* 3);
359 return mem
->base
+ (offset
* 2);
361 return mem
->base
+ (offset
* 2);
363 return mem
->base
+ (offset
* 2);
365 return mem
->base
+ (offset
* 2);
367 WARN(1, "Unknown memory region type");
372 static void wm_adsp2_show_fw_status(struct wm_adsp
*dsp
)
377 ret
= regmap_raw_read(dsp
->regmap
, dsp
->base
+ ADSP2_SCRATCH0
,
378 scratch
, sizeof(scratch
));
380 adsp_err(dsp
, "Failed to read SCRATCH regs: %d\n", ret
);
384 adsp_dbg(dsp
, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
385 be16_to_cpu(scratch
[0]),
386 be16_to_cpu(scratch
[1]),
387 be16_to_cpu(scratch
[2]),
388 be16_to_cpu(scratch
[3]));
391 static int wm_coeff_info(struct snd_kcontrol
*kcontrol
,
392 struct snd_ctl_elem_info
*uinfo
)
394 struct wm_coeff_ctl
*ctl
= (struct wm_coeff_ctl
*)kcontrol
->private_value
;
396 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_BYTES
;
397 uinfo
->count
= ctl
->len
;
401 static int wm_coeff_write_control(struct wm_coeff_ctl
*ctl
,
402 const void *buf
, size_t len
)
404 struct wm_adsp_alg_region
*alg_region
= &ctl
->alg_region
;
405 const struct wm_adsp_region
*mem
;
406 struct wm_adsp
*dsp
= ctl
->dsp
;
411 mem
= wm_adsp_find_region(dsp
, alg_region
->type
);
413 adsp_err(dsp
, "No base for region %x\n",
418 reg
= ctl
->alg_region
.base
+ ctl
->offset
;
419 reg
= wm_adsp_region_to_reg(mem
, reg
);
421 scratch
= kmemdup(buf
, ctl
->len
, GFP_KERNEL
| GFP_DMA
);
425 ret
= regmap_raw_write(dsp
->regmap
, reg
, scratch
,
428 adsp_err(dsp
, "Failed to write %zu bytes to %x: %d\n",
433 adsp_dbg(dsp
, "Wrote %zu bytes to %x\n", ctl
->len
, reg
);
440 static int wm_coeff_put(struct snd_kcontrol
*kcontrol
,
441 struct snd_ctl_elem_value
*ucontrol
)
443 struct wm_coeff_ctl
*ctl
= (struct wm_coeff_ctl
*)kcontrol
->private_value
;
444 char *p
= ucontrol
->value
.bytes
.data
;
446 memcpy(ctl
->cache
, p
, ctl
->len
);
452 return wm_coeff_write_control(ctl
, p
, ctl
->len
);
455 static int wm_coeff_read_control(struct wm_coeff_ctl
*ctl
,
456 void *buf
, size_t len
)
458 struct wm_adsp_alg_region
*alg_region
= &ctl
->alg_region
;
459 const struct wm_adsp_region
*mem
;
460 struct wm_adsp
*dsp
= ctl
->dsp
;
465 mem
= wm_adsp_find_region(dsp
, alg_region
->type
);
467 adsp_err(dsp
, "No base for region %x\n",
472 reg
= ctl
->alg_region
.base
+ ctl
->offset
;
473 reg
= wm_adsp_region_to_reg(mem
, reg
);
475 scratch
= kmalloc(ctl
->len
, GFP_KERNEL
| GFP_DMA
);
479 ret
= regmap_raw_read(dsp
->regmap
, reg
, scratch
, ctl
->len
);
481 adsp_err(dsp
, "Failed to read %zu bytes from %x: %d\n",
486 adsp_dbg(dsp
, "Read %zu bytes from %x\n", ctl
->len
, reg
);
488 memcpy(buf
, scratch
, ctl
->len
);
494 static int wm_coeff_get(struct snd_kcontrol
*kcontrol
,
495 struct snd_ctl_elem_value
*ucontrol
)
497 struct wm_coeff_ctl
*ctl
= (struct wm_coeff_ctl
*)kcontrol
->private_value
;
498 char *p
= ucontrol
->value
.bytes
.data
;
500 if (ctl
->flags
& WMFW_CTL_FLAG_VOLATILE
) {
502 return wm_coeff_read_control(ctl
, p
, ctl
->len
);
507 memcpy(p
, ctl
->cache
, ctl
->len
);
512 struct wmfw_ctl_work
{
514 struct wm_coeff_ctl
*ctl
;
515 struct work_struct work
;
518 static int wmfw_add_ctl(struct wm_adsp
*dsp
, struct wm_coeff_ctl
*ctl
)
520 struct snd_kcontrol_new
*kcontrol
;
523 if (!ctl
|| !ctl
->name
)
526 kcontrol
= kzalloc(sizeof(*kcontrol
), GFP_KERNEL
);
529 kcontrol
->iface
= SNDRV_CTL_ELEM_IFACE_MIXER
;
531 kcontrol
->name
= ctl
->name
;
532 kcontrol
->info
= wm_coeff_info
;
533 kcontrol
->get
= wm_coeff_get
;
534 kcontrol
->put
= wm_coeff_put
;
535 kcontrol
->private_value
= (unsigned long)ctl
;
538 if (ctl
->flags
& WMFW_CTL_FLAG_WRITEABLE
)
539 kcontrol
->access
|= SNDRV_CTL_ELEM_ACCESS_WRITE
;
540 if (ctl
->flags
& WMFW_CTL_FLAG_READABLE
)
541 kcontrol
->access
|= SNDRV_CTL_ELEM_ACCESS_READ
;
542 if (ctl
->flags
& WMFW_CTL_FLAG_VOLATILE
)
543 kcontrol
->access
|= SNDRV_CTL_ELEM_ACCESS_VOLATILE
;
546 ret
= snd_soc_add_card_controls(dsp
->card
,
553 ctl
->kcontrol
= snd_soc_card_get_kcontrol(dsp
->card
,
563 static int wm_coeff_init_control_caches(struct wm_adsp
*dsp
)
565 struct wm_coeff_ctl
*ctl
;
568 list_for_each_entry(ctl
, &dsp
->ctl_list
, list
) {
569 if (!ctl
->enabled
|| ctl
->set
)
571 if (ctl
->flags
& WMFW_CTL_FLAG_VOLATILE
)
574 ret
= wm_coeff_read_control(ctl
,
584 static int wm_coeff_sync_controls(struct wm_adsp
*dsp
)
586 struct wm_coeff_ctl
*ctl
;
589 list_for_each_entry(ctl
, &dsp
->ctl_list
, list
) {
592 if (ctl
->set
&& !(ctl
->flags
& WMFW_CTL_FLAG_VOLATILE
)) {
593 ret
= wm_coeff_write_control(ctl
,
604 static void wm_adsp_ctl_work(struct work_struct
*work
)
606 struct wmfw_ctl_work
*ctl_work
= container_of(work
,
607 struct wmfw_ctl_work
,
610 wmfw_add_ctl(ctl_work
->dsp
, ctl_work
->ctl
);
614 static int wm_adsp_create_control(struct wm_adsp
*dsp
,
615 const struct wm_adsp_alg_region
*alg_region
,
616 unsigned int offset
, unsigned int len
,
617 const char *subname
, unsigned int subname_len
,
620 struct wm_coeff_ctl
*ctl
;
621 struct wmfw_ctl_work
*ctl_work
;
622 char name
[SNDRV_CTL_ELEM_ID_NAME_MAXLEN
];
626 if (flags
& WMFW_CTL_FLAG_SYS
)
629 switch (alg_region
->type
) {
646 adsp_err(dsp
, "Unknown region type: %d\n", alg_region
->type
);
650 switch (dsp
->fw_ver
) {
653 snprintf(name
, SNDRV_CTL_ELEM_ID_NAME_MAXLEN
, "DSP%d %s %x",
654 dsp
->num
, region_name
, alg_region
->alg
);
657 ret
= snprintf(name
, SNDRV_CTL_ELEM_ID_NAME_MAXLEN
,
658 "DSP%d%c %.12s %x", dsp
->num
, *region_name
,
659 wm_adsp_fw_text
[dsp
->fw
], alg_region
->alg
);
661 /* Truncate the subname from the start if it is too long */
663 int avail
= SNDRV_CTL_ELEM_ID_NAME_MAXLEN
- ret
- 2;
666 if (subname_len
> avail
)
667 skip
= subname_len
- avail
;
670 SNDRV_CTL_ELEM_ID_NAME_MAXLEN
- ret
, " %.*s",
671 subname_len
- skip
, subname
+ skip
);
676 list_for_each_entry(ctl
, &dsp
->ctl_list
,
678 if (!strcmp(ctl
->name
, name
)) {
685 ctl
= kzalloc(sizeof(*ctl
), GFP_KERNEL
);
688 ctl
->fw_name
= wm_adsp_fw_text
[dsp
->fw
];
689 ctl
->alg_region
= *alg_region
;
690 ctl
->name
= kmemdup(name
, strlen(name
) + 1, GFP_KERNEL
);
697 ctl
->ops
.xget
= wm_coeff_get
;
698 ctl
->ops
.xput
= wm_coeff_put
;
702 ctl
->offset
= offset
;
704 adsp_warn(dsp
, "Truncating control %s from %d\n",
709 ctl
->cache
= kzalloc(ctl
->len
, GFP_KERNEL
);
715 list_add(&ctl
->list
, &dsp
->ctl_list
);
717 ctl_work
= kzalloc(sizeof(*ctl_work
), GFP_KERNEL
);
725 INIT_WORK(&ctl_work
->work
, wm_adsp_ctl_work
);
726 schedule_work(&ctl_work
->work
);
740 struct wm_coeff_parsed_alg
{
747 struct wm_coeff_parsed_coeff
{
757 static int wm_coeff_parse_string(int bytes
, const u8
**pos
, const u8
**str
)
766 length
= le16_to_cpu(*((__le16
*)*pos
));
775 *pos
+= ((length
+ bytes
) + 3) & ~0x03;
780 static int wm_coeff_parse_int(int bytes
, const u8
**pos
)
786 val
= le16_to_cpu(*((__le16
*)*pos
));
789 val
= le32_to_cpu(*((__le32
*)*pos
));
800 static inline void wm_coeff_parse_alg(struct wm_adsp
*dsp
, const u8
**data
,
801 struct wm_coeff_parsed_alg
*blk
)
803 const struct wmfw_adsp_alg_data
*raw
;
805 switch (dsp
->fw_ver
) {
808 raw
= (const struct wmfw_adsp_alg_data
*)*data
;
811 blk
->id
= le32_to_cpu(raw
->id
);
812 blk
->name
= raw
->name
;
813 blk
->name_len
= strlen(raw
->name
);
814 blk
->ncoeff
= le32_to_cpu(raw
->ncoeff
);
817 blk
->id
= wm_coeff_parse_int(sizeof(raw
->id
), data
);
818 blk
->name_len
= wm_coeff_parse_string(sizeof(u8
), data
,
820 wm_coeff_parse_string(sizeof(u16
), data
, NULL
);
821 blk
->ncoeff
= wm_coeff_parse_int(sizeof(raw
->ncoeff
), data
);
825 adsp_dbg(dsp
, "Algorithm ID: %#x\n", blk
->id
);
826 adsp_dbg(dsp
, "Algorithm name: %.*s\n", blk
->name_len
, blk
->name
);
827 adsp_dbg(dsp
, "# of coefficient descriptors: %#x\n", blk
->ncoeff
);
830 static inline void wm_coeff_parse_coeff(struct wm_adsp
*dsp
, const u8
**data
,
831 struct wm_coeff_parsed_coeff
*blk
)
833 const struct wmfw_adsp_coeff_data
*raw
;
837 switch (dsp
->fw_ver
) {
840 raw
= (const struct wmfw_adsp_coeff_data
*)*data
;
841 *data
= *data
+ sizeof(raw
->hdr
) + le32_to_cpu(raw
->hdr
.size
);
843 blk
->offset
= le16_to_cpu(raw
->hdr
.offset
);
844 blk
->mem_type
= le16_to_cpu(raw
->hdr
.type
);
845 blk
->name
= raw
->name
;
846 blk
->name_len
= strlen(raw
->name
);
847 blk
->ctl_type
= le16_to_cpu(raw
->ctl_type
);
848 blk
->flags
= le16_to_cpu(raw
->flags
);
849 blk
->len
= le32_to_cpu(raw
->len
);
853 blk
->offset
= wm_coeff_parse_int(sizeof(raw
->hdr
.offset
), &tmp
);
854 blk
->mem_type
= wm_coeff_parse_int(sizeof(raw
->hdr
.type
), &tmp
);
855 length
= wm_coeff_parse_int(sizeof(raw
->hdr
.size
), &tmp
);
856 blk
->name_len
= wm_coeff_parse_string(sizeof(u8
), &tmp
,
858 wm_coeff_parse_string(sizeof(u8
), &tmp
, NULL
);
859 wm_coeff_parse_string(sizeof(u16
), &tmp
, NULL
);
860 blk
->ctl_type
= wm_coeff_parse_int(sizeof(raw
->ctl_type
), &tmp
);
861 blk
->flags
= wm_coeff_parse_int(sizeof(raw
->flags
), &tmp
);
862 blk
->len
= wm_coeff_parse_int(sizeof(raw
->len
), &tmp
);
864 *data
= *data
+ sizeof(raw
->hdr
) + length
;
868 adsp_dbg(dsp
, "\tCoefficient type: %#x\n", blk
->mem_type
);
869 adsp_dbg(dsp
, "\tCoefficient offset: %#x\n", blk
->offset
);
870 adsp_dbg(dsp
, "\tCoefficient name: %.*s\n", blk
->name_len
, blk
->name
);
871 adsp_dbg(dsp
, "\tCoefficient flags: %#x\n", blk
->flags
);
872 adsp_dbg(dsp
, "\tALSA control type: %#x\n", blk
->ctl_type
);
873 adsp_dbg(dsp
, "\tALSA control len: %#x\n", blk
->len
);
876 static int wm_adsp_parse_coeff(struct wm_adsp
*dsp
,
877 const struct wmfw_region
*region
)
879 struct wm_adsp_alg_region alg_region
= {};
880 struct wm_coeff_parsed_alg alg_blk
;
881 struct wm_coeff_parsed_coeff coeff_blk
;
882 const u8
*data
= region
->data
;
885 wm_coeff_parse_alg(dsp
, &data
, &alg_blk
);
886 for (i
= 0; i
< alg_blk
.ncoeff
; i
++) {
887 wm_coeff_parse_coeff(dsp
, &data
, &coeff_blk
);
889 switch (coeff_blk
.ctl_type
) {
890 case SNDRV_CTL_ELEM_TYPE_BYTES
:
893 adsp_err(dsp
, "Unknown control type: %d\n",
898 alg_region
.type
= coeff_blk
.mem_type
;
899 alg_region
.alg
= alg_blk
.id
;
901 ret
= wm_adsp_create_control(dsp
, &alg_region
,
908 adsp_err(dsp
, "Failed to create control: %.*s, %d\n",
909 coeff_blk
.name_len
, coeff_blk
.name
, ret
);
915 static int wm_adsp_load(struct wm_adsp
*dsp
)
918 const struct firmware
*firmware
;
919 struct regmap
*regmap
= dsp
->regmap
;
920 unsigned int pos
= 0;
921 const struct wmfw_header
*header
;
922 const struct wmfw_adsp1_sizes
*adsp1_sizes
;
923 const struct wmfw_adsp2_sizes
*adsp2_sizes
;
924 const struct wmfw_footer
*footer
;
925 const struct wmfw_region
*region
;
926 const struct wm_adsp_region
*mem
;
927 const char *region_name
;
929 struct wm_adsp_buf
*buf
;
932 int ret
, offset
, type
, sizes
;
934 file
= kzalloc(PAGE_SIZE
, GFP_KERNEL
);
938 snprintf(file
, PAGE_SIZE
, "%s-dsp%d-%s.wmfw", dsp
->part
, dsp
->num
,
939 wm_adsp_fw
[dsp
->fw
].file
);
940 file
[PAGE_SIZE
- 1] = '\0';
942 ret
= request_firmware(&firmware
, file
, dsp
->dev
);
944 adsp_err(dsp
, "Failed to request '%s'\n", file
);
949 pos
= sizeof(*header
) + sizeof(*adsp1_sizes
) + sizeof(*footer
);
950 if (pos
>= firmware
->size
) {
951 adsp_err(dsp
, "%s: file too short, %zu bytes\n",
952 file
, firmware
->size
);
956 header
= (void*)&firmware
->data
[0];
958 if (memcmp(&header
->magic
[0], "WMFW", 4) != 0) {
959 adsp_err(dsp
, "%s: invalid magic\n", file
);
963 switch (header
->ver
) {
965 adsp_warn(dsp
, "%s: Depreciated file format %d\n",
972 adsp_err(dsp
, "%s: unknown file format %d\n",
977 adsp_info(dsp
, "Firmware version: %d\n", header
->ver
);
978 dsp
->fw_ver
= header
->ver
;
980 if (header
->core
!= dsp
->type
) {
981 adsp_err(dsp
, "%s: invalid core %d != %d\n",
982 file
, header
->core
, dsp
->type
);
988 pos
= sizeof(*header
) + sizeof(*adsp1_sizes
) + sizeof(*footer
);
989 adsp1_sizes
= (void *)&(header
[1]);
990 footer
= (void *)&(adsp1_sizes
[1]);
991 sizes
= sizeof(*adsp1_sizes
);
993 adsp_dbg(dsp
, "%s: %d DM, %d PM, %d ZM\n",
994 file
, le32_to_cpu(adsp1_sizes
->dm
),
995 le32_to_cpu(adsp1_sizes
->pm
),
996 le32_to_cpu(adsp1_sizes
->zm
));
1000 pos
= sizeof(*header
) + sizeof(*adsp2_sizes
) + sizeof(*footer
);
1001 adsp2_sizes
= (void *)&(header
[1]);
1002 footer
= (void *)&(adsp2_sizes
[1]);
1003 sizes
= sizeof(*adsp2_sizes
);
1005 adsp_dbg(dsp
, "%s: %d XM, %d YM %d PM, %d ZM\n",
1006 file
, le32_to_cpu(adsp2_sizes
->xm
),
1007 le32_to_cpu(adsp2_sizes
->ym
),
1008 le32_to_cpu(adsp2_sizes
->pm
),
1009 le32_to_cpu(adsp2_sizes
->zm
));
1013 WARN(1, "Unknown DSP type");
1017 if (le32_to_cpu(header
->len
) != sizeof(*header
) +
1018 sizes
+ sizeof(*footer
)) {
1019 adsp_err(dsp
, "%s: unexpected header length %d\n",
1020 file
, le32_to_cpu(header
->len
));
1024 adsp_dbg(dsp
, "%s: timestamp %llu\n", file
,
1025 le64_to_cpu(footer
->timestamp
));
1027 while (pos
< firmware
->size
&&
1028 pos
- firmware
->size
> sizeof(*region
)) {
1029 region
= (void *)&(firmware
->data
[pos
]);
1030 region_name
= "Unknown";
1033 offset
= le32_to_cpu(region
->offset
) & 0xffffff;
1034 type
= be32_to_cpu(region
->type
) & 0xff;
1035 mem
= wm_adsp_find_region(dsp
, type
);
1038 case WMFW_NAME_TEXT
:
1039 region_name
= "Firmware name";
1040 text
= kzalloc(le32_to_cpu(region
->len
) + 1,
1043 case WMFW_ALGORITHM_DATA
:
1044 region_name
= "Algorithm";
1045 ret
= wm_adsp_parse_coeff(dsp
, region
);
1049 case WMFW_INFO_TEXT
:
1050 region_name
= "Information";
1051 text
= kzalloc(le32_to_cpu(region
->len
) + 1,
1055 region_name
= "Absolute";
1060 reg
= wm_adsp_region_to_reg(mem
, offset
);
1064 reg
= wm_adsp_region_to_reg(mem
, offset
);
1068 reg
= wm_adsp_region_to_reg(mem
, offset
);
1072 reg
= wm_adsp_region_to_reg(mem
, offset
);
1076 reg
= wm_adsp_region_to_reg(mem
, offset
);
1080 "%s.%d: Unknown region type %x at %d(%x)\n",
1081 file
, regions
, type
, pos
, pos
);
1085 adsp_dbg(dsp
, "%s.%d: %d bytes at %d in %s\n", file
,
1086 regions
, le32_to_cpu(region
->len
), offset
,
1090 memcpy(text
, region
->data
, le32_to_cpu(region
->len
));
1091 adsp_info(dsp
, "%s: %s\n", file
, text
);
1096 buf
= wm_adsp_buf_alloc(region
->data
,
1097 le32_to_cpu(region
->len
),
1100 adsp_err(dsp
, "Out of memory\n");
1105 ret
= regmap_raw_write_async(regmap
, reg
, buf
->buf
,
1106 le32_to_cpu(region
->len
));
1109 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
1111 le32_to_cpu(region
->len
), offset
,
1117 pos
+= le32_to_cpu(region
->len
) + sizeof(*region
);
1121 ret
= regmap_async_complete(regmap
);
1123 adsp_err(dsp
, "Failed to complete async write: %d\n", ret
);
1127 if (pos
> firmware
->size
)
1128 adsp_warn(dsp
, "%s.%d: %zu bytes at end of file\n",
1129 file
, regions
, pos
- firmware
->size
);
1132 regmap_async_complete(regmap
);
1133 wm_adsp_buf_free(&buf_list
);
1134 release_firmware(firmware
);
1141 static void wm_adsp_ctl_fixup_base(struct wm_adsp
*dsp
,
1142 const struct wm_adsp_alg_region
*alg_region
)
1144 struct wm_coeff_ctl
*ctl
;
1146 list_for_each_entry(ctl
, &dsp
->ctl_list
, list
) {
1147 if (ctl
->fw_name
== wm_adsp_fw_text
[dsp
->fw
] &&
1148 alg_region
->alg
== ctl
->alg_region
.alg
&&
1149 alg_region
->type
== ctl
->alg_region
.type
) {
1150 ctl
->alg_region
.base
= alg_region
->base
;
1155 static void *wm_adsp_read_algs(struct wm_adsp
*dsp
, size_t n_algs
,
1156 unsigned int pos
, unsigned int len
)
1163 adsp_err(dsp
, "No algorithms\n");
1164 return ERR_PTR(-EINVAL
);
1167 if (n_algs
> 1024) {
1168 adsp_err(dsp
, "Algorithm count %zx excessive\n", n_algs
);
1169 return ERR_PTR(-EINVAL
);
1172 /* Read the terminator first to validate the length */
1173 ret
= regmap_raw_read(dsp
->regmap
, pos
+ len
, &val
, sizeof(val
));
1175 adsp_err(dsp
, "Failed to read algorithm list end: %d\n",
1177 return ERR_PTR(ret
);
1180 if (be32_to_cpu(val
) != 0xbedead)
1181 adsp_warn(dsp
, "Algorithm list end %x 0x%x != 0xbeadead\n",
1182 pos
+ len
, be32_to_cpu(val
));
1184 alg
= kzalloc(len
* 2, GFP_KERNEL
| GFP_DMA
);
1186 return ERR_PTR(-ENOMEM
);
1188 ret
= regmap_raw_read(dsp
->regmap
, pos
, alg
, len
* 2);
1190 adsp_err(dsp
, "Failed to read algorithm list: %d\n",
1193 return ERR_PTR(ret
);
1199 static struct wm_adsp_alg_region
*wm_adsp_create_region(struct wm_adsp
*dsp
,
1200 int type
, __be32 id
,
1203 struct wm_adsp_alg_region
*alg_region
;
1205 alg_region
= kzalloc(sizeof(*alg_region
), GFP_KERNEL
);
1207 return ERR_PTR(-ENOMEM
);
1209 alg_region
->type
= type
;
1210 alg_region
->alg
= be32_to_cpu(id
);
1211 alg_region
->base
= be32_to_cpu(base
);
1213 list_add_tail(&alg_region
->list
, &dsp
->alg_regions
);
1215 if (dsp
->fw_ver
> 0)
1216 wm_adsp_ctl_fixup_base(dsp
, alg_region
);
1221 static int wm_adsp1_setup_algs(struct wm_adsp
*dsp
)
1223 struct wmfw_adsp1_id_hdr adsp1_id
;
1224 struct wmfw_adsp1_alg_hdr
*adsp1_alg
;
1225 struct wm_adsp_alg_region
*alg_region
;
1226 const struct wm_adsp_region
*mem
;
1227 unsigned int pos
, len
;
1231 mem
= wm_adsp_find_region(dsp
, WMFW_ADSP1_DM
);
1235 ret
= regmap_raw_read(dsp
->regmap
, mem
->base
, &adsp1_id
,
1238 adsp_err(dsp
, "Failed to read algorithm info: %d\n",
1243 n_algs
= be32_to_cpu(adsp1_id
.n_algs
);
1244 dsp
->fw_id
= be32_to_cpu(adsp1_id
.fw
.id
);
1245 adsp_info(dsp
, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
1247 (be32_to_cpu(adsp1_id
.fw
.ver
) & 0xff0000) >> 16,
1248 (be32_to_cpu(adsp1_id
.fw
.ver
) & 0xff00) >> 8,
1249 be32_to_cpu(adsp1_id
.fw
.ver
) & 0xff,
1252 alg_region
= wm_adsp_create_region(dsp
, WMFW_ADSP1_ZM
,
1253 adsp1_id
.fw
.id
, adsp1_id
.zm
);
1254 if (IS_ERR(alg_region
))
1255 return PTR_ERR(alg_region
);
1257 alg_region
= wm_adsp_create_region(dsp
, WMFW_ADSP1_DM
,
1258 adsp1_id
.fw
.id
, adsp1_id
.dm
);
1259 if (IS_ERR(alg_region
))
1260 return PTR_ERR(alg_region
);
1262 pos
= sizeof(adsp1_id
) / 2;
1263 len
= (sizeof(*adsp1_alg
) * n_algs
) / 2;
1265 adsp1_alg
= wm_adsp_read_algs(dsp
, n_algs
, mem
->base
+ pos
, len
);
1266 if (IS_ERR(adsp1_alg
))
1267 return PTR_ERR(adsp1_alg
);
1269 for (i
= 0; i
< n_algs
; i
++) {
1270 adsp_info(dsp
, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
1271 i
, be32_to_cpu(adsp1_alg
[i
].alg
.id
),
1272 (be32_to_cpu(adsp1_alg
[i
].alg
.ver
) & 0xff0000) >> 16,
1273 (be32_to_cpu(adsp1_alg
[i
].alg
.ver
) & 0xff00) >> 8,
1274 be32_to_cpu(adsp1_alg
[i
].alg
.ver
) & 0xff,
1275 be32_to_cpu(adsp1_alg
[i
].dm
),
1276 be32_to_cpu(adsp1_alg
[i
].zm
));
1278 alg_region
= wm_adsp_create_region(dsp
, WMFW_ADSP1_DM
,
1279 adsp1_alg
[i
].alg
.id
,
1281 if (IS_ERR(alg_region
)) {
1282 ret
= PTR_ERR(alg_region
);
1285 if (dsp
->fw_ver
== 0) {
1286 if (i
+ 1 < n_algs
) {
1287 len
= be32_to_cpu(adsp1_alg
[i
+ 1].dm
);
1288 len
-= be32_to_cpu(adsp1_alg
[i
].dm
);
1290 wm_adsp_create_control(dsp
, alg_region
, 0,
1293 adsp_warn(dsp
, "Missing length info for region DM with ID %x\n",
1294 be32_to_cpu(adsp1_alg
[i
].alg
.id
));
1298 alg_region
= wm_adsp_create_region(dsp
, WMFW_ADSP1_ZM
,
1299 adsp1_alg
[i
].alg
.id
,
1301 if (IS_ERR(alg_region
)) {
1302 ret
= PTR_ERR(alg_region
);
1305 if (dsp
->fw_ver
== 0) {
1306 if (i
+ 1 < n_algs
) {
1307 len
= be32_to_cpu(adsp1_alg
[i
+ 1].zm
);
1308 len
-= be32_to_cpu(adsp1_alg
[i
].zm
);
1310 wm_adsp_create_control(dsp
, alg_region
, 0,
1313 adsp_warn(dsp
, "Missing length info for region ZM with ID %x\n",
1314 be32_to_cpu(adsp1_alg
[i
].alg
.id
));
1324 static int wm_adsp2_setup_algs(struct wm_adsp
*dsp
)
1326 struct wmfw_adsp2_id_hdr adsp2_id
;
1327 struct wmfw_adsp2_alg_hdr
*adsp2_alg
;
1328 struct wm_adsp_alg_region
*alg_region
;
1329 const struct wm_adsp_region
*mem
;
1330 unsigned int pos
, len
;
1334 mem
= wm_adsp_find_region(dsp
, WMFW_ADSP2_XM
);
1338 ret
= regmap_raw_read(dsp
->regmap
, mem
->base
, &adsp2_id
,
1341 adsp_err(dsp
, "Failed to read algorithm info: %d\n",
1346 n_algs
= be32_to_cpu(adsp2_id
.n_algs
);
1347 dsp
->fw_id
= be32_to_cpu(adsp2_id
.fw
.id
);
1348 adsp_info(dsp
, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
1350 (be32_to_cpu(adsp2_id
.fw
.ver
) & 0xff0000) >> 16,
1351 (be32_to_cpu(adsp2_id
.fw
.ver
) & 0xff00) >> 8,
1352 be32_to_cpu(adsp2_id
.fw
.ver
) & 0xff,
1355 alg_region
= wm_adsp_create_region(dsp
, WMFW_ADSP2_XM
,
1356 adsp2_id
.fw
.id
, adsp2_id
.xm
);
1357 if (IS_ERR(alg_region
))
1358 return PTR_ERR(alg_region
);
1360 alg_region
= wm_adsp_create_region(dsp
, WMFW_ADSP2_YM
,
1361 adsp2_id
.fw
.id
, adsp2_id
.ym
);
1362 if (IS_ERR(alg_region
))
1363 return PTR_ERR(alg_region
);
1365 alg_region
= wm_adsp_create_region(dsp
, WMFW_ADSP2_ZM
,
1366 adsp2_id
.fw
.id
, adsp2_id
.zm
);
1367 if (IS_ERR(alg_region
))
1368 return PTR_ERR(alg_region
);
1370 pos
= sizeof(adsp2_id
) / 2;
1371 len
= (sizeof(*adsp2_alg
) * n_algs
) / 2;
1373 adsp2_alg
= wm_adsp_read_algs(dsp
, n_algs
, mem
->base
+ pos
, len
);
1374 if (IS_ERR(adsp2_alg
))
1375 return PTR_ERR(adsp2_alg
);
1377 for (i
= 0; i
< n_algs
; i
++) {
1379 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
1380 i
, be32_to_cpu(adsp2_alg
[i
].alg
.id
),
1381 (be32_to_cpu(adsp2_alg
[i
].alg
.ver
) & 0xff0000) >> 16,
1382 (be32_to_cpu(adsp2_alg
[i
].alg
.ver
) & 0xff00) >> 8,
1383 be32_to_cpu(adsp2_alg
[i
].alg
.ver
) & 0xff,
1384 be32_to_cpu(adsp2_alg
[i
].xm
),
1385 be32_to_cpu(adsp2_alg
[i
].ym
),
1386 be32_to_cpu(adsp2_alg
[i
].zm
));
1388 alg_region
= wm_adsp_create_region(dsp
, WMFW_ADSP2_XM
,
1389 adsp2_alg
[i
].alg
.id
,
1391 if (IS_ERR(alg_region
)) {
1392 ret
= PTR_ERR(alg_region
);
1395 if (dsp
->fw_ver
== 0) {
1396 if (i
+ 1 < n_algs
) {
1397 len
= be32_to_cpu(adsp2_alg
[i
+ 1].xm
);
1398 len
-= be32_to_cpu(adsp2_alg
[i
].xm
);
1400 wm_adsp_create_control(dsp
, alg_region
, 0,
1403 adsp_warn(dsp
, "Missing length info for region XM with ID %x\n",
1404 be32_to_cpu(adsp2_alg
[i
].alg
.id
));
1408 alg_region
= wm_adsp_create_region(dsp
, WMFW_ADSP2_YM
,
1409 adsp2_alg
[i
].alg
.id
,
1411 if (IS_ERR(alg_region
)) {
1412 ret
= PTR_ERR(alg_region
);
1415 if (dsp
->fw_ver
== 0) {
1416 if (i
+ 1 < n_algs
) {
1417 len
= be32_to_cpu(adsp2_alg
[i
+ 1].ym
);
1418 len
-= be32_to_cpu(adsp2_alg
[i
].ym
);
1420 wm_adsp_create_control(dsp
, alg_region
, 0,
1423 adsp_warn(dsp
, "Missing length info for region YM with ID %x\n",
1424 be32_to_cpu(adsp2_alg
[i
].alg
.id
));
1428 alg_region
= wm_adsp_create_region(dsp
, WMFW_ADSP2_ZM
,
1429 adsp2_alg
[i
].alg
.id
,
1431 if (IS_ERR(alg_region
)) {
1432 ret
= PTR_ERR(alg_region
);
1435 if (dsp
->fw_ver
== 0) {
1436 if (i
+ 1 < n_algs
) {
1437 len
= be32_to_cpu(adsp2_alg
[i
+ 1].zm
);
1438 len
-= be32_to_cpu(adsp2_alg
[i
].zm
);
1440 wm_adsp_create_control(dsp
, alg_region
, 0,
1443 adsp_warn(dsp
, "Missing length info for region ZM with ID %x\n",
1444 be32_to_cpu(adsp2_alg
[i
].alg
.id
));
1454 static int wm_adsp_load_coeff(struct wm_adsp
*dsp
)
1456 LIST_HEAD(buf_list
);
1457 struct regmap
*regmap
= dsp
->regmap
;
1458 struct wmfw_coeff_hdr
*hdr
;
1459 struct wmfw_coeff_item
*blk
;
1460 const struct firmware
*firmware
;
1461 const struct wm_adsp_region
*mem
;
1462 struct wm_adsp_alg_region
*alg_region
;
1463 const char *region_name
;
1464 int ret
, pos
, blocks
, type
, offset
, reg
;
1466 struct wm_adsp_buf
*buf
;
1468 file
= kzalloc(PAGE_SIZE
, GFP_KERNEL
);
1472 snprintf(file
, PAGE_SIZE
, "%s-dsp%d-%s.bin", dsp
->part
, dsp
->num
,
1473 wm_adsp_fw
[dsp
->fw
].file
);
1474 file
[PAGE_SIZE
- 1] = '\0';
1476 ret
= request_firmware(&firmware
, file
, dsp
->dev
);
1478 adsp_warn(dsp
, "Failed to request '%s'\n", file
);
1484 if (sizeof(*hdr
) >= firmware
->size
) {
1485 adsp_err(dsp
, "%s: file too short, %zu bytes\n",
1486 file
, firmware
->size
);
1490 hdr
= (void*)&firmware
->data
[0];
1491 if (memcmp(hdr
->magic
, "WMDR", 4) != 0) {
1492 adsp_err(dsp
, "%s: invalid magic\n", file
);
1496 switch (be32_to_cpu(hdr
->rev
) & 0xff) {
1500 adsp_err(dsp
, "%s: Unsupported coefficient file format %d\n",
1501 file
, be32_to_cpu(hdr
->rev
) & 0xff);
1506 adsp_dbg(dsp
, "%s: v%d.%d.%d\n", file
,
1507 (le32_to_cpu(hdr
->ver
) >> 16) & 0xff,
1508 (le32_to_cpu(hdr
->ver
) >> 8) & 0xff,
1509 le32_to_cpu(hdr
->ver
) & 0xff);
1511 pos
= le32_to_cpu(hdr
->len
);
1514 while (pos
< firmware
->size
&&
1515 pos
- firmware
->size
> sizeof(*blk
)) {
1516 blk
= (void*)(&firmware
->data
[pos
]);
1518 type
= le16_to_cpu(blk
->type
);
1519 offset
= le16_to_cpu(blk
->offset
);
1521 adsp_dbg(dsp
, "%s.%d: %x v%d.%d.%d\n",
1522 file
, blocks
, le32_to_cpu(blk
->id
),
1523 (le32_to_cpu(blk
->ver
) >> 16) & 0xff,
1524 (le32_to_cpu(blk
->ver
) >> 8) & 0xff,
1525 le32_to_cpu(blk
->ver
) & 0xff);
1526 adsp_dbg(dsp
, "%s.%d: %d bytes at 0x%x in %x\n",
1527 file
, blocks
, le32_to_cpu(blk
->len
), offset
, type
);
1530 region_name
= "Unknown";
1532 case (WMFW_NAME_TEXT
<< 8):
1533 case (WMFW_INFO_TEXT
<< 8):
1535 case (WMFW_ABSOLUTE
<< 8):
1537 * Old files may use this for global
1540 if (le32_to_cpu(blk
->id
) == dsp
->fw_id
&&
1542 region_name
= "global coefficients";
1543 mem
= wm_adsp_find_region(dsp
, type
);
1545 adsp_err(dsp
, "No ZM\n");
1548 reg
= wm_adsp_region_to_reg(mem
, 0);
1551 region_name
= "register";
1560 adsp_dbg(dsp
, "%s.%d: %d bytes in %x for %x\n",
1561 file
, blocks
, le32_to_cpu(blk
->len
),
1562 type
, le32_to_cpu(blk
->id
));
1564 mem
= wm_adsp_find_region(dsp
, type
);
1566 adsp_err(dsp
, "No base for region %x\n", type
);
1571 list_for_each_entry(alg_region
,
1572 &dsp
->alg_regions
, list
) {
1573 if (le32_to_cpu(blk
->id
) == alg_region
->alg
&&
1574 type
== alg_region
->type
) {
1575 reg
= alg_region
->base
;
1576 reg
= wm_adsp_region_to_reg(mem
,
1584 adsp_err(dsp
, "No %x for algorithm %x\n",
1585 type
, le32_to_cpu(blk
->id
));
1589 adsp_err(dsp
, "%s.%d: Unknown region type %x at %d\n",
1590 file
, blocks
, type
, pos
);
1595 buf
= wm_adsp_buf_alloc(blk
->data
,
1596 le32_to_cpu(blk
->len
),
1599 adsp_err(dsp
, "Out of memory\n");
1604 adsp_dbg(dsp
, "%s.%d: Writing %d bytes at %x\n",
1605 file
, blocks
, le32_to_cpu(blk
->len
),
1607 ret
= regmap_raw_write_async(regmap
, reg
, buf
->buf
,
1608 le32_to_cpu(blk
->len
));
1611 "%s.%d: Failed to write to %x in %s: %d\n",
1612 file
, blocks
, reg
, region_name
, ret
);
1616 pos
+= (le32_to_cpu(blk
->len
) + sizeof(*blk
) + 3) & ~0x03;
1620 ret
= regmap_async_complete(regmap
);
1622 adsp_err(dsp
, "Failed to complete async write: %d\n", ret
);
1624 if (pos
> firmware
->size
)
1625 adsp_warn(dsp
, "%s.%d: %zu bytes at end of file\n",
1626 file
, blocks
, pos
- firmware
->size
);
1629 regmap_async_complete(regmap
);
1630 release_firmware(firmware
);
1631 wm_adsp_buf_free(&buf_list
);
1637 int wm_adsp1_init(struct wm_adsp
*dsp
)
1639 INIT_LIST_HEAD(&dsp
->alg_regions
);
1643 EXPORT_SYMBOL_GPL(wm_adsp1_init
);
1645 int wm_adsp1_event(struct snd_soc_dapm_widget
*w
,
1646 struct snd_kcontrol
*kcontrol
,
1649 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
1650 struct wm_adsp
*dsps
= snd_soc_codec_get_drvdata(codec
);
1651 struct wm_adsp
*dsp
= &dsps
[w
->shift
];
1652 struct wm_adsp_alg_region
*alg_region
;
1653 struct wm_coeff_ctl
*ctl
;
1657 dsp
->card
= codec
->component
.card
;
1660 case SND_SOC_DAPM_POST_PMU
:
1661 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP1_CONTROL_30
,
1662 ADSP1_SYS_ENA
, ADSP1_SYS_ENA
);
1665 * For simplicity set the DSP clock rate to be the
1666 * SYSCLK rate rather than making it configurable.
1668 if(dsp
->sysclk_reg
) {
1669 ret
= regmap_read(dsp
->regmap
, dsp
->sysclk_reg
, &val
);
1671 adsp_err(dsp
, "Failed to read SYSCLK state: %d\n",
1676 val
= (val
& dsp
->sysclk_mask
)
1677 >> dsp
->sysclk_shift
;
1679 ret
= regmap_update_bits(dsp
->regmap
,
1680 dsp
->base
+ ADSP1_CONTROL_31
,
1681 ADSP1_CLK_SEL_MASK
, val
);
1683 adsp_err(dsp
, "Failed to set clock rate: %d\n",
1689 ret
= wm_adsp_load(dsp
);
1693 ret
= wm_adsp1_setup_algs(dsp
);
1697 ret
= wm_adsp_load_coeff(dsp
);
1701 /* Initialize caches for enabled and unset controls */
1702 ret
= wm_coeff_init_control_caches(dsp
);
1706 /* Sync set controls */
1707 ret
= wm_coeff_sync_controls(dsp
);
1711 /* Start the core running */
1712 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP1_CONTROL_30
,
1713 ADSP1_CORE_ENA
| ADSP1_START
,
1714 ADSP1_CORE_ENA
| ADSP1_START
);
1717 case SND_SOC_DAPM_PRE_PMD
:
1719 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP1_CONTROL_30
,
1720 ADSP1_CORE_ENA
| ADSP1_START
, 0);
1722 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP1_CONTROL_19
,
1723 ADSP1_WDMA_BUFFER_LENGTH_MASK
, 0);
1725 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP1_CONTROL_30
,
1728 list_for_each_entry(ctl
, &dsp
->ctl_list
, list
)
1731 while (!list_empty(&dsp
->alg_regions
)) {
1732 alg_region
= list_first_entry(&dsp
->alg_regions
,
1733 struct wm_adsp_alg_region
,
1735 list_del(&alg_region
->list
);
1747 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP1_CONTROL_30
,
1751 EXPORT_SYMBOL_GPL(wm_adsp1_event
);
1753 static int wm_adsp2_ena(struct wm_adsp
*dsp
)
1758 ret
= regmap_update_bits_async(dsp
->regmap
, dsp
->base
+ ADSP2_CONTROL
,
1759 ADSP2_SYS_ENA
, ADSP2_SYS_ENA
);
1763 /* Wait for the RAM to start, should be near instantaneous */
1764 for (count
= 0; count
< 10; ++count
) {
1765 ret
= regmap_read(dsp
->regmap
, dsp
->base
+ ADSP2_STATUS1
,
1770 if (val
& ADSP2_RAM_RDY
)
1776 if (!(val
& ADSP2_RAM_RDY
)) {
1777 adsp_err(dsp
, "Failed to start DSP RAM\n");
1781 adsp_dbg(dsp
, "RAM ready after %d polls\n", count
);
1786 static void wm_adsp2_boot_work(struct work_struct
*work
)
1788 struct wm_adsp
*dsp
= container_of(work
,
1795 * For simplicity set the DSP clock rate to be the
1796 * SYSCLK rate rather than making it configurable.
1798 ret
= regmap_read(dsp
->regmap
, ARIZONA_SYSTEM_CLOCK_1
, &val
);
1800 adsp_err(dsp
, "Failed to read SYSCLK state: %d\n", ret
);
1803 val
= (val
& ARIZONA_SYSCLK_FREQ_MASK
)
1804 >> ARIZONA_SYSCLK_FREQ_SHIFT
;
1806 ret
= regmap_update_bits_async(dsp
->regmap
,
1807 dsp
->base
+ ADSP2_CLOCKING
,
1808 ADSP2_CLK_SEL_MASK
, val
);
1810 adsp_err(dsp
, "Failed to set clock rate: %d\n", ret
);
1814 ret
= wm_adsp2_ena(dsp
);
1818 ret
= wm_adsp_load(dsp
);
1822 ret
= wm_adsp2_setup_algs(dsp
);
1826 ret
= wm_adsp_load_coeff(dsp
);
1830 /* Initialize caches for enabled and unset controls */
1831 ret
= wm_coeff_init_control_caches(dsp
);
1835 /* Sync set controls */
1836 ret
= wm_coeff_sync_controls(dsp
);
1840 dsp
->running
= true;
1845 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP2_CONTROL
,
1846 ADSP2_SYS_ENA
| ADSP2_CORE_ENA
| ADSP2_START
, 0);
1849 int wm_adsp2_early_event(struct snd_soc_dapm_widget
*w
,
1850 struct snd_kcontrol
*kcontrol
, int event
)
1852 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
1853 struct wm_adsp
*dsps
= snd_soc_codec_get_drvdata(codec
);
1854 struct wm_adsp
*dsp
= &dsps
[w
->shift
];
1856 dsp
->card
= codec
->component
.card
;
1859 case SND_SOC_DAPM_PRE_PMU
:
1860 queue_work(system_unbound_wq
, &dsp
->boot_work
);
1868 EXPORT_SYMBOL_GPL(wm_adsp2_early_event
);
1870 int wm_adsp2_event(struct snd_soc_dapm_widget
*w
,
1871 struct snd_kcontrol
*kcontrol
, int event
)
1873 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
1874 struct wm_adsp
*dsps
= snd_soc_codec_get_drvdata(codec
);
1875 struct wm_adsp
*dsp
= &dsps
[w
->shift
];
1876 struct wm_adsp_alg_region
*alg_region
;
1877 struct wm_coeff_ctl
*ctl
;
1881 case SND_SOC_DAPM_POST_PMU
:
1882 flush_work(&dsp
->boot_work
);
1887 ret
= regmap_update_bits(dsp
->regmap
,
1888 dsp
->base
+ ADSP2_CONTROL
,
1889 ADSP2_CORE_ENA
| ADSP2_START
,
1890 ADSP2_CORE_ENA
| ADSP2_START
);
1895 case SND_SOC_DAPM_PRE_PMD
:
1896 /* Log firmware state, it can be useful for analysis */
1897 wm_adsp2_show_fw_status(dsp
);
1899 dsp
->running
= false;
1901 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP2_CONTROL
,
1902 ADSP2_SYS_ENA
| ADSP2_CORE_ENA
|
1905 /* Make sure DMAs are quiesced */
1906 regmap_write(dsp
->regmap
, dsp
->base
+ ADSP2_WDMA_CONFIG_1
, 0);
1907 regmap_write(dsp
->regmap
, dsp
->base
+ ADSP2_WDMA_CONFIG_2
, 0);
1908 regmap_write(dsp
->regmap
, dsp
->base
+ ADSP2_RDMA_CONFIG_1
, 0);
1910 list_for_each_entry(ctl
, &dsp
->ctl_list
, list
)
1913 while (!list_empty(&dsp
->alg_regions
)) {
1914 alg_region
= list_first_entry(&dsp
->alg_regions
,
1915 struct wm_adsp_alg_region
,
1917 list_del(&alg_region
->list
);
1921 adsp_dbg(dsp
, "Shutdown complete\n");
1930 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP2_CONTROL
,
1931 ADSP2_SYS_ENA
| ADSP2_CORE_ENA
| ADSP2_START
, 0);
1934 EXPORT_SYMBOL_GPL(wm_adsp2_event
);
1936 int wm_adsp2_init(struct wm_adsp
*dsp
)
1941 * Disable the DSP memory by default when in reset for a small
1944 ret
= regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP2_CONTROL
,
1947 adsp_err(dsp
, "Failed to clear memory retention: %d\n", ret
);
1951 INIT_LIST_HEAD(&dsp
->alg_regions
);
1952 INIT_LIST_HEAD(&dsp
->ctl_list
);
1953 INIT_WORK(&dsp
->boot_work
, wm_adsp2_boot_work
);
1957 EXPORT_SYMBOL_GPL(wm_adsp2_init
);
1959 MODULE_LICENSE("GPL v2");