sound/soc/davinci/davinci-i2s.c

   1 /*
   2  * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
   3  *
   4  * Author:      Vladimir Barinov, <vbarinov@embeddedalley.com>
   5  * Copyright:   (C) 2007 MontaVista Software, Inc., <source@mvista.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/device.h>
  15 #include <linux/delay.h>
  16 #include <linux/io.h>
  17 #include <linux/clk.h>
  18
  19 #include <sound/core.h>
  20 #include <sound/pcm.h>
  21 #include <sound/pcm_params.h>
  22 #include <sound/initval.h>
  23 #include <sound/soc.h>
  24
  25 #include "davinci-pcm.h"
  26
  27
  28 /*
  29  * NOTE:  terminology here is confusing.
  30  *
  31  *  - This driver supports the "Audio Serial Port" (ASP),
  32  *    found on dm6446, dm355, and other DaVinci chips.
  33  *
  34  *  - But it labels it a "Multi-channel Buffered Serial Port"
  35  *    (McBSP) as on older chips like the dm642 ... which was
  36  *    backward-compatible, possibly explaining that confusion.
  37  *
  38  *  - OMAP chips have a controller called McBSP, which is
  39  *    incompatible with the DaVinci flavor of McBSP.
  40  *
  41  *  - Newer DaVinci chips have a controller called McASP,
  42  *    incompatible with ASP and with either McBSP.
  43  *
  44  * In short:  this uses ASP to implement I2S, not McBSP.
  45  * And it won't be the only DaVinci implemention of I2S.
  46  */
  47 #define DAVINCI_MCBSP_DRR_REG   0x00
  48 #define DAVINCI_MCBSP_DXR_REG   0x04
  49 #define DAVINCI_MCBSP_SPCR_REG  0x08
  50 #define DAVINCI_MCBSP_RCR_REG   0x0c
  51 #define DAVINCI_MCBSP_XCR_REG   0x10
  52 #define DAVINCI_MCBSP_SRGR_REG  0x14
  53 #define DAVINCI_MCBSP_PCR_REG   0x24
  54
  55 #define DAVINCI_MCBSP_SPCR_RRST         (1 << 0)
  56 #define DAVINCI_MCBSP_SPCR_RINTM(v)     ((v) << 4)
  57 #define DAVINCI_MCBSP_SPCR_XRST         (1 << 16)
  58 #define DAVINCI_MCBSP_SPCR_XINTM(v)     ((v) << 20)
  59 #define DAVINCI_MCBSP_SPCR_GRST         (1 << 22)
  60 #define DAVINCI_MCBSP_SPCR_FRST         (1 << 23)
  61 #define DAVINCI_MCBSP_SPCR_FREE         (1 << 25)
  62
  63 #define DAVINCI_MCBSP_RCR_RWDLEN1(v)    ((v) << 5)
  64 #define DAVINCI_MCBSP_RCR_RFRLEN1(v)    ((v) << 8)
  65 #define DAVINCI_MCBSP_RCR_RDATDLY(v)    ((v) << 16)
  66 #define DAVINCI_MCBSP_RCR_RWDLEN2(v)    ((v) << 21)
  67
  68 #define DAVINCI_MCBSP_XCR_XWDLEN1(v)    ((v) << 5)
  69 #define DAVINCI_MCBSP_XCR_XFRLEN1(v)    ((v) << 8)
  70 #define DAVINCI_MCBSP_XCR_XDATDLY(v)    ((v) << 16)
  71 #define DAVINCI_MCBSP_XCR_XFIG          (1 << 18)
  72 #define DAVINCI_MCBSP_XCR_XWDLEN2(v)    ((v) << 21)
  73
  74 #define DAVINCI_MCBSP_SRGR_FWID(v)      ((v) << 8)
  75 #define DAVINCI_MCBSP_SRGR_FPER(v)      ((v) << 16)
  76 #define DAVINCI_MCBSP_SRGR_FSGM         (1 << 28)
  77
  78 #define DAVINCI_MCBSP_PCR_CLKRP         (1 << 0)
  79 #define DAVINCI_MCBSP_PCR_CLKXP         (1 << 1)
  80 #define DAVINCI_MCBSP_PCR_FSRP          (1 << 2)
  81 #define DAVINCI_MCBSP_PCR_FSXP          (1 << 3)
  82 #define DAVINCI_MCBSP_PCR_SCLKME        (1 << 7)
  83 #define DAVINCI_MCBSP_PCR_CLKRM         (1 << 8)
  84 #define DAVINCI_MCBSP_PCR_CLKXM         (1 << 9)
  85 #define DAVINCI_MCBSP_PCR_FSRM          (1 << 10)
  86 #define DAVINCI_MCBSP_PCR_FSXM          (1 << 11)
  87
  88 enum {
  89         DAVINCI_MCBSP_WORD_8 = 0,
  90         DAVINCI_MCBSP_WORD_12,
  91         DAVINCI_MCBSP_WORD_16,
  92         DAVINCI_MCBSP_WORD_20,
  93         DAVINCI_MCBSP_WORD_24,
  94         DAVINCI_MCBSP_WORD_32,
  95 };
  96
  97 static struct davinci_pcm_dma_params davinci_i2s_pcm_out = {
  98         .name = "I2S PCM Stereo out",
  99 };
 100
 101 static struct davinci_pcm_dma_params davinci_i2s_pcm_in = {
 102         .name = "I2S PCM Stereo in",
 103 };
 104
 105 struct davinci_mcbsp_dev {
 106         void __iomem                    *base;
 107         u32                             pcr;
 108         struct clk                      *clk;
 109         struct davinci_pcm_dma_params   *dma_params[2];
 110 };
 111
 112 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
 113                                            int reg, u32 val)
 114 {
 115         __raw_writel(val, dev->base + reg);
 116 }
 117
 118 static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
 119 {
 120         return __raw_readl(dev->base + reg);
 121 }
 122
 123 static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback)
 124 {
 125         u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP;
 126         /* The clock needs to toggle to complete reset.
 127          * So, fake it by toggling the clk polarity.
 128          */
 129         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m);
 130         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr);
 131 }
 132
 133 static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev,
 134                 struct snd_pcm_substream *substream)
 135 {
 136         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 137         struct snd_soc_device *socdev = rtd->socdev;
 138         struct snd_soc_platform *platform = socdev->card->platform;
 139         int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 140         u32 spcr;
 141         u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
 142         spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 143         if (spcr & mask) {
 144                 /* start off disabled */
 145                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
 146                                 spcr & ~mask);
 147                 toggle_clock(dev, playback);
 148         }
 149         /* Start the sample generator and enable transmitter/receiver */
 150         spcr |= DAVINCI_MCBSP_SPCR_GRST;
 151         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 152
 153         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 154                 /* Stop the DMA to avoid data loss */
 155                 /* while the transmitter is out of reset to handle XSYNCERR */
 156                 if (platform->pcm_ops->trigger) {
 157                         int ret = platform->pcm_ops->trigger(substream,
 158                                 SNDRV_PCM_TRIGGER_STOP);
 159                         if (ret < 0)
 160                                 printk(KERN_DEBUG "Playback DMA stop failed\n");
 161                 }
 162
 163                 /* Enable the transmitter */
 164                 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 165                 spcr |= DAVINCI_MCBSP_SPCR_XRST;
 166                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 167
 168                 /* wait for any unexpected frame sync error to occur */
 169                 udelay(100);
 170
 171                 /* Disable the transmitter to clear any outstanding XSYNCERR */
 172                 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 173                 spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
 174                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 175                 toggle_clock(dev, playback);
 176
 177                 /* Restart the DMA */
 178                 if (platform->pcm_ops->trigger) {
 179                         int ret = platform->pcm_ops->trigger(substream,
 180                                 SNDRV_PCM_TRIGGER_START);
 181                         if (ret < 0)
 182                                 printk(KERN_DEBUG "Playback DMA start failed\n");
 183                 }
 184                 /* Enable the transmitter */
 185                 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 186                 spcr |= DAVINCI_MCBSP_SPCR_XRST;
 187                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 188
 189         } else {
 190
 191                 /* Enable the reciever */
 192                 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 193                 spcr |= DAVINCI_MCBSP_SPCR_RRST;
 194                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 195         }
 196
 197
 198         /* Start frame sync */
 199         spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 200         spcr |= DAVINCI_MCBSP_SPCR_FRST;
 201         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 202 }
 203
 204 static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback)
 205 {
 206         u32 spcr;
 207
 208         /* Reset transmitter/receiver and sample rate/frame sync generators */
 209         spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 210         spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST);
 211         spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST;
 212         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 213         toggle_clock(dev, playback);
 214 }
 215
 216 static int davinci_i2s_startup(struct snd_pcm_substream *substream,
 217                                struct snd_soc_dai *dai)
 218 {
 219         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 220         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 221         struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
 222
 223         cpu_dai->dma_data = dev->dma_params[substream->stream];
 224
 225         return 0;
 226 }
 227
 228 #define DEFAULT_BITPERSAMPLE    16
 229
 230 static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 231                                    unsigned int fmt)
 232 {
 233         struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
 234         unsigned int pcr;
 235         unsigned int srgr;
 236         unsigned int rcr;
 237         unsigned int xcr;
 238         srgr = DAVINCI_MCBSP_SRGR_FSGM |
 239                 DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
 240                 DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
 241
 242         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 243         case SND_SOC_DAIFMT_CBS_CFS:
 244                 /* cpu is master */
 245                 pcr = DAVINCI_MCBSP_PCR_FSXM |
 246                         DAVINCI_MCBSP_PCR_FSRM |
 247                         DAVINCI_MCBSP_PCR_CLKXM |
 248                         DAVINCI_MCBSP_PCR_CLKRM;
 249                 break;
 250         case SND_SOC_DAIFMT_CBM_CFS:
 251                 /* McBSP CLKR pin is the input for the Sample Rate Generator.
 252                  * McBSP FSR and FSX are driven by the Sample Rate Generator. */
 253                 pcr = DAVINCI_MCBSP_PCR_SCLKME |
 254                         DAVINCI_MCBSP_PCR_FSXM |
 255                         DAVINCI_MCBSP_PCR_FSRM;
 256                 break;
 257         case SND_SOC_DAIFMT_CBM_CFM:
 258                 /* codec is master */
 259                 pcr = 0;
 260                 break;
 261         default:
 262                 printk(KERN_ERR "%s:bad master\n", __func__);
 263                 return -EINVAL;
 264         }
 265
 266         rcr = DAVINCI_MCBSP_RCR_RFRLEN1(1);
 267         xcr = DAVINCI_MCBSP_XCR_XFIG | DAVINCI_MCBSP_XCR_XFRLEN1(1);
 268         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 269         case SND_SOC_DAIFMT_DSP_B:
 270                 break;
 271         case SND_SOC_DAIFMT_I2S:
 272                 /* Davinci doesn't support TRUE I2S, but some codecs will have
 273                  * the left and right channels contiguous. This allows
 274                  * dsp_a mode to be used with an inverted normal frame clk.
 275                  * If your codec is master and does not have contiguous
 276                  * channels, then you will have sound on only one channel.
 277                  * Try using a different mode, or codec as slave.
 278                  *
 279                  * The TLV320AIC33 is an example of a codec where this works.
 280                  * It has a variable bit clock frequency allowing it to have
 281                  * valid data on every bit clock.
 282                  *
 283                  * The TLV320AIC23 is an example of a codec where this does not
 284                  * work. It has a fixed bit clock frequency with progressively
 285                  * more empty bit clock slots between channels as the sample
 286                  * rate is lowered.
 287                  */
 288                 fmt ^= SND_SOC_DAIFMT_NB_IF;
 289         case SND_SOC_DAIFMT_DSP_A:
 290                 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1);
 291                 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
 292                 break;
 293         default:
 294                 printk(KERN_ERR "%s:bad format\n", __func__);
 295                 return -EINVAL;
 296         }
 297
 298         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 299         case SND_SOC_DAIFMT_NB_NF:
 300                 /* CLKRP Receive clock polarity,
 301                  *      1 - sampled on rising edge of CLKR
 302                  *      valid on rising edge
 303                  * CLKXP Transmit clock polarity,
 304                  *      1 - clocked on falling edge of CLKX
 305                  *      valid on rising edge
 306                  * FSRP  Receive frame sync pol, 0 - active high
 307                  * FSXP  Transmit frame sync pol, 0 - active high
 308                  */
 309                 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP);
 310                 break;
 311         case SND_SOC_DAIFMT_IB_IF:
 312                 /* CLKRP Receive clock polarity,
 313                  *      0 - sampled on falling edge of CLKR
 314                  *      valid on falling edge
 315                  * CLKXP Transmit clock polarity,
 316                  *      0 - clocked on rising edge of CLKX
 317                  *      valid on falling edge
 318                  * FSRP  Receive frame sync pol, 1 - active low
 319                  * FSXP  Transmit frame sync pol, 1 - active low
 320                  */
 321                 pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
 322                 break;
 323         case SND_SOC_DAIFMT_NB_IF:
 324                 /* CLKRP Receive clock polarity,
 325                  *      1 - sampled on rising edge of CLKR
 326                  *      valid on rising edge
 327                  * CLKXP Transmit clock polarity,
 328                  *      1 - clocked on falling edge of CLKX
 329                  *      valid on rising edge
 330                  * FSRP  Receive frame sync pol, 1 - active low
 331                  * FSXP  Transmit frame sync pol, 1 - active low
 332                  */
 333                 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP |
 334                         DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
 335                 break;
 336         case SND_SOC_DAIFMT_IB_NF:
 337                 /* CLKRP Receive clock polarity,
 338                  *      0 - sampled on falling edge of CLKR
 339                  *      valid on falling edge
 340                  * CLKXP Transmit clock polarity,
 341                  *      0 - clocked on rising edge of CLKX
 342                  *      valid on falling edge
 343                  * FSRP  Receive frame sync pol, 0 - active high
 344                  * FSXP  Transmit frame sync pol, 0 - active high
 345                  */
 346                 break;
 347         default:
 348                 return -EINVAL;
 349         }
 350         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
 351         dev->pcr = pcr;
 352         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
 353         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
 354         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
 355         return 0;
 356 }
 357
 358 static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
 359                                  struct snd_pcm_hw_params *params,
 360                                  struct snd_soc_dai *dai)
 361 {
 362         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 363         struct davinci_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data;
 364         struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
 365         struct snd_interval *i = NULL;
 366         int mcbsp_word_length;
 367         unsigned int rcr, xcr, srgr;
 368         u32 spcr;
 369
 370         /* general line settings */
 371         spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 372         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 373                 spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
 374                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 375         } else {
 376                 spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
 377                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 378         }
 379
 380         i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
 381         srgr = DAVINCI_MCBSP_SRGR_FSGM;
 382         srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
 383
 384         i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
 385         srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
 386         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
 387
 388         /* Determine xfer data type */
 389         switch (params_format(params)) {
 390         case SNDRV_PCM_FORMAT_S8:
 391                 dma_params->data_type = 1;
 392                 mcbsp_word_length = DAVINCI_MCBSP_WORD_8;
 393                 break;
 394         case SNDRV_PCM_FORMAT_S16_LE:
 395                 dma_params->data_type = 2;
 396                 mcbsp_word_length = DAVINCI_MCBSP_WORD_16;
 397                 break;
 398         case SNDRV_PCM_FORMAT_S32_LE:
 399                 dma_params->data_type = 4;
 400                 mcbsp_word_length = DAVINCI_MCBSP_WORD_32;
 401                 break;
 402         default:
 403                 printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
 404                 return -EINVAL;
 405         }
 406
 407         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 408                 rcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_RCR_REG);
 409                 rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
 410                                DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
 411                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
 412
 413         } else {
 414                 xcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_XCR_REG);
 415                 xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
 416                                 DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
 417                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
 418
 419         }
 420         return 0;
 421 }
 422
 423 static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 424                                struct snd_soc_dai *dai)
 425 {
 426         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 427         struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
 428         int ret = 0;
 429         int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 430
 431         switch (cmd) {
 432         case SNDRV_PCM_TRIGGER_START:
 433         case SNDRV_PCM_TRIGGER_RESUME:
 434         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 435                 davinci_mcbsp_start(dev, substream);
 436                 break;
 437         case SNDRV_PCM_TRIGGER_STOP:
 438         case SNDRV_PCM_TRIGGER_SUSPEND:
 439         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 440                 davinci_mcbsp_stop(dev, playback);
 441                 break;
 442         default:
 443                 ret = -EINVAL;
 444         }
 445
 446         return ret;
 447 }
 448
 449 static int davinci_i2s_probe(struct platform_device *pdev,
 450                              struct snd_soc_dai *dai)
 451 {
 452         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
 453         struct snd_soc_card *card = socdev->card;
 454         struct snd_soc_dai *cpu_dai = card->dai_link->cpu_dai;
 455         struct davinci_mcbsp_dev *dev;
 456         struct resource *mem, *ioarea;
 457         struct evm_snd_platform_data *pdata;
 458         int ret;
 459
 460         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 461         if (!mem) {
 462                 dev_err(&pdev->dev, "no mem resource?\n");
 463                 return -ENODEV;
 464         }
 465
 466         ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
 467                                     pdev->name);
 468         if (!ioarea) {
 469                 dev_err(&pdev->dev, "McBSP region already claimed\n");
 470                 return -EBUSY;
 471         }
 472
 473         dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
 474         if (!dev) {
 475                 ret = -ENOMEM;
 476                 goto err_release_region;
 477         }
 478
 479         cpu_dai->private_data = dev;
 480
 481         dev->clk = clk_get(&pdev->dev, NULL);
 482         if (IS_ERR(dev->clk)) {
 483                 ret = -ENODEV;
 484                 goto err_free_mem;
 485         }
 486         clk_enable(dev->clk);
 487
 488         dev->base = (void __iomem *)IO_ADDRESS(mem->start);
 489         pdata = pdev->dev.platform_data;
 490
 491         dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &davinci_i2s_pcm_out;
 492         dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->channel = pdata->tx_dma_ch;
 493         dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->dma_addr =
 494             (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);
 495
 496         dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &davinci_i2s_pcm_in;
 497         dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->channel = pdata->rx_dma_ch;
 498         dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->dma_addr =
 499             (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);
 500
 501         return 0;
 502
 503 err_free_mem:
 504         kfree(dev);
 505 err_release_region:
 506         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 507
 508         return ret;
 509 }
 510
 511 static void davinci_i2s_remove(struct platform_device *pdev,
 512                                struct snd_soc_dai *dai)
 513 {
 514         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
 515         struct snd_soc_card *card = socdev->card;
 516         struct snd_soc_dai *cpu_dai = card->dai_link->cpu_dai;
 517         struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
 518         struct resource *mem;
 519
 520         clk_disable(dev->clk);
 521         clk_put(dev->clk);
 522         dev->clk = NULL;
 523
 524         kfree(dev);
 525
 526         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 527         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 528 }
 529
 530 #define DAVINCI_I2S_RATES       SNDRV_PCM_RATE_8000_96000
 531
 532 static struct snd_soc_dai_ops davinci_i2s_dai_ops = {
 533         .startup        = davinci_i2s_startup,
 534         .trigger        = davinci_i2s_trigger,
 535         .hw_params      = davinci_i2s_hw_params,
 536         .set_fmt        = davinci_i2s_set_dai_fmt,
 537 };
 538
 539 struct snd_soc_dai davinci_i2s_dai = {
 540         .name = "davinci-i2s",
 541         .id = 0,
 542         .probe = davinci_i2s_probe,
 543         .remove = davinci_i2s_remove,
 544         .playback = {
 545                 .channels_min = 2,
 546                 .channels_max = 2,
 547                 .rates = DAVINCI_I2S_RATES,
 548                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 549         .capture = {
 550                 .channels_min = 2,
 551                 .channels_max = 2,
 552                 .rates = DAVINCI_I2S_RATES,
 553                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 554         .ops = &davinci_i2s_dai_ops,
 555 };
 556 EXPORT_SYMBOL_GPL(davinci_i2s_dai);
 557
 558 static int __init davinci_i2s_init(void)
 559 {
 560         return snd_soc_register_dai(&davinci_i2s_dai);
 561 }
 562 module_init(davinci_i2s_init);
 563
 564 static void __exit davinci_i2s_exit(void)
 565 {
 566         snd_soc_unregister_dai(&davinci_i2s_dai);
 567 }
 568 module_exit(davinci_i2s_exit);
 569
 570 MODULE_AUTHOR("Vladimir Barinov");
 571 MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
 572 MODULE_LICENSE("GPL");