sound/soc/davinci/davinci-i2s.c

   1 /*
   2  * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
   3  *
   4  * Author:      Vladimir Barinov, <vbarinov@embeddedalley.com>
   5  * Copyright:   (C) 2007 MontaVista Software, Inc., <source@mvista.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/device.h>
  15 #include <linux/delay.h>
  16 #include <linux/io.h>
  17 #include <linux/clk.h>
  18
  19 #include <sound/core.h>
  20 #include <sound/pcm.h>
  21 #include <sound/pcm_params.h>
  22 #include <sound/initval.h>
  23 #include <sound/soc.h>
  24
  25 #include <mach/asp.h>
  26
  27 #include "davinci-pcm.h"
  28
  29
  30 /*
  31  * NOTE:  terminology here is confusing.
  32  *
  33  *  - This driver supports the "Audio Serial Port" (ASP),
  34  *    found on dm6446, dm355, and other DaVinci chips.
  35  *
  36  *  - But it labels it a "Multi-channel Buffered Serial Port"
  37  *    (McBSP) as on older chips like the dm642 ... which was
  38  *    backward-compatible, possibly explaining that confusion.
  39  *
  40  *  - OMAP chips have a controller called McBSP, which is
  41  *    incompatible with the DaVinci flavor of McBSP.
  42  *
  43  *  - Newer DaVinci chips have a controller called McASP,
  44  *    incompatible with ASP and with either McBSP.
  45  *
  46  * In short:  this uses ASP to implement I2S, not McBSP.
  47  * And it won't be the only DaVinci implemention of I2S.
  48  */
  49 #define DAVINCI_MCBSP_DRR_REG   0x00
  50 #define DAVINCI_MCBSP_DXR_REG   0x04
  51 #define DAVINCI_MCBSP_SPCR_REG  0x08
  52 #define DAVINCI_MCBSP_RCR_REG   0x0c
  53 #define DAVINCI_MCBSP_XCR_REG   0x10
  54 #define DAVINCI_MCBSP_SRGR_REG  0x14
  55 #define DAVINCI_MCBSP_PCR_REG   0x24
  56
  57 #define DAVINCI_MCBSP_SPCR_RRST         (1 << 0)
  58 #define DAVINCI_MCBSP_SPCR_RINTM(v)     ((v) << 4)
  59 #define DAVINCI_MCBSP_SPCR_XRST         (1 << 16)
  60 #define DAVINCI_MCBSP_SPCR_XINTM(v)     ((v) << 20)
  61 #define DAVINCI_MCBSP_SPCR_GRST         (1 << 22)
  62 #define DAVINCI_MCBSP_SPCR_FRST         (1 << 23)
  63 #define DAVINCI_MCBSP_SPCR_FREE         (1 << 25)
  64
  65 #define DAVINCI_MCBSP_RCR_RWDLEN1(v)    ((v) << 5)
  66 #define DAVINCI_MCBSP_RCR_RFRLEN1(v)    ((v) << 8)
  67 #define DAVINCI_MCBSP_RCR_RDATDLY(v)    ((v) << 16)
  68 #define DAVINCI_MCBSP_RCR_RFIG          (1 << 18)
  69 #define DAVINCI_MCBSP_RCR_RWDLEN2(v)    ((v) << 21)
  70
  71 #define DAVINCI_MCBSP_XCR_XWDLEN1(v)    ((v) << 5)
  72 #define DAVINCI_MCBSP_XCR_XFRLEN1(v)    ((v) << 8)
  73 #define DAVINCI_MCBSP_XCR_XDATDLY(v)    ((v) << 16)
  74 #define DAVINCI_MCBSP_XCR_XFIG          (1 << 18)
  75 #define DAVINCI_MCBSP_XCR_XWDLEN2(v)    ((v) << 21)
  76
  77 #define DAVINCI_MCBSP_SRGR_FWID(v)      ((v) << 8)
  78 #define DAVINCI_MCBSP_SRGR_FPER(v)      ((v) << 16)
  79 #define DAVINCI_MCBSP_SRGR_FSGM         (1 << 28)
  80
  81 #define DAVINCI_MCBSP_PCR_CLKRP         (1 << 0)
  82 #define DAVINCI_MCBSP_PCR_CLKXP         (1 << 1)
  83 #define DAVINCI_MCBSP_PCR_FSRP          (1 << 2)
  84 #define DAVINCI_MCBSP_PCR_FSXP          (1 << 3)
  85 #define DAVINCI_MCBSP_PCR_SCLKME        (1 << 7)
  86 #define DAVINCI_MCBSP_PCR_CLKRM         (1 << 8)
  87 #define DAVINCI_MCBSP_PCR_CLKXM         (1 << 9)
  88 #define DAVINCI_MCBSP_PCR_FSRM          (1 << 10)
  89 #define DAVINCI_MCBSP_PCR_FSXM          (1 << 11)
  90
  91 enum {
  92         DAVINCI_MCBSP_WORD_8 = 0,
  93         DAVINCI_MCBSP_WORD_12,
  94         DAVINCI_MCBSP_WORD_16,
  95         DAVINCI_MCBSP_WORD_20,
  96         DAVINCI_MCBSP_WORD_24,
  97         DAVINCI_MCBSP_WORD_32,
  98 };
  99
 100 static struct davinci_pcm_dma_params davinci_i2s_pcm_out = {
 101         .name = "I2S PCM Stereo out",
 102 };
 103
 104 static struct davinci_pcm_dma_params davinci_i2s_pcm_in = {
 105         .name = "I2S PCM Stereo in",
 106 };
 107
 108 struct davinci_mcbsp_dev {
 109         void __iomem                    *base;
 110 #define MOD_DSP_A       0
 111 #define MOD_DSP_B       1
 112         int                             mode;
 113         u32                             pcr;
 114         struct clk                      *clk;
 115         struct davinci_pcm_dma_params   *dma_params[2];
 116 };
 117
 118 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
 119                                            int reg, u32 val)
 120 {
 121         __raw_writel(val, dev->base + reg);
 122 }
 123
 124 static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
 125 {
 126         return __raw_readl(dev->base + reg);
 127 }
 128
 129 static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback)
 130 {
 131         u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP;
 132         /* The clock needs to toggle to complete reset.
 133          * So, fake it by toggling the clk polarity.
 134          */
 135         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m);
 136         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr);
 137 }
 138
 139 static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev,
 140                 struct snd_pcm_substream *substream)
 141 {
 142         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 143         struct snd_soc_device *socdev = rtd->socdev;
 144         struct snd_soc_platform *platform = socdev->card->platform;
 145         int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 146         u32 spcr;
 147         u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
 148         spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 149         if (spcr & mask) {
 150                 /* start off disabled */
 151                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
 152                                 spcr & ~mask);
 153                 toggle_clock(dev, playback);
 154         }
 155         if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM |
 156                         DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) {
 157                 /* Start the sample generator */
 158                 spcr |= DAVINCI_MCBSP_SPCR_GRST;
 159                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 160         }
 161
 162         if (playback) {
 163                 /* Stop the DMA to avoid data loss */
 164                 /* while the transmitter is out of reset to handle XSYNCERR */
 165                 if (platform->pcm_ops->trigger) {
 166                         int ret = platform->pcm_ops->trigger(substream,
 167                                 SNDRV_PCM_TRIGGER_STOP);
 168                         if (ret < 0)
 169                                 printk(KERN_DEBUG "Playback DMA stop failed\n");
 170                 }
 171
 172                 /* Enable the transmitter */
 173                 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 174                 spcr |= DAVINCI_MCBSP_SPCR_XRST;
 175                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 176
 177                 /* wait for any unexpected frame sync error to occur */
 178                 udelay(100);
 179
 180                 /* Disable the transmitter to clear any outstanding XSYNCERR */
 181                 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 182                 spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
 183                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 184                 toggle_clock(dev, playback);
 185
 186                 /* Restart the DMA */
 187                 if (platform->pcm_ops->trigger) {
 188                         int ret = platform->pcm_ops->trigger(substream,
 189                                 SNDRV_PCM_TRIGGER_START);
 190                         if (ret < 0)
 191                                 printk(KERN_DEBUG "Playback DMA start failed\n");
 192                 }
 193         }
 194
 195         /* Enable transmitter or receiver */
 196         spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 197         spcr |= mask;
 198
 199         if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) {
 200                 /* Start frame sync */
 201                 spcr |= DAVINCI_MCBSP_SPCR_FRST;
 202         }
 203         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 204 }
 205
 206 static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback)
 207 {
 208         u32 spcr;
 209
 210         /* Reset transmitter/receiver and sample rate/frame sync generators */
 211         spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 212         spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST);
 213         spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST;
 214         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 215         toggle_clock(dev, playback);
 216 }
 217
 218 static int davinci_i2s_startup(struct snd_pcm_substream *substream,
 219                                struct snd_soc_dai *cpu_dai)
 220 {
 221         struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
 222         cpu_dai->dma_data = dev->dma_params[substream->stream];
 223         return 0;
 224 }
 225
 226 #define DEFAULT_BITPERSAMPLE    16
 227
 228 static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 229                                    unsigned int fmt)
 230 {
 231         struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
 232         unsigned int pcr;
 233         unsigned int srgr;
 234         srgr = DAVINCI_MCBSP_SRGR_FSGM |
 235                 DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
 236                 DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
 237
 238         /* set master/slave audio interface */
 239         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 240         case SND_SOC_DAIFMT_CBS_CFS:
 241                 /* cpu is master */
 242                 pcr = DAVINCI_MCBSP_PCR_FSXM |
 243                         DAVINCI_MCBSP_PCR_FSRM |
 244                         DAVINCI_MCBSP_PCR_CLKXM |
 245                         DAVINCI_MCBSP_PCR_CLKRM;
 246                 break;
 247         case SND_SOC_DAIFMT_CBM_CFS:
 248                 /* McBSP CLKR pin is the input for the Sample Rate Generator.
 249                  * McBSP FSR and FSX are driven by the Sample Rate Generator. */
 250                 pcr = DAVINCI_MCBSP_PCR_SCLKME |
 251                         DAVINCI_MCBSP_PCR_FSXM |
 252                         DAVINCI_MCBSP_PCR_FSRM;
 253                 break;
 254         case SND_SOC_DAIFMT_CBM_CFM:
 255                 /* codec is master */
 256                 pcr = 0;
 257                 break;
 258         default:
 259                 printk(KERN_ERR "%s:bad master\n", __func__);
 260                 return -EINVAL;
 261         }
 262
 263         /* interface format */
 264         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 265         case SND_SOC_DAIFMT_I2S:
 266                 /* Davinci doesn't support TRUE I2S, but some codecs will have
 267                  * the left and right channels contiguous. This allows
 268                  * dsp_a mode to be used with an inverted normal frame clk.
 269                  * If your codec is master and does not have contiguous
 270                  * channels, then you will have sound on only one channel.
 271                  * Try using a different mode, or codec as slave.
 272                  *
 273                  * The TLV320AIC33 is an example of a codec where this works.
 274                  * It has a variable bit clock frequency allowing it to have
 275                  * valid data on every bit clock.
 276                  *
 277                  * The TLV320AIC23 is an example of a codec where this does not
 278                  * work. It has a fixed bit clock frequency with progressively
 279                  * more empty bit clock slots between channels as the sample
 280                  * rate is lowered.
 281                  */
 282                 fmt ^= SND_SOC_DAIFMT_NB_IF;
 283         case SND_SOC_DAIFMT_DSP_A:
 284                 dev->mode = MOD_DSP_A;
 285                 break;
 286         case SND_SOC_DAIFMT_DSP_B:
 287                 dev->mode = MOD_DSP_B;
 288                 break;
 289         default:
 290                 printk(KERN_ERR "%s:bad format\n", __func__);
 291                 return -EINVAL;
 292         }
 293
 294         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 295         case SND_SOC_DAIFMT_NB_NF:
 296                 /* CLKRP Receive clock polarity,
 297                  *      1 - sampled on rising edge of CLKR
 298                  *      valid on rising edge
 299                  * CLKXP Transmit clock polarity,
 300                  *      1 - clocked on falling edge of CLKX
 301                  *      valid on rising edge
 302                  * FSRP  Receive frame sync pol, 0 - active high
 303                  * FSXP  Transmit frame sync pol, 0 - active high
 304                  */
 305                 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP);
 306                 break;
 307         case SND_SOC_DAIFMT_IB_IF:
 308                 /* CLKRP Receive clock polarity,
 309                  *      0 - sampled on falling edge of CLKR
 310                  *      valid on falling edge
 311                  * CLKXP Transmit clock polarity,
 312                  *      0 - clocked on rising edge of CLKX
 313                  *      valid on falling edge
 314                  * FSRP  Receive frame sync pol, 1 - active low
 315                  * FSXP  Transmit frame sync pol, 1 - active low
 316                  */
 317                 pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
 318                 break;
 319         case SND_SOC_DAIFMT_NB_IF:
 320                 /* CLKRP Receive clock polarity,
 321                  *      1 - sampled on rising edge of CLKR
 322                  *      valid on rising edge
 323                  * CLKXP Transmit clock polarity,
 324                  *      1 - clocked on falling edge of CLKX
 325                  *      valid on rising edge
 326                  * FSRP  Receive frame sync pol, 1 - active low
 327                  * FSXP  Transmit frame sync pol, 1 - active low
 328                  */
 329                 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP |
 330                         DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
 331                 break;
 332         case SND_SOC_DAIFMT_IB_NF:
 333                 /* CLKRP Receive clock polarity,
 334                  *      0 - sampled on falling edge of CLKR
 335                  *      valid on falling edge
 336                  * CLKXP Transmit clock polarity,
 337                  *      0 - clocked on rising edge of CLKX
 338                  *      valid on falling edge
 339                  * FSRP  Receive frame sync pol, 0 - active high
 340                  * FSXP  Transmit frame sync pol, 0 - active high
 341                  */
 342                 break;
 343         default:
 344                 return -EINVAL;
 345         }
 346         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
 347         dev->pcr = pcr;
 348         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
 349         return 0;
 350 }
 351
 352 static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
 353                                  struct snd_pcm_hw_params *params,
 354                                  struct snd_soc_dai *dai)
 355 {
 356         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 357         struct davinci_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data;
 358         struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
 359         struct snd_interval *i = NULL;
 360         int mcbsp_word_length;
 361         unsigned int rcr, xcr, srgr;
 362         u32 spcr;
 363
 364         /* general line settings */
 365         spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 366         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 367                 spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
 368                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 369         } else {
 370                 spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
 371                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 372         }
 373
 374         i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
 375         srgr = DAVINCI_MCBSP_SRGR_FSGM;
 376         srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
 377
 378         i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
 379         srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
 380         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
 381
 382         rcr = DAVINCI_MCBSP_RCR_RFIG;
 383         xcr = DAVINCI_MCBSP_XCR_XFIG;
 384         if (dev->mode == MOD_DSP_B) {
 385                 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(0);
 386                 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(0);
 387         } else {
 388                 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1);
 389                 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
 390         }
 391         /* Determine xfer data type */
 392         switch (params_format(params)) {
 393         case SNDRV_PCM_FORMAT_S8:
 394                 dma_params->data_type = 1;
 395                 mcbsp_word_length = DAVINCI_MCBSP_WORD_8;
 396                 break;
 397         case SNDRV_PCM_FORMAT_S16_LE:
 398                 dma_params->data_type = 2;
 399                 mcbsp_word_length = DAVINCI_MCBSP_WORD_16;
 400                 break;
 401         case SNDRV_PCM_FORMAT_S32_LE:
 402                 dma_params->data_type = 4;
 403                 mcbsp_word_length = DAVINCI_MCBSP_WORD_32;
 404                 break;
 405         default:
 406                 printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
 407                 return -EINVAL;
 408         }
 409
 410         rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(1);
 411         xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(1);
 412
 413         rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
 414                 DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
 415         xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
 416                 DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
 417
 418         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 419                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
 420         else
 421                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
 422         return 0;
 423 }
 424
 425 static int davinci_i2s_prepare(struct snd_pcm_substream *substream,
 426                 struct snd_soc_dai *dai)
 427 {
 428         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 429         struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
 430         int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 431         davinci_mcbsp_stop(dev, playback);
 432         if ((dev->pcr & DAVINCI_MCBSP_PCR_FSXM) == 0) {
 433                 /* codec is master */
 434                 davinci_mcbsp_start(dev, substream);
 435         }
 436         return 0;
 437 }
 438
 439 static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 440                                struct snd_soc_dai *dai)
 441 {
 442         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 443         struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
 444         int ret = 0;
 445         int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 446         if ((dev->pcr & DAVINCI_MCBSP_PCR_FSXM) == 0)
 447                 return 0;       /* return if codec is master */
 448
 449         switch (cmd) {
 450         case SNDRV_PCM_TRIGGER_START:
 451         case SNDRV_PCM_TRIGGER_RESUME:
 452         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 453                 davinci_mcbsp_start(dev, substream);
 454                 break;
 455         case SNDRV_PCM_TRIGGER_STOP:
 456         case SNDRV_PCM_TRIGGER_SUSPEND:
 457         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 458                 davinci_mcbsp_stop(dev, playback);
 459                 break;
 460         default:
 461                 ret = -EINVAL;
 462         }
 463         return ret;
 464 }
 465
 466 static void davinci_i2s_shutdown(struct snd_pcm_substream *substream,
 467                 struct snd_soc_dai *dai)
 468 {
 469         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 470         struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
 471         int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 472         davinci_mcbsp_stop(dev, playback);
 473 }
 474
 475 #define DAVINCI_I2S_RATES       SNDRV_PCM_RATE_8000_96000
 476
 477 static struct snd_soc_dai_ops davinci_i2s_dai_ops = {
 478         .startup        = davinci_i2s_startup,
 479         .shutdown       = davinci_i2s_shutdown,
 480         .prepare        = davinci_i2s_prepare,
 481         .trigger        = davinci_i2s_trigger,
 482         .hw_params      = davinci_i2s_hw_params,
 483         .set_fmt        = davinci_i2s_set_dai_fmt,
 484
 485 };
 486
 487 struct snd_soc_dai davinci_i2s_dai = {
 488         .name = "davinci-i2s",
 489         .id = 0,
 490         .playback = {
 491                 .channels_min = 2,
 492                 .channels_max = 2,
 493                 .rates = DAVINCI_I2S_RATES,
 494                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 495         .capture = {
 496                 .channels_min = 2,
 497                 .channels_max = 2,
 498                 .rates = DAVINCI_I2S_RATES,
 499                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 500         .ops = &davinci_i2s_dai_ops,
 501
 502 };
 503 EXPORT_SYMBOL_GPL(davinci_i2s_dai);
 504
 505 static int davinci_i2s_probe(struct platform_device *pdev)
 506 {
 507         struct snd_platform_data *pdata = pdev->dev.platform_data;
 508         struct davinci_mcbsp_dev *dev;
 509         struct resource *mem, *ioarea, *res;
 510         int ret;
 511
 512         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 513         if (!mem) {
 514                 dev_err(&pdev->dev, "no mem resource?\n");
 515                 return -ENODEV;
 516         }
 517
 518         ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
 519                                     pdev->name);
 520         if (!ioarea) {
 521                 dev_err(&pdev->dev, "McBSP region already claimed\n");
 522                 return -EBUSY;
 523         }
 524
 525         dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
 526         if (!dev) {
 527                 ret = -ENOMEM;
 528                 goto err_release_region;
 529         }
 530
 531         dev->clk = clk_get(&pdev->dev, pdata->clk_name);
 532         if (IS_ERR(dev->clk)) {
 533                 ret = -ENODEV;
 534                 goto err_free_mem;
 535         }
 536         clk_enable(dev->clk);
 537
 538         dev->base = (void __iomem *)IO_ADDRESS(mem->start);
 539
 540         dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &davinci_i2s_pcm_out;
 541         dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->dma_addr =
 542             (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);
 543
 544         dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &davinci_i2s_pcm_in;
 545         dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->dma_addr =
 546             (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);
 547
 548         /* first TX, then RX */
 549         res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
 550         if (!res) {
 551                 dev_err(&pdev->dev, "no DMA resource\n");
 552                 ret = -ENXIO;
 553                 goto err_free_mem;
 554         }
 555         dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->channel = res->start;
 556
 557         res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
 558         if (!res) {
 559                 dev_err(&pdev->dev, "no DMA resource\n");
 560                 ret = -ENXIO;
 561                 goto err_free_mem;
 562         }
 563         dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->channel = res->start;
 564
 565         davinci_i2s_dai.private_data = dev;
 566         ret = snd_soc_register_dai(&davinci_i2s_dai);
 567         if (ret != 0)
 568                 goto err_free_mem;
 569
 570         return 0;
 571
 572 err_free_mem:
 573         kfree(dev);
 574 err_release_region:
 575         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 576
 577         return ret;
 578 }
 579
 580 static int davinci_i2s_remove(struct platform_device *pdev)
 581 {
 582         struct davinci_mcbsp_dev *dev = davinci_i2s_dai.private_data;
 583         struct resource *mem;
 584
 585         snd_soc_unregister_dai(&davinci_i2s_dai);
 586         clk_disable(dev->clk);
 587         clk_put(dev->clk);
 588         dev->clk = NULL;
 589         kfree(dev);
 590         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 591         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 592
 593         return 0;
 594 }
 595
 596 static struct platform_driver davinci_mcbsp_driver = {
 597         .probe          = davinci_i2s_probe,
 598         .remove         = davinci_i2s_remove,
 599         .driver         = {
 600                 .name   = "davinci-asp",
 601                 .owner  = THIS_MODULE,
 602         },
 603 };
 604
 605 static int __init davinci_i2s_init(void)
 606 {
 607         return platform_driver_register(&davinci_mcbsp_driver);
 608 }
 609 module_init(davinci_i2s_init);
 610
 611 static void __exit davinci_i2s_exit(void)
 612 {
 613         platform_driver_unregister(&davinci_mcbsp_driver);
 614 }
 615 module_exit(davinci_i2s_exit);
 616
 617 MODULE_AUTHOR("Vladimir Barinov");
 618 MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
 619 MODULE_LICENSE("GPL");