sound/soc/davinci/davinci-i2s.c

   1 /*
   2  * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
   3  *
   4  * Author:      Vladimir Barinov, <vbarinov@ru.mvista.com>
   5  * Copyright:   (C) 2007 MontaVista Software, Inc., <source@mvista.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/device.h>
  15 #include <linux/delay.h>
  16 #include <linux/io.h>
  17 #include <linux/clk.h>
  18
  19 #include <sound/core.h>
  20 #include <sound/pcm.h>
  21 #include <sound/pcm_params.h>
  22 #include <sound/initval.h>
  23 #include <sound/soc.h>
  24
  25 #include "davinci-pcm.h"
  26
  27 #define DAVINCI_MCBSP_DRR_REG   0x00
  28 #define DAVINCI_MCBSP_DXR_REG   0x04
  29 #define DAVINCI_MCBSP_SPCR_REG  0x08
  30 #define DAVINCI_MCBSP_RCR_REG   0x0c
  31 #define DAVINCI_MCBSP_XCR_REG   0x10
  32 #define DAVINCI_MCBSP_SRGR_REG  0x14
  33 #define DAVINCI_MCBSP_PCR_REG   0x24
  34
  35 #define DAVINCI_MCBSP_SPCR_RRST         (1 << 0)
  36 #define DAVINCI_MCBSP_SPCR_RINTM(v)     ((v) << 4)
  37 #define DAVINCI_MCBSP_SPCR_XRST         (1 << 16)
  38 #define DAVINCI_MCBSP_SPCR_XINTM(v)     ((v) << 20)
  39 #define DAVINCI_MCBSP_SPCR_GRST         (1 << 22)
  40 #define DAVINCI_MCBSP_SPCR_FRST         (1 << 23)
  41 #define DAVINCI_MCBSP_SPCR_FREE         (1 << 25)
  42
  43 #define DAVINCI_MCBSP_RCR_RWDLEN1(v)    ((v) << 5)
  44 #define DAVINCI_MCBSP_RCR_RFRLEN1(v)    ((v) << 8)
  45 #define DAVINCI_MCBSP_RCR_RDATDLY(v)    ((v) << 16)
  46 #define DAVINCI_MCBSP_RCR_RWDLEN2(v)    ((v) << 21)
  47
  48 #define DAVINCI_MCBSP_XCR_XWDLEN1(v)    ((v) << 5)
  49 #define DAVINCI_MCBSP_XCR_XFRLEN1(v)    ((v) << 8)
  50 #define DAVINCI_MCBSP_XCR_XDATDLY(v)    ((v) << 16)
  51 #define DAVINCI_MCBSP_XCR_XFIG          (1 << 18)
  52 #define DAVINCI_MCBSP_XCR_XWDLEN2(v)    ((v) << 21)
  53
  54 #define DAVINCI_MCBSP_SRGR_FWID(v)      ((v) << 8)
  55 #define DAVINCI_MCBSP_SRGR_FPER(v)      ((v) << 16)
  56 #define DAVINCI_MCBSP_SRGR_FSGM         (1 << 28)
  57
  58 #define DAVINCI_MCBSP_PCR_CLKRP         (1 << 0)
  59 #define DAVINCI_MCBSP_PCR_CLKXP         (1 << 1)
  60 #define DAVINCI_MCBSP_PCR_FSRP          (1 << 2)
  61 #define DAVINCI_MCBSP_PCR_FSXP          (1 << 3)
  62 #define DAVINCI_MCBSP_PCR_CLKRM         (1 << 8)
  63 #define DAVINCI_MCBSP_PCR_CLKXM         (1 << 9)
  64 #define DAVINCI_MCBSP_PCR_FSRM          (1 << 10)
  65 #define DAVINCI_MCBSP_PCR_FSXM          (1 << 11)
  66
  67 #define MOD_REG_BIT(val, mask, set) do { \
  68         if (set) { \
  69                 val |= mask; \
  70         } else { \
  71                 val &= ~mask; \
  72         } \
  73 } while (0)
  74
  75 enum {
  76         DAVINCI_MCBSP_WORD_8 = 0,
  77         DAVINCI_MCBSP_WORD_12,
  78         DAVINCI_MCBSP_WORD_16,
  79         DAVINCI_MCBSP_WORD_20,
  80         DAVINCI_MCBSP_WORD_24,
  81         DAVINCI_MCBSP_WORD_32,
  82 };
  83
  84 static struct davinci_pcm_dma_params davinci_i2s_pcm_out = {
  85         .name = "I2S PCM Stereo out",
  86 };
  87
  88 static struct davinci_pcm_dma_params davinci_i2s_pcm_in = {
  89         .name = "I2S PCM Stereo in",
  90 };
  91
  92 struct davinci_mcbsp_dev {
  93         void __iomem                    *base;
  94         struct clk                      *clk;
  95         struct davinci_pcm_dma_params   *dma_params[2];
  96 };
  97
  98 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
  99                                            int reg, u32 val)
 100 {
 101         __raw_writel(val, dev->base + reg);
 102 }
 103
 104 static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
 105 {
 106         return __raw_readl(dev->base + reg);
 107 }
 108
 109 static void davinci_mcbsp_start(struct snd_pcm_substream *substream)
 110 {
 111         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 112         struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
 113         u32 w;
 114
 115         /* Start the sample generator and enable transmitter/receiver */
 116         w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 117         MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST, 1);
 118         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 119                 MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 1);
 120         else
 121                 MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 1);
 122         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
 123
 124         /* Start frame sync */
 125         w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 126         MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_FRST, 1);
 127         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
 128 }
 129
 130 static void davinci_mcbsp_stop(struct snd_pcm_substream *substream)
 131 {
 132         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 133         struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
 134         u32 w;
 135
 136         /* Reset transmitter/receiver and sample rate/frame sync generators */
 137         w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 138         MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST |
 139                        DAVINCI_MCBSP_SPCR_FRST, 0);
 140         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 141                 MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 0);
 142         else
 143                 MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 0);
 144         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
 145 }
 146
 147 static int davinci_i2s_startup(struct snd_pcm_substream *substream)
 148 {
 149         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 150         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 151         struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
 152
 153         cpu_dai->dma_data = dev->dma_params[substream->stream];
 154
 155         return 0;
 156 }
 157
 158 static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 159                                    unsigned int fmt)
 160 {
 161         struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
 162         u32 w;
 163
 164         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 165         case SND_SOC_DAIFMT_CBS_CFS:
 166                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG,
 167                                         DAVINCI_MCBSP_PCR_FSXM |
 168                                         DAVINCI_MCBSP_PCR_FSRM |
 169                                         DAVINCI_MCBSP_PCR_CLKXM |
 170                                         DAVINCI_MCBSP_PCR_CLKRM);
 171                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG,
 172                                         DAVINCI_MCBSP_SRGR_FSGM);
 173                 break;
 174         case SND_SOC_DAIFMT_CBM_CFM:
 175                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, 0);
 176                 break;
 177         default:
 178                 return -EINVAL;
 179         }
 180
 181         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 182         case SND_SOC_DAIFMT_IB_NF:
 183                 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG);
 184                 MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_CLKXP |
 185                                DAVINCI_MCBSP_PCR_CLKRP, 1);
 186                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w);
 187                 break;
 188         case SND_SOC_DAIFMT_NB_IF:
 189                 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG);
 190                 MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_FSXP |
 191                                DAVINCI_MCBSP_PCR_FSRP, 1);
 192                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w);
 193                 break;
 194         case SND_SOC_DAIFMT_IB_IF:
 195                 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG);
 196                 MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_CLKXP |
 197                                DAVINCI_MCBSP_PCR_CLKRP |
 198                                DAVINCI_MCBSP_PCR_FSXP |
 199                                DAVINCI_MCBSP_PCR_FSRP, 1);
 200                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w);
 201                 break;
 202         case SND_SOC_DAIFMT_NB_NF:
 203                 break;
 204         default:
 205                 return -EINVAL;
 206         }
 207
 208         return 0;
 209 }
 210
 211 static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
 212                                  struct snd_pcm_hw_params *params)
 213 {
 214         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 215         struct davinci_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data;
 216         struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
 217         struct snd_interval *i = NULL;
 218         int mcbsp_word_length;
 219         u32 w;
 220
 221         /* general line settings */
 222         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
 223                                 DAVINCI_MCBSP_SPCR_RINTM(3) |
 224                                 DAVINCI_MCBSP_SPCR_XINTM(3) |
 225                                 DAVINCI_MCBSP_SPCR_FREE);
 226         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG,
 227                                 DAVINCI_MCBSP_RCR_RFRLEN1(1) |
 228                                 DAVINCI_MCBSP_RCR_RDATDLY(1));
 229         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG,
 230                                 DAVINCI_MCBSP_XCR_XFRLEN1(1) |
 231                                 DAVINCI_MCBSP_XCR_XDATDLY(1) |
 232                                 DAVINCI_MCBSP_XCR_XFIG);
 233
 234         i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
 235         w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SRGR_REG);
 236         MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1), 1);
 237         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, w);
 238
 239         i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
 240         w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SRGR_REG);
 241         MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1), 1);
 242         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, w);
 243
 244         /* Determine xfer data type */
 245         switch (params_format(params)) {
 246         case SNDRV_PCM_FORMAT_S8:
 247                 dma_params->data_type = 1;
 248                 mcbsp_word_length = DAVINCI_MCBSP_WORD_8;
 249                 break;
 250         case SNDRV_PCM_FORMAT_S16_LE:
 251                 dma_params->data_type = 2;
 252                 mcbsp_word_length = DAVINCI_MCBSP_WORD_16;
 253                 break;
 254         case SNDRV_PCM_FORMAT_S32_LE:
 255                 dma_params->data_type = 4;
 256                 mcbsp_word_length = DAVINCI_MCBSP_WORD_32;
 257                 break;
 258         default:
 259                 printk(KERN_WARNING "davinci-i2s: unsupported PCM format");
 260                 return -EINVAL;
 261         }
 262
 263         w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_RCR_REG);
 264         MOD_REG_BIT(w, DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
 265                        DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length), 1);
 266         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, w);
 267
 268         w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_XCR_REG);
 269         MOD_REG_BIT(w, DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
 270                        DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length), 1);
 271         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, w);
 272
 273         return 0;
 274 }
 275
 276 static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd)
 277 {
 278         int ret = 0;
 279
 280         switch (cmd) {
 281         case SNDRV_PCM_TRIGGER_START:
 282         case SNDRV_PCM_TRIGGER_RESUME:
 283         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 284                 davinci_mcbsp_start(substream);
 285                 break;
 286         case SNDRV_PCM_TRIGGER_STOP:
 287         case SNDRV_PCM_TRIGGER_SUSPEND:
 288         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 289                 davinci_mcbsp_stop(substream);
 290                 break;
 291         default:
 292                 ret = -EINVAL;
 293         }
 294
 295         return ret;
 296 }
 297
 298 static int davinci_i2s_probe(struct platform_device *pdev,
 299                              struct snd_soc_dai *dai)
 300 {
 301         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
 302         struct snd_soc_machine *machine = socdev->machine;
 303         struct snd_soc_dai *cpu_dai = machine->dai_link[pdev->id].cpu_dai;
 304         struct davinci_mcbsp_dev *dev;
 305         struct resource *mem, *ioarea;
 306         struct evm_snd_platform_data *pdata;
 307         int ret;
 308
 309         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 310         if (!mem) {
 311                 dev_err(&pdev->dev, "no mem resource?\n");
 312                 return -ENODEV;
 313         }
 314
 315         ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
 316                                     pdev->name);
 317         if (!ioarea) {
 318                 dev_err(&pdev->dev, "McBSP region already claimed\n");
 319                 return -EBUSY;
 320         }
 321
 322         dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
 323         if (!dev) {
 324                 ret = -ENOMEM;
 325                 goto err_release_region;
 326         }
 327
 328         cpu_dai->private_data = dev;
 329
 330         dev->clk = clk_get(&pdev->dev, "McBSPCLK");
 331         if (IS_ERR(dev->clk)) {
 332                 ret = -ENODEV;
 333                 goto err_free_mem;
 334         }
 335         clk_enable(dev->clk);
 336
 337         dev->base = (void __iomem *)IO_ADDRESS(mem->start);
 338         pdata = pdev->dev.platform_data;
 339
 340         dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &davinci_i2s_pcm_out;
 341         dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->channel = pdata->tx_dma_ch;
 342         dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->dma_addr =
 343             (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);
 344
 345         dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &davinci_i2s_pcm_in;
 346         dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->channel = pdata->rx_dma_ch;
 347         dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->dma_addr =
 348             (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);
 349
 350         return 0;
 351
 352 err_free_mem:
 353         kfree(dev);
 354 err_release_region:
 355         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 356
 357         return ret;
 358 }
 359
 360 static void davinci_i2s_remove(struct platform_device *pdev,
 361                                struct snd_soc_dai *dai)
 362 {
 363         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
 364         struct snd_soc_machine *machine = socdev->machine;
 365         struct snd_soc_dai *cpu_dai = machine->dai_link[pdev->id].cpu_dai;
 366         struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
 367         struct resource *mem;
 368
 369         clk_disable(dev->clk);
 370         clk_put(dev->clk);
 371         dev->clk = NULL;
 372
 373         kfree(dev);
 374
 375         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 376         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 377 }
 378
 379 #define DAVINCI_I2S_RATES       SNDRV_PCM_RATE_8000_96000
 380
 381 struct snd_soc_dai davinci_i2s_dai = {
 382         .name = "davinci-i2s",
 383         .id = 0,
 384         .type = SND_SOC_DAI_I2S,
 385         .probe = davinci_i2s_probe,
 386         .remove = davinci_i2s_remove,
 387         .playback = {
 388                 .channels_min = 2,
 389                 .channels_max = 2,
 390                 .rates = DAVINCI_I2S_RATES,
 391                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 392         .capture = {
 393                 .channels_min = 2,
 394                 .channels_max = 2,
 395                 .rates = DAVINCI_I2S_RATES,
 396                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 397         .ops = {
 398                 .startup = davinci_i2s_startup,
 399                 .trigger = davinci_i2s_trigger,
 400                 .hw_params = davinci_i2s_hw_params,},
 401         .dai_ops = {
 402                 .set_fmt = davinci_i2s_set_dai_fmt,
 403         },
 404 };
 405 EXPORT_SYMBOL_GPL(davinci_i2s_dai);
 406
 407 MODULE_AUTHOR("Vladimir Barinov");
 408 MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
 409 MODULE_LICENSE("GPL");