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[deliverable/linux.git] / sound / soc / davinci / davinci-mcasp.c
1 /*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/of.h>
27 #include <linux/of_platform.h>
28 #include <linux/of_device.h>
29
30 #include <sound/core.h>
31 #include <sound/pcm.h>
32 #include <sound/pcm_params.h>
33 #include <sound/initval.h>
34 #include <sound/soc.h>
35 #include <sound/dmaengine_pcm.h>
36
37 #include "davinci-pcm.h"
38 #include "davinci-mcasp.h"
39
40 #define MCASP_MAX_AFIFO_DEPTH 64
41
42 struct davinci_mcasp_context {
43 u32 txfmtctl;
44 u32 rxfmtctl;
45 u32 txfmt;
46 u32 rxfmt;
47 u32 aclkxctl;
48 u32 aclkrctl;
49 u32 pdir;
50 };
51
52 struct davinci_mcasp {
53 struct davinci_pcm_dma_params dma_params[2];
54 struct snd_dmaengine_dai_dma_data dma_data[2];
55 void __iomem *base;
56 u32 fifo_base;
57 struct device *dev;
58
59 /* McASP specific data */
60 int tdm_slots;
61 u8 op_mode;
62 u8 num_serializer;
63 u8 *serial_dir;
64 u8 version;
65 u16 bclk_lrclk_ratio;
66 int streams;
67
68 int sysclk_freq;
69 bool bclk_master;
70
71 /* McASP FIFO related */
72 u8 txnumevt;
73 u8 rxnumevt;
74
75 bool dat_port;
76
77 #ifdef CONFIG_PM_SLEEP
78 struct davinci_mcasp_context context;
79 #endif
80 };
81
82 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
83 u32 val)
84 {
85 void __iomem *reg = mcasp->base + offset;
86 __raw_writel(__raw_readl(reg) | val, reg);
87 }
88
89 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
90 u32 val)
91 {
92 void __iomem *reg = mcasp->base + offset;
93 __raw_writel((__raw_readl(reg) & ~(val)), reg);
94 }
95
96 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
97 u32 val, u32 mask)
98 {
99 void __iomem *reg = mcasp->base + offset;
100 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
101 }
102
103 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
104 u32 val)
105 {
106 __raw_writel(val, mcasp->base + offset);
107 }
108
109 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
110 {
111 return (u32)__raw_readl(mcasp->base + offset);
112 }
113
114 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
115 {
116 int i = 0;
117
118 mcasp_set_bits(mcasp, ctl_reg, val);
119
120 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
121 /* loop count is to avoid the lock-up */
122 for (i = 0; i < 1000; i++) {
123 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
124 break;
125 }
126
127 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
128 printk(KERN_ERR "GBLCTL write error\n");
129 }
130
131 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
132 {
133 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
134 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
135
136 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
137 }
138
139 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
140 {
141 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
142 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
143
144 /*
145 * When ASYNC == 0 the transmit and receive sections operate
146 * synchronously from the transmit clock and frame sync. We need to make
147 * sure that the TX signlas are enabled when starting reception.
148 */
149 if (mcasp_is_synchronous(mcasp)) {
150 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
151 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
152 }
153
154 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
155 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
156
157 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
158 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
159 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
160
161 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
162 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
163
164 if (mcasp_is_synchronous(mcasp))
165 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
166 }
167
168 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
169 {
170 u8 offset = 0, i;
171 u32 cnt;
172
173 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
174 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
175 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
176 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
177
178 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
179 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
180 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
181 for (i = 0; i < mcasp->num_serializer; i++) {
182 if (mcasp->serial_dir[i] == TX_MODE) {
183 offset = i;
184 break;
185 }
186 }
187
188 /* wait for TX ready */
189 cnt = 0;
190 while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(offset)) &
191 TXSTATE) && (cnt < 100000))
192 cnt++;
193
194 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
195 }
196
197 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
198 {
199 u32 reg;
200
201 mcasp->streams++;
202
203 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
204 if (mcasp->txnumevt) { /* enable FIFO */
205 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
206 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
207 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
208 }
209 mcasp_start_tx(mcasp);
210 } else {
211 if (mcasp->rxnumevt) { /* enable FIFO */
212 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
213 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
214 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
215 }
216 mcasp_start_rx(mcasp);
217 }
218 }
219
220 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
221 {
222 /*
223 * In synchronous mode stop the TX clocks if no other stream is
224 * running
225 */
226 if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
227 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
228
229 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
230 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
231 }
232
233 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
234 {
235 u32 val = 0;
236
237 /*
238 * In synchronous mode keep TX clocks running if the capture stream is
239 * still running.
240 */
241 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
242 val = TXHCLKRST | TXCLKRST | TXFSRST;
243
244 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
245 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
246 }
247
248 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
249 {
250 u32 reg;
251
252 mcasp->streams--;
253
254 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
255 if (mcasp->txnumevt) { /* disable FIFO */
256 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
257 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
258 }
259 mcasp_stop_tx(mcasp);
260 } else {
261 if (mcasp->rxnumevt) { /* disable FIFO */
262 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
263 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
264 }
265 mcasp_stop_rx(mcasp);
266 }
267 }
268
269 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
270 unsigned int fmt)
271 {
272 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
273 int ret = 0;
274
275 pm_runtime_get_sync(mcasp->dev);
276 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
277 case SND_SOC_DAIFMT_DSP_B:
278 case SND_SOC_DAIFMT_AC97:
279 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
280 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
281 break;
282 default:
283 /* configure a full-word SYNC pulse (LRCLK) */
284 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
285 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
286
287 /* make 1st data bit occur one ACLK cycle after the frame sync */
288 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(1));
289 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(1));
290 break;
291 }
292
293 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
294 case SND_SOC_DAIFMT_CBS_CFS:
295 /* codec is clock and frame slave */
296 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
297 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
298
299 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
300 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
301
302 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
303 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
304 mcasp->bclk_master = 1;
305 break;
306 case SND_SOC_DAIFMT_CBM_CFS:
307 /* codec is clock master and frame slave */
308 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
309 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
310
311 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
312 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
313
314 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
315 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
316 mcasp->bclk_master = 0;
317 break;
318 case SND_SOC_DAIFMT_CBM_CFM:
319 /* codec is clock and frame master */
320 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
321 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
322
323 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
324 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
325
326 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
327 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
328 mcasp->bclk_master = 0;
329 break;
330
331 default:
332 ret = -EINVAL;
333 goto out;
334 }
335
336 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
337 case SND_SOC_DAIFMT_IB_NF:
338 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
339 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
340
341 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
342 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
343 break;
344
345 case SND_SOC_DAIFMT_NB_IF:
346 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
347 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
348
349 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
350 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
351 break;
352
353 case SND_SOC_DAIFMT_IB_IF:
354 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
355 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
356
357 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
358 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
359 break;
360
361 case SND_SOC_DAIFMT_NB_NF:
362 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
363 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
364
365 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
366 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
367 break;
368
369 default:
370 ret = -EINVAL;
371 break;
372 }
373 out:
374 pm_runtime_put_sync(mcasp->dev);
375 return ret;
376 }
377
378 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
379 {
380 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
381
382 switch (div_id) {
383 case 0: /* MCLK divider */
384 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
385 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
386 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
387 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
388 break;
389
390 case 1: /* BCLK divider */
391 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
392 ACLKXDIV(div - 1), ACLKXDIV_MASK);
393 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
394 ACLKRDIV(div - 1), ACLKRDIV_MASK);
395 break;
396
397 case 2: /* BCLK/LRCLK ratio */
398 mcasp->bclk_lrclk_ratio = div;
399 break;
400
401 default:
402 return -EINVAL;
403 }
404
405 return 0;
406 }
407
408 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
409 unsigned int freq, int dir)
410 {
411 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
412
413 if (dir == SND_SOC_CLOCK_OUT) {
414 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
415 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
416 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
417 } else {
418 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
419 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
420 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
421 }
422
423 mcasp->sysclk_freq = freq;
424
425 return 0;
426 }
427
428 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
429 int word_length)
430 {
431 u32 fmt;
432 u32 tx_rotate = (word_length / 4) & 0x7;
433 u32 rx_rotate = (32 - word_length) / 4;
434 u32 mask = (1ULL << word_length) - 1;
435
436 /*
437 * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
438 * callback, take it into account here. That allows us to for example
439 * send 32 bits per channel to the codec, while only 16 of them carry
440 * audio payload.
441 * The clock ratio is given for a full period of data (for I2S format
442 * both left and right channels), so it has to be divided by number of
443 * tdm-slots (for I2S - divided by 2).
444 */
445 if (mcasp->bclk_lrclk_ratio)
446 word_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots;
447
448 /* mapping of the XSSZ bit-field as described in the datasheet */
449 fmt = (word_length >> 1) - 1;
450
451 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
452 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
453 RXSSZ(0x0F));
454 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
455 TXSSZ(0x0F));
456 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
457 TXROT(7));
458 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
459 RXROT(7));
460 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
461 }
462
463 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
464
465 return 0;
466 }
467
468 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
469 int channels)
470 {
471 int i;
472 u8 tx_ser = 0;
473 u8 rx_ser = 0;
474 u8 slots = mcasp->tdm_slots;
475 u8 max_active_serializers = (channels + slots - 1) / slots;
476 u8 active_serializers, numevt;
477 u32 reg;
478 /* Default configuration */
479 if (mcasp->version != MCASP_VERSION_4)
480 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
481
482 /* All PINS as McASP */
483 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
484
485 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
486 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
487 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
488 } else {
489 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
490 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
491 }
492
493 for (i = 0; i < mcasp->num_serializer; i++) {
494 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
495 mcasp->serial_dir[i]);
496 if (mcasp->serial_dir[i] == TX_MODE &&
497 tx_ser < max_active_serializers) {
498 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
499 tx_ser++;
500 } else if (mcasp->serial_dir[i] == RX_MODE &&
501 rx_ser < max_active_serializers) {
502 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
503 rx_ser++;
504 } else {
505 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
506 SRMOD_INACTIVE, SRMOD_MASK);
507 }
508 }
509
510 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
511 active_serializers = tx_ser;
512 numevt = mcasp->txnumevt;
513 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
514 } else {
515 active_serializers = rx_ser;
516 numevt = mcasp->rxnumevt;
517 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
518 }
519
520 if (active_serializers < max_active_serializers) {
521 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
522 "enabled in mcasp (%d)\n", channels,
523 active_serializers * slots);
524 return -EINVAL;
525 }
526
527 /* AFIFO is not in use */
528 if (!numevt)
529 return 0;
530
531 if (numevt * active_serializers > MCASP_MAX_AFIFO_DEPTH)
532 numevt = active_serializers;
533
534 /* Configure the AFIFO */
535 numevt *= active_serializers;
536 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
537 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
538
539 return 0;
540 }
541
542 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream)
543 {
544 int i, active_slots;
545 u32 mask = 0;
546 u32 busel = 0;
547
548 if ((mcasp->tdm_slots < 2) || (mcasp->tdm_slots > 32)) {
549 dev_err(mcasp->dev, "tdm slot %d not supported\n",
550 mcasp->tdm_slots);
551 return -EINVAL;
552 }
553
554 active_slots = (mcasp->tdm_slots > 31) ? 32 : mcasp->tdm_slots;
555 for (i = 0; i < active_slots; i++)
556 mask |= (1 << i);
557
558 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
559
560 if (!mcasp->dat_port)
561 busel = TXSEL;
562
563 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
564 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
565 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
566 FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF));
567
568 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
569 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
570 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
571 FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF));
572
573 return 0;
574 }
575
576 /* S/PDIF */
577 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp)
578 {
579 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
580 and LSB first */
581 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
582
583 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
584 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
585
586 /* Set the TX tdm : for all the slots */
587 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
588
589 /* Set the TX clock controls : div = 1 and internal */
590 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
591
592 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
593
594 /* Only 44100 and 48000 are valid, both have the same setting */
595 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
596
597 /* Enable the DIT */
598 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
599
600 return 0;
601 }
602
603 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
604 struct snd_pcm_hw_params *params,
605 struct snd_soc_dai *cpu_dai)
606 {
607 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
608 struct davinci_pcm_dma_params *dma_params =
609 &mcasp->dma_params[substream->stream];
610 struct snd_dmaengine_dai_dma_data *dma_data =
611 &mcasp->dma_data[substream->stream];
612 int word_length;
613 u8 fifo_level;
614 u8 slots = mcasp->tdm_slots;
615 u8 active_serializers;
616 int channels = params_channels(params);
617 int ret;
618
619 /* If mcasp is BCLK master we need to set BCLK divider */
620 if (mcasp->bclk_master) {
621 unsigned int bclk_freq = snd_soc_params_to_bclk(params);
622 if (mcasp->sysclk_freq % bclk_freq != 0) {
623 dev_err(mcasp->dev, "Can't produce required BCLK\n");
624 return -EINVAL;
625 }
626 davinci_mcasp_set_clkdiv(
627 cpu_dai, 1, mcasp->sysclk_freq / bclk_freq);
628 }
629
630 ret = mcasp_common_hw_param(mcasp, substream->stream, channels);
631 if (ret)
632 return ret;
633
634 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
635 ret = mcasp_dit_hw_param(mcasp);
636 else
637 ret = mcasp_i2s_hw_param(mcasp, substream->stream);
638
639 if (ret)
640 return ret;
641
642 switch (params_format(params)) {
643 case SNDRV_PCM_FORMAT_U8:
644 case SNDRV_PCM_FORMAT_S8:
645 dma_params->data_type = 1;
646 word_length = 8;
647 break;
648
649 case SNDRV_PCM_FORMAT_U16_LE:
650 case SNDRV_PCM_FORMAT_S16_LE:
651 dma_params->data_type = 2;
652 word_length = 16;
653 break;
654
655 case SNDRV_PCM_FORMAT_U24_3LE:
656 case SNDRV_PCM_FORMAT_S24_3LE:
657 dma_params->data_type = 3;
658 word_length = 24;
659 break;
660
661 case SNDRV_PCM_FORMAT_U24_LE:
662 case SNDRV_PCM_FORMAT_S24_LE:
663 case SNDRV_PCM_FORMAT_U32_LE:
664 case SNDRV_PCM_FORMAT_S32_LE:
665 dma_params->data_type = 4;
666 word_length = 32;
667 break;
668
669 default:
670 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
671 return -EINVAL;
672 }
673
674 /* Calculate FIFO level */
675 active_serializers = (channels + slots - 1) / slots;
676 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
677 fifo_level = mcasp->txnumevt * active_serializers;
678 else
679 fifo_level = mcasp->rxnumevt * active_serializers;
680
681 if (mcasp->version == MCASP_VERSION_2 && !fifo_level)
682 dma_params->acnt = 4;
683 else
684 dma_params->acnt = dma_params->data_type;
685
686 dma_params->fifo_level = fifo_level;
687 dma_data->maxburst = fifo_level;
688
689 davinci_config_channel_size(mcasp, word_length);
690
691 return 0;
692 }
693
694 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
695 int cmd, struct snd_soc_dai *cpu_dai)
696 {
697 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
698 int ret = 0;
699
700 switch (cmd) {
701 case SNDRV_PCM_TRIGGER_RESUME:
702 case SNDRV_PCM_TRIGGER_START:
703 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
704 davinci_mcasp_start(mcasp, substream->stream);
705 break;
706 case SNDRV_PCM_TRIGGER_SUSPEND:
707 case SNDRV_PCM_TRIGGER_STOP:
708 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
709 davinci_mcasp_stop(mcasp, substream->stream);
710 break;
711
712 default:
713 ret = -EINVAL;
714 }
715
716 return ret;
717 }
718
719 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
720 .trigger = davinci_mcasp_trigger,
721 .hw_params = davinci_mcasp_hw_params,
722 .set_fmt = davinci_mcasp_set_dai_fmt,
723 .set_clkdiv = davinci_mcasp_set_clkdiv,
724 .set_sysclk = davinci_mcasp_set_sysclk,
725 };
726
727 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
728 {
729 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
730
731 if (mcasp->version == MCASP_VERSION_4) {
732 /* Using dmaengine PCM */
733 dai->playback_dma_data =
734 &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
735 dai->capture_dma_data =
736 &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
737 } else {
738 /* Using davinci-pcm */
739 dai->playback_dma_data = mcasp->dma_params;
740 dai->capture_dma_data = mcasp->dma_params;
741 }
742
743 return 0;
744 }
745
746 #ifdef CONFIG_PM_SLEEP
747 static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
748 {
749 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
750 struct davinci_mcasp_context *context = &mcasp->context;
751
752 context->txfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG);
753 context->rxfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
754 context->txfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMT_REG);
755 context->rxfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMT_REG);
756 context->aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
757 context->aclkrctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG);
758 context->pdir = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
759
760 return 0;
761 }
762
763 static int davinci_mcasp_resume(struct snd_soc_dai *dai)
764 {
765 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
766 struct davinci_mcasp_context *context = &mcasp->context;
767
768 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, context->txfmtctl);
769 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG, context->rxfmtctl);
770 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMT_REG, context->txfmt);
771 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMT_REG, context->rxfmt);
772 mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, context->aclkxctl);
773 mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, context->aclkrctl);
774 mcasp_set_reg(mcasp, DAVINCI_MCASP_PDIR_REG, context->pdir);
775
776 return 0;
777 }
778 #else
779 #define davinci_mcasp_suspend NULL
780 #define davinci_mcasp_resume NULL
781 #endif
782
783 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
784
785 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
786 SNDRV_PCM_FMTBIT_U8 | \
787 SNDRV_PCM_FMTBIT_S16_LE | \
788 SNDRV_PCM_FMTBIT_U16_LE | \
789 SNDRV_PCM_FMTBIT_S24_LE | \
790 SNDRV_PCM_FMTBIT_U24_LE | \
791 SNDRV_PCM_FMTBIT_S24_3LE | \
792 SNDRV_PCM_FMTBIT_U24_3LE | \
793 SNDRV_PCM_FMTBIT_S32_LE | \
794 SNDRV_PCM_FMTBIT_U32_LE)
795
796 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
797 {
798 .name = "davinci-mcasp.0",
799 .probe = davinci_mcasp_dai_probe,
800 .suspend = davinci_mcasp_suspend,
801 .resume = davinci_mcasp_resume,
802 .playback = {
803 .channels_min = 2,
804 .channels_max = 32 * 16,
805 .rates = DAVINCI_MCASP_RATES,
806 .formats = DAVINCI_MCASP_PCM_FMTS,
807 },
808 .capture = {
809 .channels_min = 2,
810 .channels_max = 32 * 16,
811 .rates = DAVINCI_MCASP_RATES,
812 .formats = DAVINCI_MCASP_PCM_FMTS,
813 },
814 .ops = &davinci_mcasp_dai_ops,
815
816 },
817 {
818 .name = "davinci-mcasp.1",
819 .probe = davinci_mcasp_dai_probe,
820 .playback = {
821 .channels_min = 1,
822 .channels_max = 384,
823 .rates = DAVINCI_MCASP_RATES,
824 .formats = DAVINCI_MCASP_PCM_FMTS,
825 },
826 .ops = &davinci_mcasp_dai_ops,
827 },
828
829 };
830
831 static const struct snd_soc_component_driver davinci_mcasp_component = {
832 .name = "davinci-mcasp",
833 };
834
835 /* Some HW specific values and defaults. The rest is filled in from DT. */
836 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
837 .tx_dma_offset = 0x400,
838 .rx_dma_offset = 0x400,
839 .asp_chan_q = EVENTQ_0,
840 .version = MCASP_VERSION_1,
841 };
842
843 static struct davinci_mcasp_pdata da830_mcasp_pdata = {
844 .tx_dma_offset = 0x2000,
845 .rx_dma_offset = 0x2000,
846 .asp_chan_q = EVENTQ_0,
847 .version = MCASP_VERSION_2,
848 };
849
850 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
851 .tx_dma_offset = 0,
852 .rx_dma_offset = 0,
853 .asp_chan_q = EVENTQ_0,
854 .version = MCASP_VERSION_3,
855 };
856
857 static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
858 .tx_dma_offset = 0x200,
859 .rx_dma_offset = 0x284,
860 .asp_chan_q = EVENTQ_0,
861 .version = MCASP_VERSION_4,
862 };
863
864 static const struct of_device_id mcasp_dt_ids[] = {
865 {
866 .compatible = "ti,dm646x-mcasp-audio",
867 .data = &dm646x_mcasp_pdata,
868 },
869 {
870 .compatible = "ti,da830-mcasp-audio",
871 .data = &da830_mcasp_pdata,
872 },
873 {
874 .compatible = "ti,am33xx-mcasp-audio",
875 .data = &am33xx_mcasp_pdata,
876 },
877 {
878 .compatible = "ti,dra7-mcasp-audio",
879 .data = &dra7_mcasp_pdata,
880 },
881 { /* sentinel */ }
882 };
883 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
884
885 static int mcasp_reparent_fck(struct platform_device *pdev)
886 {
887 struct device_node *node = pdev->dev.of_node;
888 struct clk *gfclk, *parent_clk;
889 const char *parent_name;
890 int ret;
891
892 if (!node)
893 return 0;
894
895 parent_name = of_get_property(node, "fck_parent", NULL);
896 if (!parent_name)
897 return 0;
898
899 gfclk = clk_get(&pdev->dev, "fck");
900 if (IS_ERR(gfclk)) {
901 dev_err(&pdev->dev, "failed to get fck\n");
902 return PTR_ERR(gfclk);
903 }
904
905 parent_clk = clk_get(NULL, parent_name);
906 if (IS_ERR(parent_clk)) {
907 dev_err(&pdev->dev, "failed to get parent clock\n");
908 ret = PTR_ERR(parent_clk);
909 goto err1;
910 }
911
912 ret = clk_set_parent(gfclk, parent_clk);
913 if (ret) {
914 dev_err(&pdev->dev, "failed to reparent fck\n");
915 goto err2;
916 }
917
918 err2:
919 clk_put(parent_clk);
920 err1:
921 clk_put(gfclk);
922 return ret;
923 }
924
925 static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
926 struct platform_device *pdev)
927 {
928 struct device_node *np = pdev->dev.of_node;
929 struct davinci_mcasp_pdata *pdata = NULL;
930 const struct of_device_id *match =
931 of_match_device(mcasp_dt_ids, &pdev->dev);
932 struct of_phandle_args dma_spec;
933
934 const u32 *of_serial_dir32;
935 u32 val;
936 int i, ret = 0;
937
938 if (pdev->dev.platform_data) {
939 pdata = pdev->dev.platform_data;
940 return pdata;
941 } else if (match) {
942 pdata = (struct davinci_mcasp_pdata*) match->data;
943 } else {
944 /* control shouldn't reach here. something is wrong */
945 ret = -EINVAL;
946 goto nodata;
947 }
948
949 ret = of_property_read_u32(np, "op-mode", &val);
950 if (ret >= 0)
951 pdata->op_mode = val;
952
953 ret = of_property_read_u32(np, "tdm-slots", &val);
954 if (ret >= 0) {
955 if (val < 2 || val > 32) {
956 dev_err(&pdev->dev,
957 "tdm-slots must be in rage [2-32]\n");
958 ret = -EINVAL;
959 goto nodata;
960 }
961
962 pdata->tdm_slots = val;
963 }
964
965 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
966 val /= sizeof(u32);
967 if (of_serial_dir32) {
968 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
969 (sizeof(*of_serial_dir) * val),
970 GFP_KERNEL);
971 if (!of_serial_dir) {
972 ret = -ENOMEM;
973 goto nodata;
974 }
975
976 for (i = 0; i < val; i++)
977 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
978
979 pdata->num_serializer = val;
980 pdata->serial_dir = of_serial_dir;
981 }
982
983 ret = of_property_match_string(np, "dma-names", "tx");
984 if (ret < 0)
985 goto nodata;
986
987 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
988 &dma_spec);
989 if (ret < 0)
990 goto nodata;
991
992 pdata->tx_dma_channel = dma_spec.args[0];
993
994 ret = of_property_match_string(np, "dma-names", "rx");
995 if (ret < 0)
996 goto nodata;
997
998 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
999 &dma_spec);
1000 if (ret < 0)
1001 goto nodata;
1002
1003 pdata->rx_dma_channel = dma_spec.args[0];
1004
1005 ret = of_property_read_u32(np, "tx-num-evt", &val);
1006 if (ret >= 0)
1007 pdata->txnumevt = val;
1008
1009 ret = of_property_read_u32(np, "rx-num-evt", &val);
1010 if (ret >= 0)
1011 pdata->rxnumevt = val;
1012
1013 ret = of_property_read_u32(np, "sram-size-playback", &val);
1014 if (ret >= 0)
1015 pdata->sram_size_playback = val;
1016
1017 ret = of_property_read_u32(np, "sram-size-capture", &val);
1018 if (ret >= 0)
1019 pdata->sram_size_capture = val;
1020
1021 return pdata;
1022
1023 nodata:
1024 if (ret < 0) {
1025 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1026 ret);
1027 pdata = NULL;
1028 }
1029 return pdata;
1030 }
1031
1032 static int davinci_mcasp_probe(struct platform_device *pdev)
1033 {
1034 struct davinci_pcm_dma_params *dma_params;
1035 struct snd_dmaengine_dai_dma_data *dma_data;
1036 struct resource *mem, *ioarea, *res, *dat;
1037 struct davinci_mcasp_pdata *pdata;
1038 struct davinci_mcasp *mcasp;
1039 int ret;
1040
1041 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1042 dev_err(&pdev->dev, "No platform data supplied\n");
1043 return -EINVAL;
1044 }
1045
1046 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
1047 GFP_KERNEL);
1048 if (!mcasp)
1049 return -ENOMEM;
1050
1051 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1052 if (!pdata) {
1053 dev_err(&pdev->dev, "no platform data\n");
1054 return -EINVAL;
1055 }
1056
1057 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1058 if (!mem) {
1059 dev_warn(mcasp->dev,
1060 "\"mpu\" mem resource not found, using index 0\n");
1061 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1062 if (!mem) {
1063 dev_err(&pdev->dev, "no mem resource?\n");
1064 return -ENODEV;
1065 }
1066 }
1067
1068 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
1069 resource_size(mem), pdev->name);
1070 if (!ioarea) {
1071 dev_err(&pdev->dev, "Audio region already claimed\n");
1072 return -EBUSY;
1073 }
1074
1075 pm_runtime_enable(&pdev->dev);
1076
1077 ret = pm_runtime_get_sync(&pdev->dev);
1078 if (IS_ERR_VALUE(ret)) {
1079 dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
1080 return ret;
1081 }
1082
1083 mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
1084 if (!mcasp->base) {
1085 dev_err(&pdev->dev, "ioremap failed\n");
1086 ret = -ENOMEM;
1087 goto err_release_clk;
1088 }
1089
1090 mcasp->op_mode = pdata->op_mode;
1091 mcasp->tdm_slots = pdata->tdm_slots;
1092 mcasp->num_serializer = pdata->num_serializer;
1093 mcasp->serial_dir = pdata->serial_dir;
1094 mcasp->version = pdata->version;
1095 mcasp->txnumevt = pdata->txnumevt;
1096 mcasp->rxnumevt = pdata->rxnumevt;
1097
1098 mcasp->dev = &pdev->dev;
1099
1100 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
1101 if (dat)
1102 mcasp->dat_port = true;
1103
1104 dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
1105 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1106 dma_params->asp_chan_q = pdata->asp_chan_q;
1107 dma_params->ram_chan_q = pdata->ram_chan_q;
1108 dma_params->sram_pool = pdata->sram_pool;
1109 dma_params->sram_size = pdata->sram_size_playback;
1110 if (dat)
1111 dma_params->dma_addr = dat->start;
1112 else
1113 dma_params->dma_addr = mem->start + pdata->tx_dma_offset;
1114
1115 /* Unconditional dmaengine stuff */
1116 dma_data->addr = dma_params->dma_addr;
1117
1118 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1119 if (res)
1120 dma_params->channel = res->start;
1121 else
1122 dma_params->channel = pdata->tx_dma_channel;
1123
1124 /* dmaengine filter data for DT and non-DT boot */
1125 if (pdev->dev.of_node)
1126 dma_data->filter_data = "tx";
1127 else
1128 dma_data->filter_data = &dma_params->channel;
1129
1130 dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE];
1131 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1132 dma_params->asp_chan_q = pdata->asp_chan_q;
1133 dma_params->ram_chan_q = pdata->ram_chan_q;
1134 dma_params->sram_pool = pdata->sram_pool;
1135 dma_params->sram_size = pdata->sram_size_capture;
1136 if (dat)
1137 dma_params->dma_addr = dat->start;
1138 else
1139 dma_params->dma_addr = mem->start + pdata->rx_dma_offset;
1140
1141 /* Unconditional dmaengine stuff */
1142 dma_data->addr = dma_params->dma_addr;
1143
1144 if (mcasp->version < MCASP_VERSION_3) {
1145 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
1146 /* dma_params->dma_addr is pointing to the data port address */
1147 mcasp->dat_port = true;
1148 } else {
1149 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
1150 }
1151
1152 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1153 if (res)
1154 dma_params->channel = res->start;
1155 else
1156 dma_params->channel = pdata->rx_dma_channel;
1157
1158 /* dmaengine filter data for DT and non-DT boot */
1159 if (pdev->dev.of_node)
1160 dma_data->filter_data = "rx";
1161 else
1162 dma_data->filter_data = &dma_params->channel;
1163
1164 dev_set_drvdata(&pdev->dev, mcasp);
1165
1166 mcasp_reparent_fck(pdev);
1167
1168 ret = snd_soc_register_component(&pdev->dev, &davinci_mcasp_component,
1169 &davinci_mcasp_dai[pdata->op_mode], 1);
1170
1171 if (ret != 0)
1172 goto err_release_clk;
1173
1174 if (mcasp->version != MCASP_VERSION_4) {
1175 ret = davinci_soc_platform_register(&pdev->dev);
1176 if (ret) {
1177 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
1178 goto err_unregister_component;
1179 }
1180 }
1181
1182 return 0;
1183
1184 err_unregister_component:
1185 snd_soc_unregister_component(&pdev->dev);
1186 err_release_clk:
1187 pm_runtime_put_sync(&pdev->dev);
1188 pm_runtime_disable(&pdev->dev);
1189 return ret;
1190 }
1191
1192 static int davinci_mcasp_remove(struct platform_device *pdev)
1193 {
1194 struct davinci_mcasp *mcasp = dev_get_drvdata(&pdev->dev);
1195
1196 snd_soc_unregister_component(&pdev->dev);
1197 if (mcasp->version != MCASP_VERSION_4)
1198 davinci_soc_platform_unregister(&pdev->dev);
1199
1200 pm_runtime_put_sync(&pdev->dev);
1201 pm_runtime_disable(&pdev->dev);
1202
1203 return 0;
1204 }
1205
1206 static struct platform_driver davinci_mcasp_driver = {
1207 .probe = davinci_mcasp_probe,
1208 .remove = davinci_mcasp_remove,
1209 .driver = {
1210 .name = "davinci-mcasp",
1211 .owner = THIS_MODULE,
1212 .of_match_table = mcasp_dt_ids,
1213 },
1214 };
1215
1216 module_platform_driver(davinci_mcasp_driver);
1217
1218 MODULE_AUTHOR("Steve Chen");
1219 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1220 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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