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Merge branch 'pci/resource' into next
[deliverable/linux.git] / sound / soc / davinci / davinci-mcasp.c
1 /*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/of.h>
27 #include <linux/of_platform.h>
28 #include <linux/of_device.h>
29
30 #include <sound/core.h>
31 #include <sound/pcm.h>
32 #include <sound/pcm_params.h>
33 #include <sound/initval.h>
34 #include <sound/soc.h>
35 #include <sound/dmaengine_pcm.h>
36
37 #include "davinci-pcm.h"
38 #include "davinci-mcasp.h"
39
40 struct davinci_mcasp {
41 struct davinci_pcm_dma_params dma_params[2];
42 struct snd_dmaengine_dai_dma_data dma_data[2];
43 void __iomem *base;
44 u32 fifo_base;
45 struct device *dev;
46
47 /* McASP specific data */
48 int tdm_slots;
49 u8 op_mode;
50 u8 num_serializer;
51 u8 *serial_dir;
52 u8 version;
53 u16 bclk_lrclk_ratio;
54 int streams;
55
56 /* McASP FIFO related */
57 u8 txnumevt;
58 u8 rxnumevt;
59
60 bool dat_port;
61
62 #ifdef CONFIG_PM_SLEEP
63 struct {
64 u32 txfmtctl;
65 u32 rxfmtctl;
66 u32 txfmt;
67 u32 rxfmt;
68 u32 aclkxctl;
69 u32 aclkrctl;
70 u32 pdir;
71 } context;
72 #endif
73 };
74
75 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
76 u32 val)
77 {
78 void __iomem *reg = mcasp->base + offset;
79 __raw_writel(__raw_readl(reg) | val, reg);
80 }
81
82 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
83 u32 val)
84 {
85 void __iomem *reg = mcasp->base + offset;
86 __raw_writel((__raw_readl(reg) & ~(val)), reg);
87 }
88
89 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
90 u32 val, u32 mask)
91 {
92 void __iomem *reg = mcasp->base + offset;
93 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
94 }
95
96 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
97 u32 val)
98 {
99 __raw_writel(val, mcasp->base + offset);
100 }
101
102 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
103 {
104 return (u32)__raw_readl(mcasp->base + offset);
105 }
106
107 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
108 {
109 int i = 0;
110
111 mcasp_set_bits(mcasp, ctl_reg, val);
112
113 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
114 /* loop count is to avoid the lock-up */
115 for (i = 0; i < 1000; i++) {
116 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
117 break;
118 }
119
120 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
121 printk(KERN_ERR "GBLCTL write error\n");
122 }
123
124 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
125 {
126 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
127 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
128
129 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
130 }
131
132 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
133 {
134 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
135 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
136
137 /*
138 * When ASYNC == 0 the transmit and receive sections operate
139 * synchronously from the transmit clock and frame sync. We need to make
140 * sure that the TX signlas are enabled when starting reception.
141 */
142 if (mcasp_is_synchronous(mcasp)) {
143 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
144 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
145 }
146
147 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
148 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
149
150 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
151 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
152 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
153
154 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
155 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
156
157 if (mcasp_is_synchronous(mcasp))
158 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
159 }
160
161 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
162 {
163 u8 offset = 0, i;
164 u32 cnt;
165
166 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
167 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
168 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
169 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
170
171 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
172 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
173 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
174 for (i = 0; i < mcasp->num_serializer; i++) {
175 if (mcasp->serial_dir[i] == TX_MODE) {
176 offset = i;
177 break;
178 }
179 }
180
181 /* wait for TX ready */
182 cnt = 0;
183 while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(offset)) &
184 TXSTATE) && (cnt < 100000))
185 cnt++;
186
187 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
188 }
189
190 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
191 {
192 u32 reg;
193
194 mcasp->streams++;
195
196 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
197 if (mcasp->txnumevt) { /* enable FIFO */
198 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
199 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
200 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
201 }
202 mcasp_start_tx(mcasp);
203 } else {
204 if (mcasp->rxnumevt) { /* enable FIFO */
205 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
206 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
207 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
208 }
209 mcasp_start_rx(mcasp);
210 }
211 }
212
213 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
214 {
215 /*
216 * In synchronous mode stop the TX clocks if no other stream is
217 * running
218 */
219 if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
220 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
221
222 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
223 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
224 }
225
226 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
227 {
228 u32 val = 0;
229
230 /*
231 * In synchronous mode keep TX clocks running if the capture stream is
232 * still running.
233 */
234 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
235 val = TXHCLKRST | TXCLKRST | TXFSRST;
236
237 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
238 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
239 }
240
241 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
242 {
243 u32 reg;
244
245 mcasp->streams--;
246
247 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
248 if (mcasp->txnumevt) { /* disable FIFO */
249 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
250 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
251 }
252 mcasp_stop_tx(mcasp);
253 } else {
254 if (mcasp->rxnumevt) { /* disable FIFO */
255 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
256 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
257 }
258 mcasp_stop_rx(mcasp);
259 }
260 }
261
262 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
263 unsigned int fmt)
264 {
265 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
266
267 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
268 case SND_SOC_DAIFMT_DSP_B:
269 case SND_SOC_DAIFMT_AC97:
270 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
271 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
272 break;
273 default:
274 /* configure a full-word SYNC pulse (LRCLK) */
275 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
276 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
277
278 /* make 1st data bit occur one ACLK cycle after the frame sync */
279 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(1));
280 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(1));
281 break;
282 }
283
284 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
285 case SND_SOC_DAIFMT_CBS_CFS:
286 /* codec is clock and frame slave */
287 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
288 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
289
290 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
291 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
292
293 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
294 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
295 break;
296 case SND_SOC_DAIFMT_CBM_CFS:
297 /* codec is clock master and frame slave */
298 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
299 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
300
301 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
302 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
303
304 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
305 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
306 break;
307 case SND_SOC_DAIFMT_CBM_CFM:
308 /* codec is clock and frame master */
309 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
310 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
311
312 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
313 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
314
315 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
316 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
317 break;
318
319 default:
320 return -EINVAL;
321 }
322
323 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
324 case SND_SOC_DAIFMT_IB_NF:
325 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
326 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
327
328 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
329 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
330 break;
331
332 case SND_SOC_DAIFMT_NB_IF:
333 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
334 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
335
336 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
337 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
338 break;
339
340 case SND_SOC_DAIFMT_IB_IF:
341 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
342 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
343
344 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
345 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
346 break;
347
348 case SND_SOC_DAIFMT_NB_NF:
349 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
350 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
351
352 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
353 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
354 break;
355
356 default:
357 return -EINVAL;
358 }
359
360 return 0;
361 }
362
363 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
364 {
365 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
366
367 switch (div_id) {
368 case 0: /* MCLK divider */
369 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
370 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
371 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
372 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
373 break;
374
375 case 1: /* BCLK divider */
376 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
377 ACLKXDIV(div - 1), ACLKXDIV_MASK);
378 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
379 ACLKRDIV(div - 1), ACLKRDIV_MASK);
380 break;
381
382 case 2: /* BCLK/LRCLK ratio */
383 mcasp->bclk_lrclk_ratio = div;
384 break;
385
386 default:
387 return -EINVAL;
388 }
389
390 return 0;
391 }
392
393 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
394 unsigned int freq, int dir)
395 {
396 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
397
398 if (dir == SND_SOC_CLOCK_OUT) {
399 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
400 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
401 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
402 } else {
403 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
404 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
405 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
406 }
407
408 return 0;
409 }
410
411 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
412 int word_length)
413 {
414 u32 fmt;
415 u32 tx_rotate = (word_length / 4) & 0x7;
416 u32 rx_rotate = (32 - word_length) / 4;
417 u32 mask = (1ULL << word_length) - 1;
418
419 /*
420 * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
421 * callback, take it into account here. That allows us to for example
422 * send 32 bits per channel to the codec, while only 16 of them carry
423 * audio payload.
424 * The clock ratio is given for a full period of data (for I2S format
425 * both left and right channels), so it has to be divided by number of
426 * tdm-slots (for I2S - divided by 2).
427 */
428 if (mcasp->bclk_lrclk_ratio)
429 word_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots;
430
431 /* mapping of the XSSZ bit-field as described in the datasheet */
432 fmt = (word_length >> 1) - 1;
433
434 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
435 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
436 RXSSZ(0x0F));
437 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
438 TXSSZ(0x0F));
439 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
440 TXROT(7));
441 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
442 RXROT(7));
443 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
444 }
445
446 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
447
448 return 0;
449 }
450
451 static int davinci_hw_common_param(struct davinci_mcasp *mcasp, int stream,
452 int channels)
453 {
454 int i;
455 u8 tx_ser = 0;
456 u8 rx_ser = 0;
457 u8 ser;
458 u8 slots = mcasp->tdm_slots;
459 u8 max_active_serializers = (channels + slots - 1) / slots;
460 u32 reg;
461 /* Default configuration */
462 if (mcasp->version != MCASP_VERSION_4)
463 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
464
465 /* All PINS as McASP */
466 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
467
468 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
469 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
470 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
471 } else {
472 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
473 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
474 }
475
476 for (i = 0; i < mcasp->num_serializer; i++) {
477 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
478 mcasp->serial_dir[i]);
479 if (mcasp->serial_dir[i] == TX_MODE &&
480 tx_ser < max_active_serializers) {
481 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
482 tx_ser++;
483 } else if (mcasp->serial_dir[i] == RX_MODE &&
484 rx_ser < max_active_serializers) {
485 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
486 rx_ser++;
487 } else {
488 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
489 SRMOD_INACTIVE, SRMOD_MASK);
490 }
491 }
492
493 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
494 ser = tx_ser;
495 else
496 ser = rx_ser;
497
498 if (ser < max_active_serializers) {
499 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
500 "enabled in mcasp (%d)\n", channels, ser * slots);
501 return -EINVAL;
502 }
503
504 if (mcasp->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
505 if (mcasp->txnumevt * tx_ser > 64)
506 mcasp->txnumevt = 1;
507
508 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
509 mcasp_mod_bits(mcasp, reg, tx_ser, NUMDMA_MASK);
510 mcasp_mod_bits(mcasp, reg, ((mcasp->txnumevt * tx_ser) << 8),
511 NUMEVT_MASK);
512 }
513
514 if (mcasp->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
515 if (mcasp->rxnumevt * rx_ser > 64)
516 mcasp->rxnumevt = 1;
517
518 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
519 mcasp_mod_bits(mcasp, reg, rx_ser, NUMDMA_MASK);
520 mcasp_mod_bits(mcasp, reg, ((mcasp->rxnumevt * rx_ser) << 8),
521 NUMEVT_MASK);
522 }
523
524 return 0;
525 }
526
527 static void davinci_hw_param(struct davinci_mcasp *mcasp, int stream)
528 {
529 int i, active_slots;
530 u32 mask = 0;
531 u32 busel = 0;
532
533 active_slots = (mcasp->tdm_slots > 31) ? 32 : mcasp->tdm_slots;
534 for (i = 0; i < active_slots; i++)
535 mask |= (1 << i);
536
537 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
538
539 if (!mcasp->dat_port)
540 busel = TXSEL;
541
542 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
543 /* bit stream is MSB first with no delay */
544 /* DSP_B mode */
545 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
546 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
547
548 if ((mcasp->tdm_slots >= 2) && (mcasp->tdm_slots <= 32))
549 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
550 FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF));
551 else
552 printk(KERN_ERR "playback tdm slot %d not supported\n",
553 mcasp->tdm_slots);
554 } else {
555 /* bit stream is MSB first with no delay */
556 /* DSP_B mode */
557 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
558 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
559
560 if ((mcasp->tdm_slots >= 2) && (mcasp->tdm_slots <= 32))
561 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
562 FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF));
563 else
564 printk(KERN_ERR "capture tdm slot %d not supported\n",
565 mcasp->tdm_slots);
566 }
567 }
568
569 /* S/PDIF */
570 static void davinci_hw_dit_param(struct davinci_mcasp *mcasp)
571 {
572 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
573 and LSB first */
574 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
575
576 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
577 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
578
579 /* Set the TX tdm : for all the slots */
580 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
581
582 /* Set the TX clock controls : div = 1 and internal */
583 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
584
585 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
586
587 /* Only 44100 and 48000 are valid, both have the same setting */
588 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
589
590 /* Enable the DIT */
591 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
592 }
593
594 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
595 struct snd_pcm_hw_params *params,
596 struct snd_soc_dai *cpu_dai)
597 {
598 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
599 struct davinci_pcm_dma_params *dma_params =
600 &mcasp->dma_params[substream->stream];
601 struct snd_dmaengine_dai_dma_data *dma_data =
602 &mcasp->dma_data[substream->stream];
603 int word_length;
604 u8 fifo_level;
605 u8 slots = mcasp->tdm_slots;
606 u8 active_serializers;
607 int channels;
608 struct snd_interval *pcm_channels = hw_param_interval(params,
609 SNDRV_PCM_HW_PARAM_CHANNELS);
610 channels = pcm_channels->min;
611
612 active_serializers = (channels + slots - 1) / slots;
613
614 if (davinci_hw_common_param(mcasp, substream->stream, channels) == -EINVAL)
615 return -EINVAL;
616 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
617 fifo_level = mcasp->txnumevt * active_serializers;
618 else
619 fifo_level = mcasp->rxnumevt * active_serializers;
620
621 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
622 davinci_hw_dit_param(mcasp);
623 else
624 davinci_hw_param(mcasp, substream->stream);
625
626 switch (params_format(params)) {
627 case SNDRV_PCM_FORMAT_U8:
628 case SNDRV_PCM_FORMAT_S8:
629 dma_params->data_type = 1;
630 word_length = 8;
631 break;
632
633 case SNDRV_PCM_FORMAT_U16_LE:
634 case SNDRV_PCM_FORMAT_S16_LE:
635 dma_params->data_type = 2;
636 word_length = 16;
637 break;
638
639 case SNDRV_PCM_FORMAT_U24_3LE:
640 case SNDRV_PCM_FORMAT_S24_3LE:
641 dma_params->data_type = 3;
642 word_length = 24;
643 break;
644
645 case SNDRV_PCM_FORMAT_U24_LE:
646 case SNDRV_PCM_FORMAT_S24_LE:
647 case SNDRV_PCM_FORMAT_U32_LE:
648 case SNDRV_PCM_FORMAT_S32_LE:
649 dma_params->data_type = 4;
650 word_length = 32;
651 break;
652
653 default:
654 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
655 return -EINVAL;
656 }
657
658 if (mcasp->version == MCASP_VERSION_2 && !fifo_level)
659 dma_params->acnt = 4;
660 else
661 dma_params->acnt = dma_params->data_type;
662
663 dma_params->fifo_level = fifo_level;
664 dma_data->maxburst = fifo_level;
665
666 davinci_config_channel_size(mcasp, word_length);
667
668 return 0;
669 }
670
671 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
672 int cmd, struct snd_soc_dai *cpu_dai)
673 {
674 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
675 int ret = 0;
676
677 switch (cmd) {
678 case SNDRV_PCM_TRIGGER_RESUME:
679 case SNDRV_PCM_TRIGGER_START:
680 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
681 ret = pm_runtime_get_sync(mcasp->dev);
682 if (IS_ERR_VALUE(ret))
683 dev_err(mcasp->dev, "pm_runtime_get_sync() failed\n");
684 davinci_mcasp_start(mcasp, substream->stream);
685 break;
686
687 case SNDRV_PCM_TRIGGER_SUSPEND:
688 davinci_mcasp_stop(mcasp, substream->stream);
689 ret = pm_runtime_put_sync(mcasp->dev);
690 if (IS_ERR_VALUE(ret))
691 dev_err(mcasp->dev, "pm_runtime_put_sync() failed\n");
692 break;
693
694 case SNDRV_PCM_TRIGGER_STOP:
695 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
696 davinci_mcasp_stop(mcasp, substream->stream);
697 break;
698
699 default:
700 ret = -EINVAL;
701 }
702
703 return ret;
704 }
705
706 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
707 struct snd_soc_dai *dai)
708 {
709 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
710
711 if (mcasp->version == MCASP_VERSION_4)
712 snd_soc_dai_set_dma_data(dai, substream,
713 &mcasp->dma_data[substream->stream]);
714 else
715 snd_soc_dai_set_dma_data(dai, substream, mcasp->dma_params);
716
717 return 0;
718 }
719
720 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
721 .startup = davinci_mcasp_startup,
722 .trigger = davinci_mcasp_trigger,
723 .hw_params = davinci_mcasp_hw_params,
724 .set_fmt = davinci_mcasp_set_dai_fmt,
725 .set_clkdiv = davinci_mcasp_set_clkdiv,
726 .set_sysclk = davinci_mcasp_set_sysclk,
727 };
728
729 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
730
731 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
732 SNDRV_PCM_FMTBIT_U8 | \
733 SNDRV_PCM_FMTBIT_S16_LE | \
734 SNDRV_PCM_FMTBIT_U16_LE | \
735 SNDRV_PCM_FMTBIT_S24_LE | \
736 SNDRV_PCM_FMTBIT_U24_LE | \
737 SNDRV_PCM_FMTBIT_S24_3LE | \
738 SNDRV_PCM_FMTBIT_U24_3LE | \
739 SNDRV_PCM_FMTBIT_S32_LE | \
740 SNDRV_PCM_FMTBIT_U32_LE)
741
742 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
743 {
744 .name = "davinci-mcasp.0",
745 .playback = {
746 .channels_min = 2,
747 .channels_max = 32 * 16,
748 .rates = DAVINCI_MCASP_RATES,
749 .formats = DAVINCI_MCASP_PCM_FMTS,
750 },
751 .capture = {
752 .channels_min = 2,
753 .channels_max = 32 * 16,
754 .rates = DAVINCI_MCASP_RATES,
755 .formats = DAVINCI_MCASP_PCM_FMTS,
756 },
757 .ops = &davinci_mcasp_dai_ops,
758
759 },
760 {
761 .name = "davinci-mcasp.1",
762 .playback = {
763 .channels_min = 1,
764 .channels_max = 384,
765 .rates = DAVINCI_MCASP_RATES,
766 .formats = DAVINCI_MCASP_PCM_FMTS,
767 },
768 .ops = &davinci_mcasp_dai_ops,
769 },
770
771 };
772
773 static const struct snd_soc_component_driver davinci_mcasp_component = {
774 .name = "davinci-mcasp",
775 };
776
777 /* Some HW specific values and defaults. The rest is filled in from DT. */
778 static struct snd_platform_data dm646x_mcasp_pdata = {
779 .tx_dma_offset = 0x400,
780 .rx_dma_offset = 0x400,
781 .asp_chan_q = EVENTQ_0,
782 .version = MCASP_VERSION_1,
783 };
784
785 static struct snd_platform_data da830_mcasp_pdata = {
786 .tx_dma_offset = 0x2000,
787 .rx_dma_offset = 0x2000,
788 .asp_chan_q = EVENTQ_0,
789 .version = MCASP_VERSION_2,
790 };
791
792 static struct snd_platform_data am33xx_mcasp_pdata = {
793 .tx_dma_offset = 0,
794 .rx_dma_offset = 0,
795 .asp_chan_q = EVENTQ_0,
796 .version = MCASP_VERSION_3,
797 };
798
799 static struct snd_platform_data dra7_mcasp_pdata = {
800 .tx_dma_offset = 0x200,
801 .rx_dma_offset = 0x284,
802 .asp_chan_q = EVENTQ_0,
803 .version = MCASP_VERSION_4,
804 };
805
806 static const struct of_device_id mcasp_dt_ids[] = {
807 {
808 .compatible = "ti,dm646x-mcasp-audio",
809 .data = &dm646x_mcasp_pdata,
810 },
811 {
812 .compatible = "ti,da830-mcasp-audio",
813 .data = &da830_mcasp_pdata,
814 },
815 {
816 .compatible = "ti,am33xx-mcasp-audio",
817 .data = &am33xx_mcasp_pdata,
818 },
819 {
820 .compatible = "ti,dra7-mcasp-audio",
821 .data = &dra7_mcasp_pdata,
822 },
823 { /* sentinel */ }
824 };
825 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
826
827 static int mcasp_reparent_fck(struct platform_device *pdev)
828 {
829 struct device_node *node = pdev->dev.of_node;
830 struct clk *gfclk, *parent_clk;
831 const char *parent_name;
832 int ret;
833
834 if (!node)
835 return 0;
836
837 parent_name = of_get_property(node, "fck_parent", NULL);
838 if (!parent_name)
839 return 0;
840
841 gfclk = clk_get(&pdev->dev, "fck");
842 if (IS_ERR(gfclk)) {
843 dev_err(&pdev->dev, "failed to get fck\n");
844 return PTR_ERR(gfclk);
845 }
846
847 parent_clk = clk_get(NULL, parent_name);
848 if (IS_ERR(parent_clk)) {
849 dev_err(&pdev->dev, "failed to get parent clock\n");
850 ret = PTR_ERR(parent_clk);
851 goto err1;
852 }
853
854 ret = clk_set_parent(gfclk, parent_clk);
855 if (ret) {
856 dev_err(&pdev->dev, "failed to reparent fck\n");
857 goto err2;
858 }
859
860 err2:
861 clk_put(parent_clk);
862 err1:
863 clk_put(gfclk);
864 return ret;
865 }
866
867 static struct snd_platform_data *davinci_mcasp_set_pdata_from_of(
868 struct platform_device *pdev)
869 {
870 struct device_node *np = pdev->dev.of_node;
871 struct snd_platform_data *pdata = NULL;
872 const struct of_device_id *match =
873 of_match_device(mcasp_dt_ids, &pdev->dev);
874 struct of_phandle_args dma_spec;
875
876 const u32 *of_serial_dir32;
877 u32 val;
878 int i, ret = 0;
879
880 if (pdev->dev.platform_data) {
881 pdata = pdev->dev.platform_data;
882 return pdata;
883 } else if (match) {
884 pdata = (struct snd_platform_data *) match->data;
885 } else {
886 /* control shouldn't reach here. something is wrong */
887 ret = -EINVAL;
888 goto nodata;
889 }
890
891 ret = of_property_read_u32(np, "op-mode", &val);
892 if (ret >= 0)
893 pdata->op_mode = val;
894
895 ret = of_property_read_u32(np, "tdm-slots", &val);
896 if (ret >= 0) {
897 if (val < 2 || val > 32) {
898 dev_err(&pdev->dev,
899 "tdm-slots must be in rage [2-32]\n");
900 ret = -EINVAL;
901 goto nodata;
902 }
903
904 pdata->tdm_slots = val;
905 }
906
907 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
908 val /= sizeof(u32);
909 if (of_serial_dir32) {
910 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
911 (sizeof(*of_serial_dir) * val),
912 GFP_KERNEL);
913 if (!of_serial_dir) {
914 ret = -ENOMEM;
915 goto nodata;
916 }
917
918 for (i = 0; i < val; i++)
919 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
920
921 pdata->num_serializer = val;
922 pdata->serial_dir = of_serial_dir;
923 }
924
925 ret = of_property_match_string(np, "dma-names", "tx");
926 if (ret < 0)
927 goto nodata;
928
929 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
930 &dma_spec);
931 if (ret < 0)
932 goto nodata;
933
934 pdata->tx_dma_channel = dma_spec.args[0];
935
936 ret = of_property_match_string(np, "dma-names", "rx");
937 if (ret < 0)
938 goto nodata;
939
940 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
941 &dma_spec);
942 if (ret < 0)
943 goto nodata;
944
945 pdata->rx_dma_channel = dma_spec.args[0];
946
947 ret = of_property_read_u32(np, "tx-num-evt", &val);
948 if (ret >= 0)
949 pdata->txnumevt = val;
950
951 ret = of_property_read_u32(np, "rx-num-evt", &val);
952 if (ret >= 0)
953 pdata->rxnumevt = val;
954
955 ret = of_property_read_u32(np, "sram-size-playback", &val);
956 if (ret >= 0)
957 pdata->sram_size_playback = val;
958
959 ret = of_property_read_u32(np, "sram-size-capture", &val);
960 if (ret >= 0)
961 pdata->sram_size_capture = val;
962
963 return pdata;
964
965 nodata:
966 if (ret < 0) {
967 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
968 ret);
969 pdata = NULL;
970 }
971 return pdata;
972 }
973
974 static int davinci_mcasp_probe(struct platform_device *pdev)
975 {
976 struct davinci_pcm_dma_params *dma_data;
977 struct resource *mem, *ioarea, *res, *dat;
978 struct snd_platform_data *pdata;
979 struct davinci_mcasp *mcasp;
980 int ret;
981
982 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
983 dev_err(&pdev->dev, "No platform data supplied\n");
984 return -EINVAL;
985 }
986
987 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
988 GFP_KERNEL);
989 if (!mcasp)
990 return -ENOMEM;
991
992 pdata = davinci_mcasp_set_pdata_from_of(pdev);
993 if (!pdata) {
994 dev_err(&pdev->dev, "no platform data\n");
995 return -EINVAL;
996 }
997
998 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
999 if (!mem) {
1000 dev_warn(mcasp->dev,
1001 "\"mpu\" mem resource not found, using index 0\n");
1002 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1003 if (!mem) {
1004 dev_err(&pdev->dev, "no mem resource?\n");
1005 return -ENODEV;
1006 }
1007 }
1008
1009 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
1010 resource_size(mem), pdev->name);
1011 if (!ioarea) {
1012 dev_err(&pdev->dev, "Audio region already claimed\n");
1013 return -EBUSY;
1014 }
1015
1016 pm_runtime_enable(&pdev->dev);
1017
1018 ret = pm_runtime_get_sync(&pdev->dev);
1019 if (IS_ERR_VALUE(ret)) {
1020 dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
1021 return ret;
1022 }
1023
1024 mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
1025 if (!mcasp->base) {
1026 dev_err(&pdev->dev, "ioremap failed\n");
1027 ret = -ENOMEM;
1028 goto err_release_clk;
1029 }
1030
1031 mcasp->op_mode = pdata->op_mode;
1032 mcasp->tdm_slots = pdata->tdm_slots;
1033 mcasp->num_serializer = pdata->num_serializer;
1034 mcasp->serial_dir = pdata->serial_dir;
1035 mcasp->version = pdata->version;
1036 mcasp->txnumevt = pdata->txnumevt;
1037 mcasp->rxnumevt = pdata->rxnumevt;
1038
1039 mcasp->dev = &pdev->dev;
1040
1041 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
1042 if (dat)
1043 mcasp->dat_port = true;
1044
1045 dma_data = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
1046 dma_data->asp_chan_q = pdata->asp_chan_q;
1047 dma_data->ram_chan_q = pdata->ram_chan_q;
1048 dma_data->sram_pool = pdata->sram_pool;
1049 dma_data->sram_size = pdata->sram_size_playback;
1050 if (dat)
1051 dma_data->dma_addr = dat->start;
1052 else
1053 dma_data->dma_addr = mem->start + pdata->tx_dma_offset;
1054
1055 /* Unconditional dmaengine stuff */
1056 mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr = dma_data->dma_addr;
1057
1058 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1059 if (res)
1060 dma_data->channel = res->start;
1061 else
1062 dma_data->channel = pdata->tx_dma_channel;
1063
1064 dma_data = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE];
1065 dma_data->asp_chan_q = pdata->asp_chan_q;
1066 dma_data->ram_chan_q = pdata->ram_chan_q;
1067 dma_data->sram_pool = pdata->sram_pool;
1068 dma_data->sram_size = pdata->sram_size_capture;
1069 if (dat)
1070 dma_data->dma_addr = dat->start;
1071 else
1072 dma_data->dma_addr = mem->start + pdata->rx_dma_offset;
1073
1074 /* Unconditional dmaengine stuff */
1075 mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr = dma_data->dma_addr;
1076
1077 if (mcasp->version < MCASP_VERSION_3) {
1078 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
1079 /* dma_data->dma_addr is pointing to the data port address */
1080 mcasp->dat_port = true;
1081 } else {
1082 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
1083 }
1084
1085 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1086 if (res)
1087 dma_data->channel = res->start;
1088 else
1089 dma_data->channel = pdata->rx_dma_channel;
1090
1091 /* Unconditional dmaengine stuff */
1092 mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data = "tx";
1093 mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE].filter_data = "rx";
1094
1095 dev_set_drvdata(&pdev->dev, mcasp);
1096
1097 mcasp_reparent_fck(pdev);
1098
1099 ret = snd_soc_register_component(&pdev->dev, &davinci_mcasp_component,
1100 &davinci_mcasp_dai[pdata->op_mode], 1);
1101
1102 if (ret != 0)
1103 goto err_release_clk;
1104
1105 if (mcasp->version != MCASP_VERSION_4) {
1106 ret = davinci_soc_platform_register(&pdev->dev);
1107 if (ret) {
1108 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
1109 goto err_unregister_component;
1110 }
1111 }
1112
1113 return 0;
1114
1115 err_unregister_component:
1116 snd_soc_unregister_component(&pdev->dev);
1117 err_release_clk:
1118 pm_runtime_put_sync(&pdev->dev);
1119 pm_runtime_disable(&pdev->dev);
1120 return ret;
1121 }
1122
1123 static int davinci_mcasp_remove(struct platform_device *pdev)
1124 {
1125 struct davinci_mcasp *mcasp = dev_get_drvdata(&pdev->dev);
1126
1127 snd_soc_unregister_component(&pdev->dev);
1128 if (mcasp->version != MCASP_VERSION_4)
1129 davinci_soc_platform_unregister(&pdev->dev);
1130
1131 pm_runtime_put_sync(&pdev->dev);
1132 pm_runtime_disable(&pdev->dev);
1133
1134 return 0;
1135 }
1136
1137 #ifdef CONFIG_PM_SLEEP
1138 static int davinci_mcasp_suspend(struct device *dev)
1139 {
1140 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
1141
1142 mcasp->context.txfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG);
1143 mcasp->context.rxfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
1144 mcasp->context.txfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMT_REG);
1145 mcasp->context.rxfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMT_REG);
1146 mcasp->context.aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
1147 mcasp->context.aclkrctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG);
1148 mcasp->context.pdir = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
1149
1150 return 0;
1151 }
1152
1153 static int davinci_mcasp_resume(struct device *dev)
1154 {
1155 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
1156
1157 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, mcasp->context.txfmtctl);
1158 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG, mcasp->context.rxfmtctl);
1159 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMT_REG, mcasp->context.txfmt);
1160 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMT_REG, mcasp->context.rxfmt);
1161 mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, mcasp->context.aclkxctl);
1162 mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, mcasp->context.aclkrctl);
1163 mcasp_set_reg(mcasp, DAVINCI_MCASP_PDIR_REG, mcasp->context.pdir);
1164
1165 return 0;
1166 }
1167 #endif
1168
1169 SIMPLE_DEV_PM_OPS(davinci_mcasp_pm_ops,
1170 davinci_mcasp_suspend,
1171 davinci_mcasp_resume);
1172
1173 static struct platform_driver davinci_mcasp_driver = {
1174 .probe = davinci_mcasp_probe,
1175 .remove = davinci_mcasp_remove,
1176 .driver = {
1177 .name = "davinci-mcasp",
1178 .owner = THIS_MODULE,
1179 .pm = &davinci_mcasp_pm_ops,
1180 .of_match_table = mcasp_dt_ids,
1181 },
1182 };
1183
1184 module_platform_driver(davinci_mcasp_driver);
1185
1186 MODULE_AUTHOR("Steve Chen");
1187 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1188 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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