2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
4 * Multi-channel Audio Serial Port Driver
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
24 #include <linux/clk.h>
25 #include <linux/pm_runtime.h>
27 #include <linux/of_platform.h>
28 #include <linux/of_device.h>
29 #include <linux/platform_data/davinci_asp.h>
30 #include <linux/math64.h>
32 #include <sound/asoundef.h>
33 #include <sound/core.h>
34 #include <sound/pcm.h>
35 #include <sound/pcm_params.h>
36 #include <sound/initval.h>
37 #include <sound/soc.h>
38 #include <sound/dmaengine_pcm.h>
39 #include <sound/omap-pcm.h>
42 #include "davinci-mcasp.h"
44 #define MCASP_MAX_AFIFO_DEPTH 64
46 static u32 context_regs
[] = {
47 DAVINCI_MCASP_TXFMCTL_REG
,
48 DAVINCI_MCASP_RXFMCTL_REG
,
49 DAVINCI_MCASP_TXFMT_REG
,
50 DAVINCI_MCASP_RXFMT_REG
,
51 DAVINCI_MCASP_ACLKXCTL_REG
,
52 DAVINCI_MCASP_ACLKRCTL_REG
,
53 DAVINCI_MCASP_AHCLKXCTL_REG
,
54 DAVINCI_MCASP_AHCLKRCTL_REG
,
55 DAVINCI_MCASP_PDIR_REG
,
56 DAVINCI_MCASP_RXMASK_REG
,
57 DAVINCI_MCASP_TXMASK_REG
,
58 DAVINCI_MCASP_RXTDM_REG
,
59 DAVINCI_MCASP_TXTDM_REG
,
62 struct davinci_mcasp_context
{
63 u32 config_regs
[ARRAY_SIZE(context_regs
)];
64 u32 afifo_regs
[2]; /* for read/write fifo control registers */
65 u32
*xrsr_regs
; /* for serializer configuration */
69 struct davinci_mcasp_ruledata
{
70 struct davinci_mcasp
*mcasp
;
74 struct davinci_mcasp
{
75 struct snd_dmaengine_dai_dma_data dma_data
[2];
79 struct snd_pcm_substream
*substreams
[2];
81 /* McASP specific data */
96 /* McASP FIFO related */
102 /* Used for comstraint setting on the second stream */
105 #ifdef CONFIG_PM_SLEEP
106 struct davinci_mcasp_context context
;
109 struct davinci_mcasp_ruledata ruledata
[2];
112 static inline void mcasp_set_bits(struct davinci_mcasp
*mcasp
, u32 offset
,
115 void __iomem
*reg
= mcasp
->base
+ offset
;
116 __raw_writel(__raw_readl(reg
) | val
, reg
);
119 static inline void mcasp_clr_bits(struct davinci_mcasp
*mcasp
, u32 offset
,
122 void __iomem
*reg
= mcasp
->base
+ offset
;
123 __raw_writel((__raw_readl(reg
) & ~(val
)), reg
);
126 static inline void mcasp_mod_bits(struct davinci_mcasp
*mcasp
, u32 offset
,
129 void __iomem
*reg
= mcasp
->base
+ offset
;
130 __raw_writel((__raw_readl(reg
) & ~mask
) | val
, reg
);
133 static inline void mcasp_set_reg(struct davinci_mcasp
*mcasp
, u32 offset
,
136 __raw_writel(val
, mcasp
->base
+ offset
);
139 static inline u32
mcasp_get_reg(struct davinci_mcasp
*mcasp
, u32 offset
)
141 return (u32
)__raw_readl(mcasp
->base
+ offset
);
144 static void mcasp_set_ctl_reg(struct davinci_mcasp
*mcasp
, u32 ctl_reg
, u32 val
)
148 mcasp_set_bits(mcasp
, ctl_reg
, val
);
150 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
151 /* loop count is to avoid the lock-up */
152 for (i
= 0; i
< 1000; i
++) {
153 if ((mcasp_get_reg(mcasp
, ctl_reg
) & val
) == val
)
157 if (i
== 1000 && ((mcasp_get_reg(mcasp
, ctl_reg
) & val
) != val
))
158 printk(KERN_ERR
"GBLCTL write error\n");
161 static bool mcasp_is_synchronous(struct davinci_mcasp
*mcasp
)
163 u32 rxfmctl
= mcasp_get_reg(mcasp
, DAVINCI_MCASP_RXFMCTL_REG
);
164 u32 aclkxctl
= mcasp_get_reg(mcasp
, DAVINCI_MCASP_ACLKXCTL_REG
);
166 return !(aclkxctl
& TX_ASYNC
) && rxfmctl
& AFSRE
;
169 static void mcasp_start_rx(struct davinci_mcasp
*mcasp
)
171 if (mcasp
->rxnumevt
) { /* enable FIFO */
172 u32 reg
= mcasp
->fifo_base
+ MCASP_RFIFOCTL_OFFSET
;
174 mcasp_clr_bits(mcasp
, reg
, FIFO_ENABLE
);
175 mcasp_set_bits(mcasp
, reg
, FIFO_ENABLE
);
179 mcasp_set_ctl_reg(mcasp
, DAVINCI_MCASP_GBLCTLR_REG
, RXHCLKRST
);
180 mcasp_set_ctl_reg(mcasp
, DAVINCI_MCASP_GBLCTLR_REG
, RXCLKRST
);
182 * When ASYNC == 0 the transmit and receive sections operate
183 * synchronously from the transmit clock and frame sync. We need to make
184 * sure that the TX signlas are enabled when starting reception.
186 if (mcasp_is_synchronous(mcasp
)) {
187 mcasp_set_ctl_reg(mcasp
, DAVINCI_MCASP_GBLCTLX_REG
, TXHCLKRST
);
188 mcasp_set_ctl_reg(mcasp
, DAVINCI_MCASP_GBLCTLX_REG
, TXCLKRST
);
191 /* Activate serializer(s) */
192 mcasp_set_ctl_reg(mcasp
, DAVINCI_MCASP_GBLCTLR_REG
, RXSERCLR
);
193 /* Release RX state machine */
194 mcasp_set_ctl_reg(mcasp
, DAVINCI_MCASP_GBLCTLR_REG
, RXSMRST
);
195 /* Release Frame Sync generator */
196 mcasp_set_ctl_reg(mcasp
, DAVINCI_MCASP_GBLCTLR_REG
, RXFSRST
);
197 if (mcasp_is_synchronous(mcasp
))
198 mcasp_set_ctl_reg(mcasp
, DAVINCI_MCASP_GBLCTLX_REG
, TXFSRST
);
200 /* enable receive IRQs */
201 mcasp_set_bits(mcasp
, DAVINCI_MCASP_EVTCTLR_REG
,
202 mcasp
->irq_request
[SNDRV_PCM_STREAM_CAPTURE
]);
205 static void mcasp_start_tx(struct davinci_mcasp
*mcasp
)
209 if (mcasp
->txnumevt
) { /* enable FIFO */
210 u32 reg
= mcasp
->fifo_base
+ MCASP_WFIFOCTL_OFFSET
;
212 mcasp_clr_bits(mcasp
, reg
, FIFO_ENABLE
);
213 mcasp_set_bits(mcasp
, reg
, FIFO_ENABLE
);
217 mcasp_set_ctl_reg(mcasp
, DAVINCI_MCASP_GBLCTLX_REG
, TXHCLKRST
);
218 mcasp_set_ctl_reg(mcasp
, DAVINCI_MCASP_GBLCTLX_REG
, TXCLKRST
);
219 /* Activate serializer(s) */
220 mcasp_set_ctl_reg(mcasp
, DAVINCI_MCASP_GBLCTLX_REG
, TXSERCLR
);
222 /* wait for XDATA to be cleared */
224 while (!(mcasp_get_reg(mcasp
, DAVINCI_MCASP_TXSTAT_REG
) &
225 ~XRDATA
) && (cnt
< 100000))
228 /* Release TX state machine */
229 mcasp_set_ctl_reg(mcasp
, DAVINCI_MCASP_GBLCTLX_REG
, TXSMRST
);
230 /* Release Frame Sync generator */
231 mcasp_set_ctl_reg(mcasp
, DAVINCI_MCASP_GBLCTLX_REG
, TXFSRST
);
233 /* enable transmit IRQs */
234 mcasp_set_bits(mcasp
, DAVINCI_MCASP_EVTCTLX_REG
,
235 mcasp
->irq_request
[SNDRV_PCM_STREAM_PLAYBACK
]);
238 static void davinci_mcasp_start(struct davinci_mcasp
*mcasp
, int stream
)
242 if (stream
== SNDRV_PCM_STREAM_PLAYBACK
)
243 mcasp_start_tx(mcasp
);
245 mcasp_start_rx(mcasp
);
248 static void mcasp_stop_rx(struct davinci_mcasp
*mcasp
)
250 /* disable IRQ sources */
251 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_EVTCTLR_REG
,
252 mcasp
->irq_request
[SNDRV_PCM_STREAM_CAPTURE
]);
255 * In synchronous mode stop the TX clocks if no other stream is
258 if (mcasp_is_synchronous(mcasp
) && !mcasp
->streams
)
259 mcasp_set_reg(mcasp
, DAVINCI_MCASP_GBLCTLX_REG
, 0);
261 mcasp_set_reg(mcasp
, DAVINCI_MCASP_GBLCTLR_REG
, 0);
262 mcasp_set_reg(mcasp
, DAVINCI_MCASP_RXSTAT_REG
, 0xFFFFFFFF);
264 if (mcasp
->rxnumevt
) { /* disable FIFO */
265 u32 reg
= mcasp
->fifo_base
+ MCASP_RFIFOCTL_OFFSET
;
267 mcasp_clr_bits(mcasp
, reg
, FIFO_ENABLE
);
271 static void mcasp_stop_tx(struct davinci_mcasp
*mcasp
)
275 /* disable IRQ sources */
276 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_EVTCTLX_REG
,
277 mcasp
->irq_request
[SNDRV_PCM_STREAM_PLAYBACK
]);
280 * In synchronous mode keep TX clocks running if the capture stream is
283 if (mcasp_is_synchronous(mcasp
) && mcasp
->streams
)
284 val
= TXHCLKRST
| TXCLKRST
| TXFSRST
;
286 mcasp_set_reg(mcasp
, DAVINCI_MCASP_GBLCTLX_REG
, val
);
287 mcasp_set_reg(mcasp
, DAVINCI_MCASP_TXSTAT_REG
, 0xFFFFFFFF);
289 if (mcasp
->txnumevt
) { /* disable FIFO */
290 u32 reg
= mcasp
->fifo_base
+ MCASP_WFIFOCTL_OFFSET
;
292 mcasp_clr_bits(mcasp
, reg
, FIFO_ENABLE
);
296 static void davinci_mcasp_stop(struct davinci_mcasp
*mcasp
, int stream
)
300 if (stream
== SNDRV_PCM_STREAM_PLAYBACK
)
301 mcasp_stop_tx(mcasp
);
303 mcasp_stop_rx(mcasp
);
306 static irqreturn_t
davinci_mcasp_tx_irq_handler(int irq
, void *data
)
308 struct davinci_mcasp
*mcasp
= (struct davinci_mcasp
*)data
;
309 struct snd_pcm_substream
*substream
;
310 u32 irq_mask
= mcasp
->irq_request
[SNDRV_PCM_STREAM_PLAYBACK
];
311 u32 handled_mask
= 0;
314 stat
= mcasp_get_reg(mcasp
, DAVINCI_MCASP_TXSTAT_REG
);
315 if (stat
& XUNDRN
& irq_mask
) {
316 dev_warn(mcasp
->dev
, "Transmit buffer underflow\n");
317 handled_mask
|= XUNDRN
;
319 substream
= mcasp
->substreams
[SNDRV_PCM_STREAM_PLAYBACK
];
321 snd_pcm_stream_lock_irq(substream
);
322 if (snd_pcm_running(substream
))
323 snd_pcm_stop(substream
, SNDRV_PCM_STATE_XRUN
);
324 snd_pcm_stream_unlock_irq(substream
);
329 dev_warn(mcasp
->dev
, "unhandled tx event. txstat: 0x%08x\n",
333 handled_mask
|= XRERR
;
335 /* Ack the handled event only */
336 mcasp_set_reg(mcasp
, DAVINCI_MCASP_TXSTAT_REG
, handled_mask
);
338 return IRQ_RETVAL(handled_mask
);
341 static irqreturn_t
davinci_mcasp_rx_irq_handler(int irq
, void *data
)
343 struct davinci_mcasp
*mcasp
= (struct davinci_mcasp
*)data
;
344 struct snd_pcm_substream
*substream
;
345 u32 irq_mask
= mcasp
->irq_request
[SNDRV_PCM_STREAM_CAPTURE
];
346 u32 handled_mask
= 0;
349 stat
= mcasp_get_reg(mcasp
, DAVINCI_MCASP_RXSTAT_REG
);
350 if (stat
& ROVRN
& irq_mask
) {
351 dev_warn(mcasp
->dev
, "Receive buffer overflow\n");
352 handled_mask
|= ROVRN
;
354 substream
= mcasp
->substreams
[SNDRV_PCM_STREAM_CAPTURE
];
356 snd_pcm_stream_lock_irq(substream
);
357 if (snd_pcm_running(substream
))
358 snd_pcm_stop(substream
, SNDRV_PCM_STATE_XRUN
);
359 snd_pcm_stream_unlock_irq(substream
);
364 dev_warn(mcasp
->dev
, "unhandled rx event. rxstat: 0x%08x\n",
368 handled_mask
|= XRERR
;
370 /* Ack the handled event only */
371 mcasp_set_reg(mcasp
, DAVINCI_MCASP_RXSTAT_REG
, handled_mask
);
373 return IRQ_RETVAL(handled_mask
);
376 static irqreturn_t
davinci_mcasp_common_irq_handler(int irq
, void *data
)
378 struct davinci_mcasp
*mcasp
= (struct davinci_mcasp
*)data
;
379 irqreturn_t ret
= IRQ_NONE
;
381 if (mcasp
->substreams
[SNDRV_PCM_STREAM_PLAYBACK
])
382 ret
= davinci_mcasp_tx_irq_handler(irq
, data
);
384 if (mcasp
->substreams
[SNDRV_PCM_STREAM_CAPTURE
])
385 ret
|= davinci_mcasp_rx_irq_handler(irq
, data
);
390 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai
*cpu_dai
,
393 struct davinci_mcasp
*mcasp
= snd_soc_dai_get_drvdata(cpu_dai
);
399 pm_runtime_get_sync(mcasp
->dev
);
400 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
401 case SND_SOC_DAIFMT_DSP_A
:
402 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_TXFMCTL_REG
, FSXDUR
);
403 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_RXFMCTL_REG
, FSRDUR
);
404 /* 1st data bit occur one ACLK cycle after the frame sync */
407 case SND_SOC_DAIFMT_DSP_B
:
408 case SND_SOC_DAIFMT_AC97
:
409 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_TXFMCTL_REG
, FSXDUR
);
410 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_RXFMCTL_REG
, FSRDUR
);
411 /* No delay after FS */
414 case SND_SOC_DAIFMT_I2S
:
415 /* configure a full-word SYNC pulse (LRCLK) */
416 mcasp_set_bits(mcasp
, DAVINCI_MCASP_TXFMCTL_REG
, FSXDUR
);
417 mcasp_set_bits(mcasp
, DAVINCI_MCASP_RXFMCTL_REG
, FSRDUR
);
418 /* 1st data bit occur one ACLK cycle after the frame sync */
420 /* FS need to be inverted */
423 case SND_SOC_DAIFMT_LEFT_J
:
424 /* configure a full-word SYNC pulse (LRCLK) */
425 mcasp_set_bits(mcasp
, DAVINCI_MCASP_TXFMCTL_REG
, FSXDUR
);
426 mcasp_set_bits(mcasp
, DAVINCI_MCASP_RXFMCTL_REG
, FSRDUR
);
427 /* No delay after FS */
435 mcasp_mod_bits(mcasp
, DAVINCI_MCASP_TXFMT_REG
, FSXDLY(data_delay
),
437 mcasp_mod_bits(mcasp
, DAVINCI_MCASP_RXFMT_REG
, FSRDLY(data_delay
),
440 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
441 case SND_SOC_DAIFMT_CBS_CFS
:
442 /* codec is clock and frame slave */
443 mcasp_set_bits(mcasp
, DAVINCI_MCASP_ACLKXCTL_REG
, ACLKXE
);
444 mcasp_set_bits(mcasp
, DAVINCI_MCASP_TXFMCTL_REG
, AFSXE
);
446 mcasp_set_bits(mcasp
, DAVINCI_MCASP_ACLKRCTL_REG
, ACLKRE
);
447 mcasp_set_bits(mcasp
, DAVINCI_MCASP_RXFMCTL_REG
, AFSRE
);
449 mcasp_set_bits(mcasp
, DAVINCI_MCASP_PDIR_REG
, ACLKX
| ACLKR
);
450 mcasp_set_bits(mcasp
, DAVINCI_MCASP_PDIR_REG
, AFSX
| AFSR
);
451 mcasp
->bclk_master
= 1;
453 case SND_SOC_DAIFMT_CBS_CFM
:
454 /* codec is clock slave and frame master */
455 mcasp_set_bits(mcasp
, DAVINCI_MCASP_ACLKXCTL_REG
, ACLKXE
);
456 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_TXFMCTL_REG
, AFSXE
);
458 mcasp_set_bits(mcasp
, DAVINCI_MCASP_ACLKRCTL_REG
, ACLKRE
);
459 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_RXFMCTL_REG
, AFSRE
);
461 mcasp_set_bits(mcasp
, DAVINCI_MCASP_PDIR_REG
, ACLKX
| ACLKR
);
462 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_PDIR_REG
, AFSX
| AFSR
);
463 mcasp
->bclk_master
= 1;
465 case SND_SOC_DAIFMT_CBM_CFS
:
466 /* codec is clock master and frame slave */
467 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_ACLKXCTL_REG
, ACLKXE
);
468 mcasp_set_bits(mcasp
, DAVINCI_MCASP_TXFMCTL_REG
, AFSXE
);
470 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_ACLKRCTL_REG
, ACLKRE
);
471 mcasp_set_bits(mcasp
, DAVINCI_MCASP_RXFMCTL_REG
, AFSRE
);
473 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_PDIR_REG
, ACLKX
| ACLKR
);
474 mcasp_set_bits(mcasp
, DAVINCI_MCASP_PDIR_REG
, AFSX
| AFSR
);
475 mcasp
->bclk_master
= 0;
477 case SND_SOC_DAIFMT_CBM_CFM
:
478 /* codec is clock and frame master */
479 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_ACLKXCTL_REG
, ACLKXE
);
480 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_TXFMCTL_REG
, AFSXE
);
482 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_ACLKRCTL_REG
, ACLKRE
);
483 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_RXFMCTL_REG
, AFSRE
);
485 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_PDIR_REG
,
486 ACLKX
| AHCLKX
| AFSX
| ACLKR
| AHCLKR
| AFSR
);
487 mcasp
->bclk_master
= 0;
494 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
495 case SND_SOC_DAIFMT_IB_NF
:
496 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_ACLKXCTL_REG
, ACLKXPOL
);
497 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_ACLKRCTL_REG
, ACLKRPOL
);
498 fs_pol_rising
= true;
500 case SND_SOC_DAIFMT_NB_IF
:
501 mcasp_set_bits(mcasp
, DAVINCI_MCASP_ACLKXCTL_REG
, ACLKXPOL
);
502 mcasp_set_bits(mcasp
, DAVINCI_MCASP_ACLKRCTL_REG
, ACLKRPOL
);
503 fs_pol_rising
= false;
505 case SND_SOC_DAIFMT_IB_IF
:
506 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_ACLKXCTL_REG
, ACLKXPOL
);
507 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_ACLKRCTL_REG
, ACLKRPOL
);
508 fs_pol_rising
= false;
510 case SND_SOC_DAIFMT_NB_NF
:
511 mcasp_set_bits(mcasp
, DAVINCI_MCASP_ACLKXCTL_REG
, ACLKXPOL
);
512 mcasp_set_bits(mcasp
, DAVINCI_MCASP_ACLKRCTL_REG
, ACLKRPOL
);
513 fs_pol_rising
= true;
521 fs_pol_rising
= !fs_pol_rising
;
524 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_TXFMCTL_REG
, FSXPOL
);
525 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_RXFMCTL_REG
, FSRPOL
);
527 mcasp_set_bits(mcasp
, DAVINCI_MCASP_TXFMCTL_REG
, FSXPOL
);
528 mcasp_set_bits(mcasp
, DAVINCI_MCASP_RXFMCTL_REG
, FSRPOL
);
531 pm_runtime_put(mcasp
->dev
);
535 static int __davinci_mcasp_set_clkdiv(struct snd_soc_dai
*dai
, int div_id
,
536 int div
, bool explicit)
538 struct davinci_mcasp
*mcasp
= snd_soc_dai_get_drvdata(dai
);
540 pm_runtime_get_sync(mcasp
->dev
);
542 case 0: /* MCLK divider */
543 mcasp_mod_bits(mcasp
, DAVINCI_MCASP_AHCLKXCTL_REG
,
544 AHCLKXDIV(div
- 1), AHCLKXDIV_MASK
);
545 mcasp_mod_bits(mcasp
, DAVINCI_MCASP_AHCLKRCTL_REG
,
546 AHCLKRDIV(div
- 1), AHCLKRDIV_MASK
);
549 case 1: /* BCLK divider */
550 mcasp_mod_bits(mcasp
, DAVINCI_MCASP_ACLKXCTL_REG
,
551 ACLKXDIV(div
- 1), ACLKXDIV_MASK
);
552 mcasp_mod_bits(mcasp
, DAVINCI_MCASP_ACLKRCTL_REG
,
553 ACLKRDIV(div
- 1), ACLKRDIV_MASK
);
555 mcasp
->bclk_div
= div
;
558 case 2: /* BCLK/LRCLK ratio */
559 mcasp
->bclk_lrclk_ratio
= div
;
566 pm_runtime_put(mcasp
->dev
);
570 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai
*dai
, int div_id
,
573 return __davinci_mcasp_set_clkdiv(dai
, div_id
, div
, 1);
576 static int davinci_mcasp_set_sysclk(struct snd_soc_dai
*dai
, int clk_id
,
577 unsigned int freq
, int dir
)
579 struct davinci_mcasp
*mcasp
= snd_soc_dai_get_drvdata(dai
);
581 pm_runtime_get_sync(mcasp
->dev
);
582 if (dir
== SND_SOC_CLOCK_OUT
) {
583 mcasp_set_bits(mcasp
, DAVINCI_MCASP_AHCLKXCTL_REG
, AHCLKXE
);
584 mcasp_set_bits(mcasp
, DAVINCI_MCASP_AHCLKRCTL_REG
, AHCLKRE
);
585 mcasp_set_bits(mcasp
, DAVINCI_MCASP_PDIR_REG
, AHCLKX
);
587 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_AHCLKXCTL_REG
, AHCLKXE
);
588 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_AHCLKRCTL_REG
, AHCLKRE
);
589 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_PDIR_REG
, AHCLKX
);
592 mcasp
->sysclk_freq
= freq
;
594 pm_runtime_put(mcasp
->dev
);
598 static int davinci_config_channel_size(struct davinci_mcasp
*mcasp
,
602 u32 tx_rotate
= (word_length
/ 4) & 0x7;
603 u32 mask
= (1ULL << word_length
) - 1;
605 * For captured data we should not rotate, inversion and masking is
606 * enoguh to get the data to the right position:
607 * Format data from bus after reverse (XRBUF)
608 * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB|
609 * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
610 * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
611 * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB|
616 * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
617 * callback, take it into account here. That allows us to for example
618 * send 32 bits per channel to the codec, while only 16 of them carry
620 * The clock ratio is given for a full period of data (for I2S format
621 * both left and right channels), so it has to be divided by number of
622 * tdm-slots (for I2S - divided by 2).
624 if (mcasp
->bclk_lrclk_ratio
) {
625 u32 slot_length
= mcasp
->bclk_lrclk_ratio
/ mcasp
->tdm_slots
;
628 * When we have more bclk then it is needed for the data, we
629 * need to use the rotation to move the received samples to have
632 rx_rotate
= (slot_length
- word_length
) / 4;
633 word_length
= slot_length
;
636 /* mapping of the XSSZ bit-field as described in the datasheet */
637 fmt
= (word_length
>> 1) - 1;
639 if (mcasp
->op_mode
!= DAVINCI_MCASP_DIT_MODE
) {
640 mcasp_mod_bits(mcasp
, DAVINCI_MCASP_RXFMT_REG
, RXSSZ(fmt
),
642 mcasp_mod_bits(mcasp
, DAVINCI_MCASP_TXFMT_REG
, TXSSZ(fmt
),
644 mcasp_mod_bits(mcasp
, DAVINCI_MCASP_TXFMT_REG
, TXROT(tx_rotate
),
646 mcasp_mod_bits(mcasp
, DAVINCI_MCASP_RXFMT_REG
, RXROT(rx_rotate
),
648 mcasp_set_reg(mcasp
, DAVINCI_MCASP_RXMASK_REG
, mask
);
651 mcasp_set_reg(mcasp
, DAVINCI_MCASP_TXMASK_REG
, mask
);
656 static int mcasp_common_hw_param(struct davinci_mcasp
*mcasp
, int stream
,
657 int period_words
, int channels
)
659 struct snd_dmaengine_dai_dma_data
*dma_data
= &mcasp
->dma_data
[stream
];
663 u8 slots
= mcasp
->tdm_slots
;
664 u8 max_active_serializers
= (channels
+ slots
- 1) / slots
;
665 int active_serializers
, numevt
, n
;
667 /* Default configuration */
668 if (mcasp
->version
< MCASP_VERSION_3
)
669 mcasp_set_bits(mcasp
, DAVINCI_MCASP_PWREMUMGT_REG
, MCASP_SOFT
);
671 /* All PINS as McASP */
672 mcasp_set_reg(mcasp
, DAVINCI_MCASP_PFUNC_REG
, 0x00000000);
674 if (stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
675 mcasp_set_reg(mcasp
, DAVINCI_MCASP_TXSTAT_REG
, 0xFFFFFFFF);
676 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_XEVTCTL_REG
, TXDATADMADIS
);
678 mcasp_set_reg(mcasp
, DAVINCI_MCASP_RXSTAT_REG
, 0xFFFFFFFF);
679 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_REVTCTL_REG
, RXDATADMADIS
);
682 for (i
= 0; i
< mcasp
->num_serializer
; i
++) {
683 mcasp_set_bits(mcasp
, DAVINCI_MCASP_XRSRCTL_REG(i
),
684 mcasp
->serial_dir
[i
]);
685 if (mcasp
->serial_dir
[i
] == TX_MODE
&&
686 tx_ser
< max_active_serializers
) {
687 mcasp_set_bits(mcasp
, DAVINCI_MCASP_PDIR_REG
, AXR(i
));
689 } else if (mcasp
->serial_dir
[i
] == RX_MODE
&&
690 rx_ser
< max_active_serializers
) {
691 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_PDIR_REG
, AXR(i
));
694 mcasp_mod_bits(mcasp
, DAVINCI_MCASP_XRSRCTL_REG(i
),
695 SRMOD_INACTIVE
, SRMOD_MASK
);
699 if (stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
700 active_serializers
= tx_ser
;
701 numevt
= mcasp
->txnumevt
;
702 reg
= mcasp
->fifo_base
+ MCASP_WFIFOCTL_OFFSET
;
704 active_serializers
= rx_ser
;
705 numevt
= mcasp
->rxnumevt
;
706 reg
= mcasp
->fifo_base
+ MCASP_RFIFOCTL_OFFSET
;
709 if (active_serializers
< max_active_serializers
) {
710 dev_warn(mcasp
->dev
, "stream has more channels (%d) than are "
711 "enabled in mcasp (%d)\n", channels
,
712 active_serializers
* slots
);
716 /* AFIFO is not in use */
718 /* Configure the burst size for platform drivers */
719 if (active_serializers
> 1) {
721 * If more than one serializers are in use we have one
722 * DMA request to provide data for all serializers.
723 * For example if three serializers are enabled the DMA
724 * need to transfer three words per DMA request.
726 dma_data
->maxburst
= active_serializers
;
728 dma_data
->maxburst
= 0;
733 if (period_words
% active_serializers
) {
734 dev_err(mcasp
->dev
, "Invalid combination of period words and "
735 "active serializers: %d, %d\n", period_words
,
741 * Calculate the optimal AFIFO depth for platform side:
742 * The number of words for numevt need to be in steps of active
745 n
= numevt
% active_serializers
;
747 numevt
+= (active_serializers
- n
);
748 while (period_words
% numevt
&& numevt
> 0)
749 numevt
-= active_serializers
;
751 numevt
= active_serializers
;
753 mcasp_mod_bits(mcasp
, reg
, active_serializers
, NUMDMA_MASK
);
754 mcasp_mod_bits(mcasp
, reg
, NUMEVT(numevt
), NUMEVT_MASK
);
756 /* Configure the burst size for platform drivers */
759 dma_data
->maxburst
= numevt
;
764 static int mcasp_i2s_hw_param(struct davinci_mcasp
*mcasp
, int stream
,
769 int active_serializers
;
773 total_slots
= mcasp
->tdm_slots
;
776 * If more than one serializer is needed, then use them with
777 * their specified tdm_slots count. Otherwise, one serializer
778 * can cope with the transaction using as many slots as channels
779 * in the stream, requires channels symmetry
781 active_serializers
= (channels
+ total_slots
- 1) / total_slots
;
782 if (active_serializers
== 1)
783 active_slots
= channels
;
785 active_slots
= total_slots
;
787 for (i
= 0; i
< active_slots
; i
++)
790 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_ACLKXCTL_REG
, TX_ASYNC
);
792 if (!mcasp
->dat_port
)
795 mcasp_set_reg(mcasp
, DAVINCI_MCASP_TXTDM_REG
, mask
);
796 mcasp_set_bits(mcasp
, DAVINCI_MCASP_TXFMT_REG
, busel
| TXORD
);
797 mcasp_mod_bits(mcasp
, DAVINCI_MCASP_TXFMCTL_REG
,
798 FSXMOD(total_slots
), FSXMOD(0x1FF));
800 mcasp_set_reg(mcasp
, DAVINCI_MCASP_RXTDM_REG
, mask
);
801 mcasp_set_bits(mcasp
, DAVINCI_MCASP_RXFMT_REG
, busel
| RXORD
);
802 mcasp_mod_bits(mcasp
, DAVINCI_MCASP_RXFMCTL_REG
,
803 FSRMOD(total_slots
), FSRMOD(0x1FF));
809 static int mcasp_dit_hw_param(struct davinci_mcasp
*mcasp
,
813 u8
*cs_bytes
= (u8
*) &cs_value
;
815 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
817 mcasp_set_bits(mcasp
, DAVINCI_MCASP_TXFMT_REG
, TXROT(6) | TXSSZ(15));
819 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
820 mcasp_set_reg(mcasp
, DAVINCI_MCASP_TXFMCTL_REG
, AFSXE
| FSXMOD(0x180));
822 /* Set the TX tdm : for all the slots */
823 mcasp_set_reg(mcasp
, DAVINCI_MCASP_TXTDM_REG
, 0xFFFFFFFF);
825 /* Set the TX clock controls : div = 1 and internal */
826 mcasp_set_bits(mcasp
, DAVINCI_MCASP_ACLKXCTL_REG
, ACLKXE
| TX_ASYNC
);
828 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_XEVTCTL_REG
, TXDATADMADIS
);
830 /* Only 44100 and 48000 are valid, both have the same setting */
831 mcasp_set_bits(mcasp
, DAVINCI_MCASP_AHCLKXCTL_REG
, AHCLKXDIV(3));
834 mcasp_set_bits(mcasp
, DAVINCI_MCASP_TXDITCTL_REG
, DITEN
);
836 /* Set S/PDIF channel status bits */
837 cs_bytes
[0] = IEC958_AES0_CON_NOT_COPYRIGHT
;
838 cs_bytes
[1] = IEC958_AES1_CON_PCM_CODER
;
842 cs_bytes
[3] |= IEC958_AES3_CON_FS_22050
;
845 cs_bytes
[3] |= IEC958_AES3_CON_FS_24000
;
848 cs_bytes
[3] |= IEC958_AES3_CON_FS_32000
;
851 cs_bytes
[3] |= IEC958_AES3_CON_FS_44100
;
854 cs_bytes
[3] |= IEC958_AES3_CON_FS_48000
;
857 cs_bytes
[3] |= IEC958_AES3_CON_FS_88200
;
860 cs_bytes
[3] |= IEC958_AES3_CON_FS_96000
;
863 cs_bytes
[3] |= IEC958_AES3_CON_FS_176400
;
866 cs_bytes
[3] |= IEC958_AES3_CON_FS_192000
;
869 printk(KERN_WARNING
"unsupported sampling rate: %d\n", rate
);
873 mcasp_set_reg(mcasp
, DAVINCI_MCASP_DITCSRA_REG
, cs_value
);
874 mcasp_set_reg(mcasp
, DAVINCI_MCASP_DITCSRB_REG
, cs_value
);
879 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp
*mcasp
,
880 unsigned int bclk_freq
,
883 int div
= mcasp
->sysclk_freq
/ bclk_freq
;
884 int rem
= mcasp
->sysclk_freq
% bclk_freq
;
888 ((mcasp
->sysclk_freq
/ div
) - bclk_freq
) >
889 (bclk_freq
- (mcasp
->sysclk_freq
/ (div
+1)))) {
891 rem
= rem
- bclk_freq
;
896 (div
*1000000 + (int)div64_long(1000000LL*rem
,
903 static int davinci_mcasp_hw_params(struct snd_pcm_substream
*substream
,
904 struct snd_pcm_hw_params
*params
,
905 struct snd_soc_dai
*cpu_dai
)
907 struct davinci_mcasp
*mcasp
= snd_soc_dai_get_drvdata(cpu_dai
);
909 int channels
= params_channels(params
);
910 int period_size
= params_period_size(params
);
914 * If mcasp is BCLK master, and a BCLK divider was not provided by
915 * the machine driver, we need to calculate the ratio.
917 if (mcasp
->bclk_master
&& mcasp
->bclk_div
== 0 && mcasp
->sysclk_freq
) {
918 int channels
= params_channels(params
);
919 int rate
= params_rate(params
);
920 int sbits
= params_width(params
);
923 if (channels
> mcasp
->tdm_slots
)
924 channels
= mcasp
->tdm_slots
;
926 div
= davinci_mcasp_calc_clk_div(mcasp
, rate
*sbits
*channels
,
929 dev_info(mcasp
->dev
, "Sample-rate is off by %d PPM\n",
932 __davinci_mcasp_set_clkdiv(cpu_dai
, 1, div
, 0);
935 ret
= mcasp_common_hw_param(mcasp
, substream
->stream
,
936 period_size
* channels
, channels
);
940 if (mcasp
->op_mode
== DAVINCI_MCASP_DIT_MODE
)
941 ret
= mcasp_dit_hw_param(mcasp
, params_rate(params
));
943 ret
= mcasp_i2s_hw_param(mcasp
, substream
->stream
,
949 switch (params_format(params
)) {
950 case SNDRV_PCM_FORMAT_U8
:
951 case SNDRV_PCM_FORMAT_S8
:
955 case SNDRV_PCM_FORMAT_U16_LE
:
956 case SNDRV_PCM_FORMAT_S16_LE
:
960 case SNDRV_PCM_FORMAT_U24_3LE
:
961 case SNDRV_PCM_FORMAT_S24_3LE
:
965 case SNDRV_PCM_FORMAT_U24_LE
:
966 case SNDRV_PCM_FORMAT_S24_LE
:
970 case SNDRV_PCM_FORMAT_U32_LE
:
971 case SNDRV_PCM_FORMAT_S32_LE
:
976 printk(KERN_WARNING
"davinci-mcasp: unsupported PCM format");
980 davinci_config_channel_size(mcasp
, word_length
);
982 if (mcasp
->op_mode
== DAVINCI_MCASP_IIS_MODE
)
983 mcasp
->channels
= channels
;
988 static int davinci_mcasp_trigger(struct snd_pcm_substream
*substream
,
989 int cmd
, struct snd_soc_dai
*cpu_dai
)
991 struct davinci_mcasp
*mcasp
= snd_soc_dai_get_drvdata(cpu_dai
);
995 case SNDRV_PCM_TRIGGER_RESUME
:
996 case SNDRV_PCM_TRIGGER_START
:
997 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
998 davinci_mcasp_start(mcasp
, substream
->stream
);
1000 case SNDRV_PCM_TRIGGER_SUSPEND
:
1001 case SNDRV_PCM_TRIGGER_STOP
:
1002 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
1003 davinci_mcasp_stop(mcasp
, substream
->stream
);
1013 static const unsigned int davinci_mcasp_dai_rates
[] = {
1014 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1015 88200, 96000, 176400, 192000,
1018 #define DAVINCI_MAX_RATE_ERROR_PPM 1000
1020 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params
*params
,
1021 struct snd_pcm_hw_rule
*rule
)
1023 struct davinci_mcasp_ruledata
*rd
= rule
->private;
1024 struct snd_interval
*ri
=
1025 hw_param_interval(params
, SNDRV_PCM_HW_PARAM_RATE
);
1026 int sbits
= params_width(params
);
1027 int channels
= params_channels(params
);
1028 unsigned int list
[ARRAY_SIZE(davinci_mcasp_dai_rates
)];
1031 if (channels
> rd
->mcasp
->tdm_slots
)
1032 channels
= rd
->mcasp
->tdm_slots
;
1034 for (i
= 0; i
< ARRAY_SIZE(davinci_mcasp_dai_rates
); i
++) {
1035 if (ri
->min
<= davinci_mcasp_dai_rates
[i
] &&
1036 ri
->max
>= davinci_mcasp_dai_rates
[i
]) {
1037 uint bclk_freq
= sbits
*channels
*
1038 davinci_mcasp_dai_rates
[i
];
1041 davinci_mcasp_calc_clk_div(rd
->mcasp
, bclk_freq
, &ppm
);
1042 if (abs(ppm
) < DAVINCI_MAX_RATE_ERROR_PPM
)
1043 list
[count
++] = davinci_mcasp_dai_rates
[i
];
1046 dev_dbg(rd
->mcasp
->dev
,
1047 "%d frequencies (%d-%d) for %d sbits and %d channels\n",
1048 count
, ri
->min
, ri
->max
, sbits
, channels
);
1050 return snd_interval_list(hw_param_interval(params
, rule
->var
),
1054 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params
*params
,
1055 struct snd_pcm_hw_rule
*rule
)
1057 struct davinci_mcasp_ruledata
*rd
= rule
->private;
1058 struct snd_mask
*fmt
= hw_param_mask(params
, SNDRV_PCM_HW_PARAM_FORMAT
);
1059 struct snd_mask nfmt
;
1060 int rate
= params_rate(params
);
1061 int channels
= params_channels(params
);
1064 snd_mask_none(&nfmt
);
1066 if (channels
> rd
->mcasp
->tdm_slots
)
1067 channels
= rd
->mcasp
->tdm_slots
;
1069 for (i
= 0; i
< SNDRV_PCM_FORMAT_LAST
; i
++) {
1070 if (snd_mask_test(fmt
, i
)) {
1071 uint bclk_freq
= snd_pcm_format_width(i
)*channels
*rate
;
1074 davinci_mcasp_calc_clk_div(rd
->mcasp
, bclk_freq
, &ppm
);
1075 if (abs(ppm
) < DAVINCI_MAX_RATE_ERROR_PPM
) {
1076 snd_mask_set(&nfmt
, i
);
1081 dev_dbg(rd
->mcasp
->dev
,
1082 "%d possible sample format for %d Hz and %d channels\n",
1083 count
, rate
, channels
);
1085 return snd_mask_refine(fmt
, &nfmt
);
1088 static int davinci_mcasp_hw_rule_channels(struct snd_pcm_hw_params
*params
,
1089 struct snd_pcm_hw_rule
*rule
)
1091 struct davinci_mcasp_ruledata
*rd
= rule
->private;
1092 struct snd_interval
*ci
=
1093 hw_param_interval(params
, SNDRV_PCM_HW_PARAM_CHANNELS
);
1094 int sbits
= params_width(params
);
1095 int rate
= params_rate(params
);
1096 int max_chan_per_wire
= rd
->mcasp
->tdm_slots
< ci
->max
?
1097 rd
->mcasp
->tdm_slots
: ci
->max
;
1098 unsigned int list
[ci
->max
- ci
->min
+ 1];
1099 int c1
, c
, count
= 0;
1101 for (c1
= ci
->min
; c1
<= max_chan_per_wire
; c1
++) {
1102 uint bclk_freq
= c1
*sbits
*rate
;
1105 davinci_mcasp_calc_clk_div(rd
->mcasp
, bclk_freq
, &ppm
);
1106 if (abs(ppm
) < DAVINCI_MAX_RATE_ERROR_PPM
) {
1107 /* If we can use all tdm_slots, we can put any
1108 amount of channels to remaining wires as
1109 long as they fit in. */
1110 if (c1
== rd
->mcasp
->tdm_slots
) {
1111 for (c
= c1
; c
<= rd
->serializers
*c1
&&
1119 dev_dbg(rd
->mcasp
->dev
,
1120 "%d possible channel counts (%d-%d) for %d Hz and %d sbits\n",
1121 count
, ci
->min
, ci
->max
, rate
, sbits
);
1123 return snd_interval_list(hw_param_interval(params
, rule
->var
),
1127 static int davinci_mcasp_startup(struct snd_pcm_substream
*substream
,
1128 struct snd_soc_dai
*cpu_dai
)
1130 struct davinci_mcasp
*mcasp
= snd_soc_dai_get_drvdata(cpu_dai
);
1131 struct davinci_mcasp_ruledata
*ruledata
=
1132 &mcasp
->ruledata
[substream
->stream
];
1133 u32 max_channels
= 0;
1136 mcasp
->substreams
[substream
->stream
] = substream
;
1138 if (mcasp
->op_mode
== DAVINCI_MCASP_DIT_MODE
)
1142 * Limit the maximum allowed channels for the first stream:
1143 * number of serializers for the direction * tdm slots per serializer
1145 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
1150 for (i
= 0; i
< mcasp
->num_serializer
; i
++) {
1151 if (mcasp
->serial_dir
[i
] == dir
)
1154 ruledata
->serializers
= max_channels
;
1155 max_channels
*= mcasp
->tdm_slots
;
1157 * If the already active stream has less channels than the calculated
1158 * limnit based on the seirializers * tdm_slots, we need to use that as
1159 * a constraint for the second stream.
1160 * Otherwise (first stream or less allowed channels) we use the
1161 * calculated constraint.
1163 if (mcasp
->channels
&& mcasp
->channels
< max_channels
)
1164 max_channels
= mcasp
->channels
;
1166 snd_pcm_hw_constraint_minmax(substream
->runtime
,
1167 SNDRV_PCM_HW_PARAM_CHANNELS
,
1171 * If we rely on implicit BCLK divider setting we should
1172 * set constraints based on what we can provide.
1174 if (mcasp
->bclk_master
&& mcasp
->bclk_div
== 0 && mcasp
->sysclk_freq
) {
1177 ruledata
->mcasp
= mcasp
;
1179 ret
= snd_pcm_hw_rule_add(substream
->runtime
, 0,
1180 SNDRV_PCM_HW_PARAM_RATE
,
1181 davinci_mcasp_hw_rule_rate
,
1183 SNDRV_PCM_HW_PARAM_FORMAT
,
1184 SNDRV_PCM_HW_PARAM_CHANNELS
, -1);
1187 ret
= snd_pcm_hw_rule_add(substream
->runtime
, 0,
1188 SNDRV_PCM_HW_PARAM_FORMAT
,
1189 davinci_mcasp_hw_rule_format
,
1191 SNDRV_PCM_HW_PARAM_RATE
,
1192 SNDRV_PCM_HW_PARAM_CHANNELS
, -1);
1195 ret
= snd_pcm_hw_rule_add(substream
->runtime
, 0,
1196 SNDRV_PCM_HW_PARAM_CHANNELS
,
1197 davinci_mcasp_hw_rule_channels
,
1199 SNDRV_PCM_HW_PARAM_RATE
,
1200 SNDRV_PCM_HW_PARAM_FORMAT
, -1);
1208 static void davinci_mcasp_shutdown(struct snd_pcm_substream
*substream
,
1209 struct snd_soc_dai
*cpu_dai
)
1211 struct davinci_mcasp
*mcasp
= snd_soc_dai_get_drvdata(cpu_dai
);
1213 mcasp
->substreams
[substream
->stream
] = NULL
;
1215 if (mcasp
->op_mode
== DAVINCI_MCASP_DIT_MODE
)
1218 if (!cpu_dai
->active
)
1219 mcasp
->channels
= 0;
1222 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops
= {
1223 .startup
= davinci_mcasp_startup
,
1224 .shutdown
= davinci_mcasp_shutdown
,
1225 .trigger
= davinci_mcasp_trigger
,
1226 .hw_params
= davinci_mcasp_hw_params
,
1227 .set_fmt
= davinci_mcasp_set_dai_fmt
,
1228 .set_clkdiv
= davinci_mcasp_set_clkdiv
,
1229 .set_sysclk
= davinci_mcasp_set_sysclk
,
1232 static int davinci_mcasp_dai_probe(struct snd_soc_dai
*dai
)
1234 struct davinci_mcasp
*mcasp
= snd_soc_dai_get_drvdata(dai
);
1236 dai
->playback_dma_data
= &mcasp
->dma_data
[SNDRV_PCM_STREAM_PLAYBACK
];
1237 dai
->capture_dma_data
= &mcasp
->dma_data
[SNDRV_PCM_STREAM_CAPTURE
];
1242 #ifdef CONFIG_PM_SLEEP
1243 static int davinci_mcasp_suspend(struct snd_soc_dai
*dai
)
1245 struct davinci_mcasp
*mcasp
= snd_soc_dai_get_drvdata(dai
);
1246 struct davinci_mcasp_context
*context
= &mcasp
->context
;
1250 context
->pm_state
= pm_runtime_enabled(mcasp
->dev
);
1251 if (!context
->pm_state
)
1252 pm_runtime_get_sync(mcasp
->dev
);
1254 for (i
= 0; i
< ARRAY_SIZE(context_regs
); i
++)
1255 context
->config_regs
[i
] = mcasp_get_reg(mcasp
, context_regs
[i
]);
1257 if (mcasp
->txnumevt
) {
1258 reg
= mcasp
->fifo_base
+ MCASP_WFIFOCTL_OFFSET
;
1259 context
->afifo_regs
[0] = mcasp_get_reg(mcasp
, reg
);
1261 if (mcasp
->rxnumevt
) {
1262 reg
= mcasp
->fifo_base
+ MCASP_RFIFOCTL_OFFSET
;
1263 context
->afifo_regs
[1] = mcasp_get_reg(mcasp
, reg
);
1266 for (i
= 0; i
< mcasp
->num_serializer
; i
++)
1267 context
->xrsr_regs
[i
] = mcasp_get_reg(mcasp
,
1268 DAVINCI_MCASP_XRSRCTL_REG(i
));
1270 pm_runtime_put_sync(mcasp
->dev
);
1275 static int davinci_mcasp_resume(struct snd_soc_dai
*dai
)
1277 struct davinci_mcasp
*mcasp
= snd_soc_dai_get_drvdata(dai
);
1278 struct davinci_mcasp_context
*context
= &mcasp
->context
;
1282 pm_runtime_get_sync(mcasp
->dev
);
1284 for (i
= 0; i
< ARRAY_SIZE(context_regs
); i
++)
1285 mcasp_set_reg(mcasp
, context_regs
[i
], context
->config_regs
[i
]);
1287 if (mcasp
->txnumevt
) {
1288 reg
= mcasp
->fifo_base
+ MCASP_WFIFOCTL_OFFSET
;
1289 mcasp_set_reg(mcasp
, reg
, context
->afifo_regs
[0]);
1291 if (mcasp
->rxnumevt
) {
1292 reg
= mcasp
->fifo_base
+ MCASP_RFIFOCTL_OFFSET
;
1293 mcasp_set_reg(mcasp
, reg
, context
->afifo_regs
[1]);
1296 for (i
= 0; i
< mcasp
->num_serializer
; i
++)
1297 mcasp_set_reg(mcasp
, DAVINCI_MCASP_XRSRCTL_REG(i
),
1298 context
->xrsr_regs
[i
]);
1300 if (!context
->pm_state
)
1301 pm_runtime_put_sync(mcasp
->dev
);
1306 #define davinci_mcasp_suspend NULL
1307 #define davinci_mcasp_resume NULL
1310 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
1312 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1313 SNDRV_PCM_FMTBIT_U8 | \
1314 SNDRV_PCM_FMTBIT_S16_LE | \
1315 SNDRV_PCM_FMTBIT_U16_LE | \
1316 SNDRV_PCM_FMTBIT_S24_LE | \
1317 SNDRV_PCM_FMTBIT_U24_LE | \
1318 SNDRV_PCM_FMTBIT_S24_3LE | \
1319 SNDRV_PCM_FMTBIT_U24_3LE | \
1320 SNDRV_PCM_FMTBIT_S32_LE | \
1321 SNDRV_PCM_FMTBIT_U32_LE)
1323 static struct snd_soc_dai_driver davinci_mcasp_dai
[] = {
1325 .name
= "davinci-mcasp.0",
1326 .probe
= davinci_mcasp_dai_probe
,
1327 .suspend
= davinci_mcasp_suspend
,
1328 .resume
= davinci_mcasp_resume
,
1331 .channels_max
= 32 * 16,
1332 .rates
= DAVINCI_MCASP_RATES
,
1333 .formats
= DAVINCI_MCASP_PCM_FMTS
,
1337 .channels_max
= 32 * 16,
1338 .rates
= DAVINCI_MCASP_RATES
,
1339 .formats
= DAVINCI_MCASP_PCM_FMTS
,
1341 .ops
= &davinci_mcasp_dai_ops
,
1343 .symmetric_samplebits
= 1,
1346 .name
= "davinci-mcasp.1",
1347 .probe
= davinci_mcasp_dai_probe
,
1350 .channels_max
= 384,
1351 .rates
= DAVINCI_MCASP_RATES
,
1352 .formats
= DAVINCI_MCASP_PCM_FMTS
,
1354 .ops
= &davinci_mcasp_dai_ops
,
1359 static const struct snd_soc_component_driver davinci_mcasp_component
= {
1360 .name
= "davinci-mcasp",
1363 /* Some HW specific values and defaults. The rest is filled in from DT. */
1364 static struct davinci_mcasp_pdata dm646x_mcasp_pdata
= {
1365 .tx_dma_offset
= 0x400,
1366 .rx_dma_offset
= 0x400,
1367 .version
= MCASP_VERSION_1
,
1370 static struct davinci_mcasp_pdata da830_mcasp_pdata
= {
1371 .tx_dma_offset
= 0x2000,
1372 .rx_dma_offset
= 0x2000,
1373 .version
= MCASP_VERSION_2
,
1376 static struct davinci_mcasp_pdata am33xx_mcasp_pdata
= {
1379 .version
= MCASP_VERSION_3
,
1382 static struct davinci_mcasp_pdata dra7_mcasp_pdata
= {
1383 .tx_dma_offset
= 0x200,
1384 .rx_dma_offset
= 0x284,
1385 .version
= MCASP_VERSION_4
,
1388 static const struct of_device_id mcasp_dt_ids
[] = {
1390 .compatible
= "ti,dm646x-mcasp-audio",
1391 .data
= &dm646x_mcasp_pdata
,
1394 .compatible
= "ti,da830-mcasp-audio",
1395 .data
= &da830_mcasp_pdata
,
1398 .compatible
= "ti,am33xx-mcasp-audio",
1399 .data
= &am33xx_mcasp_pdata
,
1402 .compatible
= "ti,dra7-mcasp-audio",
1403 .data
= &dra7_mcasp_pdata
,
1407 MODULE_DEVICE_TABLE(of
, mcasp_dt_ids
);
1409 static int mcasp_reparent_fck(struct platform_device
*pdev
)
1411 struct device_node
*node
= pdev
->dev
.of_node
;
1412 struct clk
*gfclk
, *parent_clk
;
1413 const char *parent_name
;
1419 parent_name
= of_get_property(node
, "fck_parent", NULL
);
1423 gfclk
= clk_get(&pdev
->dev
, "fck");
1424 if (IS_ERR(gfclk
)) {
1425 dev_err(&pdev
->dev
, "failed to get fck\n");
1426 return PTR_ERR(gfclk
);
1429 parent_clk
= clk_get(NULL
, parent_name
);
1430 if (IS_ERR(parent_clk
)) {
1431 dev_err(&pdev
->dev
, "failed to get parent clock\n");
1432 ret
= PTR_ERR(parent_clk
);
1436 ret
= clk_set_parent(gfclk
, parent_clk
);
1438 dev_err(&pdev
->dev
, "failed to reparent fck\n");
1443 clk_put(parent_clk
);
1449 static struct davinci_mcasp_pdata
*davinci_mcasp_set_pdata_from_of(
1450 struct platform_device
*pdev
)
1452 struct device_node
*np
= pdev
->dev
.of_node
;
1453 struct davinci_mcasp_pdata
*pdata
= NULL
;
1454 const struct of_device_id
*match
=
1455 of_match_device(mcasp_dt_ids
, &pdev
->dev
);
1456 struct of_phandle_args dma_spec
;
1458 const u32
*of_serial_dir32
;
1462 if (pdev
->dev
.platform_data
) {
1463 pdata
= pdev
->dev
.platform_data
;
1466 pdata
= (struct davinci_mcasp_pdata
*) match
->data
;
1468 /* control shouldn't reach here. something is wrong */
1473 ret
= of_property_read_u32(np
, "op-mode", &val
);
1475 pdata
->op_mode
= val
;
1477 ret
= of_property_read_u32(np
, "tdm-slots", &val
);
1479 if (val
< 2 || val
> 32) {
1481 "tdm-slots must be in rage [2-32]\n");
1486 pdata
->tdm_slots
= val
;
1489 of_serial_dir32
= of_get_property(np
, "serial-dir", &val
);
1491 if (of_serial_dir32
) {
1492 u8
*of_serial_dir
= devm_kzalloc(&pdev
->dev
,
1493 (sizeof(*of_serial_dir
) * val
),
1495 if (!of_serial_dir
) {
1500 for (i
= 0; i
< val
; i
++)
1501 of_serial_dir
[i
] = be32_to_cpup(&of_serial_dir32
[i
]);
1503 pdata
->num_serializer
= val
;
1504 pdata
->serial_dir
= of_serial_dir
;
1507 ret
= of_property_match_string(np
, "dma-names", "tx");
1511 ret
= of_parse_phandle_with_args(np
, "dmas", "#dma-cells", ret
,
1516 pdata
->tx_dma_channel
= dma_spec
.args
[0];
1518 /* RX is not valid in DIT mode */
1519 if (pdata
->op_mode
!= DAVINCI_MCASP_DIT_MODE
) {
1520 ret
= of_property_match_string(np
, "dma-names", "rx");
1524 ret
= of_parse_phandle_with_args(np
, "dmas", "#dma-cells", ret
,
1529 pdata
->rx_dma_channel
= dma_spec
.args
[0];
1532 ret
= of_property_read_u32(np
, "tx-num-evt", &val
);
1534 pdata
->txnumevt
= val
;
1536 ret
= of_property_read_u32(np
, "rx-num-evt", &val
);
1538 pdata
->rxnumevt
= val
;
1540 ret
= of_property_read_u32(np
, "sram-size-playback", &val
);
1542 pdata
->sram_size_playback
= val
;
1544 ret
= of_property_read_u32(np
, "sram-size-capture", &val
);
1546 pdata
->sram_size_capture
= val
;
1552 dev_err(&pdev
->dev
, "Error populating platform data, err %d\n",
1559 static int davinci_mcasp_probe(struct platform_device
*pdev
)
1561 struct snd_dmaengine_dai_dma_data
*dma_data
;
1562 struct resource
*mem
, *ioarea
, *res
, *dat
;
1563 struct davinci_mcasp_pdata
*pdata
;
1564 struct davinci_mcasp
*mcasp
;
1570 if (!pdev
->dev
.platform_data
&& !pdev
->dev
.of_node
) {
1571 dev_err(&pdev
->dev
, "No platform data supplied\n");
1575 mcasp
= devm_kzalloc(&pdev
->dev
, sizeof(struct davinci_mcasp
),
1580 pdata
= davinci_mcasp_set_pdata_from_of(pdev
);
1582 dev_err(&pdev
->dev
, "no platform data\n");
1586 mem
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "mpu");
1588 dev_warn(mcasp
->dev
,
1589 "\"mpu\" mem resource not found, using index 0\n");
1590 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1592 dev_err(&pdev
->dev
, "no mem resource?\n");
1597 ioarea
= devm_request_mem_region(&pdev
->dev
, mem
->start
,
1598 resource_size(mem
), pdev
->name
);
1600 dev_err(&pdev
->dev
, "Audio region already claimed\n");
1604 pm_runtime_enable(&pdev
->dev
);
1606 mcasp
->base
= devm_ioremap(&pdev
->dev
, mem
->start
, resource_size(mem
));
1608 dev_err(&pdev
->dev
, "ioremap failed\n");
1613 mcasp
->op_mode
= pdata
->op_mode
;
1614 /* sanity check for tdm slots parameter */
1615 if (mcasp
->op_mode
== DAVINCI_MCASP_IIS_MODE
) {
1616 if (pdata
->tdm_slots
< 2) {
1617 dev_err(&pdev
->dev
, "invalid tdm slots: %d\n",
1619 mcasp
->tdm_slots
= 2;
1620 } else if (pdata
->tdm_slots
> 32) {
1621 dev_err(&pdev
->dev
, "invalid tdm slots: %d\n",
1623 mcasp
->tdm_slots
= 32;
1625 mcasp
->tdm_slots
= pdata
->tdm_slots
;
1629 mcasp
->num_serializer
= pdata
->num_serializer
;
1630 #ifdef CONFIG_PM_SLEEP
1631 mcasp
->context
.xrsr_regs
= devm_kzalloc(&pdev
->dev
,
1632 sizeof(u32
) * mcasp
->num_serializer
,
1635 mcasp
->serial_dir
= pdata
->serial_dir
;
1636 mcasp
->version
= pdata
->version
;
1637 mcasp
->txnumevt
= pdata
->txnumevt
;
1638 mcasp
->rxnumevt
= pdata
->rxnumevt
;
1640 mcasp
->dev
= &pdev
->dev
;
1642 irq
= platform_get_irq_byname(pdev
, "common");
1644 irq_name
= devm_kasprintf(&pdev
->dev
, GFP_KERNEL
, "%s_common\n",
1645 dev_name(&pdev
->dev
));
1646 ret
= devm_request_threaded_irq(&pdev
->dev
, irq
, NULL
,
1647 davinci_mcasp_common_irq_handler
,
1648 IRQF_ONESHOT
| IRQF_SHARED
,
1651 dev_err(&pdev
->dev
, "common IRQ request failed\n");
1655 mcasp
->irq_request
[SNDRV_PCM_STREAM_PLAYBACK
] = XUNDRN
;
1656 mcasp
->irq_request
[SNDRV_PCM_STREAM_CAPTURE
] = ROVRN
;
1659 irq
= platform_get_irq_byname(pdev
, "rx");
1661 irq_name
= devm_kasprintf(&pdev
->dev
, GFP_KERNEL
, "%s_rx\n",
1662 dev_name(&pdev
->dev
));
1663 ret
= devm_request_threaded_irq(&pdev
->dev
, irq
, NULL
,
1664 davinci_mcasp_rx_irq_handler
,
1665 IRQF_ONESHOT
, irq_name
, mcasp
);
1667 dev_err(&pdev
->dev
, "RX IRQ request failed\n");
1671 mcasp
->irq_request
[SNDRV_PCM_STREAM_CAPTURE
] = ROVRN
;
1674 irq
= platform_get_irq_byname(pdev
, "tx");
1676 irq_name
= devm_kasprintf(&pdev
->dev
, GFP_KERNEL
, "%s_tx\n",
1677 dev_name(&pdev
->dev
));
1678 ret
= devm_request_threaded_irq(&pdev
->dev
, irq
, NULL
,
1679 davinci_mcasp_tx_irq_handler
,
1680 IRQF_ONESHOT
, irq_name
, mcasp
);
1682 dev_err(&pdev
->dev
, "TX IRQ request failed\n");
1686 mcasp
->irq_request
[SNDRV_PCM_STREAM_PLAYBACK
] = XUNDRN
;
1689 dat
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "dat");
1691 mcasp
->dat_port
= true;
1693 dma_data
= &mcasp
->dma_data
[SNDRV_PCM_STREAM_PLAYBACK
];
1695 dma_data
->addr
= dat
->start
;
1697 dma_data
->addr
= mem
->start
+ pdata
->tx_dma_offset
;
1699 dma
= &mcasp
->dma_request
[SNDRV_PCM_STREAM_PLAYBACK
];
1700 res
= platform_get_resource(pdev
, IORESOURCE_DMA
, 0);
1704 *dma
= pdata
->tx_dma_channel
;
1706 /* dmaengine filter data for DT and non-DT boot */
1707 if (pdev
->dev
.of_node
)
1708 dma_data
->filter_data
= "tx";
1710 dma_data
->filter_data
= dma
;
1712 /* RX is not valid in DIT mode */
1713 if (mcasp
->op_mode
!= DAVINCI_MCASP_DIT_MODE
) {
1714 dma_data
= &mcasp
->dma_data
[SNDRV_PCM_STREAM_CAPTURE
];
1716 dma_data
->addr
= dat
->start
;
1718 dma_data
->addr
= mem
->start
+ pdata
->rx_dma_offset
;
1720 dma
= &mcasp
->dma_request
[SNDRV_PCM_STREAM_CAPTURE
];
1721 res
= platform_get_resource(pdev
, IORESOURCE_DMA
, 1);
1725 *dma
= pdata
->rx_dma_channel
;
1727 /* dmaengine filter data for DT and non-DT boot */
1728 if (pdev
->dev
.of_node
)
1729 dma_data
->filter_data
= "rx";
1731 dma_data
->filter_data
= dma
;
1734 if (mcasp
->version
< MCASP_VERSION_3
) {
1735 mcasp
->fifo_base
= DAVINCI_MCASP_V2_AFIFO_BASE
;
1736 /* dma_params->dma_addr is pointing to the data port address */
1737 mcasp
->dat_port
= true;
1739 mcasp
->fifo_base
= DAVINCI_MCASP_V3_AFIFO_BASE
;
1742 dev_set_drvdata(&pdev
->dev
, mcasp
);
1744 mcasp_reparent_fck(pdev
);
1746 ret
= devm_snd_soc_register_component(&pdev
->dev
,
1747 &davinci_mcasp_component
,
1748 &davinci_mcasp_dai
[pdata
->op_mode
], 1);
1753 switch (mcasp
->version
) {
1754 #if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \
1755 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1756 IS_MODULE(CONFIG_SND_EDMA_SOC))
1757 case MCASP_VERSION_1
:
1758 case MCASP_VERSION_2
:
1759 case MCASP_VERSION_3
:
1760 ret
= edma_pcm_platform_register(&pdev
->dev
);
1763 #if IS_BUILTIN(CONFIG_SND_OMAP_SOC) || \
1764 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1765 IS_MODULE(CONFIG_SND_OMAP_SOC))
1766 case MCASP_VERSION_4
:
1767 ret
= omap_pcm_platform_register(&pdev
->dev
);
1771 dev_err(&pdev
->dev
, "Invalid McASP version: %d\n",
1778 dev_err(&pdev
->dev
, "register PCM failed: %d\n", ret
);
1785 pm_runtime_disable(&pdev
->dev
);
1789 static int davinci_mcasp_remove(struct platform_device
*pdev
)
1791 pm_runtime_disable(&pdev
->dev
);
1796 static struct platform_driver davinci_mcasp_driver
= {
1797 .probe
= davinci_mcasp_probe
,
1798 .remove
= davinci_mcasp_remove
,
1800 .name
= "davinci-mcasp",
1801 .of_match_table
= mcasp_dt_ids
,
1805 module_platform_driver(davinci_mcasp_driver
);
1807 MODULE_AUTHOR("Steve Chen");
1808 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1809 MODULE_LICENSE("GPL");