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ASoC: DaVinci: McASP driver enhacements
[deliverable/linux.git] / sound / soc / davinci / davinci-mcasp.c
1 /*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/delay.h>
22 #include <linux/io.h>
23 #include <linux/clk.h>
24
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/initval.h>
29 #include <sound/soc.h>
30
31 #include "davinci-pcm.h"
32 #include "davinci-mcasp.h"
33
34 /*
35 * McASP register definitions
36 */
37 #define DAVINCI_MCASP_PID_REG 0x00
38 #define DAVINCI_MCASP_PWREMUMGT_REG 0x04
39
40 #define DAVINCI_MCASP_PFUNC_REG 0x10
41 #define DAVINCI_MCASP_PDIR_REG 0x14
42 #define DAVINCI_MCASP_PDOUT_REG 0x18
43 #define DAVINCI_MCASP_PDSET_REG 0x1c
44
45 #define DAVINCI_MCASP_PDCLR_REG 0x20
46
47 #define DAVINCI_MCASP_TLGC_REG 0x30
48 #define DAVINCI_MCASP_TLMR_REG 0x34
49
50 #define DAVINCI_MCASP_GBLCTL_REG 0x44
51 #define DAVINCI_MCASP_AMUTE_REG 0x48
52 #define DAVINCI_MCASP_LBCTL_REG 0x4c
53
54 #define DAVINCI_MCASP_TXDITCTL_REG 0x50
55
56 #define DAVINCI_MCASP_GBLCTLR_REG 0x60
57 #define DAVINCI_MCASP_RXMASK_REG 0x64
58 #define DAVINCI_MCASP_RXFMT_REG 0x68
59 #define DAVINCI_MCASP_RXFMCTL_REG 0x6c
60
61 #define DAVINCI_MCASP_ACLKRCTL_REG 0x70
62 #define DAVINCI_MCASP_AHCLKRCTL_REG 0x74
63 #define DAVINCI_MCASP_RXTDM_REG 0x78
64 #define DAVINCI_MCASP_EVTCTLR_REG 0x7c
65
66 #define DAVINCI_MCASP_RXSTAT_REG 0x80
67 #define DAVINCI_MCASP_RXTDMSLOT_REG 0x84
68 #define DAVINCI_MCASP_RXCLKCHK_REG 0x88
69 #define DAVINCI_MCASP_REVTCTL_REG 0x8c
70
71 #define DAVINCI_MCASP_GBLCTLX_REG 0xa0
72 #define DAVINCI_MCASP_TXMASK_REG 0xa4
73 #define DAVINCI_MCASP_TXFMT_REG 0xa8
74 #define DAVINCI_MCASP_TXFMCTL_REG 0xac
75
76 #define DAVINCI_MCASP_ACLKXCTL_REG 0xb0
77 #define DAVINCI_MCASP_AHCLKXCTL_REG 0xb4
78 #define DAVINCI_MCASP_TXTDM_REG 0xb8
79 #define DAVINCI_MCASP_EVTCTLX_REG 0xbc
80
81 #define DAVINCI_MCASP_TXSTAT_REG 0xc0
82 #define DAVINCI_MCASP_TXTDMSLOT_REG 0xc4
83 #define DAVINCI_MCASP_TXCLKCHK_REG 0xc8
84 #define DAVINCI_MCASP_XEVTCTL_REG 0xcc
85
86 /* Left(even TDM Slot) Channel Status Register File */
87 #define DAVINCI_MCASP_DITCSRA_REG 0x100
88 /* Right(odd TDM slot) Channel Status Register File */
89 #define DAVINCI_MCASP_DITCSRB_REG 0x118
90 /* Left(even TDM slot) User Data Register File */
91 #define DAVINCI_MCASP_DITUDRA_REG 0x130
92 /* Right(odd TDM Slot) User Data Register File */
93 #define DAVINCI_MCASP_DITUDRB_REG 0x148
94
95 /* Serializer n Control Register */
96 #define DAVINCI_MCASP_XRSRCTL_BASE_REG 0x180
97 #define DAVINCI_MCASP_XRSRCTL_REG(n) (DAVINCI_MCASP_XRSRCTL_BASE_REG + \
98 (n << 2))
99
100 /* Transmit Buffer for Serializer n */
101 #define DAVINCI_MCASP_TXBUF_REG 0x200
102 /* Receive Buffer for Serializer n */
103 #define DAVINCI_MCASP_RXBUF_REG 0x280
104
105 /* McASP FIFO Registers */
106 #define DAVINCI_MCASP_WFIFOCTL (0x1010)
107 #define DAVINCI_MCASP_WFIFOSTS (0x1014)
108 #define DAVINCI_MCASP_RFIFOCTL (0x1018)
109 #define DAVINCI_MCASP_RFIFOSTS (0x101C)
110
111 /*
112 * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
113 * Register Bits
114 */
115 #define MCASP_FREE BIT(0)
116 #define MCASP_SOFT BIT(1)
117
118 /*
119 * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
120 */
121 #define AXR(n) (1<<n)
122 #define PFUNC_AMUTE BIT(25)
123 #define ACLKX BIT(26)
124 #define AHCLKX BIT(27)
125 #define AFSX BIT(28)
126 #define ACLKR BIT(29)
127 #define AHCLKR BIT(30)
128 #define AFSR BIT(31)
129
130 /*
131 * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
132 */
133 #define AXR(n) (1<<n)
134 #define PDIR_AMUTE BIT(25)
135 #define ACLKX BIT(26)
136 #define AHCLKX BIT(27)
137 #define AFSX BIT(28)
138 #define ACLKR BIT(29)
139 #define AHCLKR BIT(30)
140 #define AFSR BIT(31)
141
142 /*
143 * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
144 */
145 #define DITEN BIT(0) /* Transmit DIT mode enable/disable */
146 #define VA BIT(2)
147 #define VB BIT(3)
148
149 /*
150 * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
151 */
152 #define TXROT(val) (val)
153 #define TXSEL BIT(3)
154 #define TXSSZ(val) (val<<4)
155 #define TXPBIT(val) (val<<8)
156 #define TXPAD(val) (val<<13)
157 #define TXORD BIT(15)
158 #define FSXDLY(val) (val<<16)
159
160 /*
161 * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits
162 */
163 #define RXROT(val) (val)
164 #define RXSEL BIT(3)
165 #define RXSSZ(val) (val<<4)
166 #define RXPBIT(val) (val<<8)
167 #define RXPAD(val) (val<<13)
168 #define RXORD BIT(15)
169 #define FSRDLY(val) (val<<16)
170
171 /*
172 * DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits
173 */
174 #define FSXPOL BIT(0)
175 #define AFSXE BIT(1)
176 #define FSXDUR BIT(4)
177 #define FSXMOD(val) (val<<7)
178
179 /*
180 * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits
181 */
182 #define FSRPOL BIT(0)
183 #define AFSRE BIT(1)
184 #define FSRDUR BIT(4)
185 #define FSRMOD(val) (val<<7)
186
187 /*
188 * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
189 */
190 #define ACLKXDIV(val) (val)
191 #define ACLKXE BIT(5)
192 #define TX_ASYNC BIT(6)
193 #define ACLKXPOL BIT(7)
194
195 /*
196 * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
197 */
198 #define ACLKRDIV(val) (val)
199 #define ACLKRE BIT(5)
200 #define RX_ASYNC BIT(6)
201 #define ACLKRPOL BIT(7)
202
203 /*
204 * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
205 * Register Bits
206 */
207 #define AHCLKXDIV(val) (val)
208 #define AHCLKXPOL BIT(14)
209 #define AHCLKXE BIT(15)
210
211 /*
212 * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
213 * Register Bits
214 */
215 #define AHCLKRDIV(val) (val)
216 #define AHCLKRPOL BIT(14)
217 #define AHCLKRE BIT(15)
218
219 /*
220 * DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits
221 */
222 #define MODE(val) (val)
223 #define DISMOD (val)(val<<2)
224 #define TXSTATE BIT(4)
225 #define RXSTATE BIT(5)
226
227 /*
228 * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits
229 */
230 #define LBEN BIT(0)
231 #define LBORD BIT(1)
232 #define LBGENMODE(val) (val<<2)
233
234 /*
235 * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
236 */
237 #define TXTDMS(n) (1<<n)
238
239 /*
240 * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration
241 */
242 #define RXTDMS(n) (1<<n)
243
244 /*
245 * DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits
246 */
247 #define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */
248 #define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */
249 #define RXSERCLR BIT(2) /* Receiver Serializer Clear */
250 #define RXSMRST BIT(3) /* Receiver State Machine Reset */
251 #define RXFSRST BIT(4) /* Frame Sync Generator Reset */
252 #define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */
253 #define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/
254 #define TXSERCLR BIT(10) /* Transmit Serializer Clear */
255 #define TXSMRST BIT(11) /* Transmitter State Machine Reset */
256 #define TXFSRST BIT(12) /* Frame Sync Generator Reset */
257
258 /*
259 * DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits
260 */
261 #define MUTENA(val) (val)
262 #define MUTEINPOL BIT(2)
263 #define MUTEINENA BIT(3)
264 #define MUTEIN BIT(4)
265 #define MUTER BIT(5)
266 #define MUTEX BIT(6)
267 #define MUTEFSR BIT(7)
268 #define MUTEFSX BIT(8)
269 #define MUTEBADCLKR BIT(9)
270 #define MUTEBADCLKX BIT(10)
271 #define MUTERXDMAERR BIT(11)
272 #define MUTETXDMAERR BIT(12)
273
274 /*
275 * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits
276 */
277 #define RXDATADMADIS BIT(0)
278
279 /*
280 * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits
281 */
282 #define TXDATADMADIS BIT(0)
283
284 /*
285 * DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits
286 */
287 #define FIFO_ENABLE BIT(16)
288 #define NUMEVT_MASK (0xFF << 8)
289 #define NUMDMA_MASK (0xFF)
290
291 #define DAVINCI_MCASP_NUM_SERIALIZER 16
292
293 static inline void mcasp_set_bits(void __iomem *reg, u32 val)
294 {
295 __raw_writel(__raw_readl(reg) | val, reg);
296 }
297
298 static inline void mcasp_clr_bits(void __iomem *reg, u32 val)
299 {
300 __raw_writel((__raw_readl(reg) & ~(val)), reg);
301 }
302
303 static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask)
304 {
305 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
306 }
307
308 static inline void mcasp_set_reg(void __iomem *reg, u32 val)
309 {
310 __raw_writel(val, reg);
311 }
312
313 static inline u32 mcasp_get_reg(void __iomem *reg)
314 {
315 return (unsigned int)__raw_readl(reg);
316 }
317
318 static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
319 {
320 int i = 0;
321
322 mcasp_set_bits(regs, val);
323
324 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
325 /* loop count is to avoid the lock-up */
326 for (i = 0; i < 1000; i++) {
327 if ((mcasp_get_reg(regs) & val) == val)
328 break;
329 }
330
331 if (i == 1000 && ((mcasp_get_reg(regs) & val) != val))
332 printk(KERN_ERR "GBLCTL write error\n");
333 }
334
335 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
336 struct snd_soc_dai *cpu_dai)
337 {
338 struct davinci_audio_dev *dev = cpu_dai->private_data;
339 cpu_dai->dma_data = dev->dma_params[substream->stream];
340 return 0;
341 }
342
343 static void mcasp_start_rx(struct davinci_audio_dev *dev)
344 {
345 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
346 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
347 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
348 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
349
350 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
351 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
352 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
353
354 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
355 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
356 }
357
358 static void mcasp_start_tx(struct davinci_audio_dev *dev)
359 {
360 u8 offset = 0, i;
361 u32 cnt;
362
363 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
364 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
365 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
366 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
367
368 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
369 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
370 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
371 for (i = 0; i < dev->num_serializer; i++) {
372 if (dev->serial_dir[i] == TX_MODE) {
373 offset = i;
374 break;
375 }
376 }
377
378 /* wait for TX ready */
379 cnt = 0;
380 while (!(mcasp_get_reg(dev->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) &
381 TXSTATE) && (cnt < 100000))
382 cnt++;
383
384 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
385 }
386
387 static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream)
388 {
389 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
390 mcasp_start_tx(dev);
391 else
392 mcasp_start_rx(dev);
393
394 /* enable FIFO */
395 if (dev->txnumevt)
396 mcasp_set_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
397
398 if (dev->rxnumevt)
399 mcasp_set_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
400 }
401
402 static void mcasp_stop_rx(struct davinci_audio_dev *dev)
403 {
404 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, 0);
405 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
406 }
407
408 static void mcasp_stop_tx(struct davinci_audio_dev *dev)
409 {
410 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, 0);
411 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
412 }
413
414 static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream)
415 {
416 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
417 mcasp_stop_tx(dev);
418 else
419 mcasp_stop_rx(dev);
420
421 /* disable FIFO */
422 if (dev->txnumevt)
423 mcasp_clr_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
424
425 if (dev->rxnumevt)
426 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
427 }
428
429 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
430 unsigned int fmt)
431 {
432 struct davinci_audio_dev *dev = cpu_dai->private_data;
433 void __iomem *base = dev->base;
434
435 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
436 case SND_SOC_DAIFMT_CBS_CFS:
437 /* codec is clock and frame slave */
438 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
439 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
440
441 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
442 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
443
444 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x7 << 26));
445 break;
446 case SND_SOC_DAIFMT_CBM_CFM:
447 /* codec is clock and frame master */
448 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
449 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
450
451 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
452 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
453
454 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG, (0x3f << 26));
455 break;
456
457 default:
458 return -EINVAL;
459 }
460
461 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
462 case SND_SOC_DAIFMT_IB_NF:
463 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
464 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
465
466 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
467 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
468 break;
469
470 case SND_SOC_DAIFMT_NB_IF:
471 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
472 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
473
474 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
475 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
476 break;
477
478 case SND_SOC_DAIFMT_IB_IF:
479 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
480 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
481
482 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
483 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
484 break;
485
486 case SND_SOC_DAIFMT_NB_NF:
487 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
488 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
489
490 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
491 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
492 break;
493
494 default:
495 return -EINVAL;
496 }
497
498 return 0;
499 }
500
501 static int davinci_config_channel_size(struct davinci_audio_dev *dev,
502 int channel_size)
503 {
504 u32 fmt = 0;
505
506 switch (channel_size) {
507 case DAVINCI_AUDIO_WORD_8:
508 fmt = 0x03;
509 break;
510
511 case DAVINCI_AUDIO_WORD_12:
512 fmt = 0x05;
513 break;
514
515 case DAVINCI_AUDIO_WORD_16:
516 fmt = 0x07;
517 break;
518
519 case DAVINCI_AUDIO_WORD_20:
520 fmt = 0x09;
521 break;
522
523 case DAVINCI_AUDIO_WORD_24:
524 fmt = 0x0B;
525 break;
526
527 case DAVINCI_AUDIO_WORD_28:
528 fmt = 0x0D;
529 break;
530
531 case DAVINCI_AUDIO_WORD_32:
532 fmt = 0x0F;
533 break;
534
535 default:
536 return -EINVAL;
537 }
538
539 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
540 RXSSZ(fmt), RXSSZ(0x0F));
541 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
542 TXSSZ(fmt), TXSSZ(0x0F));
543 return 0;
544 }
545
546 static void davinci_hw_common_param(struct davinci_audio_dev *dev, int stream)
547 {
548 int i;
549 u8 tx_ser = 0;
550 u8 rx_ser = 0;
551
552 /* Default configuration */
553 mcasp_set_bits(dev->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
554
555 /* All PINS as McASP */
556 mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000);
557
558 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
559 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
560 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG,
561 TXDATADMADIS);
562 } else {
563 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
564 mcasp_clr_bits(dev->base + DAVINCI_MCASP_REVTCTL_REG,
565 RXDATADMADIS);
566 }
567
568 for (i = 0; i < dev->num_serializer; i++) {
569 mcasp_set_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
570 dev->serial_dir[i]);
571 if (dev->serial_dir[i] == TX_MODE) {
572 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
573 AXR(i));
574 tx_ser++;
575 } else if (dev->serial_dir[i] == RX_MODE) {
576 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
577 AXR(i));
578 rx_ser++;
579 }
580 }
581
582 if (dev->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
583 if (dev->txnumevt * tx_ser > 64)
584 dev->txnumevt = 1;
585
586 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, tx_ser,
587 NUMDMA_MASK);
588 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
589 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
590 mcasp_set_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
591 }
592
593 if (dev->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
594 if (dev->rxnumevt * rx_ser > 64)
595 dev->rxnumevt = 1;
596
597 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, rx_ser,
598 NUMDMA_MASK);
599 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
600 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
601 mcasp_set_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
602 }
603 }
604
605 static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
606 {
607 int i, active_slots;
608 u32 mask = 0;
609
610 active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots;
611 for (i = 0; i < active_slots; i++)
612 mask |= (1 << i);
613
614 mcasp_clr_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
615
616 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
617 /* bit stream is MSB first with no delay */
618 /* DSP_B mode */
619 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
620 AHCLKXE);
621 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask);
622 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD);
623
624 if ((dev->tdm_slots >= 2) || (dev->tdm_slots <= 32))
625 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
626 FSXMOD(dev->tdm_slots), FSXMOD(0x1FF));
627 else
628 printk(KERN_ERR "playback tdm slot %d not supported\n",
629 dev->tdm_slots);
630
631 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, 0xFFFFFFFF);
632 mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
633 } else {
634 /* bit stream is MSB first with no delay */
635 /* DSP_B mode */
636 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD);
637 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
638 AHCLKRE);
639 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask);
640
641 if ((dev->tdm_slots >= 2) || (dev->tdm_slots <= 32))
642 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG,
643 FSRMOD(dev->tdm_slots), FSRMOD(0x1FF));
644 else
645 printk(KERN_ERR "capture tdm slot %d not supported\n",
646 dev->tdm_slots);
647
648 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG, 0xFFFFFFFF);
649 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
650 }
651 }
652
653 /* S/PDIF */
654 static void davinci_hw_dit_param(struct davinci_audio_dev *dev)
655 {
656 /* Set the PDIR for Serialiser as output */
657 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AFSX);
658
659 /* TXMASK for 24 bits */
660 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, 0x00FFFFFF);
661
662 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
663 and LSB first */
664 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
665 TXROT(6) | TXSSZ(15));
666
667 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
668 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
669 AFSXE | FSXMOD(0x180));
670
671 /* Set the TX tdm : for all the slots */
672 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
673
674 /* Set the TX clock controls : div = 1 and internal */
675 mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
676 ACLKXE | TX_ASYNC);
677
678 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
679
680 /* Only 44100 and 48000 are valid, both have the same setting */
681 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
682
683 /* Enable the DIT */
684 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN);
685 }
686
687 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
688 struct snd_pcm_hw_params *params,
689 struct snd_soc_dai *cpu_dai)
690 {
691 struct davinci_audio_dev *dev = cpu_dai->private_data;
692 struct davinci_pcm_dma_params *dma_params =
693 dev->dma_params[substream->stream];
694 int word_length;
695 u8 numevt;
696
697 davinci_hw_common_param(dev, substream->stream);
698 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
699 numevt = dev->txnumevt;
700 else
701 numevt = dev->rxnumevt;
702
703 if (!numevt)
704 numevt = 1;
705
706 if (dev->op_mode == DAVINCI_MCASP_DIT_MODE)
707 davinci_hw_dit_param(dev);
708 else
709 davinci_hw_param(dev, substream->stream);
710
711 switch (params_format(params)) {
712 case SNDRV_PCM_FORMAT_S8:
713 dma_params->data_type = 1;
714 word_length = DAVINCI_AUDIO_WORD_8;
715 break;
716
717 case SNDRV_PCM_FORMAT_S16_LE:
718 dma_params->data_type = 2;
719 word_length = DAVINCI_AUDIO_WORD_16;
720 break;
721
722 case SNDRV_PCM_FORMAT_S32_LE:
723 dma_params->data_type = 4;
724 word_length = DAVINCI_AUDIO_WORD_32;
725 break;
726
727 default:
728 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
729 return -EINVAL;
730 }
731
732 if (dev->version == MCASP_VERSION_2) {
733 dma_params->data_type *= numevt;
734 dma_params->acnt = 4 * numevt;
735 } else
736 dma_params->acnt = dma_params->data_type;
737
738 davinci_config_channel_size(dev, word_length);
739
740 return 0;
741 }
742
743 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
744 int cmd, struct snd_soc_dai *cpu_dai)
745 {
746 struct snd_soc_pcm_runtime *rtd = substream->private_data;
747 struct davinci_audio_dev *dev = rtd->dai->cpu_dai->private_data;
748 int ret = 0;
749
750 switch (cmd) {
751 case SNDRV_PCM_TRIGGER_START:
752 case SNDRV_PCM_TRIGGER_RESUME:
753 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
754 davinci_mcasp_start(dev, substream->stream);
755 break;
756
757 case SNDRV_PCM_TRIGGER_STOP:
758 case SNDRV_PCM_TRIGGER_SUSPEND:
759 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
760 davinci_mcasp_stop(dev, substream->stream);
761 break;
762
763 default:
764 ret = -EINVAL;
765 }
766
767 return ret;
768 }
769
770 static struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
771 .startup = davinci_mcasp_startup,
772 .trigger = davinci_mcasp_trigger,
773 .hw_params = davinci_mcasp_hw_params,
774 .set_fmt = davinci_mcasp_set_dai_fmt,
775
776 };
777
778 struct snd_soc_dai davinci_mcasp_dai[] = {
779 {
780 .name = "davinci-i2s",
781 .id = 0,
782 .playback = {
783 .channels_min = 2,
784 .channels_max = 2,
785 .rates = DAVINCI_MCASP_RATES,
786 .formats = SNDRV_PCM_FMTBIT_S8 |
787 SNDRV_PCM_FMTBIT_S16_LE |
788 SNDRV_PCM_FMTBIT_S32_LE,
789 },
790 .capture = {
791 .channels_min = 2,
792 .channels_max = 2,
793 .rates = DAVINCI_MCASP_RATES,
794 .formats = SNDRV_PCM_FMTBIT_S8 |
795 SNDRV_PCM_FMTBIT_S16_LE |
796 SNDRV_PCM_FMTBIT_S32_LE,
797 },
798 .ops = &davinci_mcasp_dai_ops,
799
800 },
801 {
802 .name = "davinci-dit",
803 .id = 1,
804 .playback = {
805 .channels_min = 1,
806 .channels_max = 384,
807 .rates = DAVINCI_MCASP_RATES,
808 .formats = SNDRV_PCM_FMTBIT_S16_LE,
809 },
810 .ops = &davinci_mcasp_dai_ops,
811 },
812
813 };
814 EXPORT_SYMBOL_GPL(davinci_mcasp_dai);
815
816 static int davinci_mcasp_probe(struct platform_device *pdev)
817 {
818 struct davinci_pcm_dma_params *dma_data;
819 struct resource *mem, *ioarea, *res;
820 struct snd_platform_data *pdata;
821 struct davinci_audio_dev *dev;
822 int count = 0;
823 int ret = 0;
824
825 dev = kzalloc(sizeof(struct davinci_audio_dev), GFP_KERNEL);
826 if (!dev)
827 return -ENOMEM;
828
829 dma_data = kzalloc(sizeof(struct davinci_pcm_dma_params) * 2,
830 GFP_KERNEL);
831 if (!dma_data) {
832 ret = -ENOMEM;
833 goto err_release_dev;
834 }
835
836 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
837 if (!mem) {
838 dev_err(&pdev->dev, "no mem resource?\n");
839 ret = -ENODEV;
840 goto err_release_data;
841 }
842
843 ioarea = request_mem_region(mem->start,
844 (mem->end - mem->start) + 1, pdev->name);
845 if (!ioarea) {
846 dev_err(&pdev->dev, "Audio region already claimed\n");
847 ret = -EBUSY;
848 goto err_release_data;
849 }
850
851 pdata = pdev->dev.platform_data;
852 dev->clk = clk_get(&pdev->dev, NULL);
853 if (IS_ERR(dev->clk)) {
854 ret = -ENODEV;
855 goto err_release_region;
856 }
857
858 clk_enable(dev->clk);
859
860 dev->base = (void __iomem *)IO_ADDRESS(mem->start);
861 dev->op_mode = pdata->op_mode;
862 dev->tdm_slots = pdata->tdm_slots;
863 dev->num_serializer = pdata->num_serializer;
864 dev->serial_dir = pdata->serial_dir;
865 dev->codec_fmt = pdata->codec_fmt;
866 dev->version = pdata->version;
867 dev->txnumevt = pdata->txnumevt;
868 dev->rxnumevt = pdata->rxnumevt;
869
870 dma_data[count].name = "I2S PCM Stereo out";
871 dma_data[count].eventq_no = pdata->eventq_no;
872 dma_data[count].dma_addr = (dma_addr_t) (pdata->tx_dma_offset +
873 io_v2p(dev->base));
874 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &dma_data[count];
875
876 /* first TX, then RX */
877 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
878 if (!res) {
879 dev_err(&pdev->dev, "no DMA resource\n");
880 goto err_release_region;
881 }
882
883 dma_data[count].channel = res->start;
884 count++;
885 dma_data[count].name = "I2S PCM Stereo in";
886 dma_data[count].eventq_no = pdata->eventq_no;
887 dma_data[count].dma_addr = (dma_addr_t)(pdata->rx_dma_offset +
888 io_v2p(dev->base));
889 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &dma_data[count];
890
891 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
892 if (!res) {
893 dev_err(&pdev->dev, "no DMA resource\n");
894 goto err_release_region;
895 }
896
897 dma_data[count].channel = res->start;
898 davinci_mcasp_dai[pdata->op_mode].private_data = dev;
899 davinci_mcasp_dai[pdata->op_mode].dev = &pdev->dev;
900 ret = snd_soc_register_dai(&davinci_mcasp_dai[pdata->op_mode]);
901
902 if (ret != 0)
903 goto err_release_region;
904 return 0;
905
906 err_release_region:
907 release_mem_region(mem->start, (mem->end - mem->start) + 1);
908 err_release_data:
909 kfree(dma_data);
910 err_release_dev:
911 kfree(dev);
912
913 return ret;
914 }
915
916 static int davinci_mcasp_remove(struct platform_device *pdev)
917 {
918 struct snd_platform_data *pdata = pdev->dev.platform_data;
919 struct davinci_pcm_dma_params *dma_data;
920 struct davinci_audio_dev *dev;
921 struct resource *mem;
922
923 snd_soc_unregister_dai(&davinci_mcasp_dai[pdata->op_mode]);
924 dev = davinci_mcasp_dai[pdata->op_mode].private_data;
925 clk_disable(dev->clk);
926 clk_put(dev->clk);
927 dev->clk = NULL;
928
929 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
930 release_mem_region(mem->start, (mem->end - mem->start) + 1);
931
932 dma_data = dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
933 kfree(dma_data);
934 kfree(dev);
935
936 return 0;
937 }
938
939 static struct platform_driver davinci_mcasp_driver = {
940 .probe = davinci_mcasp_probe,
941 .remove = davinci_mcasp_remove,
942 .driver = {
943 .name = "davinci-mcasp",
944 .owner = THIS_MODULE,
945 },
946 };
947
948 static int __init davinci_mcasp_init(void)
949 {
950 return platform_driver_register(&davinci_mcasp_driver);
951 }
952 module_init(davinci_mcasp_init);
953
954 static void __exit davinci_mcasp_exit(void)
955 {
956 platform_driver_unregister(&davinci_mcasp_driver);
957 }
958 module_exit(davinci_mcasp_exit);
959
960 MODULE_AUTHOR("Steve Chen");
961 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
962 MODULE_LICENSE("GPL");
963
Linux kernel - Deliverables
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