sound/soc/fsl/fsl_sai.c

   1 /*
   2  * Freescale ALSA SoC Digital Audio Interface (SAI) driver.
   3  *
   4  * Copyright 2012-2015 Freescale Semiconductor, Inc.
   5  *
   6  * This program is free software, you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License as published by the
   8  * Free Software Foundation, either version 2 of the License, or(at your
   9  * option) any later version.
  10  *
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/delay.h>
  15 #include <linux/dmaengine.h>
  16 #include <linux/module.h>
  17 #include <linux/of_address.h>
  18 #include <linux/regmap.h>
  19 #include <linux/slab.h>
  20 #include <sound/core.h>
  21 #include <sound/dmaengine_pcm.h>
  22 #include <sound/pcm_params.h>
  23
  24 #include "fsl_sai.h"
  25 #include "imx-pcm.h"
  26
  27 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
  28                        FSL_SAI_CSR_FEIE)
  29
  30 static const unsigned int fsl_sai_rates[] = {
  31         8000, 11025, 12000, 16000, 22050,
  32         24000, 32000, 44100, 48000, 64000,
  33         88200, 96000, 176400, 192000
  34 };
  35
  36 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {
  37         .count = ARRAY_SIZE(fsl_sai_rates),
  38         .list = fsl_sai_rates,
  39 };
  40
  41 static irqreturn_t fsl_sai_isr(int irq, void *devid)
  42 {
  43         struct fsl_sai *sai = (struct fsl_sai *)devid;
  44         struct device *dev = &sai->pdev->dev;
  45         u32 flags, xcsr, mask;
  46         bool irq_none = true;
  47
  48         /*
  49          * Both IRQ status bits and IRQ mask bits are in the xCSR but
  50          * different shifts. And we here create a mask only for those
  51          * IRQs that we activated.
  52          */
  53         mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
  54
  55         /* Tx IRQ */
  56         regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr);
  57         flags = xcsr & mask;
  58
  59         if (flags)
  60                 irq_none = false;
  61         else
  62                 goto irq_rx;
  63
  64         if (flags & FSL_SAI_CSR_WSF)
  65                 dev_dbg(dev, "isr: Start of Tx word detected\n");
  66
  67         if (flags & FSL_SAI_CSR_SEF)
  68                 dev_warn(dev, "isr: Tx Frame sync error detected\n");
  69
  70         if (flags & FSL_SAI_CSR_FEF) {
  71                 dev_warn(dev, "isr: Transmit underrun detected\n");
  72                 /* FIFO reset for safety */
  73                 xcsr |= FSL_SAI_CSR_FR;
  74         }
  75
  76         if (flags & FSL_SAI_CSR_FWF)
  77                 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
  78
  79         if (flags & FSL_SAI_CSR_FRF)
  80                 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n");
  81
  82         flags &= FSL_SAI_CSR_xF_W_MASK;
  83         xcsr &= ~FSL_SAI_CSR_xF_MASK;
  84
  85         if (flags)
  86                 regmap_write(sai->regmap, FSL_SAI_TCSR, flags | xcsr);
  87
  88 irq_rx:
  89         /* Rx IRQ */
  90         regmap_read(sai->regmap, FSL_SAI_RCSR, &xcsr);
  91         flags = xcsr & mask;
  92
  93         if (flags)
  94                 irq_none = false;
  95         else
  96                 goto out;
  97
  98         if (flags & FSL_SAI_CSR_WSF)
  99                 dev_dbg(dev, "isr: Start of Rx word detected\n");
 100
 101         if (flags & FSL_SAI_CSR_SEF)
 102                 dev_warn(dev, "isr: Rx Frame sync error detected\n");
 103
 104         if (flags & FSL_SAI_CSR_FEF) {
 105                 dev_warn(dev, "isr: Receive overflow detected\n");
 106                 /* FIFO reset for safety */
 107                 xcsr |= FSL_SAI_CSR_FR;
 108         }
 109
 110         if (flags & FSL_SAI_CSR_FWF)
 111                 dev_dbg(dev, "isr: Enabled receive FIFO is full\n");
 112
 113         if (flags & FSL_SAI_CSR_FRF)
 114                 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n");
 115
 116         flags &= FSL_SAI_CSR_xF_W_MASK;
 117         xcsr &= ~FSL_SAI_CSR_xF_MASK;
 118
 119         if (flags)
 120                 regmap_write(sai->regmap, FSL_SAI_RCSR, flags | xcsr);
 121
 122 out:
 123         if (irq_none)
 124                 return IRQ_NONE;
 125         else
 126                 return IRQ_HANDLED;
 127 }
 128
 129 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
 130                 int clk_id, unsigned int freq, int fsl_dir)
 131 {
 132         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
 133         bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
 134         u32 val_cr2 = 0;
 135
 136         switch (clk_id) {
 137         case FSL_SAI_CLK_BUS:
 138                 val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
 139                 break;
 140         case FSL_SAI_CLK_MAST1:
 141                 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
 142                 break;
 143         case FSL_SAI_CLK_MAST2:
 144                 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
 145                 break;
 146         case FSL_SAI_CLK_MAST3:
 147                 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
 148                 break;
 149         default:
 150                 return -EINVAL;
 151         }
 152
 153         regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
 154                            FSL_SAI_CR2_MSEL_MASK, val_cr2);
 155
 156         return 0;
 157 }
 158
 159 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
 160                 int clk_id, unsigned int freq, int dir)
 161 {
 162         int ret;
 163
 164         if (dir == SND_SOC_CLOCK_IN)
 165                 return 0;
 166
 167         ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
 168                                         FSL_FMT_TRANSMITTER);
 169         if (ret) {
 170                 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
 171                 return ret;
 172         }
 173
 174         ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
 175                                         FSL_FMT_RECEIVER);
 176         if (ret)
 177                 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
 178
 179         return ret;
 180 }
 181
 182 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
 183                                 unsigned int fmt, int fsl_dir)
 184 {
 185         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
 186         bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
 187         u32 val_cr2 = 0, val_cr4 = 0;
 188
 189         if (!sai->is_lsb_first)
 190                 val_cr4 |= FSL_SAI_CR4_MF;
 191
 192         /* DAI mode */
 193         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 194         case SND_SOC_DAIFMT_I2S:
 195                 /*
 196                  * Frame low, 1clk before data, one word length for frame sync,
 197                  * frame sync starts one serial clock cycle earlier,
 198                  * that is, together with the last bit of the previous
 199                  * data word.
 200                  */
 201                 val_cr2 |= FSL_SAI_CR2_BCP;
 202                 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
 203                 break;
 204         case SND_SOC_DAIFMT_LEFT_J:
 205                 /*
 206                  * Frame high, one word length for frame sync,
 207                  * frame sync asserts with the first bit of the frame.
 208                  */
 209                 val_cr2 |= FSL_SAI_CR2_BCP;
 210                 break;
 211         case SND_SOC_DAIFMT_DSP_A:
 212                 /*
 213                  * Frame high, 1clk before data, one bit for frame sync,
 214                  * frame sync starts one serial clock cycle earlier,
 215                  * that is, together with the last bit of the previous
 216                  * data word.
 217                  */
 218                 val_cr2 |= FSL_SAI_CR2_BCP;
 219                 val_cr4 |= FSL_SAI_CR4_FSE;
 220                 sai->is_dsp_mode = true;
 221                 break;
 222         case SND_SOC_DAIFMT_DSP_B:
 223                 /*
 224                  * Frame high, one bit for frame sync,
 225                  * frame sync asserts with the first bit of the frame.
 226                  */
 227                 val_cr2 |= FSL_SAI_CR2_BCP;
 228                 sai->is_dsp_mode = true;
 229                 break;
 230         case SND_SOC_DAIFMT_RIGHT_J:
 231                 /* To be done */
 232         default:
 233                 return -EINVAL;
 234         }
 235
 236         /* DAI clock inversion */
 237         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 238         case SND_SOC_DAIFMT_IB_IF:
 239                 /* Invert both clocks */
 240                 val_cr2 ^= FSL_SAI_CR2_BCP;
 241                 val_cr4 ^= FSL_SAI_CR4_FSP;
 242                 break;
 243         case SND_SOC_DAIFMT_IB_NF:
 244                 /* Invert bit clock */
 245                 val_cr2 ^= FSL_SAI_CR2_BCP;
 246                 break;
 247         case SND_SOC_DAIFMT_NB_IF:
 248                 /* Invert frame clock */
 249                 val_cr4 ^= FSL_SAI_CR4_FSP;
 250                 break;
 251         case SND_SOC_DAIFMT_NB_NF:
 252                 /* Nothing to do for both normal cases */
 253                 break;
 254         default:
 255                 return -EINVAL;
 256         }
 257
 258         /* DAI clock master masks */
 259         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 260         case SND_SOC_DAIFMT_CBS_CFS:
 261                 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
 262                 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
 263                 break;
 264         case SND_SOC_DAIFMT_CBM_CFM:
 265                 sai->is_slave_mode = true;
 266                 break;
 267         case SND_SOC_DAIFMT_CBS_CFM:
 268                 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
 269                 break;
 270         case SND_SOC_DAIFMT_CBM_CFS:
 271                 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
 272                 sai->is_slave_mode = true;
 273                 break;
 274         default:
 275                 return -EINVAL;
 276         }
 277
 278         regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
 279                            FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
 280         regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
 281                            FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
 282                            FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
 283
 284         return 0;
 285 }
 286
 287 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
 288 {
 289         int ret;
 290
 291         ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER);
 292         if (ret) {
 293                 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
 294                 return ret;
 295         }
 296
 297         ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER);
 298         if (ret)
 299                 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
 300
 301         return ret;
 302 }
 303
 304 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
 305 {
 306         struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
 307         unsigned long clk_rate;
 308         u32 savediv = 0, ratio, savesub = freq;
 309         u32 id;
 310         int ret = 0;
 311
 312         /* Don't apply to slave mode */
 313         if (sai->is_slave_mode)
 314                 return 0;
 315
 316         for (id = 0; id < FSL_SAI_MCLK_MAX; id++) {
 317                 clk_rate = clk_get_rate(sai->mclk_clk[id]);
 318                 if (!clk_rate)
 319                         continue;
 320
 321                 ratio = clk_rate / freq;
 322
 323                 ret = clk_rate - ratio * freq;
 324
 325                 /*
 326                  * Drop the source that can not be
 327                  * divided into the required rate.
 328                  */
 329                 if (ret != 0 && clk_rate / ret < 1000)
 330                         continue;
 331
 332                 dev_dbg(dai->dev,
 333                         "ratio %d for freq %dHz based on clock %ldHz\n",
 334                         ratio, freq, clk_rate);
 335
 336                 if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512)
 337                         ratio /= 2;
 338                 else
 339                         continue;
 340
 341                 if (ret < savesub) {
 342                         savediv = ratio;
 343                         sai->mclk_id[tx] = id;
 344                         savesub = ret;
 345                 }
 346
 347                 if (ret == 0)
 348                         break;
 349         }
 350
 351         if (savediv == 0) {
 352                 dev_err(dai->dev, "failed to derive required %cx rate: %d\n",
 353                                 tx ? 'T' : 'R', freq);
 354                 return -EINVAL;
 355         }
 356
 357         if ((tx && sai->synchronous[TX]) || (!tx && !sai->synchronous[RX])) {
 358                 regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
 359                                    FSL_SAI_CR2_MSEL_MASK,
 360                                    FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
 361                 regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
 362                                    FSL_SAI_CR2_DIV_MASK, savediv - 1);
 363         } else {
 364                 regmap_update_bits(sai->regmap, FSL_SAI_TCR2,
 365                                    FSL_SAI_CR2_MSEL_MASK,
 366                                    FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
 367                 regmap_update_bits(sai->regmap, FSL_SAI_TCR2,
 368                                    FSL_SAI_CR2_DIV_MASK, savediv - 1);
 369         }
 370
 371         dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
 372                         sai->mclk_id[tx], savediv, savesub);
 373
 374         return 0;
 375 }
 376
 377 static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
 378                 struct snd_pcm_hw_params *params,
 379                 struct snd_soc_dai *cpu_dai)
 380 {
 381         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
 382         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
 383         unsigned int channels = params_channels(params);
 384         u32 word_width = snd_pcm_format_width(params_format(params));
 385         u32 val_cr4 = 0, val_cr5 = 0;
 386         int ret;
 387
 388         if (!sai->is_slave_mode) {
 389                 ret = fsl_sai_set_bclk(cpu_dai, tx,
 390                         2 * word_width * params_rate(params));
 391                 if (ret)
 392                         return ret;
 393
 394                 /* Do not enable the clock if it is already enabled */
 395                 if (!(sai->mclk_streams & BIT(substream->stream))) {
 396                         ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]);
 397                         if (ret)
 398                                 return ret;
 399
 400                         sai->mclk_streams |= BIT(substream->stream);
 401                 }
 402
 403         }
 404
 405         if (!sai->is_dsp_mode)
 406                 val_cr4 |= FSL_SAI_CR4_SYWD(word_width);
 407
 408         val_cr5 |= FSL_SAI_CR5_WNW(word_width);
 409         val_cr5 |= FSL_SAI_CR5_W0W(word_width);
 410
 411         if (sai->is_lsb_first)
 412                 val_cr5 |= FSL_SAI_CR5_FBT(0);
 413         else
 414                 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
 415
 416         val_cr4 |= FSL_SAI_CR4_FRSZ(channels);
 417
 418         regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
 419                            FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
 420                            val_cr4);
 421         regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx),
 422                            FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
 423                            FSL_SAI_CR5_FBT_MASK, val_cr5);
 424         regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1));
 425
 426         return 0;
 427 }
 428
 429 static int fsl_sai_hw_free(struct snd_pcm_substream *substream,
 430                 struct snd_soc_dai *cpu_dai)
 431 {
 432         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
 433         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
 434
 435         if (!sai->is_slave_mode &&
 436                         sai->mclk_streams & BIT(substream->stream)) {
 437                 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]);
 438                 sai->mclk_streams &= ~BIT(substream->stream);
 439         }
 440
 441         return 0;
 442 }
 443
 444
 445 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
 446                 struct snd_soc_dai *cpu_dai)
 447 {
 448         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
 449         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
 450         u32 xcsr, count = 100;
 451
 452         /*
 453          * Asynchronous mode: Clear SYNC for both Tx and Rx.
 454          * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
 455          * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
 456          */
 457         regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC,
 458                            sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);
 459         regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC,
 460                            sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
 461
 462         /*
 463          * It is recommended that the transmitter is the last enabled
 464          * and the first disabled.
 465          */
 466         switch (cmd) {
 467         case SNDRV_PCM_TRIGGER_START:
 468         case SNDRV_PCM_TRIGGER_RESUME:
 469         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 470                 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
 471                                    FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
 472
 473                 regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
 474                                    FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
 475                 regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
 476                                    FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
 477
 478                 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
 479                                    FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
 480                 break;
 481         case SNDRV_PCM_TRIGGER_STOP:
 482         case SNDRV_PCM_TRIGGER_SUSPEND:
 483         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 484                 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
 485                                    FSL_SAI_CSR_FRDE, 0);
 486                 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
 487                                    FSL_SAI_CSR_xIE_MASK, 0);
 488
 489                 /* Check if the opposite FRDE is also disabled */
 490                 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx), &xcsr);
 491                 if (!(xcsr & FSL_SAI_CSR_FRDE)) {
 492                         /* Disable both directions and reset their FIFOs */
 493                         regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
 494                                            FSL_SAI_CSR_TERE, 0);
 495                         regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
 496                                            FSL_SAI_CSR_TERE, 0);
 497
 498                         /* TERE will remain set till the end of current frame */
 499                         do {
 500                                 udelay(10);
 501                                 regmap_read(sai->regmap, FSL_SAI_xCSR(tx), &xcsr);
 502                         } while (--count && xcsr & FSL_SAI_CSR_TERE);
 503
 504                         regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
 505                                            FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
 506                         regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
 507                                            FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
 508                 }
 509                 break;
 510         default:
 511                 return -EINVAL;
 512         }
 513
 514         return 0;
 515 }
 516
 517 static int fsl_sai_startup(struct snd_pcm_substream *substream,
 518                 struct snd_soc_dai *cpu_dai)
 519 {
 520         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
 521         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
 522         struct device *dev = &sai->pdev->dev;
 523         int ret;
 524
 525         ret = clk_prepare_enable(sai->bus_clk);
 526         if (ret) {
 527                 dev_err(dev, "failed to enable bus clock: %d\n", ret);
 528                 return ret;
 529         }
 530
 531         regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE,
 532                            FSL_SAI_CR3_TRCE);
 533
 534         ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
 535                         SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints);
 536
 537         return ret;
 538 }
 539
 540 static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
 541                 struct snd_soc_dai *cpu_dai)
 542 {
 543         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
 544         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
 545
 546         regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 0);
 547
 548         clk_disable_unprepare(sai->bus_clk);
 549 }
 550
 551 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
 552         .set_sysclk     = fsl_sai_set_dai_sysclk,
 553         .set_fmt        = fsl_sai_set_dai_fmt,
 554         .hw_params      = fsl_sai_hw_params,
 555         .hw_free        = fsl_sai_hw_free,
 556         .trigger        = fsl_sai_trigger,
 557         .startup        = fsl_sai_startup,
 558         .shutdown       = fsl_sai_shutdown,
 559 };
 560
 561 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
 562 {
 563         struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
 564
 565         /* Software Reset for both Tx and Rx */
 566         regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
 567         regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
 568         /* Clear SR bit to finish the reset */
 569         regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
 570         regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
 571
 572         regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK,
 573                            FSL_SAI_MAXBURST_TX * 2);
 574         regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK,
 575                            FSL_SAI_MAXBURST_RX - 1);
 576
 577         snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
 578                                 &sai->dma_params_rx);
 579
 580         snd_soc_dai_set_drvdata(cpu_dai, sai);
 581
 582         return 0;
 583 }
 584
 585 static struct snd_soc_dai_driver fsl_sai_dai = {
 586         .probe = fsl_sai_dai_probe,
 587         .playback = {
 588                 .stream_name = "CPU-Playback",
 589                 .channels_min = 1,
 590                 .channels_max = 2,
 591                 .rate_min = 8000,
 592                 .rate_max = 192000,
 593                 .rates = SNDRV_PCM_RATE_KNOT,
 594                 .formats = FSL_SAI_FORMATS,
 595         },
 596         .capture = {
 597                 .stream_name = "CPU-Capture",
 598                 .channels_min = 1,
 599                 .channels_max = 2,
 600                 .rate_min = 8000,
 601                 .rate_max = 192000,
 602                 .rates = SNDRV_PCM_RATE_KNOT,
 603                 .formats = FSL_SAI_FORMATS,
 604         },
 605         .ops = &fsl_sai_pcm_dai_ops,
 606 };
 607
 608 static const struct snd_soc_component_driver fsl_component = {
 609         .name           = "fsl-sai",
 610 };
 611
 612 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
 613 {
 614         switch (reg) {
 615         case FSL_SAI_TCSR:
 616         case FSL_SAI_TCR1:
 617         case FSL_SAI_TCR2:
 618         case FSL_SAI_TCR3:
 619         case FSL_SAI_TCR4:
 620         case FSL_SAI_TCR5:
 621         case FSL_SAI_TFR:
 622         case FSL_SAI_TMR:
 623         case FSL_SAI_RCSR:
 624         case FSL_SAI_RCR1:
 625         case FSL_SAI_RCR2:
 626         case FSL_SAI_RCR3:
 627         case FSL_SAI_RCR4:
 628         case FSL_SAI_RCR5:
 629         case FSL_SAI_RDR:
 630         case FSL_SAI_RFR:
 631         case FSL_SAI_RMR:
 632                 return true;
 633         default:
 634                 return false;
 635         }
 636 }
 637
 638 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
 639 {
 640         switch (reg) {
 641         case FSL_SAI_TCSR:
 642         case FSL_SAI_RCSR:
 643         case FSL_SAI_TFR:
 644         case FSL_SAI_RFR:
 645         case FSL_SAI_TDR:
 646         case FSL_SAI_RDR:
 647                 return true;
 648         default:
 649                 return false;
 650         }
 651
 652 }
 653
 654 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
 655 {
 656         switch (reg) {
 657         case FSL_SAI_TCSR:
 658         case FSL_SAI_TCR1:
 659         case FSL_SAI_TCR2:
 660         case FSL_SAI_TCR3:
 661         case FSL_SAI_TCR4:
 662         case FSL_SAI_TCR5:
 663         case FSL_SAI_TDR:
 664         case FSL_SAI_TMR:
 665         case FSL_SAI_RCSR:
 666         case FSL_SAI_RCR1:
 667         case FSL_SAI_RCR2:
 668         case FSL_SAI_RCR3:
 669         case FSL_SAI_RCR4:
 670         case FSL_SAI_RCR5:
 671         case FSL_SAI_RMR:
 672                 return true;
 673         default:
 674                 return false;
 675         }
 676 }
 677
 678 static const struct regmap_config fsl_sai_regmap_config = {
 679         .reg_bits = 32,
 680         .reg_stride = 4,
 681         .val_bits = 32,
 682
 683         .max_register = FSL_SAI_RMR,
 684         .readable_reg = fsl_sai_readable_reg,
 685         .volatile_reg = fsl_sai_volatile_reg,
 686         .writeable_reg = fsl_sai_writeable_reg,
 687         .cache_type = REGCACHE_FLAT,
 688 };
 689
 690 static int fsl_sai_probe(struct platform_device *pdev)
 691 {
 692         struct device_node *np = pdev->dev.of_node;
 693         struct fsl_sai *sai;
 694         struct resource *res;
 695         void __iomem *base;
 696         char tmp[8];
 697         int irq, ret, i;
 698
 699         sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
 700         if (!sai)
 701                 return -ENOMEM;
 702
 703         sai->pdev = pdev;
 704
 705         if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx6sx-sai"))
 706                 sai->sai_on_imx = true;
 707
 708         sai->is_lsb_first = of_property_read_bool(np, "lsb-first");
 709
 710         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 711         base = devm_ioremap_resource(&pdev->dev, res);
 712         if (IS_ERR(base))
 713                 return PTR_ERR(base);
 714
 715         sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
 716                         "bus", base, &fsl_sai_regmap_config);
 717
 718         /* Compatible with old DTB cases */
 719         if (IS_ERR(sai->regmap))
 720                 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
 721                                 "sai", base, &fsl_sai_regmap_config);
 722         if (IS_ERR(sai->regmap)) {
 723                 dev_err(&pdev->dev, "regmap init failed\n");
 724                 return PTR_ERR(sai->regmap);
 725         }
 726
 727         /* No error out for old DTB cases but only mark the clock NULL */
 728         sai->bus_clk = devm_clk_get(&pdev->dev, "bus");
 729         if (IS_ERR(sai->bus_clk)) {
 730                 dev_err(&pdev->dev, "failed to get bus clock: %ld\n",
 731                                 PTR_ERR(sai->bus_clk));
 732                 sai->bus_clk = NULL;
 733         }
 734
 735         sai->mclk_clk[0] = sai->bus_clk;
 736         for (i = 1; i < FSL_SAI_MCLK_MAX; i++) {
 737                 sprintf(tmp, "mclk%d", i);
 738                 sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
 739                 if (IS_ERR(sai->mclk_clk[i])) {
 740                         dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n",
 741                                         i + 1, PTR_ERR(sai->mclk_clk[i]));
 742                         sai->mclk_clk[i] = NULL;
 743                 }
 744         }
 745
 746         irq = platform_get_irq(pdev, 0);
 747         if (irq < 0) {
 748                 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
 749                 return irq;
 750         }
 751
 752         ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, 0, np->name, sai);
 753         if (ret) {
 754                 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
 755                 return ret;
 756         }
 757
 758         /* Sync Tx with Rx as default by following old DT binding */
 759         sai->synchronous[RX] = true;
 760         sai->synchronous[TX] = false;
 761         fsl_sai_dai.symmetric_rates = 1;
 762         fsl_sai_dai.symmetric_channels = 1;
 763         fsl_sai_dai.symmetric_samplebits = 1;
 764
 765         if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) &&
 766             of_find_property(np, "fsl,sai-asynchronous", NULL)) {
 767                 /* error out if both synchronous and asynchronous are present */
 768                 dev_err(&pdev->dev, "invalid binding for synchronous mode\n");
 769                 return -EINVAL;
 770         }
 771
 772         if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) {
 773                 /* Sync Rx with Tx */
 774                 sai->synchronous[RX] = false;
 775                 sai->synchronous[TX] = true;
 776         } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) {
 777                 /* Discard all settings for asynchronous mode */
 778                 sai->synchronous[RX] = false;
 779                 sai->synchronous[TX] = false;
 780                 fsl_sai_dai.symmetric_rates = 0;
 781                 fsl_sai_dai.symmetric_channels = 0;
 782                 fsl_sai_dai.symmetric_samplebits = 0;
 783         }
 784
 785         sai->dma_params_rx.addr = res->start + FSL_SAI_RDR;
 786         sai->dma_params_tx.addr = res->start + FSL_SAI_TDR;
 787         sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
 788         sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
 789
 790         platform_set_drvdata(pdev, sai);
 791
 792         ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component,
 793                         &fsl_sai_dai, 1);
 794         if (ret)
 795                 return ret;
 796
 797         if (sai->sai_on_imx)
 798                 return imx_pcm_dma_init(pdev, IMX_SAI_DMABUF_SIZE);
 799         else
 800                 return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
 801 }
 802
 803 static const struct of_device_id fsl_sai_ids[] = {
 804         { .compatible = "fsl,vf610-sai", },
 805         { .compatible = "fsl,imx6sx-sai", },
 806         { /* sentinel */ }
 807 };
 808 MODULE_DEVICE_TABLE(of, fsl_sai_ids);
 809
 810 #ifdef CONFIG_PM_SLEEP
 811 static int fsl_sai_suspend(struct device *dev)
 812 {
 813         struct fsl_sai *sai = dev_get_drvdata(dev);
 814
 815         regcache_cache_only(sai->regmap, true);
 816         regcache_mark_dirty(sai->regmap);
 817
 818         return 0;
 819 }
 820
 821 static int fsl_sai_resume(struct device *dev)
 822 {
 823         struct fsl_sai *sai = dev_get_drvdata(dev);
 824
 825         regcache_cache_only(sai->regmap, false);
 826         regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
 827         regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
 828         msleep(1);
 829         regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
 830         regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
 831         return regcache_sync(sai->regmap);
 832 }
 833 #endif /* CONFIG_PM_SLEEP */
 834
 835 static const struct dev_pm_ops fsl_sai_pm_ops = {
 836         SET_SYSTEM_SLEEP_PM_OPS(fsl_sai_suspend, fsl_sai_resume)
 837 };
 838
 839 static struct platform_driver fsl_sai_driver = {
 840         .probe = fsl_sai_probe,
 841         .driver = {
 842                 .name = "fsl-sai",
 843                 .pm = &fsl_sai_pm_ops,
 844                 .of_match_table = fsl_sai_ids,
 845         },
 846 };
 847 module_platform_driver(fsl_sai_driver);
 848
 849 MODULE_DESCRIPTION("Freescale Soc SAI Interface");
 850 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
 851 MODULE_ALIAS("platform:fsl-sai");
 852 MODULE_LICENSE("GPL");