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[deliverable/linux.git] / sound / soc / fsl / fsl_spdif.c
1 /*
2 * Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver
3 *
4 * Copyright (C) 2013 Freescale Semiconductor, Inc.
5 *
6 * Based on stmp3xxx_spdif_dai.c
7 * Vladimir Barinov <vbarinov@embeddedalley.com>
8 * Copyright 2008 SigmaTel, Inc
9 * Copyright 2008 Embedded Alley Solutions, Inc
10 *
11 * This file is licensed under the terms of the GNU General Public License
12 * version 2. This program is licensed "as is" without any warranty of any
13 * kind, whether express or implied.
14 */
15
16 #include <linux/bitrev.h>
17 #include <linux/clk.h>
18 #include <linux/module.h>
19 #include <linux/of_address.h>
20 #include <linux/of_device.h>
21 #include <linux/of_irq.h>
22 #include <linux/regmap.h>
23
24 #include <sound/asoundef.h>
25 #include <sound/dmaengine_pcm.h>
26 #include <sound/soc.h>
27
28 #include "fsl_spdif.h"
29 #include "imx-pcm.h"
30
31 #define FSL_SPDIF_TXFIFO_WML 0x8
32 #define FSL_SPDIF_RXFIFO_WML 0x8
33
34 #define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC)
35 #define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |\
36 INT_URX_OV | INT_QRX_FUL | INT_QRX_OV |\
37 INT_UQ_SYNC | INT_UQ_ERR | INT_RXFIFO_RESYNC |\
38 INT_LOSS_LOCK | INT_DPLL_LOCKED)
39
40 #define SIE_INTR_FOR(tx) (tx ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE)
41
42 /* Index list for the values that has if (DPLL Locked) condition */
43 static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb };
44 #define SRPC_NODPLL_START1 0x5
45 #define SRPC_NODPLL_START2 0xc
46
47 #define DEFAULT_RXCLK_SRC 1
48
49 /*
50 * SPDIF control structure
51 * Defines channel status, subcode and Q sub
52 */
53 struct spdif_mixer_control {
54 /* spinlock to access control data */
55 spinlock_t ctl_lock;
56
57 /* IEC958 channel tx status bit */
58 unsigned char ch_status[4];
59
60 /* User bits */
61 unsigned char subcode[2 * SPDIF_UBITS_SIZE];
62
63 /* Q subcode part of user bits */
64 unsigned char qsub[2 * SPDIF_QSUB_SIZE];
65
66 /* Buffer offset for U/Q */
67 u32 upos;
68 u32 qpos;
69
70 /* Ready buffer index of the two buffers */
71 u32 ready_buf;
72 };
73
74 /**
75 * fsl_spdif_priv: Freescale SPDIF private data
76 *
77 * @fsl_spdif_control: SPDIF control data
78 * @cpu_dai_drv: cpu dai driver
79 * @pdev: platform device pointer
80 * @regmap: regmap handler
81 * @dpll_locked: dpll lock flag
82 * @txrate: the best rates for playback
83 * @txclk_df: STC_TXCLK_DF dividers value for playback
84 * @sysclk_df: STC_SYSCLK_DF dividers value for playback
85 * @txclk_src: STC_TXCLK_SRC values for playback
86 * @rxclk_src: SRPC_CLKSRC_SEL values for capture
87 * @txclk: tx clock sources for playback
88 * @rxclk: rx clock sources for capture
89 * @coreclk: core clock for register access via DMA
90 * @sysclk: system clock for rx clock rate measurement
91 * @dma_params_tx: DMA parameters for transmit channel
92 * @dma_params_rx: DMA parameters for receive channel
93 */
94 struct fsl_spdif_priv {
95 struct spdif_mixer_control fsl_spdif_control;
96 struct snd_soc_dai_driver cpu_dai_drv;
97 struct platform_device *pdev;
98 struct regmap *regmap;
99 bool dpll_locked;
100 u32 txrate[SPDIF_TXRATE_MAX];
101 u8 txclk_df[SPDIF_TXRATE_MAX];
102 u8 sysclk_df[SPDIF_TXRATE_MAX];
103 u8 txclk_src[SPDIF_TXRATE_MAX];
104 u8 rxclk_src;
105 struct clk *txclk[SPDIF_TXRATE_MAX];
106 struct clk *rxclk;
107 struct clk *coreclk;
108 struct clk *sysclk;
109 struct snd_dmaengine_dai_dma_data dma_params_tx;
110 struct snd_dmaengine_dai_dma_data dma_params_rx;
111 };
112
113 /* DPLL locked and lock loss interrupt handler */
114 static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv)
115 {
116 struct regmap *regmap = spdif_priv->regmap;
117 struct platform_device *pdev = spdif_priv->pdev;
118 u32 locked;
119
120 regmap_read(regmap, REG_SPDIF_SRPC, &locked);
121 locked &= SRPC_DPLL_LOCKED;
122
123 dev_dbg(&pdev->dev, "isr: Rx dpll %s \n",
124 locked ? "locked" : "loss lock");
125
126 spdif_priv->dpll_locked = locked ? true : false;
127 }
128
129 /* Receiver found illegal symbol interrupt handler */
130 static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv)
131 {
132 struct regmap *regmap = spdif_priv->regmap;
133 struct platform_device *pdev = spdif_priv->pdev;
134
135 dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n");
136
137 /* Clear illegal symbol if DPLL unlocked since no audio stream */
138 if (!spdif_priv->dpll_locked)
139 regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0);
140 }
141
142 /* U/Q Channel receive register full */
143 static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name)
144 {
145 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
146 struct regmap *regmap = spdif_priv->regmap;
147 struct platform_device *pdev = spdif_priv->pdev;
148 u32 *pos, size, val, reg;
149
150 switch (name) {
151 case 'U':
152 pos = &ctrl->upos;
153 size = SPDIF_UBITS_SIZE;
154 reg = REG_SPDIF_SRU;
155 break;
156 case 'Q':
157 pos = &ctrl->qpos;
158 size = SPDIF_QSUB_SIZE;
159 reg = REG_SPDIF_SRQ;
160 break;
161 default:
162 dev_err(&pdev->dev, "unsupported channel name\n");
163 return;
164 }
165
166 dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name);
167
168 if (*pos >= size * 2) {
169 *pos = 0;
170 } else if (unlikely((*pos % size) + 3 > size)) {
171 dev_err(&pdev->dev, "User bit receivce buffer overflow\n");
172 return;
173 }
174
175 regmap_read(regmap, reg, &val);
176 ctrl->subcode[*pos++] = val >> 16;
177 ctrl->subcode[*pos++] = val >> 8;
178 ctrl->subcode[*pos++] = val;
179 }
180
181 /* U/Q Channel sync found */
182 static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv)
183 {
184 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
185 struct platform_device *pdev = spdif_priv->pdev;
186
187 dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n");
188
189 /* U/Q buffer reset */
190 if (ctrl->qpos == 0)
191 return;
192
193 /* Set ready to this buffer */
194 ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1;
195 }
196
197 /* U/Q Channel framing error */
198 static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv)
199 {
200 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
201 struct regmap *regmap = spdif_priv->regmap;
202 struct platform_device *pdev = spdif_priv->pdev;
203 u32 val;
204
205 dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n");
206
207 /* Read U/Q data to clear the irq and do buffer reset */
208 regmap_read(regmap, REG_SPDIF_SRU, &val);
209 regmap_read(regmap, REG_SPDIF_SRQ, &val);
210
211 /* Drop this U/Q buffer */
212 ctrl->ready_buf = 0;
213 ctrl->upos = 0;
214 ctrl->qpos = 0;
215 }
216
217 /* Get spdif interrupt status and clear the interrupt */
218 static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv)
219 {
220 struct regmap *regmap = spdif_priv->regmap;
221 u32 val, val2;
222
223 regmap_read(regmap, REG_SPDIF_SIS, &val);
224 regmap_read(regmap, REG_SPDIF_SIE, &val2);
225
226 regmap_write(regmap, REG_SPDIF_SIC, val & val2);
227
228 return val;
229 }
230
231 static irqreturn_t spdif_isr(int irq, void *devid)
232 {
233 struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid;
234 struct platform_device *pdev = spdif_priv->pdev;
235 u32 sis;
236
237 sis = spdif_intr_status_clear(spdif_priv);
238
239 if (sis & INT_DPLL_LOCKED)
240 spdif_irq_dpll_lock(spdif_priv);
241
242 if (sis & INT_TXFIFO_UNOV)
243 dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n");
244
245 if (sis & INT_TXFIFO_RESYNC)
246 dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n");
247
248 if (sis & INT_CNEW)
249 dev_dbg(&pdev->dev, "isr: cstatus new\n");
250
251 if (sis & INT_VAL_NOGOOD)
252 dev_dbg(&pdev->dev, "isr: validity flag no good\n");
253
254 if (sis & INT_SYM_ERR)
255 spdif_irq_sym_error(spdif_priv);
256
257 if (sis & INT_BIT_ERR)
258 dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n");
259
260 if (sis & INT_URX_FUL)
261 spdif_irq_uqrx_full(spdif_priv, 'U');
262
263 if (sis & INT_URX_OV)
264 dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n");
265
266 if (sis & INT_QRX_FUL)
267 spdif_irq_uqrx_full(spdif_priv, 'Q');
268
269 if (sis & INT_QRX_OV)
270 dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n");
271
272 if (sis & INT_UQ_SYNC)
273 spdif_irq_uq_sync(spdif_priv);
274
275 if (sis & INT_UQ_ERR)
276 spdif_irq_uq_err(spdif_priv);
277
278 if (sis & INT_RXFIFO_UNOV)
279 dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n");
280
281 if (sis & INT_RXFIFO_RESYNC)
282 dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n");
283
284 if (sis & INT_LOSS_LOCK)
285 spdif_irq_dpll_lock(spdif_priv);
286
287 /* FIXME: Write Tx FIFO to clear TxEm */
288 if (sis & INT_TX_EM)
289 dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n");
290
291 /* FIXME: Read Rx FIFO to clear RxFIFOFul */
292 if (sis & INT_RXFIFO_FUL)
293 dev_dbg(&pdev->dev, "isr: Rx FIFO full\n");
294
295 return IRQ_HANDLED;
296 }
297
298 static int spdif_softreset(struct fsl_spdif_priv *spdif_priv)
299 {
300 struct regmap *regmap = spdif_priv->regmap;
301 u32 val, cycle = 1000;
302
303 regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET);
304
305 /*
306 * RESET bit would be cleared after finishing its reset procedure,
307 * which typically lasts 8 cycles. 1000 cycles will keep it safe.
308 */
309 do {
310 regmap_read(regmap, REG_SPDIF_SCR, &val);
311 } while ((val & SCR_SOFT_RESET) && cycle--);
312
313 if (cycle)
314 return 0;
315 else
316 return -EBUSY;
317 }
318
319 static void spdif_set_cstatus(struct spdif_mixer_control *ctrl,
320 u8 mask, u8 cstatus)
321 {
322 ctrl->ch_status[3] &= ~mask;
323 ctrl->ch_status[3] |= cstatus & mask;
324 }
325
326 static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv)
327 {
328 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
329 struct regmap *regmap = spdif_priv->regmap;
330 struct platform_device *pdev = spdif_priv->pdev;
331 u32 ch_status;
332
333 ch_status = (bitrev8(ctrl->ch_status[0]) << 16) |
334 (bitrev8(ctrl->ch_status[1]) << 8) |
335 bitrev8(ctrl->ch_status[2]);
336 regmap_write(regmap, REG_SPDIF_STCSCH, ch_status);
337
338 dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status);
339
340 ch_status = bitrev8(ctrl->ch_status[3]) << 16;
341 regmap_write(regmap, REG_SPDIF_STCSCL, ch_status);
342
343 dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status);
344 }
345
346 /* Set SPDIF PhaseConfig register for rx clock */
347 static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv,
348 enum spdif_gainsel gainsel, int dpll_locked)
349 {
350 struct regmap *regmap = spdif_priv->regmap;
351 u8 clksrc = spdif_priv->rxclk_src;
352
353 if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX)
354 return -EINVAL;
355
356 regmap_update_bits(regmap, REG_SPDIF_SRPC,
357 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
358 SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel));
359
360 return 0;
361 }
362
363 static int spdif_set_sample_rate(struct snd_pcm_substream *substream,
364 int sample_rate)
365 {
366 struct snd_soc_pcm_runtime *rtd = substream->private_data;
367 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
368 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
369 struct regmap *regmap = spdif_priv->regmap;
370 struct platform_device *pdev = spdif_priv->pdev;
371 unsigned long csfs = 0;
372 u32 stc, mask, rate;
373 u8 clk, txclk_df, sysclk_df;
374 int ret;
375
376 switch (sample_rate) {
377 case 32000:
378 rate = SPDIF_TXRATE_32000;
379 csfs = IEC958_AES3_CON_FS_32000;
380 break;
381 case 44100:
382 rate = SPDIF_TXRATE_44100;
383 csfs = IEC958_AES3_CON_FS_44100;
384 break;
385 case 48000:
386 rate = SPDIF_TXRATE_48000;
387 csfs = IEC958_AES3_CON_FS_48000;
388 break;
389 case 96000:
390 rate = SPDIF_TXRATE_96000;
391 csfs = IEC958_AES3_CON_FS_96000;
392 break;
393 case 192000:
394 rate = SPDIF_TXRATE_192000;
395 csfs = IEC958_AES3_CON_FS_192000;
396 break;
397 default:
398 dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate);
399 return -EINVAL;
400 }
401
402 clk = spdif_priv->txclk_src[rate];
403 if (clk >= STC_TXCLK_SRC_MAX) {
404 dev_err(&pdev->dev, "tx clock source is out of range\n");
405 return -EINVAL;
406 }
407
408 txclk_df = spdif_priv->txclk_df[rate];
409 if (txclk_df == 0) {
410 dev_err(&pdev->dev, "the txclk_df can't be zero\n");
411 return -EINVAL;
412 }
413
414 sysclk_df = spdif_priv->sysclk_df[rate];
415
416 /* Don't mess up the clocks from other modules */
417 if (clk != STC_TXCLK_SPDIF_ROOT)
418 goto clk_set_bypass;
419
420 /* The S/PDIF block needs a clock of 64 * fs * txclk_df */
421 ret = clk_set_rate(spdif_priv->txclk[rate],
422 64 * sample_rate * txclk_df);
423 if (ret) {
424 dev_err(&pdev->dev, "failed to set tx clock rate\n");
425 return ret;
426 }
427
428 clk_set_bypass:
429 dev_dbg(&pdev->dev, "expected clock rate = %d\n",
430 (64 * sample_rate * txclk_df * sysclk_df));
431 dev_dbg(&pdev->dev, "actual clock rate = %ld\n",
432 clk_get_rate(spdif_priv->txclk[rate]));
433
434 /* set fs field in consumer channel status */
435 spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs);
436
437 /* select clock source and divisor */
438 stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) |
439 STC_TXCLK_DF(txclk_df) | STC_SYSCLK_DF(sysclk_df);
440 mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK |
441 STC_TXCLK_DF_MASK | STC_SYSCLK_DF_MASK;
442 regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc);
443
444 dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n",
445 spdif_priv->txrate[rate], sample_rate);
446
447 return 0;
448 }
449
450 static int fsl_spdif_startup(struct snd_pcm_substream *substream,
451 struct snd_soc_dai *cpu_dai)
452 {
453 struct snd_soc_pcm_runtime *rtd = substream->private_data;
454 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
455 struct platform_device *pdev = spdif_priv->pdev;
456 struct regmap *regmap = spdif_priv->regmap;
457 u32 scr, mask;
458 int i;
459 int ret;
460
461 /* Reset module and interrupts only for first initialization */
462 if (!cpu_dai->active) {
463 ret = clk_prepare_enable(spdif_priv->coreclk);
464 if (ret) {
465 dev_err(&pdev->dev, "failed to enable core clock\n");
466 return ret;
467 }
468
469 ret = spdif_softreset(spdif_priv);
470 if (ret) {
471 dev_err(&pdev->dev, "failed to soft reset\n");
472 goto err;
473 }
474
475 /* Disable all the interrupts */
476 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0);
477 }
478
479 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
480 scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL |
481 SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP |
482 SCR_TXFIFO_FSEL_IF8;
483 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
484 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
485 SCR_TXFIFO_FSEL_MASK;
486 for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
487 ret = clk_prepare_enable(spdif_priv->txclk[i]);
488 if (ret)
489 goto disable_txclk;
490 }
491 } else {
492 scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC;
493 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
494 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
495 ret = clk_prepare_enable(spdif_priv->rxclk);
496 if (ret)
497 goto err;
498 }
499 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
500
501 /* Power up SPDIF module */
502 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0);
503
504 return 0;
505
506 disable_txclk:
507 for (i--; i >= 0; i--)
508 clk_disable_unprepare(spdif_priv->txclk[i]);
509 err:
510 clk_disable_unprepare(spdif_priv->coreclk);
511
512 return ret;
513 }
514
515 static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,
516 struct snd_soc_dai *cpu_dai)
517 {
518 struct snd_soc_pcm_runtime *rtd = substream->private_data;
519 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
520 struct regmap *regmap = spdif_priv->regmap;
521 u32 scr, mask, i;
522
523 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
524 scr = 0;
525 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
526 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
527 SCR_TXFIFO_FSEL_MASK;
528 for (i = 0; i < SPDIF_TXRATE_MAX; i++)
529 clk_disable_unprepare(spdif_priv->txclk[i]);
530 } else {
531 scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO;
532 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
533 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
534 clk_disable_unprepare(spdif_priv->rxclk);
535 }
536 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
537
538 /* Power down SPDIF module only if tx&rx are both inactive */
539 if (!cpu_dai->active) {
540 spdif_intr_status_clear(spdif_priv);
541 regmap_update_bits(regmap, REG_SPDIF_SCR,
542 SCR_LOW_POWER, SCR_LOW_POWER);
543 clk_disable_unprepare(spdif_priv->coreclk);
544 }
545 }
546
547 static int fsl_spdif_hw_params(struct snd_pcm_substream *substream,
548 struct snd_pcm_hw_params *params,
549 struct snd_soc_dai *dai)
550 {
551 struct snd_soc_pcm_runtime *rtd = substream->private_data;
552 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
553 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
554 struct platform_device *pdev = spdif_priv->pdev;
555 u32 sample_rate = params_rate(params);
556 int ret = 0;
557
558 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
559 ret = spdif_set_sample_rate(substream, sample_rate);
560 if (ret) {
561 dev_err(&pdev->dev, "%s: set sample rate failed: %d\n",
562 __func__, sample_rate);
563 return ret;
564 }
565 spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK,
566 IEC958_AES3_CON_CLOCK_1000PPM);
567 spdif_write_channel_status(spdif_priv);
568 } else {
569 /* Setup rx clock source */
570 ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1);
571 }
572
573 return ret;
574 }
575
576 static int fsl_spdif_trigger(struct snd_pcm_substream *substream,
577 int cmd, struct snd_soc_dai *dai)
578 {
579 struct snd_soc_pcm_runtime *rtd = substream->private_data;
580 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
581 struct regmap *regmap = spdif_priv->regmap;
582 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
583 u32 intr = SIE_INTR_FOR(tx);
584 u32 dmaen = SCR_DMA_xX_EN(tx);
585
586 switch (cmd) {
587 case SNDRV_PCM_TRIGGER_START:
588 case SNDRV_PCM_TRIGGER_RESUME:
589 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
590 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr);
591 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen);
592 break;
593 case SNDRV_PCM_TRIGGER_STOP:
594 case SNDRV_PCM_TRIGGER_SUSPEND:
595 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
596 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0);
597 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0);
598 break;
599 default:
600 return -EINVAL;
601 }
602
603 return 0;
604 }
605
606 static struct snd_soc_dai_ops fsl_spdif_dai_ops = {
607 .startup = fsl_spdif_startup,
608 .hw_params = fsl_spdif_hw_params,
609 .trigger = fsl_spdif_trigger,
610 .shutdown = fsl_spdif_shutdown,
611 };
612
613
614 /*
615 * FSL SPDIF IEC958 controller(mixer) functions
616 *
617 * Channel status get/put control
618 * User bit value get/put control
619 * Valid bit value get control
620 * DPLL lock status get control
621 * User bit sync mode selection control
622 */
623
624 static int fsl_spdif_info(struct snd_kcontrol *kcontrol,
625 struct snd_ctl_elem_info *uinfo)
626 {
627 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
628 uinfo->count = 1;
629
630 return 0;
631 }
632
633 static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol,
634 struct snd_ctl_elem_value *uvalue)
635 {
636 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
637 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
638 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
639
640 uvalue->value.iec958.status[0] = ctrl->ch_status[0];
641 uvalue->value.iec958.status[1] = ctrl->ch_status[1];
642 uvalue->value.iec958.status[2] = ctrl->ch_status[2];
643 uvalue->value.iec958.status[3] = ctrl->ch_status[3];
644
645 return 0;
646 }
647
648 static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol,
649 struct snd_ctl_elem_value *uvalue)
650 {
651 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
652 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
653 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
654
655 ctrl->ch_status[0] = uvalue->value.iec958.status[0];
656 ctrl->ch_status[1] = uvalue->value.iec958.status[1];
657 ctrl->ch_status[2] = uvalue->value.iec958.status[2];
658 ctrl->ch_status[3] = uvalue->value.iec958.status[3];
659
660 spdif_write_channel_status(spdif_priv);
661
662 return 0;
663 }
664
665 /* Get channel status from SPDIF_RX_CCHAN register */
666 static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol,
667 struct snd_ctl_elem_value *ucontrol)
668 {
669 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
670 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
671 struct regmap *regmap = spdif_priv->regmap;
672 u32 cstatus, val;
673
674 regmap_read(regmap, REG_SPDIF_SIS, &val);
675 if (!(val & INT_CNEW))
676 return -EAGAIN;
677
678 regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus);
679 ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF;
680 ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF;
681 ucontrol->value.iec958.status[2] = cstatus & 0xFF;
682
683 regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus);
684 ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF;
685 ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF;
686 ucontrol->value.iec958.status[5] = cstatus & 0xFF;
687
688 /* Clear intr */
689 regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW);
690
691 return 0;
692 }
693
694 /*
695 * Get User bits (subcode) from chip value which readed out
696 * in UChannel register.
697 */
698 static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol,
699 struct snd_ctl_elem_value *ucontrol)
700 {
701 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
702 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
703 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
704 unsigned long flags;
705 int ret = -EAGAIN;
706
707 spin_lock_irqsave(&ctrl->ctl_lock, flags);
708 if (ctrl->ready_buf) {
709 int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE;
710 memcpy(&ucontrol->value.iec958.subcode[0],
711 &ctrl->subcode[idx], SPDIF_UBITS_SIZE);
712 ret = 0;
713 }
714 spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
715
716 return ret;
717 }
718
719 /* Q-subcode information. The byte size is SPDIF_UBITS_SIZE/8 */
720 static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol,
721 struct snd_ctl_elem_info *uinfo)
722 {
723 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
724 uinfo->count = SPDIF_QSUB_SIZE;
725
726 return 0;
727 }
728
729 /* Get Q subcode from chip value which readed out in QChannel register */
730 static int fsl_spdif_qget(struct snd_kcontrol *kcontrol,
731 struct snd_ctl_elem_value *ucontrol)
732 {
733 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
734 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
735 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
736 unsigned long flags;
737 int ret = -EAGAIN;
738
739 spin_lock_irqsave(&ctrl->ctl_lock, flags);
740 if (ctrl->ready_buf) {
741 int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE;
742 memcpy(&ucontrol->value.bytes.data[0],
743 &ctrl->qsub[idx], SPDIF_QSUB_SIZE);
744 ret = 0;
745 }
746 spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
747
748 return ret;
749 }
750
751 /* Valid bit information */
752 static int fsl_spdif_vbit_info(struct snd_kcontrol *kcontrol,
753 struct snd_ctl_elem_info *uinfo)
754 {
755 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
756 uinfo->count = 1;
757 uinfo->value.integer.min = 0;
758 uinfo->value.integer.max = 1;
759
760 return 0;
761 }
762
763 /* Get valid good bit from interrupt status register */
764 static int fsl_spdif_vbit_get(struct snd_kcontrol *kcontrol,
765 struct snd_ctl_elem_value *ucontrol)
766 {
767 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
768 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
769 struct regmap *regmap = spdif_priv->regmap;
770 u32 val;
771
772 regmap_read(regmap, REG_SPDIF_SIS, &val);
773 ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0;
774 regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD);
775
776 return 0;
777 }
778
779 /* DPLL lock information */
780 static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol,
781 struct snd_ctl_elem_info *uinfo)
782 {
783 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
784 uinfo->count = 1;
785 uinfo->value.integer.min = 16000;
786 uinfo->value.integer.max = 96000;
787
788 return 0;
789 }
790
791 static u32 gainsel_multi[GAINSEL_MULTI_MAX] = {
792 24, 16, 12, 8, 6, 4, 3,
793 };
794
795 /* Get RX data clock rate given the SPDIF bus_clk */
796 static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv,
797 enum spdif_gainsel gainsel)
798 {
799 struct regmap *regmap = spdif_priv->regmap;
800 struct platform_device *pdev = spdif_priv->pdev;
801 u64 tmpval64, busclk_freq = 0;
802 u32 freqmeas, phaseconf;
803 u8 clksrc;
804
805 regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas);
806 regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf);
807
808 clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf;
809
810 /* Get bus clock from system */
811 if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED))
812 busclk_freq = clk_get_rate(spdif_priv->sysclk);
813
814 /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */
815 tmpval64 = (u64) busclk_freq * freqmeas;
816 do_div(tmpval64, gainsel_multi[gainsel] * 1024);
817 do_div(tmpval64, 128 * 1024);
818
819 dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas);
820 dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq);
821 dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64);
822
823 return (int)tmpval64;
824 }
825
826 /*
827 * Get DPLL lock or not info from stable interrupt status register.
828 * User application must use this control to get locked,
829 * then can do next PCM operation
830 */
831 static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol,
832 struct snd_ctl_elem_value *ucontrol)
833 {
834 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
835 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
836 int rate = 0;
837
838 if (spdif_priv->dpll_locked)
839 rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL);
840
841 ucontrol->value.integer.value[0] = rate;
842
843 return 0;
844 }
845
846 /* User bit sync mode info */
847 static int fsl_spdif_usync_info(struct snd_kcontrol *kcontrol,
848 struct snd_ctl_elem_info *uinfo)
849 {
850 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
851 uinfo->count = 1;
852 uinfo->value.integer.min = 0;
853 uinfo->value.integer.max = 1;
854
855 return 0;
856 }
857
858 /*
859 * User bit sync mode:
860 * 1 CD User channel subcode
861 * 0 Non-CD data
862 */
863 static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol,
864 struct snd_ctl_elem_value *ucontrol)
865 {
866 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
867 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
868 struct regmap *regmap = spdif_priv->regmap;
869 u32 val;
870
871 regmap_read(regmap, REG_SPDIF_SRCD, &val);
872 ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0;
873
874 return 0;
875 }
876
877 /*
878 * User bit sync mode:
879 * 1 CD User channel subcode
880 * 0 Non-CD data
881 */
882 static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol,
883 struct snd_ctl_elem_value *ucontrol)
884 {
885 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
886 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
887 struct regmap *regmap = spdif_priv->regmap;
888 u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET;
889
890 regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val);
891
892 return 0;
893 }
894
895 /* FSL SPDIF IEC958 controller defines */
896 static struct snd_kcontrol_new fsl_spdif_ctrls[] = {
897 /* Status cchanel controller */
898 {
899 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
900 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
901 .access = SNDRV_CTL_ELEM_ACCESS_READ |
902 SNDRV_CTL_ELEM_ACCESS_WRITE |
903 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
904 .info = fsl_spdif_info,
905 .get = fsl_spdif_pb_get,
906 .put = fsl_spdif_pb_put,
907 },
908 {
909 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
910 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
911 .access = SNDRV_CTL_ELEM_ACCESS_READ |
912 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
913 .info = fsl_spdif_info,
914 .get = fsl_spdif_capture_get,
915 },
916 /* User bits controller */
917 {
918 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
919 .name = "IEC958 Subcode Capture Default",
920 .access = SNDRV_CTL_ELEM_ACCESS_READ |
921 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
922 .info = fsl_spdif_info,
923 .get = fsl_spdif_subcode_get,
924 },
925 {
926 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
927 .name = "IEC958 Q-subcode Capture Default",
928 .access = SNDRV_CTL_ELEM_ACCESS_READ |
929 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
930 .info = fsl_spdif_qinfo,
931 .get = fsl_spdif_qget,
932 },
933 /* Valid bit error controller */
934 {
935 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
936 .name = "IEC958 V-Bit Errors",
937 .access = SNDRV_CTL_ELEM_ACCESS_READ |
938 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
939 .info = fsl_spdif_vbit_info,
940 .get = fsl_spdif_vbit_get,
941 },
942 /* DPLL lock info get controller */
943 {
944 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
945 .name = "RX Sample Rate",
946 .access = SNDRV_CTL_ELEM_ACCESS_READ |
947 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
948 .info = fsl_spdif_rxrate_info,
949 .get = fsl_spdif_rxrate_get,
950 },
951 /* User bit sync mode set/get controller */
952 {
953 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
954 .name = "IEC958 USyncMode CDText",
955 .access = SNDRV_CTL_ELEM_ACCESS_READ |
956 SNDRV_CTL_ELEM_ACCESS_WRITE |
957 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
958 .info = fsl_spdif_usync_info,
959 .get = fsl_spdif_usync_get,
960 .put = fsl_spdif_usync_put,
961 },
962 };
963
964 static int fsl_spdif_dai_probe(struct snd_soc_dai *dai)
965 {
966 struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai);
967
968 snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx,
969 &spdif_private->dma_params_rx);
970
971 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls));
972
973 return 0;
974 }
975
976 static struct snd_soc_dai_driver fsl_spdif_dai = {
977 .probe = &fsl_spdif_dai_probe,
978 .playback = {
979 .stream_name = "CPU-Playback",
980 .channels_min = 2,
981 .channels_max = 2,
982 .rates = FSL_SPDIF_RATES_PLAYBACK,
983 .formats = FSL_SPDIF_FORMATS_PLAYBACK,
984 },
985 .capture = {
986 .stream_name = "CPU-Capture",
987 .channels_min = 2,
988 .channels_max = 2,
989 .rates = FSL_SPDIF_RATES_CAPTURE,
990 .formats = FSL_SPDIF_FORMATS_CAPTURE,
991 },
992 .ops = &fsl_spdif_dai_ops,
993 };
994
995 static const struct snd_soc_component_driver fsl_spdif_component = {
996 .name = "fsl-spdif",
997 };
998
999 /* FSL SPDIF REGMAP */
1000
1001 static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg)
1002 {
1003 switch (reg) {
1004 case REG_SPDIF_SCR:
1005 case REG_SPDIF_SRCD:
1006 case REG_SPDIF_SRPC:
1007 case REG_SPDIF_SIE:
1008 case REG_SPDIF_SIS:
1009 case REG_SPDIF_SRL:
1010 case REG_SPDIF_SRR:
1011 case REG_SPDIF_SRCSH:
1012 case REG_SPDIF_SRCSL:
1013 case REG_SPDIF_SRU:
1014 case REG_SPDIF_SRQ:
1015 case REG_SPDIF_STCSCH:
1016 case REG_SPDIF_STCSCL:
1017 case REG_SPDIF_SRFM:
1018 case REG_SPDIF_STC:
1019 return true;
1020 default:
1021 return false;
1022 }
1023 }
1024
1025 static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg)
1026 {
1027 switch (reg) {
1028 case REG_SPDIF_SCR:
1029 case REG_SPDIF_SRCD:
1030 case REG_SPDIF_SRPC:
1031 case REG_SPDIF_SIE:
1032 case REG_SPDIF_SIC:
1033 case REG_SPDIF_STL:
1034 case REG_SPDIF_STR:
1035 case REG_SPDIF_STCSCH:
1036 case REG_SPDIF_STCSCL:
1037 case REG_SPDIF_STC:
1038 return true;
1039 default:
1040 return false;
1041 }
1042 }
1043
1044 static const struct regmap_config fsl_spdif_regmap_config = {
1045 .reg_bits = 32,
1046 .reg_stride = 4,
1047 .val_bits = 32,
1048
1049 .max_register = REG_SPDIF_STC,
1050 .readable_reg = fsl_spdif_readable_reg,
1051 .writeable_reg = fsl_spdif_writeable_reg,
1052 };
1053
1054 static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv,
1055 struct clk *clk, u64 savesub,
1056 enum spdif_txrate index, bool round)
1057 {
1058 const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 };
1059 bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk);
1060 u64 rate_ideal, rate_actual, sub;
1061 u32 sysclk_dfmin, sysclk_dfmax;
1062 u32 txclk_df, sysclk_df, arate;
1063
1064 /* The sysclk has an extra divisor [2, 512] */
1065 sysclk_dfmin = is_sysclk ? 2 : 1;
1066 sysclk_dfmax = is_sysclk ? 512 : 1;
1067
1068 for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) {
1069 for (txclk_df = 1; txclk_df <= 128; txclk_df++) {
1070 rate_ideal = rate[index] * txclk_df * 64;
1071 if (round)
1072 rate_actual = clk_round_rate(clk, rate_ideal);
1073 else
1074 rate_actual = clk_get_rate(clk);
1075
1076 arate = rate_actual / 64;
1077 arate /= txclk_df * sysclk_df;
1078
1079 if (arate == rate[index]) {
1080 /* We are lucky */
1081 savesub = 0;
1082 spdif_priv->txclk_df[index] = txclk_df;
1083 spdif_priv->sysclk_df[index] = sysclk_df;
1084 spdif_priv->txrate[index] = arate;
1085 goto out;
1086 } else if (arate / rate[index] == 1) {
1087 /* A little bigger than expect */
1088 sub = (u64)(arate - rate[index]) * 100000;
1089 do_div(sub, rate[index]);
1090 if (sub >= savesub)
1091 continue;
1092 savesub = sub;
1093 spdif_priv->txclk_df[index] = txclk_df;
1094 spdif_priv->sysclk_df[index] = sysclk_df;
1095 spdif_priv->txrate[index] = arate;
1096 } else if (rate[index] / arate == 1) {
1097 /* A little smaller than expect */
1098 sub = (u64)(rate[index] - arate) * 100000;
1099 do_div(sub, rate[index]);
1100 if (sub >= savesub)
1101 continue;
1102 savesub = sub;
1103 spdif_priv->txclk_df[index] = txclk_df;
1104 spdif_priv->sysclk_df[index] = sysclk_df;
1105 spdif_priv->txrate[index] = arate;
1106 }
1107 }
1108 }
1109
1110 out:
1111 return savesub;
1112 }
1113
1114 static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv,
1115 enum spdif_txrate index)
1116 {
1117 const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 };
1118 struct platform_device *pdev = spdif_priv->pdev;
1119 struct device *dev = &pdev->dev;
1120 u64 savesub = 100000, ret;
1121 struct clk *clk;
1122 char tmp[16];
1123 int i;
1124
1125 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
1126 sprintf(tmp, "rxtx%d", i);
1127 clk = devm_clk_get(&pdev->dev, tmp);
1128 if (IS_ERR(clk)) {
1129 dev_err(dev, "no rxtx%d clock in devicetree\n", i);
1130 return PTR_ERR(clk);
1131 }
1132 if (!clk_get_rate(clk))
1133 continue;
1134
1135 ret = fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index,
1136 i == STC_TXCLK_SPDIF_ROOT);
1137 if (savesub == ret)
1138 continue;
1139
1140 savesub = ret;
1141 spdif_priv->txclk[index] = clk;
1142 spdif_priv->txclk_src[index] = i;
1143
1144 /* To quick catch a divisor, we allow a 0.1% deviation */
1145 if (savesub < 100)
1146 break;
1147 }
1148
1149 dev_dbg(&pdev->dev, "use rxtx%d as tx clock source for %dHz sample rate\n",
1150 spdif_priv->txclk_src[index], rate[index]);
1151 dev_dbg(&pdev->dev, "use txclk df %d for %dHz sample rate\n",
1152 spdif_priv->txclk_df[index], rate[index]);
1153 if (clk_is_match(spdif_priv->txclk[index], spdif_priv->sysclk))
1154 dev_dbg(&pdev->dev, "use sysclk df %d for %dHz sample rate\n",
1155 spdif_priv->sysclk_df[index], rate[index]);
1156 dev_dbg(&pdev->dev, "the best rate for %dHz sample rate is %dHz\n",
1157 rate[index], spdif_priv->txrate[index]);
1158
1159 return 0;
1160 }
1161
1162 static int fsl_spdif_probe(struct platform_device *pdev)
1163 {
1164 struct device_node *np = pdev->dev.of_node;
1165 struct fsl_spdif_priv *spdif_priv;
1166 struct spdif_mixer_control *ctrl;
1167 struct resource *res;
1168 void __iomem *regs;
1169 int irq, ret, i;
1170
1171 if (!np)
1172 return -ENODEV;
1173
1174 spdif_priv = devm_kzalloc(&pdev->dev, sizeof(*spdif_priv), GFP_KERNEL);
1175 if (!spdif_priv)
1176 return -ENOMEM;
1177
1178 spdif_priv->pdev = pdev;
1179
1180 /* Initialize this copy of the CPU DAI driver structure */
1181 memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai));
1182 spdif_priv->cpu_dai_drv.name = dev_name(&pdev->dev);
1183
1184 /* Get the addresses and IRQ */
1185 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1186 regs = devm_ioremap_resource(&pdev->dev, res);
1187 if (IS_ERR(regs))
1188 return PTR_ERR(regs);
1189
1190 spdif_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
1191 "core", regs, &fsl_spdif_regmap_config);
1192 if (IS_ERR(spdif_priv->regmap)) {
1193 dev_err(&pdev->dev, "regmap init failed\n");
1194 return PTR_ERR(spdif_priv->regmap);
1195 }
1196
1197 irq = platform_get_irq(pdev, 0);
1198 if (irq < 0) {
1199 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
1200 return irq;
1201 }
1202
1203 ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0,
1204 dev_name(&pdev->dev), spdif_priv);
1205 if (ret) {
1206 dev_err(&pdev->dev, "could not claim irq %u\n", irq);
1207 return ret;
1208 }
1209
1210 /* Get system clock for rx clock rate calculation */
1211 spdif_priv->sysclk = devm_clk_get(&pdev->dev, "rxtx5");
1212 if (IS_ERR(spdif_priv->sysclk)) {
1213 dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n");
1214 return PTR_ERR(spdif_priv->sysclk);
1215 }
1216
1217 /* Get core clock for data register access via DMA */
1218 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core");
1219 if (IS_ERR(spdif_priv->coreclk)) {
1220 dev_err(&pdev->dev, "no core clock in devicetree\n");
1221 return PTR_ERR(spdif_priv->coreclk);
1222 }
1223
1224 /* Select clock source for rx/tx clock */
1225 spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1");
1226 if (IS_ERR(spdif_priv->rxclk)) {
1227 dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n");
1228 return PTR_ERR(spdif_priv->rxclk);
1229 }
1230 spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC;
1231
1232 for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
1233 ret = fsl_spdif_probe_txclk(spdif_priv, i);
1234 if (ret)
1235 return ret;
1236 }
1237
1238 /* Initial spinlock for control data */
1239 ctrl = &spdif_priv->fsl_spdif_control;
1240 spin_lock_init(&ctrl->ctl_lock);
1241
1242 /* Init tx channel status default value */
1243 ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT |
1244 IEC958_AES0_CON_EMPHASIS_5015;
1245 ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID;
1246 ctrl->ch_status[2] = 0x00;
1247 ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 |
1248 IEC958_AES3_CON_CLOCK_1000PPM;
1249
1250 spdif_priv->dpll_locked = false;
1251
1252 spdif_priv->dma_params_tx.maxburst = FSL_SPDIF_TXFIFO_WML;
1253 spdif_priv->dma_params_rx.maxburst = FSL_SPDIF_RXFIFO_WML;
1254 spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL;
1255 spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL;
1256
1257 /* Register with ASoC */
1258 dev_set_drvdata(&pdev->dev, spdif_priv);
1259
1260 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component,
1261 &spdif_priv->cpu_dai_drv, 1);
1262 if (ret) {
1263 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1264 return ret;
1265 }
1266
1267 ret = imx_pcm_dma_init(pdev, IMX_SPDIF_DMABUF_SIZE);
1268 if (ret)
1269 dev_err(&pdev->dev, "imx_pcm_dma_init failed: %d\n", ret);
1270
1271 return ret;
1272 }
1273
1274 static const struct of_device_id fsl_spdif_dt_ids[] = {
1275 { .compatible = "fsl,imx35-spdif", },
1276 { .compatible = "fsl,vf610-spdif", },
1277 {}
1278 };
1279 MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids);
1280
1281 static struct platform_driver fsl_spdif_driver = {
1282 .driver = {
1283 .name = "fsl-spdif-dai",
1284 .of_match_table = fsl_spdif_dt_ids,
1285 },
1286 .probe = fsl_spdif_probe,
1287 };
1288
1289 module_platform_driver(fsl_spdif_driver);
1290
1291 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1292 MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver");
1293 MODULE_LICENSE("GPL v2");
1294 MODULE_ALIAS("platform:fsl-spdif-dai");
Linux kernel - Deliverables
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