2 * Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver
4 * Copyright (C) 2013 Freescale Semiconductor, Inc.
6 * Based on stmp3xxx_spdif_dai.c
7 * Vladimir Barinov <vbarinov@embeddedalley.com>
8 * Copyright 2008 SigmaTel, Inc
9 * Copyright 2008 Embedded Alley Solutions, Inc
11 * This file is licensed under the terms of the GNU General Public License
12 * version 2. This program is licensed "as is" without any warranty of any
13 * kind, whether express or implied.
16 #include <linux/bitrev.h>
17 #include <linux/clk.h>
18 #include <linux/module.h>
19 #include <linux/of_address.h>
20 #include <linux/of_device.h>
21 #include <linux/of_irq.h>
22 #include <linux/regmap.h>
24 #include <sound/asoundef.h>
25 #include <sound/dmaengine_pcm.h>
26 #include <sound/soc.h>
28 #include "fsl_spdif.h"
31 #define FSL_SPDIF_TXFIFO_WML 0x8
32 #define FSL_SPDIF_RXFIFO_WML 0x8
34 #define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC)
35 #define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |\
36 INT_URX_OV | INT_QRX_FUL | INT_QRX_OV |\
37 INT_UQ_SYNC | INT_UQ_ERR | INT_RXFIFO_RESYNC |\
38 INT_LOSS_LOCK | INT_DPLL_LOCKED)
40 #define SIE_INTR_FOR(tx) (tx ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE)
42 /* Index list for the values that has if (DPLL Locked) condition */
43 static u8 srpc_dpll_locked
[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb };
44 #define SRPC_NODPLL_START1 0x5
45 #define SRPC_NODPLL_START2 0xc
47 #define DEFAULT_RXCLK_SRC 1
50 * SPDIF control structure
51 * Defines channel status, subcode and Q sub
53 struct spdif_mixer_control
{
54 /* spinlock to access control data */
57 /* IEC958 channel tx status bit */
58 unsigned char ch_status
[4];
61 unsigned char subcode
[2 * SPDIF_UBITS_SIZE
];
63 /* Q subcode part of user bits */
64 unsigned char qsub
[2 * SPDIF_QSUB_SIZE
];
66 /* Buffer offset for U/Q */
70 /* Ready buffer index of the two buffers */
75 * fsl_spdif_priv: Freescale SPDIF private data
77 * @fsl_spdif_control: SPDIF control data
78 * @cpu_dai_drv: cpu dai driver
79 * @pdev: platform device pointer
80 * @regmap: regmap handler
81 * @dpll_locked: dpll lock flag
82 * @txrate: the best rates for playback
83 * @txclk_df: STC_TXCLK_DF dividers value for playback
84 * @sysclk_df: STC_SYSCLK_DF dividers value for playback
85 * @txclk_src: STC_TXCLK_SRC values for playback
86 * @rxclk_src: SRPC_CLKSRC_SEL values for capture
87 * @txclk: tx clock sources for playback
88 * @rxclk: rx clock sources for capture
89 * @coreclk: core clock for register access via DMA
90 * @sysclk: system clock for rx clock rate measurement
91 * @dma_params_tx: DMA parameters for transmit channel
92 * @dma_params_rx: DMA parameters for receive channel
94 struct fsl_spdif_priv
{
95 struct spdif_mixer_control fsl_spdif_control
;
96 struct snd_soc_dai_driver cpu_dai_drv
;
97 struct platform_device
*pdev
;
98 struct regmap
*regmap
;
100 u32 txrate
[SPDIF_TXRATE_MAX
];
101 u8 txclk_df
[SPDIF_TXRATE_MAX
];
102 u8 sysclk_df
[SPDIF_TXRATE_MAX
];
103 u8 txclk_src
[SPDIF_TXRATE_MAX
];
105 struct clk
*txclk
[SPDIF_TXRATE_MAX
];
109 struct snd_dmaengine_dai_dma_data dma_params_tx
;
110 struct snd_dmaengine_dai_dma_data dma_params_rx
;
113 /* DPLL locked and lock loss interrupt handler */
114 static void spdif_irq_dpll_lock(struct fsl_spdif_priv
*spdif_priv
)
116 struct regmap
*regmap
= spdif_priv
->regmap
;
117 struct platform_device
*pdev
= spdif_priv
->pdev
;
120 regmap_read(regmap
, REG_SPDIF_SRPC
, &locked
);
121 locked
&= SRPC_DPLL_LOCKED
;
123 dev_dbg(&pdev
->dev
, "isr: Rx dpll %s \n",
124 locked
? "locked" : "loss lock");
126 spdif_priv
->dpll_locked
= locked
? true : false;
129 /* Receiver found illegal symbol interrupt handler */
130 static void spdif_irq_sym_error(struct fsl_spdif_priv
*spdif_priv
)
132 struct regmap
*regmap
= spdif_priv
->regmap
;
133 struct platform_device
*pdev
= spdif_priv
->pdev
;
135 dev_dbg(&pdev
->dev
, "isr: receiver found illegal symbol\n");
137 /* Clear illegal symbol if DPLL unlocked since no audio stream */
138 if (!spdif_priv
->dpll_locked
)
139 regmap_update_bits(regmap
, REG_SPDIF_SIE
, INT_SYM_ERR
, 0);
142 /* U/Q Channel receive register full */
143 static void spdif_irq_uqrx_full(struct fsl_spdif_priv
*spdif_priv
, char name
)
145 struct spdif_mixer_control
*ctrl
= &spdif_priv
->fsl_spdif_control
;
146 struct regmap
*regmap
= spdif_priv
->regmap
;
147 struct platform_device
*pdev
= spdif_priv
->pdev
;
148 u32
*pos
, size
, val
, reg
;
153 size
= SPDIF_UBITS_SIZE
;
158 size
= SPDIF_QSUB_SIZE
;
162 dev_err(&pdev
->dev
, "unsupported channel name\n");
166 dev_dbg(&pdev
->dev
, "isr: %c Channel receive register full\n", name
);
168 if (*pos
>= size
* 2) {
170 } else if (unlikely((*pos
% size
) + 3 > size
)) {
171 dev_err(&pdev
->dev
, "User bit receivce buffer overflow\n");
175 regmap_read(regmap
, reg
, &val
);
176 ctrl
->subcode
[*pos
++] = val
>> 16;
177 ctrl
->subcode
[*pos
++] = val
>> 8;
178 ctrl
->subcode
[*pos
++] = val
;
181 /* U/Q Channel sync found */
182 static void spdif_irq_uq_sync(struct fsl_spdif_priv
*spdif_priv
)
184 struct spdif_mixer_control
*ctrl
= &spdif_priv
->fsl_spdif_control
;
185 struct platform_device
*pdev
= spdif_priv
->pdev
;
187 dev_dbg(&pdev
->dev
, "isr: U/Q Channel sync found\n");
189 /* U/Q buffer reset */
193 /* Set ready to this buffer */
194 ctrl
->ready_buf
= (ctrl
->qpos
- 1) / SPDIF_QSUB_SIZE
+ 1;
197 /* U/Q Channel framing error */
198 static void spdif_irq_uq_err(struct fsl_spdif_priv
*spdif_priv
)
200 struct spdif_mixer_control
*ctrl
= &spdif_priv
->fsl_spdif_control
;
201 struct regmap
*regmap
= spdif_priv
->regmap
;
202 struct platform_device
*pdev
= spdif_priv
->pdev
;
205 dev_dbg(&pdev
->dev
, "isr: U/Q Channel framing error\n");
207 /* Read U/Q data to clear the irq and do buffer reset */
208 regmap_read(regmap
, REG_SPDIF_SRU
, &val
);
209 regmap_read(regmap
, REG_SPDIF_SRQ
, &val
);
211 /* Drop this U/Q buffer */
217 /* Get spdif interrupt status and clear the interrupt */
218 static u32
spdif_intr_status_clear(struct fsl_spdif_priv
*spdif_priv
)
220 struct regmap
*regmap
= spdif_priv
->regmap
;
223 regmap_read(regmap
, REG_SPDIF_SIS
, &val
);
224 regmap_read(regmap
, REG_SPDIF_SIE
, &val2
);
226 regmap_write(regmap
, REG_SPDIF_SIC
, val
& val2
);
231 static irqreturn_t
spdif_isr(int irq
, void *devid
)
233 struct fsl_spdif_priv
*spdif_priv
= (struct fsl_spdif_priv
*)devid
;
234 struct platform_device
*pdev
= spdif_priv
->pdev
;
237 sis
= spdif_intr_status_clear(spdif_priv
);
239 if (sis
& INT_DPLL_LOCKED
)
240 spdif_irq_dpll_lock(spdif_priv
);
242 if (sis
& INT_TXFIFO_UNOV
)
243 dev_dbg(&pdev
->dev
, "isr: Tx FIFO under/overrun\n");
245 if (sis
& INT_TXFIFO_RESYNC
)
246 dev_dbg(&pdev
->dev
, "isr: Tx FIFO resync\n");
249 dev_dbg(&pdev
->dev
, "isr: cstatus new\n");
251 if (sis
& INT_VAL_NOGOOD
)
252 dev_dbg(&pdev
->dev
, "isr: validity flag no good\n");
254 if (sis
& INT_SYM_ERR
)
255 spdif_irq_sym_error(spdif_priv
);
257 if (sis
& INT_BIT_ERR
)
258 dev_dbg(&pdev
->dev
, "isr: receiver found parity bit error\n");
260 if (sis
& INT_URX_FUL
)
261 spdif_irq_uqrx_full(spdif_priv
, 'U');
263 if (sis
& INT_URX_OV
)
264 dev_dbg(&pdev
->dev
, "isr: U Channel receive register overrun\n");
266 if (sis
& INT_QRX_FUL
)
267 spdif_irq_uqrx_full(spdif_priv
, 'Q');
269 if (sis
& INT_QRX_OV
)
270 dev_dbg(&pdev
->dev
, "isr: Q Channel receive register overrun\n");
272 if (sis
& INT_UQ_SYNC
)
273 spdif_irq_uq_sync(spdif_priv
);
275 if (sis
& INT_UQ_ERR
)
276 spdif_irq_uq_err(spdif_priv
);
278 if (sis
& INT_RXFIFO_UNOV
)
279 dev_dbg(&pdev
->dev
, "isr: Rx FIFO under/overrun\n");
281 if (sis
& INT_RXFIFO_RESYNC
)
282 dev_dbg(&pdev
->dev
, "isr: Rx FIFO resync\n");
284 if (sis
& INT_LOSS_LOCK
)
285 spdif_irq_dpll_lock(spdif_priv
);
287 /* FIXME: Write Tx FIFO to clear TxEm */
289 dev_dbg(&pdev
->dev
, "isr: Tx FIFO empty\n");
291 /* FIXME: Read Rx FIFO to clear RxFIFOFul */
292 if (sis
& INT_RXFIFO_FUL
)
293 dev_dbg(&pdev
->dev
, "isr: Rx FIFO full\n");
298 static int spdif_softreset(struct fsl_spdif_priv
*spdif_priv
)
300 struct regmap
*regmap
= spdif_priv
->regmap
;
301 u32 val
, cycle
= 1000;
303 regmap_write(regmap
, REG_SPDIF_SCR
, SCR_SOFT_RESET
);
306 * RESET bit would be cleared after finishing its reset procedure,
307 * which typically lasts 8 cycles. 1000 cycles will keep it safe.
310 regmap_read(regmap
, REG_SPDIF_SCR
, &val
);
311 } while ((val
& SCR_SOFT_RESET
) && cycle
--);
319 static void spdif_set_cstatus(struct spdif_mixer_control
*ctrl
,
322 ctrl
->ch_status
[3] &= ~mask
;
323 ctrl
->ch_status
[3] |= cstatus
& mask
;
326 static void spdif_write_channel_status(struct fsl_spdif_priv
*spdif_priv
)
328 struct spdif_mixer_control
*ctrl
= &spdif_priv
->fsl_spdif_control
;
329 struct regmap
*regmap
= spdif_priv
->regmap
;
330 struct platform_device
*pdev
= spdif_priv
->pdev
;
333 ch_status
= (bitrev8(ctrl
->ch_status
[0]) << 16) |
334 (bitrev8(ctrl
->ch_status
[1]) << 8) |
335 bitrev8(ctrl
->ch_status
[2]);
336 regmap_write(regmap
, REG_SPDIF_STCSCH
, ch_status
);
338 dev_dbg(&pdev
->dev
, "STCSCH: 0x%06x\n", ch_status
);
340 ch_status
= bitrev8(ctrl
->ch_status
[3]) << 16;
341 regmap_write(regmap
, REG_SPDIF_STCSCL
, ch_status
);
343 dev_dbg(&pdev
->dev
, "STCSCL: 0x%06x\n", ch_status
);
346 /* Set SPDIF PhaseConfig register for rx clock */
347 static int spdif_set_rx_clksrc(struct fsl_spdif_priv
*spdif_priv
,
348 enum spdif_gainsel gainsel
, int dpll_locked
)
350 struct regmap
*regmap
= spdif_priv
->regmap
;
351 u8 clksrc
= spdif_priv
->rxclk_src
;
353 if (clksrc
>= SRPC_CLKSRC_MAX
|| gainsel
>= GAINSEL_MULTI_MAX
)
356 regmap_update_bits(regmap
, REG_SPDIF_SRPC
,
357 SRPC_CLKSRC_SEL_MASK
| SRPC_GAINSEL_MASK
,
358 SRPC_CLKSRC_SEL_SET(clksrc
) | SRPC_GAINSEL_SET(gainsel
));
363 static int spdif_set_sample_rate(struct snd_pcm_substream
*substream
,
366 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
367 struct fsl_spdif_priv
*spdif_priv
= snd_soc_dai_get_drvdata(rtd
->cpu_dai
);
368 struct spdif_mixer_control
*ctrl
= &spdif_priv
->fsl_spdif_control
;
369 struct regmap
*regmap
= spdif_priv
->regmap
;
370 struct platform_device
*pdev
= spdif_priv
->pdev
;
371 unsigned long csfs
= 0;
373 u8 clk
, txclk_df
, sysclk_df
;
376 switch (sample_rate
) {
378 rate
= SPDIF_TXRATE_32000
;
379 csfs
= IEC958_AES3_CON_FS_32000
;
382 rate
= SPDIF_TXRATE_44100
;
383 csfs
= IEC958_AES3_CON_FS_44100
;
386 rate
= SPDIF_TXRATE_48000
;
387 csfs
= IEC958_AES3_CON_FS_48000
;
390 rate
= SPDIF_TXRATE_96000
;
391 csfs
= IEC958_AES3_CON_FS_96000
;
394 rate
= SPDIF_TXRATE_192000
;
395 csfs
= IEC958_AES3_CON_FS_192000
;
398 dev_err(&pdev
->dev
, "unsupported sample rate %d\n", sample_rate
);
402 clk
= spdif_priv
->txclk_src
[rate
];
403 if (clk
>= STC_TXCLK_SRC_MAX
) {
404 dev_err(&pdev
->dev
, "tx clock source is out of range\n");
408 txclk_df
= spdif_priv
->txclk_df
[rate
];
410 dev_err(&pdev
->dev
, "the txclk_df can't be zero\n");
414 sysclk_df
= spdif_priv
->sysclk_df
[rate
];
416 /* Don't mess up the clocks from other modules */
417 if (clk
!= STC_TXCLK_SPDIF_ROOT
)
420 /* The S/PDIF block needs a clock of 64 * fs * txclk_df */
421 ret
= clk_set_rate(spdif_priv
->txclk
[rate
],
422 64 * sample_rate
* txclk_df
);
424 dev_err(&pdev
->dev
, "failed to set tx clock rate\n");
429 dev_dbg(&pdev
->dev
, "expected clock rate = %d\n",
430 (64 * sample_rate
* txclk_df
* sysclk_df
));
431 dev_dbg(&pdev
->dev
, "actual clock rate = %ld\n",
432 clk_get_rate(spdif_priv
->txclk
[rate
]));
434 /* set fs field in consumer channel status */
435 spdif_set_cstatus(ctrl
, IEC958_AES3_CON_FS
, csfs
);
437 /* select clock source and divisor */
438 stc
= STC_TXCLK_ALL_EN
| STC_TXCLK_SRC_SET(clk
) |
439 STC_TXCLK_DF(txclk_df
) | STC_SYSCLK_DF(sysclk_df
);
440 mask
= STC_TXCLK_ALL_EN_MASK
| STC_TXCLK_SRC_MASK
|
441 STC_TXCLK_DF_MASK
| STC_SYSCLK_DF_MASK
;
442 regmap_update_bits(regmap
, REG_SPDIF_STC
, mask
, stc
);
444 dev_dbg(&pdev
->dev
, "set sample rate to %dHz for %dHz playback\n",
445 spdif_priv
->txrate
[rate
], sample_rate
);
450 static int fsl_spdif_startup(struct snd_pcm_substream
*substream
,
451 struct snd_soc_dai
*cpu_dai
)
453 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
454 struct fsl_spdif_priv
*spdif_priv
= snd_soc_dai_get_drvdata(rtd
->cpu_dai
);
455 struct platform_device
*pdev
= spdif_priv
->pdev
;
456 struct regmap
*regmap
= spdif_priv
->regmap
;
461 /* Reset module and interrupts only for first initialization */
462 if (!cpu_dai
->active
) {
463 ret
= clk_prepare_enable(spdif_priv
->coreclk
);
465 dev_err(&pdev
->dev
, "failed to enable core clock\n");
469 ret
= spdif_softreset(spdif_priv
);
471 dev_err(&pdev
->dev
, "failed to soft reset\n");
475 /* Disable all the interrupts */
476 regmap_update_bits(regmap
, REG_SPDIF_SIE
, 0xffffff, 0);
479 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
480 scr
= SCR_TXFIFO_AUTOSYNC
| SCR_TXFIFO_CTRL_NORMAL
|
481 SCR_TXSEL_NORMAL
| SCR_USRC_SEL_CHIP
|
483 mask
= SCR_TXFIFO_AUTOSYNC_MASK
| SCR_TXFIFO_CTRL_MASK
|
484 SCR_TXSEL_MASK
| SCR_USRC_SEL_MASK
|
485 SCR_TXFIFO_FSEL_MASK
;
486 for (i
= 0; i
< SPDIF_TXRATE_MAX
; i
++) {
487 ret
= clk_prepare_enable(spdif_priv
->txclk
[i
]);
492 scr
= SCR_RXFIFO_FSEL_IF8
| SCR_RXFIFO_AUTOSYNC
;
493 mask
= SCR_RXFIFO_FSEL_MASK
| SCR_RXFIFO_AUTOSYNC_MASK
|
494 SCR_RXFIFO_CTL_MASK
| SCR_RXFIFO_OFF_MASK
;
495 ret
= clk_prepare_enable(spdif_priv
->rxclk
);
499 regmap_update_bits(regmap
, REG_SPDIF_SCR
, mask
, scr
);
501 /* Power up SPDIF module */
502 regmap_update_bits(regmap
, REG_SPDIF_SCR
, SCR_LOW_POWER
, 0);
507 for (i
--; i
>= 0; i
--)
508 clk_disable_unprepare(spdif_priv
->txclk
[i
]);
510 clk_disable_unprepare(spdif_priv
->coreclk
);
515 static void fsl_spdif_shutdown(struct snd_pcm_substream
*substream
,
516 struct snd_soc_dai
*cpu_dai
)
518 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
519 struct fsl_spdif_priv
*spdif_priv
= snd_soc_dai_get_drvdata(rtd
->cpu_dai
);
520 struct regmap
*regmap
= spdif_priv
->regmap
;
523 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
525 mask
= SCR_TXFIFO_AUTOSYNC_MASK
| SCR_TXFIFO_CTRL_MASK
|
526 SCR_TXSEL_MASK
| SCR_USRC_SEL_MASK
|
527 SCR_TXFIFO_FSEL_MASK
;
528 for (i
= 0; i
< SPDIF_TXRATE_MAX
; i
++)
529 clk_disable_unprepare(spdif_priv
->txclk
[i
]);
531 scr
= SCR_RXFIFO_OFF
| SCR_RXFIFO_CTL_ZERO
;
532 mask
= SCR_RXFIFO_FSEL_MASK
| SCR_RXFIFO_AUTOSYNC_MASK
|
533 SCR_RXFIFO_CTL_MASK
| SCR_RXFIFO_OFF_MASK
;
534 clk_disable_unprepare(spdif_priv
->rxclk
);
536 regmap_update_bits(regmap
, REG_SPDIF_SCR
, mask
, scr
);
538 /* Power down SPDIF module only if tx&rx are both inactive */
539 if (!cpu_dai
->active
) {
540 spdif_intr_status_clear(spdif_priv
);
541 regmap_update_bits(regmap
, REG_SPDIF_SCR
,
542 SCR_LOW_POWER
, SCR_LOW_POWER
);
543 clk_disable_unprepare(spdif_priv
->coreclk
);
547 static int fsl_spdif_hw_params(struct snd_pcm_substream
*substream
,
548 struct snd_pcm_hw_params
*params
,
549 struct snd_soc_dai
*dai
)
551 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
552 struct fsl_spdif_priv
*spdif_priv
= snd_soc_dai_get_drvdata(rtd
->cpu_dai
);
553 struct spdif_mixer_control
*ctrl
= &spdif_priv
->fsl_spdif_control
;
554 struct platform_device
*pdev
= spdif_priv
->pdev
;
555 u32 sample_rate
= params_rate(params
);
558 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
559 ret
= spdif_set_sample_rate(substream
, sample_rate
);
561 dev_err(&pdev
->dev
, "%s: set sample rate failed: %d\n",
562 __func__
, sample_rate
);
565 spdif_set_cstatus(ctrl
, IEC958_AES3_CON_CLOCK
,
566 IEC958_AES3_CON_CLOCK_1000PPM
);
567 spdif_write_channel_status(spdif_priv
);
569 /* Setup rx clock source */
570 ret
= spdif_set_rx_clksrc(spdif_priv
, SPDIF_DEFAULT_GAINSEL
, 1);
576 static int fsl_spdif_trigger(struct snd_pcm_substream
*substream
,
577 int cmd
, struct snd_soc_dai
*dai
)
579 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
580 struct fsl_spdif_priv
*spdif_priv
= snd_soc_dai_get_drvdata(rtd
->cpu_dai
);
581 struct regmap
*regmap
= spdif_priv
->regmap
;
582 bool tx
= substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
;
583 u32 intr
= SIE_INTR_FOR(tx
);
584 u32 dmaen
= SCR_DMA_xX_EN(tx
);
587 case SNDRV_PCM_TRIGGER_START
:
588 case SNDRV_PCM_TRIGGER_RESUME
:
589 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
590 regmap_update_bits(regmap
, REG_SPDIF_SIE
, intr
, intr
);
591 regmap_update_bits(regmap
, REG_SPDIF_SCR
, dmaen
, dmaen
);
593 case SNDRV_PCM_TRIGGER_STOP
:
594 case SNDRV_PCM_TRIGGER_SUSPEND
:
595 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
596 regmap_update_bits(regmap
, REG_SPDIF_SCR
, dmaen
, 0);
597 regmap_update_bits(regmap
, REG_SPDIF_SIE
, intr
, 0);
606 static struct snd_soc_dai_ops fsl_spdif_dai_ops
= {
607 .startup
= fsl_spdif_startup
,
608 .hw_params
= fsl_spdif_hw_params
,
609 .trigger
= fsl_spdif_trigger
,
610 .shutdown
= fsl_spdif_shutdown
,
615 * FSL SPDIF IEC958 controller(mixer) functions
617 * Channel status get/put control
618 * User bit value get/put control
619 * Valid bit value get control
620 * DPLL lock status get control
621 * User bit sync mode selection control
624 static int fsl_spdif_info(struct snd_kcontrol
*kcontrol
,
625 struct snd_ctl_elem_info
*uinfo
)
627 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_IEC958
;
633 static int fsl_spdif_pb_get(struct snd_kcontrol
*kcontrol
,
634 struct snd_ctl_elem_value
*uvalue
)
636 struct snd_soc_dai
*cpu_dai
= snd_kcontrol_chip(kcontrol
);
637 struct fsl_spdif_priv
*spdif_priv
= snd_soc_dai_get_drvdata(cpu_dai
);
638 struct spdif_mixer_control
*ctrl
= &spdif_priv
->fsl_spdif_control
;
640 uvalue
->value
.iec958
.status
[0] = ctrl
->ch_status
[0];
641 uvalue
->value
.iec958
.status
[1] = ctrl
->ch_status
[1];
642 uvalue
->value
.iec958
.status
[2] = ctrl
->ch_status
[2];
643 uvalue
->value
.iec958
.status
[3] = ctrl
->ch_status
[3];
648 static int fsl_spdif_pb_put(struct snd_kcontrol
*kcontrol
,
649 struct snd_ctl_elem_value
*uvalue
)
651 struct snd_soc_dai
*cpu_dai
= snd_kcontrol_chip(kcontrol
);
652 struct fsl_spdif_priv
*spdif_priv
= snd_soc_dai_get_drvdata(cpu_dai
);
653 struct spdif_mixer_control
*ctrl
= &spdif_priv
->fsl_spdif_control
;
655 ctrl
->ch_status
[0] = uvalue
->value
.iec958
.status
[0];
656 ctrl
->ch_status
[1] = uvalue
->value
.iec958
.status
[1];
657 ctrl
->ch_status
[2] = uvalue
->value
.iec958
.status
[2];
658 ctrl
->ch_status
[3] = uvalue
->value
.iec958
.status
[3];
660 spdif_write_channel_status(spdif_priv
);
665 /* Get channel status from SPDIF_RX_CCHAN register */
666 static int fsl_spdif_capture_get(struct snd_kcontrol
*kcontrol
,
667 struct snd_ctl_elem_value
*ucontrol
)
669 struct snd_soc_dai
*cpu_dai
= snd_kcontrol_chip(kcontrol
);
670 struct fsl_spdif_priv
*spdif_priv
= snd_soc_dai_get_drvdata(cpu_dai
);
671 struct regmap
*regmap
= spdif_priv
->regmap
;
674 regmap_read(regmap
, REG_SPDIF_SIS
, &val
);
675 if (!(val
& INT_CNEW
))
678 regmap_read(regmap
, REG_SPDIF_SRCSH
, &cstatus
);
679 ucontrol
->value
.iec958
.status
[0] = (cstatus
>> 16) & 0xFF;
680 ucontrol
->value
.iec958
.status
[1] = (cstatus
>> 8) & 0xFF;
681 ucontrol
->value
.iec958
.status
[2] = cstatus
& 0xFF;
683 regmap_read(regmap
, REG_SPDIF_SRCSL
, &cstatus
);
684 ucontrol
->value
.iec958
.status
[3] = (cstatus
>> 16) & 0xFF;
685 ucontrol
->value
.iec958
.status
[4] = (cstatus
>> 8) & 0xFF;
686 ucontrol
->value
.iec958
.status
[5] = cstatus
& 0xFF;
689 regmap_write(regmap
, REG_SPDIF_SIC
, INT_CNEW
);
695 * Get User bits (subcode) from chip value which readed out
696 * in UChannel register.
698 static int fsl_spdif_subcode_get(struct snd_kcontrol
*kcontrol
,
699 struct snd_ctl_elem_value
*ucontrol
)
701 struct snd_soc_dai
*cpu_dai
= snd_kcontrol_chip(kcontrol
);
702 struct fsl_spdif_priv
*spdif_priv
= snd_soc_dai_get_drvdata(cpu_dai
);
703 struct spdif_mixer_control
*ctrl
= &spdif_priv
->fsl_spdif_control
;
707 spin_lock_irqsave(&ctrl
->ctl_lock
, flags
);
708 if (ctrl
->ready_buf
) {
709 int idx
= (ctrl
->ready_buf
- 1) * SPDIF_UBITS_SIZE
;
710 memcpy(&ucontrol
->value
.iec958
.subcode
[0],
711 &ctrl
->subcode
[idx
], SPDIF_UBITS_SIZE
);
714 spin_unlock_irqrestore(&ctrl
->ctl_lock
, flags
);
719 /* Q-subcode information. The byte size is SPDIF_UBITS_SIZE/8 */
720 static int fsl_spdif_qinfo(struct snd_kcontrol
*kcontrol
,
721 struct snd_ctl_elem_info
*uinfo
)
723 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_BYTES
;
724 uinfo
->count
= SPDIF_QSUB_SIZE
;
729 /* Get Q subcode from chip value which readed out in QChannel register */
730 static int fsl_spdif_qget(struct snd_kcontrol
*kcontrol
,
731 struct snd_ctl_elem_value
*ucontrol
)
733 struct snd_soc_dai
*cpu_dai
= snd_kcontrol_chip(kcontrol
);
734 struct fsl_spdif_priv
*spdif_priv
= snd_soc_dai_get_drvdata(cpu_dai
);
735 struct spdif_mixer_control
*ctrl
= &spdif_priv
->fsl_spdif_control
;
739 spin_lock_irqsave(&ctrl
->ctl_lock
, flags
);
740 if (ctrl
->ready_buf
) {
741 int idx
= (ctrl
->ready_buf
- 1) * SPDIF_QSUB_SIZE
;
742 memcpy(&ucontrol
->value
.bytes
.data
[0],
743 &ctrl
->qsub
[idx
], SPDIF_QSUB_SIZE
);
746 spin_unlock_irqrestore(&ctrl
->ctl_lock
, flags
);
751 /* Valid bit information */
752 static int fsl_spdif_vbit_info(struct snd_kcontrol
*kcontrol
,
753 struct snd_ctl_elem_info
*uinfo
)
755 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_BOOLEAN
;
757 uinfo
->value
.integer
.min
= 0;
758 uinfo
->value
.integer
.max
= 1;
763 /* Get valid good bit from interrupt status register */
764 static int fsl_spdif_vbit_get(struct snd_kcontrol
*kcontrol
,
765 struct snd_ctl_elem_value
*ucontrol
)
767 struct snd_soc_dai
*cpu_dai
= snd_kcontrol_chip(kcontrol
);
768 struct fsl_spdif_priv
*spdif_priv
= snd_soc_dai_get_drvdata(cpu_dai
);
769 struct regmap
*regmap
= spdif_priv
->regmap
;
772 regmap_read(regmap
, REG_SPDIF_SIS
, &val
);
773 ucontrol
->value
.integer
.value
[0] = (val
& INT_VAL_NOGOOD
) != 0;
774 regmap_write(regmap
, REG_SPDIF_SIC
, INT_VAL_NOGOOD
);
779 /* DPLL lock information */
780 static int fsl_spdif_rxrate_info(struct snd_kcontrol
*kcontrol
,
781 struct snd_ctl_elem_info
*uinfo
)
783 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_INTEGER
;
785 uinfo
->value
.integer
.min
= 16000;
786 uinfo
->value
.integer
.max
= 96000;
791 static u32 gainsel_multi
[GAINSEL_MULTI_MAX
] = {
792 24, 16, 12, 8, 6, 4, 3,
795 /* Get RX data clock rate given the SPDIF bus_clk */
796 static int spdif_get_rxclk_rate(struct fsl_spdif_priv
*spdif_priv
,
797 enum spdif_gainsel gainsel
)
799 struct regmap
*regmap
= spdif_priv
->regmap
;
800 struct platform_device
*pdev
= spdif_priv
->pdev
;
801 u64 tmpval64
, busclk_freq
= 0;
802 u32 freqmeas
, phaseconf
;
805 regmap_read(regmap
, REG_SPDIF_SRFM
, &freqmeas
);
806 regmap_read(regmap
, REG_SPDIF_SRPC
, &phaseconf
);
808 clksrc
= (phaseconf
>> SRPC_CLKSRC_SEL_OFFSET
) & 0xf;
810 /* Get bus clock from system */
811 if (srpc_dpll_locked
[clksrc
] && (phaseconf
& SRPC_DPLL_LOCKED
))
812 busclk_freq
= clk_get_rate(spdif_priv
->sysclk
);
814 /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */
815 tmpval64
= (u64
) busclk_freq
* freqmeas
;
816 do_div(tmpval64
, gainsel_multi
[gainsel
] * 1024);
817 do_div(tmpval64
, 128 * 1024);
819 dev_dbg(&pdev
->dev
, "FreqMeas: %d\n", freqmeas
);
820 dev_dbg(&pdev
->dev
, "BusclkFreq: %lld\n", busclk_freq
);
821 dev_dbg(&pdev
->dev
, "RxRate: %lld\n", tmpval64
);
823 return (int)tmpval64
;
827 * Get DPLL lock or not info from stable interrupt status register.
828 * User application must use this control to get locked,
829 * then can do next PCM operation
831 static int fsl_spdif_rxrate_get(struct snd_kcontrol
*kcontrol
,
832 struct snd_ctl_elem_value
*ucontrol
)
834 struct snd_soc_dai
*cpu_dai
= snd_kcontrol_chip(kcontrol
);
835 struct fsl_spdif_priv
*spdif_priv
= snd_soc_dai_get_drvdata(cpu_dai
);
838 if (spdif_priv
->dpll_locked
)
839 rate
= spdif_get_rxclk_rate(spdif_priv
, SPDIF_DEFAULT_GAINSEL
);
841 ucontrol
->value
.integer
.value
[0] = rate
;
846 /* User bit sync mode info */
847 static int fsl_spdif_usync_info(struct snd_kcontrol
*kcontrol
,
848 struct snd_ctl_elem_info
*uinfo
)
850 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_BOOLEAN
;
852 uinfo
->value
.integer
.min
= 0;
853 uinfo
->value
.integer
.max
= 1;
859 * User bit sync mode:
860 * 1 CD User channel subcode
863 static int fsl_spdif_usync_get(struct snd_kcontrol
*kcontrol
,
864 struct snd_ctl_elem_value
*ucontrol
)
866 struct snd_soc_dai
*cpu_dai
= snd_kcontrol_chip(kcontrol
);
867 struct fsl_spdif_priv
*spdif_priv
= snd_soc_dai_get_drvdata(cpu_dai
);
868 struct regmap
*regmap
= spdif_priv
->regmap
;
871 regmap_read(regmap
, REG_SPDIF_SRCD
, &val
);
872 ucontrol
->value
.integer
.value
[0] = (val
& SRCD_CD_USER
) != 0;
878 * User bit sync mode:
879 * 1 CD User channel subcode
882 static int fsl_spdif_usync_put(struct snd_kcontrol
*kcontrol
,
883 struct snd_ctl_elem_value
*ucontrol
)
885 struct snd_soc_dai
*cpu_dai
= snd_kcontrol_chip(kcontrol
);
886 struct fsl_spdif_priv
*spdif_priv
= snd_soc_dai_get_drvdata(cpu_dai
);
887 struct regmap
*regmap
= spdif_priv
->regmap
;
888 u32 val
= ucontrol
->value
.integer
.value
[0] << SRCD_CD_USER_OFFSET
;
890 regmap_update_bits(regmap
, REG_SPDIF_SRCD
, SRCD_CD_USER
, val
);
895 /* FSL SPDIF IEC958 controller defines */
896 static struct snd_kcontrol_new fsl_spdif_ctrls
[] = {
897 /* Status cchanel controller */
899 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
900 .name
= SNDRV_CTL_NAME_IEC958("", PLAYBACK
, DEFAULT
),
901 .access
= SNDRV_CTL_ELEM_ACCESS_READ
|
902 SNDRV_CTL_ELEM_ACCESS_WRITE
|
903 SNDRV_CTL_ELEM_ACCESS_VOLATILE
,
904 .info
= fsl_spdif_info
,
905 .get
= fsl_spdif_pb_get
,
906 .put
= fsl_spdif_pb_put
,
909 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
910 .name
= SNDRV_CTL_NAME_IEC958("", CAPTURE
, DEFAULT
),
911 .access
= SNDRV_CTL_ELEM_ACCESS_READ
|
912 SNDRV_CTL_ELEM_ACCESS_VOLATILE
,
913 .info
= fsl_spdif_info
,
914 .get
= fsl_spdif_capture_get
,
916 /* User bits controller */
918 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
919 .name
= "IEC958 Subcode Capture Default",
920 .access
= SNDRV_CTL_ELEM_ACCESS_READ
|
921 SNDRV_CTL_ELEM_ACCESS_VOLATILE
,
922 .info
= fsl_spdif_info
,
923 .get
= fsl_spdif_subcode_get
,
926 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
927 .name
= "IEC958 Q-subcode Capture Default",
928 .access
= SNDRV_CTL_ELEM_ACCESS_READ
|
929 SNDRV_CTL_ELEM_ACCESS_VOLATILE
,
930 .info
= fsl_spdif_qinfo
,
931 .get
= fsl_spdif_qget
,
933 /* Valid bit error controller */
935 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
936 .name
= "IEC958 V-Bit Errors",
937 .access
= SNDRV_CTL_ELEM_ACCESS_READ
|
938 SNDRV_CTL_ELEM_ACCESS_VOLATILE
,
939 .info
= fsl_spdif_vbit_info
,
940 .get
= fsl_spdif_vbit_get
,
942 /* DPLL lock info get controller */
944 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
945 .name
= "RX Sample Rate",
946 .access
= SNDRV_CTL_ELEM_ACCESS_READ
|
947 SNDRV_CTL_ELEM_ACCESS_VOLATILE
,
948 .info
= fsl_spdif_rxrate_info
,
949 .get
= fsl_spdif_rxrate_get
,
951 /* User bit sync mode set/get controller */
953 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
954 .name
= "IEC958 USyncMode CDText",
955 .access
= SNDRV_CTL_ELEM_ACCESS_READ
|
956 SNDRV_CTL_ELEM_ACCESS_WRITE
|
957 SNDRV_CTL_ELEM_ACCESS_VOLATILE
,
958 .info
= fsl_spdif_usync_info
,
959 .get
= fsl_spdif_usync_get
,
960 .put
= fsl_spdif_usync_put
,
964 static int fsl_spdif_dai_probe(struct snd_soc_dai
*dai
)
966 struct fsl_spdif_priv
*spdif_private
= snd_soc_dai_get_drvdata(dai
);
968 snd_soc_dai_init_dma_data(dai
, &spdif_private
->dma_params_tx
,
969 &spdif_private
->dma_params_rx
);
971 snd_soc_add_dai_controls(dai
, fsl_spdif_ctrls
, ARRAY_SIZE(fsl_spdif_ctrls
));
976 static struct snd_soc_dai_driver fsl_spdif_dai
= {
977 .probe
= &fsl_spdif_dai_probe
,
979 .stream_name
= "CPU-Playback",
982 .rates
= FSL_SPDIF_RATES_PLAYBACK
,
983 .formats
= FSL_SPDIF_FORMATS_PLAYBACK
,
986 .stream_name
= "CPU-Capture",
989 .rates
= FSL_SPDIF_RATES_CAPTURE
,
990 .formats
= FSL_SPDIF_FORMATS_CAPTURE
,
992 .ops
= &fsl_spdif_dai_ops
,
995 static const struct snd_soc_component_driver fsl_spdif_component
= {
999 /* FSL SPDIF REGMAP */
1001 static bool fsl_spdif_readable_reg(struct device
*dev
, unsigned int reg
)
1005 case REG_SPDIF_SRCD
:
1006 case REG_SPDIF_SRPC
:
1011 case REG_SPDIF_SRCSH
:
1012 case REG_SPDIF_SRCSL
:
1015 case REG_SPDIF_STCSCH
:
1016 case REG_SPDIF_STCSCL
:
1017 case REG_SPDIF_SRFM
:
1025 static bool fsl_spdif_writeable_reg(struct device
*dev
, unsigned int reg
)
1029 case REG_SPDIF_SRCD
:
1030 case REG_SPDIF_SRPC
:
1035 case REG_SPDIF_STCSCH
:
1036 case REG_SPDIF_STCSCL
:
1044 static const struct regmap_config fsl_spdif_regmap_config
= {
1049 .max_register
= REG_SPDIF_STC
,
1050 .readable_reg
= fsl_spdif_readable_reg
,
1051 .writeable_reg
= fsl_spdif_writeable_reg
,
1054 static u32
fsl_spdif_txclk_caldiv(struct fsl_spdif_priv
*spdif_priv
,
1055 struct clk
*clk
, u64 savesub
,
1056 enum spdif_txrate index
, bool round
)
1058 const u32 rate
[] = { 32000, 44100, 48000, 96000, 192000 };
1059 bool is_sysclk
= clk_is_match(clk
, spdif_priv
->sysclk
);
1060 u64 rate_ideal
, rate_actual
, sub
;
1061 u32 sysclk_dfmin
, sysclk_dfmax
;
1062 u32 txclk_df
, sysclk_df
, arate
;
1064 /* The sysclk has an extra divisor [2, 512] */
1065 sysclk_dfmin
= is_sysclk
? 2 : 1;
1066 sysclk_dfmax
= is_sysclk
? 512 : 1;
1068 for (sysclk_df
= sysclk_dfmin
; sysclk_df
<= sysclk_dfmax
; sysclk_df
++) {
1069 for (txclk_df
= 1; txclk_df
<= 128; txclk_df
++) {
1070 rate_ideal
= rate
[index
] * txclk_df
* 64;
1072 rate_actual
= clk_round_rate(clk
, rate_ideal
);
1074 rate_actual
= clk_get_rate(clk
);
1076 arate
= rate_actual
/ 64;
1077 arate
/= txclk_df
* sysclk_df
;
1079 if (arate
== rate
[index
]) {
1082 spdif_priv
->txclk_df
[index
] = txclk_df
;
1083 spdif_priv
->sysclk_df
[index
] = sysclk_df
;
1084 spdif_priv
->txrate
[index
] = arate
;
1086 } else if (arate
/ rate
[index
] == 1) {
1087 /* A little bigger than expect */
1088 sub
= (u64
)(arate
- rate
[index
]) * 100000;
1089 do_div(sub
, rate
[index
]);
1093 spdif_priv
->txclk_df
[index
] = txclk_df
;
1094 spdif_priv
->sysclk_df
[index
] = sysclk_df
;
1095 spdif_priv
->txrate
[index
] = arate
;
1096 } else if (rate
[index
] / arate
== 1) {
1097 /* A little smaller than expect */
1098 sub
= (u64
)(rate
[index
] - arate
) * 100000;
1099 do_div(sub
, rate
[index
]);
1103 spdif_priv
->txclk_df
[index
] = txclk_df
;
1104 spdif_priv
->sysclk_df
[index
] = sysclk_df
;
1105 spdif_priv
->txrate
[index
] = arate
;
1114 static int fsl_spdif_probe_txclk(struct fsl_spdif_priv
*spdif_priv
,
1115 enum spdif_txrate index
)
1117 const u32 rate
[] = { 32000, 44100, 48000, 96000, 192000 };
1118 struct platform_device
*pdev
= spdif_priv
->pdev
;
1119 struct device
*dev
= &pdev
->dev
;
1120 u64 savesub
= 100000, ret
;
1125 for (i
= 0; i
< STC_TXCLK_SRC_MAX
; i
++) {
1126 sprintf(tmp
, "rxtx%d", i
);
1127 clk
= devm_clk_get(&pdev
->dev
, tmp
);
1129 dev_err(dev
, "no rxtx%d clock in devicetree\n", i
);
1130 return PTR_ERR(clk
);
1132 if (!clk_get_rate(clk
))
1135 ret
= fsl_spdif_txclk_caldiv(spdif_priv
, clk
, savesub
, index
,
1136 i
== STC_TXCLK_SPDIF_ROOT
);
1141 spdif_priv
->txclk
[index
] = clk
;
1142 spdif_priv
->txclk_src
[index
] = i
;
1144 /* To quick catch a divisor, we allow a 0.1% deviation */
1149 dev_dbg(&pdev
->dev
, "use rxtx%d as tx clock source for %dHz sample rate\n",
1150 spdif_priv
->txclk_src
[index
], rate
[index
]);
1151 dev_dbg(&pdev
->dev
, "use txclk df %d for %dHz sample rate\n",
1152 spdif_priv
->txclk_df
[index
], rate
[index
]);
1153 if (clk_is_match(spdif_priv
->txclk
[index
], spdif_priv
->sysclk
))
1154 dev_dbg(&pdev
->dev
, "use sysclk df %d for %dHz sample rate\n",
1155 spdif_priv
->sysclk_df
[index
], rate
[index
]);
1156 dev_dbg(&pdev
->dev
, "the best rate for %dHz sample rate is %dHz\n",
1157 rate
[index
], spdif_priv
->txrate
[index
]);
1162 static int fsl_spdif_probe(struct platform_device
*pdev
)
1164 struct device_node
*np
= pdev
->dev
.of_node
;
1165 struct fsl_spdif_priv
*spdif_priv
;
1166 struct spdif_mixer_control
*ctrl
;
1167 struct resource
*res
;
1174 spdif_priv
= devm_kzalloc(&pdev
->dev
, sizeof(*spdif_priv
), GFP_KERNEL
);
1178 spdif_priv
->pdev
= pdev
;
1180 /* Initialize this copy of the CPU DAI driver structure */
1181 memcpy(&spdif_priv
->cpu_dai_drv
, &fsl_spdif_dai
, sizeof(fsl_spdif_dai
));
1182 spdif_priv
->cpu_dai_drv
.name
= dev_name(&pdev
->dev
);
1184 /* Get the addresses and IRQ */
1185 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1186 regs
= devm_ioremap_resource(&pdev
->dev
, res
);
1188 return PTR_ERR(regs
);
1190 spdif_priv
->regmap
= devm_regmap_init_mmio_clk(&pdev
->dev
,
1191 "core", regs
, &fsl_spdif_regmap_config
);
1192 if (IS_ERR(spdif_priv
->regmap
)) {
1193 dev_err(&pdev
->dev
, "regmap init failed\n");
1194 return PTR_ERR(spdif_priv
->regmap
);
1197 irq
= platform_get_irq(pdev
, 0);
1199 dev_err(&pdev
->dev
, "no irq for node %s\n", pdev
->name
);
1203 ret
= devm_request_irq(&pdev
->dev
, irq
, spdif_isr
, 0,
1204 dev_name(&pdev
->dev
), spdif_priv
);
1206 dev_err(&pdev
->dev
, "could not claim irq %u\n", irq
);
1210 /* Get system clock for rx clock rate calculation */
1211 spdif_priv
->sysclk
= devm_clk_get(&pdev
->dev
, "rxtx5");
1212 if (IS_ERR(spdif_priv
->sysclk
)) {
1213 dev_err(&pdev
->dev
, "no sys clock (rxtx5) in devicetree\n");
1214 return PTR_ERR(spdif_priv
->sysclk
);
1217 /* Get core clock for data register access via DMA */
1218 spdif_priv
->coreclk
= devm_clk_get(&pdev
->dev
, "core");
1219 if (IS_ERR(spdif_priv
->coreclk
)) {
1220 dev_err(&pdev
->dev
, "no core clock in devicetree\n");
1221 return PTR_ERR(spdif_priv
->coreclk
);
1224 /* Select clock source for rx/tx clock */
1225 spdif_priv
->rxclk
= devm_clk_get(&pdev
->dev
, "rxtx1");
1226 if (IS_ERR(spdif_priv
->rxclk
)) {
1227 dev_err(&pdev
->dev
, "no rxtx1 clock in devicetree\n");
1228 return PTR_ERR(spdif_priv
->rxclk
);
1230 spdif_priv
->rxclk_src
= DEFAULT_RXCLK_SRC
;
1232 for (i
= 0; i
< SPDIF_TXRATE_MAX
; i
++) {
1233 ret
= fsl_spdif_probe_txclk(spdif_priv
, i
);
1238 /* Initial spinlock for control data */
1239 ctrl
= &spdif_priv
->fsl_spdif_control
;
1240 spin_lock_init(&ctrl
->ctl_lock
);
1242 /* Init tx channel status default value */
1243 ctrl
->ch_status
[0] = IEC958_AES0_CON_NOT_COPYRIGHT
|
1244 IEC958_AES0_CON_EMPHASIS_5015
;
1245 ctrl
->ch_status
[1] = IEC958_AES1_CON_DIGDIGCONV_ID
;
1246 ctrl
->ch_status
[2] = 0x00;
1247 ctrl
->ch_status
[3] = IEC958_AES3_CON_FS_44100
|
1248 IEC958_AES3_CON_CLOCK_1000PPM
;
1250 spdif_priv
->dpll_locked
= false;
1252 spdif_priv
->dma_params_tx
.maxburst
= FSL_SPDIF_TXFIFO_WML
;
1253 spdif_priv
->dma_params_rx
.maxburst
= FSL_SPDIF_RXFIFO_WML
;
1254 spdif_priv
->dma_params_tx
.addr
= res
->start
+ REG_SPDIF_STL
;
1255 spdif_priv
->dma_params_rx
.addr
= res
->start
+ REG_SPDIF_SRL
;
1257 /* Register with ASoC */
1258 dev_set_drvdata(&pdev
->dev
, spdif_priv
);
1260 ret
= devm_snd_soc_register_component(&pdev
->dev
, &fsl_spdif_component
,
1261 &spdif_priv
->cpu_dai_drv
, 1);
1263 dev_err(&pdev
->dev
, "failed to register DAI: %d\n", ret
);
1267 ret
= imx_pcm_dma_init(pdev
, IMX_SPDIF_DMABUF_SIZE
);
1269 dev_err(&pdev
->dev
, "imx_pcm_dma_init failed: %d\n", ret
);
1274 static const struct of_device_id fsl_spdif_dt_ids
[] = {
1275 { .compatible
= "fsl,imx35-spdif", },
1276 { .compatible
= "fsl,vf610-spdif", },
1279 MODULE_DEVICE_TABLE(of
, fsl_spdif_dt_ids
);
1281 static struct platform_driver fsl_spdif_driver
= {
1283 .name
= "fsl-spdif-dai",
1284 .of_match_table
= fsl_spdif_dt_ids
,
1286 .probe
= fsl_spdif_probe
,
1289 module_platform_driver(fsl_spdif_driver
);
1291 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1292 MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver");
1293 MODULE_LICENSE("GPL v2");
1294 MODULE_ALIAS("platform:fsl-spdif-dai");