projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
ASoC: fsl-spdif: Convert to use regmap framework's endianness method.
[deliverable/linux.git] / sound / soc / fsl / fsl_spdif.c
1 /*
2 * Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver
3 *
4 * Copyright (C) 2013 Freescale Semiconductor, Inc.
5 *
6 * Based on stmp3xxx_spdif_dai.c
7 * Vladimir Barinov <vbarinov@embeddedalley.com>
8 * Copyright 2008 SigmaTel, Inc
9 * Copyright 2008 Embedded Alley Solutions, Inc
10 *
11 * This file is licensed under the terms of the GNU General Public License
12 * version 2. This program is licensed "as is" without any warranty of any
13 * kind, whether express or implied.
14 */
15
16 #include <linux/bitrev.h>
17 #include <linux/clk.h>
18 #include <linux/clk-private.h>
19 #include <linux/module.h>
20 #include <linux/of_address.h>
21 #include <linux/of_device.h>
22 #include <linux/of_irq.h>
23 #include <linux/regmap.h>
24
25 #include <sound/asoundef.h>
26 #include <sound/dmaengine_pcm.h>
27 #include <sound/soc.h>
28
29 #include "fsl_spdif.h"
30 #include "imx-pcm.h"
31
32 #define FSL_SPDIF_TXFIFO_WML 0x8
33 #define FSL_SPDIF_RXFIFO_WML 0x8
34
35 #define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC)
36 #define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |\
37 INT_URX_OV | INT_QRX_FUL | INT_QRX_OV |\
38 INT_UQ_SYNC | INT_UQ_ERR | INT_RXFIFO_RESYNC |\
39 INT_LOSS_LOCK | INT_DPLL_LOCKED)
40
41 #define SIE_INTR_FOR(tx) (tx ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE)
42
43 /* Index list for the values that has if (DPLL Locked) condition */
44 static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb };
45 #define SRPC_NODPLL_START1 0x5
46 #define SRPC_NODPLL_START2 0xc
47
48 #define DEFAULT_RXCLK_SRC 1
49
50 /*
51 * SPDIF control structure
52 * Defines channel status, subcode and Q sub
53 */
54 struct spdif_mixer_control {
55 /* spinlock to access control data */
56 spinlock_t ctl_lock;
57
58 /* IEC958 channel tx status bit */
59 unsigned char ch_status[4];
60
61 /* User bits */
62 unsigned char subcode[2 * SPDIF_UBITS_SIZE];
63
64 /* Q subcode part of user bits */
65 unsigned char qsub[2 * SPDIF_QSUB_SIZE];
66
67 /* Buffer offset for U/Q */
68 u32 upos;
69 u32 qpos;
70
71 /* Ready buffer index of the two buffers */
72 u32 ready_buf;
73 };
74
75 /**
76 * fsl_spdif_priv: Freescale SPDIF private data
77 *
78 * @fsl_spdif_control: SPDIF control data
79 * @cpu_dai_drv: cpu dai driver
80 * @pdev: platform device pointer
81 * @regmap: regmap handler
82 * @dpll_locked: dpll lock flag
83 * @txrate: the best rates for playback
84 * @txclk_df: STC_TXCLK_DF dividers value for playback
85 * @sysclk_df: STC_SYSCLK_DF dividers value for playback
86 * @txclk_src: STC_TXCLK_SRC values for playback
87 * @rxclk_src: SRPC_CLKSRC_SEL values for capture
88 * @txclk: tx clock sources for playback
89 * @rxclk: rx clock sources for capture
90 * @coreclk: core clock for register access via DMA
91 * @sysclk: system clock for rx clock rate measurement
92 * @dma_params_tx: DMA parameters for transmit channel
93 * @dma_params_rx: DMA parameters for receive channel
94 * @name: driver name
95 */
96 struct fsl_spdif_priv {
97 struct spdif_mixer_control fsl_spdif_control;
98 struct snd_soc_dai_driver cpu_dai_drv;
99 struct platform_device *pdev;
100 struct regmap *regmap;
101 bool dpll_locked;
102 u32 txrate[SPDIF_TXRATE_MAX];
103 u8 txclk_df[SPDIF_TXRATE_MAX];
104 u8 sysclk_df[SPDIF_TXRATE_MAX];
105 u8 txclk_src[SPDIF_TXRATE_MAX];
106 u8 rxclk_src;
107 struct clk *txclk[SPDIF_TXRATE_MAX];
108 struct clk *rxclk;
109 struct clk *coreclk;
110 struct clk *sysclk;
111 struct snd_dmaengine_dai_dma_data dma_params_tx;
112 struct snd_dmaengine_dai_dma_data dma_params_rx;
113
114 /* The name space will be allocated dynamically */
115 char name[0];
116 };
117
118
119 /* DPLL locked and lock loss interrupt handler */
120 static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv)
121 {
122 struct regmap *regmap = spdif_priv->regmap;
123 struct platform_device *pdev = spdif_priv->pdev;
124 u32 locked;
125
126 regmap_read(regmap, REG_SPDIF_SRPC, &locked);
127 locked &= SRPC_DPLL_LOCKED;
128
129 dev_dbg(&pdev->dev, "isr: Rx dpll %s \n",
130 locked ? "locked" : "loss lock");
131
132 spdif_priv->dpll_locked = locked ? true : false;
133 }
134
135 /* Receiver found illegal symbol interrupt handler */
136 static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv)
137 {
138 struct regmap *regmap = spdif_priv->regmap;
139 struct platform_device *pdev = spdif_priv->pdev;
140
141 dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n");
142
143 /* Clear illegal symbol if DPLL unlocked since no audio stream */
144 if (!spdif_priv->dpll_locked)
145 regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0);
146 }
147
148 /* U/Q Channel receive register full */
149 static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name)
150 {
151 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
152 struct regmap *regmap = spdif_priv->regmap;
153 struct platform_device *pdev = spdif_priv->pdev;
154 u32 *pos, size, val, reg;
155
156 switch (name) {
157 case 'U':
158 pos = &ctrl->upos;
159 size = SPDIF_UBITS_SIZE;
160 reg = REG_SPDIF_SRU;
161 break;
162 case 'Q':
163 pos = &ctrl->qpos;
164 size = SPDIF_QSUB_SIZE;
165 reg = REG_SPDIF_SRQ;
166 break;
167 default:
168 dev_err(&pdev->dev, "unsupported channel name\n");
169 return;
170 }
171
172 dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name);
173
174 if (*pos >= size * 2) {
175 *pos = 0;
176 } else if (unlikely((*pos % size) + 3 > size)) {
177 dev_err(&pdev->dev, "User bit receivce buffer overflow\n");
178 return;
179 }
180
181 regmap_read(regmap, reg, &val);
182 ctrl->subcode[*pos++] = val >> 16;
183 ctrl->subcode[*pos++] = val >> 8;
184 ctrl->subcode[*pos++] = val;
185 }
186
187 /* U/Q Channel sync found */
188 static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv)
189 {
190 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
191 struct platform_device *pdev = spdif_priv->pdev;
192
193 dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n");
194
195 /* U/Q buffer reset */
196 if (ctrl->qpos == 0)
197 return;
198
199 /* Set ready to this buffer */
200 ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1;
201 }
202
203 /* U/Q Channel framing error */
204 static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv)
205 {
206 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
207 struct regmap *regmap = spdif_priv->regmap;
208 struct platform_device *pdev = spdif_priv->pdev;
209 u32 val;
210
211 dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n");
212
213 /* Read U/Q data to clear the irq and do buffer reset */
214 regmap_read(regmap, REG_SPDIF_SRU, &val);
215 regmap_read(regmap, REG_SPDIF_SRQ, &val);
216
217 /* Drop this U/Q buffer */
218 ctrl->ready_buf = 0;
219 ctrl->upos = 0;
220 ctrl->qpos = 0;
221 }
222
223 /* Get spdif interrupt status and clear the interrupt */
224 static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv)
225 {
226 struct regmap *regmap = spdif_priv->regmap;
227 u32 val, val2;
228
229 regmap_read(regmap, REG_SPDIF_SIS, &val);
230 regmap_read(regmap, REG_SPDIF_SIE, &val2);
231
232 regmap_write(regmap, REG_SPDIF_SIC, val & val2);
233
234 return val;
235 }
236
237 static irqreturn_t spdif_isr(int irq, void *devid)
238 {
239 struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid;
240 struct platform_device *pdev = spdif_priv->pdev;
241 u32 sis;
242
243 sis = spdif_intr_status_clear(spdif_priv);
244
245 if (sis & INT_DPLL_LOCKED)
246 spdif_irq_dpll_lock(spdif_priv);
247
248 if (sis & INT_TXFIFO_UNOV)
249 dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n");
250
251 if (sis & INT_TXFIFO_RESYNC)
252 dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n");
253
254 if (sis & INT_CNEW)
255 dev_dbg(&pdev->dev, "isr: cstatus new\n");
256
257 if (sis & INT_VAL_NOGOOD)
258 dev_dbg(&pdev->dev, "isr: validity flag no good\n");
259
260 if (sis & INT_SYM_ERR)
261 spdif_irq_sym_error(spdif_priv);
262
263 if (sis & INT_BIT_ERR)
264 dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n");
265
266 if (sis & INT_URX_FUL)
267 spdif_irq_uqrx_full(spdif_priv, 'U');
268
269 if (sis & INT_URX_OV)
270 dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n");
271
272 if (sis & INT_QRX_FUL)
273 spdif_irq_uqrx_full(spdif_priv, 'Q');
274
275 if (sis & INT_QRX_OV)
276 dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n");
277
278 if (sis & INT_UQ_SYNC)
279 spdif_irq_uq_sync(spdif_priv);
280
281 if (sis & INT_UQ_ERR)
282 spdif_irq_uq_err(spdif_priv);
283
284 if (sis & INT_RXFIFO_UNOV)
285 dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n");
286
287 if (sis & INT_RXFIFO_RESYNC)
288 dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n");
289
290 if (sis & INT_LOSS_LOCK)
291 spdif_irq_dpll_lock(spdif_priv);
292
293 /* FIXME: Write Tx FIFO to clear TxEm */
294 if (sis & INT_TX_EM)
295 dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n");
296
297 /* FIXME: Read Rx FIFO to clear RxFIFOFul */
298 if (sis & INT_RXFIFO_FUL)
299 dev_dbg(&pdev->dev, "isr: Rx FIFO full\n");
300
301 return IRQ_HANDLED;
302 }
303
304 static int spdif_softreset(struct fsl_spdif_priv *spdif_priv)
305 {
306 struct regmap *regmap = spdif_priv->regmap;
307 u32 val, cycle = 1000;
308
309 regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET);
310
311 /*
312 * RESET bit would be cleared after finishing its reset procedure,
313 * which typically lasts 8 cycles. 1000 cycles will keep it safe.
314 */
315 do {
316 regmap_read(regmap, REG_SPDIF_SCR, &val);
317 } while ((val & SCR_SOFT_RESET) && cycle--);
318
319 if (cycle)
320 return 0;
321 else
322 return -EBUSY;
323 }
324
325 static void spdif_set_cstatus(struct spdif_mixer_control *ctrl,
326 u8 mask, u8 cstatus)
327 {
328 ctrl->ch_status[3] &= ~mask;
329 ctrl->ch_status[3] |= cstatus & mask;
330 }
331
332 static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv)
333 {
334 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
335 struct regmap *regmap = spdif_priv->regmap;
336 struct platform_device *pdev = spdif_priv->pdev;
337 u32 ch_status;
338
339 ch_status = (bitrev8(ctrl->ch_status[0]) << 16) |
340 (bitrev8(ctrl->ch_status[1]) << 8) |
341 bitrev8(ctrl->ch_status[2]);
342 regmap_write(regmap, REG_SPDIF_STCSCH, ch_status);
343
344 dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status);
345
346 ch_status = bitrev8(ctrl->ch_status[3]) << 16;
347 regmap_write(regmap, REG_SPDIF_STCSCL, ch_status);
348
349 dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status);
350 }
351
352 /* Set SPDIF PhaseConfig register for rx clock */
353 static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv,
354 enum spdif_gainsel gainsel, int dpll_locked)
355 {
356 struct regmap *regmap = spdif_priv->regmap;
357 u8 clksrc = spdif_priv->rxclk_src;
358
359 if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX)
360 return -EINVAL;
361
362 regmap_update_bits(regmap, REG_SPDIF_SRPC,
363 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
364 SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel));
365
366 return 0;
367 }
368
369 static int spdif_set_sample_rate(struct snd_pcm_substream *substream,
370 int sample_rate)
371 {
372 struct snd_soc_pcm_runtime *rtd = substream->private_data;
373 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
374 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
375 struct regmap *regmap = spdif_priv->regmap;
376 struct platform_device *pdev = spdif_priv->pdev;
377 unsigned long csfs = 0;
378 u32 stc, mask, rate;
379 u8 clk, txclk_df, sysclk_df;
380 int ret;
381
382 switch (sample_rate) {
383 case 32000:
384 rate = SPDIF_TXRATE_32000;
385 csfs = IEC958_AES3_CON_FS_32000;
386 break;
387 case 44100:
388 rate = SPDIF_TXRATE_44100;
389 csfs = IEC958_AES3_CON_FS_44100;
390 break;
391 case 48000:
392 rate = SPDIF_TXRATE_48000;
393 csfs = IEC958_AES3_CON_FS_48000;
394 break;
395 case 96000:
396 rate = SPDIF_TXRATE_96000;
397 csfs = IEC958_AES3_CON_FS_96000;
398 break;
399 case 192000:
400 rate = SPDIF_TXRATE_192000;
401 csfs = IEC958_AES3_CON_FS_192000;
402 break;
403 default:
404 dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate);
405 return -EINVAL;
406 }
407
408 clk = spdif_priv->txclk_src[rate];
409 if (clk >= STC_TXCLK_SRC_MAX) {
410 dev_err(&pdev->dev, "tx clock source is out of range\n");
411 return -EINVAL;
412 }
413
414 txclk_df = spdif_priv->txclk_df[rate];
415 if (txclk_df == 0) {
416 dev_err(&pdev->dev, "the txclk_df can't be zero\n");
417 return -EINVAL;
418 }
419
420 sysclk_df = spdif_priv->sysclk_df[rate];
421
422 /* Don't mess up the clocks from other modules */
423 if (clk != STC_TXCLK_SPDIF_ROOT)
424 goto clk_set_bypass;
425
426 /*
427 * The S/PDIF block needs a clock of 64 * fs * txclk_df.
428 * So request 64 * fs * (txclk_df + 1) to get rounded.
429 */
430 ret = clk_set_rate(spdif_priv->txclk[rate], 64 * sample_rate * (txclk_df + 1));
431 if (ret) {
432 dev_err(&pdev->dev, "failed to set tx clock rate\n");
433 return ret;
434 }
435
436 clk_set_bypass:
437 dev_dbg(&pdev->dev, "expected clock rate = %d\n",
438 (64 * sample_rate * txclk_df * sysclk_df));
439 dev_dbg(&pdev->dev, "actual clock rate = %ld\n",
440 clk_get_rate(spdif_priv->txclk[rate]));
441
442 /* set fs field in consumer channel status */
443 spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs);
444
445 /* select clock source and divisor */
446 stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) |
447 STC_TXCLK_DF(txclk_df) | STC_SYSCLK_DF(sysclk_df);
448 mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK |
449 STC_TXCLK_DF_MASK | STC_SYSCLK_DF_MASK;
450 regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc);
451
452 dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n",
453 spdif_priv->txrate[rate], sample_rate);
454
455 return 0;
456 }
457
458 static int fsl_spdif_startup(struct snd_pcm_substream *substream,
459 struct snd_soc_dai *cpu_dai)
460 {
461 struct snd_soc_pcm_runtime *rtd = substream->private_data;
462 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
463 struct platform_device *pdev = spdif_priv->pdev;
464 struct regmap *regmap = spdif_priv->regmap;
465 u32 scr, mask, i;
466 int ret;
467
468 /* Reset module and interrupts only for first initialization */
469 if (!cpu_dai->active) {
470 ret = clk_prepare_enable(spdif_priv->coreclk);
471 if (ret) {
472 dev_err(&pdev->dev, "failed to enable core clock\n");
473 return ret;
474 }
475
476 ret = spdif_softreset(spdif_priv);
477 if (ret) {
478 dev_err(&pdev->dev, "failed to soft reset\n");
479 goto err;
480 }
481
482 /* Disable all the interrupts */
483 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0);
484 }
485
486 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
487 scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL |
488 SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP |
489 SCR_TXFIFO_FSEL_IF8;
490 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
491 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
492 SCR_TXFIFO_FSEL_MASK;
493 for (i = 0; i < SPDIF_TXRATE_MAX; i++)
494 clk_prepare_enable(spdif_priv->txclk[i]);
495 } else {
496 scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC;
497 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
498 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
499 clk_prepare_enable(spdif_priv->rxclk);
500 }
501 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
502
503 /* Power up SPDIF module */
504 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0);
505
506 return 0;
507
508 err:
509 clk_disable_unprepare(spdif_priv->coreclk);
510
511 return ret;
512 }
513
514 static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,
515 struct snd_soc_dai *cpu_dai)
516 {
517 struct snd_soc_pcm_runtime *rtd = substream->private_data;
518 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
519 struct regmap *regmap = spdif_priv->regmap;
520 u32 scr, mask, i;
521
522 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
523 scr = 0;
524 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
525 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
526 SCR_TXFIFO_FSEL_MASK;
527 for (i = 0; i < SPDIF_TXRATE_MAX; i++)
528 clk_disable_unprepare(spdif_priv->txclk[i]);
529 } else {
530 scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO;
531 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
532 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
533 clk_disable_unprepare(spdif_priv->rxclk);
534 }
535 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
536
537 /* Power down SPDIF module only if tx&rx are both inactive */
538 if (!cpu_dai->active) {
539 spdif_intr_status_clear(spdif_priv);
540 regmap_update_bits(regmap, REG_SPDIF_SCR,
541 SCR_LOW_POWER, SCR_LOW_POWER);
542 clk_disable_unprepare(spdif_priv->coreclk);
543 }
544 }
545
546 static int fsl_spdif_hw_params(struct snd_pcm_substream *substream,
547 struct snd_pcm_hw_params *params,
548 struct snd_soc_dai *dai)
549 {
550 struct snd_soc_pcm_runtime *rtd = substream->private_data;
551 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
552 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
553 struct platform_device *pdev = spdif_priv->pdev;
554 u32 sample_rate = params_rate(params);
555 int ret = 0;
556
557 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
558 ret = spdif_set_sample_rate(substream, sample_rate);
559 if (ret) {
560 dev_err(&pdev->dev, "%s: set sample rate failed: %d\n",
561 __func__, sample_rate);
562 return ret;
563 }
564 spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK,
565 IEC958_AES3_CON_CLOCK_1000PPM);
566 spdif_write_channel_status(spdif_priv);
567 } else {
568 /* Setup rx clock source */
569 ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1);
570 }
571
572 return ret;
573 }
574
575 static int fsl_spdif_trigger(struct snd_pcm_substream *substream,
576 int cmd, struct snd_soc_dai *dai)
577 {
578 struct snd_soc_pcm_runtime *rtd = substream->private_data;
579 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
580 struct regmap *regmap = spdif_priv->regmap;
581 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
582 u32 intr = SIE_INTR_FOR(tx);
583 u32 dmaen = SCR_DMA_xX_EN(tx);
584
585 switch (cmd) {
586 case SNDRV_PCM_TRIGGER_START:
587 case SNDRV_PCM_TRIGGER_RESUME:
588 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
589 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr);
590 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen);
591 break;
592 case SNDRV_PCM_TRIGGER_STOP:
593 case SNDRV_PCM_TRIGGER_SUSPEND:
594 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
595 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0);
596 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0);
597 break;
598 default:
599 return -EINVAL;
600 }
601
602 return 0;
603 }
604
605 static struct snd_soc_dai_ops fsl_spdif_dai_ops = {
606 .startup = fsl_spdif_startup,
607 .hw_params = fsl_spdif_hw_params,
608 .trigger = fsl_spdif_trigger,
609 .shutdown = fsl_spdif_shutdown,
610 };
611
612
613 /*
614 * FSL SPDIF IEC958 controller(mixer) functions
615 *
616 * Channel status get/put control
617 * User bit value get/put control
618 * Valid bit value get control
619 * DPLL lock status get control
620 * User bit sync mode selection control
621 */
622
623 static int fsl_spdif_info(struct snd_kcontrol *kcontrol,
624 struct snd_ctl_elem_info *uinfo)
625 {
626 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
627 uinfo->count = 1;
628
629 return 0;
630 }
631
632 static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol,
633 struct snd_ctl_elem_value *uvalue)
634 {
635 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
636 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
637 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
638
639 uvalue->value.iec958.status[0] = ctrl->ch_status[0];
640 uvalue->value.iec958.status[1] = ctrl->ch_status[1];
641 uvalue->value.iec958.status[2] = ctrl->ch_status[2];
642 uvalue->value.iec958.status[3] = ctrl->ch_status[3];
643
644 return 0;
645 }
646
647 static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol,
648 struct snd_ctl_elem_value *uvalue)
649 {
650 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
651 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
652 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
653
654 ctrl->ch_status[0] = uvalue->value.iec958.status[0];
655 ctrl->ch_status[1] = uvalue->value.iec958.status[1];
656 ctrl->ch_status[2] = uvalue->value.iec958.status[2];
657 ctrl->ch_status[3] = uvalue->value.iec958.status[3];
658
659 spdif_write_channel_status(spdif_priv);
660
661 return 0;
662 }
663
664 /* Get channel status from SPDIF_RX_CCHAN register */
665 static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol,
666 struct snd_ctl_elem_value *ucontrol)
667 {
668 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
669 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
670 struct regmap *regmap = spdif_priv->regmap;
671 u32 cstatus, val;
672
673 regmap_read(regmap, REG_SPDIF_SIS, &val);
674 if (!(val & INT_CNEW))
675 return -EAGAIN;
676
677 regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus);
678 ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF;
679 ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF;
680 ucontrol->value.iec958.status[2] = cstatus & 0xFF;
681
682 regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus);
683 ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF;
684 ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF;
685 ucontrol->value.iec958.status[5] = cstatus & 0xFF;
686
687 /* Clear intr */
688 regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW);
689
690 return 0;
691 }
692
693 /*
694 * Get User bits (subcode) from chip value which readed out
695 * in UChannel register.
696 */
697 static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol,
698 struct snd_ctl_elem_value *ucontrol)
699 {
700 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
701 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
702 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
703 unsigned long flags;
704 int ret = -EAGAIN;
705
706 spin_lock_irqsave(&ctrl->ctl_lock, flags);
707 if (ctrl->ready_buf) {
708 int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE;
709 memcpy(&ucontrol->value.iec958.subcode[0],
710 &ctrl->subcode[idx], SPDIF_UBITS_SIZE);
711 ret = 0;
712 }
713 spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
714
715 return ret;
716 }
717
718 /* Q-subcode infomation. The byte size is SPDIF_UBITS_SIZE/8 */
719 static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol,
720 struct snd_ctl_elem_info *uinfo)
721 {
722 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
723 uinfo->count = SPDIF_QSUB_SIZE;
724
725 return 0;
726 }
727
728 /* Get Q subcode from chip value which readed out in QChannel register */
729 static int fsl_spdif_qget(struct snd_kcontrol *kcontrol,
730 struct snd_ctl_elem_value *ucontrol)
731 {
732 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
733 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
734 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
735 unsigned long flags;
736 int ret = -EAGAIN;
737
738 spin_lock_irqsave(&ctrl->ctl_lock, flags);
739 if (ctrl->ready_buf) {
740 int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE;
741 memcpy(&ucontrol->value.bytes.data[0],
742 &ctrl->qsub[idx], SPDIF_QSUB_SIZE);
743 ret = 0;
744 }
745 spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
746
747 return ret;
748 }
749
750 /* Valid bit infomation */
751 static int fsl_spdif_vbit_info(struct snd_kcontrol *kcontrol,
752 struct snd_ctl_elem_info *uinfo)
753 {
754 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
755 uinfo->count = 1;
756 uinfo->value.integer.min = 0;
757 uinfo->value.integer.max = 1;
758
759 return 0;
760 }
761
762 /* Get valid good bit from interrupt status register */
763 static int fsl_spdif_vbit_get(struct snd_kcontrol *kcontrol,
764 struct snd_ctl_elem_value *ucontrol)
765 {
766 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
767 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
768 struct regmap *regmap = spdif_priv->regmap;
769 u32 val;
770
771 regmap_read(regmap, REG_SPDIF_SIS, &val);
772 ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0;
773 regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD);
774
775 return 0;
776 }
777
778 /* DPLL lock infomation */
779 static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol,
780 struct snd_ctl_elem_info *uinfo)
781 {
782 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
783 uinfo->count = 1;
784 uinfo->value.integer.min = 16000;
785 uinfo->value.integer.max = 96000;
786
787 return 0;
788 }
789
790 static u32 gainsel_multi[GAINSEL_MULTI_MAX] = {
791 24, 16, 12, 8, 6, 4, 3,
792 };
793
794 /* Get RX data clock rate given the SPDIF bus_clk */
795 static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv,
796 enum spdif_gainsel gainsel)
797 {
798 struct regmap *regmap = spdif_priv->regmap;
799 struct platform_device *pdev = spdif_priv->pdev;
800 u64 tmpval64, busclk_freq = 0;
801 u32 freqmeas, phaseconf;
802 u8 clksrc;
803
804 regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas);
805 regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf);
806
807 clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf;
808
809 /* Get bus clock from system */
810 if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED))
811 busclk_freq = clk_get_rate(spdif_priv->sysclk);
812
813 /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */
814 tmpval64 = (u64) busclk_freq * freqmeas;
815 do_div(tmpval64, gainsel_multi[gainsel] * 1024);
816 do_div(tmpval64, 128 * 1024);
817
818 dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas);
819 dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq);
820 dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64);
821
822 return (int)tmpval64;
823 }
824
825 /*
826 * Get DPLL lock or not info from stable interrupt status register.
827 * User application must use this control to get locked,
828 * then can do next PCM operation
829 */
830 static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol,
831 struct snd_ctl_elem_value *ucontrol)
832 {
833 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
834 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
835 int rate = 0;
836
837 if (spdif_priv->dpll_locked)
838 rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL);
839
840 ucontrol->value.integer.value[0] = rate;
841
842 return 0;
843 }
844
845 /* User bit sync mode info */
846 static int fsl_spdif_usync_info(struct snd_kcontrol *kcontrol,
847 struct snd_ctl_elem_info *uinfo)
848 {
849 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
850 uinfo->count = 1;
851 uinfo->value.integer.min = 0;
852 uinfo->value.integer.max = 1;
853
854 return 0;
855 }
856
857 /*
858 * User bit sync mode:
859 * 1 CD User channel subcode
860 * 0 Non-CD data
861 */
862 static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol,
863 struct snd_ctl_elem_value *ucontrol)
864 {
865 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
866 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
867 struct regmap *regmap = spdif_priv->regmap;
868 u32 val;
869
870 regmap_read(regmap, REG_SPDIF_SRCD, &val);
871 ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0;
872
873 return 0;
874 }
875
876 /*
877 * User bit sync mode:
878 * 1 CD User channel subcode
879 * 0 Non-CD data
880 */
881 static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol,
882 struct snd_ctl_elem_value *ucontrol)
883 {
884 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
885 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
886 struct regmap *regmap = spdif_priv->regmap;
887 u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET;
888
889 regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val);
890
891 return 0;
892 }
893
894 /* FSL SPDIF IEC958 controller defines */
895 static struct snd_kcontrol_new fsl_spdif_ctrls[] = {
896 /* Status cchanel controller */
897 {
898 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
899 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
900 .access = SNDRV_CTL_ELEM_ACCESS_READ |
901 SNDRV_CTL_ELEM_ACCESS_WRITE |
902 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
903 .info = fsl_spdif_info,
904 .get = fsl_spdif_pb_get,
905 .put = fsl_spdif_pb_put,
906 },
907 {
908 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
909 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
910 .access = SNDRV_CTL_ELEM_ACCESS_READ |
911 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
912 .info = fsl_spdif_info,
913 .get = fsl_spdif_capture_get,
914 },
915 /* User bits controller */
916 {
917 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
918 .name = "IEC958 Subcode Capture Default",
919 .access = SNDRV_CTL_ELEM_ACCESS_READ |
920 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
921 .info = fsl_spdif_info,
922 .get = fsl_spdif_subcode_get,
923 },
924 {
925 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
926 .name = "IEC958 Q-subcode Capture Default",
927 .access = SNDRV_CTL_ELEM_ACCESS_READ |
928 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
929 .info = fsl_spdif_qinfo,
930 .get = fsl_spdif_qget,
931 },
932 /* Valid bit error controller */
933 {
934 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
935 .name = "IEC958 V-Bit Errors",
936 .access = SNDRV_CTL_ELEM_ACCESS_READ |
937 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
938 .info = fsl_spdif_vbit_info,
939 .get = fsl_spdif_vbit_get,
940 },
941 /* DPLL lock info get controller */
942 {
943 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
944 .name = "RX Sample Rate",
945 .access = SNDRV_CTL_ELEM_ACCESS_READ |
946 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
947 .info = fsl_spdif_rxrate_info,
948 .get = fsl_spdif_rxrate_get,
949 },
950 /* User bit sync mode set/get controller */
951 {
952 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
953 .name = "IEC958 USyncMode CDText",
954 .access = SNDRV_CTL_ELEM_ACCESS_READ |
955 SNDRV_CTL_ELEM_ACCESS_WRITE |
956 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
957 .info = fsl_spdif_usync_info,
958 .get = fsl_spdif_usync_get,
959 .put = fsl_spdif_usync_put,
960 },
961 };
962
963 static int fsl_spdif_dai_probe(struct snd_soc_dai *dai)
964 {
965 struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai);
966
967 snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx,
968 &spdif_private->dma_params_rx);
969
970 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls));
971
972 return 0;
973 }
974
975 static struct snd_soc_dai_driver fsl_spdif_dai = {
976 .probe = &fsl_spdif_dai_probe,
977 .playback = {
978 .stream_name = "CPU-Playback",
979 .channels_min = 2,
980 .channels_max = 2,
981 .rates = FSL_SPDIF_RATES_PLAYBACK,
982 .formats = FSL_SPDIF_FORMATS_PLAYBACK,
983 },
984 .capture = {
985 .stream_name = "CPU-Capture",
986 .channels_min = 2,
987 .channels_max = 2,
988 .rates = FSL_SPDIF_RATES_CAPTURE,
989 .formats = FSL_SPDIF_FORMATS_CAPTURE,
990 },
991 .ops = &fsl_spdif_dai_ops,
992 };
993
994 static const struct snd_soc_component_driver fsl_spdif_component = {
995 .name = "fsl-spdif",
996 };
997
998 /* FSL SPDIF REGMAP */
999
1000 static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg)
1001 {
1002 switch (reg) {
1003 case REG_SPDIF_SCR:
1004 case REG_SPDIF_SRCD:
1005 case REG_SPDIF_SRPC:
1006 case REG_SPDIF_SIE:
1007 case REG_SPDIF_SIS:
1008 case REG_SPDIF_SRL:
1009 case REG_SPDIF_SRR:
1010 case REG_SPDIF_SRCSH:
1011 case REG_SPDIF_SRCSL:
1012 case REG_SPDIF_SRU:
1013 case REG_SPDIF_SRQ:
1014 case REG_SPDIF_STCSCH:
1015 case REG_SPDIF_STCSCL:
1016 case REG_SPDIF_SRFM:
1017 case REG_SPDIF_STC:
1018 return true;
1019 default:
1020 return false;
1021 }
1022 }
1023
1024 static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg)
1025 {
1026 switch (reg) {
1027 case REG_SPDIF_SCR:
1028 case REG_SPDIF_SRCD:
1029 case REG_SPDIF_SRPC:
1030 case REG_SPDIF_SIE:
1031 case REG_SPDIF_SIC:
1032 case REG_SPDIF_STL:
1033 case REG_SPDIF_STR:
1034 case REG_SPDIF_STCSCH:
1035 case REG_SPDIF_STCSCL:
1036 case REG_SPDIF_STC:
1037 return true;
1038 default:
1039 return false;
1040 }
1041 }
1042
1043 static const struct regmap_config fsl_spdif_regmap_config = {
1044 .reg_bits = 32,
1045 .reg_stride = 4,
1046 .val_bits = 32,
1047
1048 .max_register = REG_SPDIF_STC,
1049 .readable_reg = fsl_spdif_readable_reg,
1050 .writeable_reg = fsl_spdif_writeable_reg,
1051 };
1052
1053 static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv,
1054 struct clk *clk, u64 savesub,
1055 enum spdif_txrate index, bool round)
1056 {
1057 const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 };
1058 bool is_sysclk = clk == spdif_priv->sysclk;
1059 u64 rate_ideal, rate_actual, sub;
1060 u32 sysclk_dfmin, sysclk_dfmax;
1061 u32 txclk_df, sysclk_df, arate;
1062
1063 /* The sysclk has an extra divisor [2, 512] */
1064 sysclk_dfmin = is_sysclk ? 2 : 1;
1065 sysclk_dfmax = is_sysclk ? 512 : 1;
1066
1067 for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) {
1068 for (txclk_df = 1; txclk_df <= 128; txclk_df++) {
1069 rate_ideal = rate[index] * (txclk_df + 1) * 64;
1070 if (round)
1071 rate_actual = clk_round_rate(clk, rate_ideal);
1072 else
1073 rate_actual = clk_get_rate(clk);
1074
1075 arate = rate_actual / 64;
1076 arate /= txclk_df * sysclk_df;
1077
1078 if (arate == rate[index]) {
1079 /* We are lucky */
1080 savesub = 0;
1081 spdif_priv->txclk_df[index] = txclk_df;
1082 spdif_priv->sysclk_df[index] = sysclk_df;
1083 spdif_priv->txrate[index] = arate;
1084 goto out;
1085 } else if (arate / rate[index] == 1) {
1086 /* A little bigger than expect */
1087 sub = (u64)(arate - rate[index]) * 100000;
1088 do_div(sub, rate[index]);
1089 if (sub >= savesub)
1090 continue;
1091 savesub = sub;
1092 spdif_priv->txclk_df[index] = txclk_df;
1093 spdif_priv->sysclk_df[index] = sysclk_df;
1094 spdif_priv->txrate[index] = arate;
1095 } else if (rate[index] / arate == 1) {
1096 /* A little smaller than expect */
1097 sub = (u64)(rate[index] - arate) * 100000;
1098 do_div(sub, rate[index]);
1099 if (sub >= savesub)
1100 continue;
1101 savesub = sub;
1102 spdif_priv->txclk_df[index] = txclk_df;
1103 spdif_priv->sysclk_df[index] = sysclk_df;
1104 spdif_priv->txrate[index] = arate;
1105 }
1106 }
1107 }
1108
1109 out:
1110 return savesub;
1111 }
1112
1113 static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv,
1114 enum spdif_txrate index)
1115 {
1116 const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 };
1117 struct platform_device *pdev = spdif_priv->pdev;
1118 struct device *dev = &pdev->dev;
1119 u64 savesub = 100000, ret;
1120 struct clk *clk;
1121 char tmp[16];
1122 int i;
1123
1124 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
1125 sprintf(tmp, "rxtx%d", i);
1126 clk = devm_clk_get(&pdev->dev, tmp);
1127 if (IS_ERR(clk)) {
1128 dev_err(dev, "no rxtx%d clock in devicetree\n", i);
1129 return PTR_ERR(clk);
1130 }
1131 if (!clk_get_rate(clk))
1132 continue;
1133
1134 ret = fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index,
1135 i == STC_TXCLK_SPDIF_ROOT);
1136 if (savesub == ret)
1137 continue;
1138
1139 savesub = ret;
1140 spdif_priv->txclk[index] = clk;
1141 spdif_priv->txclk_src[index] = i;
1142
1143 /* To quick catch a divisor, we allow a 0.1% deviation */
1144 if (savesub < 100)
1145 break;
1146 }
1147
1148 dev_dbg(&pdev->dev, "use rxtx%d as tx clock source for %dHz sample rate\n",
1149 spdif_priv->txclk_src[index], rate[index]);
1150 dev_dbg(&pdev->dev, "use txclk df %d for %dHz sample rate\n",
1151 spdif_priv->txclk_df[index], rate[index]);
1152 if (spdif_priv->txclk[index] == spdif_priv->sysclk)
1153 dev_dbg(&pdev->dev, "use sysclk df %d for %dHz sample rate\n",
1154 spdif_priv->sysclk_df[index], rate[index]);
1155 dev_dbg(&pdev->dev, "the best rate for %dHz sample rate is %dHz\n",
1156 rate[index], spdif_priv->txrate[index]);
1157
1158 return 0;
1159 }
1160
1161 static int fsl_spdif_probe(struct platform_device *pdev)
1162 {
1163 struct device_node *np = pdev->dev.of_node;
1164 struct fsl_spdif_priv *spdif_priv;
1165 struct spdif_mixer_control *ctrl;
1166 struct resource *res;
1167 void __iomem *regs;
1168 int irq, ret, i;
1169
1170 if (!np)
1171 return -ENODEV;
1172
1173 spdif_priv = devm_kzalloc(&pdev->dev,
1174 sizeof(struct fsl_spdif_priv) + strlen(np->name) + 1,
1175 GFP_KERNEL);
1176 if (!spdif_priv)
1177 return -ENOMEM;
1178
1179 strcpy(spdif_priv->name, np->name);
1180
1181 spdif_priv->pdev = pdev;
1182
1183 /* Initialize this copy of the CPU DAI driver structure */
1184 memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai));
1185 spdif_priv->cpu_dai_drv.name = spdif_priv->name;
1186
1187 /* Get the addresses and IRQ */
1188 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1189 regs = devm_ioremap_resource(&pdev->dev, res);
1190 if (IS_ERR(regs))
1191 return PTR_ERR(regs);
1192
1193 spdif_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
1194 "core", regs, &fsl_spdif_regmap_config);
1195 if (IS_ERR(spdif_priv->regmap)) {
1196 dev_err(&pdev->dev, "regmap init failed\n");
1197 return PTR_ERR(spdif_priv->regmap);
1198 }
1199
1200 irq = platform_get_irq(pdev, 0);
1201 if (irq < 0) {
1202 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
1203 return irq;
1204 }
1205
1206 ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0,
1207 spdif_priv->name, spdif_priv);
1208 if (ret) {
1209 dev_err(&pdev->dev, "could not claim irq %u\n", irq);
1210 return ret;
1211 }
1212
1213 /* Get system clock for rx clock rate calculation */
1214 spdif_priv->sysclk = devm_clk_get(&pdev->dev, "rxtx5");
1215 if (IS_ERR(spdif_priv->sysclk)) {
1216 dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n");
1217 return PTR_ERR(spdif_priv->sysclk);
1218 }
1219
1220 /* Get core clock for data register access via DMA */
1221 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core");
1222 if (IS_ERR(spdif_priv->coreclk)) {
1223 dev_err(&pdev->dev, "no core clock in devicetree\n");
1224 return PTR_ERR(spdif_priv->coreclk);
1225 }
1226
1227 /* Select clock source for rx/tx clock */
1228 spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1");
1229 if (IS_ERR(spdif_priv->rxclk)) {
1230 dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n");
1231 return PTR_ERR(spdif_priv->rxclk);
1232 }
1233 spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC;
1234
1235 for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
1236 ret = fsl_spdif_probe_txclk(spdif_priv, i);
1237 if (ret)
1238 return ret;
1239 }
1240
1241 /* Initial spinlock for control data */
1242 ctrl = &spdif_priv->fsl_spdif_control;
1243 spin_lock_init(&ctrl->ctl_lock);
1244
1245 /* Init tx channel status default value */
1246 ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT |
1247 IEC958_AES0_CON_EMPHASIS_5015;
1248 ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID;
1249 ctrl->ch_status[2] = 0x00;
1250 ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 |
1251 IEC958_AES3_CON_CLOCK_1000PPM;
1252
1253 spdif_priv->dpll_locked = false;
1254
1255 spdif_priv->dma_params_tx.maxburst = FSL_SPDIF_TXFIFO_WML;
1256 spdif_priv->dma_params_rx.maxburst = FSL_SPDIF_RXFIFO_WML;
1257 spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL;
1258 spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL;
1259
1260 /* Register with ASoC */
1261 dev_set_drvdata(&pdev->dev, spdif_priv);
1262
1263 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component,
1264 &spdif_priv->cpu_dai_drv, 1);
1265 if (ret) {
1266 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1267 return ret;
1268 }
1269
1270 ret = imx_pcm_dma_init(pdev);
1271 if (ret)
1272 dev_err(&pdev->dev, "imx_pcm_dma_init failed: %d\n", ret);
1273
1274 return ret;
1275 }
1276
1277 static const struct of_device_id fsl_spdif_dt_ids[] = {
1278 { .compatible = "fsl,imx35-spdif", },
1279 { .compatible = "fsl,vf610-spdif", },
1280 {}
1281 };
1282 MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids);
1283
1284 static struct platform_driver fsl_spdif_driver = {
1285 .driver = {
1286 .name = "fsl-spdif-dai",
1287 .owner = THIS_MODULE,
1288 .of_match_table = fsl_spdif_dt_ids,
1289 },
1290 .probe = fsl_spdif_probe,
1291 };
1292
1293 module_platform_driver(fsl_spdif_driver);
1294
1295 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1296 MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver");
1297 MODULE_LICENSE("GPL v2");
1298 MODULE_ALIAS("platform:fsl-spdif-dai");
Linux kernel - Deliverables
This page took 0.089742 seconds and 5 git commands to generate.